at91dci.c revision 184610
1#include <sys/cdefs.h> 2__FBSDID("$FreeBSD: head/sys/dev/usb2/controller/at91dci.c 184610 2008-11-04 02:31:03Z alfred $"); 3 4/*- 5 * Copyright (c) 2007-2008 Hans Petter Selasky. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * This file contains the driver for the AT91 series USB Device 31 * Controller 32 */ 33 34/* 35 * Thanks to "David Brownell" for helping out regarding the hardware 36 * endpoint profiles. 37 */ 38 39/* 40 * NOTE: The "fifo_bank" is not reset in hardware when the endpoint is 41 * reset ! 42 * 43 * NOTE: When the chip detects BUS-reset it will also reset the 44 * endpoints, Function-address and more. 45 */ 46 47#include <dev/usb2/include/usb2_standard.h> 48#include <dev/usb2/include/usb2_mfunc.h> 49#include <dev/usb2/include/usb2_error.h> 50#include <dev/usb2/include/usb2_defs.h> 51 52#define USB_DEBUG_VAR at91dcidebug 53#define usb2_config_td_cc at91dci_config_copy 54#define usb2_config_td_softc at91dci_softc 55 56#include <dev/usb2/core/usb2_core.h> 57#include <dev/usb2/core/usb2_debug.h> 58#include <dev/usb2/core/usb2_busdma.h> 59#include <dev/usb2/core/usb2_process.h> 60#include <dev/usb2/core/usb2_config_td.h> 61#include <dev/usb2/core/usb2_sw_transfer.h> 62#include <dev/usb2/core/usb2_transfer.h> 63#include <dev/usb2/core/usb2_device.h> 64#include <dev/usb2/core/usb2_hub.h> 65#include <dev/usb2/core/usb2_util.h> 66 67#include <dev/usb2/controller/usb2_controller.h> 68#include <dev/usb2/controller/usb2_bus.h> 69#include <dev/usb2/controller/at91dci.h> 70 71#define AT9100_DCI_BUS2SC(bus) \ 72 ((struct at91dci_softc *)(((uint8_t *)(bus)) - \ 73 USB_P2U(&(((struct at91dci_softc *)0)->sc_bus)))) 74 75#define AT9100_DCI_PC2SC(pc) \ 76 AT9100_DCI_BUS2SC((pc)->tag_parent->info->bus) 77 78#if USB_DEBUG 79static int at91dcidebug = 0; 80 81SYSCTL_NODE(_hw_usb2, OID_AUTO, at91dci, CTLFLAG_RW, 0, "USB at91dci"); 82SYSCTL_INT(_hw_usb2_at91dci, OID_AUTO, debug, CTLFLAG_RW, 83 &at91dcidebug, 0, "at91dci debug level"); 84#endif 85 86#define AT9100_DCI_INTR_ENDPT 1 87 88/* prototypes */ 89 90struct usb2_bus_methods at91dci_bus_methods; 91struct usb2_pipe_methods at91dci_device_bulk_methods; 92struct usb2_pipe_methods at91dci_device_ctrl_methods; 93struct usb2_pipe_methods at91dci_device_intr_methods; 94struct usb2_pipe_methods at91dci_device_isoc_fs_methods; 95struct usb2_pipe_methods at91dci_root_ctrl_methods; 96struct usb2_pipe_methods at91dci_root_intr_methods; 97 98static at91dci_cmd_t at91dci_setup_rx; 99static at91dci_cmd_t at91dci_data_rx; 100static at91dci_cmd_t at91dci_data_tx; 101static at91dci_cmd_t at91dci_data_tx_sync; 102static void at91dci_device_done(struct usb2_xfer *xfer, usb2_error_t error); 103static void at91dci_do_poll(struct usb2_bus *bus); 104static void at91dci_root_ctrl_poll(struct at91dci_softc *sc); 105static void at91dci_standard_done(struct usb2_xfer *xfer); 106 107static usb2_sw_transfer_func_t at91dci_root_intr_done; 108static usb2_sw_transfer_func_t at91dci_root_ctrl_done; 109static usb2_config_td_command_t at91dci_root_ctrl_task; 110 111/* 112 * NOTE: Some of the bits in the CSR register have inverse meaning so 113 * we need a helper macro when acknowledging events: 114 */ 115#define AT91_CSR_ACK(csr, what) do { \ 116 (csr) &= ~((AT91_UDP_CSR_FORCESTALL| \ 117 AT91_UDP_CSR_TXPKTRDY| \ 118 AT91_UDP_CSR_RXBYTECNT) ^ (what));\ 119 (csr) |= ((AT91_UDP_CSR_RX_DATA_BK0| \ 120 AT91_UDP_CSR_RX_DATA_BK1| \ 121 AT91_UDP_CSR_TXCOMP| \ 122 AT91_UDP_CSR_RXSETUP| \ 123 AT91_UDP_CSR_STALLSENT) ^ (what)); \ 124} while (0) 125 126/* 127 * Here is a list of what the chip supports. 128 * Probably it supports more than listed here! 129 */ 130static const struct usb2_hw_ep_profile 131 at91dci_ep_profile[AT91_UDP_EP_MAX] = { 132 133 [0] = { 134 .max_in_frame_size = 8, 135 .max_out_frame_size = 8, 136 .is_simplex = 1, 137 .support_control = 1, 138 }, 139 [1] = { 140 .max_in_frame_size = 64, 141 .max_out_frame_size = 64, 142 .is_simplex = 1, 143 .support_multi_buffer = 1, 144 .support_bulk = 1, 145 .support_interrupt = 1, 146 .support_isochronous = 1, 147 .support_in = 1, 148 .support_out = 1, 149 }, 150 [2] = { 151 .max_in_frame_size = 64, 152 .max_out_frame_size = 64, 153 .is_simplex = 1, 154 .support_multi_buffer = 1, 155 .support_bulk = 1, 156 .support_interrupt = 1, 157 .support_isochronous = 1, 158 .support_in = 1, 159 .support_out = 1, 160 }, 161 [3] = { 162 /* can also do BULK */ 163 .max_in_frame_size = 8, 164 .max_out_frame_size = 8, 165 .is_simplex = 1, 166 .support_interrupt = 1, 167 .support_in = 1, 168 .support_out = 1, 169 }, 170 [4] = { 171 .max_in_frame_size = 256, 172 .max_out_frame_size = 256, 173 .is_simplex = 1, 174 .support_multi_buffer = 1, 175 .support_bulk = 1, 176 .support_interrupt = 1, 177 .support_isochronous = 1, 178 .support_in = 1, 179 .support_out = 1, 180 }, 181 [5] = { 182 .max_in_frame_size = 256, 183 .max_out_frame_size = 256, 184 .is_simplex = 1, 185 .support_multi_buffer = 1, 186 .support_bulk = 1, 187 .support_interrupt = 1, 188 .support_isochronous = 1, 189 .support_in = 1, 190 .support_out = 1, 191 }, 192}; 193 194static void 195at91dci_get_hw_ep_profile(struct usb2_device *udev, 196 const struct usb2_hw_ep_profile **ppf, uint8_t ep_addr) 197{ 198 if (ep_addr < AT91_UDP_EP_MAX) { 199 *ppf = (at91dci_ep_profile + ep_addr); 200 } else { 201 *ppf = NULL; 202 } 203 return; 204} 205 206static void 207at91dci_clocks_on(struct at91dci_softc *sc) 208{ 209 if (sc->sc_flags.clocks_off && 210 sc->sc_flags.port_powered) { 211 212 DPRINTFN(5, "\n"); 213 214 if (sc->sc_clocks_on) { 215 (sc->sc_clocks_on) (sc->sc_clocks_arg); 216 } 217 sc->sc_flags.clocks_off = 0; 218 219 /* enable Transceiver */ 220 AT91_UDP_WRITE_4(sc, AT91_UDP_TXVC, 0); 221 } 222 return; 223} 224 225static void 226at91dci_clocks_off(struct at91dci_softc *sc) 227{ 228 if (!sc->sc_flags.clocks_off) { 229 230 DPRINTFN(5, "\n"); 231 232 /* disable Transceiver */ 233 AT91_UDP_WRITE_4(sc, AT91_UDP_TXVC, AT91_UDP_TXVC_DIS); 234 235 if (sc->sc_clocks_off) { 236 (sc->sc_clocks_off) (sc->sc_clocks_arg); 237 } 238 sc->sc_flags.clocks_off = 1; 239 } 240 return; 241} 242 243static void 244at91dci_pull_up(struct at91dci_softc *sc) 245{ 246 /* pullup D+, if possible */ 247 248 if (!sc->sc_flags.d_pulled_up && 249 sc->sc_flags.port_powered) { 250 sc->sc_flags.d_pulled_up = 1; 251 (sc->sc_pull_up) (sc->sc_pull_arg); 252 } 253 return; 254} 255 256static void 257at91dci_pull_down(struct at91dci_softc *sc) 258{ 259 /* pulldown D+, if possible */ 260 261 if (sc->sc_flags.d_pulled_up) { 262 sc->sc_flags.d_pulled_up = 0; 263 (sc->sc_pull_down) (sc->sc_pull_arg); 264 } 265 return; 266} 267 268static void 269at91dci_wakeup_peer(struct at91dci_softc *sc) 270{ 271 uint32_t temp; 272 273 if (!(sc->sc_flags.status_suspend)) { 274 return; 275 } 276 temp = AT91_UDP_READ_4(sc, AT91_UDP_GSTATE); 277 278 if (!(temp & AT91_UDP_GSTATE_ESR)) { 279 return; 280 } 281 AT91_UDP_WRITE_4(sc, AT91_UDP_GSTATE, temp); 282 283 return; 284} 285 286static void 287at91dci_rem_wakeup_set(struct usb2_device *udev, uint8_t is_on) 288{ 289 struct at91dci_softc *sc; 290 uint32_t temp; 291 292 DPRINTFN(5, "is_on=%u\n", is_on); 293 294 mtx_assert(&udev->bus->mtx, MA_OWNED); 295 296 sc = AT9100_DCI_BUS2SC(udev->bus); 297 298 temp = AT91_UDP_READ_4(sc, AT91_UDP_GSTATE); 299 300 if (is_on) { 301 temp |= AT91_UDP_GSTATE_ESR; 302 } else { 303 temp &= ~AT91_UDP_GSTATE_ESR; 304 } 305 306 AT91_UDP_WRITE_4(sc, AT91_UDP_GSTATE, temp); 307 308 return; 309} 310 311static void 312at91dci_set_address(struct at91dci_softc *sc, uint8_t addr) 313{ 314 DPRINTFN(5, "addr=%d\n", addr); 315 316 AT91_UDP_WRITE_4(sc, AT91_UDP_FADDR, addr | 317 AT91_UDP_FADDR_EN); 318 319 return; 320} 321 322static uint8_t 323at91dci_setup_rx(struct at91dci_td *td) 324{ 325 struct at91dci_softc *sc; 326 struct usb2_device_request req; 327 uint32_t csr; 328 uint32_t temp; 329 uint16_t count; 330 331 /* read out FIFO status */ 332 csr = bus_space_read_4(td->io_tag, td->io_hdl, 333 td->status_reg); 334 335 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder); 336 337 temp = csr; 338 temp &= (AT91_UDP_CSR_RX_DATA_BK0 | 339 AT91_UDP_CSR_RX_DATA_BK1 | 340 AT91_UDP_CSR_STALLSENT | 341 AT91_UDP_CSR_RXSETUP | 342 AT91_UDP_CSR_TXCOMP); 343 344 if (!(csr & AT91_UDP_CSR_RXSETUP)) { 345 /* abort any ongoing transfer */ 346 if (!td->did_stall) { 347 DPRINTFN(5, "stalling\n"); 348 temp |= AT91_UDP_CSR_FORCESTALL; 349 td->did_stall = 1; 350 } 351 goto not_complete; 352 } 353 /* get the packet byte count */ 354 count = (csr & AT91_UDP_CSR_RXBYTECNT) >> 16; 355 356 /* verify data length */ 357 if (count != td->remainder) { 358 DPRINTFN(0, "Invalid SETUP packet " 359 "length, %d bytes\n", count); 360 goto not_complete; 361 } 362 if (count != sizeof(req)) { 363 DPRINTFN(0, "Unsupported SETUP packet " 364 "length, %d bytes\n", count); 365 goto not_complete; 366 } 367 /* receive data */ 368 bus_space_read_multi_1(td->io_tag, td->io_hdl, 369 td->fifo_reg, (void *)&req, sizeof(req)); 370 371 /* copy data into real buffer */ 372 usb2_copy_in(td->pc, 0, &req, sizeof(req)); 373 374 td->offset = sizeof(req); 375 td->remainder = 0; 376 377 /* get pointer to softc */ 378 sc = AT9100_DCI_PC2SC(td->pc); 379 380 /* sneak peek the set address */ 381 if ((req.bmRequestType == UT_WRITE_DEVICE) && 382 (req.bRequest == UR_SET_ADDRESS)) { 383 sc->sc_dv_addr = req.wValue[0] & 0x7F; 384 } else { 385 sc->sc_dv_addr = 0xFF; 386 } 387 388 /* sneak peek the endpoint direction */ 389 if (req.bmRequestType & UE_DIR_IN) { 390 csr |= AT91_UDP_CSR_DIR; 391 } else { 392 csr &= ~AT91_UDP_CSR_DIR; 393 } 394 395 /* write the direction of the control transfer */ 396 AT91_CSR_ACK(csr, temp); 397 bus_space_write_4(td->io_tag, td->io_hdl, 398 td->status_reg, csr); 399 return (0); /* complete */ 400 401not_complete: 402 /* clear interrupts, if any */ 403 if (temp) { 404 DPRINTFN(5, "clearing 0x%08x\n", temp); 405 AT91_CSR_ACK(csr, temp); 406 bus_space_write_4(td->io_tag, td->io_hdl, 407 td->status_reg, csr); 408 } 409 return (1); /* not complete */ 410 411} 412 413static uint8_t 414at91dci_data_rx(struct at91dci_td *td) 415{ 416 struct usb2_page_search buf_res; 417 uint32_t csr; 418 uint32_t temp; 419 uint16_t count; 420 uint8_t to; 421 uint8_t got_short; 422 423 to = 2; /* don't loop forever! */ 424 got_short = 0; 425 426 /* check if any of the FIFO banks have data */ 427repeat: 428 /* read out FIFO status */ 429 csr = bus_space_read_4(td->io_tag, td->io_hdl, 430 td->status_reg); 431 432 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder); 433 434 if (csr & AT91_UDP_CSR_RXSETUP) { 435 if (td->remainder == 0) { 436 /* 437 * We are actually complete and have 438 * received the next SETUP 439 */ 440 DPRINTFN(5, "faking complete\n"); 441 return (0); /* complete */ 442 } 443 /* 444 * USB Host Aborted the transfer. 445 */ 446 td->error = 1; 447 return (0); /* complete */ 448 } 449 /* Make sure that "STALLSENT" gets cleared */ 450 temp = csr; 451 temp &= AT91_UDP_CSR_STALLSENT; 452 453 /* check status */ 454 if (!(csr & (AT91_UDP_CSR_RX_DATA_BK0 | 455 AT91_UDP_CSR_RX_DATA_BK1))) { 456 if (temp) { 457 /* write command */ 458 AT91_CSR_ACK(csr, temp); 459 bus_space_write_4(td->io_tag, td->io_hdl, 460 td->status_reg, csr); 461 } 462 return (1); /* not complete */ 463 } 464 /* get the packet byte count */ 465 count = (csr & AT91_UDP_CSR_RXBYTECNT) >> 16; 466 467 /* verify the packet byte count */ 468 if (count != td->max_packet_size) { 469 if (count < td->max_packet_size) { 470 /* we have a short packet */ 471 td->short_pkt = 1; 472 got_short = 1; 473 } else { 474 /* invalid USB packet */ 475 td->error = 1; 476 return (0); /* we are complete */ 477 } 478 } 479 /* verify the packet byte count */ 480 if (count > td->remainder) { 481 /* invalid USB packet */ 482 td->error = 1; 483 return (0); /* we are complete */ 484 } 485 while (count > 0) { 486 usb2_get_page(td->pc, td->offset, &buf_res); 487 488 /* get correct length */ 489 if (buf_res.length > count) { 490 buf_res.length = count; 491 } 492 /* receive data */ 493 bus_space_read_multi_1(td->io_tag, td->io_hdl, 494 td->fifo_reg, buf_res.buffer, buf_res.length); 495 496 /* update counters */ 497 count -= buf_res.length; 498 td->offset += buf_res.length; 499 td->remainder -= buf_res.length; 500 } 501 502 /* clear status bits */ 503 if (td->support_multi_buffer) { 504 if (td->fifo_bank) { 505 td->fifo_bank = 0; 506 temp |= AT91_UDP_CSR_RX_DATA_BK1; 507 } else { 508 td->fifo_bank = 1; 509 temp |= AT91_UDP_CSR_RX_DATA_BK0; 510 } 511 } else { 512 temp |= (AT91_UDP_CSR_RX_DATA_BK0 | 513 AT91_UDP_CSR_RX_DATA_BK1); 514 } 515 516 /* write command */ 517 AT91_CSR_ACK(csr, temp); 518 bus_space_write_4(td->io_tag, td->io_hdl, 519 td->status_reg, csr); 520 521 /* 522 * NOTE: We may have to delay a little bit before 523 * proceeding after clearing the DATA_BK bits. 524 */ 525 526 /* check if we are complete */ 527 if ((td->remainder == 0) || got_short) { 528 if (td->short_pkt) { 529 /* we are complete */ 530 return (0); 531 } 532 /* else need to receive a zero length packet */ 533 } 534 if (--to) { 535 goto repeat; 536 } 537 return (1); /* not complete */ 538} 539 540static uint8_t 541at91dci_data_tx(struct at91dci_td *td) 542{ 543 struct usb2_page_search buf_res; 544 uint32_t csr; 545 uint32_t temp; 546 uint16_t count; 547 uint8_t to; 548 549 to = 2; /* don't loop forever! */ 550 551repeat: 552 553 /* read out FIFO status */ 554 csr = bus_space_read_4(td->io_tag, td->io_hdl, 555 td->status_reg); 556 557 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder); 558 559 if (csr & AT91_UDP_CSR_RXSETUP) { 560 /* 561 * The current transfer was aborted 562 * by the USB Host 563 */ 564 td->error = 1; 565 return (0); /* complete */ 566 } 567 /* Make sure that "STALLSENT" gets cleared */ 568 temp = csr; 569 temp &= AT91_UDP_CSR_STALLSENT; 570 571 if (csr & AT91_UDP_CSR_TXPKTRDY) { 572 if (temp) { 573 /* write command */ 574 AT91_CSR_ACK(csr, temp); 575 bus_space_write_4(td->io_tag, td->io_hdl, 576 td->status_reg, csr); 577 } 578 return (1); /* not complete */ 579 } else { 580 /* clear TXCOMP and set TXPKTRDY */ 581 temp |= (AT91_UDP_CSR_TXCOMP | 582 AT91_UDP_CSR_TXPKTRDY); 583 } 584 585 count = td->max_packet_size; 586 if (td->remainder < count) { 587 /* we have a short packet */ 588 td->short_pkt = 1; 589 count = td->remainder; 590 } 591 while (count > 0) { 592 593 usb2_get_page(td->pc, td->offset, &buf_res); 594 595 /* get correct length */ 596 if (buf_res.length > count) { 597 buf_res.length = count; 598 } 599 /* transmit data */ 600 bus_space_write_multi_1(td->io_tag, td->io_hdl, 601 td->fifo_reg, buf_res.buffer, buf_res.length); 602 603 /* update counters */ 604 count -= buf_res.length; 605 td->offset += buf_res.length; 606 td->remainder -= buf_res.length; 607 } 608 609 /* write command */ 610 AT91_CSR_ACK(csr, temp); 611 bus_space_write_4(td->io_tag, td->io_hdl, 612 td->status_reg, csr); 613 614 /* check remainder */ 615 if (td->remainder == 0) { 616 if (td->short_pkt) { 617 return (0); /* complete */ 618 } 619 /* else we need to transmit a short packet */ 620 } 621 if (--to) { 622 goto repeat; 623 } 624 return (1); /* not complete */ 625} 626 627static uint8_t 628at91dci_data_tx_sync(struct at91dci_td *td) 629{ 630 struct at91dci_softc *sc; 631 uint32_t csr; 632 uint32_t temp; 633 634#if 0 635repeat: 636#endif 637 638 /* read out FIFO status */ 639 csr = bus_space_read_4(td->io_tag, td->io_hdl, 640 td->status_reg); 641 642 DPRINTFN(5, "csr=0x%08x\n", csr); 643 644 if (csr & AT91_UDP_CSR_RXSETUP) { 645 DPRINTFN(5, "faking complete\n"); 646 /* Race condition */ 647 return (0); /* complete */ 648 } 649 temp = csr; 650 temp &= (AT91_UDP_CSR_STALLSENT | 651 AT91_UDP_CSR_TXCOMP); 652 653 /* check status */ 654 if (csr & AT91_UDP_CSR_TXPKTRDY) { 655 goto not_complete; 656 } 657 if (!(csr & AT91_UDP_CSR_TXCOMP)) { 658 goto not_complete; 659 } 660 sc = AT9100_DCI_PC2SC(td->pc); 661 if (sc->sc_dv_addr != 0xFF) { 662 /* 663 * The AT91 has a special requirement with regard to 664 * setting the address and that is to write the new 665 * address before clearing TXCOMP: 666 */ 667 at91dci_set_address(sc, sc->sc_dv_addr); 668 } 669 /* write command */ 670 AT91_CSR_ACK(csr, temp); 671 bus_space_write_4(td->io_tag, td->io_hdl, 672 td->status_reg, csr); 673 674 return (0); /* complete */ 675 676not_complete: 677 if (temp) { 678 /* write command */ 679 AT91_CSR_ACK(csr, temp); 680 bus_space_write_4(td->io_tag, td->io_hdl, 681 td->status_reg, csr); 682 } 683 return (1); /* not complete */ 684} 685 686static uint8_t 687at91dci_xfer_do_fifo(struct usb2_xfer *xfer) 688{ 689 struct at91dci_softc *sc; 690 struct at91dci_td *td; 691 uint8_t temp; 692 693 DPRINTFN(9, "\n"); 694 695 td = xfer->td_transfer_cache; 696 while (1) { 697 if ((td->func) (td)) { 698 /* operation in progress */ 699 break; 700 } 701 if (((void *)td) == xfer->td_transfer_last) { 702 goto done; 703 } 704 if (td->error) { 705 goto done; 706 } else if (td->remainder > 0) { 707 /* 708 * We had a short transfer. If there is no alternate 709 * next, stop processing ! 710 */ 711 if (!td->alt_next) { 712 goto done; 713 } 714 } 715 /* 716 * Fetch the next transfer descriptor and transfer 717 * some flags to the next transfer descriptor 718 */ 719 temp = 0; 720 if (td->fifo_bank) 721 temp |= 1; 722 td = td->obj_next; 723 xfer->td_transfer_cache = td; 724 if (temp & 1) 725 td->fifo_bank = 1; 726 } 727 return (1); /* not complete */ 728 729done: 730 sc = xfer->usb2_sc; 731 temp = (xfer->endpoint & UE_ADDR); 732 733 /* update FIFO bank flag and multi buffer */ 734 if (td->fifo_bank) { 735 sc->sc_ep_flags[temp].fifo_bank = 1; 736 } else { 737 sc->sc_ep_flags[temp].fifo_bank = 0; 738 } 739 740 /* compute all actual lengths */ 741 742 at91dci_standard_done(xfer); 743 744 return (0); /* complete */ 745} 746 747static void 748at91dci_interrupt_poll(struct at91dci_softc *sc) 749{ 750 struct usb2_xfer *xfer; 751 752repeat: 753 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 754 if (!at91dci_xfer_do_fifo(xfer)) { 755 /* queue has been modified */ 756 goto repeat; 757 } 758 } 759 return; 760} 761 762static void 763at91dci_vbus_interrupt(struct usb2_bus *bus, uint8_t is_on) 764{ 765 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(bus); 766 767 DPRINTFN(5, "vbus = %u\n", is_on); 768 769 mtx_lock(&sc->sc_bus.mtx); 770 if (is_on) { 771 if (!sc->sc_flags.status_vbus) { 772 sc->sc_flags.status_vbus = 1; 773 774 /* complete root HUB interrupt endpoint */ 775 776 usb2_sw_transfer(&sc->sc_root_intr, 777 &at91dci_root_intr_done); 778 } 779 } else { 780 if (sc->sc_flags.status_vbus) { 781 sc->sc_flags.status_vbus = 0; 782 sc->sc_flags.status_bus_reset = 0; 783 sc->sc_flags.status_suspend = 0; 784 sc->sc_flags.change_suspend = 0; 785 sc->sc_flags.change_connect = 1; 786 787 /* complete root HUB interrupt endpoint */ 788 789 usb2_sw_transfer(&sc->sc_root_intr, 790 &at91dci_root_intr_done); 791 } 792 } 793 794 mtx_unlock(&sc->sc_bus.mtx); 795 796 return; 797} 798 799void 800at91dci_interrupt(struct at91dci_softc *sc) 801{ 802 uint32_t status; 803 804 mtx_lock(&sc->sc_bus.mtx); 805 806 status = AT91_UDP_READ_4(sc, AT91_UDP_ISR); 807 status &= AT91_UDP_INT_DEFAULT; 808 809 if (!status) { 810 mtx_unlock(&sc->sc_bus.mtx); 811 return; 812 } 813 /* acknowledge interrupts */ 814 815 AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, status); 816 817 /* check for any bus state change interrupts */ 818 819 if (status & AT91_UDP_INT_BUS) { 820 821 DPRINTFN(5, "real bus interrupt 0x%08x\n", status); 822 823 if (status & AT91_UDP_INT_END_BR) { 824 825 /* set correct state */ 826 sc->sc_flags.status_bus_reset = 1; 827 sc->sc_flags.status_suspend = 0; 828 sc->sc_flags.change_suspend = 0; 829 sc->sc_flags.change_connect = 1; 830 831 /* disable resume interrupt */ 832 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 833 AT91_UDP_INT_RXRSM); 834 /* enable suspend interrupt */ 835 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, 836 AT91_UDP_INT_RXSUSP); 837 } 838 /* 839 * If RXRSM and RXSUSP is set at the same time we interpret 840 * that like RESUME. Resume is set when there is at least 3 841 * milliseconds of inactivity on the USB BUS. 842 */ 843 if (status & AT91_UDP_INT_RXRSM) { 844 if (sc->sc_flags.status_suspend) { 845 sc->sc_flags.status_suspend = 0; 846 sc->sc_flags.change_suspend = 1; 847 848 /* disable resume interrupt */ 849 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 850 AT91_UDP_INT_RXRSM); 851 /* enable suspend interrupt */ 852 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, 853 AT91_UDP_INT_RXSUSP); 854 } 855 } else if (status & AT91_UDP_INT_RXSUSP) { 856 if (!sc->sc_flags.status_suspend) { 857 sc->sc_flags.status_suspend = 1; 858 sc->sc_flags.change_suspend = 1; 859 860 /* disable suspend interrupt */ 861 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 862 AT91_UDP_INT_RXSUSP); 863 864 /* enable resume interrupt */ 865 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, 866 AT91_UDP_INT_RXRSM); 867 } 868 } 869 /* complete root HUB interrupt endpoint */ 870 871 usb2_sw_transfer(&sc->sc_root_intr, 872 &at91dci_root_intr_done); 873 } 874 /* check for any endpoint interrupts */ 875 876 if (status & AT91_UDP_INT_EPS) { 877 878 DPRINTFN(5, "real endpoint interrupt 0x%08x\n", status); 879 880 at91dci_interrupt_poll(sc); 881 } 882 mtx_unlock(&sc->sc_bus.mtx); 883 884 return; 885} 886 887static void 888at91dci_setup_standard_chain_sub(struct at91dci_std_temp *temp) 889{ 890 struct at91dci_td *td; 891 892 /* get current Transfer Descriptor */ 893 td = temp->td_next; 894 temp->td = td; 895 896 /* prepare for next TD */ 897 temp->td_next = td->obj_next; 898 899 /* fill out the Transfer Descriptor */ 900 td->func = temp->func; 901 td->pc = temp->pc; 902 td->offset = temp->offset; 903 td->remainder = temp->len; 904 td->fifo_bank = 0; 905 td->error = 0; 906 td->did_stall = 0; 907 td->short_pkt = temp->short_pkt; 908 td->alt_next = temp->setup_alt_next; 909 return; 910} 911 912static void 913at91dci_setup_standard_chain(struct usb2_xfer *xfer) 914{ 915 struct at91dci_std_temp temp; 916 struct at91dci_softc *sc; 917 struct at91dci_td *td; 918 uint32_t x; 919 uint8_t ep_no; 920 uint8_t need_sync; 921 922 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 923 xfer->address, UE_GET_ADDR(xfer->endpoint), 924 xfer->sumlen, usb2_get_speed(xfer->udev)); 925 926 temp.max_frame_size = xfer->max_frame_size; 927 928 td = xfer->td_start[0]; 929 xfer->td_transfer_first = td; 930 xfer->td_transfer_cache = td; 931 932 /* setup temp */ 933 934 temp.td = NULL; 935 temp.td_next = xfer->td_start[0]; 936 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 937 temp.offset = 0; 938 939 sc = xfer->usb2_sc; 940 ep_no = (xfer->endpoint & UE_ADDR); 941 942 /* check if we should prepend a setup message */ 943 944 if (xfer->flags_int.control_xfr) { 945 if (xfer->flags_int.control_hdr) { 946 947 temp.func = &at91dci_setup_rx; 948 temp.len = xfer->frlengths[0]; 949 temp.pc = xfer->frbuffers + 0; 950 temp.short_pkt = temp.len ? 1 : 0; 951 952 at91dci_setup_standard_chain_sub(&temp); 953 } 954 x = 1; 955 } else { 956 x = 0; 957 } 958 959 if (x != xfer->nframes) { 960 if (xfer->endpoint & UE_DIR_IN) { 961 temp.func = &at91dci_data_tx; 962 need_sync = 1; 963 } else { 964 temp.func = &at91dci_data_rx; 965 need_sync = 0; 966 } 967 968 /* setup "pc" pointer */ 969 temp.pc = xfer->frbuffers + x; 970 } else { 971 need_sync = 0; 972 } 973 while (x != xfer->nframes) { 974 975 /* DATA0 / DATA1 message */ 976 977 temp.len = xfer->frlengths[x]; 978 979 x++; 980 981 if (x == xfer->nframes) { 982 temp.setup_alt_next = 0; 983 } 984 if (temp.len == 0) { 985 986 /* make sure that we send an USB packet */ 987 988 temp.short_pkt = 0; 989 990 } else { 991 992 /* regular data transfer */ 993 994 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 995 } 996 997 at91dci_setup_standard_chain_sub(&temp); 998 999 if (xfer->flags_int.isochronous_xfr) { 1000 temp.offset += temp.len; 1001 } else { 1002 /* get next Page Cache pointer */ 1003 temp.pc = xfer->frbuffers + x; 1004 } 1005 } 1006 1007 /* always setup a valid "pc" pointer for status and sync */ 1008 temp.pc = xfer->frbuffers + 0; 1009 1010 /* check if we need to sync */ 1011 if (need_sync && xfer->flags_int.control_xfr) { 1012 1013 /* we need a SYNC point after TX */ 1014 temp.func = &at91dci_data_tx_sync; 1015 temp.len = 0; 1016 temp.short_pkt = 0; 1017 1018 at91dci_setup_standard_chain_sub(&temp); 1019 } 1020 /* check if we should append a status stage */ 1021 if (xfer->flags_int.control_xfr && 1022 !xfer->flags_int.control_act) { 1023 1024 /* 1025 * Send a DATA1 message and invert the current 1026 * endpoint direction. 1027 */ 1028 if (xfer->endpoint & UE_DIR_IN) { 1029 temp.func = &at91dci_data_rx; 1030 need_sync = 0; 1031 } else { 1032 temp.func = &at91dci_data_tx; 1033 need_sync = 1; 1034 } 1035 temp.len = 0; 1036 temp.short_pkt = 0; 1037 1038 at91dci_setup_standard_chain_sub(&temp); 1039 if (need_sync) { 1040 /* we need a SYNC point after TX */ 1041 temp.func = &at91dci_data_tx_sync; 1042 temp.len = 0; 1043 temp.short_pkt = 0; 1044 1045 at91dci_setup_standard_chain_sub(&temp); 1046 } 1047 } 1048 /* must have at least one frame! */ 1049 td = temp.td; 1050 xfer->td_transfer_last = td; 1051 1052 /* setup the correct fifo bank */ 1053 if (sc->sc_ep_flags[ep_no].fifo_bank) { 1054 td = xfer->td_transfer_first; 1055 td->fifo_bank = 1; 1056 } 1057 return; 1058} 1059 1060static void 1061at91dci_timeout(void *arg) 1062{ 1063 struct usb2_xfer *xfer = arg; 1064 struct at91dci_softc *sc = xfer->usb2_sc; 1065 1066 DPRINTF("xfer=%p\n", xfer); 1067 1068 mtx_assert(&sc->sc_bus.mtx, MA_OWNED); 1069 1070 /* transfer is transferred */ 1071 at91dci_device_done(xfer, USB_ERR_TIMEOUT); 1072 1073 mtx_unlock(&sc->sc_bus.mtx); 1074 1075 return; 1076} 1077 1078static void 1079at91dci_start_standard_chain(struct usb2_xfer *xfer) 1080{ 1081 DPRINTFN(9, "\n"); 1082 1083 /* poll one time */ 1084 if (at91dci_xfer_do_fifo(xfer)) { 1085 1086 struct at91dci_softc *sc = xfer->usb2_sc; 1087 uint8_t ep_no = xfer->endpoint & UE_ADDR; 1088 1089 /* 1090 * Only enable the endpoint interrupt when we are actually 1091 * waiting for data, hence we are dealing with level 1092 * triggered interrupts ! 1093 */ 1094 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, AT91_UDP_INT_EP(ep_no)); 1095 1096 DPRINTFN(15, "enable interrupts on endpoint %d\n", ep_no); 1097 1098 /* put transfer on interrupt queue */ 1099 usb2_transfer_enqueue(&xfer->udev->bus->intr_q, xfer); 1100 1101 /* start timeout, if any */ 1102 if (xfer->timeout != 0) { 1103 usb2_transfer_timeout_ms(xfer, 1104 &at91dci_timeout, xfer->timeout); 1105 } 1106 } 1107 return; 1108} 1109 1110static void 1111at91dci_root_intr_done(struct usb2_xfer *xfer, 1112 struct usb2_sw_transfer *std) 1113{ 1114 struct at91dci_softc *sc = xfer->usb2_sc; 1115 1116 DPRINTFN(9, "\n"); 1117 1118 mtx_assert(&sc->sc_bus.mtx, MA_OWNED); 1119 1120 if (std->state != USB_SW_TR_PRE_DATA) { 1121 if (std->state == USB_SW_TR_PRE_CALLBACK) { 1122 /* transfer transferred */ 1123 at91dci_device_done(xfer, std->err); 1124 } 1125 goto done; 1126 } 1127 /* setup buffer */ 1128 std->ptr = sc->sc_hub_idata; 1129 std->len = sizeof(sc->sc_hub_idata); 1130 1131 /* set port bit */ 1132 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 1133 1134done: 1135 return; 1136} 1137 1138static usb2_error_t 1139at91dci_standard_done_sub(struct usb2_xfer *xfer) 1140{ 1141 struct at91dci_td *td; 1142 uint32_t len; 1143 uint8_t error; 1144 1145 DPRINTFN(9, "\n"); 1146 1147 td = xfer->td_transfer_cache; 1148 1149 do { 1150 len = td->remainder; 1151 1152 if (xfer->aframes != xfer->nframes) { 1153 /* 1154 * Verify the length and subtract 1155 * the remainder from "frlengths[]": 1156 */ 1157 if (len > xfer->frlengths[xfer->aframes]) { 1158 td->error = 1; 1159 } else { 1160 xfer->frlengths[xfer->aframes] -= len; 1161 } 1162 } 1163 /* Check for transfer error */ 1164 if (td->error) { 1165 /* the transfer is finished */ 1166 error = 1; 1167 td = NULL; 1168 break; 1169 } 1170 /* Check for short transfer */ 1171 if (len > 0) { 1172 if (xfer->flags_int.short_frames_ok) { 1173 /* follow alt next */ 1174 if (td->alt_next) { 1175 td = td->obj_next; 1176 } else { 1177 td = NULL; 1178 } 1179 } else { 1180 /* the transfer is finished */ 1181 td = NULL; 1182 } 1183 error = 0; 1184 break; 1185 } 1186 td = td->obj_next; 1187 1188 /* this USB frame is complete */ 1189 error = 0; 1190 break; 1191 1192 } while (0); 1193 1194 /* update transfer cache */ 1195 1196 xfer->td_transfer_cache = td; 1197 1198 return (error ? 1199 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1200} 1201 1202static void 1203at91dci_standard_done(struct usb2_xfer *xfer) 1204{ 1205 usb2_error_t err = 0; 1206 1207 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 1208 xfer, xfer->pipe); 1209 1210 /* reset scanner */ 1211 1212 xfer->td_transfer_cache = xfer->td_transfer_first; 1213 1214 if (xfer->flags_int.control_xfr) { 1215 1216 if (xfer->flags_int.control_hdr) { 1217 1218 err = at91dci_standard_done_sub(xfer); 1219 } 1220 xfer->aframes = 1; 1221 1222 if (xfer->td_transfer_cache == NULL) { 1223 goto done; 1224 } 1225 } 1226 while (xfer->aframes != xfer->nframes) { 1227 1228 err = at91dci_standard_done_sub(xfer); 1229 xfer->aframes++; 1230 1231 if (xfer->td_transfer_cache == NULL) { 1232 goto done; 1233 } 1234 } 1235 1236 if (xfer->flags_int.control_xfr && 1237 !xfer->flags_int.control_act) { 1238 1239 err = at91dci_standard_done_sub(xfer); 1240 } 1241done: 1242 at91dci_device_done(xfer, err); 1243 return; 1244} 1245 1246/*------------------------------------------------------------------------* 1247 * at91dci_device_done 1248 * 1249 * NOTE: this function can be called more than one time on the 1250 * same USB transfer! 1251 *------------------------------------------------------------------------*/ 1252static void 1253at91dci_device_done(struct usb2_xfer *xfer, usb2_error_t error) 1254{ 1255 struct at91dci_softc *sc = xfer->usb2_sc; 1256 uint8_t ep_no; 1257 1258 mtx_assert(&sc->sc_bus.mtx, MA_OWNED); 1259 1260 DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n", 1261 xfer, xfer->pipe, error); 1262 1263 if (xfer->flags_int.usb2_mode == USB_MODE_DEVICE) { 1264 ep_no = (xfer->endpoint & UE_ADDR); 1265 1266 /* disable endpoint interrupt */ 1267 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, AT91_UDP_INT_EP(ep_no)); 1268 1269 DPRINTFN(15, "disable interrupts on endpoint %d\n", ep_no); 1270 } 1271 /* dequeue transfer and start next transfer */ 1272 usb2_transfer_done(xfer, error); 1273 return; 1274} 1275 1276static void 1277at91dci_set_stall(struct usb2_device *udev, struct usb2_xfer *xfer, 1278 struct usb2_pipe *pipe) 1279{ 1280 struct at91dci_softc *sc; 1281 uint32_t csr_val; 1282 uint8_t csr_reg; 1283 1284 mtx_assert(&udev->bus->mtx, MA_OWNED); 1285 1286 DPRINTFN(5, "pipe=%p\n", pipe); 1287 1288 if (xfer) { 1289 /* cancel any ongoing transfers */ 1290 at91dci_device_done(xfer, USB_ERR_STALLED); 1291 } 1292 /* set FORCESTALL */ 1293 sc = AT9100_DCI_BUS2SC(udev->bus); 1294 csr_reg = (pipe->edesc->bEndpointAddress & UE_ADDR); 1295 csr_reg = AT91_UDP_CSR(csr_reg); 1296 csr_val = AT91_UDP_READ_4(sc, csr_reg); 1297 AT91_CSR_ACK(csr_val, AT91_UDP_CSR_FORCESTALL); 1298 AT91_UDP_WRITE_4(sc, csr_reg, csr_val); 1299 return; 1300} 1301 1302static void 1303at91dci_clear_stall_sub(struct at91dci_softc *sc, uint8_t ep_no, 1304 uint8_t ep_type, uint8_t ep_dir) 1305{ 1306 const struct usb2_hw_ep_profile *pf; 1307 uint32_t csr_val; 1308 uint32_t temp; 1309 uint8_t csr_reg; 1310 uint8_t to; 1311 1312 if (ep_type == UE_CONTROL) { 1313 /* clearing stall is not needed */ 1314 return; 1315 } 1316 /* compute CSR register offset */ 1317 csr_reg = AT91_UDP_CSR(ep_no); 1318 1319 /* compute default CSR value */ 1320 csr_val = 0; 1321 AT91_CSR_ACK(csr_val, 0); 1322 1323 /* disable endpoint */ 1324 AT91_UDP_WRITE_4(sc, csr_reg, csr_val); 1325 1326 /* get endpoint profile */ 1327 at91dci_get_hw_ep_profile(NULL, &pf, ep_no); 1328 1329 /* reset FIFO */ 1330 AT91_UDP_WRITE_4(sc, AT91_UDP_RST, AT91_UDP_RST_EP(ep_no)); 1331 AT91_UDP_WRITE_4(sc, AT91_UDP_RST, 0); 1332 1333 /* 1334 * NOTE: One would assume that a FIFO reset would release the 1335 * FIFO banks aswell, but it doesn't! We have to do this 1336 * manually! 1337 */ 1338 1339 /* release FIFO banks, if any */ 1340 for (to = 0; to != 2; to++) { 1341 1342 /* get csr value */ 1343 csr_val = AT91_UDP_READ_4(sc, csr_reg); 1344 1345 if (csr_val & (AT91_UDP_CSR_RX_DATA_BK0 | 1346 AT91_UDP_CSR_RX_DATA_BK1)) { 1347 /* clear status bits */ 1348 if (pf->support_multi_buffer) { 1349 if (sc->sc_ep_flags[ep_no].fifo_bank) { 1350 sc->sc_ep_flags[ep_no].fifo_bank = 0; 1351 temp = AT91_UDP_CSR_RX_DATA_BK1; 1352 } else { 1353 sc->sc_ep_flags[ep_no].fifo_bank = 1; 1354 temp = AT91_UDP_CSR_RX_DATA_BK0; 1355 } 1356 } else { 1357 temp = (AT91_UDP_CSR_RX_DATA_BK0 | 1358 AT91_UDP_CSR_RX_DATA_BK1); 1359 } 1360 } else { 1361 temp = 0; 1362 } 1363 1364 /* clear FORCESTALL */ 1365 temp |= AT91_UDP_CSR_STALLSENT; 1366 1367 AT91_CSR_ACK(csr_val, temp); 1368 AT91_UDP_WRITE_4(sc, csr_reg, csr_val); 1369 } 1370 1371 /* compute default CSR value */ 1372 csr_val = 0; 1373 AT91_CSR_ACK(csr_val, 0); 1374 1375 /* enable endpoint */ 1376 csr_val &= ~AT91_UDP_CSR_ET_MASK; 1377 csr_val |= AT91_UDP_CSR_EPEDS; 1378 1379 if (ep_type == UE_CONTROL) { 1380 csr_val |= AT91_UDP_CSR_ET_CTRL; 1381 } else { 1382 if (ep_type == UE_BULK) { 1383 csr_val |= AT91_UDP_CSR_ET_BULK; 1384 } else if (ep_type == UE_INTERRUPT) { 1385 csr_val |= AT91_UDP_CSR_ET_INT; 1386 } else { 1387 csr_val |= AT91_UDP_CSR_ET_ISO; 1388 } 1389 if (ep_dir & UE_DIR_IN) { 1390 csr_val |= AT91_UDP_CSR_ET_DIR_IN; 1391 } 1392 } 1393 1394 /* enable endpoint */ 1395 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(ep_no), csr_val); 1396 1397 return; 1398} 1399 1400static void 1401at91dci_clear_stall(struct usb2_device *udev, struct usb2_pipe *pipe) 1402{ 1403 struct at91dci_softc *sc; 1404 struct usb2_endpoint_descriptor *ed; 1405 1406 DPRINTFN(5, "pipe=%p\n", pipe); 1407 1408 mtx_assert(&udev->bus->mtx, MA_OWNED); 1409 1410 /* check mode */ 1411 if (udev->flags.usb2_mode != USB_MODE_DEVICE) { 1412 /* not supported */ 1413 return; 1414 } 1415 /* get softc */ 1416 sc = AT9100_DCI_BUS2SC(udev->bus); 1417 1418 /* get endpoint descriptor */ 1419 ed = pipe->edesc; 1420 1421 /* reset endpoint */ 1422 at91dci_clear_stall_sub(sc, 1423 (ed->bEndpointAddress & UE_ADDR), 1424 (ed->bmAttributes & UE_XFERTYPE), 1425 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1426 return; 1427} 1428 1429usb2_error_t 1430at91dci_init(struct at91dci_softc *sc) 1431{ 1432 uint32_t csr_val; 1433 uint8_t n; 1434 1435 DPRINTF("start\n"); 1436 1437 /* set up the bus structure */ 1438 sc->sc_bus.usbrev = USB_REV_1_1; 1439 sc->sc_bus.methods = &at91dci_bus_methods; 1440 1441 mtx_lock(&sc->sc_bus.mtx); 1442 1443 /* turn on clocks */ 1444 1445 if (sc->sc_clocks_on) { 1446 (sc->sc_clocks_on) (sc->sc_clocks_arg); 1447 } 1448 /* wait a little for things to stabilise */ 1449 usb2_pause_mtx(&sc->sc_bus.mtx, 1); 1450 1451 /* disable and clear all interrupts */ 1452 1453 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 0xFFFFFFFF); 1454 AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, 0xFFFFFFFF); 1455 1456 /* compute default CSR value */ 1457 1458 csr_val = 0; 1459 AT91_CSR_ACK(csr_val, 0); 1460 1461 /* disable all endpoints */ 1462 1463 for (n = 0; n != AT91_UDP_EP_MAX; n++) { 1464 1465 /* disable endpoint */ 1466 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(n), csr_val); 1467 } 1468 1469 /* enable the control endpoint */ 1470 1471 AT91_CSR_ACK(csr_val, AT91_UDP_CSR_ET_CTRL | 1472 AT91_UDP_CSR_EPEDS); 1473 1474 /* write to FIFO control register */ 1475 1476 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(0), csr_val); 1477 1478 /* enable the interrupts we want */ 1479 1480 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, AT91_UDP_INT_BUS); 1481 1482 /* turn off clocks */ 1483 1484 at91dci_clocks_off(sc); 1485 1486 mtx_unlock(&sc->sc_bus.mtx); 1487 1488 /* catch any lost interrupts */ 1489 1490 at91dci_do_poll(&sc->sc_bus); 1491 1492 return (0); /* success */ 1493} 1494 1495void 1496at91dci_uninit(struct at91dci_softc *sc) 1497{ 1498 mtx_lock(&sc->sc_bus.mtx); 1499 1500 /* disable and clear all interrupts */ 1501 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 0xFFFFFFFF); 1502 AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, 0xFFFFFFFF); 1503 1504 sc->sc_flags.port_powered = 0; 1505 sc->sc_flags.status_vbus = 0; 1506 sc->sc_flags.status_bus_reset = 0; 1507 sc->sc_flags.status_suspend = 0; 1508 sc->sc_flags.change_suspend = 0; 1509 sc->sc_flags.change_connect = 1; 1510 1511 at91dci_pull_down(sc); 1512 at91dci_clocks_off(sc); 1513 mtx_unlock(&sc->sc_bus.mtx); 1514 1515 return; 1516} 1517 1518void 1519at91dci_suspend(struct at91dci_softc *sc) 1520{ 1521 return; 1522} 1523 1524void 1525at91dci_resume(struct at91dci_softc *sc) 1526{ 1527 return; 1528} 1529 1530static void 1531at91dci_do_poll(struct usb2_bus *bus) 1532{ 1533 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(bus); 1534 1535 mtx_lock(&sc->sc_bus.mtx); 1536 at91dci_interrupt_poll(sc); 1537 at91dci_root_ctrl_poll(sc); 1538 mtx_unlock(&sc->sc_bus.mtx); 1539 return; 1540} 1541 1542/*------------------------------------------------------------------------* 1543 * at91dci bulk support 1544 *------------------------------------------------------------------------*/ 1545static void 1546at91dci_device_bulk_open(struct usb2_xfer *xfer) 1547{ 1548 return; 1549} 1550 1551static void 1552at91dci_device_bulk_close(struct usb2_xfer *xfer) 1553{ 1554 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1555 return; 1556} 1557 1558static void 1559at91dci_device_bulk_enter(struct usb2_xfer *xfer) 1560{ 1561 return; 1562} 1563 1564static void 1565at91dci_device_bulk_start(struct usb2_xfer *xfer) 1566{ 1567 /* setup TDs */ 1568 at91dci_setup_standard_chain(xfer); 1569 at91dci_start_standard_chain(xfer); 1570 return; 1571} 1572 1573struct usb2_pipe_methods at91dci_device_bulk_methods = 1574{ 1575 .open = at91dci_device_bulk_open, 1576 .close = at91dci_device_bulk_close, 1577 .enter = at91dci_device_bulk_enter, 1578 .start = at91dci_device_bulk_start, 1579 .enter_is_cancelable = 1, 1580 .start_is_cancelable = 1, 1581}; 1582 1583/*------------------------------------------------------------------------* 1584 * at91dci control support 1585 *------------------------------------------------------------------------*/ 1586static void 1587at91dci_device_ctrl_open(struct usb2_xfer *xfer) 1588{ 1589 return; 1590} 1591 1592static void 1593at91dci_device_ctrl_close(struct usb2_xfer *xfer) 1594{ 1595 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1596 return; 1597} 1598 1599static void 1600at91dci_device_ctrl_enter(struct usb2_xfer *xfer) 1601{ 1602 return; 1603} 1604 1605static void 1606at91dci_device_ctrl_start(struct usb2_xfer *xfer) 1607{ 1608 /* setup TDs */ 1609 at91dci_setup_standard_chain(xfer); 1610 at91dci_start_standard_chain(xfer); 1611 return; 1612} 1613 1614struct usb2_pipe_methods at91dci_device_ctrl_methods = 1615{ 1616 .open = at91dci_device_ctrl_open, 1617 .close = at91dci_device_ctrl_close, 1618 .enter = at91dci_device_ctrl_enter, 1619 .start = at91dci_device_ctrl_start, 1620 .enter_is_cancelable = 1, 1621 .start_is_cancelable = 1, 1622}; 1623 1624/*------------------------------------------------------------------------* 1625 * at91dci interrupt support 1626 *------------------------------------------------------------------------*/ 1627static void 1628at91dci_device_intr_open(struct usb2_xfer *xfer) 1629{ 1630 return; 1631} 1632 1633static void 1634at91dci_device_intr_close(struct usb2_xfer *xfer) 1635{ 1636 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1637 return; 1638} 1639 1640static void 1641at91dci_device_intr_enter(struct usb2_xfer *xfer) 1642{ 1643 return; 1644} 1645 1646static void 1647at91dci_device_intr_start(struct usb2_xfer *xfer) 1648{ 1649 /* setup TDs */ 1650 at91dci_setup_standard_chain(xfer); 1651 at91dci_start_standard_chain(xfer); 1652 return; 1653} 1654 1655struct usb2_pipe_methods at91dci_device_intr_methods = 1656{ 1657 .open = at91dci_device_intr_open, 1658 .close = at91dci_device_intr_close, 1659 .enter = at91dci_device_intr_enter, 1660 .start = at91dci_device_intr_start, 1661 .enter_is_cancelable = 1, 1662 .start_is_cancelable = 1, 1663}; 1664 1665/*------------------------------------------------------------------------* 1666 * at91dci full speed isochronous support 1667 *------------------------------------------------------------------------*/ 1668static void 1669at91dci_device_isoc_fs_open(struct usb2_xfer *xfer) 1670{ 1671 return; 1672} 1673 1674static void 1675at91dci_device_isoc_fs_close(struct usb2_xfer *xfer) 1676{ 1677 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1678 return; 1679} 1680 1681static void 1682at91dci_device_isoc_fs_enter(struct usb2_xfer *xfer) 1683{ 1684 struct at91dci_softc *sc = xfer->usb2_sc; 1685 uint32_t temp; 1686 uint32_t nframes; 1687 1688 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 1689 xfer, xfer->pipe->isoc_next, xfer->nframes); 1690 1691 /* get the current frame index */ 1692 1693 nframes = AT91_UDP_READ_4(sc, AT91_UDP_FRM); 1694 1695 /* 1696 * check if the frame index is within the window where the frames 1697 * will be inserted 1698 */ 1699 temp = (nframes - xfer->pipe->isoc_next) & AT91_UDP_FRM_MASK; 1700 1701 if ((xfer->pipe->is_synced == 0) || 1702 (temp < xfer->nframes)) { 1703 /* 1704 * If there is data underflow or the pipe queue is 1705 * empty we schedule the transfer a few frames ahead 1706 * of the current frame position. Else two isochronous 1707 * transfers might overlap. 1708 */ 1709 xfer->pipe->isoc_next = (nframes + 3) & AT91_UDP_FRM_MASK; 1710 xfer->pipe->is_synced = 1; 1711 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next); 1712 } 1713 /* 1714 * compute how many milliseconds the insertion is ahead of the 1715 * current frame position: 1716 */ 1717 temp = (xfer->pipe->isoc_next - nframes) & AT91_UDP_FRM_MASK; 1718 1719 /* 1720 * pre-compute when the isochronous transfer will be finished: 1721 */ 1722 xfer->isoc_time_complete = 1723 usb2_isoc_time_expand(&sc->sc_bus, nframes) + temp + 1724 xfer->nframes; 1725 1726 /* compute frame number for next insertion */ 1727 xfer->pipe->isoc_next += xfer->nframes; 1728 1729 /* setup TDs */ 1730 at91dci_setup_standard_chain(xfer); 1731 return; 1732} 1733 1734static void 1735at91dci_device_isoc_fs_start(struct usb2_xfer *xfer) 1736{ 1737 /* start TD chain */ 1738 at91dci_start_standard_chain(xfer); 1739 return; 1740} 1741 1742struct usb2_pipe_methods at91dci_device_isoc_fs_methods = 1743{ 1744 .open = at91dci_device_isoc_fs_open, 1745 .close = at91dci_device_isoc_fs_close, 1746 .enter = at91dci_device_isoc_fs_enter, 1747 .start = at91dci_device_isoc_fs_start, 1748 .enter_is_cancelable = 1, 1749 .start_is_cancelable = 1, 1750}; 1751 1752/*------------------------------------------------------------------------* 1753 * at91dci root control support 1754 *------------------------------------------------------------------------* 1755 * simulate a hardware HUB by handling 1756 * all the necessary requests 1757 *------------------------------------------------------------------------*/ 1758 1759static void 1760at91dci_root_ctrl_open(struct usb2_xfer *xfer) 1761{ 1762 return; 1763} 1764 1765static void 1766at91dci_root_ctrl_close(struct usb2_xfer *xfer) 1767{ 1768 struct at91dci_softc *sc = xfer->usb2_sc; 1769 1770 if (sc->sc_root_ctrl.xfer == xfer) { 1771 sc->sc_root_ctrl.xfer = NULL; 1772 } 1773 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1774 return; 1775} 1776 1777/* 1778 * USB descriptors for the virtual Root HUB: 1779 */ 1780 1781static const struct usb2_device_descriptor at91dci_devd = { 1782 .bLength = sizeof(struct usb2_device_descriptor), 1783 .bDescriptorType = UDESC_DEVICE, 1784 .bcdUSB = {0x00, 0x02}, 1785 .bDeviceClass = UDCLASS_HUB, 1786 .bDeviceSubClass = UDSUBCLASS_HUB, 1787 .bDeviceProtocol = UDPROTO_HSHUBSTT, 1788 .bMaxPacketSize = 64, 1789 .bcdDevice = {0x00, 0x01}, 1790 .iManufacturer = 1, 1791 .iProduct = 2, 1792 .bNumConfigurations = 1, 1793}; 1794 1795static const struct usb2_device_qualifier at91dci_odevd = { 1796 .bLength = sizeof(struct usb2_device_qualifier), 1797 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 1798 .bcdUSB = {0x00, 0x02}, 1799 .bDeviceClass = UDCLASS_HUB, 1800 .bDeviceSubClass = UDSUBCLASS_HUB, 1801 .bDeviceProtocol = UDPROTO_FSHUB, 1802 .bMaxPacketSize0 = 0, 1803 .bNumConfigurations = 0, 1804}; 1805 1806static const struct at91dci_config_desc at91dci_confd = { 1807 .confd = { 1808 .bLength = sizeof(struct usb2_config_descriptor), 1809 .bDescriptorType = UDESC_CONFIG, 1810 .wTotalLength[0] = sizeof(at91dci_confd), 1811 .bNumInterface = 1, 1812 .bConfigurationValue = 1, 1813 .iConfiguration = 0, 1814 .bmAttributes = UC_SELF_POWERED, 1815 .bMaxPower = 0, 1816 }, 1817 .ifcd = { 1818 .bLength = sizeof(struct usb2_interface_descriptor), 1819 .bDescriptorType = UDESC_INTERFACE, 1820 .bNumEndpoints = 1, 1821 .bInterfaceClass = UICLASS_HUB, 1822 .bInterfaceSubClass = UISUBCLASS_HUB, 1823 .bInterfaceProtocol = UIPROTO_HSHUBSTT, 1824 }, 1825 1826 .endpd = { 1827 .bLength = sizeof(struct usb2_endpoint_descriptor), 1828 .bDescriptorType = UDESC_ENDPOINT, 1829 .bEndpointAddress = (UE_DIR_IN | AT9100_DCI_INTR_ENDPT), 1830 .bmAttributes = UE_INTERRUPT, 1831 .wMaxPacketSize[0] = 8, 1832 .bInterval = 255, 1833 }, 1834}; 1835 1836static const struct usb2_hub_descriptor_min at91dci_hubd = { 1837 .bDescLength = sizeof(at91dci_hubd), 1838 .bDescriptorType = UDESC_HUB, 1839 .bNbrPorts = 1, 1840 .wHubCharacteristics[0] = 1841 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) & 0xFF, 1842 .wHubCharacteristics[1] = 1843 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) >> 16, 1844 .bPwrOn2PwrGood = 50, 1845 .bHubContrCurrent = 0, 1846 .DeviceRemovable = {0}, /* port is removable */ 1847}; 1848 1849#define STRING_LANG \ 1850 0x09, 0x04, /* American English */ 1851 1852#define STRING_VENDOR \ 1853 'A', 0, 'T', 0, 'M', 0, 'E', 0, 'L', 0 1854 1855#define STRING_PRODUCT \ 1856 'D', 0, 'C', 0, 'I', 0, ' ', 0, 'R', 0, \ 1857 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \ 1858 'U', 0, 'B', 0, 1859 1860USB_MAKE_STRING_DESC(STRING_LANG, at91dci_langtab); 1861USB_MAKE_STRING_DESC(STRING_VENDOR, at91dci_vendor); 1862USB_MAKE_STRING_DESC(STRING_PRODUCT, at91dci_product); 1863 1864static void 1865at91dci_root_ctrl_enter(struct usb2_xfer *xfer) 1866{ 1867 return; 1868} 1869 1870static void 1871at91dci_root_ctrl_start(struct usb2_xfer *xfer) 1872{ 1873 struct at91dci_softc *sc = xfer->usb2_sc; 1874 1875 sc->sc_root_ctrl.xfer = xfer; 1876 1877 usb2_config_td_queue_command( 1878 &sc->sc_config_td, NULL, &at91dci_root_ctrl_task, 0, 0); 1879 1880 return; 1881} 1882 1883static void 1884at91dci_root_ctrl_task(struct at91dci_softc *sc, 1885 struct at91dci_config_copy *cc, uint16_t refcount) 1886{ 1887 at91dci_root_ctrl_poll(sc); 1888 return; 1889} 1890 1891static void 1892at91dci_root_ctrl_done(struct usb2_xfer *xfer, 1893 struct usb2_sw_transfer *std) 1894{ 1895 struct at91dci_softc *sc = xfer->usb2_sc; 1896 uint16_t value; 1897 uint16_t index; 1898 uint8_t use_polling; 1899 1900 mtx_assert(&sc->sc_bus.mtx, MA_OWNED); 1901 1902 if (std->state != USB_SW_TR_SETUP) { 1903 if (std->state == USB_SW_TR_PRE_CALLBACK) { 1904 /* transfer transferred */ 1905 at91dci_device_done(xfer, std->err); 1906 } 1907 goto done; 1908 } 1909 /* buffer reset */ 1910 std->ptr = USB_ADD_BYTES(&sc->sc_hub_temp, 0); 1911 std->len = 0; 1912 1913 value = UGETW(std->req.wValue); 1914 index = UGETW(std->req.wIndex); 1915 1916 use_polling = mtx_owned(xfer->priv_mtx) ? 1 : 0; 1917 1918 /* demultiplex the control request */ 1919 1920 switch (std->req.bmRequestType) { 1921 case UT_READ_DEVICE: 1922 switch (std->req.bRequest) { 1923 case UR_GET_DESCRIPTOR: 1924 goto tr_handle_get_descriptor; 1925 case UR_GET_CONFIG: 1926 goto tr_handle_get_config; 1927 case UR_GET_STATUS: 1928 goto tr_handle_get_status; 1929 default: 1930 goto tr_stalled; 1931 } 1932 break; 1933 1934 case UT_WRITE_DEVICE: 1935 switch (std->req.bRequest) { 1936 case UR_SET_ADDRESS: 1937 goto tr_handle_set_address; 1938 case UR_SET_CONFIG: 1939 goto tr_handle_set_config; 1940 case UR_CLEAR_FEATURE: 1941 goto tr_valid; /* nop */ 1942 case UR_SET_DESCRIPTOR: 1943 goto tr_valid; /* nop */ 1944 case UR_SET_FEATURE: 1945 default: 1946 goto tr_stalled; 1947 } 1948 break; 1949 1950 case UT_WRITE_ENDPOINT: 1951 switch (std->req.bRequest) { 1952 case UR_CLEAR_FEATURE: 1953 switch (UGETW(std->req.wValue)) { 1954 case UF_ENDPOINT_HALT: 1955 goto tr_handle_clear_halt; 1956 case UF_DEVICE_REMOTE_WAKEUP: 1957 goto tr_handle_clear_wakeup; 1958 default: 1959 goto tr_stalled; 1960 } 1961 break; 1962 case UR_SET_FEATURE: 1963 switch (UGETW(std->req.wValue)) { 1964 case UF_ENDPOINT_HALT: 1965 goto tr_handle_set_halt; 1966 case UF_DEVICE_REMOTE_WAKEUP: 1967 goto tr_handle_set_wakeup; 1968 default: 1969 goto tr_stalled; 1970 } 1971 break; 1972 case UR_SYNCH_FRAME: 1973 goto tr_valid; /* nop */ 1974 default: 1975 goto tr_stalled; 1976 } 1977 break; 1978 1979 case UT_READ_ENDPOINT: 1980 switch (std->req.bRequest) { 1981 case UR_GET_STATUS: 1982 goto tr_handle_get_ep_status; 1983 default: 1984 goto tr_stalled; 1985 } 1986 break; 1987 1988 case UT_WRITE_INTERFACE: 1989 switch (std->req.bRequest) { 1990 case UR_SET_INTERFACE: 1991 goto tr_handle_set_interface; 1992 case UR_CLEAR_FEATURE: 1993 goto tr_valid; /* nop */ 1994 case UR_SET_FEATURE: 1995 default: 1996 goto tr_stalled; 1997 } 1998 break; 1999 2000 case UT_READ_INTERFACE: 2001 switch (std->req.bRequest) { 2002 case UR_GET_INTERFACE: 2003 goto tr_handle_get_interface; 2004 case UR_GET_STATUS: 2005 goto tr_handle_get_iface_status; 2006 default: 2007 goto tr_stalled; 2008 } 2009 break; 2010 2011 case UT_WRITE_CLASS_INTERFACE: 2012 case UT_WRITE_VENDOR_INTERFACE: 2013 /* XXX forward */ 2014 break; 2015 2016 case UT_READ_CLASS_INTERFACE: 2017 case UT_READ_VENDOR_INTERFACE: 2018 /* XXX forward */ 2019 break; 2020 2021 case UT_WRITE_CLASS_DEVICE: 2022 switch (std->req.bRequest) { 2023 case UR_CLEAR_FEATURE: 2024 goto tr_valid; 2025 case UR_SET_DESCRIPTOR: 2026 case UR_SET_FEATURE: 2027 break; 2028 default: 2029 goto tr_stalled; 2030 } 2031 break; 2032 2033 case UT_WRITE_CLASS_OTHER: 2034 switch (std->req.bRequest) { 2035 case UR_CLEAR_FEATURE: 2036 goto tr_handle_clear_port_feature; 2037 case UR_SET_FEATURE: 2038 goto tr_handle_set_port_feature; 2039 case UR_CLEAR_TT_BUFFER: 2040 case UR_RESET_TT: 2041 case UR_STOP_TT: 2042 goto tr_valid; 2043 2044 default: 2045 goto tr_stalled; 2046 } 2047 break; 2048 2049 case UT_READ_CLASS_OTHER: 2050 switch (std->req.bRequest) { 2051 case UR_GET_TT_STATE: 2052 goto tr_handle_get_tt_state; 2053 case UR_GET_STATUS: 2054 goto tr_handle_get_port_status; 2055 default: 2056 goto tr_stalled; 2057 } 2058 break; 2059 2060 case UT_READ_CLASS_DEVICE: 2061 switch (std->req.bRequest) { 2062 case UR_GET_DESCRIPTOR: 2063 goto tr_handle_get_class_descriptor; 2064 case UR_GET_STATUS: 2065 goto tr_handle_get_class_status; 2066 2067 default: 2068 goto tr_stalled; 2069 } 2070 break; 2071 default: 2072 goto tr_stalled; 2073 } 2074 goto tr_valid; 2075 2076tr_handle_get_descriptor: 2077 switch (value >> 8) { 2078 case UDESC_DEVICE: 2079 if (value & 0xff) { 2080 goto tr_stalled; 2081 } 2082 std->len = sizeof(at91dci_devd); 2083 std->ptr = USB_ADD_BYTES(&at91dci_devd, 0); 2084 goto tr_valid; 2085 case UDESC_CONFIG: 2086 if (value & 0xff) { 2087 goto tr_stalled; 2088 } 2089 std->len = sizeof(at91dci_confd); 2090 std->ptr = USB_ADD_BYTES(&at91dci_confd, 0); 2091 goto tr_valid; 2092 case UDESC_STRING: 2093 switch (value & 0xff) { 2094 case 0: /* Language table */ 2095 std->len = sizeof(at91dci_langtab); 2096 std->ptr = USB_ADD_BYTES(&at91dci_langtab, 0); 2097 goto tr_valid; 2098 2099 case 1: /* Vendor */ 2100 std->len = sizeof(at91dci_vendor); 2101 std->ptr = USB_ADD_BYTES(&at91dci_vendor, 0); 2102 goto tr_valid; 2103 2104 case 2: /* Product */ 2105 std->len = sizeof(at91dci_product); 2106 std->ptr = USB_ADD_BYTES(&at91dci_product, 0); 2107 goto tr_valid; 2108 default: 2109 break; 2110 } 2111 break; 2112 default: 2113 goto tr_stalled; 2114 } 2115 goto tr_stalled; 2116 2117tr_handle_get_config: 2118 std->len = 1; 2119 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 2120 goto tr_valid; 2121 2122tr_handle_get_status: 2123 std->len = 2; 2124 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 2125 goto tr_valid; 2126 2127tr_handle_set_address: 2128 if (value & 0xFF00) { 2129 goto tr_stalled; 2130 } 2131 sc->sc_rt_addr = value; 2132 goto tr_valid; 2133 2134tr_handle_set_config: 2135 if (value >= 2) { 2136 goto tr_stalled; 2137 } 2138 sc->sc_conf = value; 2139 goto tr_valid; 2140 2141tr_handle_get_interface: 2142 std->len = 1; 2143 sc->sc_hub_temp.wValue[0] = 0; 2144 goto tr_valid; 2145 2146tr_handle_get_tt_state: 2147tr_handle_get_class_status: 2148tr_handle_get_iface_status: 2149tr_handle_get_ep_status: 2150 std->len = 2; 2151 USETW(sc->sc_hub_temp.wValue, 0); 2152 goto tr_valid; 2153 2154tr_handle_set_halt: 2155tr_handle_set_interface: 2156tr_handle_set_wakeup: 2157tr_handle_clear_wakeup: 2158tr_handle_clear_halt: 2159 goto tr_valid; 2160 2161tr_handle_clear_port_feature: 2162 if (index != 1) { 2163 goto tr_stalled; 2164 } 2165 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 2166 2167 switch (value) { 2168 case UHF_PORT_SUSPEND: 2169 at91dci_wakeup_peer(sc); 2170 break; 2171 2172 case UHF_PORT_ENABLE: 2173 sc->sc_flags.port_enabled = 0; 2174 break; 2175 2176 case UHF_PORT_TEST: 2177 case UHF_PORT_INDICATOR: 2178 case UHF_C_PORT_ENABLE: 2179 case UHF_C_PORT_OVER_CURRENT: 2180 case UHF_C_PORT_RESET: 2181 /* nops */ 2182 break; 2183 case UHF_PORT_POWER: 2184 sc->sc_flags.port_powered = 0; 2185 at91dci_pull_down(sc); 2186 at91dci_clocks_off(sc); 2187 break; 2188 case UHF_C_PORT_CONNECTION: 2189 sc->sc_flags.change_connect = 0; 2190 break; 2191 case UHF_C_PORT_SUSPEND: 2192 sc->sc_flags.change_suspend = 0; 2193 break; 2194 default: 2195 std->err = USB_ERR_IOERROR; 2196 goto done; 2197 } 2198 goto tr_valid; 2199 2200tr_handle_set_port_feature: 2201 if (index != 1) { 2202 goto tr_stalled; 2203 } 2204 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 2205 2206 switch (value) { 2207 case UHF_PORT_ENABLE: 2208 sc->sc_flags.port_enabled = 1; 2209 break; 2210 case UHF_PORT_SUSPEND: 2211 case UHF_PORT_RESET: 2212 case UHF_PORT_TEST: 2213 case UHF_PORT_INDICATOR: 2214 /* nops */ 2215 break; 2216 case UHF_PORT_POWER: 2217 sc->sc_flags.port_powered = 1; 2218 break; 2219 default: 2220 std->err = USB_ERR_IOERROR; 2221 goto done; 2222 } 2223 goto tr_valid; 2224 2225tr_handle_get_port_status: 2226 2227 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 2228 2229 if (index != 1) { 2230 goto tr_stalled; 2231 } 2232 if (sc->sc_flags.status_vbus) { 2233 at91dci_clocks_on(sc); 2234 at91dci_pull_up(sc); 2235 } else { 2236 at91dci_pull_down(sc); 2237 at91dci_clocks_off(sc); 2238 } 2239 2240 /* Select FULL-speed and Device Side Mode */ 2241 2242 value = UPS_PORT_MODE_DEVICE; 2243 2244 if (sc->sc_flags.port_powered) { 2245 value |= UPS_PORT_POWER; 2246 } 2247 if (sc->sc_flags.port_enabled) { 2248 value |= UPS_PORT_ENABLED; 2249 } 2250 if (sc->sc_flags.status_vbus && 2251 sc->sc_flags.status_bus_reset) { 2252 value |= UPS_CURRENT_CONNECT_STATUS; 2253 } 2254 if (sc->sc_flags.status_suspend) { 2255 value |= UPS_SUSPEND; 2256 } 2257 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 2258 2259 value = 0; 2260 2261 if (sc->sc_flags.change_connect) { 2262 value |= UPS_C_CONNECT_STATUS; 2263 2264 if (sc->sc_flags.status_vbus && 2265 sc->sc_flags.status_bus_reset) { 2266 /* reset endpoint flags */ 2267 bzero(sc->sc_ep_flags, sizeof(sc->sc_ep_flags)); 2268 } 2269 } 2270 if (sc->sc_flags.change_suspend) { 2271 value |= UPS_C_SUSPEND; 2272 } 2273 USETW(sc->sc_hub_temp.ps.wPortChange, value); 2274 std->len = sizeof(sc->sc_hub_temp.ps); 2275 goto tr_valid; 2276 2277tr_handle_get_class_descriptor: 2278 if (value & 0xFF) { 2279 goto tr_stalled; 2280 } 2281 std->ptr = USB_ADD_BYTES(&at91dci_hubd, 0); 2282 std->len = sizeof(at91dci_hubd); 2283 goto tr_valid; 2284 2285tr_stalled: 2286 std->err = USB_ERR_STALLED; 2287tr_valid: 2288done: 2289 return; 2290} 2291 2292static void 2293at91dci_root_ctrl_poll(struct at91dci_softc *sc) 2294{ 2295 usb2_sw_transfer(&sc->sc_root_ctrl, 2296 &at91dci_root_ctrl_done); 2297 return; 2298} 2299 2300struct usb2_pipe_methods at91dci_root_ctrl_methods = 2301{ 2302 .open = at91dci_root_ctrl_open, 2303 .close = at91dci_root_ctrl_close, 2304 .enter = at91dci_root_ctrl_enter, 2305 .start = at91dci_root_ctrl_start, 2306 .enter_is_cancelable = 1, 2307 .start_is_cancelable = 0, 2308}; 2309 2310/*------------------------------------------------------------------------* 2311 * at91dci root interrupt support 2312 *------------------------------------------------------------------------*/ 2313static void 2314at91dci_root_intr_open(struct usb2_xfer *xfer) 2315{ 2316 return; 2317} 2318 2319static void 2320at91dci_root_intr_close(struct usb2_xfer *xfer) 2321{ 2322 struct at91dci_softc *sc = xfer->usb2_sc; 2323 2324 if (sc->sc_root_intr.xfer == xfer) { 2325 sc->sc_root_intr.xfer = NULL; 2326 } 2327 at91dci_device_done(xfer, USB_ERR_CANCELLED); 2328 return; 2329} 2330 2331static void 2332at91dci_root_intr_enter(struct usb2_xfer *xfer) 2333{ 2334 return; 2335} 2336 2337static void 2338at91dci_root_intr_start(struct usb2_xfer *xfer) 2339{ 2340 struct at91dci_softc *sc = xfer->usb2_sc; 2341 2342 sc->sc_root_intr.xfer = xfer; 2343 return; 2344} 2345 2346struct usb2_pipe_methods at91dci_root_intr_methods = 2347{ 2348 .open = at91dci_root_intr_open, 2349 .close = at91dci_root_intr_close, 2350 .enter = at91dci_root_intr_enter, 2351 .start = at91dci_root_intr_start, 2352 .enter_is_cancelable = 1, 2353 .start_is_cancelable = 1, 2354}; 2355 2356static void 2357at91dci_xfer_setup(struct usb2_setup_params *parm) 2358{ 2359 const struct usb2_hw_ep_profile *pf; 2360 struct at91dci_softc *sc; 2361 struct usb2_xfer *xfer; 2362 void *last_obj; 2363 uint32_t ntd; 2364 uint32_t n; 2365 uint8_t ep_no; 2366 2367 sc = AT9100_DCI_BUS2SC(parm->udev->bus); 2368 xfer = parm->curr_xfer; 2369 2370 /* 2371 * setup xfer 2372 */ 2373 xfer->usb2_sc = sc; 2374 2375 /* 2376 * NOTE: This driver does not use any of the parameters that 2377 * are computed from the following values. Just set some 2378 * reasonable dummies: 2379 */ 2380 parm->hc_max_packet_size = 0x500; 2381 parm->hc_max_packet_count = 1; 2382 parm->hc_max_frame_size = 0x500; 2383 2384 usb2_transfer_setup_sub(parm); 2385 2386 /* 2387 * compute maximum number of TDs 2388 */ 2389 if (parm->methods == &at91dci_device_ctrl_methods) { 2390 2391 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 2392 + 1 /* SYNC 2 */ ; 2393 2394 } else if (parm->methods == &at91dci_device_bulk_methods) { 2395 2396 ntd = xfer->nframes + 1 /* SYNC */ ; 2397 2398 } else if (parm->methods == &at91dci_device_intr_methods) { 2399 2400 ntd = xfer->nframes + 1 /* SYNC */ ; 2401 2402 } else if (parm->methods == &at91dci_device_isoc_fs_methods) { 2403 2404 ntd = xfer->nframes + 1 /* SYNC */ ; 2405 2406 } else { 2407 2408 ntd = 0; 2409 } 2410 2411 /* 2412 * check if "usb2_transfer_setup_sub" set an error 2413 */ 2414 if (parm->err) { 2415 return; 2416 } 2417 /* 2418 * allocate transfer descriptors 2419 */ 2420 last_obj = NULL; 2421 2422 /* 2423 * get profile stuff 2424 */ 2425 if (ntd) { 2426 2427 ep_no = xfer->endpoint & UE_ADDR; 2428 at91dci_get_hw_ep_profile(parm->udev, &pf, ep_no); 2429 2430 if (pf == NULL) { 2431 /* should not happen */ 2432 parm->err = USB_ERR_INVAL; 2433 return; 2434 } 2435 } else { 2436 ep_no = 0; 2437 pf = NULL; 2438 } 2439 2440 /* align data */ 2441 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2442 2443 for (n = 0; n != ntd; n++) { 2444 2445 struct at91dci_td *td; 2446 2447 if (parm->buf) { 2448 2449 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2450 2451 /* init TD */ 2452 td->io_tag = sc->sc_io_tag; 2453 td->io_hdl = sc->sc_io_hdl; 2454 td->max_packet_size = xfer->max_packet_size; 2455 td->status_reg = AT91_UDP_CSR(ep_no); 2456 td->fifo_reg = AT91_UDP_FDR(ep_no); 2457 if (pf->support_multi_buffer) { 2458 td->support_multi_buffer = 1; 2459 } 2460 td->obj_next = last_obj; 2461 2462 last_obj = td; 2463 } 2464 parm->size[0] += sizeof(*td); 2465 } 2466 2467 xfer->td_start[0] = last_obj; 2468 return; 2469} 2470 2471static void 2472at91dci_xfer_unsetup(struct usb2_xfer *xfer) 2473{ 2474 return; 2475} 2476 2477static void 2478at91dci_pipe_init(struct usb2_device *udev, struct usb2_endpoint_descriptor *edesc, 2479 struct usb2_pipe *pipe) 2480{ 2481 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(udev->bus); 2482 2483 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 2484 pipe, udev->address, 2485 edesc->bEndpointAddress, udev->flags.usb2_mode, 2486 sc->sc_rt_addr); 2487 2488 if (udev->device_index == sc->sc_rt_addr) { 2489 2490 if (udev->flags.usb2_mode != USB_MODE_HOST) { 2491 /* not supported */ 2492 return; 2493 } 2494 switch (edesc->bEndpointAddress) { 2495 case USB_CONTROL_ENDPOINT: 2496 pipe->methods = &at91dci_root_ctrl_methods; 2497 break; 2498 case UE_DIR_IN | AT9100_DCI_INTR_ENDPT: 2499 pipe->methods = &at91dci_root_intr_methods; 2500 break; 2501 default: 2502 /* do nothing */ 2503 break; 2504 } 2505 } else { 2506 2507 if (udev->flags.usb2_mode != USB_MODE_DEVICE) { 2508 /* not supported */ 2509 return; 2510 } 2511 if (udev->speed != USB_SPEED_FULL) { 2512 /* not supported */ 2513 return; 2514 } 2515 switch (edesc->bmAttributes & UE_XFERTYPE) { 2516 case UE_CONTROL: 2517 pipe->methods = &at91dci_device_ctrl_methods; 2518 break; 2519 case UE_INTERRUPT: 2520 pipe->methods = &at91dci_device_intr_methods; 2521 break; 2522 case UE_ISOCHRONOUS: 2523 pipe->methods = &at91dci_device_isoc_fs_methods; 2524 break; 2525 case UE_BULK: 2526 pipe->methods = &at91dci_device_bulk_methods; 2527 break; 2528 default: 2529 /* do nothing */ 2530 break; 2531 } 2532 } 2533 return; 2534} 2535 2536struct usb2_bus_methods at91dci_bus_methods = 2537{ 2538 .pipe_init = &at91dci_pipe_init, 2539 .xfer_setup = &at91dci_xfer_setup, 2540 .xfer_unsetup = &at91dci_xfer_unsetup, 2541 .do_poll = &at91dci_do_poll, 2542 .get_hw_ep_profile = &at91dci_get_hw_ep_profile, 2543 .set_stall = &at91dci_set_stall, 2544 .clear_stall = &at91dci_clear_stall, 2545 .vbus_interrupt = &at91dci_vbus_interrupt, 2546 .rem_wakeup_set = &at91dci_rem_wakeup_set, 2547}; 2548