at91dci.c revision 213802
1#include <sys/cdefs.h> 2__FBSDID("$FreeBSD: head/sys/dev/usb/controller/at91dci.c 213802 2010-10-13 20:37:19Z hselasky $"); 3 4/*- 5 * Copyright (c) 2007-2008 Hans Petter Selasky. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * This file contains the driver for the AT91 series USB Device 31 * Controller 32 */ 33 34/* 35 * Thanks to "David Brownell" for helping out regarding the hardware 36 * endpoint profiles. 37 */ 38 39/* 40 * NOTE: The "fifo_bank" is not reset in hardware when the endpoint is 41 * reset. 42 * 43 * NOTE: When the chip detects BUS-reset it will also reset the 44 * endpoints, Function-address and more. 45 */ 46 47#include <sys/stdint.h> 48#include <sys/stddef.h> 49#include <sys/param.h> 50#include <sys/queue.h> 51#include <sys/types.h> 52#include <sys/systm.h> 53#include <sys/kernel.h> 54#include <sys/bus.h> 55#include <sys/linker_set.h> 56#include <sys/module.h> 57#include <sys/lock.h> 58#include <sys/mutex.h> 59#include <sys/condvar.h> 60#include <sys/sysctl.h> 61#include <sys/sx.h> 62#include <sys/unistd.h> 63#include <sys/callout.h> 64#include <sys/malloc.h> 65#include <sys/priv.h> 66 67#include <dev/usb/usb.h> 68#include <dev/usb/usbdi.h> 69 70#define USB_DEBUG_VAR at91dcidebug 71 72#include <dev/usb/usb_core.h> 73#include <dev/usb/usb_debug.h> 74#include <dev/usb/usb_busdma.h> 75#include <dev/usb/usb_process.h> 76#include <dev/usb/usb_transfer.h> 77#include <dev/usb/usb_device.h> 78#include <dev/usb/usb_hub.h> 79#include <dev/usb/usb_util.h> 80 81#include <dev/usb/usb_controller.h> 82#include <dev/usb/usb_bus.h> 83#include <dev/usb/controller/at91dci.h> 84 85#define AT9100_DCI_BUS2SC(bus) \ 86 ((struct at91dci_softc *)(((uint8_t *)(bus)) - \ 87 ((uint8_t *)&(((struct at91dci_softc *)0)->sc_bus)))) 88 89#define AT9100_DCI_PC2SC(pc) \ 90 AT9100_DCI_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 91 92#ifdef USB_DEBUG 93static int at91dcidebug = 0; 94 95SYSCTL_NODE(_hw_usb, OID_AUTO, at91dci, CTLFLAG_RW, 0, "USB at91dci"); 96SYSCTL_INT(_hw_usb_at91dci, OID_AUTO, debug, CTLFLAG_RW, 97 &at91dcidebug, 0, "at91dci debug level"); 98#endif 99 100#define AT9100_DCI_INTR_ENDPT 1 101 102/* prototypes */ 103 104struct usb_bus_methods at91dci_bus_methods; 105struct usb_pipe_methods at91dci_device_bulk_methods; 106struct usb_pipe_methods at91dci_device_ctrl_methods; 107struct usb_pipe_methods at91dci_device_intr_methods; 108struct usb_pipe_methods at91dci_device_isoc_fs_methods; 109 110static at91dci_cmd_t at91dci_setup_rx; 111static at91dci_cmd_t at91dci_data_rx; 112static at91dci_cmd_t at91dci_data_tx; 113static at91dci_cmd_t at91dci_data_tx_sync; 114static void at91dci_device_done(struct usb_xfer *, usb_error_t); 115static void at91dci_do_poll(struct usb_bus *); 116static void at91dci_standard_done(struct usb_xfer *); 117static void at91dci_root_intr(struct at91dci_softc *sc); 118 119/* 120 * NOTE: Some of the bits in the CSR register have inverse meaning so 121 * we need a helper macro when acknowledging events: 122 */ 123#define AT91_CSR_ACK(csr, what) do { \ 124 (csr) &= ~((AT91_UDP_CSR_FORCESTALL| \ 125 AT91_UDP_CSR_TXPKTRDY| \ 126 AT91_UDP_CSR_RXBYTECNT) ^ (what));\ 127 (csr) |= ((AT91_UDP_CSR_RX_DATA_BK0| \ 128 AT91_UDP_CSR_RX_DATA_BK1| \ 129 AT91_UDP_CSR_TXCOMP| \ 130 AT91_UDP_CSR_RXSETUP| \ 131 AT91_UDP_CSR_STALLSENT) ^ (what)); \ 132} while (0) 133 134/* 135 * Here is a list of what the chip supports. 136 * Probably it supports more than listed here! 137 */ 138static const struct usb_hw_ep_profile 139 at91dci_ep_profile[AT91_UDP_EP_MAX] = { 140 141 [0] = { 142 .max_in_frame_size = 8, 143 .max_out_frame_size = 8, 144 .is_simplex = 1, 145 .support_control = 1, 146 }, 147 [1] = { 148 .max_in_frame_size = 64, 149 .max_out_frame_size = 64, 150 .is_simplex = 1, 151 .support_multi_buffer = 1, 152 .support_bulk = 1, 153 .support_interrupt = 1, 154 .support_isochronous = 1, 155 .support_in = 1, 156 .support_out = 1, 157 }, 158 [2] = { 159 .max_in_frame_size = 64, 160 .max_out_frame_size = 64, 161 .is_simplex = 1, 162 .support_multi_buffer = 1, 163 .support_bulk = 1, 164 .support_interrupt = 1, 165 .support_isochronous = 1, 166 .support_in = 1, 167 .support_out = 1, 168 }, 169 [3] = { 170 /* can also do BULK */ 171 .max_in_frame_size = 8, 172 .max_out_frame_size = 8, 173 .is_simplex = 1, 174 .support_interrupt = 1, 175 .support_in = 1, 176 .support_out = 1, 177 }, 178 [4] = { 179 .max_in_frame_size = 256, 180 .max_out_frame_size = 256, 181 .is_simplex = 1, 182 .support_multi_buffer = 1, 183 .support_bulk = 1, 184 .support_interrupt = 1, 185 .support_isochronous = 1, 186 .support_in = 1, 187 .support_out = 1, 188 }, 189 [5] = { 190 .max_in_frame_size = 256, 191 .max_out_frame_size = 256, 192 .is_simplex = 1, 193 .support_multi_buffer = 1, 194 .support_bulk = 1, 195 .support_interrupt = 1, 196 .support_isochronous = 1, 197 .support_in = 1, 198 .support_out = 1, 199 }, 200}; 201 202static void 203at91dci_get_hw_ep_profile(struct usb_device *udev, 204 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 205{ 206 if (ep_addr < AT91_UDP_EP_MAX) { 207 *ppf = (at91dci_ep_profile + ep_addr); 208 } else { 209 *ppf = NULL; 210 } 211} 212 213static void 214at91dci_clocks_on(struct at91dci_softc *sc) 215{ 216 if (sc->sc_flags.clocks_off && 217 sc->sc_flags.port_powered) { 218 219 DPRINTFN(5, "\n"); 220 221 if (sc->sc_clocks_on) { 222 (sc->sc_clocks_on) (sc->sc_clocks_arg); 223 } 224 sc->sc_flags.clocks_off = 0; 225 226 /* enable Transceiver */ 227 AT91_UDP_WRITE_4(sc, AT91_UDP_TXVC, 0); 228 } 229} 230 231static void 232at91dci_clocks_off(struct at91dci_softc *sc) 233{ 234 if (!sc->sc_flags.clocks_off) { 235 236 DPRINTFN(5, "\n"); 237 238 /* disable Transceiver */ 239 AT91_UDP_WRITE_4(sc, AT91_UDP_TXVC, AT91_UDP_TXVC_DIS); 240 241 if (sc->sc_clocks_off) { 242 (sc->sc_clocks_off) (sc->sc_clocks_arg); 243 } 244 sc->sc_flags.clocks_off = 1; 245 } 246} 247 248static void 249at91dci_pull_up(struct at91dci_softc *sc) 250{ 251 /* pullup D+, if possible */ 252 253 if (!sc->sc_flags.d_pulled_up && 254 sc->sc_flags.port_powered) { 255 sc->sc_flags.d_pulled_up = 1; 256 (sc->sc_pull_up) (sc->sc_pull_arg); 257 } 258} 259 260static void 261at91dci_pull_down(struct at91dci_softc *sc) 262{ 263 /* pulldown D+, if possible */ 264 265 if (sc->sc_flags.d_pulled_up) { 266 sc->sc_flags.d_pulled_up = 0; 267 (sc->sc_pull_down) (sc->sc_pull_arg); 268 } 269} 270 271static void 272at91dci_wakeup_peer(struct at91dci_softc *sc) 273{ 274 if (!(sc->sc_flags.status_suspend)) { 275 return; 276 } 277 278 AT91_UDP_WRITE_4(sc, AT91_UDP_GSTATE, AT91_UDP_GSTATE_ESR); 279 280 /* wait 8 milliseconds */ 281 /* Wait for reset to complete. */ 282 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 283 284 AT91_UDP_WRITE_4(sc, AT91_UDP_GSTATE, 0); 285} 286 287static void 288at91dci_set_address(struct at91dci_softc *sc, uint8_t addr) 289{ 290 DPRINTFN(5, "addr=%d\n", addr); 291 292 AT91_UDP_WRITE_4(sc, AT91_UDP_FADDR, addr | 293 AT91_UDP_FADDR_EN); 294} 295 296static uint8_t 297at91dci_setup_rx(struct at91dci_td *td) 298{ 299 struct at91dci_softc *sc; 300 struct usb_device_request req; 301 uint32_t csr; 302 uint32_t temp; 303 uint16_t count; 304 305 /* read out FIFO status */ 306 csr = bus_space_read_4(td->io_tag, td->io_hdl, 307 td->status_reg); 308 309 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder); 310 311 temp = csr; 312 temp &= (AT91_UDP_CSR_RX_DATA_BK0 | 313 AT91_UDP_CSR_RX_DATA_BK1 | 314 AT91_UDP_CSR_STALLSENT | 315 AT91_UDP_CSR_RXSETUP | 316 AT91_UDP_CSR_TXCOMP); 317 318 if (!(csr & AT91_UDP_CSR_RXSETUP)) { 319 goto not_complete; 320 } 321 /* clear did stall */ 322 td->did_stall = 0; 323 324 /* get the packet byte count */ 325 count = (csr & AT91_UDP_CSR_RXBYTECNT) >> 16; 326 327 /* verify data length */ 328 if (count != td->remainder) { 329 DPRINTFN(0, "Invalid SETUP packet " 330 "length, %d bytes\n", count); 331 goto not_complete; 332 } 333 if (count != sizeof(req)) { 334 DPRINTFN(0, "Unsupported SETUP packet " 335 "length, %d bytes\n", count); 336 goto not_complete; 337 } 338 /* receive data */ 339 bus_space_read_multi_1(td->io_tag, td->io_hdl, 340 td->fifo_reg, (void *)&req, sizeof(req)); 341 342 /* copy data into real buffer */ 343 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 344 345 td->offset = sizeof(req); 346 td->remainder = 0; 347 348 /* get pointer to softc */ 349 sc = AT9100_DCI_PC2SC(td->pc); 350 351 /* sneak peek the set address */ 352 if ((req.bmRequestType == UT_WRITE_DEVICE) && 353 (req.bRequest == UR_SET_ADDRESS)) { 354 sc->sc_dv_addr = req.wValue[0] & 0x7F; 355 } else { 356 sc->sc_dv_addr = 0xFF; 357 } 358 359 /* sneak peek the endpoint direction */ 360 if (req.bmRequestType & UE_DIR_IN) { 361 csr |= AT91_UDP_CSR_DIR; 362 } else { 363 csr &= ~AT91_UDP_CSR_DIR; 364 } 365 366 /* write the direction of the control transfer */ 367 AT91_CSR_ACK(csr, temp); 368 bus_space_write_4(td->io_tag, td->io_hdl, 369 td->status_reg, csr); 370 return (0); /* complete */ 371 372not_complete: 373 /* abort any ongoing transfer */ 374 if (!td->did_stall) { 375 DPRINTFN(5, "stalling\n"); 376 temp |= AT91_UDP_CSR_FORCESTALL; 377 td->did_stall = 1; 378 } 379 380 /* clear interrupts, if any */ 381 if (temp) { 382 DPRINTFN(5, "clearing 0x%08x\n", temp); 383 AT91_CSR_ACK(csr, temp); 384 bus_space_write_4(td->io_tag, td->io_hdl, 385 td->status_reg, csr); 386 } 387 return (1); /* not complete */ 388 389} 390 391static uint8_t 392at91dci_data_rx(struct at91dci_td *td) 393{ 394 struct usb_page_search buf_res; 395 uint32_t csr; 396 uint32_t temp; 397 uint16_t count; 398 uint8_t to; 399 uint8_t got_short; 400 401 to = 2; /* don't loop forever! */ 402 got_short = 0; 403 404 /* check if any of the FIFO banks have data */ 405repeat: 406 /* read out FIFO status */ 407 csr = bus_space_read_4(td->io_tag, td->io_hdl, 408 td->status_reg); 409 410 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder); 411 412 if (csr & AT91_UDP_CSR_RXSETUP) { 413 if (td->remainder == 0) { 414 /* 415 * We are actually complete and have 416 * received the next SETUP 417 */ 418 DPRINTFN(5, "faking complete\n"); 419 return (0); /* complete */ 420 } 421 /* 422 * USB Host Aborted the transfer. 423 */ 424 td->error = 1; 425 return (0); /* complete */ 426 } 427 /* Make sure that "STALLSENT" gets cleared */ 428 temp = csr; 429 temp &= AT91_UDP_CSR_STALLSENT; 430 431 /* check status */ 432 if (!(csr & (AT91_UDP_CSR_RX_DATA_BK0 | 433 AT91_UDP_CSR_RX_DATA_BK1))) { 434 if (temp) { 435 /* write command */ 436 AT91_CSR_ACK(csr, temp); 437 bus_space_write_4(td->io_tag, td->io_hdl, 438 td->status_reg, csr); 439 } 440 return (1); /* not complete */ 441 } 442 /* get the packet byte count */ 443 count = (csr & AT91_UDP_CSR_RXBYTECNT) >> 16; 444 445 /* verify the packet byte count */ 446 if (count != td->max_packet_size) { 447 if (count < td->max_packet_size) { 448 /* we have a short packet */ 449 td->short_pkt = 1; 450 got_short = 1; 451 } else { 452 /* invalid USB packet */ 453 td->error = 1; 454 return (0); /* we are complete */ 455 } 456 } 457 /* verify the packet byte count */ 458 if (count > td->remainder) { 459 /* invalid USB packet */ 460 td->error = 1; 461 return (0); /* we are complete */ 462 } 463 while (count > 0) { 464 usbd_get_page(td->pc, td->offset, &buf_res); 465 466 /* get correct length */ 467 if (buf_res.length > count) { 468 buf_res.length = count; 469 } 470 /* receive data */ 471 bus_space_read_multi_1(td->io_tag, td->io_hdl, 472 td->fifo_reg, buf_res.buffer, buf_res.length); 473 474 /* update counters */ 475 count -= buf_res.length; 476 td->offset += buf_res.length; 477 td->remainder -= buf_res.length; 478 } 479 480 /* clear status bits */ 481 if (td->support_multi_buffer) { 482 if (td->fifo_bank) { 483 td->fifo_bank = 0; 484 temp |= AT91_UDP_CSR_RX_DATA_BK1; 485 } else { 486 td->fifo_bank = 1; 487 temp |= AT91_UDP_CSR_RX_DATA_BK0; 488 } 489 } else { 490 temp |= (AT91_UDP_CSR_RX_DATA_BK0 | 491 AT91_UDP_CSR_RX_DATA_BK1); 492 } 493 494 /* write command */ 495 AT91_CSR_ACK(csr, temp); 496 bus_space_write_4(td->io_tag, td->io_hdl, 497 td->status_reg, csr); 498 499 /* 500 * NOTE: We may have to delay a little bit before 501 * proceeding after clearing the DATA_BK bits. 502 */ 503 504 /* check if we are complete */ 505 if ((td->remainder == 0) || got_short) { 506 if (td->short_pkt) { 507 /* we are complete */ 508 return (0); 509 } 510 /* else need to receive a zero length packet */ 511 } 512 if (--to) { 513 goto repeat; 514 } 515 return (1); /* not complete */ 516} 517 518static uint8_t 519at91dci_data_tx(struct at91dci_td *td) 520{ 521 struct usb_page_search buf_res; 522 uint32_t csr; 523 uint32_t temp; 524 uint16_t count; 525 uint8_t to; 526 527 to = 2; /* don't loop forever! */ 528 529repeat: 530 531 /* read out FIFO status */ 532 csr = bus_space_read_4(td->io_tag, td->io_hdl, 533 td->status_reg); 534 535 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder); 536 537 if (csr & AT91_UDP_CSR_RXSETUP) { 538 /* 539 * The current transfer was aborted 540 * by the USB Host 541 */ 542 td->error = 1; 543 return (0); /* complete */ 544 } 545 /* Make sure that "STALLSENT" gets cleared */ 546 temp = csr; 547 temp &= AT91_UDP_CSR_STALLSENT; 548 549 if (csr & AT91_UDP_CSR_TXPKTRDY) { 550 if (temp) { 551 /* write command */ 552 AT91_CSR_ACK(csr, temp); 553 bus_space_write_4(td->io_tag, td->io_hdl, 554 td->status_reg, csr); 555 } 556 return (1); /* not complete */ 557 } else { 558 /* clear TXCOMP and set TXPKTRDY */ 559 temp |= (AT91_UDP_CSR_TXCOMP | 560 AT91_UDP_CSR_TXPKTRDY); 561 } 562 563 count = td->max_packet_size; 564 if (td->remainder < count) { 565 /* we have a short packet */ 566 td->short_pkt = 1; 567 count = td->remainder; 568 } 569 while (count > 0) { 570 571 usbd_get_page(td->pc, td->offset, &buf_res); 572 573 /* get correct length */ 574 if (buf_res.length > count) { 575 buf_res.length = count; 576 } 577 /* transmit data */ 578 bus_space_write_multi_1(td->io_tag, td->io_hdl, 579 td->fifo_reg, buf_res.buffer, buf_res.length); 580 581 /* update counters */ 582 count -= buf_res.length; 583 td->offset += buf_res.length; 584 td->remainder -= buf_res.length; 585 } 586 587 /* write command */ 588 AT91_CSR_ACK(csr, temp); 589 bus_space_write_4(td->io_tag, td->io_hdl, 590 td->status_reg, csr); 591 592 /* check remainder */ 593 if (td->remainder == 0) { 594 if (td->short_pkt) { 595 return (0); /* complete */ 596 } 597 /* else we need to transmit a short packet */ 598 } 599 if (--to) { 600 goto repeat; 601 } 602 return (1); /* not complete */ 603} 604 605static uint8_t 606at91dci_data_tx_sync(struct at91dci_td *td) 607{ 608 struct at91dci_softc *sc; 609 uint32_t csr; 610 uint32_t temp; 611 612#if 0 613repeat: 614#endif 615 616 /* read out FIFO status */ 617 csr = bus_space_read_4(td->io_tag, td->io_hdl, 618 td->status_reg); 619 620 DPRINTFN(5, "csr=0x%08x\n", csr); 621 622 if (csr & AT91_UDP_CSR_RXSETUP) { 623 DPRINTFN(5, "faking complete\n"); 624 /* Race condition */ 625 return (0); /* complete */ 626 } 627 temp = csr; 628 temp &= (AT91_UDP_CSR_STALLSENT | 629 AT91_UDP_CSR_TXCOMP); 630 631 /* check status */ 632 if (csr & AT91_UDP_CSR_TXPKTRDY) { 633 goto not_complete; 634 } 635 if (!(csr & AT91_UDP_CSR_TXCOMP)) { 636 goto not_complete; 637 } 638 sc = AT9100_DCI_PC2SC(td->pc); 639 if (sc->sc_dv_addr != 0xFF) { 640 /* 641 * The AT91 has a special requirement with regard to 642 * setting the address and that is to write the new 643 * address before clearing TXCOMP: 644 */ 645 at91dci_set_address(sc, sc->sc_dv_addr); 646 } 647 /* write command */ 648 AT91_CSR_ACK(csr, temp); 649 bus_space_write_4(td->io_tag, td->io_hdl, 650 td->status_reg, csr); 651 652 return (0); /* complete */ 653 654not_complete: 655 if (temp) { 656 /* write command */ 657 AT91_CSR_ACK(csr, temp); 658 bus_space_write_4(td->io_tag, td->io_hdl, 659 td->status_reg, csr); 660 } 661 return (1); /* not complete */ 662} 663 664static uint8_t 665at91dci_xfer_do_fifo(struct usb_xfer *xfer) 666{ 667 struct at91dci_softc *sc; 668 struct at91dci_td *td; 669 uint8_t temp; 670 671 DPRINTFN(9, "\n"); 672 673 td = xfer->td_transfer_cache; 674 while (1) { 675 if ((td->func) (td)) { 676 /* operation in progress */ 677 break; 678 } 679 if (((void *)td) == xfer->td_transfer_last) { 680 goto done; 681 } 682 if (td->error) { 683 goto done; 684 } else if (td->remainder > 0) { 685 /* 686 * We had a short transfer. If there is no alternate 687 * next, stop processing ! 688 */ 689 if (!td->alt_next) { 690 goto done; 691 } 692 } 693 /* 694 * Fetch the next transfer descriptor and transfer 695 * some flags to the next transfer descriptor 696 */ 697 temp = 0; 698 if (td->fifo_bank) 699 temp |= 1; 700 td = td->obj_next; 701 xfer->td_transfer_cache = td; 702 if (temp & 1) 703 td->fifo_bank = 1; 704 } 705 return (1); /* not complete */ 706 707done: 708 sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 709 temp = (xfer->endpointno & UE_ADDR); 710 711 /* update FIFO bank flag and multi buffer */ 712 if (td->fifo_bank) { 713 sc->sc_ep_flags[temp].fifo_bank = 1; 714 } else { 715 sc->sc_ep_flags[temp].fifo_bank = 0; 716 } 717 718 /* compute all actual lengths */ 719 720 at91dci_standard_done(xfer); 721 722 return (0); /* complete */ 723} 724 725static void 726at91dci_interrupt_poll(struct at91dci_softc *sc) 727{ 728 struct usb_xfer *xfer; 729 730repeat: 731 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 732 if (!at91dci_xfer_do_fifo(xfer)) { 733 /* queue has been modified */ 734 goto repeat; 735 } 736 } 737} 738 739void 740at91dci_vbus_interrupt(struct at91dci_softc *sc, uint8_t is_on) 741{ 742 DPRINTFN(5, "vbus = %u\n", is_on); 743 744 USB_BUS_LOCK(&sc->sc_bus); 745 if (is_on) { 746 if (!sc->sc_flags.status_vbus) { 747 sc->sc_flags.status_vbus = 1; 748 749 /* complete root HUB interrupt endpoint */ 750 at91dci_root_intr(sc); 751 } 752 } else { 753 if (sc->sc_flags.status_vbus) { 754 sc->sc_flags.status_vbus = 0; 755 sc->sc_flags.status_bus_reset = 0; 756 sc->sc_flags.status_suspend = 0; 757 sc->sc_flags.change_suspend = 0; 758 sc->sc_flags.change_connect = 1; 759 760 /* complete root HUB interrupt endpoint */ 761 at91dci_root_intr(sc); 762 } 763 } 764 USB_BUS_UNLOCK(&sc->sc_bus); 765} 766 767void 768at91dci_interrupt(struct at91dci_softc *sc) 769{ 770 uint32_t status; 771 772 USB_BUS_LOCK(&sc->sc_bus); 773 774 status = AT91_UDP_READ_4(sc, AT91_UDP_ISR); 775 status &= AT91_UDP_INT_DEFAULT; 776 777 if (!status) { 778 USB_BUS_UNLOCK(&sc->sc_bus); 779 return; 780 } 781 /* acknowledge interrupts */ 782 783 AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, status); 784 785 /* check for any bus state change interrupts */ 786 787 if (status & AT91_UDP_INT_BUS) { 788 789 DPRINTFN(5, "real bus interrupt 0x%08x\n", status); 790 791 if (status & AT91_UDP_INT_END_BR) { 792 793 /* set correct state */ 794 sc->sc_flags.status_bus_reset = 1; 795 sc->sc_flags.status_suspend = 0; 796 sc->sc_flags.change_suspend = 0; 797 sc->sc_flags.change_connect = 1; 798 799 /* disable resume interrupt */ 800 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 801 AT91_UDP_INT_RXRSM); 802 /* enable suspend interrupt */ 803 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, 804 AT91_UDP_INT_RXSUSP); 805 } 806 /* 807 * If RXRSM and RXSUSP is set at the same time we interpret 808 * that like RESUME. Resume is set when there is at least 3 809 * milliseconds of inactivity on the USB BUS. 810 */ 811 if (status & AT91_UDP_INT_RXRSM) { 812 if (sc->sc_flags.status_suspend) { 813 sc->sc_flags.status_suspend = 0; 814 sc->sc_flags.change_suspend = 1; 815 816 /* disable resume interrupt */ 817 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 818 AT91_UDP_INT_RXRSM); 819 /* enable suspend interrupt */ 820 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, 821 AT91_UDP_INT_RXSUSP); 822 } 823 } else if (status & AT91_UDP_INT_RXSUSP) { 824 if (!sc->sc_flags.status_suspend) { 825 sc->sc_flags.status_suspend = 1; 826 sc->sc_flags.change_suspend = 1; 827 828 /* disable suspend interrupt */ 829 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 830 AT91_UDP_INT_RXSUSP); 831 832 /* enable resume interrupt */ 833 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, 834 AT91_UDP_INT_RXRSM); 835 } 836 } 837 /* complete root HUB interrupt endpoint */ 838 at91dci_root_intr(sc); 839 } 840 /* check for any endpoint interrupts */ 841 842 if (status & AT91_UDP_INT_EPS) { 843 844 DPRINTFN(5, "real endpoint interrupt 0x%08x\n", status); 845 846 at91dci_interrupt_poll(sc); 847 } 848 USB_BUS_UNLOCK(&sc->sc_bus); 849} 850 851static void 852at91dci_setup_standard_chain_sub(struct at91dci_std_temp *temp) 853{ 854 struct at91dci_td *td; 855 856 /* get current Transfer Descriptor */ 857 td = temp->td_next; 858 temp->td = td; 859 860 /* prepare for next TD */ 861 temp->td_next = td->obj_next; 862 863 /* fill out the Transfer Descriptor */ 864 td->func = temp->func; 865 td->pc = temp->pc; 866 td->offset = temp->offset; 867 td->remainder = temp->len; 868 td->fifo_bank = 0; 869 td->error = 0; 870 td->did_stall = temp->did_stall; 871 td->short_pkt = temp->short_pkt; 872 td->alt_next = temp->setup_alt_next; 873} 874 875static void 876at91dci_setup_standard_chain(struct usb_xfer *xfer) 877{ 878 struct at91dci_std_temp temp; 879 struct at91dci_softc *sc; 880 struct at91dci_td *td; 881 uint32_t x; 882 uint8_t ep_no; 883 uint8_t need_sync; 884 885 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 886 xfer->address, UE_GET_ADDR(xfer->endpointno), 887 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 888 889 temp.max_frame_size = xfer->max_frame_size; 890 891 td = xfer->td_start[0]; 892 xfer->td_transfer_first = td; 893 xfer->td_transfer_cache = td; 894 895 /* setup temp */ 896 897 temp.pc = NULL; 898 temp.td = NULL; 899 temp.td_next = xfer->td_start[0]; 900 temp.offset = 0; 901 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 902 temp.did_stall = !xfer->flags_int.control_stall; 903 904 sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 905 ep_no = (xfer->endpointno & UE_ADDR); 906 907 /* check if we should prepend a setup message */ 908 909 if (xfer->flags_int.control_xfr) { 910 if (xfer->flags_int.control_hdr) { 911 912 temp.func = &at91dci_setup_rx; 913 temp.len = xfer->frlengths[0]; 914 temp.pc = xfer->frbuffers + 0; 915 temp.short_pkt = temp.len ? 1 : 0; 916 /* check for last frame */ 917 if (xfer->nframes == 1) { 918 /* no STATUS stage yet, SETUP is last */ 919 if (xfer->flags_int.control_act) 920 temp.setup_alt_next = 0; 921 } 922 923 at91dci_setup_standard_chain_sub(&temp); 924 } 925 x = 1; 926 } else { 927 x = 0; 928 } 929 930 if (x != xfer->nframes) { 931 if (xfer->endpointno & UE_DIR_IN) { 932 temp.func = &at91dci_data_tx; 933 need_sync = 1; 934 } else { 935 temp.func = &at91dci_data_rx; 936 need_sync = 0; 937 } 938 939 /* setup "pc" pointer */ 940 temp.pc = xfer->frbuffers + x; 941 } else { 942 need_sync = 0; 943 } 944 while (x != xfer->nframes) { 945 946 /* DATA0 / DATA1 message */ 947 948 temp.len = xfer->frlengths[x]; 949 950 x++; 951 952 if (x == xfer->nframes) { 953 if (xfer->flags_int.control_xfr) { 954 if (xfer->flags_int.control_act) { 955 temp.setup_alt_next = 0; 956 } 957 } else { 958 temp.setup_alt_next = 0; 959 } 960 } 961 if (temp.len == 0) { 962 963 /* make sure that we send an USB packet */ 964 965 temp.short_pkt = 0; 966 967 } else { 968 969 /* regular data transfer */ 970 971 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 972 } 973 974 at91dci_setup_standard_chain_sub(&temp); 975 976 if (xfer->flags_int.isochronous_xfr) { 977 temp.offset += temp.len; 978 } else { 979 /* get next Page Cache pointer */ 980 temp.pc = xfer->frbuffers + x; 981 } 982 } 983 984 /* check for control transfer */ 985 if (xfer->flags_int.control_xfr) { 986 987 /* always setup a valid "pc" pointer for status and sync */ 988 temp.pc = xfer->frbuffers + 0; 989 temp.len = 0; 990 temp.short_pkt = 0; 991 temp.setup_alt_next = 0; 992 993 /* check if we need to sync */ 994 if (need_sync) { 995 /* we need a SYNC point after TX */ 996 temp.func = &at91dci_data_tx_sync; 997 at91dci_setup_standard_chain_sub(&temp); 998 } 999 1000 /* check if we should append a status stage */ 1001 if (!xfer->flags_int.control_act) { 1002 1003 /* 1004 * Send a DATA1 message and invert the current 1005 * endpoint direction. 1006 */ 1007 if (xfer->endpointno & UE_DIR_IN) { 1008 temp.func = &at91dci_data_rx; 1009 need_sync = 0; 1010 } else { 1011 temp.func = &at91dci_data_tx; 1012 need_sync = 1; 1013 } 1014 1015 at91dci_setup_standard_chain_sub(&temp); 1016 if (need_sync) { 1017 /* we need a SYNC point after TX */ 1018 temp.func = &at91dci_data_tx_sync; 1019 at91dci_setup_standard_chain_sub(&temp); 1020 } 1021 } 1022 } 1023 1024 /* must have at least one frame! */ 1025 td = temp.td; 1026 xfer->td_transfer_last = td; 1027 1028 /* setup the correct fifo bank */ 1029 if (sc->sc_ep_flags[ep_no].fifo_bank) { 1030 td = xfer->td_transfer_first; 1031 td->fifo_bank = 1; 1032 } 1033} 1034 1035static void 1036at91dci_timeout(void *arg) 1037{ 1038 struct usb_xfer *xfer = arg; 1039 1040 DPRINTF("xfer=%p\n", xfer); 1041 1042 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1043 1044 /* transfer is transferred */ 1045 at91dci_device_done(xfer, USB_ERR_TIMEOUT); 1046} 1047 1048static void 1049at91dci_start_standard_chain(struct usb_xfer *xfer) 1050{ 1051 DPRINTFN(9, "\n"); 1052 1053 /* poll one time */ 1054 if (at91dci_xfer_do_fifo(xfer)) { 1055 1056 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 1057 uint8_t ep_no = xfer->endpointno & UE_ADDR; 1058 1059 /* 1060 * Only enable the endpoint interrupt when we are actually 1061 * waiting for data, hence we are dealing with level 1062 * triggered interrupts ! 1063 */ 1064 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, AT91_UDP_INT_EP(ep_no)); 1065 1066 DPRINTFN(15, "enable interrupts on endpoint %d\n", ep_no); 1067 1068 /* put transfer on interrupt queue */ 1069 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 1070 1071 /* start timeout, if any */ 1072 if (xfer->timeout != 0) { 1073 usbd_transfer_timeout_ms(xfer, 1074 &at91dci_timeout, xfer->timeout); 1075 } 1076 } 1077} 1078 1079static void 1080at91dci_root_intr(struct at91dci_softc *sc) 1081{ 1082 DPRINTFN(9, "\n"); 1083 1084 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1085 1086 /* set port bit */ 1087 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 1088 1089 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 1090 sizeof(sc->sc_hub_idata)); 1091} 1092 1093static usb_error_t 1094at91dci_standard_done_sub(struct usb_xfer *xfer) 1095{ 1096 struct at91dci_td *td; 1097 uint32_t len; 1098 uint8_t error; 1099 1100 DPRINTFN(9, "\n"); 1101 1102 td = xfer->td_transfer_cache; 1103 1104 do { 1105 len = td->remainder; 1106 1107 if (xfer->aframes != xfer->nframes) { 1108 /* 1109 * Verify the length and subtract 1110 * the remainder from "frlengths[]": 1111 */ 1112 if (len > xfer->frlengths[xfer->aframes]) { 1113 td->error = 1; 1114 } else { 1115 xfer->frlengths[xfer->aframes] -= len; 1116 } 1117 } 1118 /* Check for transfer error */ 1119 if (td->error) { 1120 /* the transfer is finished */ 1121 error = 1; 1122 td = NULL; 1123 break; 1124 } 1125 /* Check for short transfer */ 1126 if (len > 0) { 1127 if (xfer->flags_int.short_frames_ok) { 1128 /* follow alt next */ 1129 if (td->alt_next) { 1130 td = td->obj_next; 1131 } else { 1132 td = NULL; 1133 } 1134 } else { 1135 /* the transfer is finished */ 1136 td = NULL; 1137 } 1138 error = 0; 1139 break; 1140 } 1141 td = td->obj_next; 1142 1143 /* this USB frame is complete */ 1144 error = 0; 1145 break; 1146 1147 } while (0); 1148 1149 /* update transfer cache */ 1150 1151 xfer->td_transfer_cache = td; 1152 1153 return (error ? 1154 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1155} 1156 1157static void 1158at91dci_standard_done(struct usb_xfer *xfer) 1159{ 1160 usb_error_t err = 0; 1161 1162 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1163 xfer, xfer->endpoint); 1164 1165 /* reset scanner */ 1166 1167 xfer->td_transfer_cache = xfer->td_transfer_first; 1168 1169 if (xfer->flags_int.control_xfr) { 1170 1171 if (xfer->flags_int.control_hdr) { 1172 1173 err = at91dci_standard_done_sub(xfer); 1174 } 1175 xfer->aframes = 1; 1176 1177 if (xfer->td_transfer_cache == NULL) { 1178 goto done; 1179 } 1180 } 1181 while (xfer->aframes != xfer->nframes) { 1182 1183 err = at91dci_standard_done_sub(xfer); 1184 xfer->aframes++; 1185 1186 if (xfer->td_transfer_cache == NULL) { 1187 goto done; 1188 } 1189 } 1190 1191 if (xfer->flags_int.control_xfr && 1192 !xfer->flags_int.control_act) { 1193 1194 err = at91dci_standard_done_sub(xfer); 1195 } 1196done: 1197 at91dci_device_done(xfer, err); 1198} 1199 1200/*------------------------------------------------------------------------* 1201 * at91dci_device_done 1202 * 1203 * NOTE: this function can be called more than one time on the 1204 * same USB transfer! 1205 *------------------------------------------------------------------------*/ 1206static void 1207at91dci_device_done(struct usb_xfer *xfer, usb_error_t error) 1208{ 1209 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 1210 uint8_t ep_no; 1211 1212 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1213 1214 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 1215 xfer, xfer->endpoint, error); 1216 1217 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 1218 ep_no = (xfer->endpointno & UE_ADDR); 1219 1220 /* disable endpoint interrupt */ 1221 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, AT91_UDP_INT_EP(ep_no)); 1222 1223 DPRINTFN(15, "disable interrupts on endpoint %d\n", ep_no); 1224 } 1225 /* dequeue transfer and start next transfer */ 1226 usbd_transfer_done(xfer, error); 1227} 1228 1229static void 1230at91dci_set_stall(struct usb_device *udev, struct usb_xfer *xfer, 1231 struct usb_endpoint *ep, uint8_t *did_stall) 1232{ 1233 struct at91dci_softc *sc; 1234 uint32_t csr_val; 1235 uint8_t csr_reg; 1236 1237 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1238 1239 DPRINTFN(5, "endpoint=%p\n", ep); 1240 1241 if (xfer) { 1242 /* cancel any ongoing transfers */ 1243 at91dci_device_done(xfer, USB_ERR_STALLED); 1244 } 1245 /* set FORCESTALL */ 1246 sc = AT9100_DCI_BUS2SC(udev->bus); 1247 csr_reg = (ep->edesc->bEndpointAddress & UE_ADDR); 1248 csr_reg = AT91_UDP_CSR(csr_reg); 1249 csr_val = AT91_UDP_READ_4(sc, csr_reg); 1250 AT91_CSR_ACK(csr_val, AT91_UDP_CSR_FORCESTALL); 1251 AT91_UDP_WRITE_4(sc, csr_reg, csr_val); 1252} 1253 1254static void 1255at91dci_clear_stall_sub(struct at91dci_softc *sc, uint8_t ep_no, 1256 uint8_t ep_type, uint8_t ep_dir) 1257{ 1258 const struct usb_hw_ep_profile *pf; 1259 uint32_t csr_val; 1260 uint32_t temp; 1261 uint8_t csr_reg; 1262 uint8_t to; 1263 1264 if (ep_type == UE_CONTROL) { 1265 /* clearing stall is not needed */ 1266 return; 1267 } 1268 /* compute CSR register offset */ 1269 csr_reg = AT91_UDP_CSR(ep_no); 1270 1271 /* compute default CSR value */ 1272 csr_val = 0; 1273 AT91_CSR_ACK(csr_val, 0); 1274 1275 /* disable endpoint */ 1276 AT91_UDP_WRITE_4(sc, csr_reg, csr_val); 1277 1278 /* get endpoint profile */ 1279 at91dci_get_hw_ep_profile(NULL, &pf, ep_no); 1280 1281 /* reset FIFO */ 1282 AT91_UDP_WRITE_4(sc, AT91_UDP_RST, AT91_UDP_RST_EP(ep_no)); 1283 AT91_UDP_WRITE_4(sc, AT91_UDP_RST, 0); 1284 1285 /* 1286 * NOTE: One would assume that a FIFO reset would release the 1287 * FIFO banks aswell, but it doesn't! We have to do this 1288 * manually! 1289 */ 1290 1291 /* release FIFO banks, if any */ 1292 for (to = 0; to != 2; to++) { 1293 1294 /* get csr value */ 1295 csr_val = AT91_UDP_READ_4(sc, csr_reg); 1296 1297 if (csr_val & (AT91_UDP_CSR_RX_DATA_BK0 | 1298 AT91_UDP_CSR_RX_DATA_BK1)) { 1299 /* clear status bits */ 1300 if (pf->support_multi_buffer) { 1301 if (sc->sc_ep_flags[ep_no].fifo_bank) { 1302 sc->sc_ep_flags[ep_no].fifo_bank = 0; 1303 temp = AT91_UDP_CSR_RX_DATA_BK1; 1304 } else { 1305 sc->sc_ep_flags[ep_no].fifo_bank = 1; 1306 temp = AT91_UDP_CSR_RX_DATA_BK0; 1307 } 1308 } else { 1309 temp = (AT91_UDP_CSR_RX_DATA_BK0 | 1310 AT91_UDP_CSR_RX_DATA_BK1); 1311 } 1312 } else { 1313 temp = 0; 1314 } 1315 1316 /* clear FORCESTALL */ 1317 temp |= AT91_UDP_CSR_STALLSENT; 1318 1319 AT91_CSR_ACK(csr_val, temp); 1320 AT91_UDP_WRITE_4(sc, csr_reg, csr_val); 1321 } 1322 1323 /* compute default CSR value */ 1324 csr_val = 0; 1325 AT91_CSR_ACK(csr_val, 0); 1326 1327 /* enable endpoint */ 1328 csr_val &= ~AT91_UDP_CSR_ET_MASK; 1329 csr_val |= AT91_UDP_CSR_EPEDS; 1330 1331 if (ep_type == UE_CONTROL) { 1332 csr_val |= AT91_UDP_CSR_ET_CTRL; 1333 } else { 1334 if (ep_type == UE_BULK) { 1335 csr_val |= AT91_UDP_CSR_ET_BULK; 1336 } else if (ep_type == UE_INTERRUPT) { 1337 csr_val |= AT91_UDP_CSR_ET_INT; 1338 } else { 1339 csr_val |= AT91_UDP_CSR_ET_ISO; 1340 } 1341 if (ep_dir & UE_DIR_IN) { 1342 csr_val |= AT91_UDP_CSR_ET_DIR_IN; 1343 } 1344 } 1345 1346 /* enable endpoint */ 1347 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(ep_no), csr_val); 1348} 1349 1350static void 1351at91dci_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 1352{ 1353 struct at91dci_softc *sc; 1354 struct usb_endpoint_descriptor *ed; 1355 1356 DPRINTFN(5, "endpoint=%p\n", ep); 1357 1358 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1359 1360 /* check mode */ 1361 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 1362 /* not supported */ 1363 return; 1364 } 1365 /* get softc */ 1366 sc = AT9100_DCI_BUS2SC(udev->bus); 1367 1368 /* get endpoint descriptor */ 1369 ed = ep->edesc; 1370 1371 /* reset endpoint */ 1372 at91dci_clear_stall_sub(sc, 1373 (ed->bEndpointAddress & UE_ADDR), 1374 (ed->bmAttributes & UE_XFERTYPE), 1375 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1376} 1377 1378usb_error_t 1379at91dci_init(struct at91dci_softc *sc) 1380{ 1381 uint32_t csr_val; 1382 uint8_t n; 1383 1384 DPRINTF("start\n"); 1385 1386 /* set up the bus structure */ 1387 sc->sc_bus.usbrev = USB_REV_1_1; 1388 sc->sc_bus.methods = &at91dci_bus_methods; 1389 1390 USB_BUS_LOCK(&sc->sc_bus); 1391 1392 /* turn on clocks */ 1393 1394 if (sc->sc_clocks_on) { 1395 (sc->sc_clocks_on) (sc->sc_clocks_arg); 1396 } 1397 /* wait a little for things to stabilise */ 1398 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 1399 1400 /* disable and clear all interrupts */ 1401 1402 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 0xFFFFFFFF); 1403 AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, 0xFFFFFFFF); 1404 1405 /* compute default CSR value */ 1406 1407 csr_val = 0; 1408 AT91_CSR_ACK(csr_val, 0); 1409 1410 /* disable all endpoints */ 1411 1412 for (n = 0; n != AT91_UDP_EP_MAX; n++) { 1413 1414 /* disable endpoint */ 1415 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(n), csr_val); 1416 } 1417 1418 /* enable the control endpoint */ 1419 1420 AT91_CSR_ACK(csr_val, AT91_UDP_CSR_ET_CTRL | 1421 AT91_UDP_CSR_EPEDS); 1422 1423 /* write to FIFO control register */ 1424 1425 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(0), csr_val); 1426 1427 /* enable the interrupts we want */ 1428 1429 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, AT91_UDP_INT_BUS); 1430 1431 /* turn off clocks */ 1432 1433 at91dci_clocks_off(sc); 1434 1435 USB_BUS_UNLOCK(&sc->sc_bus); 1436 1437 /* catch any lost interrupts */ 1438 1439 at91dci_do_poll(&sc->sc_bus); 1440 1441 return (0); /* success */ 1442} 1443 1444void 1445at91dci_uninit(struct at91dci_softc *sc) 1446{ 1447 USB_BUS_LOCK(&sc->sc_bus); 1448 1449 /* disable and clear all interrupts */ 1450 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 0xFFFFFFFF); 1451 AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, 0xFFFFFFFF); 1452 1453 sc->sc_flags.port_powered = 0; 1454 sc->sc_flags.status_vbus = 0; 1455 sc->sc_flags.status_bus_reset = 0; 1456 sc->sc_flags.status_suspend = 0; 1457 sc->sc_flags.change_suspend = 0; 1458 sc->sc_flags.change_connect = 1; 1459 1460 at91dci_pull_down(sc); 1461 at91dci_clocks_off(sc); 1462 USB_BUS_UNLOCK(&sc->sc_bus); 1463} 1464 1465void 1466at91dci_suspend(struct at91dci_softc *sc) 1467{ 1468 return; 1469} 1470 1471void 1472at91dci_resume(struct at91dci_softc *sc) 1473{ 1474 return; 1475} 1476 1477static void 1478at91dci_do_poll(struct usb_bus *bus) 1479{ 1480 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(bus); 1481 1482 USB_BUS_LOCK(&sc->sc_bus); 1483 at91dci_interrupt_poll(sc); 1484 USB_BUS_UNLOCK(&sc->sc_bus); 1485} 1486 1487/*------------------------------------------------------------------------* 1488 * at91dci bulk support 1489 *------------------------------------------------------------------------*/ 1490static void 1491at91dci_device_bulk_open(struct usb_xfer *xfer) 1492{ 1493 return; 1494} 1495 1496static void 1497at91dci_device_bulk_close(struct usb_xfer *xfer) 1498{ 1499 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1500} 1501 1502static void 1503at91dci_device_bulk_enter(struct usb_xfer *xfer) 1504{ 1505 return; 1506} 1507 1508static void 1509at91dci_device_bulk_start(struct usb_xfer *xfer) 1510{ 1511 /* setup TDs */ 1512 at91dci_setup_standard_chain(xfer); 1513 at91dci_start_standard_chain(xfer); 1514} 1515 1516struct usb_pipe_methods at91dci_device_bulk_methods = 1517{ 1518 .open = at91dci_device_bulk_open, 1519 .close = at91dci_device_bulk_close, 1520 .enter = at91dci_device_bulk_enter, 1521 .start = at91dci_device_bulk_start, 1522}; 1523 1524/*------------------------------------------------------------------------* 1525 * at91dci control support 1526 *------------------------------------------------------------------------*/ 1527static void 1528at91dci_device_ctrl_open(struct usb_xfer *xfer) 1529{ 1530 return; 1531} 1532 1533static void 1534at91dci_device_ctrl_close(struct usb_xfer *xfer) 1535{ 1536 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1537} 1538 1539static void 1540at91dci_device_ctrl_enter(struct usb_xfer *xfer) 1541{ 1542 return; 1543} 1544 1545static void 1546at91dci_device_ctrl_start(struct usb_xfer *xfer) 1547{ 1548 /* setup TDs */ 1549 at91dci_setup_standard_chain(xfer); 1550 at91dci_start_standard_chain(xfer); 1551} 1552 1553struct usb_pipe_methods at91dci_device_ctrl_methods = 1554{ 1555 .open = at91dci_device_ctrl_open, 1556 .close = at91dci_device_ctrl_close, 1557 .enter = at91dci_device_ctrl_enter, 1558 .start = at91dci_device_ctrl_start, 1559}; 1560 1561/*------------------------------------------------------------------------* 1562 * at91dci interrupt support 1563 *------------------------------------------------------------------------*/ 1564static void 1565at91dci_device_intr_open(struct usb_xfer *xfer) 1566{ 1567 return; 1568} 1569 1570static void 1571at91dci_device_intr_close(struct usb_xfer *xfer) 1572{ 1573 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1574} 1575 1576static void 1577at91dci_device_intr_enter(struct usb_xfer *xfer) 1578{ 1579 return; 1580} 1581 1582static void 1583at91dci_device_intr_start(struct usb_xfer *xfer) 1584{ 1585 /* setup TDs */ 1586 at91dci_setup_standard_chain(xfer); 1587 at91dci_start_standard_chain(xfer); 1588} 1589 1590struct usb_pipe_methods at91dci_device_intr_methods = 1591{ 1592 .open = at91dci_device_intr_open, 1593 .close = at91dci_device_intr_close, 1594 .enter = at91dci_device_intr_enter, 1595 .start = at91dci_device_intr_start, 1596}; 1597 1598/*------------------------------------------------------------------------* 1599 * at91dci full speed isochronous support 1600 *------------------------------------------------------------------------*/ 1601static void 1602at91dci_device_isoc_fs_open(struct usb_xfer *xfer) 1603{ 1604 return; 1605} 1606 1607static void 1608at91dci_device_isoc_fs_close(struct usb_xfer *xfer) 1609{ 1610 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1611} 1612 1613static void 1614at91dci_device_isoc_fs_enter(struct usb_xfer *xfer) 1615{ 1616 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 1617 uint32_t temp; 1618 uint32_t nframes; 1619 1620 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 1621 xfer, xfer->endpoint->isoc_next, xfer->nframes); 1622 1623 /* get the current frame index */ 1624 1625 nframes = AT91_UDP_READ_4(sc, AT91_UDP_FRM); 1626 1627 /* 1628 * check if the frame index is within the window where the frames 1629 * will be inserted 1630 */ 1631 temp = (nframes - xfer->endpoint->isoc_next) & AT91_UDP_FRM_MASK; 1632 1633 if ((xfer->endpoint->is_synced == 0) || 1634 (temp < xfer->nframes)) { 1635 /* 1636 * If there is data underflow or the endpoint queue is 1637 * empty we schedule the transfer a few frames ahead 1638 * of the current frame position. Else two isochronous 1639 * transfers might overlap. 1640 */ 1641 xfer->endpoint->isoc_next = (nframes + 3) & AT91_UDP_FRM_MASK; 1642 xfer->endpoint->is_synced = 1; 1643 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 1644 } 1645 /* 1646 * compute how many milliseconds the insertion is ahead of the 1647 * current frame position: 1648 */ 1649 temp = (xfer->endpoint->isoc_next - nframes) & AT91_UDP_FRM_MASK; 1650 1651 /* 1652 * pre-compute when the isochronous transfer will be finished: 1653 */ 1654 xfer->isoc_time_complete = 1655 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp + 1656 xfer->nframes; 1657 1658 /* compute frame number for next insertion */ 1659 xfer->endpoint->isoc_next += xfer->nframes; 1660 1661 /* setup TDs */ 1662 at91dci_setup_standard_chain(xfer); 1663} 1664 1665static void 1666at91dci_device_isoc_fs_start(struct usb_xfer *xfer) 1667{ 1668 /* start TD chain */ 1669 at91dci_start_standard_chain(xfer); 1670} 1671 1672struct usb_pipe_methods at91dci_device_isoc_fs_methods = 1673{ 1674 .open = at91dci_device_isoc_fs_open, 1675 .close = at91dci_device_isoc_fs_close, 1676 .enter = at91dci_device_isoc_fs_enter, 1677 .start = at91dci_device_isoc_fs_start, 1678}; 1679 1680/*------------------------------------------------------------------------* 1681 * at91dci root control support 1682 *------------------------------------------------------------------------* 1683 * Simulate a hardware HUB by handling all the necessary requests. 1684 *------------------------------------------------------------------------*/ 1685 1686static const struct usb_device_descriptor at91dci_devd = { 1687 .bLength = sizeof(struct usb_device_descriptor), 1688 .bDescriptorType = UDESC_DEVICE, 1689 .bcdUSB = {0x00, 0x02}, 1690 .bDeviceClass = UDCLASS_HUB, 1691 .bDeviceSubClass = UDSUBCLASS_HUB, 1692 .bDeviceProtocol = UDPROTO_FSHUB, 1693 .bMaxPacketSize = 64, 1694 .bcdDevice = {0x00, 0x01}, 1695 .iManufacturer = 1, 1696 .iProduct = 2, 1697 .bNumConfigurations = 1, 1698}; 1699 1700static const struct at91dci_config_desc at91dci_confd = { 1701 .confd = { 1702 .bLength = sizeof(struct usb_config_descriptor), 1703 .bDescriptorType = UDESC_CONFIG, 1704 .wTotalLength[0] = sizeof(at91dci_confd), 1705 .bNumInterface = 1, 1706 .bConfigurationValue = 1, 1707 .iConfiguration = 0, 1708 .bmAttributes = UC_SELF_POWERED, 1709 .bMaxPower = 0, 1710 }, 1711 .ifcd = { 1712 .bLength = sizeof(struct usb_interface_descriptor), 1713 .bDescriptorType = UDESC_INTERFACE, 1714 .bNumEndpoints = 1, 1715 .bInterfaceClass = UICLASS_HUB, 1716 .bInterfaceSubClass = UISUBCLASS_HUB, 1717 .bInterfaceProtocol = 0, 1718 }, 1719 .endpd = { 1720 .bLength = sizeof(struct usb_endpoint_descriptor), 1721 .bDescriptorType = UDESC_ENDPOINT, 1722 .bEndpointAddress = (UE_DIR_IN | AT9100_DCI_INTR_ENDPT), 1723 .bmAttributes = UE_INTERRUPT, 1724 .wMaxPacketSize[0] = 8, 1725 .bInterval = 255, 1726 }, 1727}; 1728 1729static const struct usb_hub_descriptor_min at91dci_hubd = { 1730 .bDescLength = sizeof(at91dci_hubd), 1731 .bDescriptorType = UDESC_HUB, 1732 .bNbrPorts = 1, 1733 .wHubCharacteristics[0] = 1734 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) & 0xFF, 1735 .wHubCharacteristics[1] = 1736 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) >> 8, 1737 .bPwrOn2PwrGood = 50, 1738 .bHubContrCurrent = 0, 1739 .DeviceRemovable = {0}, /* port is removable */ 1740}; 1741 1742#define STRING_LANG \ 1743 0x09, 0x04, /* American English */ 1744 1745#define STRING_VENDOR \ 1746 'A', 0, 'T', 0, 'M', 0, 'E', 0, 'L', 0 1747 1748#define STRING_PRODUCT \ 1749 'D', 0, 'C', 0, 'I', 0, ' ', 0, 'R', 0, \ 1750 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \ 1751 'U', 0, 'B', 0, 1752 1753USB_MAKE_STRING_DESC(STRING_LANG, at91dci_langtab); 1754USB_MAKE_STRING_DESC(STRING_VENDOR, at91dci_vendor); 1755USB_MAKE_STRING_DESC(STRING_PRODUCT, at91dci_product); 1756 1757static usb_error_t 1758at91dci_roothub_exec(struct usb_device *udev, 1759 struct usb_device_request *req, const void **pptr, uint16_t *plength) 1760{ 1761 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(udev->bus); 1762 const void *ptr; 1763 uint16_t len; 1764 uint16_t value; 1765 uint16_t index; 1766 usb_error_t err; 1767 1768 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1769 1770 /* buffer reset */ 1771 ptr = (const void *)&sc->sc_hub_temp; 1772 len = 0; 1773 err = 0; 1774 1775 value = UGETW(req->wValue); 1776 index = UGETW(req->wIndex); 1777 1778 /* demultiplex the control request */ 1779 1780 switch (req->bmRequestType) { 1781 case UT_READ_DEVICE: 1782 switch (req->bRequest) { 1783 case UR_GET_DESCRIPTOR: 1784 goto tr_handle_get_descriptor; 1785 case UR_GET_CONFIG: 1786 goto tr_handle_get_config; 1787 case UR_GET_STATUS: 1788 goto tr_handle_get_status; 1789 default: 1790 goto tr_stalled; 1791 } 1792 break; 1793 1794 case UT_WRITE_DEVICE: 1795 switch (req->bRequest) { 1796 case UR_SET_ADDRESS: 1797 goto tr_handle_set_address; 1798 case UR_SET_CONFIG: 1799 goto tr_handle_set_config; 1800 case UR_CLEAR_FEATURE: 1801 goto tr_valid; /* nop */ 1802 case UR_SET_DESCRIPTOR: 1803 goto tr_valid; /* nop */ 1804 case UR_SET_FEATURE: 1805 default: 1806 goto tr_stalled; 1807 } 1808 break; 1809 1810 case UT_WRITE_ENDPOINT: 1811 switch (req->bRequest) { 1812 case UR_CLEAR_FEATURE: 1813 switch (UGETW(req->wValue)) { 1814 case UF_ENDPOINT_HALT: 1815 goto tr_handle_clear_halt; 1816 case UF_DEVICE_REMOTE_WAKEUP: 1817 goto tr_handle_clear_wakeup; 1818 default: 1819 goto tr_stalled; 1820 } 1821 break; 1822 case UR_SET_FEATURE: 1823 switch (UGETW(req->wValue)) { 1824 case UF_ENDPOINT_HALT: 1825 goto tr_handle_set_halt; 1826 case UF_DEVICE_REMOTE_WAKEUP: 1827 goto tr_handle_set_wakeup; 1828 default: 1829 goto tr_stalled; 1830 } 1831 break; 1832 case UR_SYNCH_FRAME: 1833 goto tr_valid; /* nop */ 1834 default: 1835 goto tr_stalled; 1836 } 1837 break; 1838 1839 case UT_READ_ENDPOINT: 1840 switch (req->bRequest) { 1841 case UR_GET_STATUS: 1842 goto tr_handle_get_ep_status; 1843 default: 1844 goto tr_stalled; 1845 } 1846 break; 1847 1848 case UT_WRITE_INTERFACE: 1849 switch (req->bRequest) { 1850 case UR_SET_INTERFACE: 1851 goto tr_handle_set_interface; 1852 case UR_CLEAR_FEATURE: 1853 goto tr_valid; /* nop */ 1854 case UR_SET_FEATURE: 1855 default: 1856 goto tr_stalled; 1857 } 1858 break; 1859 1860 case UT_READ_INTERFACE: 1861 switch (req->bRequest) { 1862 case UR_GET_INTERFACE: 1863 goto tr_handle_get_interface; 1864 case UR_GET_STATUS: 1865 goto tr_handle_get_iface_status; 1866 default: 1867 goto tr_stalled; 1868 } 1869 break; 1870 1871 case UT_WRITE_CLASS_INTERFACE: 1872 case UT_WRITE_VENDOR_INTERFACE: 1873 /* XXX forward */ 1874 break; 1875 1876 case UT_READ_CLASS_INTERFACE: 1877 case UT_READ_VENDOR_INTERFACE: 1878 /* XXX forward */ 1879 break; 1880 1881 case UT_WRITE_CLASS_DEVICE: 1882 switch (req->bRequest) { 1883 case UR_CLEAR_FEATURE: 1884 goto tr_valid; 1885 case UR_SET_DESCRIPTOR: 1886 case UR_SET_FEATURE: 1887 break; 1888 default: 1889 goto tr_stalled; 1890 } 1891 break; 1892 1893 case UT_WRITE_CLASS_OTHER: 1894 switch (req->bRequest) { 1895 case UR_CLEAR_FEATURE: 1896 goto tr_handle_clear_port_feature; 1897 case UR_SET_FEATURE: 1898 goto tr_handle_set_port_feature; 1899 case UR_CLEAR_TT_BUFFER: 1900 case UR_RESET_TT: 1901 case UR_STOP_TT: 1902 goto tr_valid; 1903 1904 default: 1905 goto tr_stalled; 1906 } 1907 break; 1908 1909 case UT_READ_CLASS_OTHER: 1910 switch (req->bRequest) { 1911 case UR_GET_TT_STATE: 1912 goto tr_handle_get_tt_state; 1913 case UR_GET_STATUS: 1914 goto tr_handle_get_port_status; 1915 default: 1916 goto tr_stalled; 1917 } 1918 break; 1919 1920 case UT_READ_CLASS_DEVICE: 1921 switch (req->bRequest) { 1922 case UR_GET_DESCRIPTOR: 1923 goto tr_handle_get_class_descriptor; 1924 case UR_GET_STATUS: 1925 goto tr_handle_get_class_status; 1926 1927 default: 1928 goto tr_stalled; 1929 } 1930 break; 1931 default: 1932 goto tr_stalled; 1933 } 1934 goto tr_valid; 1935 1936tr_handle_get_descriptor: 1937 switch (value >> 8) { 1938 case UDESC_DEVICE: 1939 if (value & 0xff) { 1940 goto tr_stalled; 1941 } 1942 len = sizeof(at91dci_devd); 1943 ptr = (const void *)&at91dci_devd; 1944 goto tr_valid; 1945 case UDESC_CONFIG: 1946 if (value & 0xff) { 1947 goto tr_stalled; 1948 } 1949 len = sizeof(at91dci_confd); 1950 ptr = (const void *)&at91dci_confd; 1951 goto tr_valid; 1952 case UDESC_STRING: 1953 switch (value & 0xff) { 1954 case 0: /* Language table */ 1955 len = sizeof(at91dci_langtab); 1956 ptr = (const void *)&at91dci_langtab; 1957 goto tr_valid; 1958 1959 case 1: /* Vendor */ 1960 len = sizeof(at91dci_vendor); 1961 ptr = (const void *)&at91dci_vendor; 1962 goto tr_valid; 1963 1964 case 2: /* Product */ 1965 len = sizeof(at91dci_product); 1966 ptr = (const void *)&at91dci_product; 1967 goto tr_valid; 1968 default: 1969 break; 1970 } 1971 break; 1972 default: 1973 goto tr_stalled; 1974 } 1975 goto tr_stalled; 1976 1977tr_handle_get_config: 1978 len = 1; 1979 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 1980 goto tr_valid; 1981 1982tr_handle_get_status: 1983 len = 2; 1984 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 1985 goto tr_valid; 1986 1987tr_handle_set_address: 1988 if (value & 0xFF00) { 1989 goto tr_stalled; 1990 } 1991 sc->sc_rt_addr = value; 1992 goto tr_valid; 1993 1994tr_handle_set_config: 1995 if (value >= 2) { 1996 goto tr_stalled; 1997 } 1998 sc->sc_conf = value; 1999 goto tr_valid; 2000 2001tr_handle_get_interface: 2002 len = 1; 2003 sc->sc_hub_temp.wValue[0] = 0; 2004 goto tr_valid; 2005 2006tr_handle_get_tt_state: 2007tr_handle_get_class_status: 2008tr_handle_get_iface_status: 2009tr_handle_get_ep_status: 2010 len = 2; 2011 USETW(sc->sc_hub_temp.wValue, 0); 2012 goto tr_valid; 2013 2014tr_handle_set_halt: 2015tr_handle_set_interface: 2016tr_handle_set_wakeup: 2017tr_handle_clear_wakeup: 2018tr_handle_clear_halt: 2019 goto tr_valid; 2020 2021tr_handle_clear_port_feature: 2022 if (index != 1) { 2023 goto tr_stalled; 2024 } 2025 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 2026 2027 switch (value) { 2028 case UHF_PORT_SUSPEND: 2029 at91dci_wakeup_peer(sc); 2030 break; 2031 2032 case UHF_PORT_ENABLE: 2033 sc->sc_flags.port_enabled = 0; 2034 break; 2035 2036 case UHF_PORT_TEST: 2037 case UHF_PORT_INDICATOR: 2038 case UHF_C_PORT_ENABLE: 2039 case UHF_C_PORT_OVER_CURRENT: 2040 case UHF_C_PORT_RESET: 2041 /* nops */ 2042 break; 2043 case UHF_PORT_POWER: 2044 sc->sc_flags.port_powered = 0; 2045 at91dci_pull_down(sc); 2046 at91dci_clocks_off(sc); 2047 break; 2048 case UHF_C_PORT_CONNECTION: 2049 sc->sc_flags.change_connect = 0; 2050 break; 2051 case UHF_C_PORT_SUSPEND: 2052 sc->sc_flags.change_suspend = 0; 2053 break; 2054 default: 2055 err = USB_ERR_IOERROR; 2056 goto done; 2057 } 2058 goto tr_valid; 2059 2060tr_handle_set_port_feature: 2061 if (index != 1) { 2062 goto tr_stalled; 2063 } 2064 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 2065 2066 switch (value) { 2067 case UHF_PORT_ENABLE: 2068 sc->sc_flags.port_enabled = 1; 2069 break; 2070 case UHF_PORT_SUSPEND: 2071 case UHF_PORT_RESET: 2072 case UHF_PORT_TEST: 2073 case UHF_PORT_INDICATOR: 2074 /* nops */ 2075 break; 2076 case UHF_PORT_POWER: 2077 sc->sc_flags.port_powered = 1; 2078 break; 2079 default: 2080 err = USB_ERR_IOERROR; 2081 goto done; 2082 } 2083 goto tr_valid; 2084 2085tr_handle_get_port_status: 2086 2087 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 2088 2089 if (index != 1) { 2090 goto tr_stalled; 2091 } 2092 if (sc->sc_flags.status_vbus) { 2093 at91dci_clocks_on(sc); 2094 at91dci_pull_up(sc); 2095 } else { 2096 at91dci_pull_down(sc); 2097 at91dci_clocks_off(sc); 2098 } 2099 2100 /* Select FULL-speed and Device Side Mode */ 2101 2102 value = UPS_PORT_MODE_DEVICE; 2103 2104 if (sc->sc_flags.port_powered) { 2105 value |= UPS_PORT_POWER; 2106 } 2107 if (sc->sc_flags.port_enabled) { 2108 value |= UPS_PORT_ENABLED; 2109 } 2110 if (sc->sc_flags.status_vbus && 2111 sc->sc_flags.status_bus_reset) { 2112 value |= UPS_CURRENT_CONNECT_STATUS; 2113 } 2114 if (sc->sc_flags.status_suspend) { 2115 value |= UPS_SUSPEND; 2116 } 2117 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 2118 2119 value = 0; 2120 2121 if (sc->sc_flags.change_connect) { 2122 value |= UPS_C_CONNECT_STATUS; 2123 2124 if (sc->sc_flags.status_vbus && 2125 sc->sc_flags.status_bus_reset) { 2126 /* reset endpoint flags */ 2127 bzero(sc->sc_ep_flags, sizeof(sc->sc_ep_flags)); 2128 } 2129 } 2130 if (sc->sc_flags.change_suspend) { 2131 value |= UPS_C_SUSPEND; 2132 } 2133 USETW(sc->sc_hub_temp.ps.wPortChange, value); 2134 len = sizeof(sc->sc_hub_temp.ps); 2135 goto tr_valid; 2136 2137tr_handle_get_class_descriptor: 2138 if (value & 0xFF) { 2139 goto tr_stalled; 2140 } 2141 ptr = (const void *)&at91dci_hubd; 2142 len = sizeof(at91dci_hubd); 2143 goto tr_valid; 2144 2145tr_stalled: 2146 err = USB_ERR_STALLED; 2147tr_valid: 2148done: 2149 *plength = len; 2150 *pptr = ptr; 2151 return (err); 2152} 2153 2154static void 2155at91dci_xfer_setup(struct usb_setup_params *parm) 2156{ 2157 const struct usb_hw_ep_profile *pf; 2158 struct at91dci_softc *sc; 2159 struct usb_xfer *xfer; 2160 void *last_obj; 2161 uint32_t ntd; 2162 uint32_t n; 2163 uint8_t ep_no; 2164 2165 sc = AT9100_DCI_BUS2SC(parm->udev->bus); 2166 xfer = parm->curr_xfer; 2167 2168 /* 2169 * NOTE: This driver does not use any of the parameters that 2170 * are computed from the following values. Just set some 2171 * reasonable dummies: 2172 */ 2173 parm->hc_max_packet_size = 0x500; 2174 parm->hc_max_packet_count = 1; 2175 parm->hc_max_frame_size = 0x500; 2176 2177 usbd_transfer_setup_sub(parm); 2178 2179 /* 2180 * compute maximum number of TDs 2181 */ 2182 if (parm->methods == &at91dci_device_ctrl_methods) { 2183 2184 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 2185 + 1 /* SYNC 2 */ ; 2186 2187 } else if (parm->methods == &at91dci_device_bulk_methods) { 2188 2189 ntd = xfer->nframes + 1 /* SYNC */ ; 2190 2191 } else if (parm->methods == &at91dci_device_intr_methods) { 2192 2193 ntd = xfer->nframes + 1 /* SYNC */ ; 2194 2195 } else if (parm->methods == &at91dci_device_isoc_fs_methods) { 2196 2197 ntd = xfer->nframes + 1 /* SYNC */ ; 2198 2199 } else { 2200 2201 ntd = 0; 2202 } 2203 2204 /* 2205 * check if "usbd_transfer_setup_sub" set an error 2206 */ 2207 if (parm->err) { 2208 return; 2209 } 2210 /* 2211 * allocate transfer descriptors 2212 */ 2213 last_obj = NULL; 2214 2215 /* 2216 * get profile stuff 2217 */ 2218 if (ntd) { 2219 2220 ep_no = xfer->endpointno & UE_ADDR; 2221 at91dci_get_hw_ep_profile(parm->udev, &pf, ep_no); 2222 2223 if (pf == NULL) { 2224 /* should not happen */ 2225 parm->err = USB_ERR_INVAL; 2226 return; 2227 } 2228 } else { 2229 ep_no = 0; 2230 pf = NULL; 2231 } 2232 2233 /* align data */ 2234 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2235 2236 for (n = 0; n != ntd; n++) { 2237 2238 struct at91dci_td *td; 2239 2240 if (parm->buf) { 2241 2242 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2243 2244 /* init TD */ 2245 td->io_tag = sc->sc_io_tag; 2246 td->io_hdl = sc->sc_io_hdl; 2247 td->max_packet_size = xfer->max_packet_size; 2248 td->status_reg = AT91_UDP_CSR(ep_no); 2249 td->fifo_reg = AT91_UDP_FDR(ep_no); 2250 if (pf->support_multi_buffer) { 2251 td->support_multi_buffer = 1; 2252 } 2253 td->obj_next = last_obj; 2254 2255 last_obj = td; 2256 } 2257 parm->size[0] += sizeof(*td); 2258 } 2259 2260 xfer->td_start[0] = last_obj; 2261} 2262 2263static void 2264at91dci_xfer_unsetup(struct usb_xfer *xfer) 2265{ 2266 return; 2267} 2268 2269static void 2270at91dci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 2271 struct usb_endpoint *ep) 2272{ 2273 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(udev->bus); 2274 2275 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 2276 ep, udev->address, 2277 edesc->bEndpointAddress, udev->flags.usb_mode, 2278 sc->sc_rt_addr); 2279 2280 if (udev->device_index != sc->sc_rt_addr) { 2281 2282 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 2283 /* not supported */ 2284 return; 2285 } 2286 if (udev->speed != USB_SPEED_FULL) { 2287 /* not supported */ 2288 return; 2289 } 2290 switch (edesc->bmAttributes & UE_XFERTYPE) { 2291 case UE_CONTROL: 2292 ep->methods = &at91dci_device_ctrl_methods; 2293 break; 2294 case UE_INTERRUPT: 2295 ep->methods = &at91dci_device_intr_methods; 2296 break; 2297 case UE_ISOCHRONOUS: 2298 ep->methods = &at91dci_device_isoc_fs_methods; 2299 break; 2300 case UE_BULK: 2301 ep->methods = &at91dci_device_bulk_methods; 2302 break; 2303 default: 2304 /* do nothing */ 2305 break; 2306 } 2307 } 2308} 2309 2310struct usb_bus_methods at91dci_bus_methods = 2311{ 2312 .endpoint_init = &at91dci_ep_init, 2313 .xfer_setup = &at91dci_xfer_setup, 2314 .xfer_unsetup = &at91dci_xfer_unsetup, 2315 .get_hw_ep_profile = &at91dci_get_hw_ep_profile, 2316 .set_stall = &at91dci_set_stall, 2317 .clear_stall = &at91dci_clear_stall, 2318 .roothub_exec = &at91dci_roothub_exec, 2319 .xfer_poll = &at91dci_do_poll, 2320}; 2321