at91dci.c revision 193045
1#include <sys/cdefs.h> 2__FBSDID("$FreeBSD: head/sys/dev/usb/controller/at91dci.c 193045 2009-05-29 18:46:57Z thompsa $"); 3 4/*- 5 * Copyright (c) 2007-2008 Hans Petter Selasky. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * This file contains the driver for the AT91 series USB Device 31 * Controller 32 */ 33 34/* 35 * Thanks to "David Brownell" for helping out regarding the hardware 36 * endpoint profiles. 37 */ 38 39/* 40 * NOTE: The "fifo_bank" is not reset in hardware when the endpoint is 41 * reset. 42 * 43 * NOTE: When the chip detects BUS-reset it will also reset the 44 * endpoints, Function-address and more. 45 */ 46 47#include <dev/usb/usb.h> 48#include <dev/usb/usb_mfunc.h> 49#include <dev/usb/usb_error.h> 50 51#define USB_DEBUG_VAR at91dcidebug 52 53#include <dev/usb/usb_core.h> 54#include <dev/usb/usb_debug.h> 55#include <dev/usb/usb_busdma.h> 56#include <dev/usb/usb_process.h> 57#include <dev/usb/usb_transfer.h> 58#include <dev/usb/usb_device.h> 59#include <dev/usb/usb_hub.h> 60#include <dev/usb/usb_util.h> 61 62#include <dev/usb/usb_controller.h> 63#include <dev/usb/usb_bus.h> 64#include <dev/usb/controller/at91dci.h> 65 66#define AT9100_DCI_BUS2SC(bus) \ 67 ((struct at91dci_softc *)(((uint8_t *)(bus)) - \ 68 ((uint8_t *)&(((struct at91dci_softc *)0)->sc_bus)))) 69 70#define AT9100_DCI_PC2SC(pc) \ 71 AT9100_DCI_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 72 73#if USB_DEBUG 74static int at91dcidebug = 0; 75 76SYSCTL_NODE(_hw_usb, OID_AUTO, at91dci, CTLFLAG_RW, 0, "USB at91dci"); 77SYSCTL_INT(_hw_usb_at91dci, OID_AUTO, debug, CTLFLAG_RW, 78 &at91dcidebug, 0, "at91dci debug level"); 79#endif 80 81#define AT9100_DCI_INTR_ENDPT 1 82 83/* prototypes */ 84 85struct usb_bus_methods at91dci_bus_methods; 86struct usb_pipe_methods at91dci_device_bulk_methods; 87struct usb_pipe_methods at91dci_device_ctrl_methods; 88struct usb_pipe_methods at91dci_device_intr_methods; 89struct usb_pipe_methods at91dci_device_isoc_fs_methods; 90 91static at91dci_cmd_t at91dci_setup_rx; 92static at91dci_cmd_t at91dci_data_rx; 93static at91dci_cmd_t at91dci_data_tx; 94static at91dci_cmd_t at91dci_data_tx_sync; 95static void at91dci_device_done(struct usb_xfer *, usb_error_t); 96static void at91dci_do_poll(struct usb_bus *); 97static void at91dci_standard_done(struct usb_xfer *); 98static void at91dci_root_intr(struct at91dci_softc *sc); 99 100/* 101 * NOTE: Some of the bits in the CSR register have inverse meaning so 102 * we need a helper macro when acknowledging events: 103 */ 104#define AT91_CSR_ACK(csr, what) do { \ 105 (csr) &= ~((AT91_UDP_CSR_FORCESTALL| \ 106 AT91_UDP_CSR_TXPKTRDY| \ 107 AT91_UDP_CSR_RXBYTECNT) ^ (what));\ 108 (csr) |= ((AT91_UDP_CSR_RX_DATA_BK0| \ 109 AT91_UDP_CSR_RX_DATA_BK1| \ 110 AT91_UDP_CSR_TXCOMP| \ 111 AT91_UDP_CSR_RXSETUP| \ 112 AT91_UDP_CSR_STALLSENT) ^ (what)); \ 113} while (0) 114 115/* 116 * Here is a list of what the chip supports. 117 * Probably it supports more than listed here! 118 */ 119static const struct usb_hw_ep_profile 120 at91dci_ep_profile[AT91_UDP_EP_MAX] = { 121 122 [0] = { 123 .max_in_frame_size = 8, 124 .max_out_frame_size = 8, 125 .is_simplex = 1, 126 .support_control = 1, 127 }, 128 [1] = { 129 .max_in_frame_size = 64, 130 .max_out_frame_size = 64, 131 .is_simplex = 1, 132 .support_multi_buffer = 1, 133 .support_bulk = 1, 134 .support_interrupt = 1, 135 .support_isochronous = 1, 136 .support_in = 1, 137 .support_out = 1, 138 }, 139 [2] = { 140 .max_in_frame_size = 64, 141 .max_out_frame_size = 64, 142 .is_simplex = 1, 143 .support_multi_buffer = 1, 144 .support_bulk = 1, 145 .support_interrupt = 1, 146 .support_isochronous = 1, 147 .support_in = 1, 148 .support_out = 1, 149 }, 150 [3] = { 151 /* can also do BULK */ 152 .max_in_frame_size = 8, 153 .max_out_frame_size = 8, 154 .is_simplex = 1, 155 .support_interrupt = 1, 156 .support_in = 1, 157 .support_out = 1, 158 }, 159 [4] = { 160 .max_in_frame_size = 256, 161 .max_out_frame_size = 256, 162 .is_simplex = 1, 163 .support_multi_buffer = 1, 164 .support_bulk = 1, 165 .support_interrupt = 1, 166 .support_isochronous = 1, 167 .support_in = 1, 168 .support_out = 1, 169 }, 170 [5] = { 171 .max_in_frame_size = 256, 172 .max_out_frame_size = 256, 173 .is_simplex = 1, 174 .support_multi_buffer = 1, 175 .support_bulk = 1, 176 .support_interrupt = 1, 177 .support_isochronous = 1, 178 .support_in = 1, 179 .support_out = 1, 180 }, 181}; 182 183static void 184at91dci_get_hw_ep_profile(struct usb_device *udev, 185 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 186{ 187 if (ep_addr < AT91_UDP_EP_MAX) { 188 *ppf = (at91dci_ep_profile + ep_addr); 189 } else { 190 *ppf = NULL; 191 } 192} 193 194static void 195at91dci_clocks_on(struct at91dci_softc *sc) 196{ 197 if (sc->sc_flags.clocks_off && 198 sc->sc_flags.port_powered) { 199 200 DPRINTFN(5, "\n"); 201 202 if (sc->sc_clocks_on) { 203 (sc->sc_clocks_on) (sc->sc_clocks_arg); 204 } 205 sc->sc_flags.clocks_off = 0; 206 207 /* enable Transceiver */ 208 AT91_UDP_WRITE_4(sc, AT91_UDP_TXVC, 0); 209 } 210} 211 212static void 213at91dci_clocks_off(struct at91dci_softc *sc) 214{ 215 if (!sc->sc_flags.clocks_off) { 216 217 DPRINTFN(5, "\n"); 218 219 /* disable Transceiver */ 220 AT91_UDP_WRITE_4(sc, AT91_UDP_TXVC, AT91_UDP_TXVC_DIS); 221 222 if (sc->sc_clocks_off) { 223 (sc->sc_clocks_off) (sc->sc_clocks_arg); 224 } 225 sc->sc_flags.clocks_off = 1; 226 } 227} 228 229static void 230at91dci_pull_up(struct at91dci_softc *sc) 231{ 232 /* pullup D+, if possible */ 233 234 if (!sc->sc_flags.d_pulled_up && 235 sc->sc_flags.port_powered) { 236 sc->sc_flags.d_pulled_up = 1; 237 (sc->sc_pull_up) (sc->sc_pull_arg); 238 } 239} 240 241static void 242at91dci_pull_down(struct at91dci_softc *sc) 243{ 244 /* pulldown D+, if possible */ 245 246 if (sc->sc_flags.d_pulled_up) { 247 sc->sc_flags.d_pulled_up = 0; 248 (sc->sc_pull_down) (sc->sc_pull_arg); 249 } 250} 251 252static void 253at91dci_wakeup_peer(struct at91dci_softc *sc) 254{ 255 if (!(sc->sc_flags.status_suspend)) { 256 return; 257 } 258 259 AT91_UDP_WRITE_4(sc, AT91_UDP_GSTATE, AT91_UDP_GSTATE_ESR); 260 261 /* wait 8 milliseconds */ 262 /* Wait for reset to complete. */ 263 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 264 265 AT91_UDP_WRITE_4(sc, AT91_UDP_GSTATE, 0); 266} 267 268static void 269at91dci_set_address(struct at91dci_softc *sc, uint8_t addr) 270{ 271 DPRINTFN(5, "addr=%d\n", addr); 272 273 AT91_UDP_WRITE_4(sc, AT91_UDP_FADDR, addr | 274 AT91_UDP_FADDR_EN); 275} 276 277static uint8_t 278at91dci_setup_rx(struct at91dci_td *td) 279{ 280 struct at91dci_softc *sc; 281 struct usb_device_request req; 282 uint32_t csr; 283 uint32_t temp; 284 uint16_t count; 285 286 /* read out FIFO status */ 287 csr = bus_space_read_4(td->io_tag, td->io_hdl, 288 td->status_reg); 289 290 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder); 291 292 temp = csr; 293 temp &= (AT91_UDP_CSR_RX_DATA_BK0 | 294 AT91_UDP_CSR_RX_DATA_BK1 | 295 AT91_UDP_CSR_STALLSENT | 296 AT91_UDP_CSR_RXSETUP | 297 AT91_UDP_CSR_TXCOMP); 298 299 if (!(csr & AT91_UDP_CSR_RXSETUP)) { 300 goto not_complete; 301 } 302 /* clear did stall */ 303 td->did_stall = 0; 304 305 /* get the packet byte count */ 306 count = (csr & AT91_UDP_CSR_RXBYTECNT) >> 16; 307 308 /* verify data length */ 309 if (count != td->remainder) { 310 DPRINTFN(0, "Invalid SETUP packet " 311 "length, %d bytes\n", count); 312 goto not_complete; 313 } 314 if (count != sizeof(req)) { 315 DPRINTFN(0, "Unsupported SETUP packet " 316 "length, %d bytes\n", count); 317 goto not_complete; 318 } 319 /* receive data */ 320 bus_space_read_multi_1(td->io_tag, td->io_hdl, 321 td->fifo_reg, (void *)&req, sizeof(req)); 322 323 /* copy data into real buffer */ 324 usb2_copy_in(td->pc, 0, &req, sizeof(req)); 325 326 td->offset = sizeof(req); 327 td->remainder = 0; 328 329 /* get pointer to softc */ 330 sc = AT9100_DCI_PC2SC(td->pc); 331 332 /* sneak peek the set address */ 333 if ((req.bmRequestType == UT_WRITE_DEVICE) && 334 (req.bRequest == UR_SET_ADDRESS)) { 335 sc->sc_dv_addr = req.wValue[0] & 0x7F; 336 } else { 337 sc->sc_dv_addr = 0xFF; 338 } 339 340 /* sneak peek the endpoint direction */ 341 if (req.bmRequestType & UE_DIR_IN) { 342 csr |= AT91_UDP_CSR_DIR; 343 } else { 344 csr &= ~AT91_UDP_CSR_DIR; 345 } 346 347 /* write the direction of the control transfer */ 348 AT91_CSR_ACK(csr, temp); 349 bus_space_write_4(td->io_tag, td->io_hdl, 350 td->status_reg, csr); 351 return (0); /* complete */ 352 353not_complete: 354 /* abort any ongoing transfer */ 355 if (!td->did_stall) { 356 DPRINTFN(5, "stalling\n"); 357 temp |= AT91_UDP_CSR_FORCESTALL; 358 td->did_stall = 1; 359 } 360 361 /* clear interrupts, if any */ 362 if (temp) { 363 DPRINTFN(5, "clearing 0x%08x\n", temp); 364 AT91_CSR_ACK(csr, temp); 365 bus_space_write_4(td->io_tag, td->io_hdl, 366 td->status_reg, csr); 367 } 368 return (1); /* not complete */ 369 370} 371 372static uint8_t 373at91dci_data_rx(struct at91dci_td *td) 374{ 375 struct usb_page_search buf_res; 376 uint32_t csr; 377 uint32_t temp; 378 uint16_t count; 379 uint8_t to; 380 uint8_t got_short; 381 382 to = 2; /* don't loop forever! */ 383 got_short = 0; 384 385 /* check if any of the FIFO banks have data */ 386repeat: 387 /* read out FIFO status */ 388 csr = bus_space_read_4(td->io_tag, td->io_hdl, 389 td->status_reg); 390 391 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder); 392 393 if (csr & AT91_UDP_CSR_RXSETUP) { 394 if (td->remainder == 0) { 395 /* 396 * We are actually complete and have 397 * received the next SETUP 398 */ 399 DPRINTFN(5, "faking complete\n"); 400 return (0); /* complete */ 401 } 402 /* 403 * USB Host Aborted the transfer. 404 */ 405 td->error = 1; 406 return (0); /* complete */ 407 } 408 /* Make sure that "STALLSENT" gets cleared */ 409 temp = csr; 410 temp &= AT91_UDP_CSR_STALLSENT; 411 412 /* check status */ 413 if (!(csr & (AT91_UDP_CSR_RX_DATA_BK0 | 414 AT91_UDP_CSR_RX_DATA_BK1))) { 415 if (temp) { 416 /* write command */ 417 AT91_CSR_ACK(csr, temp); 418 bus_space_write_4(td->io_tag, td->io_hdl, 419 td->status_reg, csr); 420 } 421 return (1); /* not complete */ 422 } 423 /* get the packet byte count */ 424 count = (csr & AT91_UDP_CSR_RXBYTECNT) >> 16; 425 426 /* verify the packet byte count */ 427 if (count != td->max_packet_size) { 428 if (count < td->max_packet_size) { 429 /* we have a short packet */ 430 td->short_pkt = 1; 431 got_short = 1; 432 } else { 433 /* invalid USB packet */ 434 td->error = 1; 435 return (0); /* we are complete */ 436 } 437 } 438 /* verify the packet byte count */ 439 if (count > td->remainder) { 440 /* invalid USB packet */ 441 td->error = 1; 442 return (0); /* we are complete */ 443 } 444 while (count > 0) { 445 usb2_get_page(td->pc, td->offset, &buf_res); 446 447 /* get correct length */ 448 if (buf_res.length > count) { 449 buf_res.length = count; 450 } 451 /* receive data */ 452 bus_space_read_multi_1(td->io_tag, td->io_hdl, 453 td->fifo_reg, buf_res.buffer, buf_res.length); 454 455 /* update counters */ 456 count -= buf_res.length; 457 td->offset += buf_res.length; 458 td->remainder -= buf_res.length; 459 } 460 461 /* clear status bits */ 462 if (td->support_multi_buffer) { 463 if (td->fifo_bank) { 464 td->fifo_bank = 0; 465 temp |= AT91_UDP_CSR_RX_DATA_BK1; 466 } else { 467 td->fifo_bank = 1; 468 temp |= AT91_UDP_CSR_RX_DATA_BK0; 469 } 470 } else { 471 temp |= (AT91_UDP_CSR_RX_DATA_BK0 | 472 AT91_UDP_CSR_RX_DATA_BK1); 473 } 474 475 /* write command */ 476 AT91_CSR_ACK(csr, temp); 477 bus_space_write_4(td->io_tag, td->io_hdl, 478 td->status_reg, csr); 479 480 /* 481 * NOTE: We may have to delay a little bit before 482 * proceeding after clearing the DATA_BK bits. 483 */ 484 485 /* check if we are complete */ 486 if ((td->remainder == 0) || got_short) { 487 if (td->short_pkt) { 488 /* we are complete */ 489 return (0); 490 } 491 /* else need to receive a zero length packet */ 492 } 493 if (--to) { 494 goto repeat; 495 } 496 return (1); /* not complete */ 497} 498 499static uint8_t 500at91dci_data_tx(struct at91dci_td *td) 501{ 502 struct usb_page_search buf_res; 503 uint32_t csr; 504 uint32_t temp; 505 uint16_t count; 506 uint8_t to; 507 508 to = 2; /* don't loop forever! */ 509 510repeat: 511 512 /* read out FIFO status */ 513 csr = bus_space_read_4(td->io_tag, td->io_hdl, 514 td->status_reg); 515 516 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder); 517 518 if (csr & AT91_UDP_CSR_RXSETUP) { 519 /* 520 * The current transfer was aborted 521 * by the USB Host 522 */ 523 td->error = 1; 524 return (0); /* complete */ 525 } 526 /* Make sure that "STALLSENT" gets cleared */ 527 temp = csr; 528 temp &= AT91_UDP_CSR_STALLSENT; 529 530 if (csr & AT91_UDP_CSR_TXPKTRDY) { 531 if (temp) { 532 /* write command */ 533 AT91_CSR_ACK(csr, temp); 534 bus_space_write_4(td->io_tag, td->io_hdl, 535 td->status_reg, csr); 536 } 537 return (1); /* not complete */ 538 } else { 539 /* clear TXCOMP and set TXPKTRDY */ 540 temp |= (AT91_UDP_CSR_TXCOMP | 541 AT91_UDP_CSR_TXPKTRDY); 542 } 543 544 count = td->max_packet_size; 545 if (td->remainder < count) { 546 /* we have a short packet */ 547 td->short_pkt = 1; 548 count = td->remainder; 549 } 550 while (count > 0) { 551 552 usb2_get_page(td->pc, td->offset, &buf_res); 553 554 /* get correct length */ 555 if (buf_res.length > count) { 556 buf_res.length = count; 557 } 558 /* transmit data */ 559 bus_space_write_multi_1(td->io_tag, td->io_hdl, 560 td->fifo_reg, buf_res.buffer, buf_res.length); 561 562 /* update counters */ 563 count -= buf_res.length; 564 td->offset += buf_res.length; 565 td->remainder -= buf_res.length; 566 } 567 568 /* write command */ 569 AT91_CSR_ACK(csr, temp); 570 bus_space_write_4(td->io_tag, td->io_hdl, 571 td->status_reg, csr); 572 573 /* check remainder */ 574 if (td->remainder == 0) { 575 if (td->short_pkt) { 576 return (0); /* complete */ 577 } 578 /* else we need to transmit a short packet */ 579 } 580 if (--to) { 581 goto repeat; 582 } 583 return (1); /* not complete */ 584} 585 586static uint8_t 587at91dci_data_tx_sync(struct at91dci_td *td) 588{ 589 struct at91dci_softc *sc; 590 uint32_t csr; 591 uint32_t temp; 592 593#if 0 594repeat: 595#endif 596 597 /* read out FIFO status */ 598 csr = bus_space_read_4(td->io_tag, td->io_hdl, 599 td->status_reg); 600 601 DPRINTFN(5, "csr=0x%08x\n", csr); 602 603 if (csr & AT91_UDP_CSR_RXSETUP) { 604 DPRINTFN(5, "faking complete\n"); 605 /* Race condition */ 606 return (0); /* complete */ 607 } 608 temp = csr; 609 temp &= (AT91_UDP_CSR_STALLSENT | 610 AT91_UDP_CSR_TXCOMP); 611 612 /* check status */ 613 if (csr & AT91_UDP_CSR_TXPKTRDY) { 614 goto not_complete; 615 } 616 if (!(csr & AT91_UDP_CSR_TXCOMP)) { 617 goto not_complete; 618 } 619 sc = AT9100_DCI_PC2SC(td->pc); 620 if (sc->sc_dv_addr != 0xFF) { 621 /* 622 * The AT91 has a special requirement with regard to 623 * setting the address and that is to write the new 624 * address before clearing TXCOMP: 625 */ 626 at91dci_set_address(sc, sc->sc_dv_addr); 627 } 628 /* write command */ 629 AT91_CSR_ACK(csr, temp); 630 bus_space_write_4(td->io_tag, td->io_hdl, 631 td->status_reg, csr); 632 633 return (0); /* complete */ 634 635not_complete: 636 if (temp) { 637 /* write command */ 638 AT91_CSR_ACK(csr, temp); 639 bus_space_write_4(td->io_tag, td->io_hdl, 640 td->status_reg, csr); 641 } 642 return (1); /* not complete */ 643} 644 645static uint8_t 646at91dci_xfer_do_fifo(struct usb_xfer *xfer) 647{ 648 struct at91dci_softc *sc; 649 struct at91dci_td *td; 650 uint8_t temp; 651 652 DPRINTFN(9, "\n"); 653 654 td = xfer->td_transfer_cache; 655 while (1) { 656 if ((td->func) (td)) { 657 /* operation in progress */ 658 break; 659 } 660 if (((void *)td) == xfer->td_transfer_last) { 661 goto done; 662 } 663 if (td->error) { 664 goto done; 665 } else if (td->remainder > 0) { 666 /* 667 * We had a short transfer. If there is no alternate 668 * next, stop processing ! 669 */ 670 if (!td->alt_next) { 671 goto done; 672 } 673 } 674 /* 675 * Fetch the next transfer descriptor and transfer 676 * some flags to the next transfer descriptor 677 */ 678 temp = 0; 679 if (td->fifo_bank) 680 temp |= 1; 681 td = td->obj_next; 682 xfer->td_transfer_cache = td; 683 if (temp & 1) 684 td->fifo_bank = 1; 685 } 686 return (1); /* not complete */ 687 688done: 689 sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 690 temp = (xfer->endpoint & UE_ADDR); 691 692 /* update FIFO bank flag and multi buffer */ 693 if (td->fifo_bank) { 694 sc->sc_ep_flags[temp].fifo_bank = 1; 695 } else { 696 sc->sc_ep_flags[temp].fifo_bank = 0; 697 } 698 699 /* compute all actual lengths */ 700 701 at91dci_standard_done(xfer); 702 703 return (0); /* complete */ 704} 705 706static void 707at91dci_interrupt_poll(struct at91dci_softc *sc) 708{ 709 struct usb_xfer *xfer; 710 711repeat: 712 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 713 if (!at91dci_xfer_do_fifo(xfer)) { 714 /* queue has been modified */ 715 goto repeat; 716 } 717 } 718} 719 720void 721at91dci_vbus_interrupt(struct at91dci_softc *sc, uint8_t is_on) 722{ 723 DPRINTFN(5, "vbus = %u\n", is_on); 724 725 USB_BUS_LOCK(&sc->sc_bus); 726 if (is_on) { 727 if (!sc->sc_flags.status_vbus) { 728 sc->sc_flags.status_vbus = 1; 729 730 /* complete root HUB interrupt endpoint */ 731 at91dci_root_intr(sc); 732 } 733 } else { 734 if (sc->sc_flags.status_vbus) { 735 sc->sc_flags.status_vbus = 0; 736 sc->sc_flags.status_bus_reset = 0; 737 sc->sc_flags.status_suspend = 0; 738 sc->sc_flags.change_suspend = 0; 739 sc->sc_flags.change_connect = 1; 740 741 /* complete root HUB interrupt endpoint */ 742 at91dci_root_intr(sc); 743 } 744 } 745 USB_BUS_UNLOCK(&sc->sc_bus); 746} 747 748void 749at91dci_interrupt(struct at91dci_softc *sc) 750{ 751 uint32_t status; 752 753 USB_BUS_LOCK(&sc->sc_bus); 754 755 status = AT91_UDP_READ_4(sc, AT91_UDP_ISR); 756 status &= AT91_UDP_INT_DEFAULT; 757 758 if (!status) { 759 USB_BUS_UNLOCK(&sc->sc_bus); 760 return; 761 } 762 /* acknowledge interrupts */ 763 764 AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, status); 765 766 /* check for any bus state change interrupts */ 767 768 if (status & AT91_UDP_INT_BUS) { 769 770 DPRINTFN(5, "real bus interrupt 0x%08x\n", status); 771 772 if (status & AT91_UDP_INT_END_BR) { 773 774 /* set correct state */ 775 sc->sc_flags.status_bus_reset = 1; 776 sc->sc_flags.status_suspend = 0; 777 sc->sc_flags.change_suspend = 0; 778 sc->sc_flags.change_connect = 1; 779 780 /* disable resume interrupt */ 781 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 782 AT91_UDP_INT_RXRSM); 783 /* enable suspend interrupt */ 784 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, 785 AT91_UDP_INT_RXSUSP); 786 } 787 /* 788 * If RXRSM and RXSUSP is set at the same time we interpret 789 * that like RESUME. Resume is set when there is at least 3 790 * milliseconds of inactivity on the USB BUS. 791 */ 792 if (status & AT91_UDP_INT_RXRSM) { 793 if (sc->sc_flags.status_suspend) { 794 sc->sc_flags.status_suspend = 0; 795 sc->sc_flags.change_suspend = 1; 796 797 /* disable resume interrupt */ 798 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 799 AT91_UDP_INT_RXRSM); 800 /* enable suspend interrupt */ 801 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, 802 AT91_UDP_INT_RXSUSP); 803 } 804 } else if (status & AT91_UDP_INT_RXSUSP) { 805 if (!sc->sc_flags.status_suspend) { 806 sc->sc_flags.status_suspend = 1; 807 sc->sc_flags.change_suspend = 1; 808 809 /* disable suspend interrupt */ 810 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 811 AT91_UDP_INT_RXSUSP); 812 813 /* enable resume interrupt */ 814 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, 815 AT91_UDP_INT_RXRSM); 816 } 817 } 818 /* complete root HUB interrupt endpoint */ 819 at91dci_root_intr(sc); 820 } 821 /* check for any endpoint interrupts */ 822 823 if (status & AT91_UDP_INT_EPS) { 824 825 DPRINTFN(5, "real endpoint interrupt 0x%08x\n", status); 826 827 at91dci_interrupt_poll(sc); 828 } 829 USB_BUS_UNLOCK(&sc->sc_bus); 830} 831 832static void 833at91dci_setup_standard_chain_sub(struct at91dci_std_temp *temp) 834{ 835 struct at91dci_td *td; 836 837 /* get current Transfer Descriptor */ 838 td = temp->td_next; 839 temp->td = td; 840 841 /* prepare for next TD */ 842 temp->td_next = td->obj_next; 843 844 /* fill out the Transfer Descriptor */ 845 td->func = temp->func; 846 td->pc = temp->pc; 847 td->offset = temp->offset; 848 td->remainder = temp->len; 849 td->fifo_bank = 0; 850 td->error = 0; 851 td->did_stall = temp->did_stall; 852 td->short_pkt = temp->short_pkt; 853 td->alt_next = temp->setup_alt_next; 854} 855 856static void 857at91dci_setup_standard_chain(struct usb_xfer *xfer) 858{ 859 struct at91dci_std_temp temp; 860 struct at91dci_softc *sc; 861 struct at91dci_td *td; 862 uint32_t x; 863 uint8_t ep_no; 864 uint8_t need_sync; 865 866 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 867 xfer->address, UE_GET_ADDR(xfer->endpoint), 868 xfer->sumlen, usb2_get_speed(xfer->xroot->udev)); 869 870 temp.max_frame_size = xfer->max_frame_size; 871 872 td = xfer->td_start[0]; 873 xfer->td_transfer_first = td; 874 xfer->td_transfer_cache = td; 875 876 /* setup temp */ 877 878 temp.td = NULL; 879 temp.td_next = xfer->td_start[0]; 880 temp.offset = 0; 881 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 882 temp.did_stall = !xfer->flags_int.control_stall; 883 884 sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 885 ep_no = (xfer->endpoint & UE_ADDR); 886 887 /* check if we should prepend a setup message */ 888 889 if (xfer->flags_int.control_xfr) { 890 if (xfer->flags_int.control_hdr) { 891 892 temp.func = &at91dci_setup_rx; 893 temp.len = xfer->frlengths[0]; 894 temp.pc = xfer->frbuffers + 0; 895 temp.short_pkt = temp.len ? 1 : 0; 896 /* check for last frame */ 897 if (xfer->nframes == 1) { 898 /* no STATUS stage yet, SETUP is last */ 899 if (xfer->flags_int.control_act) 900 temp.setup_alt_next = 0; 901 } 902 903 at91dci_setup_standard_chain_sub(&temp); 904 } 905 x = 1; 906 } else { 907 x = 0; 908 } 909 910 if (x != xfer->nframes) { 911 if (xfer->endpoint & UE_DIR_IN) { 912 temp.func = &at91dci_data_tx; 913 need_sync = 1; 914 } else { 915 temp.func = &at91dci_data_rx; 916 need_sync = 0; 917 } 918 919 /* setup "pc" pointer */ 920 temp.pc = xfer->frbuffers + x; 921 } else { 922 need_sync = 0; 923 } 924 while (x != xfer->nframes) { 925 926 /* DATA0 / DATA1 message */ 927 928 temp.len = xfer->frlengths[x]; 929 930 x++; 931 932 if (x == xfer->nframes) { 933 if (xfer->flags_int.control_xfr) { 934 if (xfer->flags_int.control_act) { 935 temp.setup_alt_next = 0; 936 } 937 } else { 938 temp.setup_alt_next = 0; 939 } 940 } 941 if (temp.len == 0) { 942 943 /* make sure that we send an USB packet */ 944 945 temp.short_pkt = 0; 946 947 } else { 948 949 /* regular data transfer */ 950 951 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 952 } 953 954 at91dci_setup_standard_chain_sub(&temp); 955 956 if (xfer->flags_int.isochronous_xfr) { 957 temp.offset += temp.len; 958 } else { 959 /* get next Page Cache pointer */ 960 temp.pc = xfer->frbuffers + x; 961 } 962 } 963 964 /* check for control transfer */ 965 if (xfer->flags_int.control_xfr) { 966 967 /* always setup a valid "pc" pointer for status and sync */ 968 temp.pc = xfer->frbuffers + 0; 969 temp.len = 0; 970 temp.short_pkt = 0; 971 temp.setup_alt_next = 0; 972 973 /* check if we need to sync */ 974 if (need_sync) { 975 /* we need a SYNC point after TX */ 976 temp.func = &at91dci_data_tx_sync; 977 at91dci_setup_standard_chain_sub(&temp); 978 } 979 980 /* check if we should append a status stage */ 981 if (!xfer->flags_int.control_act) { 982 983 /* 984 * Send a DATA1 message and invert the current 985 * endpoint direction. 986 */ 987 if (xfer->endpoint & UE_DIR_IN) { 988 temp.func = &at91dci_data_rx; 989 need_sync = 0; 990 } else { 991 temp.func = &at91dci_data_tx; 992 need_sync = 1; 993 } 994 995 at91dci_setup_standard_chain_sub(&temp); 996 if (need_sync) { 997 /* we need a SYNC point after TX */ 998 temp.func = &at91dci_data_tx_sync; 999 at91dci_setup_standard_chain_sub(&temp); 1000 } 1001 } 1002 } 1003 1004 /* must have at least one frame! */ 1005 td = temp.td; 1006 xfer->td_transfer_last = td; 1007 1008 /* setup the correct fifo bank */ 1009 if (sc->sc_ep_flags[ep_no].fifo_bank) { 1010 td = xfer->td_transfer_first; 1011 td->fifo_bank = 1; 1012 } 1013} 1014 1015static void 1016at91dci_timeout(void *arg) 1017{ 1018 struct usb_xfer *xfer = arg; 1019 1020 DPRINTF("xfer=%p\n", xfer); 1021 1022 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1023 1024 /* transfer is transferred */ 1025 at91dci_device_done(xfer, USB_ERR_TIMEOUT); 1026} 1027 1028static void 1029at91dci_start_standard_chain(struct usb_xfer *xfer) 1030{ 1031 DPRINTFN(9, "\n"); 1032 1033 /* poll one time */ 1034 if (at91dci_xfer_do_fifo(xfer)) { 1035 1036 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 1037 uint8_t ep_no = xfer->endpoint & UE_ADDR; 1038 1039 /* 1040 * Only enable the endpoint interrupt when we are actually 1041 * waiting for data, hence we are dealing with level 1042 * triggered interrupts ! 1043 */ 1044 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, AT91_UDP_INT_EP(ep_no)); 1045 1046 DPRINTFN(15, "enable interrupts on endpoint %d\n", ep_no); 1047 1048 /* put transfer on interrupt queue */ 1049 usb2_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 1050 1051 /* start timeout, if any */ 1052 if (xfer->timeout != 0) { 1053 usb2_transfer_timeout_ms(xfer, 1054 &at91dci_timeout, xfer->timeout); 1055 } 1056 } 1057} 1058 1059static void 1060at91dci_root_intr(struct at91dci_softc *sc) 1061{ 1062 DPRINTFN(9, "\n"); 1063 1064 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1065 1066 /* set port bit */ 1067 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 1068 1069 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 1070 sizeof(sc->sc_hub_idata)); 1071} 1072 1073static usb_error_t 1074at91dci_standard_done_sub(struct usb_xfer *xfer) 1075{ 1076 struct at91dci_td *td; 1077 uint32_t len; 1078 uint8_t error; 1079 1080 DPRINTFN(9, "\n"); 1081 1082 td = xfer->td_transfer_cache; 1083 1084 do { 1085 len = td->remainder; 1086 1087 if (xfer->aframes != xfer->nframes) { 1088 /* 1089 * Verify the length and subtract 1090 * the remainder from "frlengths[]": 1091 */ 1092 if (len > xfer->frlengths[xfer->aframes]) { 1093 td->error = 1; 1094 } else { 1095 xfer->frlengths[xfer->aframes] -= len; 1096 } 1097 } 1098 /* Check for transfer error */ 1099 if (td->error) { 1100 /* the transfer is finished */ 1101 error = 1; 1102 td = NULL; 1103 break; 1104 } 1105 /* Check for short transfer */ 1106 if (len > 0) { 1107 if (xfer->flags_int.short_frames_ok) { 1108 /* follow alt next */ 1109 if (td->alt_next) { 1110 td = td->obj_next; 1111 } else { 1112 td = NULL; 1113 } 1114 } else { 1115 /* the transfer is finished */ 1116 td = NULL; 1117 } 1118 error = 0; 1119 break; 1120 } 1121 td = td->obj_next; 1122 1123 /* this USB frame is complete */ 1124 error = 0; 1125 break; 1126 1127 } while (0); 1128 1129 /* update transfer cache */ 1130 1131 xfer->td_transfer_cache = td; 1132 1133 return (error ? 1134 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1135} 1136 1137static void 1138at91dci_standard_done(struct usb_xfer *xfer) 1139{ 1140 usb_error_t err = 0; 1141 1142 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 1143 xfer, xfer->pipe); 1144 1145 /* reset scanner */ 1146 1147 xfer->td_transfer_cache = xfer->td_transfer_first; 1148 1149 if (xfer->flags_int.control_xfr) { 1150 1151 if (xfer->flags_int.control_hdr) { 1152 1153 err = at91dci_standard_done_sub(xfer); 1154 } 1155 xfer->aframes = 1; 1156 1157 if (xfer->td_transfer_cache == NULL) { 1158 goto done; 1159 } 1160 } 1161 while (xfer->aframes != xfer->nframes) { 1162 1163 err = at91dci_standard_done_sub(xfer); 1164 xfer->aframes++; 1165 1166 if (xfer->td_transfer_cache == NULL) { 1167 goto done; 1168 } 1169 } 1170 1171 if (xfer->flags_int.control_xfr && 1172 !xfer->flags_int.control_act) { 1173 1174 err = at91dci_standard_done_sub(xfer); 1175 } 1176done: 1177 at91dci_device_done(xfer, err); 1178} 1179 1180/*------------------------------------------------------------------------* 1181 * at91dci_device_done 1182 * 1183 * NOTE: this function can be called more than one time on the 1184 * same USB transfer! 1185 *------------------------------------------------------------------------*/ 1186static void 1187at91dci_device_done(struct usb_xfer *xfer, usb_error_t error) 1188{ 1189 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 1190 uint8_t ep_no; 1191 1192 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1193 1194 DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n", 1195 xfer, xfer->pipe, error); 1196 1197 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 1198 ep_no = (xfer->endpoint & UE_ADDR); 1199 1200 /* disable endpoint interrupt */ 1201 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, AT91_UDP_INT_EP(ep_no)); 1202 1203 DPRINTFN(15, "disable interrupts on endpoint %d\n", ep_no); 1204 } 1205 /* dequeue transfer and start next transfer */ 1206 usb2_transfer_done(xfer, error); 1207} 1208 1209static void 1210at91dci_set_stall(struct usb_device *udev, struct usb_xfer *xfer, 1211 struct usb_pipe *pipe) 1212{ 1213 struct at91dci_softc *sc; 1214 uint32_t csr_val; 1215 uint8_t csr_reg; 1216 1217 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1218 1219 DPRINTFN(5, "pipe=%p\n", pipe); 1220 1221 if (xfer) { 1222 /* cancel any ongoing transfers */ 1223 at91dci_device_done(xfer, USB_ERR_STALLED); 1224 } 1225 /* set FORCESTALL */ 1226 sc = AT9100_DCI_BUS2SC(udev->bus); 1227 csr_reg = (pipe->edesc->bEndpointAddress & UE_ADDR); 1228 csr_reg = AT91_UDP_CSR(csr_reg); 1229 csr_val = AT91_UDP_READ_4(sc, csr_reg); 1230 AT91_CSR_ACK(csr_val, AT91_UDP_CSR_FORCESTALL); 1231 AT91_UDP_WRITE_4(sc, csr_reg, csr_val); 1232} 1233 1234static void 1235at91dci_clear_stall_sub(struct at91dci_softc *sc, uint8_t ep_no, 1236 uint8_t ep_type, uint8_t ep_dir) 1237{ 1238 const struct usb_hw_ep_profile *pf; 1239 uint32_t csr_val; 1240 uint32_t temp; 1241 uint8_t csr_reg; 1242 uint8_t to; 1243 1244 if (ep_type == UE_CONTROL) { 1245 /* clearing stall is not needed */ 1246 return; 1247 } 1248 /* compute CSR register offset */ 1249 csr_reg = AT91_UDP_CSR(ep_no); 1250 1251 /* compute default CSR value */ 1252 csr_val = 0; 1253 AT91_CSR_ACK(csr_val, 0); 1254 1255 /* disable endpoint */ 1256 AT91_UDP_WRITE_4(sc, csr_reg, csr_val); 1257 1258 /* get endpoint profile */ 1259 at91dci_get_hw_ep_profile(NULL, &pf, ep_no); 1260 1261 /* reset FIFO */ 1262 AT91_UDP_WRITE_4(sc, AT91_UDP_RST, AT91_UDP_RST_EP(ep_no)); 1263 AT91_UDP_WRITE_4(sc, AT91_UDP_RST, 0); 1264 1265 /* 1266 * NOTE: One would assume that a FIFO reset would release the 1267 * FIFO banks aswell, but it doesn't! We have to do this 1268 * manually! 1269 */ 1270 1271 /* release FIFO banks, if any */ 1272 for (to = 0; to != 2; to++) { 1273 1274 /* get csr value */ 1275 csr_val = AT91_UDP_READ_4(sc, csr_reg); 1276 1277 if (csr_val & (AT91_UDP_CSR_RX_DATA_BK0 | 1278 AT91_UDP_CSR_RX_DATA_BK1)) { 1279 /* clear status bits */ 1280 if (pf->support_multi_buffer) { 1281 if (sc->sc_ep_flags[ep_no].fifo_bank) { 1282 sc->sc_ep_flags[ep_no].fifo_bank = 0; 1283 temp = AT91_UDP_CSR_RX_DATA_BK1; 1284 } else { 1285 sc->sc_ep_flags[ep_no].fifo_bank = 1; 1286 temp = AT91_UDP_CSR_RX_DATA_BK0; 1287 } 1288 } else { 1289 temp = (AT91_UDP_CSR_RX_DATA_BK0 | 1290 AT91_UDP_CSR_RX_DATA_BK1); 1291 } 1292 } else { 1293 temp = 0; 1294 } 1295 1296 /* clear FORCESTALL */ 1297 temp |= AT91_UDP_CSR_STALLSENT; 1298 1299 AT91_CSR_ACK(csr_val, temp); 1300 AT91_UDP_WRITE_4(sc, csr_reg, csr_val); 1301 } 1302 1303 /* compute default CSR value */ 1304 csr_val = 0; 1305 AT91_CSR_ACK(csr_val, 0); 1306 1307 /* enable endpoint */ 1308 csr_val &= ~AT91_UDP_CSR_ET_MASK; 1309 csr_val |= AT91_UDP_CSR_EPEDS; 1310 1311 if (ep_type == UE_CONTROL) { 1312 csr_val |= AT91_UDP_CSR_ET_CTRL; 1313 } else { 1314 if (ep_type == UE_BULK) { 1315 csr_val |= AT91_UDP_CSR_ET_BULK; 1316 } else if (ep_type == UE_INTERRUPT) { 1317 csr_val |= AT91_UDP_CSR_ET_INT; 1318 } else { 1319 csr_val |= AT91_UDP_CSR_ET_ISO; 1320 } 1321 if (ep_dir & UE_DIR_IN) { 1322 csr_val |= AT91_UDP_CSR_ET_DIR_IN; 1323 } 1324 } 1325 1326 /* enable endpoint */ 1327 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(ep_no), csr_val); 1328} 1329 1330static void 1331at91dci_clear_stall(struct usb_device *udev, struct usb_pipe *pipe) 1332{ 1333 struct at91dci_softc *sc; 1334 struct usb_endpoint_descriptor *ed; 1335 1336 DPRINTFN(5, "pipe=%p\n", pipe); 1337 1338 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1339 1340 /* check mode */ 1341 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 1342 /* not supported */ 1343 return; 1344 } 1345 /* get softc */ 1346 sc = AT9100_DCI_BUS2SC(udev->bus); 1347 1348 /* get endpoint descriptor */ 1349 ed = pipe->edesc; 1350 1351 /* reset endpoint */ 1352 at91dci_clear_stall_sub(sc, 1353 (ed->bEndpointAddress & UE_ADDR), 1354 (ed->bmAttributes & UE_XFERTYPE), 1355 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1356} 1357 1358usb_error_t 1359at91dci_init(struct at91dci_softc *sc) 1360{ 1361 uint32_t csr_val; 1362 uint8_t n; 1363 1364 DPRINTF("start\n"); 1365 1366 /* set up the bus structure */ 1367 sc->sc_bus.usbrev = USB_REV_1_1; 1368 sc->sc_bus.methods = &at91dci_bus_methods; 1369 1370 USB_BUS_LOCK(&sc->sc_bus); 1371 1372 /* turn on clocks */ 1373 1374 if (sc->sc_clocks_on) { 1375 (sc->sc_clocks_on) (sc->sc_clocks_arg); 1376 } 1377 /* wait a little for things to stabilise */ 1378 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 1379 1380 /* disable and clear all interrupts */ 1381 1382 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 0xFFFFFFFF); 1383 AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, 0xFFFFFFFF); 1384 1385 /* compute default CSR value */ 1386 1387 csr_val = 0; 1388 AT91_CSR_ACK(csr_val, 0); 1389 1390 /* disable all endpoints */ 1391 1392 for (n = 0; n != AT91_UDP_EP_MAX; n++) { 1393 1394 /* disable endpoint */ 1395 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(n), csr_val); 1396 } 1397 1398 /* enable the control endpoint */ 1399 1400 AT91_CSR_ACK(csr_val, AT91_UDP_CSR_ET_CTRL | 1401 AT91_UDP_CSR_EPEDS); 1402 1403 /* write to FIFO control register */ 1404 1405 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(0), csr_val); 1406 1407 /* enable the interrupts we want */ 1408 1409 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, AT91_UDP_INT_BUS); 1410 1411 /* turn off clocks */ 1412 1413 at91dci_clocks_off(sc); 1414 1415 USB_BUS_UNLOCK(&sc->sc_bus); 1416 1417 /* catch any lost interrupts */ 1418 1419 at91dci_do_poll(&sc->sc_bus); 1420 1421 return (0); /* success */ 1422} 1423 1424void 1425at91dci_uninit(struct at91dci_softc *sc) 1426{ 1427 USB_BUS_LOCK(&sc->sc_bus); 1428 1429 /* disable and clear all interrupts */ 1430 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 0xFFFFFFFF); 1431 AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, 0xFFFFFFFF); 1432 1433 sc->sc_flags.port_powered = 0; 1434 sc->sc_flags.status_vbus = 0; 1435 sc->sc_flags.status_bus_reset = 0; 1436 sc->sc_flags.status_suspend = 0; 1437 sc->sc_flags.change_suspend = 0; 1438 sc->sc_flags.change_connect = 1; 1439 1440 at91dci_pull_down(sc); 1441 at91dci_clocks_off(sc); 1442 USB_BUS_UNLOCK(&sc->sc_bus); 1443} 1444 1445void 1446at91dci_suspend(struct at91dci_softc *sc) 1447{ 1448 return; 1449} 1450 1451void 1452at91dci_resume(struct at91dci_softc *sc) 1453{ 1454 return; 1455} 1456 1457static void 1458at91dci_do_poll(struct usb_bus *bus) 1459{ 1460 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(bus); 1461 1462 USB_BUS_LOCK(&sc->sc_bus); 1463 at91dci_interrupt_poll(sc); 1464 USB_BUS_UNLOCK(&sc->sc_bus); 1465} 1466 1467/*------------------------------------------------------------------------* 1468 * at91dci bulk support 1469 *------------------------------------------------------------------------*/ 1470static void 1471at91dci_device_bulk_open(struct usb_xfer *xfer) 1472{ 1473 return; 1474} 1475 1476static void 1477at91dci_device_bulk_close(struct usb_xfer *xfer) 1478{ 1479 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1480} 1481 1482static void 1483at91dci_device_bulk_enter(struct usb_xfer *xfer) 1484{ 1485 return; 1486} 1487 1488static void 1489at91dci_device_bulk_start(struct usb_xfer *xfer) 1490{ 1491 /* setup TDs */ 1492 at91dci_setup_standard_chain(xfer); 1493 at91dci_start_standard_chain(xfer); 1494} 1495 1496struct usb_pipe_methods at91dci_device_bulk_methods = 1497{ 1498 .open = at91dci_device_bulk_open, 1499 .close = at91dci_device_bulk_close, 1500 .enter = at91dci_device_bulk_enter, 1501 .start = at91dci_device_bulk_start, 1502}; 1503 1504/*------------------------------------------------------------------------* 1505 * at91dci control support 1506 *------------------------------------------------------------------------*/ 1507static void 1508at91dci_device_ctrl_open(struct usb_xfer *xfer) 1509{ 1510 return; 1511} 1512 1513static void 1514at91dci_device_ctrl_close(struct usb_xfer *xfer) 1515{ 1516 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1517} 1518 1519static void 1520at91dci_device_ctrl_enter(struct usb_xfer *xfer) 1521{ 1522 return; 1523} 1524 1525static void 1526at91dci_device_ctrl_start(struct usb_xfer *xfer) 1527{ 1528 /* setup TDs */ 1529 at91dci_setup_standard_chain(xfer); 1530 at91dci_start_standard_chain(xfer); 1531} 1532 1533struct usb_pipe_methods at91dci_device_ctrl_methods = 1534{ 1535 .open = at91dci_device_ctrl_open, 1536 .close = at91dci_device_ctrl_close, 1537 .enter = at91dci_device_ctrl_enter, 1538 .start = at91dci_device_ctrl_start, 1539}; 1540 1541/*------------------------------------------------------------------------* 1542 * at91dci interrupt support 1543 *------------------------------------------------------------------------*/ 1544static void 1545at91dci_device_intr_open(struct usb_xfer *xfer) 1546{ 1547 return; 1548} 1549 1550static void 1551at91dci_device_intr_close(struct usb_xfer *xfer) 1552{ 1553 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1554} 1555 1556static void 1557at91dci_device_intr_enter(struct usb_xfer *xfer) 1558{ 1559 return; 1560} 1561 1562static void 1563at91dci_device_intr_start(struct usb_xfer *xfer) 1564{ 1565 /* setup TDs */ 1566 at91dci_setup_standard_chain(xfer); 1567 at91dci_start_standard_chain(xfer); 1568} 1569 1570struct usb_pipe_methods at91dci_device_intr_methods = 1571{ 1572 .open = at91dci_device_intr_open, 1573 .close = at91dci_device_intr_close, 1574 .enter = at91dci_device_intr_enter, 1575 .start = at91dci_device_intr_start, 1576}; 1577 1578/*------------------------------------------------------------------------* 1579 * at91dci full speed isochronous support 1580 *------------------------------------------------------------------------*/ 1581static void 1582at91dci_device_isoc_fs_open(struct usb_xfer *xfer) 1583{ 1584 return; 1585} 1586 1587static void 1588at91dci_device_isoc_fs_close(struct usb_xfer *xfer) 1589{ 1590 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1591} 1592 1593static void 1594at91dci_device_isoc_fs_enter(struct usb_xfer *xfer) 1595{ 1596 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 1597 uint32_t temp; 1598 uint32_t nframes; 1599 1600 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 1601 xfer, xfer->pipe->isoc_next, xfer->nframes); 1602 1603 /* get the current frame index */ 1604 1605 nframes = AT91_UDP_READ_4(sc, AT91_UDP_FRM); 1606 1607 /* 1608 * check if the frame index is within the window where the frames 1609 * will be inserted 1610 */ 1611 temp = (nframes - xfer->pipe->isoc_next) & AT91_UDP_FRM_MASK; 1612 1613 if ((xfer->pipe->is_synced == 0) || 1614 (temp < xfer->nframes)) { 1615 /* 1616 * If there is data underflow or the pipe queue is 1617 * empty we schedule the transfer a few frames ahead 1618 * of the current frame position. Else two isochronous 1619 * transfers might overlap. 1620 */ 1621 xfer->pipe->isoc_next = (nframes + 3) & AT91_UDP_FRM_MASK; 1622 xfer->pipe->is_synced = 1; 1623 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next); 1624 } 1625 /* 1626 * compute how many milliseconds the insertion is ahead of the 1627 * current frame position: 1628 */ 1629 temp = (xfer->pipe->isoc_next - nframes) & AT91_UDP_FRM_MASK; 1630 1631 /* 1632 * pre-compute when the isochronous transfer will be finished: 1633 */ 1634 xfer->isoc_time_complete = 1635 usb2_isoc_time_expand(&sc->sc_bus, nframes) + temp + 1636 xfer->nframes; 1637 1638 /* compute frame number for next insertion */ 1639 xfer->pipe->isoc_next += xfer->nframes; 1640 1641 /* setup TDs */ 1642 at91dci_setup_standard_chain(xfer); 1643} 1644 1645static void 1646at91dci_device_isoc_fs_start(struct usb_xfer *xfer) 1647{ 1648 /* start TD chain */ 1649 at91dci_start_standard_chain(xfer); 1650} 1651 1652struct usb_pipe_methods at91dci_device_isoc_fs_methods = 1653{ 1654 .open = at91dci_device_isoc_fs_open, 1655 .close = at91dci_device_isoc_fs_close, 1656 .enter = at91dci_device_isoc_fs_enter, 1657 .start = at91dci_device_isoc_fs_start, 1658}; 1659 1660/*------------------------------------------------------------------------* 1661 * at91dci root control support 1662 *------------------------------------------------------------------------* 1663 * Simulate a hardware HUB by handling all the necessary requests. 1664 *------------------------------------------------------------------------*/ 1665 1666static const struct usb_device_descriptor at91dci_devd = { 1667 .bLength = sizeof(struct usb_device_descriptor), 1668 .bDescriptorType = UDESC_DEVICE, 1669 .bcdUSB = {0x00, 0x02}, 1670 .bDeviceClass = UDCLASS_HUB, 1671 .bDeviceSubClass = UDSUBCLASS_HUB, 1672 .bDeviceProtocol = UDPROTO_HSHUBSTT, 1673 .bMaxPacketSize = 64, 1674 .bcdDevice = {0x00, 0x01}, 1675 .iManufacturer = 1, 1676 .iProduct = 2, 1677 .bNumConfigurations = 1, 1678}; 1679 1680static const struct usb_device_qualifier at91dci_odevd = { 1681 .bLength = sizeof(struct usb_device_qualifier), 1682 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 1683 .bcdUSB = {0x00, 0x02}, 1684 .bDeviceClass = UDCLASS_HUB, 1685 .bDeviceSubClass = UDSUBCLASS_HUB, 1686 .bDeviceProtocol = UDPROTO_FSHUB, 1687 .bMaxPacketSize0 = 0, 1688 .bNumConfigurations = 0, 1689}; 1690 1691static const struct at91dci_config_desc at91dci_confd = { 1692 .confd = { 1693 .bLength = sizeof(struct usb_config_descriptor), 1694 .bDescriptorType = UDESC_CONFIG, 1695 .wTotalLength[0] = sizeof(at91dci_confd), 1696 .bNumInterface = 1, 1697 .bConfigurationValue = 1, 1698 .iConfiguration = 0, 1699 .bmAttributes = UC_SELF_POWERED, 1700 .bMaxPower = 0, 1701 }, 1702 .ifcd = { 1703 .bLength = sizeof(struct usb_interface_descriptor), 1704 .bDescriptorType = UDESC_INTERFACE, 1705 .bNumEndpoints = 1, 1706 .bInterfaceClass = UICLASS_HUB, 1707 .bInterfaceSubClass = UISUBCLASS_HUB, 1708 .bInterfaceProtocol = UIPROTO_HSHUBSTT, 1709 }, 1710 .endpd = { 1711 .bLength = sizeof(struct usb_endpoint_descriptor), 1712 .bDescriptorType = UDESC_ENDPOINT, 1713 .bEndpointAddress = (UE_DIR_IN | AT9100_DCI_INTR_ENDPT), 1714 .bmAttributes = UE_INTERRUPT, 1715 .wMaxPacketSize[0] = 8, 1716 .bInterval = 255, 1717 }, 1718}; 1719 1720static const struct usb_hub_descriptor_min at91dci_hubd = { 1721 .bDescLength = sizeof(at91dci_hubd), 1722 .bDescriptorType = UDESC_HUB, 1723 .bNbrPorts = 1, 1724 .wHubCharacteristics[0] = 1725 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) & 0xFF, 1726 .wHubCharacteristics[1] = 1727 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) >> 8, 1728 .bPwrOn2PwrGood = 50, 1729 .bHubContrCurrent = 0, 1730 .DeviceRemovable = {0}, /* port is removable */ 1731}; 1732 1733#define STRING_LANG \ 1734 0x09, 0x04, /* American English */ 1735 1736#define STRING_VENDOR \ 1737 'A', 0, 'T', 0, 'M', 0, 'E', 0, 'L', 0 1738 1739#define STRING_PRODUCT \ 1740 'D', 0, 'C', 0, 'I', 0, ' ', 0, 'R', 0, \ 1741 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \ 1742 'U', 0, 'B', 0, 1743 1744USB_MAKE_STRING_DESC(STRING_LANG, at91dci_langtab); 1745USB_MAKE_STRING_DESC(STRING_VENDOR, at91dci_vendor); 1746USB_MAKE_STRING_DESC(STRING_PRODUCT, at91dci_product); 1747 1748static usb_error_t 1749at91dci_roothub_exec(struct usb_device *udev, 1750 struct usb_device_request *req, const void **pptr, uint16_t *plength) 1751{ 1752 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(udev->bus); 1753 const void *ptr; 1754 uint16_t len; 1755 uint16_t value; 1756 uint16_t index; 1757 usb_error_t err; 1758 1759 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1760 1761 /* buffer reset */ 1762 ptr = (const void *)&sc->sc_hub_temp; 1763 len = 0; 1764 err = 0; 1765 1766 value = UGETW(req->wValue); 1767 index = UGETW(req->wIndex); 1768 1769 /* demultiplex the control request */ 1770 1771 switch (req->bmRequestType) { 1772 case UT_READ_DEVICE: 1773 switch (req->bRequest) { 1774 case UR_GET_DESCRIPTOR: 1775 goto tr_handle_get_descriptor; 1776 case UR_GET_CONFIG: 1777 goto tr_handle_get_config; 1778 case UR_GET_STATUS: 1779 goto tr_handle_get_status; 1780 default: 1781 goto tr_stalled; 1782 } 1783 break; 1784 1785 case UT_WRITE_DEVICE: 1786 switch (req->bRequest) { 1787 case UR_SET_ADDRESS: 1788 goto tr_handle_set_address; 1789 case UR_SET_CONFIG: 1790 goto tr_handle_set_config; 1791 case UR_CLEAR_FEATURE: 1792 goto tr_valid; /* nop */ 1793 case UR_SET_DESCRIPTOR: 1794 goto tr_valid; /* nop */ 1795 case UR_SET_FEATURE: 1796 default: 1797 goto tr_stalled; 1798 } 1799 break; 1800 1801 case UT_WRITE_ENDPOINT: 1802 switch (req->bRequest) { 1803 case UR_CLEAR_FEATURE: 1804 switch (UGETW(req->wValue)) { 1805 case UF_ENDPOINT_HALT: 1806 goto tr_handle_clear_halt; 1807 case UF_DEVICE_REMOTE_WAKEUP: 1808 goto tr_handle_clear_wakeup; 1809 default: 1810 goto tr_stalled; 1811 } 1812 break; 1813 case UR_SET_FEATURE: 1814 switch (UGETW(req->wValue)) { 1815 case UF_ENDPOINT_HALT: 1816 goto tr_handle_set_halt; 1817 case UF_DEVICE_REMOTE_WAKEUP: 1818 goto tr_handle_set_wakeup; 1819 default: 1820 goto tr_stalled; 1821 } 1822 break; 1823 case UR_SYNCH_FRAME: 1824 goto tr_valid; /* nop */ 1825 default: 1826 goto tr_stalled; 1827 } 1828 break; 1829 1830 case UT_READ_ENDPOINT: 1831 switch (req->bRequest) { 1832 case UR_GET_STATUS: 1833 goto tr_handle_get_ep_status; 1834 default: 1835 goto tr_stalled; 1836 } 1837 break; 1838 1839 case UT_WRITE_INTERFACE: 1840 switch (req->bRequest) { 1841 case UR_SET_INTERFACE: 1842 goto tr_handle_set_interface; 1843 case UR_CLEAR_FEATURE: 1844 goto tr_valid; /* nop */ 1845 case UR_SET_FEATURE: 1846 default: 1847 goto tr_stalled; 1848 } 1849 break; 1850 1851 case UT_READ_INTERFACE: 1852 switch (req->bRequest) { 1853 case UR_GET_INTERFACE: 1854 goto tr_handle_get_interface; 1855 case UR_GET_STATUS: 1856 goto tr_handle_get_iface_status; 1857 default: 1858 goto tr_stalled; 1859 } 1860 break; 1861 1862 case UT_WRITE_CLASS_INTERFACE: 1863 case UT_WRITE_VENDOR_INTERFACE: 1864 /* XXX forward */ 1865 break; 1866 1867 case UT_READ_CLASS_INTERFACE: 1868 case UT_READ_VENDOR_INTERFACE: 1869 /* XXX forward */ 1870 break; 1871 1872 case UT_WRITE_CLASS_DEVICE: 1873 switch (req->bRequest) { 1874 case UR_CLEAR_FEATURE: 1875 goto tr_valid; 1876 case UR_SET_DESCRIPTOR: 1877 case UR_SET_FEATURE: 1878 break; 1879 default: 1880 goto tr_stalled; 1881 } 1882 break; 1883 1884 case UT_WRITE_CLASS_OTHER: 1885 switch (req->bRequest) { 1886 case UR_CLEAR_FEATURE: 1887 goto tr_handle_clear_port_feature; 1888 case UR_SET_FEATURE: 1889 goto tr_handle_set_port_feature; 1890 case UR_CLEAR_TT_BUFFER: 1891 case UR_RESET_TT: 1892 case UR_STOP_TT: 1893 goto tr_valid; 1894 1895 default: 1896 goto tr_stalled; 1897 } 1898 break; 1899 1900 case UT_READ_CLASS_OTHER: 1901 switch (req->bRequest) { 1902 case UR_GET_TT_STATE: 1903 goto tr_handle_get_tt_state; 1904 case UR_GET_STATUS: 1905 goto tr_handle_get_port_status; 1906 default: 1907 goto tr_stalled; 1908 } 1909 break; 1910 1911 case UT_READ_CLASS_DEVICE: 1912 switch (req->bRequest) { 1913 case UR_GET_DESCRIPTOR: 1914 goto tr_handle_get_class_descriptor; 1915 case UR_GET_STATUS: 1916 goto tr_handle_get_class_status; 1917 1918 default: 1919 goto tr_stalled; 1920 } 1921 break; 1922 default: 1923 goto tr_stalled; 1924 } 1925 goto tr_valid; 1926 1927tr_handle_get_descriptor: 1928 switch (value >> 8) { 1929 case UDESC_DEVICE: 1930 if (value & 0xff) { 1931 goto tr_stalled; 1932 } 1933 len = sizeof(at91dci_devd); 1934 ptr = (const void *)&at91dci_devd; 1935 goto tr_valid; 1936 case UDESC_CONFIG: 1937 if (value & 0xff) { 1938 goto tr_stalled; 1939 } 1940 len = sizeof(at91dci_confd); 1941 ptr = (const void *)&at91dci_confd; 1942 goto tr_valid; 1943 case UDESC_STRING: 1944 switch (value & 0xff) { 1945 case 0: /* Language table */ 1946 len = sizeof(at91dci_langtab); 1947 ptr = (const void *)&at91dci_langtab; 1948 goto tr_valid; 1949 1950 case 1: /* Vendor */ 1951 len = sizeof(at91dci_vendor); 1952 ptr = (const void *)&at91dci_vendor; 1953 goto tr_valid; 1954 1955 case 2: /* Product */ 1956 len = sizeof(at91dci_product); 1957 ptr = (const void *)&at91dci_product; 1958 goto tr_valid; 1959 default: 1960 break; 1961 } 1962 break; 1963 default: 1964 goto tr_stalled; 1965 } 1966 goto tr_stalled; 1967 1968tr_handle_get_config: 1969 len = 1; 1970 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 1971 goto tr_valid; 1972 1973tr_handle_get_status: 1974 len = 2; 1975 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 1976 goto tr_valid; 1977 1978tr_handle_set_address: 1979 if (value & 0xFF00) { 1980 goto tr_stalled; 1981 } 1982 sc->sc_rt_addr = value; 1983 goto tr_valid; 1984 1985tr_handle_set_config: 1986 if (value >= 2) { 1987 goto tr_stalled; 1988 } 1989 sc->sc_conf = value; 1990 goto tr_valid; 1991 1992tr_handle_get_interface: 1993 len = 1; 1994 sc->sc_hub_temp.wValue[0] = 0; 1995 goto tr_valid; 1996 1997tr_handle_get_tt_state: 1998tr_handle_get_class_status: 1999tr_handle_get_iface_status: 2000tr_handle_get_ep_status: 2001 len = 2; 2002 USETW(sc->sc_hub_temp.wValue, 0); 2003 goto tr_valid; 2004 2005tr_handle_set_halt: 2006tr_handle_set_interface: 2007tr_handle_set_wakeup: 2008tr_handle_clear_wakeup: 2009tr_handle_clear_halt: 2010 goto tr_valid; 2011 2012tr_handle_clear_port_feature: 2013 if (index != 1) { 2014 goto tr_stalled; 2015 } 2016 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 2017 2018 switch (value) { 2019 case UHF_PORT_SUSPEND: 2020 at91dci_wakeup_peer(sc); 2021 break; 2022 2023 case UHF_PORT_ENABLE: 2024 sc->sc_flags.port_enabled = 0; 2025 break; 2026 2027 case UHF_PORT_TEST: 2028 case UHF_PORT_INDICATOR: 2029 case UHF_C_PORT_ENABLE: 2030 case UHF_C_PORT_OVER_CURRENT: 2031 case UHF_C_PORT_RESET: 2032 /* nops */ 2033 break; 2034 case UHF_PORT_POWER: 2035 sc->sc_flags.port_powered = 0; 2036 at91dci_pull_down(sc); 2037 at91dci_clocks_off(sc); 2038 break; 2039 case UHF_C_PORT_CONNECTION: 2040 sc->sc_flags.change_connect = 0; 2041 break; 2042 case UHF_C_PORT_SUSPEND: 2043 sc->sc_flags.change_suspend = 0; 2044 break; 2045 default: 2046 err = USB_ERR_IOERROR; 2047 goto done; 2048 } 2049 goto tr_valid; 2050 2051tr_handle_set_port_feature: 2052 if (index != 1) { 2053 goto tr_stalled; 2054 } 2055 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 2056 2057 switch (value) { 2058 case UHF_PORT_ENABLE: 2059 sc->sc_flags.port_enabled = 1; 2060 break; 2061 case UHF_PORT_SUSPEND: 2062 case UHF_PORT_RESET: 2063 case UHF_PORT_TEST: 2064 case UHF_PORT_INDICATOR: 2065 /* nops */ 2066 break; 2067 case UHF_PORT_POWER: 2068 sc->sc_flags.port_powered = 1; 2069 break; 2070 default: 2071 err = USB_ERR_IOERROR; 2072 goto done; 2073 } 2074 goto tr_valid; 2075 2076tr_handle_get_port_status: 2077 2078 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 2079 2080 if (index != 1) { 2081 goto tr_stalled; 2082 } 2083 if (sc->sc_flags.status_vbus) { 2084 at91dci_clocks_on(sc); 2085 at91dci_pull_up(sc); 2086 } else { 2087 at91dci_pull_down(sc); 2088 at91dci_clocks_off(sc); 2089 } 2090 2091 /* Select FULL-speed and Device Side Mode */ 2092 2093 value = UPS_PORT_MODE_DEVICE; 2094 2095 if (sc->sc_flags.port_powered) { 2096 value |= UPS_PORT_POWER; 2097 } 2098 if (sc->sc_flags.port_enabled) { 2099 value |= UPS_PORT_ENABLED; 2100 } 2101 if (sc->sc_flags.status_vbus && 2102 sc->sc_flags.status_bus_reset) { 2103 value |= UPS_CURRENT_CONNECT_STATUS; 2104 } 2105 if (sc->sc_flags.status_suspend) { 2106 value |= UPS_SUSPEND; 2107 } 2108 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 2109 2110 value = 0; 2111 2112 if (sc->sc_flags.change_connect) { 2113 value |= UPS_C_CONNECT_STATUS; 2114 2115 if (sc->sc_flags.status_vbus && 2116 sc->sc_flags.status_bus_reset) { 2117 /* reset endpoint flags */ 2118 bzero(sc->sc_ep_flags, sizeof(sc->sc_ep_flags)); 2119 } 2120 } 2121 if (sc->sc_flags.change_suspend) { 2122 value |= UPS_C_SUSPEND; 2123 } 2124 USETW(sc->sc_hub_temp.ps.wPortChange, value); 2125 len = sizeof(sc->sc_hub_temp.ps); 2126 goto tr_valid; 2127 2128tr_handle_get_class_descriptor: 2129 if (value & 0xFF) { 2130 goto tr_stalled; 2131 } 2132 ptr = (const void *)&at91dci_hubd; 2133 len = sizeof(at91dci_hubd); 2134 goto tr_valid; 2135 2136tr_stalled: 2137 err = USB_ERR_STALLED; 2138tr_valid: 2139done: 2140 *plength = len; 2141 *pptr = ptr; 2142 return (err); 2143} 2144 2145static void 2146at91dci_xfer_setup(struct usb_setup_params *parm) 2147{ 2148 const struct usb_hw_ep_profile *pf; 2149 struct at91dci_softc *sc; 2150 struct usb_xfer *xfer; 2151 void *last_obj; 2152 uint32_t ntd; 2153 uint32_t n; 2154 uint8_t ep_no; 2155 2156 sc = AT9100_DCI_BUS2SC(parm->udev->bus); 2157 xfer = parm->curr_xfer; 2158 2159 /* 2160 * NOTE: This driver does not use any of the parameters that 2161 * are computed from the following values. Just set some 2162 * reasonable dummies: 2163 */ 2164 parm->hc_max_packet_size = 0x500; 2165 parm->hc_max_packet_count = 1; 2166 parm->hc_max_frame_size = 0x500; 2167 2168 usb2_transfer_setup_sub(parm); 2169 2170 /* 2171 * compute maximum number of TDs 2172 */ 2173 if (parm->methods == &at91dci_device_ctrl_methods) { 2174 2175 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 2176 + 1 /* SYNC 2 */ ; 2177 2178 } else if (parm->methods == &at91dci_device_bulk_methods) { 2179 2180 ntd = xfer->nframes + 1 /* SYNC */ ; 2181 2182 } else if (parm->methods == &at91dci_device_intr_methods) { 2183 2184 ntd = xfer->nframes + 1 /* SYNC */ ; 2185 2186 } else if (parm->methods == &at91dci_device_isoc_fs_methods) { 2187 2188 ntd = xfer->nframes + 1 /* SYNC */ ; 2189 2190 } else { 2191 2192 ntd = 0; 2193 } 2194 2195 /* 2196 * check if "usb2_transfer_setup_sub" set an error 2197 */ 2198 if (parm->err) { 2199 return; 2200 } 2201 /* 2202 * allocate transfer descriptors 2203 */ 2204 last_obj = NULL; 2205 2206 /* 2207 * get profile stuff 2208 */ 2209 if (ntd) { 2210 2211 ep_no = xfer->endpoint & UE_ADDR; 2212 at91dci_get_hw_ep_profile(parm->udev, &pf, ep_no); 2213 2214 if (pf == NULL) { 2215 /* should not happen */ 2216 parm->err = USB_ERR_INVAL; 2217 return; 2218 } 2219 } else { 2220 ep_no = 0; 2221 pf = NULL; 2222 } 2223 2224 /* align data */ 2225 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2226 2227 for (n = 0; n != ntd; n++) { 2228 2229 struct at91dci_td *td; 2230 2231 if (parm->buf) { 2232 2233 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2234 2235 /* init TD */ 2236 td->io_tag = sc->sc_io_tag; 2237 td->io_hdl = sc->sc_io_hdl; 2238 td->max_packet_size = xfer->max_packet_size; 2239 td->status_reg = AT91_UDP_CSR(ep_no); 2240 td->fifo_reg = AT91_UDP_FDR(ep_no); 2241 if (pf->support_multi_buffer) { 2242 td->support_multi_buffer = 1; 2243 } 2244 td->obj_next = last_obj; 2245 2246 last_obj = td; 2247 } 2248 parm->size[0] += sizeof(*td); 2249 } 2250 2251 xfer->td_start[0] = last_obj; 2252} 2253 2254static void 2255at91dci_xfer_unsetup(struct usb_xfer *xfer) 2256{ 2257 return; 2258} 2259 2260static void 2261at91dci_pipe_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 2262 struct usb_pipe *pipe) 2263{ 2264 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(udev->bus); 2265 2266 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 2267 pipe, udev->address, 2268 edesc->bEndpointAddress, udev->flags.usb_mode, 2269 sc->sc_rt_addr); 2270 2271 if (udev->device_index != sc->sc_rt_addr) { 2272 2273 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 2274 /* not supported */ 2275 return; 2276 } 2277 if (udev->speed != USB_SPEED_FULL) { 2278 /* not supported */ 2279 return; 2280 } 2281 switch (edesc->bmAttributes & UE_XFERTYPE) { 2282 case UE_CONTROL: 2283 pipe->methods = &at91dci_device_ctrl_methods; 2284 break; 2285 case UE_INTERRUPT: 2286 pipe->methods = &at91dci_device_intr_methods; 2287 break; 2288 case UE_ISOCHRONOUS: 2289 pipe->methods = &at91dci_device_isoc_fs_methods; 2290 break; 2291 case UE_BULK: 2292 pipe->methods = &at91dci_device_bulk_methods; 2293 break; 2294 default: 2295 /* do nothing */ 2296 break; 2297 } 2298 } 2299} 2300 2301struct usb_bus_methods at91dci_bus_methods = 2302{ 2303 .pipe_init = &at91dci_pipe_init, 2304 .xfer_setup = &at91dci_xfer_setup, 2305 .xfer_unsetup = &at91dci_xfer_unsetup, 2306 .get_hw_ep_profile = &at91dci_get_hw_ep_profile, 2307 .set_stall = &at91dci_set_stall, 2308 .clear_stall = &at91dci_clear_stall, 2309 .roothub_exec = &at91dci_roothub_exec, 2310}; 2311