at91dci.c revision 192499
1#include <sys/cdefs.h> 2__FBSDID("$FreeBSD: head/sys/dev/usb/controller/at91dci.c 192499 2009-05-21 00:04:17Z thompsa $"); 3 4/*- 5 * Copyright (c) 2007-2008 Hans Petter Selasky. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * This file contains the driver for the AT91 series USB Device 31 * Controller 32 */ 33 34/* 35 * Thanks to "David Brownell" for helping out regarding the hardware 36 * endpoint profiles. 37 */ 38 39/* 40 * NOTE: The "fifo_bank" is not reset in hardware when the endpoint is 41 * reset. 42 * 43 * NOTE: When the chip detects BUS-reset it will also reset the 44 * endpoints, Function-address and more. 45 */ 46 47#include <dev/usb/usb.h> 48#include <dev/usb/usb_mfunc.h> 49#include <dev/usb/usb_error.h> 50 51#define USB_DEBUG_VAR at91dcidebug 52 53#include <dev/usb/usb_core.h> 54#include <dev/usb/usb_debug.h> 55#include <dev/usb/usb_busdma.h> 56#include <dev/usb/usb_process.h> 57#include <dev/usb/usb_transfer.h> 58#include <dev/usb/usb_device.h> 59#include <dev/usb/usb_hub.h> 60#include <dev/usb/usb_util.h> 61 62#include <dev/usb/usb_controller.h> 63#include <dev/usb/usb_bus.h> 64#include <dev/usb/controller/at91dci.h> 65 66#define AT9100_DCI_BUS2SC(bus) \ 67 ((struct at91dci_softc *)(((uint8_t *)(bus)) - \ 68 ((uint8_t *)&(((struct at91dci_softc *)0)->sc_bus)))) 69 70#define AT9100_DCI_PC2SC(pc) \ 71 AT9100_DCI_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 72 73#if USB_DEBUG 74static int at91dcidebug = 0; 75 76SYSCTL_NODE(_hw_usb2, OID_AUTO, at91dci, CTLFLAG_RW, 0, "USB at91dci"); 77SYSCTL_INT(_hw_usb2_at91dci, OID_AUTO, debug, CTLFLAG_RW, 78 &at91dcidebug, 0, "at91dci debug level"); 79#endif 80 81#define AT9100_DCI_INTR_ENDPT 1 82 83/* prototypes */ 84 85struct usb2_bus_methods at91dci_bus_methods; 86struct usb2_pipe_methods at91dci_device_bulk_methods; 87struct usb2_pipe_methods at91dci_device_ctrl_methods; 88struct usb2_pipe_methods at91dci_device_intr_methods; 89struct usb2_pipe_methods at91dci_device_isoc_fs_methods; 90 91static at91dci_cmd_t at91dci_setup_rx; 92static at91dci_cmd_t at91dci_data_rx; 93static at91dci_cmd_t at91dci_data_tx; 94static at91dci_cmd_t at91dci_data_tx_sync; 95static void at91dci_device_done(struct usb2_xfer *, usb2_error_t); 96static void at91dci_do_poll(struct usb2_bus *); 97static void at91dci_standard_done(struct usb2_xfer *); 98static void at91dci_root_intr(struct at91dci_softc *sc); 99 100/* 101 * NOTE: Some of the bits in the CSR register have inverse meaning so 102 * we need a helper macro when acknowledging events: 103 */ 104#define AT91_CSR_ACK(csr, what) do { \ 105 (csr) &= ~((AT91_UDP_CSR_FORCESTALL| \ 106 AT91_UDP_CSR_TXPKTRDY| \ 107 AT91_UDP_CSR_RXBYTECNT) ^ (what));\ 108 (csr) |= ((AT91_UDP_CSR_RX_DATA_BK0| \ 109 AT91_UDP_CSR_RX_DATA_BK1| \ 110 AT91_UDP_CSR_TXCOMP| \ 111 AT91_UDP_CSR_RXSETUP| \ 112 AT91_UDP_CSR_STALLSENT) ^ (what)); \ 113} while (0) 114 115/* 116 * Here is a list of what the chip supports. 117 * Probably it supports more than listed here! 118 */ 119static const struct usb2_hw_ep_profile 120 at91dci_ep_profile[AT91_UDP_EP_MAX] = { 121 122 [0] = { 123 .max_in_frame_size = 8, 124 .max_out_frame_size = 8, 125 .is_simplex = 1, 126 .support_control = 1, 127 }, 128 [1] = { 129 .max_in_frame_size = 64, 130 .max_out_frame_size = 64, 131 .is_simplex = 1, 132 .support_multi_buffer = 1, 133 .support_bulk = 1, 134 .support_interrupt = 1, 135 .support_isochronous = 1, 136 .support_in = 1, 137 .support_out = 1, 138 }, 139 [2] = { 140 .max_in_frame_size = 64, 141 .max_out_frame_size = 64, 142 .is_simplex = 1, 143 .support_multi_buffer = 1, 144 .support_bulk = 1, 145 .support_interrupt = 1, 146 .support_isochronous = 1, 147 .support_in = 1, 148 .support_out = 1, 149 }, 150 [3] = { 151 /* can also do BULK */ 152 .max_in_frame_size = 8, 153 .max_out_frame_size = 8, 154 .is_simplex = 1, 155 .support_interrupt = 1, 156 .support_in = 1, 157 .support_out = 1, 158 }, 159 [4] = { 160 .max_in_frame_size = 256, 161 .max_out_frame_size = 256, 162 .is_simplex = 1, 163 .support_multi_buffer = 1, 164 .support_bulk = 1, 165 .support_interrupt = 1, 166 .support_isochronous = 1, 167 .support_in = 1, 168 .support_out = 1, 169 }, 170 [5] = { 171 .max_in_frame_size = 256, 172 .max_out_frame_size = 256, 173 .is_simplex = 1, 174 .support_multi_buffer = 1, 175 .support_bulk = 1, 176 .support_interrupt = 1, 177 .support_isochronous = 1, 178 .support_in = 1, 179 .support_out = 1, 180 }, 181}; 182 183static void 184at91dci_get_hw_ep_profile(struct usb2_device *udev, 185 const struct usb2_hw_ep_profile **ppf, uint8_t ep_addr) 186{ 187 if (ep_addr < AT91_UDP_EP_MAX) { 188 *ppf = (at91dci_ep_profile + ep_addr); 189 } else { 190 *ppf = NULL; 191 } 192} 193 194static void 195at91dci_clocks_on(struct at91dci_softc *sc) 196{ 197 if (sc->sc_flags.clocks_off && 198 sc->sc_flags.port_powered) { 199 200 DPRINTFN(5, "\n"); 201 202 if (sc->sc_clocks_on) { 203 (sc->sc_clocks_on) (sc->sc_clocks_arg); 204 } 205 sc->sc_flags.clocks_off = 0; 206 207 /* enable Transceiver */ 208 AT91_UDP_WRITE_4(sc, AT91_UDP_TXVC, 0); 209 } 210} 211 212static void 213at91dci_clocks_off(struct at91dci_softc *sc) 214{ 215 if (!sc->sc_flags.clocks_off) { 216 217 DPRINTFN(5, "\n"); 218 219 /* disable Transceiver */ 220 AT91_UDP_WRITE_4(sc, AT91_UDP_TXVC, AT91_UDP_TXVC_DIS); 221 222 if (sc->sc_clocks_off) { 223 (sc->sc_clocks_off) (sc->sc_clocks_arg); 224 } 225 sc->sc_flags.clocks_off = 1; 226 } 227} 228 229static void 230at91dci_pull_up(struct at91dci_softc *sc) 231{ 232 /* pullup D+, if possible */ 233 234 if (!sc->sc_flags.d_pulled_up && 235 sc->sc_flags.port_powered) { 236 sc->sc_flags.d_pulled_up = 1; 237 (sc->sc_pull_up) (sc->sc_pull_arg); 238 } 239} 240 241static void 242at91dci_pull_down(struct at91dci_softc *sc) 243{ 244 /* pulldown D+, if possible */ 245 246 if (sc->sc_flags.d_pulled_up) { 247 sc->sc_flags.d_pulled_up = 0; 248 (sc->sc_pull_down) (sc->sc_pull_arg); 249 } 250} 251 252static void 253at91dci_wakeup_peer(struct at91dci_softc *sc) 254{ 255 if (!(sc->sc_flags.status_suspend)) { 256 return; 257 } 258 259 AT91_UDP_WRITE_4(sc, AT91_UDP_GSTATE, AT91_UDP_GSTATE_ESR); 260 261 /* wait 8 milliseconds */ 262 /* Wait for reset to complete. */ 263 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 264 265 AT91_UDP_WRITE_4(sc, AT91_UDP_GSTATE, 0); 266} 267 268static void 269at91dci_set_address(struct at91dci_softc *sc, uint8_t addr) 270{ 271 DPRINTFN(5, "addr=%d\n", addr); 272 273 AT91_UDP_WRITE_4(sc, AT91_UDP_FADDR, addr | 274 AT91_UDP_FADDR_EN); 275} 276 277static uint8_t 278at91dci_setup_rx(struct at91dci_td *td) 279{ 280 struct at91dci_softc *sc; 281 struct usb2_device_request req; 282 uint32_t csr; 283 uint32_t temp; 284 uint16_t count; 285 286 /* read out FIFO status */ 287 csr = bus_space_read_4(td->io_tag, td->io_hdl, 288 td->status_reg); 289 290 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder); 291 292 temp = csr; 293 temp &= (AT91_UDP_CSR_RX_DATA_BK0 | 294 AT91_UDP_CSR_RX_DATA_BK1 | 295 AT91_UDP_CSR_STALLSENT | 296 AT91_UDP_CSR_RXSETUP | 297 AT91_UDP_CSR_TXCOMP); 298 299 if (!(csr & AT91_UDP_CSR_RXSETUP)) { 300 goto not_complete; 301 } 302 /* clear did stall */ 303 td->did_stall = 0; 304 305 /* get the packet byte count */ 306 count = (csr & AT91_UDP_CSR_RXBYTECNT) >> 16; 307 308 /* verify data length */ 309 if (count != td->remainder) { 310 DPRINTFN(0, "Invalid SETUP packet " 311 "length, %d bytes\n", count); 312 goto not_complete; 313 } 314 if (count != sizeof(req)) { 315 DPRINTFN(0, "Unsupported SETUP packet " 316 "length, %d bytes\n", count); 317 goto not_complete; 318 } 319 /* receive data */ 320 bus_space_read_multi_1(td->io_tag, td->io_hdl, 321 td->fifo_reg, (void *)&req, sizeof(req)); 322 323 /* copy data into real buffer */ 324 usb2_copy_in(td->pc, 0, &req, sizeof(req)); 325 326 td->offset = sizeof(req); 327 td->remainder = 0; 328 329 /* get pointer to softc */ 330 sc = AT9100_DCI_PC2SC(td->pc); 331 332 /* sneak peek the set address */ 333 if ((req.bmRequestType == UT_WRITE_DEVICE) && 334 (req.bRequest == UR_SET_ADDRESS)) { 335 sc->sc_dv_addr = req.wValue[0] & 0x7F; 336 } else { 337 sc->sc_dv_addr = 0xFF; 338 } 339 340 /* sneak peek the endpoint direction */ 341 if (req.bmRequestType & UE_DIR_IN) { 342 csr |= AT91_UDP_CSR_DIR; 343 } else { 344 csr &= ~AT91_UDP_CSR_DIR; 345 } 346 347 /* write the direction of the control transfer */ 348 AT91_CSR_ACK(csr, temp); 349 bus_space_write_4(td->io_tag, td->io_hdl, 350 td->status_reg, csr); 351 return (0); /* complete */ 352 353not_complete: 354 /* abort any ongoing transfer */ 355 if (!td->did_stall) { 356 DPRINTFN(5, "stalling\n"); 357 temp |= AT91_UDP_CSR_FORCESTALL; 358 td->did_stall = 1; 359 } 360 361 /* clear interrupts, if any */ 362 if (temp) { 363 DPRINTFN(5, "clearing 0x%08x\n", temp); 364 AT91_CSR_ACK(csr, temp); 365 bus_space_write_4(td->io_tag, td->io_hdl, 366 td->status_reg, csr); 367 } 368 return (1); /* not complete */ 369 370} 371 372static uint8_t 373at91dci_data_rx(struct at91dci_td *td) 374{ 375 struct usb2_page_search buf_res; 376 uint32_t csr; 377 uint32_t temp; 378 uint16_t count; 379 uint8_t to; 380 uint8_t got_short; 381 382 to = 2; /* don't loop forever! */ 383 got_short = 0; 384 385 /* check if any of the FIFO banks have data */ 386repeat: 387 /* read out FIFO status */ 388 csr = bus_space_read_4(td->io_tag, td->io_hdl, 389 td->status_reg); 390 391 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder); 392 393 if (csr & AT91_UDP_CSR_RXSETUP) { 394 if (td->remainder == 0) { 395 /* 396 * We are actually complete and have 397 * received the next SETUP 398 */ 399 DPRINTFN(5, "faking complete\n"); 400 return (0); /* complete */ 401 } 402 /* 403 * USB Host Aborted the transfer. 404 */ 405 td->error = 1; 406 return (0); /* complete */ 407 } 408 /* Make sure that "STALLSENT" gets cleared */ 409 temp = csr; 410 temp &= AT91_UDP_CSR_STALLSENT; 411 412 /* check status */ 413 if (!(csr & (AT91_UDP_CSR_RX_DATA_BK0 | 414 AT91_UDP_CSR_RX_DATA_BK1))) { 415 if (temp) { 416 /* write command */ 417 AT91_CSR_ACK(csr, temp); 418 bus_space_write_4(td->io_tag, td->io_hdl, 419 td->status_reg, csr); 420 } 421 return (1); /* not complete */ 422 } 423 /* get the packet byte count */ 424 count = (csr & AT91_UDP_CSR_RXBYTECNT) >> 16; 425 426 /* verify the packet byte count */ 427 if (count != td->max_packet_size) { 428 if (count < td->max_packet_size) { 429 /* we have a short packet */ 430 td->short_pkt = 1; 431 got_short = 1; 432 } else { 433 /* invalid USB packet */ 434 td->error = 1; 435 return (0); /* we are complete */ 436 } 437 } 438 /* verify the packet byte count */ 439 if (count > td->remainder) { 440 /* invalid USB packet */ 441 td->error = 1; 442 return (0); /* we are complete */ 443 } 444 while (count > 0) { 445 usb2_get_page(td->pc, td->offset, &buf_res); 446 447 /* get correct length */ 448 if (buf_res.length > count) { 449 buf_res.length = count; 450 } 451 /* receive data */ 452 bus_space_read_multi_1(td->io_tag, td->io_hdl, 453 td->fifo_reg, buf_res.buffer, buf_res.length); 454 455 /* update counters */ 456 count -= buf_res.length; 457 td->offset += buf_res.length; 458 td->remainder -= buf_res.length; 459 } 460 461 /* clear status bits */ 462 if (td->support_multi_buffer) { 463 if (td->fifo_bank) { 464 td->fifo_bank = 0; 465 temp |= AT91_UDP_CSR_RX_DATA_BK1; 466 } else { 467 td->fifo_bank = 1; 468 temp |= AT91_UDP_CSR_RX_DATA_BK0; 469 } 470 } else { 471 temp |= (AT91_UDP_CSR_RX_DATA_BK0 | 472 AT91_UDP_CSR_RX_DATA_BK1); 473 } 474 475 /* write command */ 476 AT91_CSR_ACK(csr, temp); 477 bus_space_write_4(td->io_tag, td->io_hdl, 478 td->status_reg, csr); 479 480 /* 481 * NOTE: We may have to delay a little bit before 482 * proceeding after clearing the DATA_BK bits. 483 */ 484 485 /* check if we are complete */ 486 if ((td->remainder == 0) || got_short) { 487 if (td->short_pkt) { 488 /* we are complete */ 489 return (0); 490 } 491 /* else need to receive a zero length packet */ 492 } 493 if (--to) { 494 goto repeat; 495 } 496 return (1); /* not complete */ 497} 498 499static uint8_t 500at91dci_data_tx(struct at91dci_td *td) 501{ 502 struct usb2_page_search buf_res; 503 uint32_t csr; 504 uint32_t temp; 505 uint16_t count; 506 uint8_t to; 507 508 to = 2; /* don't loop forever! */ 509 510repeat: 511 512 /* read out FIFO status */ 513 csr = bus_space_read_4(td->io_tag, td->io_hdl, 514 td->status_reg); 515 516 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder); 517 518 if (csr & AT91_UDP_CSR_RXSETUP) { 519 /* 520 * The current transfer was aborted 521 * by the USB Host 522 */ 523 td->error = 1; 524 return (0); /* complete */ 525 } 526 /* Make sure that "STALLSENT" gets cleared */ 527 temp = csr; 528 temp &= AT91_UDP_CSR_STALLSENT; 529 530 if (csr & AT91_UDP_CSR_TXPKTRDY) { 531 if (temp) { 532 /* write command */ 533 AT91_CSR_ACK(csr, temp); 534 bus_space_write_4(td->io_tag, td->io_hdl, 535 td->status_reg, csr); 536 } 537 return (1); /* not complete */ 538 } else { 539 /* clear TXCOMP and set TXPKTRDY */ 540 temp |= (AT91_UDP_CSR_TXCOMP | 541 AT91_UDP_CSR_TXPKTRDY); 542 } 543 544 count = td->max_packet_size; 545 if (td->remainder < count) { 546 /* we have a short packet */ 547 td->short_pkt = 1; 548 count = td->remainder; 549 } 550 while (count > 0) { 551 552 usb2_get_page(td->pc, td->offset, &buf_res); 553 554 /* get correct length */ 555 if (buf_res.length > count) { 556 buf_res.length = count; 557 } 558 /* transmit data */ 559 bus_space_write_multi_1(td->io_tag, td->io_hdl, 560 td->fifo_reg, buf_res.buffer, buf_res.length); 561 562 /* update counters */ 563 count -= buf_res.length; 564 td->offset += buf_res.length; 565 td->remainder -= buf_res.length; 566 } 567 568 /* write command */ 569 AT91_CSR_ACK(csr, temp); 570 bus_space_write_4(td->io_tag, td->io_hdl, 571 td->status_reg, csr); 572 573 /* check remainder */ 574 if (td->remainder == 0) { 575 if (td->short_pkt) { 576 return (0); /* complete */ 577 } 578 /* else we need to transmit a short packet */ 579 } 580 if (--to) { 581 goto repeat; 582 } 583 return (1); /* not complete */ 584} 585 586static uint8_t 587at91dci_data_tx_sync(struct at91dci_td *td) 588{ 589 struct at91dci_softc *sc; 590 uint32_t csr; 591 uint32_t temp; 592 593#if 0 594repeat: 595#endif 596 597 /* read out FIFO status */ 598 csr = bus_space_read_4(td->io_tag, td->io_hdl, 599 td->status_reg); 600 601 DPRINTFN(5, "csr=0x%08x\n", csr); 602 603 if (csr & AT91_UDP_CSR_RXSETUP) { 604 DPRINTFN(5, "faking complete\n"); 605 /* Race condition */ 606 return (0); /* complete */ 607 } 608 temp = csr; 609 temp &= (AT91_UDP_CSR_STALLSENT | 610 AT91_UDP_CSR_TXCOMP); 611 612 /* check status */ 613 if (csr & AT91_UDP_CSR_TXPKTRDY) { 614 goto not_complete; 615 } 616 if (!(csr & AT91_UDP_CSR_TXCOMP)) { 617 goto not_complete; 618 } 619 sc = AT9100_DCI_PC2SC(td->pc); 620 if (sc->sc_dv_addr != 0xFF) { 621 /* 622 * The AT91 has a special requirement with regard to 623 * setting the address and that is to write the new 624 * address before clearing TXCOMP: 625 */ 626 at91dci_set_address(sc, sc->sc_dv_addr); 627 } 628 /* write command */ 629 AT91_CSR_ACK(csr, temp); 630 bus_space_write_4(td->io_tag, td->io_hdl, 631 td->status_reg, csr); 632 633 return (0); /* complete */ 634 635not_complete: 636 if (temp) { 637 /* write command */ 638 AT91_CSR_ACK(csr, temp); 639 bus_space_write_4(td->io_tag, td->io_hdl, 640 td->status_reg, csr); 641 } 642 return (1); /* not complete */ 643} 644 645static uint8_t 646at91dci_xfer_do_fifo(struct usb2_xfer *xfer) 647{ 648 struct at91dci_softc *sc; 649 struct at91dci_td *td; 650 uint8_t temp; 651 652 DPRINTFN(9, "\n"); 653 654 td = xfer->td_transfer_cache; 655 while (1) { 656 if ((td->func) (td)) { 657 /* operation in progress */ 658 break; 659 } 660 if (((void *)td) == xfer->td_transfer_last) { 661 goto done; 662 } 663 if (td->error) { 664 goto done; 665 } else if (td->remainder > 0) { 666 /* 667 * We had a short transfer. If there is no alternate 668 * next, stop processing ! 669 */ 670 if (!td->alt_next) { 671 goto done; 672 } 673 } 674 /* 675 * Fetch the next transfer descriptor and transfer 676 * some flags to the next transfer descriptor 677 */ 678 temp = 0; 679 if (td->fifo_bank) 680 temp |= 1; 681 td = td->obj_next; 682 xfer->td_transfer_cache = td; 683 if (temp & 1) 684 td->fifo_bank = 1; 685 } 686 return (1); /* not complete */ 687 688done: 689 sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 690 temp = (xfer->endpoint & UE_ADDR); 691 692 /* update FIFO bank flag and multi buffer */ 693 if (td->fifo_bank) { 694 sc->sc_ep_flags[temp].fifo_bank = 1; 695 } else { 696 sc->sc_ep_flags[temp].fifo_bank = 0; 697 } 698 699 /* compute all actual lengths */ 700 701 at91dci_standard_done(xfer); 702 703 return (0); /* complete */ 704} 705 706static void 707at91dci_interrupt_poll(struct at91dci_softc *sc) 708{ 709 struct usb2_xfer *xfer; 710 711repeat: 712 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 713 if (!at91dci_xfer_do_fifo(xfer)) { 714 /* queue has been modified */ 715 goto repeat; 716 } 717 } 718} 719 720void 721at91dci_vbus_interrupt(struct at91dci_softc *sc, uint8_t is_on) 722{ 723 DPRINTFN(5, "vbus = %u\n", is_on); 724 725 USB_BUS_LOCK(&sc->sc_bus); 726 if (is_on) { 727 if (!sc->sc_flags.status_vbus) { 728 sc->sc_flags.status_vbus = 1; 729 730 /* complete root HUB interrupt endpoint */ 731 at91dci_root_intr(sc); 732 } 733 } else { 734 if (sc->sc_flags.status_vbus) { 735 sc->sc_flags.status_vbus = 0; 736 sc->sc_flags.status_bus_reset = 0; 737 sc->sc_flags.status_suspend = 0; 738 sc->sc_flags.change_suspend = 0; 739 sc->sc_flags.change_connect = 1; 740 741 /* complete root HUB interrupt endpoint */ 742 at91dci_root_intr(sc); 743 } 744 } 745 USB_BUS_UNLOCK(&sc->sc_bus); 746} 747 748void 749at91dci_interrupt(struct at91dci_softc *sc) 750{ 751 uint32_t status; 752 753 USB_BUS_LOCK(&sc->sc_bus); 754 755 status = AT91_UDP_READ_4(sc, AT91_UDP_ISR); 756 status &= AT91_UDP_INT_DEFAULT; 757 758 if (!status) { 759 USB_BUS_UNLOCK(&sc->sc_bus); 760 return; 761 } 762 /* acknowledge interrupts */ 763 764 AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, status); 765 766 /* check for any bus state change interrupts */ 767 768 if (status & AT91_UDP_INT_BUS) { 769 770 DPRINTFN(5, "real bus interrupt 0x%08x\n", status); 771 772 if (status & AT91_UDP_INT_END_BR) { 773 774 /* set correct state */ 775 sc->sc_flags.status_bus_reset = 1; 776 sc->sc_flags.status_suspend = 0; 777 sc->sc_flags.change_suspend = 0; 778 sc->sc_flags.change_connect = 1; 779 780 /* disable resume interrupt */ 781 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 782 AT91_UDP_INT_RXRSM); 783 /* enable suspend interrupt */ 784 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, 785 AT91_UDP_INT_RXSUSP); 786 } 787 /* 788 * If RXRSM and RXSUSP is set at the same time we interpret 789 * that like RESUME. Resume is set when there is at least 3 790 * milliseconds of inactivity on the USB BUS. 791 */ 792 if (status & AT91_UDP_INT_RXRSM) { 793 if (sc->sc_flags.status_suspend) { 794 sc->sc_flags.status_suspend = 0; 795 sc->sc_flags.change_suspend = 1; 796 797 /* disable resume interrupt */ 798 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 799 AT91_UDP_INT_RXRSM); 800 /* enable suspend interrupt */ 801 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, 802 AT91_UDP_INT_RXSUSP); 803 } 804 } else if (status & AT91_UDP_INT_RXSUSP) { 805 if (!sc->sc_flags.status_suspend) { 806 sc->sc_flags.status_suspend = 1; 807 sc->sc_flags.change_suspend = 1; 808 809 /* disable suspend interrupt */ 810 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 811 AT91_UDP_INT_RXSUSP); 812 813 /* enable resume interrupt */ 814 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, 815 AT91_UDP_INT_RXRSM); 816 } 817 } 818 /* complete root HUB interrupt endpoint */ 819 at91dci_root_intr(sc); 820 } 821 /* check for any endpoint interrupts */ 822 823 if (status & AT91_UDP_INT_EPS) { 824 825 DPRINTFN(5, "real endpoint interrupt 0x%08x\n", status); 826 827 at91dci_interrupt_poll(sc); 828 } 829 USB_BUS_UNLOCK(&sc->sc_bus); 830} 831 832static void 833at91dci_setup_standard_chain_sub(struct at91dci_std_temp *temp) 834{ 835 struct at91dci_td *td; 836 837 /* get current Transfer Descriptor */ 838 td = temp->td_next; 839 temp->td = td; 840 841 /* prepare for next TD */ 842 temp->td_next = td->obj_next; 843 844 /* fill out the Transfer Descriptor */ 845 td->func = temp->func; 846 td->pc = temp->pc; 847 td->offset = temp->offset; 848 td->remainder = temp->len; 849 td->fifo_bank = 0; 850 td->error = 0; 851 td->did_stall = 0; 852 td->short_pkt = temp->short_pkt; 853 td->alt_next = temp->setup_alt_next; 854} 855 856static void 857at91dci_setup_standard_chain(struct usb2_xfer *xfer) 858{ 859 struct at91dci_std_temp temp; 860 struct at91dci_softc *sc; 861 struct at91dci_td *td; 862 uint32_t x; 863 uint8_t ep_no; 864 uint8_t need_sync; 865 866 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 867 xfer->address, UE_GET_ADDR(xfer->endpoint), 868 xfer->sumlen, usb2_get_speed(xfer->xroot->udev)); 869 870 temp.max_frame_size = xfer->max_frame_size; 871 872 td = xfer->td_start[0]; 873 xfer->td_transfer_first = td; 874 xfer->td_transfer_cache = td; 875 876 /* setup temp */ 877 878 temp.td = NULL; 879 temp.td_next = xfer->td_start[0]; 880 temp.offset = 0; 881 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 882 883 sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 884 ep_no = (xfer->endpoint & UE_ADDR); 885 886 /* check if we should prepend a setup message */ 887 888 if (xfer->flags_int.control_xfr) { 889 if (xfer->flags_int.control_hdr) { 890 891 temp.func = &at91dci_setup_rx; 892 temp.len = xfer->frlengths[0]; 893 temp.pc = xfer->frbuffers + 0; 894 temp.short_pkt = temp.len ? 1 : 0; 895 /* check for last frame */ 896 if (xfer->nframes == 1) { 897 /* no STATUS stage yet, SETUP is last */ 898 if (xfer->flags_int.control_act) 899 temp.setup_alt_next = 0; 900 } 901 902 at91dci_setup_standard_chain_sub(&temp); 903 } 904 x = 1; 905 } else { 906 x = 0; 907 } 908 909 if (x != xfer->nframes) { 910 if (xfer->endpoint & UE_DIR_IN) { 911 temp.func = &at91dci_data_tx; 912 need_sync = 1; 913 } else { 914 temp.func = &at91dci_data_rx; 915 need_sync = 0; 916 } 917 918 /* setup "pc" pointer */ 919 temp.pc = xfer->frbuffers + x; 920 } else { 921 need_sync = 0; 922 } 923 while (x != xfer->nframes) { 924 925 /* DATA0 / DATA1 message */ 926 927 temp.len = xfer->frlengths[x]; 928 929 x++; 930 931 if (x == xfer->nframes) { 932 if (xfer->flags_int.control_xfr) { 933 if (xfer->flags_int.control_act) { 934 temp.setup_alt_next = 0; 935 } 936 } else { 937 temp.setup_alt_next = 0; 938 } 939 } 940 if (temp.len == 0) { 941 942 /* make sure that we send an USB packet */ 943 944 temp.short_pkt = 0; 945 946 } else { 947 948 /* regular data transfer */ 949 950 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 951 } 952 953 at91dci_setup_standard_chain_sub(&temp); 954 955 if (xfer->flags_int.isochronous_xfr) { 956 temp.offset += temp.len; 957 } else { 958 /* get next Page Cache pointer */ 959 temp.pc = xfer->frbuffers + x; 960 } 961 } 962 963 /* check for control transfer */ 964 if (xfer->flags_int.control_xfr) { 965 966 /* always setup a valid "pc" pointer for status and sync */ 967 temp.pc = xfer->frbuffers + 0; 968 temp.len = 0; 969 temp.short_pkt = 0; 970 temp.setup_alt_next = 0; 971 972 /* check if we need to sync */ 973 if (need_sync) { 974 /* we need a SYNC point after TX */ 975 temp.func = &at91dci_data_tx_sync; 976 at91dci_setup_standard_chain_sub(&temp); 977 } 978 979 /* check if we should append a status stage */ 980 if (!xfer->flags_int.control_act) { 981 982 /* 983 * Send a DATA1 message and invert the current 984 * endpoint direction. 985 */ 986 if (xfer->endpoint & UE_DIR_IN) { 987 temp.func = &at91dci_data_rx; 988 need_sync = 0; 989 } else { 990 temp.func = &at91dci_data_tx; 991 need_sync = 1; 992 } 993 994 at91dci_setup_standard_chain_sub(&temp); 995 if (need_sync) { 996 /* we need a SYNC point after TX */ 997 temp.func = &at91dci_data_tx_sync; 998 at91dci_setup_standard_chain_sub(&temp); 999 } 1000 } 1001 } 1002 1003 /* must have at least one frame! */ 1004 td = temp.td; 1005 xfer->td_transfer_last = td; 1006 1007 /* setup the correct fifo bank */ 1008 if (sc->sc_ep_flags[ep_no].fifo_bank) { 1009 td = xfer->td_transfer_first; 1010 td->fifo_bank = 1; 1011 } 1012} 1013 1014static void 1015at91dci_timeout(void *arg) 1016{ 1017 struct usb2_xfer *xfer = arg; 1018 1019 DPRINTF("xfer=%p\n", xfer); 1020 1021 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1022 1023 /* transfer is transferred */ 1024 at91dci_device_done(xfer, USB_ERR_TIMEOUT); 1025} 1026 1027static void 1028at91dci_start_standard_chain(struct usb2_xfer *xfer) 1029{ 1030 DPRINTFN(9, "\n"); 1031 1032 /* poll one time */ 1033 if (at91dci_xfer_do_fifo(xfer)) { 1034 1035 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 1036 uint8_t ep_no = xfer->endpoint & UE_ADDR; 1037 1038 /* 1039 * Only enable the endpoint interrupt when we are actually 1040 * waiting for data, hence we are dealing with level 1041 * triggered interrupts ! 1042 */ 1043 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, AT91_UDP_INT_EP(ep_no)); 1044 1045 DPRINTFN(15, "enable interrupts on endpoint %d\n", ep_no); 1046 1047 /* put transfer on interrupt queue */ 1048 usb2_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 1049 1050 /* start timeout, if any */ 1051 if (xfer->timeout != 0) { 1052 usb2_transfer_timeout_ms(xfer, 1053 &at91dci_timeout, xfer->timeout); 1054 } 1055 } 1056} 1057 1058static void 1059at91dci_root_intr(struct at91dci_softc *sc) 1060{ 1061 DPRINTFN(9, "\n"); 1062 1063 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1064 1065 /* set port bit */ 1066 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 1067 1068 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 1069 sizeof(sc->sc_hub_idata)); 1070} 1071 1072static usb2_error_t 1073at91dci_standard_done_sub(struct usb2_xfer *xfer) 1074{ 1075 struct at91dci_td *td; 1076 uint32_t len; 1077 uint8_t error; 1078 1079 DPRINTFN(9, "\n"); 1080 1081 td = xfer->td_transfer_cache; 1082 1083 do { 1084 len = td->remainder; 1085 1086 if (xfer->aframes != xfer->nframes) { 1087 /* 1088 * Verify the length and subtract 1089 * the remainder from "frlengths[]": 1090 */ 1091 if (len > xfer->frlengths[xfer->aframes]) { 1092 td->error = 1; 1093 } else { 1094 xfer->frlengths[xfer->aframes] -= len; 1095 } 1096 } 1097 /* Check for transfer error */ 1098 if (td->error) { 1099 /* the transfer is finished */ 1100 error = 1; 1101 td = NULL; 1102 break; 1103 } 1104 /* Check for short transfer */ 1105 if (len > 0) { 1106 if (xfer->flags_int.short_frames_ok) { 1107 /* follow alt next */ 1108 if (td->alt_next) { 1109 td = td->obj_next; 1110 } else { 1111 td = NULL; 1112 } 1113 } else { 1114 /* the transfer is finished */ 1115 td = NULL; 1116 } 1117 error = 0; 1118 break; 1119 } 1120 td = td->obj_next; 1121 1122 /* this USB frame is complete */ 1123 error = 0; 1124 break; 1125 1126 } while (0); 1127 1128 /* update transfer cache */ 1129 1130 xfer->td_transfer_cache = td; 1131 1132 return (error ? 1133 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1134} 1135 1136static void 1137at91dci_standard_done(struct usb2_xfer *xfer) 1138{ 1139 usb2_error_t err = 0; 1140 1141 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 1142 xfer, xfer->pipe); 1143 1144 /* reset scanner */ 1145 1146 xfer->td_transfer_cache = xfer->td_transfer_first; 1147 1148 if (xfer->flags_int.control_xfr) { 1149 1150 if (xfer->flags_int.control_hdr) { 1151 1152 err = at91dci_standard_done_sub(xfer); 1153 } 1154 xfer->aframes = 1; 1155 1156 if (xfer->td_transfer_cache == NULL) { 1157 goto done; 1158 } 1159 } 1160 while (xfer->aframes != xfer->nframes) { 1161 1162 err = at91dci_standard_done_sub(xfer); 1163 xfer->aframes++; 1164 1165 if (xfer->td_transfer_cache == NULL) { 1166 goto done; 1167 } 1168 } 1169 1170 if (xfer->flags_int.control_xfr && 1171 !xfer->flags_int.control_act) { 1172 1173 err = at91dci_standard_done_sub(xfer); 1174 } 1175done: 1176 at91dci_device_done(xfer, err); 1177} 1178 1179/*------------------------------------------------------------------------* 1180 * at91dci_device_done 1181 * 1182 * NOTE: this function can be called more than one time on the 1183 * same USB transfer! 1184 *------------------------------------------------------------------------*/ 1185static void 1186at91dci_device_done(struct usb2_xfer *xfer, usb2_error_t error) 1187{ 1188 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 1189 uint8_t ep_no; 1190 1191 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1192 1193 DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n", 1194 xfer, xfer->pipe, error); 1195 1196 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 1197 ep_no = (xfer->endpoint & UE_ADDR); 1198 1199 /* disable endpoint interrupt */ 1200 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, AT91_UDP_INT_EP(ep_no)); 1201 1202 DPRINTFN(15, "disable interrupts on endpoint %d\n", ep_no); 1203 } 1204 /* dequeue transfer and start next transfer */ 1205 usb2_transfer_done(xfer, error); 1206} 1207 1208static void 1209at91dci_set_stall(struct usb2_device *udev, struct usb2_xfer *xfer, 1210 struct usb2_pipe *pipe) 1211{ 1212 struct at91dci_softc *sc; 1213 uint32_t csr_val; 1214 uint8_t csr_reg; 1215 1216 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1217 1218 DPRINTFN(5, "pipe=%p\n", pipe); 1219 1220 if (xfer) { 1221 /* cancel any ongoing transfers */ 1222 at91dci_device_done(xfer, USB_ERR_STALLED); 1223 } 1224 /* set FORCESTALL */ 1225 sc = AT9100_DCI_BUS2SC(udev->bus); 1226 csr_reg = (pipe->edesc->bEndpointAddress & UE_ADDR); 1227 csr_reg = AT91_UDP_CSR(csr_reg); 1228 csr_val = AT91_UDP_READ_4(sc, csr_reg); 1229 AT91_CSR_ACK(csr_val, AT91_UDP_CSR_FORCESTALL); 1230 AT91_UDP_WRITE_4(sc, csr_reg, csr_val); 1231} 1232 1233static void 1234at91dci_clear_stall_sub(struct at91dci_softc *sc, uint8_t ep_no, 1235 uint8_t ep_type, uint8_t ep_dir) 1236{ 1237 const struct usb2_hw_ep_profile *pf; 1238 uint32_t csr_val; 1239 uint32_t temp; 1240 uint8_t csr_reg; 1241 uint8_t to; 1242 1243 if (ep_type == UE_CONTROL) { 1244 /* clearing stall is not needed */ 1245 return; 1246 } 1247 /* compute CSR register offset */ 1248 csr_reg = AT91_UDP_CSR(ep_no); 1249 1250 /* compute default CSR value */ 1251 csr_val = 0; 1252 AT91_CSR_ACK(csr_val, 0); 1253 1254 /* disable endpoint */ 1255 AT91_UDP_WRITE_4(sc, csr_reg, csr_val); 1256 1257 /* get endpoint profile */ 1258 at91dci_get_hw_ep_profile(NULL, &pf, ep_no); 1259 1260 /* reset FIFO */ 1261 AT91_UDP_WRITE_4(sc, AT91_UDP_RST, AT91_UDP_RST_EP(ep_no)); 1262 AT91_UDP_WRITE_4(sc, AT91_UDP_RST, 0); 1263 1264 /* 1265 * NOTE: One would assume that a FIFO reset would release the 1266 * FIFO banks aswell, but it doesn't! We have to do this 1267 * manually! 1268 */ 1269 1270 /* release FIFO banks, if any */ 1271 for (to = 0; to != 2; to++) { 1272 1273 /* get csr value */ 1274 csr_val = AT91_UDP_READ_4(sc, csr_reg); 1275 1276 if (csr_val & (AT91_UDP_CSR_RX_DATA_BK0 | 1277 AT91_UDP_CSR_RX_DATA_BK1)) { 1278 /* clear status bits */ 1279 if (pf->support_multi_buffer) { 1280 if (sc->sc_ep_flags[ep_no].fifo_bank) { 1281 sc->sc_ep_flags[ep_no].fifo_bank = 0; 1282 temp = AT91_UDP_CSR_RX_DATA_BK1; 1283 } else { 1284 sc->sc_ep_flags[ep_no].fifo_bank = 1; 1285 temp = AT91_UDP_CSR_RX_DATA_BK0; 1286 } 1287 } else { 1288 temp = (AT91_UDP_CSR_RX_DATA_BK0 | 1289 AT91_UDP_CSR_RX_DATA_BK1); 1290 } 1291 } else { 1292 temp = 0; 1293 } 1294 1295 /* clear FORCESTALL */ 1296 temp |= AT91_UDP_CSR_STALLSENT; 1297 1298 AT91_CSR_ACK(csr_val, temp); 1299 AT91_UDP_WRITE_4(sc, csr_reg, csr_val); 1300 } 1301 1302 /* compute default CSR value */ 1303 csr_val = 0; 1304 AT91_CSR_ACK(csr_val, 0); 1305 1306 /* enable endpoint */ 1307 csr_val &= ~AT91_UDP_CSR_ET_MASK; 1308 csr_val |= AT91_UDP_CSR_EPEDS; 1309 1310 if (ep_type == UE_CONTROL) { 1311 csr_val |= AT91_UDP_CSR_ET_CTRL; 1312 } else { 1313 if (ep_type == UE_BULK) { 1314 csr_val |= AT91_UDP_CSR_ET_BULK; 1315 } else if (ep_type == UE_INTERRUPT) { 1316 csr_val |= AT91_UDP_CSR_ET_INT; 1317 } else { 1318 csr_val |= AT91_UDP_CSR_ET_ISO; 1319 } 1320 if (ep_dir & UE_DIR_IN) { 1321 csr_val |= AT91_UDP_CSR_ET_DIR_IN; 1322 } 1323 } 1324 1325 /* enable endpoint */ 1326 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(ep_no), csr_val); 1327} 1328 1329static void 1330at91dci_clear_stall(struct usb2_device *udev, struct usb2_pipe *pipe) 1331{ 1332 struct at91dci_softc *sc; 1333 struct usb2_endpoint_descriptor *ed; 1334 1335 DPRINTFN(5, "pipe=%p\n", pipe); 1336 1337 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1338 1339 /* check mode */ 1340 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 1341 /* not supported */ 1342 return; 1343 } 1344 /* get softc */ 1345 sc = AT9100_DCI_BUS2SC(udev->bus); 1346 1347 /* get endpoint descriptor */ 1348 ed = pipe->edesc; 1349 1350 /* reset endpoint */ 1351 at91dci_clear_stall_sub(sc, 1352 (ed->bEndpointAddress & UE_ADDR), 1353 (ed->bmAttributes & UE_XFERTYPE), 1354 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1355} 1356 1357usb2_error_t 1358at91dci_init(struct at91dci_softc *sc) 1359{ 1360 uint32_t csr_val; 1361 uint8_t n; 1362 1363 DPRINTF("start\n"); 1364 1365 /* set up the bus structure */ 1366 sc->sc_bus.usbrev = USB_REV_1_1; 1367 sc->sc_bus.methods = &at91dci_bus_methods; 1368 1369 USB_BUS_LOCK(&sc->sc_bus); 1370 1371 /* turn on clocks */ 1372 1373 if (sc->sc_clocks_on) { 1374 (sc->sc_clocks_on) (sc->sc_clocks_arg); 1375 } 1376 /* wait a little for things to stabilise */ 1377 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 1378 1379 /* disable and clear all interrupts */ 1380 1381 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 0xFFFFFFFF); 1382 AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, 0xFFFFFFFF); 1383 1384 /* compute default CSR value */ 1385 1386 csr_val = 0; 1387 AT91_CSR_ACK(csr_val, 0); 1388 1389 /* disable all endpoints */ 1390 1391 for (n = 0; n != AT91_UDP_EP_MAX; n++) { 1392 1393 /* disable endpoint */ 1394 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(n), csr_val); 1395 } 1396 1397 /* enable the control endpoint */ 1398 1399 AT91_CSR_ACK(csr_val, AT91_UDP_CSR_ET_CTRL | 1400 AT91_UDP_CSR_EPEDS); 1401 1402 /* write to FIFO control register */ 1403 1404 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(0), csr_val); 1405 1406 /* enable the interrupts we want */ 1407 1408 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, AT91_UDP_INT_BUS); 1409 1410 /* turn off clocks */ 1411 1412 at91dci_clocks_off(sc); 1413 1414 USB_BUS_UNLOCK(&sc->sc_bus); 1415 1416 /* catch any lost interrupts */ 1417 1418 at91dci_do_poll(&sc->sc_bus); 1419 1420 return (0); /* success */ 1421} 1422 1423void 1424at91dci_uninit(struct at91dci_softc *sc) 1425{ 1426 USB_BUS_LOCK(&sc->sc_bus); 1427 1428 /* disable and clear all interrupts */ 1429 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 0xFFFFFFFF); 1430 AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, 0xFFFFFFFF); 1431 1432 sc->sc_flags.port_powered = 0; 1433 sc->sc_flags.status_vbus = 0; 1434 sc->sc_flags.status_bus_reset = 0; 1435 sc->sc_flags.status_suspend = 0; 1436 sc->sc_flags.change_suspend = 0; 1437 sc->sc_flags.change_connect = 1; 1438 1439 at91dci_pull_down(sc); 1440 at91dci_clocks_off(sc); 1441 USB_BUS_UNLOCK(&sc->sc_bus); 1442} 1443 1444void 1445at91dci_suspend(struct at91dci_softc *sc) 1446{ 1447 return; 1448} 1449 1450void 1451at91dci_resume(struct at91dci_softc *sc) 1452{ 1453 return; 1454} 1455 1456static void 1457at91dci_do_poll(struct usb2_bus *bus) 1458{ 1459 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(bus); 1460 1461 USB_BUS_LOCK(&sc->sc_bus); 1462 at91dci_interrupt_poll(sc); 1463 USB_BUS_UNLOCK(&sc->sc_bus); 1464} 1465 1466/*------------------------------------------------------------------------* 1467 * at91dci bulk support 1468 *------------------------------------------------------------------------*/ 1469static void 1470at91dci_device_bulk_open(struct usb2_xfer *xfer) 1471{ 1472 return; 1473} 1474 1475static void 1476at91dci_device_bulk_close(struct usb2_xfer *xfer) 1477{ 1478 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1479} 1480 1481static void 1482at91dci_device_bulk_enter(struct usb2_xfer *xfer) 1483{ 1484 return; 1485} 1486 1487static void 1488at91dci_device_bulk_start(struct usb2_xfer *xfer) 1489{ 1490 /* setup TDs */ 1491 at91dci_setup_standard_chain(xfer); 1492 at91dci_start_standard_chain(xfer); 1493} 1494 1495struct usb2_pipe_methods at91dci_device_bulk_methods = 1496{ 1497 .open = at91dci_device_bulk_open, 1498 .close = at91dci_device_bulk_close, 1499 .enter = at91dci_device_bulk_enter, 1500 .start = at91dci_device_bulk_start, 1501}; 1502 1503/*------------------------------------------------------------------------* 1504 * at91dci control support 1505 *------------------------------------------------------------------------*/ 1506static void 1507at91dci_device_ctrl_open(struct usb2_xfer *xfer) 1508{ 1509 return; 1510} 1511 1512static void 1513at91dci_device_ctrl_close(struct usb2_xfer *xfer) 1514{ 1515 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1516} 1517 1518static void 1519at91dci_device_ctrl_enter(struct usb2_xfer *xfer) 1520{ 1521 return; 1522} 1523 1524static void 1525at91dci_device_ctrl_start(struct usb2_xfer *xfer) 1526{ 1527 /* setup TDs */ 1528 at91dci_setup_standard_chain(xfer); 1529 at91dci_start_standard_chain(xfer); 1530} 1531 1532struct usb2_pipe_methods at91dci_device_ctrl_methods = 1533{ 1534 .open = at91dci_device_ctrl_open, 1535 .close = at91dci_device_ctrl_close, 1536 .enter = at91dci_device_ctrl_enter, 1537 .start = at91dci_device_ctrl_start, 1538}; 1539 1540/*------------------------------------------------------------------------* 1541 * at91dci interrupt support 1542 *------------------------------------------------------------------------*/ 1543static void 1544at91dci_device_intr_open(struct usb2_xfer *xfer) 1545{ 1546 return; 1547} 1548 1549static void 1550at91dci_device_intr_close(struct usb2_xfer *xfer) 1551{ 1552 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1553} 1554 1555static void 1556at91dci_device_intr_enter(struct usb2_xfer *xfer) 1557{ 1558 return; 1559} 1560 1561static void 1562at91dci_device_intr_start(struct usb2_xfer *xfer) 1563{ 1564 /* setup TDs */ 1565 at91dci_setup_standard_chain(xfer); 1566 at91dci_start_standard_chain(xfer); 1567} 1568 1569struct usb2_pipe_methods at91dci_device_intr_methods = 1570{ 1571 .open = at91dci_device_intr_open, 1572 .close = at91dci_device_intr_close, 1573 .enter = at91dci_device_intr_enter, 1574 .start = at91dci_device_intr_start, 1575}; 1576 1577/*------------------------------------------------------------------------* 1578 * at91dci full speed isochronous support 1579 *------------------------------------------------------------------------*/ 1580static void 1581at91dci_device_isoc_fs_open(struct usb2_xfer *xfer) 1582{ 1583 return; 1584} 1585 1586static void 1587at91dci_device_isoc_fs_close(struct usb2_xfer *xfer) 1588{ 1589 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1590} 1591 1592static void 1593at91dci_device_isoc_fs_enter(struct usb2_xfer *xfer) 1594{ 1595 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 1596 uint32_t temp; 1597 uint32_t nframes; 1598 1599 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 1600 xfer, xfer->pipe->isoc_next, xfer->nframes); 1601 1602 /* get the current frame index */ 1603 1604 nframes = AT91_UDP_READ_4(sc, AT91_UDP_FRM); 1605 1606 /* 1607 * check if the frame index is within the window where the frames 1608 * will be inserted 1609 */ 1610 temp = (nframes - xfer->pipe->isoc_next) & AT91_UDP_FRM_MASK; 1611 1612 if ((xfer->pipe->is_synced == 0) || 1613 (temp < xfer->nframes)) { 1614 /* 1615 * If there is data underflow or the pipe queue is 1616 * empty we schedule the transfer a few frames ahead 1617 * of the current frame position. Else two isochronous 1618 * transfers might overlap. 1619 */ 1620 xfer->pipe->isoc_next = (nframes + 3) & AT91_UDP_FRM_MASK; 1621 xfer->pipe->is_synced = 1; 1622 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next); 1623 } 1624 /* 1625 * compute how many milliseconds the insertion is ahead of the 1626 * current frame position: 1627 */ 1628 temp = (xfer->pipe->isoc_next - nframes) & AT91_UDP_FRM_MASK; 1629 1630 /* 1631 * pre-compute when the isochronous transfer will be finished: 1632 */ 1633 xfer->isoc_time_complete = 1634 usb2_isoc_time_expand(&sc->sc_bus, nframes) + temp + 1635 xfer->nframes; 1636 1637 /* compute frame number for next insertion */ 1638 xfer->pipe->isoc_next += xfer->nframes; 1639 1640 /* setup TDs */ 1641 at91dci_setup_standard_chain(xfer); 1642} 1643 1644static void 1645at91dci_device_isoc_fs_start(struct usb2_xfer *xfer) 1646{ 1647 /* start TD chain */ 1648 at91dci_start_standard_chain(xfer); 1649} 1650 1651struct usb2_pipe_methods at91dci_device_isoc_fs_methods = 1652{ 1653 .open = at91dci_device_isoc_fs_open, 1654 .close = at91dci_device_isoc_fs_close, 1655 .enter = at91dci_device_isoc_fs_enter, 1656 .start = at91dci_device_isoc_fs_start, 1657}; 1658 1659/*------------------------------------------------------------------------* 1660 * at91dci root control support 1661 *------------------------------------------------------------------------* 1662 * Simulate a hardware HUB by handling all the necessary requests. 1663 *------------------------------------------------------------------------*/ 1664 1665static const struct usb2_device_descriptor at91dci_devd = { 1666 .bLength = sizeof(struct usb2_device_descriptor), 1667 .bDescriptorType = UDESC_DEVICE, 1668 .bcdUSB = {0x00, 0x02}, 1669 .bDeviceClass = UDCLASS_HUB, 1670 .bDeviceSubClass = UDSUBCLASS_HUB, 1671 .bDeviceProtocol = UDPROTO_HSHUBSTT, 1672 .bMaxPacketSize = 64, 1673 .bcdDevice = {0x00, 0x01}, 1674 .iManufacturer = 1, 1675 .iProduct = 2, 1676 .bNumConfigurations = 1, 1677}; 1678 1679static const struct usb2_device_qualifier at91dci_odevd = { 1680 .bLength = sizeof(struct usb2_device_qualifier), 1681 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 1682 .bcdUSB = {0x00, 0x02}, 1683 .bDeviceClass = UDCLASS_HUB, 1684 .bDeviceSubClass = UDSUBCLASS_HUB, 1685 .bDeviceProtocol = UDPROTO_FSHUB, 1686 .bMaxPacketSize0 = 0, 1687 .bNumConfigurations = 0, 1688}; 1689 1690static const struct at91dci_config_desc at91dci_confd = { 1691 .confd = { 1692 .bLength = sizeof(struct usb2_config_descriptor), 1693 .bDescriptorType = UDESC_CONFIG, 1694 .wTotalLength[0] = sizeof(at91dci_confd), 1695 .bNumInterface = 1, 1696 .bConfigurationValue = 1, 1697 .iConfiguration = 0, 1698 .bmAttributes = UC_SELF_POWERED, 1699 .bMaxPower = 0, 1700 }, 1701 .ifcd = { 1702 .bLength = sizeof(struct usb2_interface_descriptor), 1703 .bDescriptorType = UDESC_INTERFACE, 1704 .bNumEndpoints = 1, 1705 .bInterfaceClass = UICLASS_HUB, 1706 .bInterfaceSubClass = UISUBCLASS_HUB, 1707 .bInterfaceProtocol = UIPROTO_HSHUBSTT, 1708 }, 1709 .endpd = { 1710 .bLength = sizeof(struct usb2_endpoint_descriptor), 1711 .bDescriptorType = UDESC_ENDPOINT, 1712 .bEndpointAddress = (UE_DIR_IN | AT9100_DCI_INTR_ENDPT), 1713 .bmAttributes = UE_INTERRUPT, 1714 .wMaxPacketSize[0] = 8, 1715 .bInterval = 255, 1716 }, 1717}; 1718 1719static const struct usb2_hub_descriptor_min at91dci_hubd = { 1720 .bDescLength = sizeof(at91dci_hubd), 1721 .bDescriptorType = UDESC_HUB, 1722 .bNbrPorts = 1, 1723 .wHubCharacteristics[0] = 1724 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) & 0xFF, 1725 .wHubCharacteristics[1] = 1726 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) >> 8, 1727 .bPwrOn2PwrGood = 50, 1728 .bHubContrCurrent = 0, 1729 .DeviceRemovable = {0}, /* port is removable */ 1730}; 1731 1732#define STRING_LANG \ 1733 0x09, 0x04, /* American English */ 1734 1735#define STRING_VENDOR \ 1736 'A', 0, 'T', 0, 'M', 0, 'E', 0, 'L', 0 1737 1738#define STRING_PRODUCT \ 1739 'D', 0, 'C', 0, 'I', 0, ' ', 0, 'R', 0, \ 1740 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \ 1741 'U', 0, 'B', 0, 1742 1743USB_MAKE_STRING_DESC(STRING_LANG, at91dci_langtab); 1744USB_MAKE_STRING_DESC(STRING_VENDOR, at91dci_vendor); 1745USB_MAKE_STRING_DESC(STRING_PRODUCT, at91dci_product); 1746 1747static usb2_error_t 1748at91dci_roothub_exec(struct usb2_device *udev, 1749 struct usb2_device_request *req, const void **pptr, uint16_t *plength) 1750{ 1751 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(udev->bus); 1752 const void *ptr; 1753 uint16_t len; 1754 uint16_t value; 1755 uint16_t index; 1756 usb2_error_t err; 1757 1758 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1759 1760 /* buffer reset */ 1761 ptr = (const void *)&sc->sc_hub_temp; 1762 len = 0; 1763 err = 0; 1764 1765 value = UGETW(req->wValue); 1766 index = UGETW(req->wIndex); 1767 1768 /* demultiplex the control request */ 1769 1770 switch (req->bmRequestType) { 1771 case UT_READ_DEVICE: 1772 switch (req->bRequest) { 1773 case UR_GET_DESCRIPTOR: 1774 goto tr_handle_get_descriptor; 1775 case UR_GET_CONFIG: 1776 goto tr_handle_get_config; 1777 case UR_GET_STATUS: 1778 goto tr_handle_get_status; 1779 default: 1780 goto tr_stalled; 1781 } 1782 break; 1783 1784 case UT_WRITE_DEVICE: 1785 switch (req->bRequest) { 1786 case UR_SET_ADDRESS: 1787 goto tr_handle_set_address; 1788 case UR_SET_CONFIG: 1789 goto tr_handle_set_config; 1790 case UR_CLEAR_FEATURE: 1791 goto tr_valid; /* nop */ 1792 case UR_SET_DESCRIPTOR: 1793 goto tr_valid; /* nop */ 1794 case UR_SET_FEATURE: 1795 default: 1796 goto tr_stalled; 1797 } 1798 break; 1799 1800 case UT_WRITE_ENDPOINT: 1801 switch (req->bRequest) { 1802 case UR_CLEAR_FEATURE: 1803 switch (UGETW(req->wValue)) { 1804 case UF_ENDPOINT_HALT: 1805 goto tr_handle_clear_halt; 1806 case UF_DEVICE_REMOTE_WAKEUP: 1807 goto tr_handle_clear_wakeup; 1808 default: 1809 goto tr_stalled; 1810 } 1811 break; 1812 case UR_SET_FEATURE: 1813 switch (UGETW(req->wValue)) { 1814 case UF_ENDPOINT_HALT: 1815 goto tr_handle_set_halt; 1816 case UF_DEVICE_REMOTE_WAKEUP: 1817 goto tr_handle_set_wakeup; 1818 default: 1819 goto tr_stalled; 1820 } 1821 break; 1822 case UR_SYNCH_FRAME: 1823 goto tr_valid; /* nop */ 1824 default: 1825 goto tr_stalled; 1826 } 1827 break; 1828 1829 case UT_READ_ENDPOINT: 1830 switch (req->bRequest) { 1831 case UR_GET_STATUS: 1832 goto tr_handle_get_ep_status; 1833 default: 1834 goto tr_stalled; 1835 } 1836 break; 1837 1838 case UT_WRITE_INTERFACE: 1839 switch (req->bRequest) { 1840 case UR_SET_INTERFACE: 1841 goto tr_handle_set_interface; 1842 case UR_CLEAR_FEATURE: 1843 goto tr_valid; /* nop */ 1844 case UR_SET_FEATURE: 1845 default: 1846 goto tr_stalled; 1847 } 1848 break; 1849 1850 case UT_READ_INTERFACE: 1851 switch (req->bRequest) { 1852 case UR_GET_INTERFACE: 1853 goto tr_handle_get_interface; 1854 case UR_GET_STATUS: 1855 goto tr_handle_get_iface_status; 1856 default: 1857 goto tr_stalled; 1858 } 1859 break; 1860 1861 case UT_WRITE_CLASS_INTERFACE: 1862 case UT_WRITE_VENDOR_INTERFACE: 1863 /* XXX forward */ 1864 break; 1865 1866 case UT_READ_CLASS_INTERFACE: 1867 case UT_READ_VENDOR_INTERFACE: 1868 /* XXX forward */ 1869 break; 1870 1871 case UT_WRITE_CLASS_DEVICE: 1872 switch (req->bRequest) { 1873 case UR_CLEAR_FEATURE: 1874 goto tr_valid; 1875 case UR_SET_DESCRIPTOR: 1876 case UR_SET_FEATURE: 1877 break; 1878 default: 1879 goto tr_stalled; 1880 } 1881 break; 1882 1883 case UT_WRITE_CLASS_OTHER: 1884 switch (req->bRequest) { 1885 case UR_CLEAR_FEATURE: 1886 goto tr_handle_clear_port_feature; 1887 case UR_SET_FEATURE: 1888 goto tr_handle_set_port_feature; 1889 case UR_CLEAR_TT_BUFFER: 1890 case UR_RESET_TT: 1891 case UR_STOP_TT: 1892 goto tr_valid; 1893 1894 default: 1895 goto tr_stalled; 1896 } 1897 break; 1898 1899 case UT_READ_CLASS_OTHER: 1900 switch (req->bRequest) { 1901 case UR_GET_TT_STATE: 1902 goto tr_handle_get_tt_state; 1903 case UR_GET_STATUS: 1904 goto tr_handle_get_port_status; 1905 default: 1906 goto tr_stalled; 1907 } 1908 break; 1909 1910 case UT_READ_CLASS_DEVICE: 1911 switch (req->bRequest) { 1912 case UR_GET_DESCRIPTOR: 1913 goto tr_handle_get_class_descriptor; 1914 case UR_GET_STATUS: 1915 goto tr_handle_get_class_status; 1916 1917 default: 1918 goto tr_stalled; 1919 } 1920 break; 1921 default: 1922 goto tr_stalled; 1923 } 1924 goto tr_valid; 1925 1926tr_handle_get_descriptor: 1927 switch (value >> 8) { 1928 case UDESC_DEVICE: 1929 if (value & 0xff) { 1930 goto tr_stalled; 1931 } 1932 len = sizeof(at91dci_devd); 1933 ptr = (const void *)&at91dci_devd; 1934 goto tr_valid; 1935 case UDESC_CONFIG: 1936 if (value & 0xff) { 1937 goto tr_stalled; 1938 } 1939 len = sizeof(at91dci_confd); 1940 ptr = (const void *)&at91dci_confd; 1941 goto tr_valid; 1942 case UDESC_STRING: 1943 switch (value & 0xff) { 1944 case 0: /* Language table */ 1945 len = sizeof(at91dci_langtab); 1946 ptr = (const void *)&at91dci_langtab; 1947 goto tr_valid; 1948 1949 case 1: /* Vendor */ 1950 len = sizeof(at91dci_vendor); 1951 ptr = (const void *)&at91dci_vendor; 1952 goto tr_valid; 1953 1954 case 2: /* Product */ 1955 len = sizeof(at91dci_product); 1956 ptr = (const void *)&at91dci_product; 1957 goto tr_valid; 1958 default: 1959 break; 1960 } 1961 break; 1962 default: 1963 goto tr_stalled; 1964 } 1965 goto tr_stalled; 1966 1967tr_handle_get_config: 1968 len = 1; 1969 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 1970 goto tr_valid; 1971 1972tr_handle_get_status: 1973 len = 2; 1974 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 1975 goto tr_valid; 1976 1977tr_handle_set_address: 1978 if (value & 0xFF00) { 1979 goto tr_stalled; 1980 } 1981 sc->sc_rt_addr = value; 1982 goto tr_valid; 1983 1984tr_handle_set_config: 1985 if (value >= 2) { 1986 goto tr_stalled; 1987 } 1988 sc->sc_conf = value; 1989 goto tr_valid; 1990 1991tr_handle_get_interface: 1992 len = 1; 1993 sc->sc_hub_temp.wValue[0] = 0; 1994 goto tr_valid; 1995 1996tr_handle_get_tt_state: 1997tr_handle_get_class_status: 1998tr_handle_get_iface_status: 1999tr_handle_get_ep_status: 2000 len = 2; 2001 USETW(sc->sc_hub_temp.wValue, 0); 2002 goto tr_valid; 2003 2004tr_handle_set_halt: 2005tr_handle_set_interface: 2006tr_handle_set_wakeup: 2007tr_handle_clear_wakeup: 2008tr_handle_clear_halt: 2009 goto tr_valid; 2010 2011tr_handle_clear_port_feature: 2012 if (index != 1) { 2013 goto tr_stalled; 2014 } 2015 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 2016 2017 switch (value) { 2018 case UHF_PORT_SUSPEND: 2019 at91dci_wakeup_peer(sc); 2020 break; 2021 2022 case UHF_PORT_ENABLE: 2023 sc->sc_flags.port_enabled = 0; 2024 break; 2025 2026 case UHF_PORT_TEST: 2027 case UHF_PORT_INDICATOR: 2028 case UHF_C_PORT_ENABLE: 2029 case UHF_C_PORT_OVER_CURRENT: 2030 case UHF_C_PORT_RESET: 2031 /* nops */ 2032 break; 2033 case UHF_PORT_POWER: 2034 sc->sc_flags.port_powered = 0; 2035 at91dci_pull_down(sc); 2036 at91dci_clocks_off(sc); 2037 break; 2038 case UHF_C_PORT_CONNECTION: 2039 sc->sc_flags.change_connect = 0; 2040 break; 2041 case UHF_C_PORT_SUSPEND: 2042 sc->sc_flags.change_suspend = 0; 2043 break; 2044 default: 2045 err = USB_ERR_IOERROR; 2046 goto done; 2047 } 2048 goto tr_valid; 2049 2050tr_handle_set_port_feature: 2051 if (index != 1) { 2052 goto tr_stalled; 2053 } 2054 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 2055 2056 switch (value) { 2057 case UHF_PORT_ENABLE: 2058 sc->sc_flags.port_enabled = 1; 2059 break; 2060 case UHF_PORT_SUSPEND: 2061 case UHF_PORT_RESET: 2062 case UHF_PORT_TEST: 2063 case UHF_PORT_INDICATOR: 2064 /* nops */ 2065 break; 2066 case UHF_PORT_POWER: 2067 sc->sc_flags.port_powered = 1; 2068 break; 2069 default: 2070 err = USB_ERR_IOERROR; 2071 goto done; 2072 } 2073 goto tr_valid; 2074 2075tr_handle_get_port_status: 2076 2077 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 2078 2079 if (index != 1) { 2080 goto tr_stalled; 2081 } 2082 if (sc->sc_flags.status_vbus) { 2083 at91dci_clocks_on(sc); 2084 at91dci_pull_up(sc); 2085 } else { 2086 at91dci_pull_down(sc); 2087 at91dci_clocks_off(sc); 2088 } 2089 2090 /* Select FULL-speed and Device Side Mode */ 2091 2092 value = UPS_PORT_MODE_DEVICE; 2093 2094 if (sc->sc_flags.port_powered) { 2095 value |= UPS_PORT_POWER; 2096 } 2097 if (sc->sc_flags.port_enabled) { 2098 value |= UPS_PORT_ENABLED; 2099 } 2100 if (sc->sc_flags.status_vbus && 2101 sc->sc_flags.status_bus_reset) { 2102 value |= UPS_CURRENT_CONNECT_STATUS; 2103 } 2104 if (sc->sc_flags.status_suspend) { 2105 value |= UPS_SUSPEND; 2106 } 2107 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 2108 2109 value = 0; 2110 2111 if (sc->sc_flags.change_connect) { 2112 value |= UPS_C_CONNECT_STATUS; 2113 2114 if (sc->sc_flags.status_vbus && 2115 sc->sc_flags.status_bus_reset) { 2116 /* reset endpoint flags */ 2117 bzero(sc->sc_ep_flags, sizeof(sc->sc_ep_flags)); 2118 } 2119 } 2120 if (sc->sc_flags.change_suspend) { 2121 value |= UPS_C_SUSPEND; 2122 } 2123 USETW(sc->sc_hub_temp.ps.wPortChange, value); 2124 len = sizeof(sc->sc_hub_temp.ps); 2125 goto tr_valid; 2126 2127tr_handle_get_class_descriptor: 2128 if (value & 0xFF) { 2129 goto tr_stalled; 2130 } 2131 ptr = (const void *)&at91dci_hubd; 2132 len = sizeof(at91dci_hubd); 2133 goto tr_valid; 2134 2135tr_stalled: 2136 err = USB_ERR_STALLED; 2137tr_valid: 2138done: 2139 *plength = len; 2140 *pptr = ptr; 2141 return (err); 2142} 2143 2144static void 2145at91dci_xfer_setup(struct usb2_setup_params *parm) 2146{ 2147 const struct usb2_hw_ep_profile *pf; 2148 struct at91dci_softc *sc; 2149 struct usb2_xfer *xfer; 2150 void *last_obj; 2151 uint32_t ntd; 2152 uint32_t n; 2153 uint8_t ep_no; 2154 2155 sc = AT9100_DCI_BUS2SC(parm->udev->bus); 2156 xfer = parm->curr_xfer; 2157 2158 /* 2159 * NOTE: This driver does not use any of the parameters that 2160 * are computed from the following values. Just set some 2161 * reasonable dummies: 2162 */ 2163 parm->hc_max_packet_size = 0x500; 2164 parm->hc_max_packet_count = 1; 2165 parm->hc_max_frame_size = 0x500; 2166 2167 usb2_transfer_setup_sub(parm); 2168 2169 /* 2170 * compute maximum number of TDs 2171 */ 2172 if (parm->methods == &at91dci_device_ctrl_methods) { 2173 2174 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 2175 + 1 /* SYNC 2 */ ; 2176 2177 } else if (parm->methods == &at91dci_device_bulk_methods) { 2178 2179 ntd = xfer->nframes + 1 /* SYNC */ ; 2180 2181 } else if (parm->methods == &at91dci_device_intr_methods) { 2182 2183 ntd = xfer->nframes + 1 /* SYNC */ ; 2184 2185 } else if (parm->methods == &at91dci_device_isoc_fs_methods) { 2186 2187 ntd = xfer->nframes + 1 /* SYNC */ ; 2188 2189 } else { 2190 2191 ntd = 0; 2192 } 2193 2194 /* 2195 * check if "usb2_transfer_setup_sub" set an error 2196 */ 2197 if (parm->err) { 2198 return; 2199 } 2200 /* 2201 * allocate transfer descriptors 2202 */ 2203 last_obj = NULL; 2204 2205 /* 2206 * get profile stuff 2207 */ 2208 if (ntd) { 2209 2210 ep_no = xfer->endpoint & UE_ADDR; 2211 at91dci_get_hw_ep_profile(parm->udev, &pf, ep_no); 2212 2213 if (pf == NULL) { 2214 /* should not happen */ 2215 parm->err = USB_ERR_INVAL; 2216 return; 2217 } 2218 } else { 2219 ep_no = 0; 2220 pf = NULL; 2221 } 2222 2223 /* align data */ 2224 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2225 2226 for (n = 0; n != ntd; n++) { 2227 2228 struct at91dci_td *td; 2229 2230 if (parm->buf) { 2231 2232 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2233 2234 /* init TD */ 2235 td->io_tag = sc->sc_io_tag; 2236 td->io_hdl = sc->sc_io_hdl; 2237 td->max_packet_size = xfer->max_packet_size; 2238 td->status_reg = AT91_UDP_CSR(ep_no); 2239 td->fifo_reg = AT91_UDP_FDR(ep_no); 2240 if (pf->support_multi_buffer) { 2241 td->support_multi_buffer = 1; 2242 } 2243 td->obj_next = last_obj; 2244 2245 last_obj = td; 2246 } 2247 parm->size[0] += sizeof(*td); 2248 } 2249 2250 xfer->td_start[0] = last_obj; 2251} 2252 2253static void 2254at91dci_xfer_unsetup(struct usb2_xfer *xfer) 2255{ 2256 return; 2257} 2258 2259static void 2260at91dci_pipe_init(struct usb2_device *udev, struct usb2_endpoint_descriptor *edesc, 2261 struct usb2_pipe *pipe) 2262{ 2263 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(udev->bus); 2264 2265 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 2266 pipe, udev->address, 2267 edesc->bEndpointAddress, udev->flags.usb_mode, 2268 sc->sc_rt_addr); 2269 2270 if (udev->device_index != sc->sc_rt_addr) { 2271 2272 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 2273 /* not supported */ 2274 return; 2275 } 2276 if (udev->speed != USB_SPEED_FULL) { 2277 /* not supported */ 2278 return; 2279 } 2280 switch (edesc->bmAttributes & UE_XFERTYPE) { 2281 case UE_CONTROL: 2282 pipe->methods = &at91dci_device_ctrl_methods; 2283 break; 2284 case UE_INTERRUPT: 2285 pipe->methods = &at91dci_device_intr_methods; 2286 break; 2287 case UE_ISOCHRONOUS: 2288 pipe->methods = &at91dci_device_isoc_fs_methods; 2289 break; 2290 case UE_BULK: 2291 pipe->methods = &at91dci_device_bulk_methods; 2292 break; 2293 default: 2294 /* do nothing */ 2295 break; 2296 } 2297 } 2298} 2299 2300struct usb2_bus_methods at91dci_bus_methods = 2301{ 2302 .pipe_init = &at91dci_pipe_init, 2303 .xfer_setup = &at91dci_xfer_setup, 2304 .xfer_unsetup = &at91dci_xfer_unsetup, 2305 .get_hw_ep_profile = &at91dci_get_hw_ep_profile, 2306 .set_stall = &at91dci_set_stall, 2307 .clear_stall = &at91dci_clear_stall, 2308 .roothub_exec = &at91dci_roothub_exec, 2309}; 2310