at91dci.c revision 188983
1#include <sys/cdefs.h> 2__FBSDID("$FreeBSD: head/sys/dev/usb/controller/at91dci.c 188983 2009-02-24 03:39:13Z thompsa $"); 3 4/*- 5 * Copyright (c) 2007-2008 Hans Petter Selasky. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * This file contains the driver for the AT91 series USB Device 31 * Controller 32 */ 33 34/* 35 * Thanks to "David Brownell" for helping out regarding the hardware 36 * endpoint profiles. 37 */ 38 39/* 40 * NOTE: The "fifo_bank" is not reset in hardware when the endpoint is 41 * reset ! 42 * 43 * NOTE: When the chip detects BUS-reset it will also reset the 44 * endpoints, Function-address and more. 45 */ 46 47#include <dev/usb/usb.h> 48#include <dev/usb/usb_mfunc.h> 49#include <dev/usb/usb_error.h> 50#include <dev/usb/usb_defs.h> 51 52#define USB_DEBUG_VAR at91dcidebug 53 54#include <dev/usb/usb_core.h> 55#include <dev/usb/usb_debug.h> 56#include <dev/usb/usb_busdma.h> 57#include <dev/usb/usb_process.h> 58#include <dev/usb/usb_sw_transfer.h> 59#include <dev/usb/usb_transfer.h> 60#include <dev/usb/usb_device.h> 61#include <dev/usb/usb_hub.h> 62#include <dev/usb/usb_util.h> 63 64#include <dev/usb/usb_controller.h> 65#include <dev/usb/usb_bus.h> 66#include <dev/usb/controller/at91dci.h> 67 68#define AT9100_DCI_BUS2SC(bus) \ 69 ((struct at91dci_softc *)(((uint8_t *)(bus)) - \ 70 USB_P2U(&(((struct at91dci_softc *)0)->sc_bus)))) 71 72#define AT9100_DCI_PC2SC(pc) \ 73 AT9100_DCI_BUS2SC((pc)->tag_parent->info->bus) 74 75#if USB_DEBUG 76static int at91dcidebug = 0; 77 78SYSCTL_NODE(_hw_usb2, OID_AUTO, at91dci, CTLFLAG_RW, 0, "USB at91dci"); 79SYSCTL_INT(_hw_usb2_at91dci, OID_AUTO, debug, CTLFLAG_RW, 80 &at91dcidebug, 0, "at91dci debug level"); 81#endif 82 83#define AT9100_DCI_INTR_ENDPT 1 84 85/* prototypes */ 86 87struct usb2_bus_methods at91dci_bus_methods; 88struct usb2_pipe_methods at91dci_device_bulk_methods; 89struct usb2_pipe_methods at91dci_device_ctrl_methods; 90struct usb2_pipe_methods at91dci_device_intr_methods; 91struct usb2_pipe_methods at91dci_device_isoc_fs_methods; 92struct usb2_pipe_methods at91dci_root_ctrl_methods; 93struct usb2_pipe_methods at91dci_root_intr_methods; 94 95static at91dci_cmd_t at91dci_setup_rx; 96static at91dci_cmd_t at91dci_data_rx; 97static at91dci_cmd_t at91dci_data_tx; 98static at91dci_cmd_t at91dci_data_tx_sync; 99static void at91dci_device_done(struct usb2_xfer *, usb2_error_t); 100static void at91dci_do_poll(struct usb2_bus *); 101static void at91dci_root_ctrl_poll(struct at91dci_softc *); 102static void at91dci_standard_done(struct usb2_xfer *); 103 104static usb2_sw_transfer_func_t at91dci_root_intr_done; 105static usb2_sw_transfer_func_t at91dci_root_ctrl_done; 106 107/* 108 * NOTE: Some of the bits in the CSR register have inverse meaning so 109 * we need a helper macro when acknowledging events: 110 */ 111#define AT91_CSR_ACK(csr, what) do { \ 112 (csr) &= ~((AT91_UDP_CSR_FORCESTALL| \ 113 AT91_UDP_CSR_TXPKTRDY| \ 114 AT91_UDP_CSR_RXBYTECNT) ^ (what));\ 115 (csr) |= ((AT91_UDP_CSR_RX_DATA_BK0| \ 116 AT91_UDP_CSR_RX_DATA_BK1| \ 117 AT91_UDP_CSR_TXCOMP| \ 118 AT91_UDP_CSR_RXSETUP| \ 119 AT91_UDP_CSR_STALLSENT) ^ (what)); \ 120} while (0) 121 122/* 123 * Here is a list of what the chip supports. 124 * Probably it supports more than listed here! 125 */ 126static const struct usb2_hw_ep_profile 127 at91dci_ep_profile[AT91_UDP_EP_MAX] = { 128 129 [0] = { 130 .max_in_frame_size = 8, 131 .max_out_frame_size = 8, 132 .is_simplex = 1, 133 .support_control = 1, 134 }, 135 [1] = { 136 .max_in_frame_size = 64, 137 .max_out_frame_size = 64, 138 .is_simplex = 1, 139 .support_multi_buffer = 1, 140 .support_bulk = 1, 141 .support_interrupt = 1, 142 .support_isochronous = 1, 143 .support_in = 1, 144 .support_out = 1, 145 }, 146 [2] = { 147 .max_in_frame_size = 64, 148 .max_out_frame_size = 64, 149 .is_simplex = 1, 150 .support_multi_buffer = 1, 151 .support_bulk = 1, 152 .support_interrupt = 1, 153 .support_isochronous = 1, 154 .support_in = 1, 155 .support_out = 1, 156 }, 157 [3] = { 158 /* can also do BULK */ 159 .max_in_frame_size = 8, 160 .max_out_frame_size = 8, 161 .is_simplex = 1, 162 .support_interrupt = 1, 163 .support_in = 1, 164 .support_out = 1, 165 }, 166 [4] = { 167 .max_in_frame_size = 256, 168 .max_out_frame_size = 256, 169 .is_simplex = 1, 170 .support_multi_buffer = 1, 171 .support_bulk = 1, 172 .support_interrupt = 1, 173 .support_isochronous = 1, 174 .support_in = 1, 175 .support_out = 1, 176 }, 177 [5] = { 178 .max_in_frame_size = 256, 179 .max_out_frame_size = 256, 180 .is_simplex = 1, 181 .support_multi_buffer = 1, 182 .support_bulk = 1, 183 .support_interrupt = 1, 184 .support_isochronous = 1, 185 .support_in = 1, 186 .support_out = 1, 187 }, 188}; 189 190static void 191at91dci_get_hw_ep_profile(struct usb2_device *udev, 192 const struct usb2_hw_ep_profile **ppf, uint8_t ep_addr) 193{ 194 if (ep_addr < AT91_UDP_EP_MAX) { 195 *ppf = (at91dci_ep_profile + ep_addr); 196 } else { 197 *ppf = NULL; 198 } 199} 200 201static void 202at91dci_clocks_on(struct at91dci_softc *sc) 203{ 204 if (sc->sc_flags.clocks_off && 205 sc->sc_flags.port_powered) { 206 207 DPRINTFN(5, "\n"); 208 209 if (sc->sc_clocks_on) { 210 (sc->sc_clocks_on) (sc->sc_clocks_arg); 211 } 212 sc->sc_flags.clocks_off = 0; 213 214 /* enable Transceiver */ 215 AT91_UDP_WRITE_4(sc, AT91_UDP_TXVC, 0); 216 } 217} 218 219static void 220at91dci_clocks_off(struct at91dci_softc *sc) 221{ 222 if (!sc->sc_flags.clocks_off) { 223 224 DPRINTFN(5, "\n"); 225 226 /* disable Transceiver */ 227 AT91_UDP_WRITE_4(sc, AT91_UDP_TXVC, AT91_UDP_TXVC_DIS); 228 229 if (sc->sc_clocks_off) { 230 (sc->sc_clocks_off) (sc->sc_clocks_arg); 231 } 232 sc->sc_flags.clocks_off = 1; 233 } 234} 235 236static void 237at91dci_pull_up(struct at91dci_softc *sc) 238{ 239 /* pullup D+, if possible */ 240 241 if (!sc->sc_flags.d_pulled_up && 242 sc->sc_flags.port_powered) { 243 sc->sc_flags.d_pulled_up = 1; 244 (sc->sc_pull_up) (sc->sc_pull_arg); 245 } 246} 247 248static void 249at91dci_pull_down(struct at91dci_softc *sc) 250{ 251 /* pulldown D+, if possible */ 252 253 if (sc->sc_flags.d_pulled_up) { 254 sc->sc_flags.d_pulled_up = 0; 255 (sc->sc_pull_down) (sc->sc_pull_arg); 256 } 257} 258 259static void 260at91dci_wakeup_peer(struct usb2_xfer *xfer) 261{ 262 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 263 264 if (!(sc->sc_flags.status_suspend)) { 265 return; 266 } 267 268 AT91_UDP_WRITE_4(sc, AT91_UDP_GSTATE, AT91_UDP_GSTATE_ESR); 269 270 /* wait 8 milliseconds */ 271 /* Wait for reset to complete. */ 272 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 273 274 AT91_UDP_WRITE_4(sc, AT91_UDP_GSTATE, 0); 275} 276 277static void 278at91dci_set_address(struct at91dci_softc *sc, uint8_t addr) 279{ 280 DPRINTFN(5, "addr=%d\n", addr); 281 282 AT91_UDP_WRITE_4(sc, AT91_UDP_FADDR, addr | 283 AT91_UDP_FADDR_EN); 284} 285 286static uint8_t 287at91dci_setup_rx(struct at91dci_td *td) 288{ 289 struct at91dci_softc *sc; 290 struct usb2_device_request req; 291 uint32_t csr; 292 uint32_t temp; 293 uint16_t count; 294 295 /* read out FIFO status */ 296 csr = bus_space_read_4(td->io_tag, td->io_hdl, 297 td->status_reg); 298 299 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder); 300 301 temp = csr; 302 temp &= (AT91_UDP_CSR_RX_DATA_BK0 | 303 AT91_UDP_CSR_RX_DATA_BK1 | 304 AT91_UDP_CSR_STALLSENT | 305 AT91_UDP_CSR_RXSETUP | 306 AT91_UDP_CSR_TXCOMP); 307 308 if (!(csr & AT91_UDP_CSR_RXSETUP)) { 309 /* abort any ongoing transfer */ 310 if (!td->did_stall) { 311 DPRINTFN(5, "stalling\n"); 312 temp |= AT91_UDP_CSR_FORCESTALL; 313 td->did_stall = 1; 314 } 315 goto not_complete; 316 } 317 /* get the packet byte count */ 318 count = (csr & AT91_UDP_CSR_RXBYTECNT) >> 16; 319 320 /* verify data length */ 321 if (count != td->remainder) { 322 DPRINTFN(0, "Invalid SETUP packet " 323 "length, %d bytes\n", count); 324 goto not_complete; 325 } 326 if (count != sizeof(req)) { 327 DPRINTFN(0, "Unsupported SETUP packet " 328 "length, %d bytes\n", count); 329 goto not_complete; 330 } 331 /* receive data */ 332 bus_space_read_multi_1(td->io_tag, td->io_hdl, 333 td->fifo_reg, (void *)&req, sizeof(req)); 334 335 /* copy data into real buffer */ 336 usb2_copy_in(td->pc, 0, &req, sizeof(req)); 337 338 td->offset = sizeof(req); 339 td->remainder = 0; 340 341 /* get pointer to softc */ 342 sc = AT9100_DCI_PC2SC(td->pc); 343 344 /* sneak peek the set address */ 345 if ((req.bmRequestType == UT_WRITE_DEVICE) && 346 (req.bRequest == UR_SET_ADDRESS)) { 347 sc->sc_dv_addr = req.wValue[0] & 0x7F; 348 } else { 349 sc->sc_dv_addr = 0xFF; 350 } 351 352 /* sneak peek the endpoint direction */ 353 if (req.bmRequestType & UE_DIR_IN) { 354 csr |= AT91_UDP_CSR_DIR; 355 } else { 356 csr &= ~AT91_UDP_CSR_DIR; 357 } 358 359 /* write the direction of the control transfer */ 360 AT91_CSR_ACK(csr, temp); 361 bus_space_write_4(td->io_tag, td->io_hdl, 362 td->status_reg, csr); 363 return (0); /* complete */ 364 365not_complete: 366 /* clear interrupts, if any */ 367 if (temp) { 368 DPRINTFN(5, "clearing 0x%08x\n", temp); 369 AT91_CSR_ACK(csr, temp); 370 bus_space_write_4(td->io_tag, td->io_hdl, 371 td->status_reg, csr); 372 } 373 return (1); /* not complete */ 374 375} 376 377static uint8_t 378at91dci_data_rx(struct at91dci_td *td) 379{ 380 struct usb2_page_search buf_res; 381 uint32_t csr; 382 uint32_t temp; 383 uint16_t count; 384 uint8_t to; 385 uint8_t got_short; 386 387 to = 2; /* don't loop forever! */ 388 got_short = 0; 389 390 /* check if any of the FIFO banks have data */ 391repeat: 392 /* read out FIFO status */ 393 csr = bus_space_read_4(td->io_tag, td->io_hdl, 394 td->status_reg); 395 396 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder); 397 398 if (csr & AT91_UDP_CSR_RXSETUP) { 399 if (td->remainder == 0) { 400 /* 401 * We are actually complete and have 402 * received the next SETUP 403 */ 404 DPRINTFN(5, "faking complete\n"); 405 return (0); /* complete */ 406 } 407 /* 408 * USB Host Aborted the transfer. 409 */ 410 td->error = 1; 411 return (0); /* complete */ 412 } 413 /* Make sure that "STALLSENT" gets cleared */ 414 temp = csr; 415 temp &= AT91_UDP_CSR_STALLSENT; 416 417 /* check status */ 418 if (!(csr & (AT91_UDP_CSR_RX_DATA_BK0 | 419 AT91_UDP_CSR_RX_DATA_BK1))) { 420 if (temp) { 421 /* write command */ 422 AT91_CSR_ACK(csr, temp); 423 bus_space_write_4(td->io_tag, td->io_hdl, 424 td->status_reg, csr); 425 } 426 return (1); /* not complete */ 427 } 428 /* get the packet byte count */ 429 count = (csr & AT91_UDP_CSR_RXBYTECNT) >> 16; 430 431 /* verify the packet byte count */ 432 if (count != td->max_packet_size) { 433 if (count < td->max_packet_size) { 434 /* we have a short packet */ 435 td->short_pkt = 1; 436 got_short = 1; 437 } else { 438 /* invalid USB packet */ 439 td->error = 1; 440 return (0); /* we are complete */ 441 } 442 } 443 /* verify the packet byte count */ 444 if (count > td->remainder) { 445 /* invalid USB packet */ 446 td->error = 1; 447 return (0); /* we are complete */ 448 } 449 while (count > 0) { 450 usb2_get_page(td->pc, td->offset, &buf_res); 451 452 /* get correct length */ 453 if (buf_res.length > count) { 454 buf_res.length = count; 455 } 456 /* receive data */ 457 bus_space_read_multi_1(td->io_tag, td->io_hdl, 458 td->fifo_reg, buf_res.buffer, buf_res.length); 459 460 /* update counters */ 461 count -= buf_res.length; 462 td->offset += buf_res.length; 463 td->remainder -= buf_res.length; 464 } 465 466 /* clear status bits */ 467 if (td->support_multi_buffer) { 468 if (td->fifo_bank) { 469 td->fifo_bank = 0; 470 temp |= AT91_UDP_CSR_RX_DATA_BK1; 471 } else { 472 td->fifo_bank = 1; 473 temp |= AT91_UDP_CSR_RX_DATA_BK0; 474 } 475 } else { 476 temp |= (AT91_UDP_CSR_RX_DATA_BK0 | 477 AT91_UDP_CSR_RX_DATA_BK1); 478 } 479 480 /* write command */ 481 AT91_CSR_ACK(csr, temp); 482 bus_space_write_4(td->io_tag, td->io_hdl, 483 td->status_reg, csr); 484 485 /* 486 * NOTE: We may have to delay a little bit before 487 * proceeding after clearing the DATA_BK bits. 488 */ 489 490 /* check if we are complete */ 491 if ((td->remainder == 0) || got_short) { 492 if (td->short_pkt) { 493 /* we are complete */ 494 return (0); 495 } 496 /* else need to receive a zero length packet */ 497 } 498 if (--to) { 499 goto repeat; 500 } 501 return (1); /* not complete */ 502} 503 504static uint8_t 505at91dci_data_tx(struct at91dci_td *td) 506{ 507 struct usb2_page_search buf_res; 508 uint32_t csr; 509 uint32_t temp; 510 uint16_t count; 511 uint8_t to; 512 513 to = 2; /* don't loop forever! */ 514 515repeat: 516 517 /* read out FIFO status */ 518 csr = bus_space_read_4(td->io_tag, td->io_hdl, 519 td->status_reg); 520 521 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder); 522 523 if (csr & AT91_UDP_CSR_RXSETUP) { 524 /* 525 * The current transfer was aborted 526 * by the USB Host 527 */ 528 td->error = 1; 529 return (0); /* complete */ 530 } 531 /* Make sure that "STALLSENT" gets cleared */ 532 temp = csr; 533 temp &= AT91_UDP_CSR_STALLSENT; 534 535 if (csr & AT91_UDP_CSR_TXPKTRDY) { 536 if (temp) { 537 /* write command */ 538 AT91_CSR_ACK(csr, temp); 539 bus_space_write_4(td->io_tag, td->io_hdl, 540 td->status_reg, csr); 541 } 542 return (1); /* not complete */ 543 } else { 544 /* clear TXCOMP and set TXPKTRDY */ 545 temp |= (AT91_UDP_CSR_TXCOMP | 546 AT91_UDP_CSR_TXPKTRDY); 547 } 548 549 count = td->max_packet_size; 550 if (td->remainder < count) { 551 /* we have a short packet */ 552 td->short_pkt = 1; 553 count = td->remainder; 554 } 555 while (count > 0) { 556 557 usb2_get_page(td->pc, td->offset, &buf_res); 558 559 /* get correct length */ 560 if (buf_res.length > count) { 561 buf_res.length = count; 562 } 563 /* transmit data */ 564 bus_space_write_multi_1(td->io_tag, td->io_hdl, 565 td->fifo_reg, buf_res.buffer, buf_res.length); 566 567 /* update counters */ 568 count -= buf_res.length; 569 td->offset += buf_res.length; 570 td->remainder -= buf_res.length; 571 } 572 573 /* write command */ 574 AT91_CSR_ACK(csr, temp); 575 bus_space_write_4(td->io_tag, td->io_hdl, 576 td->status_reg, csr); 577 578 /* check remainder */ 579 if (td->remainder == 0) { 580 if (td->short_pkt) { 581 return (0); /* complete */ 582 } 583 /* else we need to transmit a short packet */ 584 } 585 if (--to) { 586 goto repeat; 587 } 588 return (1); /* not complete */ 589} 590 591static uint8_t 592at91dci_data_tx_sync(struct at91dci_td *td) 593{ 594 struct at91dci_softc *sc; 595 uint32_t csr; 596 uint32_t temp; 597 598#if 0 599repeat: 600#endif 601 602 /* read out FIFO status */ 603 csr = bus_space_read_4(td->io_tag, td->io_hdl, 604 td->status_reg); 605 606 DPRINTFN(5, "csr=0x%08x\n", csr); 607 608 if (csr & AT91_UDP_CSR_RXSETUP) { 609 DPRINTFN(5, "faking complete\n"); 610 /* Race condition */ 611 return (0); /* complete */ 612 } 613 temp = csr; 614 temp &= (AT91_UDP_CSR_STALLSENT | 615 AT91_UDP_CSR_TXCOMP); 616 617 /* check status */ 618 if (csr & AT91_UDP_CSR_TXPKTRDY) { 619 goto not_complete; 620 } 621 if (!(csr & AT91_UDP_CSR_TXCOMP)) { 622 goto not_complete; 623 } 624 sc = AT9100_DCI_PC2SC(td->pc); 625 if (sc->sc_dv_addr != 0xFF) { 626 /* 627 * The AT91 has a special requirement with regard to 628 * setting the address and that is to write the new 629 * address before clearing TXCOMP: 630 */ 631 at91dci_set_address(sc, sc->sc_dv_addr); 632 } 633 /* write command */ 634 AT91_CSR_ACK(csr, temp); 635 bus_space_write_4(td->io_tag, td->io_hdl, 636 td->status_reg, csr); 637 638 return (0); /* complete */ 639 640not_complete: 641 if (temp) { 642 /* write command */ 643 AT91_CSR_ACK(csr, temp); 644 bus_space_write_4(td->io_tag, td->io_hdl, 645 td->status_reg, csr); 646 } 647 return (1); /* not complete */ 648} 649 650static uint8_t 651at91dci_xfer_do_fifo(struct usb2_xfer *xfer) 652{ 653 struct at91dci_softc *sc; 654 struct at91dci_td *td; 655 uint8_t temp; 656 657 DPRINTFN(9, "\n"); 658 659 td = xfer->td_transfer_cache; 660 while (1) { 661 if ((td->func) (td)) { 662 /* operation in progress */ 663 break; 664 } 665 if (((void *)td) == xfer->td_transfer_last) { 666 goto done; 667 } 668 if (td->error) { 669 goto done; 670 } else if (td->remainder > 0) { 671 /* 672 * We had a short transfer. If there is no alternate 673 * next, stop processing ! 674 */ 675 if (!td->alt_next) { 676 goto done; 677 } 678 } 679 /* 680 * Fetch the next transfer descriptor and transfer 681 * some flags to the next transfer descriptor 682 */ 683 temp = 0; 684 if (td->fifo_bank) 685 temp |= 1; 686 td = td->obj_next; 687 xfer->td_transfer_cache = td; 688 if (temp & 1) 689 td->fifo_bank = 1; 690 } 691 return (1); /* not complete */ 692 693done: 694 sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 695 temp = (xfer->endpoint & UE_ADDR); 696 697 /* update FIFO bank flag and multi buffer */ 698 if (td->fifo_bank) { 699 sc->sc_ep_flags[temp].fifo_bank = 1; 700 } else { 701 sc->sc_ep_flags[temp].fifo_bank = 0; 702 } 703 704 /* compute all actual lengths */ 705 706 at91dci_standard_done(xfer); 707 708 return (0); /* complete */ 709} 710 711static void 712at91dci_interrupt_poll(struct at91dci_softc *sc) 713{ 714 struct usb2_xfer *xfer; 715 716repeat: 717 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 718 if (!at91dci_xfer_do_fifo(xfer)) { 719 /* queue has been modified */ 720 goto repeat; 721 } 722 } 723} 724 725void 726at91dci_vbus_interrupt(struct at91dci_softc *sc, uint8_t is_on) 727{ 728 DPRINTFN(5, "vbus = %u\n", is_on); 729 730 USB_BUS_LOCK(&sc->sc_bus); 731 if (is_on) { 732 if (!sc->sc_flags.status_vbus) { 733 sc->sc_flags.status_vbus = 1; 734 735 /* complete root HUB interrupt endpoint */ 736 737 usb2_sw_transfer(&sc->sc_root_intr, 738 &at91dci_root_intr_done); 739 } 740 } else { 741 if (sc->sc_flags.status_vbus) { 742 sc->sc_flags.status_vbus = 0; 743 sc->sc_flags.status_bus_reset = 0; 744 sc->sc_flags.status_suspend = 0; 745 sc->sc_flags.change_suspend = 0; 746 sc->sc_flags.change_connect = 1; 747 748 /* complete root HUB interrupt endpoint */ 749 750 usb2_sw_transfer(&sc->sc_root_intr, 751 &at91dci_root_intr_done); 752 } 753 } 754 USB_BUS_UNLOCK(&sc->sc_bus); 755} 756 757void 758at91dci_interrupt(struct at91dci_softc *sc) 759{ 760 uint32_t status; 761 762 USB_BUS_LOCK(&sc->sc_bus); 763 764 status = AT91_UDP_READ_4(sc, AT91_UDP_ISR); 765 status &= AT91_UDP_INT_DEFAULT; 766 767 if (!status) { 768 USB_BUS_UNLOCK(&sc->sc_bus); 769 return; 770 } 771 /* acknowledge interrupts */ 772 773 AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, status); 774 775 /* check for any bus state change interrupts */ 776 777 if (status & AT91_UDP_INT_BUS) { 778 779 DPRINTFN(5, "real bus interrupt 0x%08x\n", status); 780 781 if (status & AT91_UDP_INT_END_BR) { 782 783 /* set correct state */ 784 sc->sc_flags.status_bus_reset = 1; 785 sc->sc_flags.status_suspend = 0; 786 sc->sc_flags.change_suspend = 0; 787 sc->sc_flags.change_connect = 1; 788 789 /* disable resume interrupt */ 790 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 791 AT91_UDP_INT_RXRSM); 792 /* enable suspend interrupt */ 793 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, 794 AT91_UDP_INT_RXSUSP); 795 } 796 /* 797 * If RXRSM and RXSUSP is set at the same time we interpret 798 * that like RESUME. Resume is set when there is at least 3 799 * milliseconds of inactivity on the USB BUS. 800 */ 801 if (status & AT91_UDP_INT_RXRSM) { 802 if (sc->sc_flags.status_suspend) { 803 sc->sc_flags.status_suspend = 0; 804 sc->sc_flags.change_suspend = 1; 805 806 /* disable resume interrupt */ 807 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 808 AT91_UDP_INT_RXRSM); 809 /* enable suspend interrupt */ 810 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, 811 AT91_UDP_INT_RXSUSP); 812 } 813 } else if (status & AT91_UDP_INT_RXSUSP) { 814 if (!sc->sc_flags.status_suspend) { 815 sc->sc_flags.status_suspend = 1; 816 sc->sc_flags.change_suspend = 1; 817 818 /* disable suspend interrupt */ 819 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 820 AT91_UDP_INT_RXSUSP); 821 822 /* enable resume interrupt */ 823 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, 824 AT91_UDP_INT_RXRSM); 825 } 826 } 827 /* complete root HUB interrupt endpoint */ 828 829 usb2_sw_transfer(&sc->sc_root_intr, 830 &at91dci_root_intr_done); 831 } 832 /* check for any endpoint interrupts */ 833 834 if (status & AT91_UDP_INT_EPS) { 835 836 DPRINTFN(5, "real endpoint interrupt 0x%08x\n", status); 837 838 at91dci_interrupt_poll(sc); 839 } 840 USB_BUS_UNLOCK(&sc->sc_bus); 841} 842 843static void 844at91dci_setup_standard_chain_sub(struct at91dci_std_temp *temp) 845{ 846 struct at91dci_td *td; 847 848 /* get current Transfer Descriptor */ 849 td = temp->td_next; 850 temp->td = td; 851 852 /* prepare for next TD */ 853 temp->td_next = td->obj_next; 854 855 /* fill out the Transfer Descriptor */ 856 td->func = temp->func; 857 td->pc = temp->pc; 858 td->offset = temp->offset; 859 td->remainder = temp->len; 860 td->fifo_bank = 0; 861 td->error = 0; 862 td->did_stall = 0; 863 td->short_pkt = temp->short_pkt; 864 td->alt_next = temp->setup_alt_next; 865} 866 867static void 868at91dci_setup_standard_chain(struct usb2_xfer *xfer) 869{ 870 struct at91dci_std_temp temp; 871 struct at91dci_softc *sc; 872 struct at91dci_td *td; 873 uint32_t x; 874 uint8_t ep_no; 875 uint8_t need_sync; 876 877 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 878 xfer->address, UE_GET_ADDR(xfer->endpoint), 879 xfer->sumlen, usb2_get_speed(xfer->xroot->udev)); 880 881 temp.max_frame_size = xfer->max_frame_size; 882 883 td = xfer->td_start[0]; 884 xfer->td_transfer_first = td; 885 xfer->td_transfer_cache = td; 886 887 /* setup temp */ 888 889 temp.td = NULL; 890 temp.td_next = xfer->td_start[0]; 891 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 892 temp.offset = 0; 893 894 sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 895 ep_no = (xfer->endpoint & UE_ADDR); 896 897 /* check if we should prepend a setup message */ 898 899 if (xfer->flags_int.control_xfr) { 900 if (xfer->flags_int.control_hdr) { 901 902 temp.func = &at91dci_setup_rx; 903 temp.len = xfer->frlengths[0]; 904 temp.pc = xfer->frbuffers + 0; 905 temp.short_pkt = temp.len ? 1 : 0; 906 907 at91dci_setup_standard_chain_sub(&temp); 908 } 909 x = 1; 910 } else { 911 x = 0; 912 } 913 914 if (x != xfer->nframes) { 915 if (xfer->endpoint & UE_DIR_IN) { 916 temp.func = &at91dci_data_tx; 917 need_sync = 1; 918 } else { 919 temp.func = &at91dci_data_rx; 920 need_sync = 0; 921 } 922 923 /* setup "pc" pointer */ 924 temp.pc = xfer->frbuffers + x; 925 } else { 926 need_sync = 0; 927 } 928 while (x != xfer->nframes) { 929 930 /* DATA0 / DATA1 message */ 931 932 temp.len = xfer->frlengths[x]; 933 934 x++; 935 936 if (x == xfer->nframes) { 937 temp.setup_alt_next = 0; 938 } 939 if (temp.len == 0) { 940 941 /* make sure that we send an USB packet */ 942 943 temp.short_pkt = 0; 944 945 } else { 946 947 /* regular data transfer */ 948 949 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 950 } 951 952 at91dci_setup_standard_chain_sub(&temp); 953 954 if (xfer->flags_int.isochronous_xfr) { 955 temp.offset += temp.len; 956 } else { 957 /* get next Page Cache pointer */ 958 temp.pc = xfer->frbuffers + x; 959 } 960 } 961 962 /* always setup a valid "pc" pointer for status and sync */ 963 temp.pc = xfer->frbuffers + 0; 964 965 /* check if we need to sync */ 966 if (need_sync && xfer->flags_int.control_xfr) { 967 968 /* we need a SYNC point after TX */ 969 temp.func = &at91dci_data_tx_sync; 970 temp.len = 0; 971 temp.short_pkt = 0; 972 973 at91dci_setup_standard_chain_sub(&temp); 974 } 975 /* check if we should append a status stage */ 976 if (xfer->flags_int.control_xfr && 977 !xfer->flags_int.control_act) { 978 979 /* 980 * Send a DATA1 message and invert the current 981 * endpoint direction. 982 */ 983 if (xfer->endpoint & UE_DIR_IN) { 984 temp.func = &at91dci_data_rx; 985 need_sync = 0; 986 } else { 987 temp.func = &at91dci_data_tx; 988 need_sync = 1; 989 } 990 temp.len = 0; 991 temp.short_pkt = 0; 992 993 at91dci_setup_standard_chain_sub(&temp); 994 if (need_sync) { 995 /* we need a SYNC point after TX */ 996 temp.func = &at91dci_data_tx_sync; 997 temp.len = 0; 998 temp.short_pkt = 0; 999 1000 at91dci_setup_standard_chain_sub(&temp); 1001 } 1002 } 1003 /* must have at least one frame! */ 1004 td = temp.td; 1005 xfer->td_transfer_last = td; 1006 1007 /* setup the correct fifo bank */ 1008 if (sc->sc_ep_flags[ep_no].fifo_bank) { 1009 td = xfer->td_transfer_first; 1010 td->fifo_bank = 1; 1011 } 1012} 1013 1014static void 1015at91dci_timeout(void *arg) 1016{ 1017 struct usb2_xfer *xfer = arg; 1018 1019 DPRINTF("xfer=%p\n", xfer); 1020 1021 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1022 1023 /* transfer is transferred */ 1024 at91dci_device_done(xfer, USB_ERR_TIMEOUT); 1025} 1026 1027static void 1028at91dci_start_standard_chain(struct usb2_xfer *xfer) 1029{ 1030 DPRINTFN(9, "\n"); 1031 1032 /* poll one time */ 1033 if (at91dci_xfer_do_fifo(xfer)) { 1034 1035 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 1036 uint8_t ep_no = xfer->endpoint & UE_ADDR; 1037 1038 /* 1039 * Only enable the endpoint interrupt when we are actually 1040 * waiting for data, hence we are dealing with level 1041 * triggered interrupts ! 1042 */ 1043 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, AT91_UDP_INT_EP(ep_no)); 1044 1045 DPRINTFN(15, "enable interrupts on endpoint %d\n", ep_no); 1046 1047 /* put transfer on interrupt queue */ 1048 usb2_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 1049 1050 /* start timeout, if any */ 1051 if (xfer->timeout != 0) { 1052 usb2_transfer_timeout_ms(xfer, 1053 &at91dci_timeout, xfer->timeout); 1054 } 1055 } 1056} 1057 1058static void 1059at91dci_root_intr_done(struct usb2_xfer *xfer, 1060 struct usb2_sw_transfer *std) 1061{ 1062 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 1063 1064 DPRINTFN(9, "\n"); 1065 1066 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1067 1068 if (std->state != USB_SW_TR_PRE_DATA) { 1069 if (std->state == USB_SW_TR_PRE_CALLBACK) { 1070 /* transfer transferred */ 1071 at91dci_device_done(xfer, std->err); 1072 } 1073 goto done; 1074 } 1075 /* setup buffer */ 1076 std->ptr = sc->sc_hub_idata; 1077 std->len = sizeof(sc->sc_hub_idata); 1078 1079 /* set port bit */ 1080 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 1081 1082done: 1083 return; 1084} 1085 1086static usb2_error_t 1087at91dci_standard_done_sub(struct usb2_xfer *xfer) 1088{ 1089 struct at91dci_td *td; 1090 uint32_t len; 1091 uint8_t error; 1092 1093 DPRINTFN(9, "\n"); 1094 1095 td = xfer->td_transfer_cache; 1096 1097 do { 1098 len = td->remainder; 1099 1100 if (xfer->aframes != xfer->nframes) { 1101 /* 1102 * Verify the length and subtract 1103 * the remainder from "frlengths[]": 1104 */ 1105 if (len > xfer->frlengths[xfer->aframes]) { 1106 td->error = 1; 1107 } else { 1108 xfer->frlengths[xfer->aframes] -= len; 1109 } 1110 } 1111 /* Check for transfer error */ 1112 if (td->error) { 1113 /* the transfer is finished */ 1114 error = 1; 1115 td = NULL; 1116 break; 1117 } 1118 /* Check for short transfer */ 1119 if (len > 0) { 1120 if (xfer->flags_int.short_frames_ok) { 1121 /* follow alt next */ 1122 if (td->alt_next) { 1123 td = td->obj_next; 1124 } else { 1125 td = NULL; 1126 } 1127 } else { 1128 /* the transfer is finished */ 1129 td = NULL; 1130 } 1131 error = 0; 1132 break; 1133 } 1134 td = td->obj_next; 1135 1136 /* this USB frame is complete */ 1137 error = 0; 1138 break; 1139 1140 } while (0); 1141 1142 /* update transfer cache */ 1143 1144 xfer->td_transfer_cache = td; 1145 1146 return (error ? 1147 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1148} 1149 1150static void 1151at91dci_standard_done(struct usb2_xfer *xfer) 1152{ 1153 usb2_error_t err = 0; 1154 1155 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 1156 xfer, xfer->pipe); 1157 1158 /* reset scanner */ 1159 1160 xfer->td_transfer_cache = xfer->td_transfer_first; 1161 1162 if (xfer->flags_int.control_xfr) { 1163 1164 if (xfer->flags_int.control_hdr) { 1165 1166 err = at91dci_standard_done_sub(xfer); 1167 } 1168 xfer->aframes = 1; 1169 1170 if (xfer->td_transfer_cache == NULL) { 1171 goto done; 1172 } 1173 } 1174 while (xfer->aframes != xfer->nframes) { 1175 1176 err = at91dci_standard_done_sub(xfer); 1177 xfer->aframes++; 1178 1179 if (xfer->td_transfer_cache == NULL) { 1180 goto done; 1181 } 1182 } 1183 1184 if (xfer->flags_int.control_xfr && 1185 !xfer->flags_int.control_act) { 1186 1187 err = at91dci_standard_done_sub(xfer); 1188 } 1189done: 1190 at91dci_device_done(xfer, err); 1191} 1192 1193/*------------------------------------------------------------------------* 1194 * at91dci_device_done 1195 * 1196 * NOTE: this function can be called more than one time on the 1197 * same USB transfer! 1198 *------------------------------------------------------------------------*/ 1199static void 1200at91dci_device_done(struct usb2_xfer *xfer, usb2_error_t error) 1201{ 1202 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 1203 uint8_t ep_no; 1204 1205 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1206 1207 DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n", 1208 xfer, xfer->pipe, error); 1209 1210 if (xfer->flags_int.usb2_mode == USB_MODE_DEVICE) { 1211 ep_no = (xfer->endpoint & UE_ADDR); 1212 1213 /* disable endpoint interrupt */ 1214 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, AT91_UDP_INT_EP(ep_no)); 1215 1216 DPRINTFN(15, "disable interrupts on endpoint %d\n", ep_no); 1217 } 1218 /* dequeue transfer and start next transfer */ 1219 usb2_transfer_done(xfer, error); 1220} 1221 1222static void 1223at91dci_set_stall(struct usb2_device *udev, struct usb2_xfer *xfer, 1224 struct usb2_pipe *pipe) 1225{ 1226 struct at91dci_softc *sc; 1227 uint32_t csr_val; 1228 uint8_t csr_reg; 1229 1230 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1231 1232 DPRINTFN(5, "pipe=%p\n", pipe); 1233 1234 if (xfer) { 1235 /* cancel any ongoing transfers */ 1236 at91dci_device_done(xfer, USB_ERR_STALLED); 1237 } 1238 /* set FORCESTALL */ 1239 sc = AT9100_DCI_BUS2SC(udev->bus); 1240 csr_reg = (pipe->edesc->bEndpointAddress & UE_ADDR); 1241 csr_reg = AT91_UDP_CSR(csr_reg); 1242 csr_val = AT91_UDP_READ_4(sc, csr_reg); 1243 AT91_CSR_ACK(csr_val, AT91_UDP_CSR_FORCESTALL); 1244 AT91_UDP_WRITE_4(sc, csr_reg, csr_val); 1245} 1246 1247static void 1248at91dci_clear_stall_sub(struct at91dci_softc *sc, uint8_t ep_no, 1249 uint8_t ep_type, uint8_t ep_dir) 1250{ 1251 const struct usb2_hw_ep_profile *pf; 1252 uint32_t csr_val; 1253 uint32_t temp; 1254 uint8_t csr_reg; 1255 uint8_t to; 1256 1257 if (ep_type == UE_CONTROL) { 1258 /* clearing stall is not needed */ 1259 return; 1260 } 1261 /* compute CSR register offset */ 1262 csr_reg = AT91_UDP_CSR(ep_no); 1263 1264 /* compute default CSR value */ 1265 csr_val = 0; 1266 AT91_CSR_ACK(csr_val, 0); 1267 1268 /* disable endpoint */ 1269 AT91_UDP_WRITE_4(sc, csr_reg, csr_val); 1270 1271 /* get endpoint profile */ 1272 at91dci_get_hw_ep_profile(NULL, &pf, ep_no); 1273 1274 /* reset FIFO */ 1275 AT91_UDP_WRITE_4(sc, AT91_UDP_RST, AT91_UDP_RST_EP(ep_no)); 1276 AT91_UDP_WRITE_4(sc, AT91_UDP_RST, 0); 1277 1278 /* 1279 * NOTE: One would assume that a FIFO reset would release the 1280 * FIFO banks aswell, but it doesn't! We have to do this 1281 * manually! 1282 */ 1283 1284 /* release FIFO banks, if any */ 1285 for (to = 0; to != 2; to++) { 1286 1287 /* get csr value */ 1288 csr_val = AT91_UDP_READ_4(sc, csr_reg); 1289 1290 if (csr_val & (AT91_UDP_CSR_RX_DATA_BK0 | 1291 AT91_UDP_CSR_RX_DATA_BK1)) { 1292 /* clear status bits */ 1293 if (pf->support_multi_buffer) { 1294 if (sc->sc_ep_flags[ep_no].fifo_bank) { 1295 sc->sc_ep_flags[ep_no].fifo_bank = 0; 1296 temp = AT91_UDP_CSR_RX_DATA_BK1; 1297 } else { 1298 sc->sc_ep_flags[ep_no].fifo_bank = 1; 1299 temp = AT91_UDP_CSR_RX_DATA_BK0; 1300 } 1301 } else { 1302 temp = (AT91_UDP_CSR_RX_DATA_BK0 | 1303 AT91_UDP_CSR_RX_DATA_BK1); 1304 } 1305 } else { 1306 temp = 0; 1307 } 1308 1309 /* clear FORCESTALL */ 1310 temp |= AT91_UDP_CSR_STALLSENT; 1311 1312 AT91_CSR_ACK(csr_val, temp); 1313 AT91_UDP_WRITE_4(sc, csr_reg, csr_val); 1314 } 1315 1316 /* compute default CSR value */ 1317 csr_val = 0; 1318 AT91_CSR_ACK(csr_val, 0); 1319 1320 /* enable endpoint */ 1321 csr_val &= ~AT91_UDP_CSR_ET_MASK; 1322 csr_val |= AT91_UDP_CSR_EPEDS; 1323 1324 if (ep_type == UE_CONTROL) { 1325 csr_val |= AT91_UDP_CSR_ET_CTRL; 1326 } else { 1327 if (ep_type == UE_BULK) { 1328 csr_val |= AT91_UDP_CSR_ET_BULK; 1329 } else if (ep_type == UE_INTERRUPT) { 1330 csr_val |= AT91_UDP_CSR_ET_INT; 1331 } else { 1332 csr_val |= AT91_UDP_CSR_ET_ISO; 1333 } 1334 if (ep_dir & UE_DIR_IN) { 1335 csr_val |= AT91_UDP_CSR_ET_DIR_IN; 1336 } 1337 } 1338 1339 /* enable endpoint */ 1340 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(ep_no), csr_val); 1341} 1342 1343static void 1344at91dci_clear_stall(struct usb2_device *udev, struct usb2_pipe *pipe) 1345{ 1346 struct at91dci_softc *sc; 1347 struct usb2_endpoint_descriptor *ed; 1348 1349 DPRINTFN(5, "pipe=%p\n", pipe); 1350 1351 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1352 1353 /* check mode */ 1354 if (udev->flags.usb2_mode != USB_MODE_DEVICE) { 1355 /* not supported */ 1356 return; 1357 } 1358 /* get softc */ 1359 sc = AT9100_DCI_BUS2SC(udev->bus); 1360 1361 /* get endpoint descriptor */ 1362 ed = pipe->edesc; 1363 1364 /* reset endpoint */ 1365 at91dci_clear_stall_sub(sc, 1366 (ed->bEndpointAddress & UE_ADDR), 1367 (ed->bmAttributes & UE_XFERTYPE), 1368 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1369} 1370 1371usb2_error_t 1372at91dci_init(struct at91dci_softc *sc) 1373{ 1374 uint32_t csr_val; 1375 uint8_t n; 1376 1377 DPRINTF("start\n"); 1378 1379 /* set up the bus structure */ 1380 sc->sc_bus.usbrev = USB_REV_1_1; 1381 sc->sc_bus.methods = &at91dci_bus_methods; 1382 1383 USB_BUS_LOCK(&sc->sc_bus); 1384 1385 /* turn on clocks */ 1386 1387 if (sc->sc_clocks_on) { 1388 (sc->sc_clocks_on) (sc->sc_clocks_arg); 1389 } 1390 /* wait a little for things to stabilise */ 1391 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 1392 1393 /* disable and clear all interrupts */ 1394 1395 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 0xFFFFFFFF); 1396 AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, 0xFFFFFFFF); 1397 1398 /* compute default CSR value */ 1399 1400 csr_val = 0; 1401 AT91_CSR_ACK(csr_val, 0); 1402 1403 /* disable all endpoints */ 1404 1405 for (n = 0; n != AT91_UDP_EP_MAX; n++) { 1406 1407 /* disable endpoint */ 1408 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(n), csr_val); 1409 } 1410 1411 /* enable the control endpoint */ 1412 1413 AT91_CSR_ACK(csr_val, AT91_UDP_CSR_ET_CTRL | 1414 AT91_UDP_CSR_EPEDS); 1415 1416 /* write to FIFO control register */ 1417 1418 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(0), csr_val); 1419 1420 /* enable the interrupts we want */ 1421 1422 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, AT91_UDP_INT_BUS); 1423 1424 /* turn off clocks */ 1425 1426 at91dci_clocks_off(sc); 1427 1428 USB_BUS_UNLOCK(&sc->sc_bus); 1429 1430 /* catch any lost interrupts */ 1431 1432 at91dci_do_poll(&sc->sc_bus); 1433 1434 return (0); /* success */ 1435} 1436 1437void 1438at91dci_uninit(struct at91dci_softc *sc) 1439{ 1440 USB_BUS_LOCK(&sc->sc_bus); 1441 1442 /* disable and clear all interrupts */ 1443 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 0xFFFFFFFF); 1444 AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, 0xFFFFFFFF); 1445 1446 sc->sc_flags.port_powered = 0; 1447 sc->sc_flags.status_vbus = 0; 1448 sc->sc_flags.status_bus_reset = 0; 1449 sc->sc_flags.status_suspend = 0; 1450 sc->sc_flags.change_suspend = 0; 1451 sc->sc_flags.change_connect = 1; 1452 1453 at91dci_pull_down(sc); 1454 at91dci_clocks_off(sc); 1455 USB_BUS_UNLOCK(&sc->sc_bus); 1456} 1457 1458void 1459at91dci_suspend(struct at91dci_softc *sc) 1460{ 1461 return; 1462} 1463 1464void 1465at91dci_resume(struct at91dci_softc *sc) 1466{ 1467 return; 1468} 1469 1470static void 1471at91dci_do_poll(struct usb2_bus *bus) 1472{ 1473 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(bus); 1474 1475 USB_BUS_LOCK(&sc->sc_bus); 1476 at91dci_interrupt_poll(sc); 1477 at91dci_root_ctrl_poll(sc); 1478 USB_BUS_UNLOCK(&sc->sc_bus); 1479} 1480 1481/*------------------------------------------------------------------------* 1482 * at91dci bulk support 1483 *------------------------------------------------------------------------*/ 1484static void 1485at91dci_device_bulk_open(struct usb2_xfer *xfer) 1486{ 1487 return; 1488} 1489 1490static void 1491at91dci_device_bulk_close(struct usb2_xfer *xfer) 1492{ 1493 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1494} 1495 1496static void 1497at91dci_device_bulk_enter(struct usb2_xfer *xfer) 1498{ 1499 return; 1500} 1501 1502static void 1503at91dci_device_bulk_start(struct usb2_xfer *xfer) 1504{ 1505 /* setup TDs */ 1506 at91dci_setup_standard_chain(xfer); 1507 at91dci_start_standard_chain(xfer); 1508} 1509 1510struct usb2_pipe_methods at91dci_device_bulk_methods = 1511{ 1512 .open = at91dci_device_bulk_open, 1513 .close = at91dci_device_bulk_close, 1514 .enter = at91dci_device_bulk_enter, 1515 .start = at91dci_device_bulk_start, 1516 .enter_is_cancelable = 1, 1517 .start_is_cancelable = 1, 1518}; 1519 1520/*------------------------------------------------------------------------* 1521 * at91dci control support 1522 *------------------------------------------------------------------------*/ 1523static void 1524at91dci_device_ctrl_open(struct usb2_xfer *xfer) 1525{ 1526 return; 1527} 1528 1529static void 1530at91dci_device_ctrl_close(struct usb2_xfer *xfer) 1531{ 1532 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1533} 1534 1535static void 1536at91dci_device_ctrl_enter(struct usb2_xfer *xfer) 1537{ 1538 return; 1539} 1540 1541static void 1542at91dci_device_ctrl_start(struct usb2_xfer *xfer) 1543{ 1544 /* setup TDs */ 1545 at91dci_setup_standard_chain(xfer); 1546 at91dci_start_standard_chain(xfer); 1547} 1548 1549struct usb2_pipe_methods at91dci_device_ctrl_methods = 1550{ 1551 .open = at91dci_device_ctrl_open, 1552 .close = at91dci_device_ctrl_close, 1553 .enter = at91dci_device_ctrl_enter, 1554 .start = at91dci_device_ctrl_start, 1555 .enter_is_cancelable = 1, 1556 .start_is_cancelable = 1, 1557}; 1558 1559/*------------------------------------------------------------------------* 1560 * at91dci interrupt support 1561 *------------------------------------------------------------------------*/ 1562static void 1563at91dci_device_intr_open(struct usb2_xfer *xfer) 1564{ 1565 return; 1566} 1567 1568static void 1569at91dci_device_intr_close(struct usb2_xfer *xfer) 1570{ 1571 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1572} 1573 1574static void 1575at91dci_device_intr_enter(struct usb2_xfer *xfer) 1576{ 1577 return; 1578} 1579 1580static void 1581at91dci_device_intr_start(struct usb2_xfer *xfer) 1582{ 1583 /* setup TDs */ 1584 at91dci_setup_standard_chain(xfer); 1585 at91dci_start_standard_chain(xfer); 1586} 1587 1588struct usb2_pipe_methods at91dci_device_intr_methods = 1589{ 1590 .open = at91dci_device_intr_open, 1591 .close = at91dci_device_intr_close, 1592 .enter = at91dci_device_intr_enter, 1593 .start = at91dci_device_intr_start, 1594 .enter_is_cancelable = 1, 1595 .start_is_cancelable = 1, 1596}; 1597 1598/*------------------------------------------------------------------------* 1599 * at91dci full speed isochronous support 1600 *------------------------------------------------------------------------*/ 1601static void 1602at91dci_device_isoc_fs_open(struct usb2_xfer *xfer) 1603{ 1604 return; 1605} 1606 1607static void 1608at91dci_device_isoc_fs_close(struct usb2_xfer *xfer) 1609{ 1610 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1611} 1612 1613static void 1614at91dci_device_isoc_fs_enter(struct usb2_xfer *xfer) 1615{ 1616 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 1617 uint32_t temp; 1618 uint32_t nframes; 1619 1620 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 1621 xfer, xfer->pipe->isoc_next, xfer->nframes); 1622 1623 /* get the current frame index */ 1624 1625 nframes = AT91_UDP_READ_4(sc, AT91_UDP_FRM); 1626 1627 /* 1628 * check if the frame index is within the window where the frames 1629 * will be inserted 1630 */ 1631 temp = (nframes - xfer->pipe->isoc_next) & AT91_UDP_FRM_MASK; 1632 1633 if ((xfer->pipe->is_synced == 0) || 1634 (temp < xfer->nframes)) { 1635 /* 1636 * If there is data underflow or the pipe queue is 1637 * empty we schedule the transfer a few frames ahead 1638 * of the current frame position. Else two isochronous 1639 * transfers might overlap. 1640 */ 1641 xfer->pipe->isoc_next = (nframes + 3) & AT91_UDP_FRM_MASK; 1642 xfer->pipe->is_synced = 1; 1643 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next); 1644 } 1645 /* 1646 * compute how many milliseconds the insertion is ahead of the 1647 * current frame position: 1648 */ 1649 temp = (xfer->pipe->isoc_next - nframes) & AT91_UDP_FRM_MASK; 1650 1651 /* 1652 * pre-compute when the isochronous transfer will be finished: 1653 */ 1654 xfer->isoc_time_complete = 1655 usb2_isoc_time_expand(&sc->sc_bus, nframes) + temp + 1656 xfer->nframes; 1657 1658 /* compute frame number for next insertion */ 1659 xfer->pipe->isoc_next += xfer->nframes; 1660 1661 /* setup TDs */ 1662 at91dci_setup_standard_chain(xfer); 1663} 1664 1665static void 1666at91dci_device_isoc_fs_start(struct usb2_xfer *xfer) 1667{ 1668 /* start TD chain */ 1669 at91dci_start_standard_chain(xfer); 1670} 1671 1672struct usb2_pipe_methods at91dci_device_isoc_fs_methods = 1673{ 1674 .open = at91dci_device_isoc_fs_open, 1675 .close = at91dci_device_isoc_fs_close, 1676 .enter = at91dci_device_isoc_fs_enter, 1677 .start = at91dci_device_isoc_fs_start, 1678 .enter_is_cancelable = 1, 1679 .start_is_cancelable = 1, 1680}; 1681 1682/*------------------------------------------------------------------------* 1683 * at91dci root control support 1684 *------------------------------------------------------------------------* 1685 * simulate a hardware HUB by handling 1686 * all the necessary requests 1687 *------------------------------------------------------------------------*/ 1688 1689static void 1690at91dci_root_ctrl_open(struct usb2_xfer *xfer) 1691{ 1692 return; 1693} 1694 1695static void 1696at91dci_root_ctrl_close(struct usb2_xfer *xfer) 1697{ 1698 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 1699 1700 if (sc->sc_root_ctrl.xfer == xfer) { 1701 sc->sc_root_ctrl.xfer = NULL; 1702 } 1703 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1704} 1705 1706/* 1707 * USB descriptors for the virtual Root HUB: 1708 */ 1709 1710static const struct usb2_device_descriptor at91dci_devd = { 1711 .bLength = sizeof(struct usb2_device_descriptor), 1712 .bDescriptorType = UDESC_DEVICE, 1713 .bcdUSB = {0x00, 0x02}, 1714 .bDeviceClass = UDCLASS_HUB, 1715 .bDeviceSubClass = UDSUBCLASS_HUB, 1716 .bDeviceProtocol = UDPROTO_HSHUBSTT, 1717 .bMaxPacketSize = 64, 1718 .bcdDevice = {0x00, 0x01}, 1719 .iManufacturer = 1, 1720 .iProduct = 2, 1721 .bNumConfigurations = 1, 1722}; 1723 1724static const struct usb2_device_qualifier at91dci_odevd = { 1725 .bLength = sizeof(struct usb2_device_qualifier), 1726 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 1727 .bcdUSB = {0x00, 0x02}, 1728 .bDeviceClass = UDCLASS_HUB, 1729 .bDeviceSubClass = UDSUBCLASS_HUB, 1730 .bDeviceProtocol = UDPROTO_FSHUB, 1731 .bMaxPacketSize0 = 0, 1732 .bNumConfigurations = 0, 1733}; 1734 1735static const struct at91dci_config_desc at91dci_confd = { 1736 .confd = { 1737 .bLength = sizeof(struct usb2_config_descriptor), 1738 .bDescriptorType = UDESC_CONFIG, 1739 .wTotalLength[0] = sizeof(at91dci_confd), 1740 .bNumInterface = 1, 1741 .bConfigurationValue = 1, 1742 .iConfiguration = 0, 1743 .bmAttributes = UC_SELF_POWERED, 1744 .bMaxPower = 0, 1745 }, 1746 .ifcd = { 1747 .bLength = sizeof(struct usb2_interface_descriptor), 1748 .bDescriptorType = UDESC_INTERFACE, 1749 .bNumEndpoints = 1, 1750 .bInterfaceClass = UICLASS_HUB, 1751 .bInterfaceSubClass = UISUBCLASS_HUB, 1752 .bInterfaceProtocol = UIPROTO_HSHUBSTT, 1753 }, 1754 1755 .endpd = { 1756 .bLength = sizeof(struct usb2_endpoint_descriptor), 1757 .bDescriptorType = UDESC_ENDPOINT, 1758 .bEndpointAddress = (UE_DIR_IN | AT9100_DCI_INTR_ENDPT), 1759 .bmAttributes = UE_INTERRUPT, 1760 .wMaxPacketSize[0] = 8, 1761 .bInterval = 255, 1762 }, 1763}; 1764 1765static const struct usb2_hub_descriptor_min at91dci_hubd = { 1766 .bDescLength = sizeof(at91dci_hubd), 1767 .bDescriptorType = UDESC_HUB, 1768 .bNbrPorts = 1, 1769 .wHubCharacteristics[0] = 1770 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) & 0xFF, 1771 .wHubCharacteristics[1] = 1772 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) >> 8, 1773 .bPwrOn2PwrGood = 50, 1774 .bHubContrCurrent = 0, 1775 .DeviceRemovable = {0}, /* port is removable */ 1776}; 1777 1778#define STRING_LANG \ 1779 0x09, 0x04, /* American English */ 1780 1781#define STRING_VENDOR \ 1782 'A', 0, 'T', 0, 'M', 0, 'E', 0, 'L', 0 1783 1784#define STRING_PRODUCT \ 1785 'D', 0, 'C', 0, 'I', 0, ' ', 0, 'R', 0, \ 1786 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \ 1787 'U', 0, 'B', 0, 1788 1789USB_MAKE_STRING_DESC(STRING_LANG, at91dci_langtab); 1790USB_MAKE_STRING_DESC(STRING_VENDOR, at91dci_vendor); 1791USB_MAKE_STRING_DESC(STRING_PRODUCT, at91dci_product); 1792 1793static void 1794at91dci_root_ctrl_enter(struct usb2_xfer *xfer) 1795{ 1796 return; 1797} 1798 1799static void 1800at91dci_root_ctrl_start(struct usb2_xfer *xfer) 1801{ 1802 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 1803 1804 sc->sc_root_ctrl.xfer = xfer; 1805 1806 usb2_bus_roothub_exec(xfer->xroot->bus); 1807} 1808 1809static void 1810at91dci_root_ctrl_task(struct usb2_bus *bus) 1811{ 1812 at91dci_root_ctrl_poll(AT9100_DCI_BUS2SC(bus)); 1813} 1814 1815static void 1816at91dci_root_ctrl_done(struct usb2_xfer *xfer, 1817 struct usb2_sw_transfer *std) 1818{ 1819 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 1820 uint16_t value; 1821 uint16_t index; 1822 1823 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1824 1825 if (std->state != USB_SW_TR_SETUP) { 1826 if (std->state == USB_SW_TR_PRE_CALLBACK) { 1827 /* transfer transferred */ 1828 at91dci_device_done(xfer, std->err); 1829 } 1830 goto done; 1831 } 1832 /* buffer reset */ 1833 std->ptr = USB_ADD_BYTES(&sc->sc_hub_temp, 0); 1834 std->len = 0; 1835 1836 value = UGETW(std->req.wValue); 1837 index = UGETW(std->req.wIndex); 1838 1839 /* demultiplex the control request */ 1840 1841 switch (std->req.bmRequestType) { 1842 case UT_READ_DEVICE: 1843 switch (std->req.bRequest) { 1844 case UR_GET_DESCRIPTOR: 1845 goto tr_handle_get_descriptor; 1846 case UR_GET_CONFIG: 1847 goto tr_handle_get_config; 1848 case UR_GET_STATUS: 1849 goto tr_handle_get_status; 1850 default: 1851 goto tr_stalled; 1852 } 1853 break; 1854 1855 case UT_WRITE_DEVICE: 1856 switch (std->req.bRequest) { 1857 case UR_SET_ADDRESS: 1858 goto tr_handle_set_address; 1859 case UR_SET_CONFIG: 1860 goto tr_handle_set_config; 1861 case UR_CLEAR_FEATURE: 1862 goto tr_valid; /* nop */ 1863 case UR_SET_DESCRIPTOR: 1864 goto tr_valid; /* nop */ 1865 case UR_SET_FEATURE: 1866 default: 1867 goto tr_stalled; 1868 } 1869 break; 1870 1871 case UT_WRITE_ENDPOINT: 1872 switch (std->req.bRequest) { 1873 case UR_CLEAR_FEATURE: 1874 switch (UGETW(std->req.wValue)) { 1875 case UF_ENDPOINT_HALT: 1876 goto tr_handle_clear_halt; 1877 case UF_DEVICE_REMOTE_WAKEUP: 1878 goto tr_handle_clear_wakeup; 1879 default: 1880 goto tr_stalled; 1881 } 1882 break; 1883 case UR_SET_FEATURE: 1884 switch (UGETW(std->req.wValue)) { 1885 case UF_ENDPOINT_HALT: 1886 goto tr_handle_set_halt; 1887 case UF_DEVICE_REMOTE_WAKEUP: 1888 goto tr_handle_set_wakeup; 1889 default: 1890 goto tr_stalled; 1891 } 1892 break; 1893 case UR_SYNCH_FRAME: 1894 goto tr_valid; /* nop */ 1895 default: 1896 goto tr_stalled; 1897 } 1898 break; 1899 1900 case UT_READ_ENDPOINT: 1901 switch (std->req.bRequest) { 1902 case UR_GET_STATUS: 1903 goto tr_handle_get_ep_status; 1904 default: 1905 goto tr_stalled; 1906 } 1907 break; 1908 1909 case UT_WRITE_INTERFACE: 1910 switch (std->req.bRequest) { 1911 case UR_SET_INTERFACE: 1912 goto tr_handle_set_interface; 1913 case UR_CLEAR_FEATURE: 1914 goto tr_valid; /* nop */ 1915 case UR_SET_FEATURE: 1916 default: 1917 goto tr_stalled; 1918 } 1919 break; 1920 1921 case UT_READ_INTERFACE: 1922 switch (std->req.bRequest) { 1923 case UR_GET_INTERFACE: 1924 goto tr_handle_get_interface; 1925 case UR_GET_STATUS: 1926 goto tr_handle_get_iface_status; 1927 default: 1928 goto tr_stalled; 1929 } 1930 break; 1931 1932 case UT_WRITE_CLASS_INTERFACE: 1933 case UT_WRITE_VENDOR_INTERFACE: 1934 /* XXX forward */ 1935 break; 1936 1937 case UT_READ_CLASS_INTERFACE: 1938 case UT_READ_VENDOR_INTERFACE: 1939 /* XXX forward */ 1940 break; 1941 1942 case UT_WRITE_CLASS_DEVICE: 1943 switch (std->req.bRequest) { 1944 case UR_CLEAR_FEATURE: 1945 goto tr_valid; 1946 case UR_SET_DESCRIPTOR: 1947 case UR_SET_FEATURE: 1948 break; 1949 default: 1950 goto tr_stalled; 1951 } 1952 break; 1953 1954 case UT_WRITE_CLASS_OTHER: 1955 switch (std->req.bRequest) { 1956 case UR_CLEAR_FEATURE: 1957 goto tr_handle_clear_port_feature; 1958 case UR_SET_FEATURE: 1959 goto tr_handle_set_port_feature; 1960 case UR_CLEAR_TT_BUFFER: 1961 case UR_RESET_TT: 1962 case UR_STOP_TT: 1963 goto tr_valid; 1964 1965 default: 1966 goto tr_stalled; 1967 } 1968 break; 1969 1970 case UT_READ_CLASS_OTHER: 1971 switch (std->req.bRequest) { 1972 case UR_GET_TT_STATE: 1973 goto tr_handle_get_tt_state; 1974 case UR_GET_STATUS: 1975 goto tr_handle_get_port_status; 1976 default: 1977 goto tr_stalled; 1978 } 1979 break; 1980 1981 case UT_READ_CLASS_DEVICE: 1982 switch (std->req.bRequest) { 1983 case UR_GET_DESCRIPTOR: 1984 goto tr_handle_get_class_descriptor; 1985 case UR_GET_STATUS: 1986 goto tr_handle_get_class_status; 1987 1988 default: 1989 goto tr_stalled; 1990 } 1991 break; 1992 default: 1993 goto tr_stalled; 1994 } 1995 goto tr_valid; 1996 1997tr_handle_get_descriptor: 1998 switch (value >> 8) { 1999 case UDESC_DEVICE: 2000 if (value & 0xff) { 2001 goto tr_stalled; 2002 } 2003 std->len = sizeof(at91dci_devd); 2004 std->ptr = USB_ADD_BYTES(&at91dci_devd, 0); 2005 goto tr_valid; 2006 case UDESC_CONFIG: 2007 if (value & 0xff) { 2008 goto tr_stalled; 2009 } 2010 std->len = sizeof(at91dci_confd); 2011 std->ptr = USB_ADD_BYTES(&at91dci_confd, 0); 2012 goto tr_valid; 2013 case UDESC_STRING: 2014 switch (value & 0xff) { 2015 case 0: /* Language table */ 2016 std->len = sizeof(at91dci_langtab); 2017 std->ptr = USB_ADD_BYTES(&at91dci_langtab, 0); 2018 goto tr_valid; 2019 2020 case 1: /* Vendor */ 2021 std->len = sizeof(at91dci_vendor); 2022 std->ptr = USB_ADD_BYTES(&at91dci_vendor, 0); 2023 goto tr_valid; 2024 2025 case 2: /* Product */ 2026 std->len = sizeof(at91dci_product); 2027 std->ptr = USB_ADD_BYTES(&at91dci_product, 0); 2028 goto tr_valid; 2029 default: 2030 break; 2031 } 2032 break; 2033 default: 2034 goto tr_stalled; 2035 } 2036 goto tr_stalled; 2037 2038tr_handle_get_config: 2039 std->len = 1; 2040 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 2041 goto tr_valid; 2042 2043tr_handle_get_status: 2044 std->len = 2; 2045 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 2046 goto tr_valid; 2047 2048tr_handle_set_address: 2049 if (value & 0xFF00) { 2050 goto tr_stalled; 2051 } 2052 sc->sc_rt_addr = value; 2053 goto tr_valid; 2054 2055tr_handle_set_config: 2056 if (value >= 2) { 2057 goto tr_stalled; 2058 } 2059 sc->sc_conf = value; 2060 goto tr_valid; 2061 2062tr_handle_get_interface: 2063 std->len = 1; 2064 sc->sc_hub_temp.wValue[0] = 0; 2065 goto tr_valid; 2066 2067tr_handle_get_tt_state: 2068tr_handle_get_class_status: 2069tr_handle_get_iface_status: 2070tr_handle_get_ep_status: 2071 std->len = 2; 2072 USETW(sc->sc_hub_temp.wValue, 0); 2073 goto tr_valid; 2074 2075tr_handle_set_halt: 2076tr_handle_set_interface: 2077tr_handle_set_wakeup: 2078tr_handle_clear_wakeup: 2079tr_handle_clear_halt: 2080 goto tr_valid; 2081 2082tr_handle_clear_port_feature: 2083 if (index != 1) { 2084 goto tr_stalled; 2085 } 2086 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 2087 2088 switch (value) { 2089 case UHF_PORT_SUSPEND: 2090 at91dci_wakeup_peer(xfer); 2091 break; 2092 2093 case UHF_PORT_ENABLE: 2094 sc->sc_flags.port_enabled = 0; 2095 break; 2096 2097 case UHF_PORT_TEST: 2098 case UHF_PORT_INDICATOR: 2099 case UHF_C_PORT_ENABLE: 2100 case UHF_C_PORT_OVER_CURRENT: 2101 case UHF_C_PORT_RESET: 2102 /* nops */ 2103 break; 2104 case UHF_PORT_POWER: 2105 sc->sc_flags.port_powered = 0; 2106 at91dci_pull_down(sc); 2107 at91dci_clocks_off(sc); 2108 break; 2109 case UHF_C_PORT_CONNECTION: 2110 sc->sc_flags.change_connect = 0; 2111 break; 2112 case UHF_C_PORT_SUSPEND: 2113 sc->sc_flags.change_suspend = 0; 2114 break; 2115 default: 2116 std->err = USB_ERR_IOERROR; 2117 goto done; 2118 } 2119 goto tr_valid; 2120 2121tr_handle_set_port_feature: 2122 if (index != 1) { 2123 goto tr_stalled; 2124 } 2125 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 2126 2127 switch (value) { 2128 case UHF_PORT_ENABLE: 2129 sc->sc_flags.port_enabled = 1; 2130 break; 2131 case UHF_PORT_SUSPEND: 2132 case UHF_PORT_RESET: 2133 case UHF_PORT_TEST: 2134 case UHF_PORT_INDICATOR: 2135 /* nops */ 2136 break; 2137 case UHF_PORT_POWER: 2138 sc->sc_flags.port_powered = 1; 2139 break; 2140 default: 2141 std->err = USB_ERR_IOERROR; 2142 goto done; 2143 } 2144 goto tr_valid; 2145 2146tr_handle_get_port_status: 2147 2148 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 2149 2150 if (index != 1) { 2151 goto tr_stalled; 2152 } 2153 if (sc->sc_flags.status_vbus) { 2154 at91dci_clocks_on(sc); 2155 at91dci_pull_up(sc); 2156 } else { 2157 at91dci_pull_down(sc); 2158 at91dci_clocks_off(sc); 2159 } 2160 2161 /* Select FULL-speed and Device Side Mode */ 2162 2163 value = UPS_PORT_MODE_DEVICE; 2164 2165 if (sc->sc_flags.port_powered) { 2166 value |= UPS_PORT_POWER; 2167 } 2168 if (sc->sc_flags.port_enabled) { 2169 value |= UPS_PORT_ENABLED; 2170 } 2171 if (sc->sc_flags.status_vbus && 2172 sc->sc_flags.status_bus_reset) { 2173 value |= UPS_CURRENT_CONNECT_STATUS; 2174 } 2175 if (sc->sc_flags.status_suspend) { 2176 value |= UPS_SUSPEND; 2177 } 2178 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 2179 2180 value = 0; 2181 2182 if (sc->sc_flags.change_connect) { 2183 value |= UPS_C_CONNECT_STATUS; 2184 2185 if (sc->sc_flags.status_vbus && 2186 sc->sc_flags.status_bus_reset) { 2187 /* reset endpoint flags */ 2188 bzero(sc->sc_ep_flags, sizeof(sc->sc_ep_flags)); 2189 } 2190 } 2191 if (sc->sc_flags.change_suspend) { 2192 value |= UPS_C_SUSPEND; 2193 } 2194 USETW(sc->sc_hub_temp.ps.wPortChange, value); 2195 std->len = sizeof(sc->sc_hub_temp.ps); 2196 goto tr_valid; 2197 2198tr_handle_get_class_descriptor: 2199 if (value & 0xFF) { 2200 goto tr_stalled; 2201 } 2202 std->ptr = USB_ADD_BYTES(&at91dci_hubd, 0); 2203 std->len = sizeof(at91dci_hubd); 2204 goto tr_valid; 2205 2206tr_stalled: 2207 std->err = USB_ERR_STALLED; 2208tr_valid: 2209done: 2210 return; 2211} 2212 2213static void 2214at91dci_root_ctrl_poll(struct at91dci_softc *sc) 2215{ 2216 usb2_sw_transfer(&sc->sc_root_ctrl, 2217 &at91dci_root_ctrl_done); 2218} 2219 2220struct usb2_pipe_methods at91dci_root_ctrl_methods = 2221{ 2222 .open = at91dci_root_ctrl_open, 2223 .close = at91dci_root_ctrl_close, 2224 .enter = at91dci_root_ctrl_enter, 2225 .start = at91dci_root_ctrl_start, 2226 .enter_is_cancelable = 1, 2227 .start_is_cancelable = 0, 2228}; 2229 2230/*------------------------------------------------------------------------* 2231 * at91dci root interrupt support 2232 *------------------------------------------------------------------------*/ 2233static void 2234at91dci_root_intr_open(struct usb2_xfer *xfer) 2235{ 2236 return; 2237} 2238 2239static void 2240at91dci_root_intr_close(struct usb2_xfer *xfer) 2241{ 2242 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 2243 2244 if (sc->sc_root_intr.xfer == xfer) { 2245 sc->sc_root_intr.xfer = NULL; 2246 } 2247 at91dci_device_done(xfer, USB_ERR_CANCELLED); 2248} 2249 2250static void 2251at91dci_root_intr_enter(struct usb2_xfer *xfer) 2252{ 2253 return; 2254} 2255 2256static void 2257at91dci_root_intr_start(struct usb2_xfer *xfer) 2258{ 2259 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 2260 2261 sc->sc_root_intr.xfer = xfer; 2262} 2263 2264struct usb2_pipe_methods at91dci_root_intr_methods = 2265{ 2266 .open = at91dci_root_intr_open, 2267 .close = at91dci_root_intr_close, 2268 .enter = at91dci_root_intr_enter, 2269 .start = at91dci_root_intr_start, 2270 .enter_is_cancelable = 1, 2271 .start_is_cancelable = 1, 2272}; 2273 2274static void 2275at91dci_xfer_setup(struct usb2_setup_params *parm) 2276{ 2277 const struct usb2_hw_ep_profile *pf; 2278 struct at91dci_softc *sc; 2279 struct usb2_xfer *xfer; 2280 void *last_obj; 2281 uint32_t ntd; 2282 uint32_t n; 2283 uint8_t ep_no; 2284 2285 sc = AT9100_DCI_BUS2SC(parm->udev->bus); 2286 xfer = parm->curr_xfer; 2287 2288 /* 2289 * NOTE: This driver does not use any of the parameters that 2290 * are computed from the following values. Just set some 2291 * reasonable dummies: 2292 */ 2293 parm->hc_max_packet_size = 0x500; 2294 parm->hc_max_packet_count = 1; 2295 parm->hc_max_frame_size = 0x500; 2296 2297 usb2_transfer_setup_sub(parm); 2298 2299 /* 2300 * compute maximum number of TDs 2301 */ 2302 if (parm->methods == &at91dci_device_ctrl_methods) { 2303 2304 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 2305 + 1 /* SYNC 2 */ ; 2306 2307 } else if (parm->methods == &at91dci_device_bulk_methods) { 2308 2309 ntd = xfer->nframes + 1 /* SYNC */ ; 2310 2311 } else if (parm->methods == &at91dci_device_intr_methods) { 2312 2313 ntd = xfer->nframes + 1 /* SYNC */ ; 2314 2315 } else if (parm->methods == &at91dci_device_isoc_fs_methods) { 2316 2317 ntd = xfer->nframes + 1 /* SYNC */ ; 2318 2319 } else { 2320 2321 ntd = 0; 2322 } 2323 2324 /* 2325 * check if "usb2_transfer_setup_sub" set an error 2326 */ 2327 if (parm->err) { 2328 return; 2329 } 2330 /* 2331 * allocate transfer descriptors 2332 */ 2333 last_obj = NULL; 2334 2335 /* 2336 * get profile stuff 2337 */ 2338 if (ntd) { 2339 2340 ep_no = xfer->endpoint & UE_ADDR; 2341 at91dci_get_hw_ep_profile(parm->udev, &pf, ep_no); 2342 2343 if (pf == NULL) { 2344 /* should not happen */ 2345 parm->err = USB_ERR_INVAL; 2346 return; 2347 } 2348 } else { 2349 ep_no = 0; 2350 pf = NULL; 2351 } 2352 2353 /* align data */ 2354 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2355 2356 for (n = 0; n != ntd; n++) { 2357 2358 struct at91dci_td *td; 2359 2360 if (parm->buf) { 2361 2362 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2363 2364 /* init TD */ 2365 td->io_tag = sc->sc_io_tag; 2366 td->io_hdl = sc->sc_io_hdl; 2367 td->max_packet_size = xfer->max_packet_size; 2368 td->status_reg = AT91_UDP_CSR(ep_no); 2369 td->fifo_reg = AT91_UDP_FDR(ep_no); 2370 if (pf->support_multi_buffer) { 2371 td->support_multi_buffer = 1; 2372 } 2373 td->obj_next = last_obj; 2374 2375 last_obj = td; 2376 } 2377 parm->size[0] += sizeof(*td); 2378 } 2379 2380 xfer->td_start[0] = last_obj; 2381} 2382 2383static void 2384at91dci_xfer_unsetup(struct usb2_xfer *xfer) 2385{ 2386 return; 2387} 2388 2389static void 2390at91dci_pipe_init(struct usb2_device *udev, struct usb2_endpoint_descriptor *edesc, 2391 struct usb2_pipe *pipe) 2392{ 2393 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(udev->bus); 2394 2395 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 2396 pipe, udev->address, 2397 edesc->bEndpointAddress, udev->flags.usb2_mode, 2398 sc->sc_rt_addr); 2399 2400 if (udev->device_index == sc->sc_rt_addr) { 2401 2402 if (udev->flags.usb2_mode != USB_MODE_HOST) { 2403 /* not supported */ 2404 return; 2405 } 2406 switch (edesc->bEndpointAddress) { 2407 case USB_CONTROL_ENDPOINT: 2408 pipe->methods = &at91dci_root_ctrl_methods; 2409 break; 2410 case UE_DIR_IN | AT9100_DCI_INTR_ENDPT: 2411 pipe->methods = &at91dci_root_intr_methods; 2412 break; 2413 default: 2414 /* do nothing */ 2415 break; 2416 } 2417 } else { 2418 2419 if (udev->flags.usb2_mode != USB_MODE_DEVICE) { 2420 /* not supported */ 2421 return; 2422 } 2423 if (udev->speed != USB_SPEED_FULL) { 2424 /* not supported */ 2425 return; 2426 } 2427 switch (edesc->bmAttributes & UE_XFERTYPE) { 2428 case UE_CONTROL: 2429 pipe->methods = &at91dci_device_ctrl_methods; 2430 break; 2431 case UE_INTERRUPT: 2432 pipe->methods = &at91dci_device_intr_methods; 2433 break; 2434 case UE_ISOCHRONOUS: 2435 pipe->methods = &at91dci_device_isoc_fs_methods; 2436 break; 2437 case UE_BULK: 2438 pipe->methods = &at91dci_device_bulk_methods; 2439 break; 2440 default: 2441 /* do nothing */ 2442 break; 2443 } 2444 } 2445} 2446 2447struct usb2_bus_methods at91dci_bus_methods = 2448{ 2449 .pipe_init = &at91dci_pipe_init, 2450 .xfer_setup = &at91dci_xfer_setup, 2451 .xfer_unsetup = &at91dci_xfer_unsetup, 2452 .get_hw_ep_profile = &at91dci_get_hw_ep_profile, 2453 .set_stall = &at91dci_set_stall, 2454 .clear_stall = &at91dci_clear_stall, 2455 .roothub_exec = &at91dci_root_ctrl_task, 2456}; 2457