ubsec.c revision 159225
1/* $OpenBSD: ubsec.c,v 1.115 2002/09/24 18:33:26 jason Exp $ */ 2 3/*- 4 * Copyright (c) 2000 Jason L. Wright (jason@thought.net) 5 * Copyright (c) 2000 Theo de Raadt (deraadt@openbsd.org) 6 * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com) 7 * 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Jason L. Wright 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 32 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 33 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Effort sponsored in part by the Defense Advanced Research Projects 37 * Agency (DARPA) and Air Force Research Laboratory, Air Force 38 * Materiel Command, USAF, under agreement number F30602-01-2-0537. 39 */ 40 41#include <sys/cdefs.h> 42__FBSDID("$FreeBSD: head/sys/dev/ubsec/ubsec.c 159225 2006-06-04 14:13:17Z pjd $"); 43 44/* 45 * uBsec 5[56]01, 58xx hardware crypto accelerator 46 */ 47 48#include "opt_ubsec.h" 49 50#include <sys/param.h> 51#include <sys/systm.h> 52#include <sys/proc.h> 53#include <sys/errno.h> 54#include <sys/malloc.h> 55#include <sys/kernel.h> 56#include <sys/module.h> 57#include <sys/mbuf.h> 58#include <sys/lock.h> 59#include <sys/mutex.h> 60#include <sys/sysctl.h> 61#include <sys/endian.h> 62 63#include <vm/vm.h> 64#include <vm/pmap.h> 65 66#include <machine/bus.h> 67#include <machine/resource.h> 68#include <sys/bus.h> 69#include <sys/rman.h> 70 71#include <crypto/sha1.h> 72#include <opencrypto/cryptodev.h> 73#include <opencrypto/cryptosoft.h> 74#include <sys/md5.h> 75#include <sys/random.h> 76 77#include <dev/pci/pcivar.h> 78#include <dev/pci/pcireg.h> 79 80/* grr, #defines for gratuitous incompatibility in queue.h */ 81#define SIMPLEQ_HEAD STAILQ_HEAD 82#define SIMPLEQ_ENTRY STAILQ_ENTRY 83#define SIMPLEQ_INIT STAILQ_INIT 84#define SIMPLEQ_INSERT_TAIL STAILQ_INSERT_TAIL 85#define SIMPLEQ_EMPTY STAILQ_EMPTY 86#define SIMPLEQ_FIRST STAILQ_FIRST 87#define SIMPLEQ_REMOVE_HEAD STAILQ_REMOVE_HEAD_UNTIL 88#define SIMPLEQ_FOREACH STAILQ_FOREACH 89/* ditto for endian.h */ 90#define letoh16(x) le16toh(x) 91#define letoh32(x) le32toh(x) 92 93#ifdef UBSEC_RNDTEST 94#include <dev/rndtest/rndtest.h> 95#endif 96#include <dev/ubsec/ubsecreg.h> 97#include <dev/ubsec/ubsecvar.h> 98 99/* 100 * Prototypes and count for the pci_device structure 101 */ 102static int ubsec_probe(device_t); 103static int ubsec_attach(device_t); 104static int ubsec_detach(device_t); 105static int ubsec_suspend(device_t); 106static int ubsec_resume(device_t); 107static void ubsec_shutdown(device_t); 108 109static device_method_t ubsec_methods[] = { 110 /* Device interface */ 111 DEVMETHOD(device_probe, ubsec_probe), 112 DEVMETHOD(device_attach, ubsec_attach), 113 DEVMETHOD(device_detach, ubsec_detach), 114 DEVMETHOD(device_suspend, ubsec_suspend), 115 DEVMETHOD(device_resume, ubsec_resume), 116 DEVMETHOD(device_shutdown, ubsec_shutdown), 117 118 /* bus interface */ 119 DEVMETHOD(bus_print_child, bus_generic_print_child), 120 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 121 122 { 0, 0 } 123}; 124static driver_t ubsec_driver = { 125 "ubsec", 126 ubsec_methods, 127 sizeof (struct ubsec_softc) 128}; 129static devclass_t ubsec_devclass; 130 131DRIVER_MODULE(ubsec, pci, ubsec_driver, ubsec_devclass, 0, 0); 132MODULE_DEPEND(ubsec, crypto, 1, 1, 1); 133#ifdef UBSEC_RNDTEST 134MODULE_DEPEND(ubsec, rndtest, 1, 1, 1); 135#endif 136 137static void ubsec_intr(void *); 138static int ubsec_newsession(void *, u_int32_t *, struct cryptoini *); 139static int ubsec_freesession(void *, u_int64_t); 140static int ubsec_process(void *, struct cryptop *, int); 141static void ubsec_callback(struct ubsec_softc *, struct ubsec_q *); 142static void ubsec_feed(struct ubsec_softc *); 143static void ubsec_mcopy(struct mbuf *, struct mbuf *, int, int); 144static void ubsec_callback2(struct ubsec_softc *, struct ubsec_q2 *); 145static int ubsec_feed2(struct ubsec_softc *); 146static void ubsec_rng(void *); 147static int ubsec_dma_malloc(struct ubsec_softc *, bus_size_t, 148 struct ubsec_dma_alloc *, int); 149#define ubsec_dma_sync(_dma, _flags) \ 150 bus_dmamap_sync((_dma)->dma_tag, (_dma)->dma_map, (_flags)) 151static void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *); 152static int ubsec_dmamap_aligned(struct ubsec_operand *op); 153 154static void ubsec_reset_board(struct ubsec_softc *sc); 155static void ubsec_init_board(struct ubsec_softc *sc); 156static void ubsec_init_pciregs(device_t dev); 157static void ubsec_totalreset(struct ubsec_softc *sc); 158 159static int ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q); 160 161static int ubsec_kprocess(void*, struct cryptkop *, int); 162static int ubsec_kprocess_modexp_hw(struct ubsec_softc *, struct cryptkop *, int); 163static int ubsec_kprocess_modexp_sw(struct ubsec_softc *, struct cryptkop *, int); 164static int ubsec_kprocess_rsapriv(struct ubsec_softc *, struct cryptkop *, int); 165static void ubsec_kfree(struct ubsec_softc *, struct ubsec_q2 *); 166static int ubsec_ksigbits(struct crparam *); 167static void ubsec_kshift_r(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 168static void ubsec_kshift_l(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 169 170SYSCTL_NODE(_hw, OID_AUTO, ubsec, CTLFLAG_RD, 0, "Broadcom driver parameters"); 171 172#ifdef UBSEC_DEBUG 173static void ubsec_dump_pb(volatile struct ubsec_pktbuf *); 174static void ubsec_dump_mcr(struct ubsec_mcr *); 175static void ubsec_dump_ctx2(struct ubsec_ctx_keyop *); 176 177static int ubsec_debug = 0; 178SYSCTL_INT(_hw_ubsec, OID_AUTO, debug, CTLFLAG_RW, &ubsec_debug, 179 0, "control debugging msgs"); 180#endif 181 182#define READ_REG(sc,r) \ 183 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r)) 184 185#define WRITE_REG(sc,reg,val) \ 186 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val) 187 188#define SWAP32(x) (x) = htole32(ntohl((x))) 189#define HTOLE32(x) (x) = htole32(x) 190 191struct ubsec_stats ubsecstats; 192SYSCTL_STRUCT(_hw_ubsec, OID_AUTO, stats, CTLFLAG_RD, &ubsecstats, 193 ubsec_stats, "driver statistics"); 194 195static int 196ubsec_probe(device_t dev) 197{ 198 if (pci_get_vendor(dev) == PCI_VENDOR_SUN && 199 (pci_get_device(dev) == PCI_PRODUCT_SUN_5821 || 200 pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K)) 201 return (BUS_PROBE_DEFAULT); 202 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL && 203 (pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5501 || 204 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601)) 205 return (BUS_PROBE_DEFAULT); 206 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 207 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5801 || 208 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 || 209 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805 || 210 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820 || 211 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 || 212 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 || 213 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823 214 )) 215 return (BUS_PROBE_DEFAULT); 216 return (ENXIO); 217} 218 219static const char* 220ubsec_partname(struct ubsec_softc *sc) 221{ 222 /* XXX sprintf numbers when not decoded */ 223 switch (pci_get_vendor(sc->sc_dev)) { 224 case PCI_VENDOR_BROADCOM: 225 switch (pci_get_device(sc->sc_dev)) { 226 case PCI_PRODUCT_BROADCOM_5801: return "Broadcom 5801"; 227 case PCI_PRODUCT_BROADCOM_5802: return "Broadcom 5802"; 228 case PCI_PRODUCT_BROADCOM_5805: return "Broadcom 5805"; 229 case PCI_PRODUCT_BROADCOM_5820: return "Broadcom 5820"; 230 case PCI_PRODUCT_BROADCOM_5821: return "Broadcom 5821"; 231 case PCI_PRODUCT_BROADCOM_5822: return "Broadcom 5822"; 232 case PCI_PRODUCT_BROADCOM_5823: return "Broadcom 5823"; 233 } 234 return "Broadcom unknown-part"; 235 case PCI_VENDOR_BLUESTEEL: 236 switch (pci_get_device(sc->sc_dev)) { 237 case PCI_PRODUCT_BLUESTEEL_5601: return "Bluesteel 5601"; 238 } 239 return "Bluesteel unknown-part"; 240 case PCI_VENDOR_SUN: 241 switch (pci_get_device(sc->sc_dev)) { 242 case PCI_PRODUCT_SUN_5821: return "Sun Crypto 5821"; 243 case PCI_PRODUCT_SUN_SCA1K: return "Sun Crypto 1K"; 244 } 245 return "Sun unknown-part"; 246 } 247 return "Unknown-vendor unknown-part"; 248} 249 250static void 251default_harvest(struct rndtest_state *rsp, void *buf, u_int count) 252{ 253 random_harvest(buf, count, count*NBBY, 0, RANDOM_PURE); 254} 255 256static int 257ubsec_attach(device_t dev) 258{ 259 struct ubsec_softc *sc = device_get_softc(dev); 260 struct ubsec_dma *dmap; 261 u_int32_t cmd, i; 262 int rid; 263 264 bzero(sc, sizeof (*sc)); 265 sc->sc_dev = dev; 266 267 SIMPLEQ_INIT(&sc->sc_queue); 268 SIMPLEQ_INIT(&sc->sc_qchip); 269 SIMPLEQ_INIT(&sc->sc_queue2); 270 SIMPLEQ_INIT(&sc->sc_qchip2); 271 SIMPLEQ_INIT(&sc->sc_q2free); 272 273 /* XXX handle power management */ 274 275 sc->sc_statmask = BS_STAT_MCR1_DONE | BS_STAT_DMAERR; 276 277 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL && 278 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601) 279 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG; 280 281 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 282 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 || 283 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805)) 284 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG; 285 286 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 287 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820) 288 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG | 289 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY; 290 291 if ((pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 292 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 || 293 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 || 294 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823)) || 295 (pci_get_vendor(dev) == PCI_VENDOR_SUN && 296 (pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K || 297 pci_get_device(dev) == PCI_PRODUCT_SUN_5821))) { 298 /* NB: the 5821/5822 defines some additional status bits */ 299 sc->sc_statmask |= BS_STAT_MCR1_ALLEMPTY | 300 BS_STAT_MCR2_ALLEMPTY; 301 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG | 302 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY; 303 } 304 305 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 306 cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN; 307 pci_write_config(dev, PCIR_COMMAND, cmd, 4); 308 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 309 310 if (!(cmd & PCIM_CMD_MEMEN)) { 311 device_printf(dev, "failed to enable memory mapping\n"); 312 goto bad; 313 } 314 315 if (!(cmd & PCIM_CMD_BUSMASTEREN)) { 316 device_printf(dev, "failed to enable bus mastering\n"); 317 goto bad; 318 } 319 320 /* 321 * Setup memory-mapping of PCI registers. 322 */ 323 rid = BS_BAR; 324 sc->sc_sr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 325 RF_ACTIVE); 326 if (sc->sc_sr == NULL) { 327 device_printf(dev, "cannot map register space\n"); 328 goto bad; 329 } 330 sc->sc_st = rman_get_bustag(sc->sc_sr); 331 sc->sc_sh = rman_get_bushandle(sc->sc_sr); 332 333 /* 334 * Arrange interrupt line. 335 */ 336 rid = 0; 337 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 338 RF_SHAREABLE|RF_ACTIVE); 339 if (sc->sc_irq == NULL) { 340 device_printf(dev, "could not map interrupt\n"); 341 goto bad1; 342 } 343 /* 344 * NB: Network code assumes we are blocked with splimp() 345 * so make sure the IRQ is mapped appropriately. 346 */ 347 if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE, 348 ubsec_intr, sc, &sc->sc_ih)) { 349 device_printf(dev, "could not establish interrupt\n"); 350 goto bad2; 351 } 352 353 sc->sc_cid = crypto_get_driverid(0); 354 if (sc->sc_cid < 0) { 355 device_printf(dev, "could not get crypto driver id\n"); 356 goto bad3; 357 } 358 359 /* 360 * Setup DMA descriptor area. 361 */ 362 if (bus_dma_tag_create(NULL, /* parent */ 363 1, 0, /* alignment, bounds */ 364 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 365 BUS_SPACE_MAXADDR, /* highaddr */ 366 NULL, NULL, /* filter, filterarg */ 367 0x3ffff, /* maxsize */ 368 UBS_MAX_SCATTER, /* nsegments */ 369 0xffff, /* maxsegsize */ 370 BUS_DMA_ALLOCNOW, /* flags */ 371 NULL, NULL, /* lockfunc, lockarg */ 372 &sc->sc_dmat)) { 373 device_printf(dev, "cannot allocate DMA tag\n"); 374 goto bad4; 375 } 376 SIMPLEQ_INIT(&sc->sc_freequeue); 377 dmap = sc->sc_dmaa; 378 for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) { 379 struct ubsec_q *q; 380 381 q = (struct ubsec_q *)malloc(sizeof(struct ubsec_q), 382 M_DEVBUF, M_NOWAIT); 383 if (q == NULL) { 384 device_printf(dev, "cannot allocate queue buffers\n"); 385 break; 386 } 387 388 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_dmachunk), 389 &dmap->d_alloc, 0)) { 390 device_printf(dev, "cannot allocate dma buffers\n"); 391 free(q, M_DEVBUF); 392 break; 393 } 394 dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr; 395 396 q->q_dma = dmap; 397 sc->sc_queuea[i] = q; 398 399 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 400 } 401 mtx_init(&sc->sc_mcr1lock, device_get_nameunit(dev), 402 "mcr1 operations", MTX_DEF); 403 mtx_init(&sc->sc_freeqlock, device_get_nameunit(dev), 404 "mcr1 free q", MTX_DEF); 405 406 device_printf(sc->sc_dev, "%s\n", ubsec_partname(sc)); 407 408 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0, 409 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 410 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0, 411 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 412 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0, 413 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 414 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0, 415 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 416 417 /* 418 * Reset Broadcom chip 419 */ 420 ubsec_reset_board(sc); 421 422 /* 423 * Init Broadcom specific PCI settings 424 */ 425 ubsec_init_pciregs(dev); 426 427 /* 428 * Init Broadcom chip 429 */ 430 ubsec_init_board(sc); 431 432#ifndef UBSEC_NO_RNG 433 if (sc->sc_flags & UBS_FLAGS_RNG) { 434 sc->sc_statmask |= BS_STAT_MCR2_DONE; 435#ifdef UBSEC_RNDTEST 436 sc->sc_rndtest = rndtest_attach(dev); 437 if (sc->sc_rndtest) 438 sc->sc_harvest = rndtest_harvest; 439 else 440 sc->sc_harvest = default_harvest; 441#else 442 sc->sc_harvest = default_harvest; 443#endif 444 445 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 446 &sc->sc_rng.rng_q.q_mcr, 0)) 447 goto skip_rng; 448 449 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rngbypass), 450 &sc->sc_rng.rng_q.q_ctx, 0)) { 451 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 452 goto skip_rng; 453 } 454 455 if (ubsec_dma_malloc(sc, sizeof(u_int32_t) * 456 UBSEC_RNG_BUFSIZ, &sc->sc_rng.rng_buf, 0)) { 457 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx); 458 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 459 goto skip_rng; 460 } 461 462 if (hz >= 100) 463 sc->sc_rnghz = hz / 100; 464 else 465 sc->sc_rnghz = 1; 466 callout_init(&sc->sc_rngto, CALLOUT_MPSAFE); 467 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 468skip_rng: 469 ; 470 } 471#endif /* UBSEC_NO_RNG */ 472 mtx_init(&sc->sc_mcr2lock, device_get_nameunit(dev), 473 "mcr2 operations", MTX_DEF); 474 475 if (sc->sc_flags & UBS_FLAGS_KEY) { 476 sc->sc_statmask |= BS_STAT_MCR2_DONE; 477 478 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0, 479 ubsec_kprocess, sc); 480#if 0 481 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0, 482 ubsec_kprocess, sc); 483#endif 484 } 485 return (0); 486bad4: 487 crypto_unregister_all(sc->sc_cid); 488bad3: 489 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 490bad2: 491 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 492bad1: 493 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 494bad: 495 return (ENXIO); 496} 497 498/* 499 * Detach a device that successfully probed. 500 */ 501static int 502ubsec_detach(device_t dev) 503{ 504 struct ubsec_softc *sc = device_get_softc(dev); 505 506 /* XXX wait/abort active ops */ 507 508 /* disable interrupts */ 509 WRITE_REG(sc, BS_CTRL, READ_REG(sc, BS_CTRL) &~ 510 (BS_CTRL_MCR2INT | BS_CTRL_MCR1INT | BS_CTRL_DMAERR)); 511 512 callout_stop(&sc->sc_rngto); 513 514 crypto_unregister_all(sc->sc_cid); 515 516#ifdef UBSEC_RNDTEST 517 if (sc->sc_rndtest) 518 rndtest_detach(sc->sc_rndtest); 519#endif 520 521 while (!SIMPLEQ_EMPTY(&sc->sc_freequeue)) { 522 struct ubsec_q *q; 523 524 q = SIMPLEQ_FIRST(&sc->sc_freequeue); 525 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q, q_next); 526 ubsec_dma_free(sc, &q->q_dma->d_alloc); 527 free(q, M_DEVBUF); 528 } 529 mtx_destroy(&sc->sc_mcr1lock); 530 mtx_destroy(&sc->sc_freeqlock); 531#ifndef UBSEC_NO_RNG 532 if (sc->sc_flags & UBS_FLAGS_RNG) { 533 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 534 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx); 535 ubsec_dma_free(sc, &sc->sc_rng.rng_buf); 536 } 537#endif /* UBSEC_NO_RNG */ 538 mtx_destroy(&sc->sc_mcr2lock); 539 540 bus_generic_detach(dev); 541 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 542 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 543 544 bus_dma_tag_destroy(sc->sc_dmat); 545 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 546 547 return (0); 548} 549 550/* 551 * Stop all chip i/o so that the kernel's probe routines don't 552 * get confused by errant DMAs when rebooting. 553 */ 554static void 555ubsec_shutdown(device_t dev) 556{ 557#ifdef notyet 558 ubsec_stop(device_get_softc(dev)); 559#endif 560} 561 562/* 563 * Device suspend routine. 564 */ 565static int 566ubsec_suspend(device_t dev) 567{ 568 struct ubsec_softc *sc = device_get_softc(dev); 569 570#ifdef notyet 571 /* XXX stop the device and save PCI settings */ 572#endif 573 sc->sc_suspended = 1; 574 575 return (0); 576} 577 578static int 579ubsec_resume(device_t dev) 580{ 581 struct ubsec_softc *sc = device_get_softc(dev); 582 583#ifdef notyet 584 /* XXX retore PCI settings and start the device */ 585#endif 586 sc->sc_suspended = 0; 587 return (0); 588} 589 590/* 591 * UBSEC Interrupt routine 592 */ 593static void 594ubsec_intr(void *arg) 595{ 596 struct ubsec_softc *sc = arg; 597 volatile u_int32_t stat; 598 struct ubsec_q *q; 599 struct ubsec_dma *dmap; 600 int npkts = 0, i; 601 602 stat = READ_REG(sc, BS_STAT); 603 stat &= sc->sc_statmask; 604 if (stat == 0) 605 return; 606 607 WRITE_REG(sc, BS_STAT, stat); /* IACK */ 608 609 /* 610 * Check to see if we have any packets waiting for us 611 */ 612 if ((stat & BS_STAT_MCR1_DONE)) { 613 mtx_lock(&sc->sc_mcr1lock); 614 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 615 q = SIMPLEQ_FIRST(&sc->sc_qchip); 616 dmap = q->q_dma; 617 618 if ((dmap->d_dma->d_mcr.mcr_flags & htole16(UBS_MCR_DONE)) == 0) 619 break; 620 621 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q, q_next); 622 623 npkts = q->q_nstacked_mcrs; 624 sc->sc_nqchip -= 1+npkts; 625 /* 626 * search for further sc_qchip ubsec_q's that share 627 * the same MCR, and complete them too, they must be 628 * at the top. 629 */ 630 for (i = 0; i < npkts; i++) { 631 if(q->q_stacked_mcr[i]) { 632 ubsec_callback(sc, q->q_stacked_mcr[i]); 633 } else { 634 break; 635 } 636 } 637 ubsec_callback(sc, q); 638 } 639 /* 640 * Don't send any more packet to chip if there has been 641 * a DMAERR. 642 */ 643 if (!(stat & BS_STAT_DMAERR)) 644 ubsec_feed(sc); 645 mtx_unlock(&sc->sc_mcr1lock); 646 } 647 648 /* 649 * Check to see if we have any key setups/rng's waiting for us 650 */ 651 if ((sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) && 652 (stat & BS_STAT_MCR2_DONE)) { 653 struct ubsec_q2 *q2; 654 struct ubsec_mcr *mcr; 655 656 mtx_lock(&sc->sc_mcr2lock); 657 while (!SIMPLEQ_EMPTY(&sc->sc_qchip2)) { 658 q2 = SIMPLEQ_FIRST(&sc->sc_qchip2); 659 660 ubsec_dma_sync(&q2->q_mcr, 661 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 662 663 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr; 664 if ((mcr->mcr_flags & htole16(UBS_MCR_DONE)) == 0) { 665 ubsec_dma_sync(&q2->q_mcr, 666 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 667 break; 668 } 669 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip2, q2, q_next); 670 ubsec_callback2(sc, q2); 671 /* 672 * Don't send any more packet to chip if there has been 673 * a DMAERR. 674 */ 675 if (!(stat & BS_STAT_DMAERR)) 676 ubsec_feed2(sc); 677 } 678 mtx_unlock(&sc->sc_mcr2lock); 679 } 680 681 /* 682 * Check to see if we got any DMA Error 683 */ 684 if (stat & BS_STAT_DMAERR) { 685#ifdef UBSEC_DEBUG 686 if (ubsec_debug) { 687 volatile u_int32_t a = READ_REG(sc, BS_ERR); 688 689 printf("dmaerr %s@%08x\n", 690 (a & BS_ERR_READ) ? "read" : "write", 691 a & BS_ERR_ADDR); 692 } 693#endif /* UBSEC_DEBUG */ 694 ubsecstats.hst_dmaerr++; 695 mtx_lock(&sc->sc_mcr1lock); 696 ubsec_totalreset(sc); 697 ubsec_feed(sc); 698 mtx_unlock(&sc->sc_mcr1lock); 699 } 700 701 if (sc->sc_needwakeup) { /* XXX check high watermark */ 702 int wakeup; 703 704 mtx_lock(&sc->sc_freeqlock); 705 wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 706#ifdef UBSEC_DEBUG 707 if (ubsec_debug) 708 device_printf(sc->sc_dev, "wakeup crypto (%x)\n", 709 sc->sc_needwakeup); 710#endif /* UBSEC_DEBUG */ 711 sc->sc_needwakeup &= ~wakeup; 712 mtx_unlock(&sc->sc_freeqlock); 713 crypto_unblock(sc->sc_cid, wakeup); 714 } 715} 716 717/* 718 * ubsec_feed() - aggregate and post requests to chip 719 */ 720static void 721ubsec_feed(struct ubsec_softc *sc) 722{ 723 struct ubsec_q *q, *q2; 724 int npkts, i; 725 void *v; 726 u_int32_t stat; 727 728 /* 729 * Decide how many ops to combine in a single MCR. We cannot 730 * aggregate more than UBS_MAX_AGGR because this is the number 731 * of slots defined in the data structure. Note that 732 * aggregation only happens if ops are marked batch'able. 733 * Aggregating ops reduces the number of interrupts to the host 734 * but also (potentially) increases the latency for processing 735 * completed ops as we only get an interrupt when all aggregated 736 * ops have completed. 737 */ 738 if (sc->sc_nqueue == 0) 739 return; 740 if (sc->sc_nqueue > 1) { 741 npkts = 0; 742 SIMPLEQ_FOREACH(q, &sc->sc_queue, q_next) { 743 npkts++; 744 if ((q->q_crp->crp_flags & CRYPTO_F_BATCH) == 0) 745 break; 746 } 747 } else 748 npkts = 1; 749 /* 750 * Check device status before going any further. 751 */ 752 if ((stat = READ_REG(sc, BS_STAT)) & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { 753 if (stat & BS_STAT_DMAERR) { 754 ubsec_totalreset(sc); 755 ubsecstats.hst_dmaerr++; 756 } else 757 ubsecstats.hst_mcr1full++; 758 return; 759 } 760 if (sc->sc_nqueue > ubsecstats.hst_maxqueue) 761 ubsecstats.hst_maxqueue = sc->sc_nqueue; 762 if (npkts > UBS_MAX_AGGR) 763 npkts = UBS_MAX_AGGR; 764 if (npkts < 2) /* special case 1 op */ 765 goto feed1; 766 767 ubsecstats.hst_totbatch += npkts-1; 768#ifdef UBSEC_DEBUG 769 if (ubsec_debug) 770 printf("merging %d records\n", npkts); 771#endif /* UBSEC_DEBUG */ 772 773 q = SIMPLEQ_FIRST(&sc->sc_queue); 774 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q, q_next); 775 --sc->sc_nqueue; 776 777 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE); 778 if (q->q_dst_map != NULL) 779 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD); 780 781 q->q_nstacked_mcrs = npkts - 1; /* Number of packets stacked */ 782 783 for (i = 0; i < q->q_nstacked_mcrs; i++) { 784 q2 = SIMPLEQ_FIRST(&sc->sc_queue); 785 bus_dmamap_sync(sc->sc_dmat, q2->q_src_map, 786 BUS_DMASYNC_PREWRITE); 787 if (q2->q_dst_map != NULL) 788 bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map, 789 BUS_DMASYNC_PREREAD); 790 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q2, q_next); 791 --sc->sc_nqueue; 792 793 v = (void*)(((char *)&q2->q_dma->d_dma->d_mcr) + sizeof(struct ubsec_mcr) - 794 sizeof(struct ubsec_mcr_add)); 795 bcopy(v, &q->q_dma->d_dma->d_mcradd[i], sizeof(struct ubsec_mcr_add)); 796 q->q_stacked_mcr[i] = q2; 797 } 798 q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts); 799 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 800 sc->sc_nqchip += npkts; 801 if (sc->sc_nqchip > ubsecstats.hst_maxqchip) 802 ubsecstats.hst_maxqchip = sc->sc_nqchip; 803 ubsec_dma_sync(&q->q_dma->d_alloc, 804 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 805 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 806 offsetof(struct ubsec_dmachunk, d_mcr)); 807 return; 808feed1: 809 q = SIMPLEQ_FIRST(&sc->sc_queue); 810 811 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE); 812 if (q->q_dst_map != NULL) 813 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD); 814 ubsec_dma_sync(&q->q_dma->d_alloc, 815 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 816 817 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 818 offsetof(struct ubsec_dmachunk, d_mcr)); 819#ifdef UBSEC_DEBUG 820 if (ubsec_debug) 821 printf("feed1: q->chip %p %08x stat %08x\n", 822 q, (u_int32_t)vtophys(&q->q_dma->d_dma->d_mcr), 823 stat); 824#endif /* UBSEC_DEBUG */ 825 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q, q_next); 826 --sc->sc_nqueue; 827 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 828 sc->sc_nqchip++; 829 if (sc->sc_nqchip > ubsecstats.hst_maxqchip) 830 ubsecstats.hst_maxqchip = sc->sc_nqchip; 831 return; 832} 833 834static void 835ubsec_setup_enckey(struct ubsec_session *ses, int algo, caddr_t key) 836{ 837 838 /* Go ahead and compute key in ubsec's byte order */ 839 if (algo == CRYPTO_DES_CBC) { 840 bcopy(key, &ses->ses_deskey[0], 8); 841 bcopy(key, &ses->ses_deskey[2], 8); 842 bcopy(key, &ses->ses_deskey[4], 8); 843 } else 844 bcopy(key, ses->ses_deskey, 24); 845 846 SWAP32(ses->ses_deskey[0]); 847 SWAP32(ses->ses_deskey[1]); 848 SWAP32(ses->ses_deskey[2]); 849 SWAP32(ses->ses_deskey[3]); 850 SWAP32(ses->ses_deskey[4]); 851 SWAP32(ses->ses_deskey[5]); 852} 853 854static void 855ubsec_setup_mackey(struct ubsec_session *ses, int algo, caddr_t key, int klen) 856{ 857 MD5_CTX md5ctx; 858 SHA1_CTX sha1ctx; 859 int i; 860 861 for (i = 0; i < klen; i++) 862 key[i] ^= HMAC_IPAD_VAL; 863 864 if (algo == CRYPTO_MD5_HMAC) { 865 MD5Init(&md5ctx); 866 MD5Update(&md5ctx, key, klen); 867 MD5Update(&md5ctx, hmac_ipad_buffer, HMAC_BLOCK_LEN - klen); 868 bcopy(md5ctx.state, ses->ses_hminner, sizeof(md5ctx.state)); 869 } else { 870 SHA1Init(&sha1ctx); 871 SHA1Update(&sha1ctx, key, klen); 872 SHA1Update(&sha1ctx, hmac_ipad_buffer, HMAC_BLOCK_LEN - klen); 873 bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32)); 874 } 875 876 for (i = 0; i < klen; i++) 877 key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); 878 879 if (algo == CRYPTO_MD5_HMAC) { 880 MD5Init(&md5ctx); 881 MD5Update(&md5ctx, key, klen); 882 MD5Update(&md5ctx, hmac_opad_buffer, HMAC_BLOCK_LEN - klen); 883 bcopy(md5ctx.state, ses->ses_hmouter, sizeof(md5ctx.state)); 884 } else { 885 SHA1Init(&sha1ctx); 886 SHA1Update(&sha1ctx, key, klen); 887 SHA1Update(&sha1ctx, hmac_opad_buffer, HMAC_BLOCK_LEN - klen); 888 bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32)); 889 } 890 891 for (i = 0; i < klen; i++) 892 key[i] ^= HMAC_OPAD_VAL; 893} 894 895/* 896 * Allocate a new 'session' and return an encoded session id. 'sidp' 897 * contains our registration id, and should contain an encoded session 898 * id on successful allocation. 899 */ 900static int 901ubsec_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri) 902{ 903 struct cryptoini *c, *encini = NULL, *macini = NULL; 904 struct ubsec_softc *sc = arg; 905 struct ubsec_session *ses = NULL; 906 int sesn; 907 908 if (sidp == NULL || cri == NULL || sc == NULL) 909 return (EINVAL); 910 911 for (c = cri; c != NULL; c = c->cri_next) { 912 if (c->cri_alg == CRYPTO_MD5_HMAC || 913 c->cri_alg == CRYPTO_SHA1_HMAC) { 914 if (macini) 915 return (EINVAL); 916 macini = c; 917 } else if (c->cri_alg == CRYPTO_DES_CBC || 918 c->cri_alg == CRYPTO_3DES_CBC) { 919 if (encini) 920 return (EINVAL); 921 encini = c; 922 } else 923 return (EINVAL); 924 } 925 if (encini == NULL && macini == NULL) 926 return (EINVAL); 927 928 if (sc->sc_sessions == NULL) { 929 ses = sc->sc_sessions = (struct ubsec_session *)malloc( 930 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT); 931 if (ses == NULL) 932 return (ENOMEM); 933 sesn = 0; 934 sc->sc_nsessions = 1; 935 } else { 936 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { 937 if (sc->sc_sessions[sesn].ses_used == 0) { 938 ses = &sc->sc_sessions[sesn]; 939 break; 940 } 941 } 942 943 if (ses == NULL) { 944 sesn = sc->sc_nsessions; 945 ses = (struct ubsec_session *)malloc((sesn + 1) * 946 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT); 947 if (ses == NULL) 948 return (ENOMEM); 949 bcopy(sc->sc_sessions, ses, sesn * 950 sizeof(struct ubsec_session)); 951 bzero(sc->sc_sessions, sesn * 952 sizeof(struct ubsec_session)); 953 free(sc->sc_sessions, M_DEVBUF); 954 sc->sc_sessions = ses; 955 ses = &sc->sc_sessions[sesn]; 956 sc->sc_nsessions++; 957 } 958 } 959 bzero(ses, sizeof(struct ubsec_session)); 960 ses->ses_used = 1; 961 962 if (encini) { 963 /* get an IV, network byte order */ 964 /* XXX may read fewer than requested */ 965 read_random(ses->ses_iv, sizeof(ses->ses_iv)); 966 967 if (encini->cri_key != NULL) { 968 ubsec_setup_enckey(ses, encini->cri_alg, 969 encini->cri_key); 970 } 971 } 972 973 if (macini) { 974 ses->ses_mlen = macini->cri_mlen; 975 if (ses->ses_mlen == 0) { 976 if (macini->cri_alg == CRYPTO_MD5_HMAC) 977 ses->ses_mlen = MD5_DIGEST_LENGTH; 978 else 979 ses->ses_mlen = SHA1_RESULTLEN; 980 } 981 982 if (macini->cri_key != NULL) { 983 ubsec_setup_mackey(ses, macini->cri_alg, 984 macini->cri_key, macini->cri_klen / 8); 985 } 986 } 987 988 *sidp = UBSEC_SID(device_get_unit(sc->sc_dev), sesn); 989 return (0); 990} 991 992/* 993 * Deallocate a session. 994 */ 995static int 996ubsec_freesession(void *arg, u_int64_t tid) 997{ 998 struct ubsec_softc *sc = arg; 999 int session, ret; 1000 u_int32_t sid = CRYPTO_SESID2LID(tid); 1001 1002 if (sc == NULL) 1003 return (EINVAL); 1004 1005 session = UBSEC_SESSION(sid); 1006 if (session < sc->sc_nsessions) { 1007 bzero(&sc->sc_sessions[session], 1008 sizeof(sc->sc_sessions[session])); 1009 ret = 0; 1010 } else 1011 ret = EINVAL; 1012 1013 return (ret); 1014} 1015 1016static void 1017ubsec_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error) 1018{ 1019 struct ubsec_operand *op = arg; 1020 1021 KASSERT(nsegs <= UBS_MAX_SCATTER, 1022 ("Too many DMA segments returned when mapping operand")); 1023#ifdef UBSEC_DEBUG 1024 if (ubsec_debug) 1025 printf("ubsec_op_cb: mapsize %u nsegs %d\n", 1026 (u_int) mapsize, nsegs); 1027#endif 1028 op->mapsize = mapsize; 1029 op->nsegs = nsegs; 1030 bcopy(seg, op->segs, nsegs * sizeof (seg[0])); 1031} 1032 1033static int 1034ubsec_process(void *arg, struct cryptop *crp, int hint) 1035{ 1036 struct ubsec_q *q = NULL; 1037 int err = 0, i, j, nicealign; 1038 struct ubsec_softc *sc = arg; 1039 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 1040 int encoffset = 0, macoffset = 0, cpskip, cpoffset; 1041 int sskip, dskip, stheend, dtheend; 1042 int16_t coffset; 1043 struct ubsec_session *ses; 1044 struct ubsec_pktctx ctx; 1045 struct ubsec_dma *dmap = NULL; 1046 1047 if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { 1048 ubsecstats.hst_invalid++; 1049 return (EINVAL); 1050 } 1051 if (UBSEC_SESSION(crp->crp_sid) >= sc->sc_nsessions) { 1052 ubsecstats.hst_badsession++; 1053 return (EINVAL); 1054 } 1055 1056 mtx_lock(&sc->sc_freeqlock); 1057 if (SIMPLEQ_EMPTY(&sc->sc_freequeue)) { 1058 ubsecstats.hst_queuefull++; 1059 sc->sc_needwakeup |= CRYPTO_SYMQ; 1060 mtx_unlock(&sc->sc_freeqlock); 1061 return (ERESTART); 1062 } 1063 q = SIMPLEQ_FIRST(&sc->sc_freequeue); 1064 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q, q_next); 1065 mtx_unlock(&sc->sc_freeqlock); 1066 1067 dmap = q->q_dma; /* Save dma pointer */ 1068 bzero(q, sizeof(struct ubsec_q)); 1069 bzero(&ctx, sizeof(ctx)); 1070 1071 q->q_sesn = UBSEC_SESSION(crp->crp_sid); 1072 q->q_dma = dmap; 1073 ses = &sc->sc_sessions[q->q_sesn]; 1074 1075 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1076 q->q_src_m = (struct mbuf *)crp->crp_buf; 1077 q->q_dst_m = (struct mbuf *)crp->crp_buf; 1078 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1079 q->q_src_io = (struct uio *)crp->crp_buf; 1080 q->q_dst_io = (struct uio *)crp->crp_buf; 1081 } else { 1082 ubsecstats.hst_badflags++; 1083 err = EINVAL; 1084 goto errout; /* XXX we don't handle contiguous blocks! */ 1085 } 1086 1087 bzero(&dmap->d_dma->d_mcr, sizeof(struct ubsec_mcr)); 1088 1089 dmap->d_dma->d_mcr.mcr_pkts = htole16(1); 1090 dmap->d_dma->d_mcr.mcr_flags = 0; 1091 q->q_crp = crp; 1092 1093 crd1 = crp->crp_desc; 1094 if (crd1 == NULL) { 1095 ubsecstats.hst_nodesc++; 1096 err = EINVAL; 1097 goto errout; 1098 } 1099 crd2 = crd1->crd_next; 1100 1101 if (crd2 == NULL) { 1102 if (crd1->crd_alg == CRYPTO_MD5_HMAC || 1103 crd1->crd_alg == CRYPTO_SHA1_HMAC) { 1104 maccrd = crd1; 1105 enccrd = NULL; 1106 } else if (crd1->crd_alg == CRYPTO_DES_CBC || 1107 crd1->crd_alg == CRYPTO_3DES_CBC) { 1108 maccrd = NULL; 1109 enccrd = crd1; 1110 } else { 1111 ubsecstats.hst_badalg++; 1112 err = EINVAL; 1113 goto errout; 1114 } 1115 } else { 1116 if ((crd1->crd_alg == CRYPTO_MD5_HMAC || 1117 crd1->crd_alg == CRYPTO_SHA1_HMAC) && 1118 (crd2->crd_alg == CRYPTO_DES_CBC || 1119 crd2->crd_alg == CRYPTO_3DES_CBC) && 1120 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 1121 maccrd = crd1; 1122 enccrd = crd2; 1123 } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 1124 crd1->crd_alg == CRYPTO_3DES_CBC) && 1125 (crd2->crd_alg == CRYPTO_MD5_HMAC || 1126 crd2->crd_alg == CRYPTO_SHA1_HMAC) && 1127 (crd1->crd_flags & CRD_F_ENCRYPT)) { 1128 enccrd = crd1; 1129 maccrd = crd2; 1130 } else { 1131 /* 1132 * We cannot order the ubsec as requested 1133 */ 1134 ubsecstats.hst_badalg++; 1135 err = EINVAL; 1136 goto errout; 1137 } 1138 } 1139 1140 if (enccrd) { 1141 if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) { 1142 ubsec_setup_enckey(ses, enccrd->crd_alg, 1143 enccrd->crd_key); 1144 } 1145 1146 encoffset = enccrd->crd_skip; 1147 ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_3DES); 1148 1149 if (enccrd->crd_flags & CRD_F_ENCRYPT) { 1150 q->q_flags |= UBSEC_QFLAGS_COPYOUTIV; 1151 1152 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1153 bcopy(enccrd->crd_iv, ctx.pc_iv, 8); 1154 else { 1155 ctx.pc_iv[0] = ses->ses_iv[0]; 1156 ctx.pc_iv[1] = ses->ses_iv[1]; 1157 } 1158 1159 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { 1160 if (crp->crp_flags & CRYPTO_F_IMBUF) 1161 m_copyback(q->q_src_m, 1162 enccrd->crd_inject, 1163 8, (caddr_t)ctx.pc_iv); 1164 else if (crp->crp_flags & CRYPTO_F_IOV) 1165 cuio_copyback(q->q_src_io, 1166 enccrd->crd_inject, 1167 8, (caddr_t)ctx.pc_iv); 1168 } 1169 } else { 1170 ctx.pc_flags |= htole16(UBS_PKTCTX_INBOUND); 1171 1172 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1173 bcopy(enccrd->crd_iv, ctx.pc_iv, 8); 1174 else if (crp->crp_flags & CRYPTO_F_IMBUF) 1175 m_copydata(q->q_src_m, enccrd->crd_inject, 1176 8, (caddr_t)ctx.pc_iv); 1177 else if (crp->crp_flags & CRYPTO_F_IOV) 1178 cuio_copydata(q->q_src_io, 1179 enccrd->crd_inject, 8, 1180 (caddr_t)ctx.pc_iv); 1181 } 1182 1183 ctx.pc_deskey[0] = ses->ses_deskey[0]; 1184 ctx.pc_deskey[1] = ses->ses_deskey[1]; 1185 ctx.pc_deskey[2] = ses->ses_deskey[2]; 1186 ctx.pc_deskey[3] = ses->ses_deskey[3]; 1187 ctx.pc_deskey[4] = ses->ses_deskey[4]; 1188 ctx.pc_deskey[5] = ses->ses_deskey[5]; 1189 SWAP32(ctx.pc_iv[0]); 1190 SWAP32(ctx.pc_iv[1]); 1191 } 1192 1193 if (maccrd) { 1194 if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) { 1195 ubsec_setup_mackey(ses, maccrd->crd_alg, 1196 maccrd->crd_key, maccrd->crd_klen / 8); 1197 } 1198 1199 macoffset = maccrd->crd_skip; 1200 1201 if (maccrd->crd_alg == CRYPTO_MD5_HMAC) 1202 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_MD5); 1203 else 1204 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_SHA1); 1205 1206 for (i = 0; i < 5; i++) { 1207 ctx.pc_hminner[i] = ses->ses_hminner[i]; 1208 ctx.pc_hmouter[i] = ses->ses_hmouter[i]; 1209 1210 HTOLE32(ctx.pc_hminner[i]); 1211 HTOLE32(ctx.pc_hmouter[i]); 1212 } 1213 } 1214 1215 if (enccrd && maccrd) { 1216 /* 1217 * ubsec cannot handle packets where the end of encryption 1218 * and authentication are not the same, or where the 1219 * encrypted part begins before the authenticated part. 1220 */ 1221 if ((encoffset + enccrd->crd_len) != 1222 (macoffset + maccrd->crd_len)) { 1223 ubsecstats.hst_lenmismatch++; 1224 err = EINVAL; 1225 goto errout; 1226 } 1227 if (enccrd->crd_skip < maccrd->crd_skip) { 1228 ubsecstats.hst_skipmismatch++; 1229 err = EINVAL; 1230 goto errout; 1231 } 1232 sskip = maccrd->crd_skip; 1233 cpskip = dskip = enccrd->crd_skip; 1234 stheend = maccrd->crd_len; 1235 dtheend = enccrd->crd_len; 1236 coffset = enccrd->crd_skip - maccrd->crd_skip; 1237 cpoffset = cpskip + dtheend; 1238#ifdef UBSEC_DEBUG 1239 if (ubsec_debug) { 1240 printf("mac: skip %d, len %d, inject %d\n", 1241 maccrd->crd_skip, maccrd->crd_len, maccrd->crd_inject); 1242 printf("enc: skip %d, len %d, inject %d\n", 1243 enccrd->crd_skip, enccrd->crd_len, enccrd->crd_inject); 1244 printf("src: skip %d, len %d\n", sskip, stheend); 1245 printf("dst: skip %d, len %d\n", dskip, dtheend); 1246 printf("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n", 1247 coffset, stheend, cpskip, cpoffset); 1248 } 1249#endif 1250 } else { 1251 cpskip = dskip = sskip = macoffset + encoffset; 1252 dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len; 1253 cpoffset = cpskip + dtheend; 1254 coffset = 0; 1255 } 1256 ctx.pc_offset = htole16(coffset >> 2); 1257 1258 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &q->q_src_map)) { 1259 ubsecstats.hst_nomap++; 1260 err = ENOMEM; 1261 goto errout; 1262 } 1263 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1264 if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map, 1265 q->q_src_m, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) { 1266 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1267 q->q_src_map = NULL; 1268 ubsecstats.hst_noload++; 1269 err = ENOMEM; 1270 goto errout; 1271 } 1272 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1273 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map, 1274 q->q_src_io, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) { 1275 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1276 q->q_src_map = NULL; 1277 ubsecstats.hst_noload++; 1278 err = ENOMEM; 1279 goto errout; 1280 } 1281 } 1282 nicealign = ubsec_dmamap_aligned(&q->q_src); 1283 1284 dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend); 1285 1286#ifdef UBSEC_DEBUG 1287 if (ubsec_debug) 1288 printf("src skip: %d nicealign: %u\n", sskip, nicealign); 1289#endif 1290 for (i = j = 0; i < q->q_src_nsegs; i++) { 1291 struct ubsec_pktbuf *pb; 1292 bus_size_t packl = q->q_src_segs[i].ds_len; 1293 bus_addr_t packp = q->q_src_segs[i].ds_addr; 1294 1295 if (sskip >= packl) { 1296 sskip -= packl; 1297 continue; 1298 } 1299 1300 packl -= sskip; 1301 packp += sskip; 1302 sskip = 0; 1303 1304 if (packl > 0xfffc) { 1305 err = EIO; 1306 goto errout; 1307 } 1308 1309 if (j == 0) 1310 pb = &dmap->d_dma->d_mcr.mcr_ipktbuf; 1311 else 1312 pb = &dmap->d_dma->d_sbuf[j - 1]; 1313 1314 pb->pb_addr = htole32(packp); 1315 1316 if (stheend) { 1317 if (packl > stheend) { 1318 pb->pb_len = htole32(stheend); 1319 stheend = 0; 1320 } else { 1321 pb->pb_len = htole32(packl); 1322 stheend -= packl; 1323 } 1324 } else 1325 pb->pb_len = htole32(packl); 1326 1327 if ((i + 1) == q->q_src_nsegs) 1328 pb->pb_next = 0; 1329 else 1330 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1331 offsetof(struct ubsec_dmachunk, d_sbuf[j])); 1332 j++; 1333 } 1334 1335 if (enccrd == NULL && maccrd != NULL) { 1336 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0; 1337 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0; 1338 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next = htole32(dmap->d_alloc.dma_paddr + 1339 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1340#ifdef UBSEC_DEBUG 1341 if (ubsec_debug) 1342 printf("opkt: %x %x %x\n", 1343 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr, 1344 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len, 1345 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next); 1346#endif 1347 } else { 1348 if (crp->crp_flags & CRYPTO_F_IOV) { 1349 if (!nicealign) { 1350 ubsecstats.hst_iovmisaligned++; 1351 err = EINVAL; 1352 goto errout; 1353 } 1354 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 1355 &q->q_dst_map)) { 1356 ubsecstats.hst_nomap++; 1357 err = ENOMEM; 1358 goto errout; 1359 } 1360 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map, 1361 q->q_dst_io, ubsec_op_cb, &q->q_dst, BUS_DMA_NOWAIT) != 0) { 1362 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1363 q->q_dst_map = NULL; 1364 ubsecstats.hst_noload++; 1365 err = ENOMEM; 1366 goto errout; 1367 } 1368 } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1369 if (nicealign) { 1370 q->q_dst = q->q_src; 1371 } else { 1372 int totlen, len; 1373 struct mbuf *m, *top, **mp; 1374 1375 ubsecstats.hst_unaligned++; 1376 totlen = q->q_src_mapsize; 1377 if (q->q_src_m->m_flags & M_PKTHDR) { 1378 len = MHLEN; 1379 MGETHDR(m, M_DONTWAIT, MT_DATA); 1380 if (m && !m_dup_pkthdr(m, q->q_src_m, M_DONTWAIT)) { 1381 m_free(m); 1382 m = NULL; 1383 } 1384 } else { 1385 len = MLEN; 1386 MGET(m, M_DONTWAIT, MT_DATA); 1387 } 1388 if (m == NULL) { 1389 ubsecstats.hst_nombuf++; 1390 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1391 goto errout; 1392 } 1393 if (totlen >= MINCLSIZE) { 1394 MCLGET(m, M_DONTWAIT); 1395 if ((m->m_flags & M_EXT) == 0) { 1396 m_free(m); 1397 ubsecstats.hst_nomcl++; 1398 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1399 goto errout; 1400 } 1401 len = MCLBYTES; 1402 } 1403 m->m_len = len; 1404 top = NULL; 1405 mp = ⊤ 1406 1407 while (totlen > 0) { 1408 if (top) { 1409 MGET(m, M_DONTWAIT, MT_DATA); 1410 if (m == NULL) { 1411 m_freem(top); 1412 ubsecstats.hst_nombuf++; 1413 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1414 goto errout; 1415 } 1416 len = MLEN; 1417 } 1418 if (top && totlen >= MINCLSIZE) { 1419 MCLGET(m, M_DONTWAIT); 1420 if ((m->m_flags & M_EXT) == 0) { 1421 *mp = m; 1422 m_freem(top); 1423 ubsecstats.hst_nomcl++; 1424 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1425 goto errout; 1426 } 1427 len = MCLBYTES; 1428 } 1429 m->m_len = len = min(totlen, len); 1430 totlen -= len; 1431 *mp = m; 1432 mp = &m->m_next; 1433 } 1434 q->q_dst_m = top; 1435 ubsec_mcopy(q->q_src_m, q->q_dst_m, 1436 cpskip, cpoffset); 1437 if (bus_dmamap_create(sc->sc_dmat, 1438 BUS_DMA_NOWAIT, &q->q_dst_map) != 0) { 1439 ubsecstats.hst_nomap++; 1440 err = ENOMEM; 1441 goto errout; 1442 } 1443 if (bus_dmamap_load_mbuf(sc->sc_dmat, 1444 q->q_dst_map, q->q_dst_m, 1445 ubsec_op_cb, &q->q_dst, 1446 BUS_DMA_NOWAIT) != 0) { 1447 bus_dmamap_destroy(sc->sc_dmat, 1448 q->q_dst_map); 1449 q->q_dst_map = NULL; 1450 ubsecstats.hst_noload++; 1451 err = ENOMEM; 1452 goto errout; 1453 } 1454 } 1455 } else { 1456 ubsecstats.hst_badflags++; 1457 err = EINVAL; 1458 goto errout; 1459 } 1460 1461#ifdef UBSEC_DEBUG 1462 if (ubsec_debug) 1463 printf("dst skip: %d\n", dskip); 1464#endif 1465 for (i = j = 0; i < q->q_dst_nsegs; i++) { 1466 struct ubsec_pktbuf *pb; 1467 bus_size_t packl = q->q_dst_segs[i].ds_len; 1468 bus_addr_t packp = q->q_dst_segs[i].ds_addr; 1469 1470 if (dskip >= packl) { 1471 dskip -= packl; 1472 continue; 1473 } 1474 1475 packl -= dskip; 1476 packp += dskip; 1477 dskip = 0; 1478 1479 if (packl > 0xfffc) { 1480 err = EIO; 1481 goto errout; 1482 } 1483 1484 if (j == 0) 1485 pb = &dmap->d_dma->d_mcr.mcr_opktbuf; 1486 else 1487 pb = &dmap->d_dma->d_dbuf[j - 1]; 1488 1489 pb->pb_addr = htole32(packp); 1490 1491 if (dtheend) { 1492 if (packl > dtheend) { 1493 pb->pb_len = htole32(dtheend); 1494 dtheend = 0; 1495 } else { 1496 pb->pb_len = htole32(packl); 1497 dtheend -= packl; 1498 } 1499 } else 1500 pb->pb_len = htole32(packl); 1501 1502 if ((i + 1) == q->q_dst_nsegs) { 1503 if (maccrd) 1504 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1505 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1506 else 1507 pb->pb_next = 0; 1508 } else 1509 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1510 offsetof(struct ubsec_dmachunk, d_dbuf[j])); 1511 j++; 1512 } 1513 } 1514 1515 dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr + 1516 offsetof(struct ubsec_dmachunk, d_ctx)); 1517 1518 if (sc->sc_flags & UBS_FLAGS_LONGCTX) { 1519 struct ubsec_pktctx_long *ctxl; 1520 1521 ctxl = (struct ubsec_pktctx_long *)(dmap->d_alloc.dma_vaddr + 1522 offsetof(struct ubsec_dmachunk, d_ctx)); 1523 1524 /* transform small context into long context */ 1525 ctxl->pc_len = htole16(sizeof(struct ubsec_pktctx_long)); 1526 ctxl->pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC); 1527 ctxl->pc_flags = ctx.pc_flags; 1528 ctxl->pc_offset = ctx.pc_offset; 1529 for (i = 0; i < 6; i++) 1530 ctxl->pc_deskey[i] = ctx.pc_deskey[i]; 1531 for (i = 0; i < 5; i++) 1532 ctxl->pc_hminner[i] = ctx.pc_hminner[i]; 1533 for (i = 0; i < 5; i++) 1534 ctxl->pc_hmouter[i] = ctx.pc_hmouter[i]; 1535 ctxl->pc_iv[0] = ctx.pc_iv[0]; 1536 ctxl->pc_iv[1] = ctx.pc_iv[1]; 1537 } else 1538 bcopy(&ctx, dmap->d_alloc.dma_vaddr + 1539 offsetof(struct ubsec_dmachunk, d_ctx), 1540 sizeof(struct ubsec_pktctx)); 1541 1542 mtx_lock(&sc->sc_mcr1lock); 1543 SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next); 1544 sc->sc_nqueue++; 1545 ubsecstats.hst_ipackets++; 1546 ubsecstats.hst_ibytes += dmap->d_alloc.dma_size; 1547 if ((hint & CRYPTO_HINT_MORE) == 0 || sc->sc_nqueue >= UBS_MAX_AGGR) 1548 ubsec_feed(sc); 1549 mtx_unlock(&sc->sc_mcr1lock); 1550 return (0); 1551 1552errout: 1553 if (q != NULL) { 1554 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 1555 m_freem(q->q_dst_m); 1556 1557 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1558 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1559 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1560 } 1561 if (q->q_src_map != NULL) { 1562 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1563 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1564 } 1565 } 1566 if (q != NULL || err == ERESTART) { 1567 mtx_lock(&sc->sc_freeqlock); 1568 if (q != NULL) 1569 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1570 if (err == ERESTART) 1571 sc->sc_needwakeup |= CRYPTO_SYMQ; 1572 mtx_unlock(&sc->sc_freeqlock); 1573 } 1574 if (err != ERESTART) { 1575 crp->crp_etype = err; 1576 crypto_done(crp); 1577 } 1578 return (err); 1579} 1580 1581static void 1582ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q) 1583{ 1584 struct cryptop *crp = (struct cryptop *)q->q_crp; 1585 struct cryptodesc *crd; 1586 struct ubsec_dma *dmap = q->q_dma; 1587 1588 ubsecstats.hst_opackets++; 1589 ubsecstats.hst_obytes += dmap->d_alloc.dma_size; 1590 1591 ubsec_dma_sync(&dmap->d_alloc, 1592 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1593 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1594 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, 1595 BUS_DMASYNC_POSTREAD); 1596 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1597 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1598 } 1599 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_POSTWRITE); 1600 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1601 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1602 1603 if ((crp->crp_flags & CRYPTO_F_IMBUF) && (q->q_src_m != q->q_dst_m)) { 1604 m_freem(q->q_src_m); 1605 crp->crp_buf = (caddr_t)q->q_dst_m; 1606 } 1607 ubsecstats.hst_obytes += ((struct mbuf *)crp->crp_buf)->m_len; 1608 1609 /* copy out IV for future use */ 1610 if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) { 1611 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1612 if (crd->crd_alg != CRYPTO_DES_CBC && 1613 crd->crd_alg != CRYPTO_3DES_CBC) 1614 continue; 1615 if (crp->crp_flags & CRYPTO_F_IMBUF) 1616 m_copydata((struct mbuf *)crp->crp_buf, 1617 crd->crd_skip + crd->crd_len - 8, 8, 1618 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); 1619 else if (crp->crp_flags & CRYPTO_F_IOV) { 1620 cuio_copydata((struct uio *)crp->crp_buf, 1621 crd->crd_skip + crd->crd_len - 8, 8, 1622 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); 1623 } 1624 break; 1625 } 1626 } 1627 1628 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1629 if (crd->crd_alg != CRYPTO_MD5_HMAC && 1630 crd->crd_alg != CRYPTO_SHA1_HMAC) 1631 continue; 1632 if (crp->crp_flags & CRYPTO_F_IMBUF) 1633 m_copyback((struct mbuf *)crp->crp_buf, 1634 crd->crd_inject, 1635 sc->sc_sessions[q->q_sesn].ses_mlen, 1636 (caddr_t)dmap->d_dma->d_macbuf); 1637 else if (crp->crp_flags & CRYPTO_F_IOV) 1638 cuio_copyback((struct uio *)crp->crp_buf, 1639 crd->crd_inject, 1640 sc->sc_sessions[q->q_sesn].ses_mlen, 1641 (caddr_t)dmap->d_dma->d_macbuf); 1642 break; 1643 } 1644 mtx_lock(&sc->sc_freeqlock); 1645 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1646 mtx_unlock(&sc->sc_freeqlock); 1647 crypto_done(crp); 1648} 1649 1650static void 1651ubsec_mcopy(struct mbuf *srcm, struct mbuf *dstm, int hoffset, int toffset) 1652{ 1653 int i, j, dlen, slen; 1654 caddr_t dptr, sptr; 1655 1656 j = 0; 1657 sptr = srcm->m_data; 1658 slen = srcm->m_len; 1659 dptr = dstm->m_data; 1660 dlen = dstm->m_len; 1661 1662 while (1) { 1663 for (i = 0; i < min(slen, dlen); i++) { 1664 if (j < hoffset || j >= toffset) 1665 *dptr++ = *sptr++; 1666 slen--; 1667 dlen--; 1668 j++; 1669 } 1670 if (slen == 0) { 1671 srcm = srcm->m_next; 1672 if (srcm == NULL) 1673 return; 1674 sptr = srcm->m_data; 1675 slen = srcm->m_len; 1676 } 1677 if (dlen == 0) { 1678 dstm = dstm->m_next; 1679 if (dstm == NULL) 1680 return; 1681 dptr = dstm->m_data; 1682 dlen = dstm->m_len; 1683 } 1684 } 1685} 1686 1687/* 1688 * feed the key generator, must be called at splimp() or higher. 1689 */ 1690static int 1691ubsec_feed2(struct ubsec_softc *sc) 1692{ 1693 struct ubsec_q2 *q; 1694 1695 while (!SIMPLEQ_EMPTY(&sc->sc_queue2)) { 1696 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR2_FULL) 1697 break; 1698 q = SIMPLEQ_FIRST(&sc->sc_queue2); 1699 1700 ubsec_dma_sync(&q->q_mcr, 1701 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1702 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_PREWRITE); 1703 1704 WRITE_REG(sc, BS_MCR2, q->q_mcr.dma_paddr); 1705 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue2, q, q_next); 1706 --sc->sc_nqueue2; 1707 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip2, q, q_next); 1708 } 1709 return (0); 1710} 1711 1712/* 1713 * Callback for handling random numbers 1714 */ 1715static void 1716ubsec_callback2(struct ubsec_softc *sc, struct ubsec_q2 *q) 1717{ 1718 struct cryptkop *krp; 1719 struct ubsec_ctx_keyop *ctx; 1720 1721 ctx = (struct ubsec_ctx_keyop *)q->q_ctx.dma_vaddr; 1722 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_POSTWRITE); 1723 1724 switch (q->q_type) { 1725#ifndef UBSEC_NO_RNG 1726 case UBS_CTXOP_RNGBYPASS: { 1727 struct ubsec_q2_rng *rng = (struct ubsec_q2_rng *)q; 1728 1729 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_POSTREAD); 1730 (*sc->sc_harvest)(sc->sc_rndtest, 1731 rng->rng_buf.dma_vaddr, 1732 UBSEC_RNG_BUFSIZ*sizeof (u_int32_t)); 1733 rng->rng_used = 0; 1734 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 1735 break; 1736 } 1737#endif 1738 case UBS_CTXOP_MODEXP: { 1739 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 1740 u_int rlen, clen; 1741 1742 krp = me->me_krp; 1743 rlen = (me->me_modbits + 7) / 8; 1744 clen = (krp->krp_param[krp->krp_iparams].crp_nbits + 7) / 8; 1745 1746 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_POSTWRITE); 1747 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_POSTWRITE); 1748 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_POSTREAD); 1749 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_POSTWRITE); 1750 1751 if (clen < rlen) 1752 krp->krp_status = E2BIG; 1753 else { 1754 if (sc->sc_flags & UBS_FLAGS_HWNORM) { 1755 bzero(krp->krp_param[krp->krp_iparams].crp_p, 1756 (krp->krp_param[krp->krp_iparams].crp_nbits 1757 + 7) / 8); 1758 bcopy(me->me_C.dma_vaddr, 1759 krp->krp_param[krp->krp_iparams].crp_p, 1760 (me->me_modbits + 7) / 8); 1761 } else 1762 ubsec_kshift_l(me->me_shiftbits, 1763 me->me_C.dma_vaddr, me->me_normbits, 1764 krp->krp_param[krp->krp_iparams].crp_p, 1765 krp->krp_param[krp->krp_iparams].crp_nbits); 1766 } 1767 1768 crypto_kdone(krp); 1769 1770 /* bzero all potentially sensitive data */ 1771 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 1772 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 1773 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 1774 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 1775 1776 /* Can't free here, so put us on the free list. */ 1777 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &me->me_q, q_next); 1778 break; 1779 } 1780 case UBS_CTXOP_RSAPRIV: { 1781 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 1782 u_int len; 1783 1784 krp = rp->rpr_krp; 1785 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_POSTWRITE); 1786 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_POSTREAD); 1787 1788 len = (krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_nbits + 7) / 8; 1789 bcopy(rp->rpr_msgout.dma_vaddr, 1790 krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_p, len); 1791 1792 crypto_kdone(krp); 1793 1794 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size); 1795 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size); 1796 bzero(rp->rpr_q.q_ctx.dma_vaddr, rp->rpr_q.q_ctx.dma_size); 1797 1798 /* Can't free here, so put us on the free list. */ 1799 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &rp->rpr_q, q_next); 1800 break; 1801 } 1802 default: 1803 device_printf(sc->sc_dev, "unknown ctx op: %x\n", 1804 letoh16(ctx->ctx_op)); 1805 break; 1806 } 1807} 1808 1809#ifndef UBSEC_NO_RNG 1810static void 1811ubsec_rng(void *vsc) 1812{ 1813 struct ubsec_softc *sc = vsc; 1814 struct ubsec_q2_rng *rng = &sc->sc_rng; 1815 struct ubsec_mcr *mcr; 1816 struct ubsec_ctx_rngbypass *ctx; 1817 1818 mtx_lock(&sc->sc_mcr2lock); 1819 if (rng->rng_used) { 1820 mtx_unlock(&sc->sc_mcr2lock); 1821 return; 1822 } 1823 sc->sc_nqueue2++; 1824 if (sc->sc_nqueue2 >= UBS_MAX_NQUEUE) 1825 goto out; 1826 1827 mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr; 1828 ctx = (struct ubsec_ctx_rngbypass *)rng->rng_q.q_ctx.dma_vaddr; 1829 1830 mcr->mcr_pkts = htole16(1); 1831 mcr->mcr_flags = 0; 1832 mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr); 1833 mcr->mcr_ipktbuf.pb_addr = mcr->mcr_ipktbuf.pb_next = 0; 1834 mcr->mcr_ipktbuf.pb_len = 0; 1835 mcr->mcr_reserved = mcr->mcr_pktlen = 0; 1836 mcr->mcr_opktbuf.pb_addr = htole32(rng->rng_buf.dma_paddr); 1837 mcr->mcr_opktbuf.pb_len = htole32(((sizeof(u_int32_t) * UBSEC_RNG_BUFSIZ)) & 1838 UBS_PKTBUF_LEN); 1839 mcr->mcr_opktbuf.pb_next = 0; 1840 1841 ctx->rbp_len = htole16(sizeof(struct ubsec_ctx_rngbypass)); 1842 ctx->rbp_op = htole16(UBS_CTXOP_RNGBYPASS); 1843 rng->rng_q.q_type = UBS_CTXOP_RNGBYPASS; 1844 1845 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_PREREAD); 1846 1847 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rng->rng_q, q_next); 1848 rng->rng_used = 1; 1849 ubsec_feed2(sc); 1850 ubsecstats.hst_rng++; 1851 mtx_unlock(&sc->sc_mcr2lock); 1852 1853 return; 1854 1855out: 1856 /* 1857 * Something weird happened, generate our own call back. 1858 */ 1859 sc->sc_nqueue2--; 1860 mtx_unlock(&sc->sc_mcr2lock); 1861 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 1862} 1863#endif /* UBSEC_NO_RNG */ 1864 1865static void 1866ubsec_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1867{ 1868 bus_addr_t *paddr = (bus_addr_t*) arg; 1869 *paddr = segs->ds_addr; 1870} 1871 1872static int 1873ubsec_dma_malloc( 1874 struct ubsec_softc *sc, 1875 bus_size_t size, 1876 struct ubsec_dma_alloc *dma, 1877 int mapflags 1878) 1879{ 1880 int r; 1881 1882 /* XXX could specify sc_dmat as parent but that just adds overhead */ 1883 r = bus_dma_tag_create(NULL, /* parent */ 1884 1, 0, /* alignment, bounds */ 1885 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1886 BUS_SPACE_MAXADDR, /* highaddr */ 1887 NULL, NULL, /* filter, filterarg */ 1888 size, /* maxsize */ 1889 1, /* nsegments */ 1890 size, /* maxsegsize */ 1891 BUS_DMA_ALLOCNOW, /* flags */ 1892 NULL, NULL, /* lockfunc, lockarg */ 1893 &dma->dma_tag); 1894 if (r != 0) { 1895 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1896 "bus_dma_tag_create failed; error %u\n", r); 1897 goto fail_0; 1898 } 1899 1900 r = bus_dmamap_create(dma->dma_tag, BUS_DMA_NOWAIT, &dma->dma_map); 1901 if (r != 0) { 1902 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1903 "bus_dmamap_create failed; error %u\n", r); 1904 goto fail_1; 1905 } 1906 1907 r = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr, 1908 BUS_DMA_NOWAIT, &dma->dma_map); 1909 if (r != 0) { 1910 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1911 "bus_dmammem_alloc failed; size %zu, error %u\n", 1912 size, r); 1913 goto fail_2; 1914 } 1915 1916 r = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, 1917 size, 1918 ubsec_dmamap_cb, 1919 &dma->dma_paddr, 1920 mapflags | BUS_DMA_NOWAIT); 1921 if (r != 0) { 1922 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1923 "bus_dmamap_load failed; error %u\n", r); 1924 goto fail_3; 1925 } 1926 1927 dma->dma_size = size; 1928 return (0); 1929 1930fail_3: 1931 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1932fail_2: 1933 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1934fail_1: 1935 bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1936 bus_dma_tag_destroy(dma->dma_tag); 1937fail_0: 1938 dma->dma_map = NULL; 1939 dma->dma_tag = NULL; 1940 return (r); 1941} 1942 1943static void 1944ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma) 1945{ 1946 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1947 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1948 bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1949 bus_dma_tag_destroy(dma->dma_tag); 1950} 1951 1952/* 1953 * Resets the board. Values in the regesters are left as is 1954 * from the reset (i.e. initial values are assigned elsewhere). 1955 */ 1956static void 1957ubsec_reset_board(struct ubsec_softc *sc) 1958{ 1959 volatile u_int32_t ctrl; 1960 1961 ctrl = READ_REG(sc, BS_CTRL); 1962 ctrl |= BS_CTRL_RESET; 1963 WRITE_REG(sc, BS_CTRL, ctrl); 1964 1965 /* 1966 * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us 1967 */ 1968 DELAY(10); 1969} 1970 1971/* 1972 * Init Broadcom registers 1973 */ 1974static void 1975ubsec_init_board(struct ubsec_softc *sc) 1976{ 1977 u_int32_t ctrl; 1978 1979 ctrl = READ_REG(sc, BS_CTRL); 1980 ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64); 1981 ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT; 1982 1983 if (sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) 1984 ctrl |= BS_CTRL_MCR2INT; 1985 else 1986 ctrl &= ~BS_CTRL_MCR2INT; 1987 1988 if (sc->sc_flags & UBS_FLAGS_HWNORM) 1989 ctrl &= ~BS_CTRL_SWNORM; 1990 1991 WRITE_REG(sc, BS_CTRL, ctrl); 1992} 1993 1994/* 1995 * Init Broadcom PCI registers 1996 */ 1997static void 1998ubsec_init_pciregs(device_t dev) 1999{ 2000#if 0 2001 u_int32_t misc; 2002 2003 misc = pci_conf_read(pc, pa->pa_tag, BS_RTY_TOUT); 2004 misc = (misc & ~(UBS_PCI_RTY_MASK << UBS_PCI_RTY_SHIFT)) 2005 | ((UBS_DEF_RTY & 0xff) << UBS_PCI_RTY_SHIFT); 2006 misc = (misc & ~(UBS_PCI_TOUT_MASK << UBS_PCI_TOUT_SHIFT)) 2007 | ((UBS_DEF_TOUT & 0xff) << UBS_PCI_TOUT_SHIFT); 2008 pci_conf_write(pc, pa->pa_tag, BS_RTY_TOUT, misc); 2009#endif 2010 2011 /* 2012 * This will set the cache line size to 1, this will 2013 * force the BCM58xx chip just to do burst read/writes. 2014 * Cache line read/writes are to slow 2015 */ 2016 pci_write_config(dev, PCIR_CACHELNSZ, UBS_DEF_CACHELINE, 1); 2017} 2018 2019/* 2020 * Clean up after a chip crash. 2021 * It is assumed that the caller in splimp() 2022 */ 2023static void 2024ubsec_cleanchip(struct ubsec_softc *sc) 2025{ 2026 struct ubsec_q *q; 2027 2028 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 2029 q = SIMPLEQ_FIRST(&sc->sc_qchip); 2030 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q, q_next); 2031 ubsec_free_q(sc, q); 2032 } 2033 sc->sc_nqchip = 0; 2034} 2035 2036/* 2037 * free a ubsec_q 2038 * It is assumed that the caller is within splimp(). 2039 */ 2040static int 2041ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q) 2042{ 2043 struct ubsec_q *q2; 2044 struct cryptop *crp; 2045 int npkts; 2046 int i; 2047 2048 npkts = q->q_nstacked_mcrs; 2049 2050 for (i = 0; i < npkts; i++) { 2051 if(q->q_stacked_mcr[i]) { 2052 q2 = q->q_stacked_mcr[i]; 2053 2054 if ((q2->q_dst_m != NULL) && (q2->q_src_m != q2->q_dst_m)) 2055 m_freem(q2->q_dst_m); 2056 2057 crp = (struct cryptop *)q2->q_crp; 2058 2059 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next); 2060 2061 crp->crp_etype = EFAULT; 2062 crypto_done(crp); 2063 } else { 2064 break; 2065 } 2066 } 2067 2068 /* 2069 * Free header MCR 2070 */ 2071 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 2072 m_freem(q->q_dst_m); 2073 2074 crp = (struct cryptop *)q->q_crp; 2075 2076 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 2077 2078 crp->crp_etype = EFAULT; 2079 crypto_done(crp); 2080 return(0); 2081} 2082 2083/* 2084 * Routine to reset the chip and clean up. 2085 * It is assumed that the caller is in splimp() 2086 */ 2087static void 2088ubsec_totalreset(struct ubsec_softc *sc) 2089{ 2090 ubsec_reset_board(sc); 2091 ubsec_init_board(sc); 2092 ubsec_cleanchip(sc); 2093} 2094 2095static int 2096ubsec_dmamap_aligned(struct ubsec_operand *op) 2097{ 2098 int i; 2099 2100 for (i = 0; i < op->nsegs; i++) { 2101 if (op->segs[i].ds_addr & 3) 2102 return (0); 2103 if ((i != (op->nsegs - 1)) && 2104 (op->segs[i].ds_len & 3)) 2105 return (0); 2106 } 2107 return (1); 2108} 2109 2110static void 2111ubsec_kfree(struct ubsec_softc *sc, struct ubsec_q2 *q) 2112{ 2113 switch (q->q_type) { 2114 case UBS_CTXOP_MODEXP: { 2115 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 2116 2117 ubsec_dma_free(sc, &me->me_q.q_mcr); 2118 ubsec_dma_free(sc, &me->me_q.q_ctx); 2119 ubsec_dma_free(sc, &me->me_M); 2120 ubsec_dma_free(sc, &me->me_E); 2121 ubsec_dma_free(sc, &me->me_C); 2122 ubsec_dma_free(sc, &me->me_epb); 2123 free(me, M_DEVBUF); 2124 break; 2125 } 2126 case UBS_CTXOP_RSAPRIV: { 2127 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 2128 2129 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 2130 ubsec_dma_free(sc, &rp->rpr_q.q_ctx); 2131 ubsec_dma_free(sc, &rp->rpr_msgin); 2132 ubsec_dma_free(sc, &rp->rpr_msgout); 2133 free(rp, M_DEVBUF); 2134 break; 2135 } 2136 default: 2137 device_printf(sc->sc_dev, "invalid kfree 0x%x\n", q->q_type); 2138 break; 2139 } 2140} 2141 2142static int 2143ubsec_kprocess(void *arg, struct cryptkop *krp, int hint) 2144{ 2145 struct ubsec_softc *sc = arg; 2146 int r; 2147 2148 if (krp == NULL || krp->krp_callback == NULL) 2149 return (EINVAL); 2150 2151 while (!SIMPLEQ_EMPTY(&sc->sc_q2free)) { 2152 struct ubsec_q2 *q; 2153 2154 q = SIMPLEQ_FIRST(&sc->sc_q2free); 2155 SIMPLEQ_REMOVE_HEAD(&sc->sc_q2free, q, q_next); 2156 ubsec_kfree(sc, q); 2157 } 2158 2159 switch (krp->krp_op) { 2160 case CRK_MOD_EXP: 2161 if (sc->sc_flags & UBS_FLAGS_HWNORM) 2162 r = ubsec_kprocess_modexp_hw(sc, krp, hint); 2163 else 2164 r = ubsec_kprocess_modexp_sw(sc, krp, hint); 2165 break; 2166 case CRK_MOD_EXP_CRT: 2167 return (ubsec_kprocess_rsapriv(sc, krp, hint)); 2168 default: 2169 device_printf(sc->sc_dev, "kprocess: invalid op 0x%x\n", 2170 krp->krp_op); 2171 krp->krp_status = EOPNOTSUPP; 2172 crypto_kdone(krp); 2173 return (0); 2174 } 2175 return (0); /* silence compiler */ 2176} 2177 2178/* 2179 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (sw normalization) 2180 */ 2181static int 2182ubsec_kprocess_modexp_sw(struct ubsec_softc *sc, struct cryptkop *krp, int hint) 2183{ 2184 struct ubsec_q2_modexp *me; 2185 struct ubsec_mcr *mcr; 2186 struct ubsec_ctx_modexp *ctx; 2187 struct ubsec_pktbuf *epb; 2188 int err = 0; 2189 u_int nbits, normbits, mbits, shiftbits, ebits; 2190 2191 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT); 2192 if (me == NULL) { 2193 err = ENOMEM; 2194 goto errout; 2195 } 2196 bzero(me, sizeof *me); 2197 me->me_krp = krp; 2198 me->me_q.q_type = UBS_CTXOP_MODEXP; 2199 2200 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2201 if (nbits <= 512) 2202 normbits = 512; 2203 else if (nbits <= 768) 2204 normbits = 768; 2205 else if (nbits <= 1024) 2206 normbits = 1024; 2207 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2208 normbits = 1536; 2209 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2210 normbits = 2048; 2211 else { 2212 err = E2BIG; 2213 goto errout; 2214 } 2215 2216 shiftbits = normbits - nbits; 2217 2218 me->me_modbits = nbits; 2219 me->me_shiftbits = shiftbits; 2220 me->me_normbits = normbits; 2221 2222 /* Sanity check: result bits must be >= true modulus bits. */ 2223 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2224 err = ERANGE; 2225 goto errout; 2226 } 2227 2228 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2229 &me->me_q.q_mcr, 0)) { 2230 err = ENOMEM; 2231 goto errout; 2232 } 2233 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2234 2235 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2236 &me->me_q.q_ctx, 0)) { 2237 err = ENOMEM; 2238 goto errout; 2239 } 2240 2241 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2242 if (mbits > nbits) { 2243 err = E2BIG; 2244 goto errout; 2245 } 2246 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2247 err = ENOMEM; 2248 goto errout; 2249 } 2250 ubsec_kshift_r(shiftbits, 2251 krp->krp_param[UBS_MODEXP_PAR_M].crp_p, mbits, 2252 me->me_M.dma_vaddr, normbits); 2253 2254 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2255 err = ENOMEM; 2256 goto errout; 2257 } 2258 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2259 2260 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2261 if (ebits > nbits) { 2262 err = E2BIG; 2263 goto errout; 2264 } 2265 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2266 err = ENOMEM; 2267 goto errout; 2268 } 2269 ubsec_kshift_r(shiftbits, 2270 krp->krp_param[UBS_MODEXP_PAR_E].crp_p, ebits, 2271 me->me_E.dma_vaddr, normbits); 2272 2273 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2274 &me->me_epb, 0)) { 2275 err = ENOMEM; 2276 goto errout; 2277 } 2278 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2279 epb->pb_addr = htole32(me->me_E.dma_paddr); 2280 epb->pb_next = 0; 2281 epb->pb_len = htole32(normbits / 8); 2282 2283#ifdef UBSEC_DEBUG 2284 if (ubsec_debug) { 2285 printf("Epb "); 2286 ubsec_dump_pb(epb); 2287 } 2288#endif 2289 2290 mcr->mcr_pkts = htole16(1); 2291 mcr->mcr_flags = 0; 2292 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2293 mcr->mcr_reserved = 0; 2294 mcr->mcr_pktlen = 0; 2295 2296 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2297 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2298 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2299 2300 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2301 mcr->mcr_opktbuf.pb_next = 0; 2302 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2303 2304#ifdef DIAGNOSTIC 2305 /* Misaligned output buffer will hang the chip. */ 2306 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2307 panic("%s: modexp invalid addr 0x%x\n", 2308 device_get_nameunit(sc->sc_dev), 2309 letoh32(mcr->mcr_opktbuf.pb_addr)); 2310 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2311 panic("%s: modexp invalid len 0x%x\n", 2312 device_get_nameunit(sc->sc_dev), 2313 letoh32(mcr->mcr_opktbuf.pb_len)); 2314#endif 2315 2316 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2317 bzero(ctx, sizeof(*ctx)); 2318 ubsec_kshift_r(shiftbits, 2319 krp->krp_param[UBS_MODEXP_PAR_N].crp_p, nbits, 2320 ctx->me_N, normbits); 2321 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2322 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2323 ctx->me_E_len = htole16(nbits); 2324 ctx->me_N_len = htole16(nbits); 2325 2326#ifdef UBSEC_DEBUG 2327 if (ubsec_debug) { 2328 ubsec_dump_mcr(mcr); 2329 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2330 } 2331#endif 2332 2333 /* 2334 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2335 * everything else. 2336 */ 2337 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE); 2338 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE); 2339 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD); 2340 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE); 2341 2342 /* Enqueue and we're done... */ 2343 mtx_lock(&sc->sc_mcr2lock); 2344 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2345 ubsec_feed2(sc); 2346 ubsecstats.hst_modexp++; 2347 mtx_unlock(&sc->sc_mcr2lock); 2348 2349 return (0); 2350 2351errout: 2352 if (me != NULL) { 2353 if (me->me_q.q_mcr.dma_map != NULL) 2354 ubsec_dma_free(sc, &me->me_q.q_mcr); 2355 if (me->me_q.q_ctx.dma_map != NULL) { 2356 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 2357 ubsec_dma_free(sc, &me->me_q.q_ctx); 2358 } 2359 if (me->me_M.dma_map != NULL) { 2360 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 2361 ubsec_dma_free(sc, &me->me_M); 2362 } 2363 if (me->me_E.dma_map != NULL) { 2364 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 2365 ubsec_dma_free(sc, &me->me_E); 2366 } 2367 if (me->me_C.dma_map != NULL) { 2368 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2369 ubsec_dma_free(sc, &me->me_C); 2370 } 2371 if (me->me_epb.dma_map != NULL) 2372 ubsec_dma_free(sc, &me->me_epb); 2373 free(me, M_DEVBUF); 2374 } 2375 krp->krp_status = err; 2376 crypto_kdone(krp); 2377 return (0); 2378} 2379 2380/* 2381 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (hw normalization) 2382 */ 2383static int 2384ubsec_kprocess_modexp_hw(struct ubsec_softc *sc, struct cryptkop *krp, int hint) 2385{ 2386 struct ubsec_q2_modexp *me; 2387 struct ubsec_mcr *mcr; 2388 struct ubsec_ctx_modexp *ctx; 2389 struct ubsec_pktbuf *epb; 2390 int err = 0; 2391 u_int nbits, normbits, mbits, shiftbits, ebits; 2392 2393 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT); 2394 if (me == NULL) { 2395 err = ENOMEM; 2396 goto errout; 2397 } 2398 bzero(me, sizeof *me); 2399 me->me_krp = krp; 2400 me->me_q.q_type = UBS_CTXOP_MODEXP; 2401 2402 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2403 if (nbits <= 512) 2404 normbits = 512; 2405 else if (nbits <= 768) 2406 normbits = 768; 2407 else if (nbits <= 1024) 2408 normbits = 1024; 2409 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2410 normbits = 1536; 2411 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2412 normbits = 2048; 2413 else { 2414 err = E2BIG; 2415 goto errout; 2416 } 2417 2418 shiftbits = normbits - nbits; 2419 2420 /* XXX ??? */ 2421 me->me_modbits = nbits; 2422 me->me_shiftbits = shiftbits; 2423 me->me_normbits = normbits; 2424 2425 /* Sanity check: result bits must be >= true modulus bits. */ 2426 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2427 err = ERANGE; 2428 goto errout; 2429 } 2430 2431 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2432 &me->me_q.q_mcr, 0)) { 2433 err = ENOMEM; 2434 goto errout; 2435 } 2436 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2437 2438 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2439 &me->me_q.q_ctx, 0)) { 2440 err = ENOMEM; 2441 goto errout; 2442 } 2443 2444 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2445 if (mbits > nbits) { 2446 err = E2BIG; 2447 goto errout; 2448 } 2449 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2450 err = ENOMEM; 2451 goto errout; 2452 } 2453 bzero(me->me_M.dma_vaddr, normbits / 8); 2454 bcopy(krp->krp_param[UBS_MODEXP_PAR_M].crp_p, 2455 me->me_M.dma_vaddr, (mbits + 7) / 8); 2456 2457 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2458 err = ENOMEM; 2459 goto errout; 2460 } 2461 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2462 2463 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2464 if (ebits > nbits) { 2465 err = E2BIG; 2466 goto errout; 2467 } 2468 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2469 err = ENOMEM; 2470 goto errout; 2471 } 2472 bzero(me->me_E.dma_vaddr, normbits / 8); 2473 bcopy(krp->krp_param[UBS_MODEXP_PAR_E].crp_p, 2474 me->me_E.dma_vaddr, (ebits + 7) / 8); 2475 2476 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2477 &me->me_epb, 0)) { 2478 err = ENOMEM; 2479 goto errout; 2480 } 2481 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2482 epb->pb_addr = htole32(me->me_E.dma_paddr); 2483 epb->pb_next = 0; 2484 epb->pb_len = htole32((ebits + 7) / 8); 2485 2486#ifdef UBSEC_DEBUG 2487 if (ubsec_debug) { 2488 printf("Epb "); 2489 ubsec_dump_pb(epb); 2490 } 2491#endif 2492 2493 mcr->mcr_pkts = htole16(1); 2494 mcr->mcr_flags = 0; 2495 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2496 mcr->mcr_reserved = 0; 2497 mcr->mcr_pktlen = 0; 2498 2499 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2500 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2501 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2502 2503 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2504 mcr->mcr_opktbuf.pb_next = 0; 2505 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2506 2507#ifdef DIAGNOSTIC 2508 /* Misaligned output buffer will hang the chip. */ 2509 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2510 panic("%s: modexp invalid addr 0x%x\n", 2511 device_get_nameunit(sc->sc_dev), 2512 letoh32(mcr->mcr_opktbuf.pb_addr)); 2513 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2514 panic("%s: modexp invalid len 0x%x\n", 2515 device_get_nameunit(sc->sc_dev), 2516 letoh32(mcr->mcr_opktbuf.pb_len)); 2517#endif 2518 2519 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2520 bzero(ctx, sizeof(*ctx)); 2521 bcopy(krp->krp_param[UBS_MODEXP_PAR_N].crp_p, ctx->me_N, 2522 (nbits + 7) / 8); 2523 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2524 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2525 ctx->me_E_len = htole16(ebits); 2526 ctx->me_N_len = htole16(nbits); 2527 2528#ifdef UBSEC_DEBUG 2529 if (ubsec_debug) { 2530 ubsec_dump_mcr(mcr); 2531 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2532 } 2533#endif 2534 2535 /* 2536 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2537 * everything else. 2538 */ 2539 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE); 2540 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE); 2541 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD); 2542 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE); 2543 2544 /* Enqueue and we're done... */ 2545 mtx_lock(&sc->sc_mcr2lock); 2546 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2547 ubsec_feed2(sc); 2548 mtx_unlock(&sc->sc_mcr2lock); 2549 2550 return (0); 2551 2552errout: 2553 if (me != NULL) { 2554 if (me->me_q.q_mcr.dma_map != NULL) 2555 ubsec_dma_free(sc, &me->me_q.q_mcr); 2556 if (me->me_q.q_ctx.dma_map != NULL) { 2557 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 2558 ubsec_dma_free(sc, &me->me_q.q_ctx); 2559 } 2560 if (me->me_M.dma_map != NULL) { 2561 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 2562 ubsec_dma_free(sc, &me->me_M); 2563 } 2564 if (me->me_E.dma_map != NULL) { 2565 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 2566 ubsec_dma_free(sc, &me->me_E); 2567 } 2568 if (me->me_C.dma_map != NULL) { 2569 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2570 ubsec_dma_free(sc, &me->me_C); 2571 } 2572 if (me->me_epb.dma_map != NULL) 2573 ubsec_dma_free(sc, &me->me_epb); 2574 free(me, M_DEVBUF); 2575 } 2576 krp->krp_status = err; 2577 crypto_kdone(krp); 2578 return (0); 2579} 2580 2581static int 2582ubsec_kprocess_rsapriv(struct ubsec_softc *sc, struct cryptkop *krp, int hint) 2583{ 2584 struct ubsec_q2_rsapriv *rp = NULL; 2585 struct ubsec_mcr *mcr; 2586 struct ubsec_ctx_rsapriv *ctx; 2587 int err = 0; 2588 u_int padlen, msglen; 2589 2590 msglen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_P]); 2591 padlen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_Q]); 2592 if (msglen > padlen) 2593 padlen = msglen; 2594 2595 if (padlen <= 256) 2596 padlen = 256; 2597 else if (padlen <= 384) 2598 padlen = 384; 2599 else if (padlen <= 512) 2600 padlen = 512; 2601 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 768) 2602 padlen = 768; 2603 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 1024) 2604 padlen = 1024; 2605 else { 2606 err = E2BIG; 2607 goto errout; 2608 } 2609 2610 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DP]) > padlen) { 2611 err = E2BIG; 2612 goto errout; 2613 } 2614 2615 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DQ]) > padlen) { 2616 err = E2BIG; 2617 goto errout; 2618 } 2619 2620 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_PINV]) > padlen) { 2621 err = E2BIG; 2622 goto errout; 2623 } 2624 2625 rp = (struct ubsec_q2_rsapriv *)malloc(sizeof *rp, M_DEVBUF, M_NOWAIT); 2626 if (rp == NULL) 2627 return (ENOMEM); 2628 bzero(rp, sizeof *rp); 2629 rp->rpr_krp = krp; 2630 rp->rpr_q.q_type = UBS_CTXOP_RSAPRIV; 2631 2632 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2633 &rp->rpr_q.q_mcr, 0)) { 2634 err = ENOMEM; 2635 goto errout; 2636 } 2637 mcr = (struct ubsec_mcr *)rp->rpr_q.q_mcr.dma_vaddr; 2638 2639 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rsapriv), 2640 &rp->rpr_q.q_ctx, 0)) { 2641 err = ENOMEM; 2642 goto errout; 2643 } 2644 ctx = (struct ubsec_ctx_rsapriv *)rp->rpr_q.q_ctx.dma_vaddr; 2645 bzero(ctx, sizeof *ctx); 2646 2647 /* Copy in p */ 2648 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_P].crp_p, 2649 &ctx->rpr_buf[0 * (padlen / 8)], 2650 (krp->krp_param[UBS_RSAPRIV_PAR_P].crp_nbits + 7) / 8); 2651 2652 /* Copy in q */ 2653 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_p, 2654 &ctx->rpr_buf[1 * (padlen / 8)], 2655 (krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_nbits + 7) / 8); 2656 2657 /* Copy in dp */ 2658 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_p, 2659 &ctx->rpr_buf[2 * (padlen / 8)], 2660 (krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_nbits + 7) / 8); 2661 2662 /* Copy in dq */ 2663 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_p, 2664 &ctx->rpr_buf[3 * (padlen / 8)], 2665 (krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_nbits + 7) / 8); 2666 2667 /* Copy in pinv */ 2668 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_p, 2669 &ctx->rpr_buf[4 * (padlen / 8)], 2670 (krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_nbits + 7) / 8); 2671 2672 msglen = padlen * 2; 2673 2674 /* Copy in input message (aligned buffer/length). */ 2675 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGIN]) > msglen) { 2676 /* Is this likely? */ 2677 err = E2BIG; 2678 goto errout; 2679 } 2680 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgin, 0)) { 2681 err = ENOMEM; 2682 goto errout; 2683 } 2684 bzero(rp->rpr_msgin.dma_vaddr, (msglen + 7) / 8); 2685 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_p, 2686 rp->rpr_msgin.dma_vaddr, 2687 (krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_nbits + 7) / 8); 2688 2689 /* Prepare space for output message (aligned buffer/length). */ 2690 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT]) < msglen) { 2691 /* Is this likely? */ 2692 err = E2BIG; 2693 goto errout; 2694 } 2695 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgout, 0)) { 2696 err = ENOMEM; 2697 goto errout; 2698 } 2699 bzero(rp->rpr_msgout.dma_vaddr, (msglen + 7) / 8); 2700 2701 mcr->mcr_pkts = htole16(1); 2702 mcr->mcr_flags = 0; 2703 mcr->mcr_cmdctxp = htole32(rp->rpr_q.q_ctx.dma_paddr); 2704 mcr->mcr_ipktbuf.pb_addr = htole32(rp->rpr_msgin.dma_paddr); 2705 mcr->mcr_ipktbuf.pb_next = 0; 2706 mcr->mcr_ipktbuf.pb_len = htole32(rp->rpr_msgin.dma_size); 2707 mcr->mcr_reserved = 0; 2708 mcr->mcr_pktlen = htole16(msglen); 2709 mcr->mcr_opktbuf.pb_addr = htole32(rp->rpr_msgout.dma_paddr); 2710 mcr->mcr_opktbuf.pb_next = 0; 2711 mcr->mcr_opktbuf.pb_len = htole32(rp->rpr_msgout.dma_size); 2712 2713#ifdef DIAGNOSTIC 2714 if (rp->rpr_msgin.dma_paddr & 3 || rp->rpr_msgin.dma_size & 3) { 2715 panic("%s: rsapriv: invalid msgin %x(0x%jx)", 2716 device_get_nameunit(sc->sc_dev), 2717 rp->rpr_msgin.dma_paddr, (uintmax_t)rp->rpr_msgin.dma_size); 2718 } 2719 if (rp->rpr_msgout.dma_paddr & 3 || rp->rpr_msgout.dma_size & 3) { 2720 panic("%s: rsapriv: invalid msgout %x(0x%jx)", 2721 device_get_nameunit(sc->sc_dev), 2722 rp->rpr_msgout.dma_paddr, (uintmax_t)rp->rpr_msgout.dma_size); 2723 } 2724#endif 2725 2726 ctx->rpr_len = (sizeof(u_int16_t) * 4) + (5 * (padlen / 8)); 2727 ctx->rpr_op = htole16(UBS_CTXOP_RSAPRIV); 2728 ctx->rpr_q_len = htole16(padlen); 2729 ctx->rpr_p_len = htole16(padlen); 2730 2731 /* 2732 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2733 * everything else. 2734 */ 2735 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_PREWRITE); 2736 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_PREREAD); 2737 2738 /* Enqueue and we're done... */ 2739 mtx_lock(&sc->sc_mcr2lock); 2740 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rp->rpr_q, q_next); 2741 ubsec_feed2(sc); 2742 ubsecstats.hst_modexpcrt++; 2743 mtx_unlock(&sc->sc_mcr2lock); 2744 return (0); 2745 2746errout: 2747 if (rp != NULL) { 2748 if (rp->rpr_q.q_mcr.dma_map != NULL) 2749 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 2750 if (rp->rpr_msgin.dma_map != NULL) { 2751 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size); 2752 ubsec_dma_free(sc, &rp->rpr_msgin); 2753 } 2754 if (rp->rpr_msgout.dma_map != NULL) { 2755 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size); 2756 ubsec_dma_free(sc, &rp->rpr_msgout); 2757 } 2758 free(rp, M_DEVBUF); 2759 } 2760 krp->krp_status = err; 2761 crypto_kdone(krp); 2762 return (0); 2763} 2764 2765#ifdef UBSEC_DEBUG 2766static void 2767ubsec_dump_pb(volatile struct ubsec_pktbuf *pb) 2768{ 2769 printf("addr 0x%x (0x%x) next 0x%x\n", 2770 pb->pb_addr, pb->pb_len, pb->pb_next); 2771} 2772 2773static void 2774ubsec_dump_ctx2(struct ubsec_ctx_keyop *c) 2775{ 2776 printf("CTX (0x%x):\n", c->ctx_len); 2777 switch (letoh16(c->ctx_op)) { 2778 case UBS_CTXOP_RNGBYPASS: 2779 case UBS_CTXOP_RNGSHA1: 2780 break; 2781 case UBS_CTXOP_MODEXP: 2782 { 2783 struct ubsec_ctx_modexp *cx = (void *)c; 2784 int i, len; 2785 2786 printf(" Elen %u, Nlen %u\n", 2787 letoh16(cx->me_E_len), letoh16(cx->me_N_len)); 2788 len = (cx->me_N_len + 7)/8; 2789 for (i = 0; i < len; i++) 2790 printf("%s%02x", (i == 0) ? " N: " : ":", cx->me_N[i]); 2791 printf("\n"); 2792 break; 2793 } 2794 default: 2795 printf("unknown context: %x\n", c->ctx_op); 2796 } 2797 printf("END CTX\n"); 2798} 2799 2800static void 2801ubsec_dump_mcr(struct ubsec_mcr *mcr) 2802{ 2803 volatile struct ubsec_mcr_add *ma; 2804 int i; 2805 2806 printf("MCR:\n"); 2807 printf(" pkts: %u, flags 0x%x\n", 2808 letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags)); 2809 ma = (volatile struct ubsec_mcr_add *)&mcr->mcr_cmdctxp; 2810 for (i = 0; i < letoh16(mcr->mcr_pkts); i++) { 2811 printf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i, 2812 letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen), 2813 letoh16(ma->mcr_reserved)); 2814 printf(" %d: ipkt ", i); 2815 ubsec_dump_pb(&ma->mcr_ipktbuf); 2816 printf(" %d: opkt ", i); 2817 ubsec_dump_pb(&ma->mcr_opktbuf); 2818 ma++; 2819 } 2820 printf("END MCR\n"); 2821} 2822#endif /* UBSEC_DEBUG */ 2823 2824/* 2825 * Return the number of significant bits of a big number. 2826 */ 2827static int 2828ubsec_ksigbits(struct crparam *cr) 2829{ 2830 u_int plen = (cr->crp_nbits + 7) / 8; 2831 int i, sig = plen * 8; 2832 u_int8_t c, *p = cr->crp_p; 2833 2834 for (i = plen - 1; i >= 0; i--) { 2835 c = p[i]; 2836 if (c != 0) { 2837 while ((c & 0x80) == 0) { 2838 sig--; 2839 c <<= 1; 2840 } 2841 break; 2842 } 2843 sig -= 8; 2844 } 2845 return (sig); 2846} 2847 2848static void 2849ubsec_kshift_r( 2850 u_int shiftbits, 2851 u_int8_t *src, u_int srcbits, 2852 u_int8_t *dst, u_int dstbits) 2853{ 2854 u_int slen, dlen; 2855 int i, si, di, n; 2856 2857 slen = (srcbits + 7) / 8; 2858 dlen = (dstbits + 7) / 8; 2859 2860 for (i = 0; i < slen; i++) 2861 dst[i] = src[i]; 2862 for (i = 0; i < dlen - slen; i++) 2863 dst[slen + i] = 0; 2864 2865 n = shiftbits / 8; 2866 if (n != 0) { 2867 si = dlen - n - 1; 2868 di = dlen - 1; 2869 while (si >= 0) 2870 dst[di--] = dst[si--]; 2871 while (di >= 0) 2872 dst[di--] = 0; 2873 } 2874 2875 n = shiftbits % 8; 2876 if (n != 0) { 2877 for (i = dlen - 1; i > 0; i--) 2878 dst[i] = (dst[i] << n) | 2879 (dst[i - 1] >> (8 - n)); 2880 dst[0] = dst[0] << n; 2881 } 2882} 2883 2884static void 2885ubsec_kshift_l( 2886 u_int shiftbits, 2887 u_int8_t *src, u_int srcbits, 2888 u_int8_t *dst, u_int dstbits) 2889{ 2890 int slen, dlen, i, n; 2891 2892 slen = (srcbits + 7) / 8; 2893 dlen = (dstbits + 7) / 8; 2894 2895 n = shiftbits / 8; 2896 for (i = 0; i < slen; i++) 2897 dst[i] = src[i + n]; 2898 for (i = 0; i < dlen - slen; i++) 2899 dst[slen + i] = 0; 2900 2901 n = shiftbits % 8; 2902 if (n != 0) { 2903 for (i = 0; i < (dlen - 1); i++) 2904 dst[i] = (dst[i] >> n) | (dst[i + 1] << (8 - n)); 2905 dst[dlen - 1] = dst[dlen - 1] >> n; 2906 } 2907} 2908