ubsec.c revision 127135
1/* $OpenBSD: ubsec.c,v 1.115 2002/09/24 18:33:26 jason Exp $ */ 2 3/* 4 * Copyright (c) 2000 Jason L. Wright (jason@thought.net) 5 * Copyright (c) 2000 Theo de Raadt (deraadt@openbsd.org) 6 * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com) 7 * 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Jason L. Wright 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 32 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 33 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Effort sponsored in part by the Defense Advanced Research Projects 37 * Agency (DARPA) and Air Force Research Laboratory, Air Force 38 * Materiel Command, USAF, under agreement number F30602-01-2-0537. 39 */ 40 41#include <sys/cdefs.h> 42__FBSDID("$FreeBSD: head/sys/dev/ubsec/ubsec.c 127135 2004-03-17 17:50:55Z njl $"); 43 44/* 45 * uBsec 5[56]01, 58xx hardware crypto accelerator 46 */ 47 48#include "opt_ubsec.h" 49 50#include <sys/param.h> 51#include <sys/systm.h> 52#include <sys/proc.h> 53#include <sys/errno.h> 54#include <sys/malloc.h> 55#include <sys/kernel.h> 56#include <sys/mbuf.h> 57#include <sys/lock.h> 58#include <sys/mutex.h> 59#include <sys/sysctl.h> 60#include <sys/endian.h> 61 62#include <vm/vm.h> 63#include <vm/pmap.h> 64 65#include <machine/clock.h> 66#include <machine/bus.h> 67#include <machine/resource.h> 68#include <sys/bus.h> 69#include <sys/rman.h> 70 71#include <crypto/sha1.h> 72#include <opencrypto/cryptodev.h> 73#include <opencrypto/cryptosoft.h> 74#include <sys/md5.h> 75#include <sys/random.h> 76 77#include <dev/pci/pcivar.h> 78#include <dev/pci/pcireg.h> 79 80/* grr, #defines for gratuitous incompatibility in queue.h */ 81#define SIMPLEQ_HEAD STAILQ_HEAD 82#define SIMPLEQ_ENTRY STAILQ_ENTRY 83#define SIMPLEQ_INIT STAILQ_INIT 84#define SIMPLEQ_INSERT_TAIL STAILQ_INSERT_TAIL 85#define SIMPLEQ_EMPTY STAILQ_EMPTY 86#define SIMPLEQ_FIRST STAILQ_FIRST 87#define SIMPLEQ_REMOVE_HEAD STAILQ_REMOVE_HEAD_UNTIL 88#define SIMPLEQ_FOREACH STAILQ_FOREACH 89/* ditto for endian.h */ 90#define letoh16(x) le16toh(x) 91#define letoh32(x) le32toh(x) 92 93#ifdef UBSEC_RNDTEST 94#include <dev/rndtest/rndtest.h> 95#endif 96#include <dev/ubsec/ubsecreg.h> 97#include <dev/ubsec/ubsecvar.h> 98 99/* 100 * Prototypes and count for the pci_device structure 101 */ 102static int ubsec_probe(device_t); 103static int ubsec_attach(device_t); 104static int ubsec_detach(device_t); 105static int ubsec_suspend(device_t); 106static int ubsec_resume(device_t); 107static void ubsec_shutdown(device_t); 108 109static device_method_t ubsec_methods[] = { 110 /* Device interface */ 111 DEVMETHOD(device_probe, ubsec_probe), 112 DEVMETHOD(device_attach, ubsec_attach), 113 DEVMETHOD(device_detach, ubsec_detach), 114 DEVMETHOD(device_suspend, ubsec_suspend), 115 DEVMETHOD(device_resume, ubsec_resume), 116 DEVMETHOD(device_shutdown, ubsec_shutdown), 117 118 /* bus interface */ 119 DEVMETHOD(bus_print_child, bus_generic_print_child), 120 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 121 122 { 0, 0 } 123}; 124static driver_t ubsec_driver = { 125 "ubsec", 126 ubsec_methods, 127 sizeof (struct ubsec_softc) 128}; 129static devclass_t ubsec_devclass; 130 131DRIVER_MODULE(ubsec, pci, ubsec_driver, ubsec_devclass, 0, 0); 132MODULE_DEPEND(ubsec, crypto, 1, 1, 1); 133#ifdef UBSEC_RNDTEST 134MODULE_DEPEND(ubsec, rndtest, 1, 1, 1); 135#endif 136 137static void ubsec_intr(void *); 138static int ubsec_newsession(void *, u_int32_t *, struct cryptoini *); 139static int ubsec_freesession(void *, u_int64_t); 140static int ubsec_process(void *, struct cryptop *, int); 141static void ubsec_callback(struct ubsec_softc *, struct ubsec_q *); 142static void ubsec_feed(struct ubsec_softc *); 143static void ubsec_mcopy(struct mbuf *, struct mbuf *, int, int); 144static void ubsec_callback2(struct ubsec_softc *, struct ubsec_q2 *); 145static int ubsec_feed2(struct ubsec_softc *); 146static void ubsec_rng(void *); 147static int ubsec_dma_malloc(struct ubsec_softc *, bus_size_t, 148 struct ubsec_dma_alloc *, int); 149#define ubsec_dma_sync(_dma, _flags) \ 150 bus_dmamap_sync((_dma)->dma_tag, (_dma)->dma_map, (_flags)) 151static void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *); 152static int ubsec_dmamap_aligned(struct ubsec_operand *op); 153 154static void ubsec_reset_board(struct ubsec_softc *sc); 155static void ubsec_init_board(struct ubsec_softc *sc); 156static void ubsec_init_pciregs(device_t dev); 157static void ubsec_totalreset(struct ubsec_softc *sc); 158 159static int ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q); 160 161static int ubsec_kprocess(void*, struct cryptkop *, int); 162static int ubsec_kprocess_modexp_hw(struct ubsec_softc *, struct cryptkop *, int); 163static int ubsec_kprocess_modexp_sw(struct ubsec_softc *, struct cryptkop *, int); 164static int ubsec_kprocess_rsapriv(struct ubsec_softc *, struct cryptkop *, int); 165static void ubsec_kfree(struct ubsec_softc *, struct ubsec_q2 *); 166static int ubsec_ksigbits(struct crparam *); 167static void ubsec_kshift_r(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 168static void ubsec_kshift_l(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 169 170SYSCTL_NODE(_hw, OID_AUTO, ubsec, CTLFLAG_RD, 0, "Broadcom driver parameters"); 171 172#ifdef UBSEC_DEBUG 173static void ubsec_dump_pb(volatile struct ubsec_pktbuf *); 174static void ubsec_dump_mcr(struct ubsec_mcr *); 175static void ubsec_dump_ctx2(struct ubsec_ctx_keyop *); 176 177static int ubsec_debug = 0; 178SYSCTL_INT(_hw_ubsec, OID_AUTO, debug, CTLFLAG_RW, &ubsec_debug, 179 0, "control debugging msgs"); 180#endif 181 182#define READ_REG(sc,r) \ 183 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r)) 184 185#define WRITE_REG(sc,reg,val) \ 186 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val) 187 188#define SWAP32(x) (x) = htole32(ntohl((x))) 189#define HTOLE32(x) (x) = htole32(x) 190 191struct ubsec_stats ubsecstats; 192SYSCTL_STRUCT(_hw_ubsec, OID_AUTO, stats, CTLFLAG_RD, &ubsecstats, 193 ubsec_stats, "driver statistics"); 194 195static int 196ubsec_probe(device_t dev) 197{ 198 if (pci_get_vendor(dev) == PCI_VENDOR_SUN && 199 (pci_get_device(dev) == PCI_PRODUCT_SUN_5821 || 200 pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K)) 201 return (0); 202 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL && 203 (pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5501 || 204 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601)) 205 return (0); 206 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 207 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5801 || 208 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 || 209 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805 || 210 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820 || 211 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 || 212 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 || 213 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823 214 )) 215 return (0); 216 return (ENXIO); 217} 218 219static const char* 220ubsec_partname(struct ubsec_softc *sc) 221{ 222 /* XXX sprintf numbers when not decoded */ 223 switch (pci_get_vendor(sc->sc_dev)) { 224 case PCI_VENDOR_BROADCOM: 225 switch (pci_get_device(sc->sc_dev)) { 226 case PCI_PRODUCT_BROADCOM_5801: return "Broadcom 5801"; 227 case PCI_PRODUCT_BROADCOM_5802: return "Broadcom 5802"; 228 case PCI_PRODUCT_BROADCOM_5805: return "Broadcom 5805"; 229 case PCI_PRODUCT_BROADCOM_5820: return "Broadcom 5820"; 230 case PCI_PRODUCT_BROADCOM_5821: return "Broadcom 5821"; 231 case PCI_PRODUCT_BROADCOM_5822: return "Broadcom 5822"; 232 case PCI_PRODUCT_BROADCOM_5823: return "Broadcom 5823"; 233 } 234 return "Broadcom unknown-part"; 235 case PCI_VENDOR_BLUESTEEL: 236 switch (pci_get_device(sc->sc_dev)) { 237 case PCI_PRODUCT_BLUESTEEL_5601: return "Bluesteel 5601"; 238 } 239 return "Bluesteel unknown-part"; 240 case PCI_VENDOR_SUN: 241 switch (pci_get_device(sc->sc_dev)) { 242 case PCI_PRODUCT_SUN_5821: return "Sun Crypto 5821"; 243 case PCI_PRODUCT_SUN_SCA1K: return "Sun Crypto 1K"; 244 } 245 return "Sun unknown-part"; 246 } 247 return "Unknown-vendor unknown-part"; 248} 249 250static void 251default_harvest(struct rndtest_state *rsp, void *buf, u_int count) 252{ 253 random_harvest(buf, count, count*NBBY, 0, RANDOM_PURE); 254} 255 256static int 257ubsec_attach(device_t dev) 258{ 259 struct ubsec_softc *sc = device_get_softc(dev); 260 struct ubsec_dma *dmap; 261 u_int32_t cmd, i; 262 int rid; 263 264 bzero(sc, sizeof (*sc)); 265 sc->sc_dev = dev; 266 267 SIMPLEQ_INIT(&sc->sc_queue); 268 SIMPLEQ_INIT(&sc->sc_qchip); 269 SIMPLEQ_INIT(&sc->sc_queue2); 270 SIMPLEQ_INIT(&sc->sc_qchip2); 271 SIMPLEQ_INIT(&sc->sc_q2free); 272 273 /* XXX handle power management */ 274 275 sc->sc_statmask = BS_STAT_MCR1_DONE | BS_STAT_DMAERR; 276 277 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL && 278 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601) 279 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG; 280 281 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 282 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 || 283 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805)) 284 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG; 285 286 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 287 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820) 288 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG | 289 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY; 290 291 if ((pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 292 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 || 293 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 || 294 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823)) || 295 (pci_get_vendor(dev) == PCI_VENDOR_SUN && 296 (pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K || 297 pci_get_device(dev) == PCI_PRODUCT_SUN_5821))) { 298 /* NB: the 5821/5822 defines some additional status bits */ 299 sc->sc_statmask |= BS_STAT_MCR1_ALLEMPTY | 300 BS_STAT_MCR2_ALLEMPTY; 301 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG | 302 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY; 303 } 304 305 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 306 cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN; 307 pci_write_config(dev, PCIR_COMMAND, cmd, 4); 308 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 309 310 if (!(cmd & PCIM_CMD_MEMEN)) { 311 device_printf(dev, "failed to enable memory mapping\n"); 312 goto bad; 313 } 314 315 if (!(cmd & PCIM_CMD_BUSMASTEREN)) { 316 device_printf(dev, "failed to enable bus mastering\n"); 317 goto bad; 318 } 319 320 /* 321 * Setup memory-mapping of PCI registers. 322 */ 323 rid = BS_BAR; 324 sc->sc_sr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 325 RF_ACTIVE); 326 if (sc->sc_sr == NULL) { 327 device_printf(dev, "cannot map register space\n"); 328 goto bad; 329 } 330 sc->sc_st = rman_get_bustag(sc->sc_sr); 331 sc->sc_sh = rman_get_bushandle(sc->sc_sr); 332 333 /* 334 * Arrange interrupt line. 335 */ 336 rid = 0; 337 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 338 RF_SHAREABLE|RF_ACTIVE); 339 if (sc->sc_irq == NULL) { 340 device_printf(dev, "could not map interrupt\n"); 341 goto bad1; 342 } 343 /* 344 * NB: Network code assumes we are blocked with splimp() 345 * so make sure the IRQ is mapped appropriately. 346 */ 347 if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE, 348 ubsec_intr, sc, &sc->sc_ih)) { 349 device_printf(dev, "could not establish interrupt\n"); 350 goto bad2; 351 } 352 353 sc->sc_cid = crypto_get_driverid(0); 354 if (sc->sc_cid < 0) { 355 device_printf(dev, "could not get crypto driver id\n"); 356 goto bad3; 357 } 358 359 /* 360 * Setup DMA descriptor area. 361 */ 362 if (bus_dma_tag_create(NULL, /* parent */ 363 1, 0, /* alignment, bounds */ 364 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 365 BUS_SPACE_MAXADDR, /* highaddr */ 366 NULL, NULL, /* filter, filterarg */ 367 0x3ffff, /* maxsize */ 368 UBS_MAX_SCATTER, /* nsegments */ 369 0xffff, /* maxsegsize */ 370 BUS_DMA_ALLOCNOW, /* flags */ 371 NULL, NULL, /* lockfunc, lockarg */ 372 &sc->sc_dmat)) { 373 device_printf(dev, "cannot allocate DMA tag\n"); 374 goto bad4; 375 } 376 SIMPLEQ_INIT(&sc->sc_freequeue); 377 dmap = sc->sc_dmaa; 378 for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) { 379 struct ubsec_q *q; 380 381 q = (struct ubsec_q *)malloc(sizeof(struct ubsec_q), 382 M_DEVBUF, M_NOWAIT); 383 if (q == NULL) { 384 device_printf(dev, "cannot allocate queue buffers\n"); 385 break; 386 } 387 388 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_dmachunk), 389 &dmap->d_alloc, 0)) { 390 device_printf(dev, "cannot allocate dma buffers\n"); 391 free(q, M_DEVBUF); 392 break; 393 } 394 dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr; 395 396 q->q_dma = dmap; 397 sc->sc_queuea[i] = q; 398 399 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 400 } 401 mtx_init(&sc->sc_mcr1lock, device_get_nameunit(dev), 402 "mcr1 operations", MTX_DEF); 403 mtx_init(&sc->sc_freeqlock, device_get_nameunit(dev), 404 "mcr1 free q", MTX_DEF); 405 406 device_printf(sc->sc_dev, "%s\n", ubsec_partname(sc)); 407 408 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0, 409 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 410 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0, 411 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 412 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0, 413 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 414 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0, 415 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 416 417 /* 418 * Reset Broadcom chip 419 */ 420 ubsec_reset_board(sc); 421 422 /* 423 * Init Broadcom specific PCI settings 424 */ 425 ubsec_init_pciregs(dev); 426 427 /* 428 * Init Broadcom chip 429 */ 430 ubsec_init_board(sc); 431 432#ifndef UBSEC_NO_RNG 433 if (sc->sc_flags & UBS_FLAGS_RNG) { 434 sc->sc_statmask |= BS_STAT_MCR2_DONE; 435#ifdef UBSEC_RNDTEST 436 sc->sc_rndtest = rndtest_attach(dev); 437 if (sc->sc_rndtest) 438 sc->sc_harvest = rndtest_harvest; 439 else 440 sc->sc_harvest = default_harvest; 441#else 442 sc->sc_harvest = default_harvest; 443#endif 444 445 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 446 &sc->sc_rng.rng_q.q_mcr, 0)) 447 goto skip_rng; 448 449 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rngbypass), 450 &sc->sc_rng.rng_q.q_ctx, 0)) { 451 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 452 goto skip_rng; 453 } 454 455 if (ubsec_dma_malloc(sc, sizeof(u_int32_t) * 456 UBSEC_RNG_BUFSIZ, &sc->sc_rng.rng_buf, 0)) { 457 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx); 458 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 459 goto skip_rng; 460 } 461 462 if (hz >= 100) 463 sc->sc_rnghz = hz / 100; 464 else 465 sc->sc_rnghz = 1; 466 callout_init(&sc->sc_rngto, CALLOUT_MPSAFE); 467 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 468skip_rng: 469 ; 470 } 471#endif /* UBSEC_NO_RNG */ 472 mtx_init(&sc->sc_mcr2lock, device_get_nameunit(dev), 473 "mcr2 operations", MTX_DEF); 474 475 if (sc->sc_flags & UBS_FLAGS_KEY) { 476 sc->sc_statmask |= BS_STAT_MCR2_DONE; 477 478 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0, 479 ubsec_kprocess, sc); 480#if 0 481 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0, 482 ubsec_kprocess, sc); 483#endif 484 } 485 return (0); 486bad4: 487 crypto_unregister_all(sc->sc_cid); 488bad3: 489 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 490bad2: 491 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 492bad1: 493 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 494bad: 495 return (ENXIO); 496} 497 498/* 499 * Detach a device that successfully probed. 500 */ 501static int 502ubsec_detach(device_t dev) 503{ 504 struct ubsec_softc *sc = device_get_softc(dev); 505 506 /* XXX wait/abort active ops */ 507 508 /* disable interrupts */ 509 WRITE_REG(sc, BS_CTRL, READ_REG(sc, BS_CTRL) &~ 510 (BS_CTRL_MCR2INT | BS_CTRL_MCR1INT | BS_CTRL_DMAERR)); 511 512 callout_stop(&sc->sc_rngto); 513 514 crypto_unregister_all(sc->sc_cid); 515 516#ifdef UBSEC_RNDTEST 517 if (sc->sc_rndtest) 518 rndtest_detach(sc->sc_rndtest); 519#endif 520 521 while (!SIMPLEQ_EMPTY(&sc->sc_freequeue)) { 522 struct ubsec_q *q; 523 524 q = SIMPLEQ_FIRST(&sc->sc_freequeue); 525 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q, q_next); 526 ubsec_dma_free(sc, &q->q_dma->d_alloc); 527 free(q, M_DEVBUF); 528 } 529 mtx_destroy(&sc->sc_mcr1lock); 530#ifndef UBSEC_NO_RNG 531 if (sc->sc_flags & UBS_FLAGS_RNG) { 532 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 533 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx); 534 ubsec_dma_free(sc, &sc->sc_rng.rng_buf); 535 } 536#endif /* UBSEC_NO_RNG */ 537 mtx_destroy(&sc->sc_mcr2lock); 538 539 bus_generic_detach(dev); 540 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 541 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 542 543 bus_dma_tag_destroy(sc->sc_dmat); 544 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 545 546 return (0); 547} 548 549/* 550 * Stop all chip i/o so that the kernel's probe routines don't 551 * get confused by errant DMAs when rebooting. 552 */ 553static void 554ubsec_shutdown(device_t dev) 555{ 556#ifdef notyet 557 ubsec_stop(device_get_softc(dev)); 558#endif 559} 560 561/* 562 * Device suspend routine. 563 */ 564static int 565ubsec_suspend(device_t dev) 566{ 567 struct ubsec_softc *sc = device_get_softc(dev); 568 569#ifdef notyet 570 /* XXX stop the device and save PCI settings */ 571#endif 572 sc->sc_suspended = 1; 573 574 return (0); 575} 576 577static int 578ubsec_resume(device_t dev) 579{ 580 struct ubsec_softc *sc = device_get_softc(dev); 581 582#ifdef notyet 583 /* XXX retore PCI settings and start the device */ 584#endif 585 sc->sc_suspended = 0; 586 return (0); 587} 588 589/* 590 * UBSEC Interrupt routine 591 */ 592static void 593ubsec_intr(void *arg) 594{ 595 struct ubsec_softc *sc = arg; 596 volatile u_int32_t stat; 597 struct ubsec_q *q; 598 struct ubsec_dma *dmap; 599 int npkts = 0, i; 600 601 stat = READ_REG(sc, BS_STAT); 602 stat &= sc->sc_statmask; 603 if (stat == 0) 604 return; 605 606 WRITE_REG(sc, BS_STAT, stat); /* IACK */ 607 608 /* 609 * Check to see if we have any packets waiting for us 610 */ 611 if ((stat & BS_STAT_MCR1_DONE)) { 612 mtx_lock(&sc->sc_mcr1lock); 613 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 614 q = SIMPLEQ_FIRST(&sc->sc_qchip); 615 dmap = q->q_dma; 616 617 if ((dmap->d_dma->d_mcr.mcr_flags & htole16(UBS_MCR_DONE)) == 0) 618 break; 619 620 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q, q_next); 621 622 npkts = q->q_nstacked_mcrs; 623 sc->sc_nqchip -= 1+npkts; 624 /* 625 * search for further sc_qchip ubsec_q's that share 626 * the same MCR, and complete them too, they must be 627 * at the top. 628 */ 629 for (i = 0; i < npkts; i++) { 630 if(q->q_stacked_mcr[i]) { 631 ubsec_callback(sc, q->q_stacked_mcr[i]); 632 } else { 633 break; 634 } 635 } 636 ubsec_callback(sc, q); 637 } 638 /* 639 * Don't send any more packet to chip if there has been 640 * a DMAERR. 641 */ 642 if (!(stat & BS_STAT_DMAERR)) 643 ubsec_feed(sc); 644 mtx_unlock(&sc->sc_mcr1lock); 645 } 646 647 /* 648 * Check to see if we have any key setups/rng's waiting for us 649 */ 650 if ((sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) && 651 (stat & BS_STAT_MCR2_DONE)) { 652 struct ubsec_q2 *q2; 653 struct ubsec_mcr *mcr; 654 655 mtx_lock(&sc->sc_mcr2lock); 656 while (!SIMPLEQ_EMPTY(&sc->sc_qchip2)) { 657 q2 = SIMPLEQ_FIRST(&sc->sc_qchip2); 658 659 ubsec_dma_sync(&q2->q_mcr, 660 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 661 662 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr; 663 if ((mcr->mcr_flags & htole16(UBS_MCR_DONE)) == 0) { 664 ubsec_dma_sync(&q2->q_mcr, 665 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 666 break; 667 } 668 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip2, q2, q_next); 669 ubsec_callback2(sc, q2); 670 /* 671 * Don't send any more packet to chip if there has been 672 * a DMAERR. 673 */ 674 if (!(stat & BS_STAT_DMAERR)) 675 ubsec_feed2(sc); 676 } 677 mtx_unlock(&sc->sc_mcr2lock); 678 } 679 680 /* 681 * Check to see if we got any DMA Error 682 */ 683 if (stat & BS_STAT_DMAERR) { 684#ifdef UBSEC_DEBUG 685 if (ubsec_debug) { 686 volatile u_int32_t a = READ_REG(sc, BS_ERR); 687 688 printf("dmaerr %s@%08x\n", 689 (a & BS_ERR_READ) ? "read" : "write", 690 a & BS_ERR_ADDR); 691 } 692#endif /* UBSEC_DEBUG */ 693 ubsecstats.hst_dmaerr++; 694 mtx_lock(&sc->sc_mcr1lock); 695 ubsec_totalreset(sc); 696 ubsec_feed(sc); 697 mtx_unlock(&sc->sc_mcr1lock); 698 } 699 700 if (sc->sc_needwakeup) { /* XXX check high watermark */ 701 int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 702#ifdef UBSEC_DEBUG 703 if (ubsec_debug) 704 device_printf(sc->sc_dev, "wakeup crypto (%x)\n", 705 sc->sc_needwakeup); 706#endif /* UBSEC_DEBUG */ 707 sc->sc_needwakeup &= ~wakeup; 708 crypto_unblock(sc->sc_cid, wakeup); 709 } 710} 711 712/* 713 * ubsec_feed() - aggregate and post requests to chip 714 */ 715static void 716ubsec_feed(struct ubsec_softc *sc) 717{ 718 struct ubsec_q *q, *q2; 719 int npkts, i; 720 void *v; 721 u_int32_t stat; 722 723 /* 724 * Decide how many ops to combine in a single MCR. We cannot 725 * aggregate more than UBS_MAX_AGGR because this is the number 726 * of slots defined in the data structure. Note that 727 * aggregation only happens if ops are marked batch'able. 728 * Aggregating ops reduces the number of interrupts to the host 729 * but also (potentially) increases the latency for processing 730 * completed ops as we only get an interrupt when all aggregated 731 * ops have completed. 732 */ 733 if (sc->sc_nqueue == 0) 734 return; 735 if (sc->sc_nqueue > 1) { 736 npkts = 0; 737 SIMPLEQ_FOREACH(q, &sc->sc_queue, q_next) { 738 npkts++; 739 if ((q->q_crp->crp_flags & CRYPTO_F_BATCH) == 0) 740 break; 741 } 742 } else 743 npkts = 1; 744 /* 745 * Check device status before going any further. 746 */ 747 if ((stat = READ_REG(sc, BS_STAT)) & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { 748 if (stat & BS_STAT_DMAERR) { 749 ubsec_totalreset(sc); 750 ubsecstats.hst_dmaerr++; 751 } else 752 ubsecstats.hst_mcr1full++; 753 return; 754 } 755 if (sc->sc_nqueue > ubsecstats.hst_maxqueue) 756 ubsecstats.hst_maxqueue = sc->sc_nqueue; 757 if (npkts > UBS_MAX_AGGR) 758 npkts = UBS_MAX_AGGR; 759 if (npkts < 2) /* special case 1 op */ 760 goto feed1; 761 762 ubsecstats.hst_totbatch += npkts-1; 763#ifdef UBSEC_DEBUG 764 if (ubsec_debug) 765 printf("merging %d records\n", npkts); 766#endif /* UBSEC_DEBUG */ 767 768 q = SIMPLEQ_FIRST(&sc->sc_queue); 769 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q, q_next); 770 --sc->sc_nqueue; 771 772 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE); 773 if (q->q_dst_map != NULL) 774 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD); 775 776 q->q_nstacked_mcrs = npkts - 1; /* Number of packets stacked */ 777 778 for (i = 0; i < q->q_nstacked_mcrs; i++) { 779 q2 = SIMPLEQ_FIRST(&sc->sc_queue); 780 bus_dmamap_sync(sc->sc_dmat, q2->q_src_map, 781 BUS_DMASYNC_PREWRITE); 782 if (q2->q_dst_map != NULL) 783 bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map, 784 BUS_DMASYNC_PREREAD); 785 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q2, q_next); 786 --sc->sc_nqueue; 787 788 v = (void*)(((char *)&q2->q_dma->d_dma->d_mcr) + sizeof(struct ubsec_mcr) - 789 sizeof(struct ubsec_mcr_add)); 790 bcopy(v, &q->q_dma->d_dma->d_mcradd[i], sizeof(struct ubsec_mcr_add)); 791 q->q_stacked_mcr[i] = q2; 792 } 793 q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts); 794 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 795 sc->sc_nqchip += npkts; 796 if (sc->sc_nqchip > ubsecstats.hst_maxqchip) 797 ubsecstats.hst_maxqchip = sc->sc_nqchip; 798 ubsec_dma_sync(&q->q_dma->d_alloc, 799 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 800 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 801 offsetof(struct ubsec_dmachunk, d_mcr)); 802 return; 803feed1: 804 q = SIMPLEQ_FIRST(&sc->sc_queue); 805 806 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE); 807 if (q->q_dst_map != NULL) 808 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD); 809 ubsec_dma_sync(&q->q_dma->d_alloc, 810 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 811 812 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 813 offsetof(struct ubsec_dmachunk, d_mcr)); 814#ifdef UBSEC_DEBUG 815 if (ubsec_debug) 816 printf("feed1: q->chip %p %08x stat %08x\n", 817 q, (u_int32_t)vtophys(&q->q_dma->d_dma->d_mcr), 818 stat); 819#endif /* UBSEC_DEBUG */ 820 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q, q_next); 821 --sc->sc_nqueue; 822 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 823 sc->sc_nqchip++; 824 if (sc->sc_nqchip > ubsecstats.hst_maxqchip) 825 ubsecstats.hst_maxqchip = sc->sc_nqchip; 826 return; 827} 828 829/* 830 * Allocate a new 'session' and return an encoded session id. 'sidp' 831 * contains our registration id, and should contain an encoded session 832 * id on successful allocation. 833 */ 834static int 835ubsec_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri) 836{ 837 struct cryptoini *c, *encini = NULL, *macini = NULL; 838 struct ubsec_softc *sc = arg; 839 struct ubsec_session *ses = NULL; 840 MD5_CTX md5ctx; 841 SHA1_CTX sha1ctx; 842 int i, sesn; 843 844 if (sidp == NULL || cri == NULL || sc == NULL) 845 return (EINVAL); 846 847 for (c = cri; c != NULL; c = c->cri_next) { 848 if (c->cri_alg == CRYPTO_MD5_HMAC || 849 c->cri_alg == CRYPTO_SHA1_HMAC) { 850 if (macini) 851 return (EINVAL); 852 macini = c; 853 } else if (c->cri_alg == CRYPTO_DES_CBC || 854 c->cri_alg == CRYPTO_3DES_CBC) { 855 if (encini) 856 return (EINVAL); 857 encini = c; 858 } else 859 return (EINVAL); 860 } 861 if (encini == NULL && macini == NULL) 862 return (EINVAL); 863 864 if (sc->sc_sessions == NULL) { 865 ses = sc->sc_sessions = (struct ubsec_session *)malloc( 866 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT); 867 if (ses == NULL) 868 return (ENOMEM); 869 sesn = 0; 870 sc->sc_nsessions = 1; 871 } else { 872 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { 873 if (sc->sc_sessions[sesn].ses_used == 0) { 874 ses = &sc->sc_sessions[sesn]; 875 break; 876 } 877 } 878 879 if (ses == NULL) { 880 sesn = sc->sc_nsessions; 881 ses = (struct ubsec_session *)malloc((sesn + 1) * 882 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT); 883 if (ses == NULL) 884 return (ENOMEM); 885 bcopy(sc->sc_sessions, ses, sesn * 886 sizeof(struct ubsec_session)); 887 bzero(sc->sc_sessions, sesn * 888 sizeof(struct ubsec_session)); 889 free(sc->sc_sessions, M_DEVBUF); 890 sc->sc_sessions = ses; 891 ses = &sc->sc_sessions[sesn]; 892 sc->sc_nsessions++; 893 } 894 } 895 bzero(ses, sizeof(struct ubsec_session)); 896 ses->ses_used = 1; 897 898 if (encini) { 899 /* get an IV, network byte order */ 900 /* XXX may read fewer than requested */ 901 read_random(ses->ses_iv, sizeof(ses->ses_iv)); 902 903 /* Go ahead and compute key in ubsec's byte order */ 904 if (encini->cri_alg == CRYPTO_DES_CBC) { 905 bcopy(encini->cri_key, &ses->ses_deskey[0], 8); 906 bcopy(encini->cri_key, &ses->ses_deskey[2], 8); 907 bcopy(encini->cri_key, &ses->ses_deskey[4], 8); 908 } else 909 bcopy(encini->cri_key, ses->ses_deskey, 24); 910 911 SWAP32(ses->ses_deskey[0]); 912 SWAP32(ses->ses_deskey[1]); 913 SWAP32(ses->ses_deskey[2]); 914 SWAP32(ses->ses_deskey[3]); 915 SWAP32(ses->ses_deskey[4]); 916 SWAP32(ses->ses_deskey[5]); 917 } 918 919 if (macini) { 920 for (i = 0; i < macini->cri_klen / 8; i++) 921 macini->cri_key[i] ^= HMAC_IPAD_VAL; 922 923 if (macini->cri_alg == CRYPTO_MD5_HMAC) { 924 MD5Init(&md5ctx); 925 MD5Update(&md5ctx, macini->cri_key, 926 macini->cri_klen / 8); 927 MD5Update(&md5ctx, hmac_ipad_buffer, 928 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 929 bcopy(md5ctx.state, ses->ses_hminner, 930 sizeof(md5ctx.state)); 931 } else { 932 SHA1Init(&sha1ctx); 933 SHA1Update(&sha1ctx, macini->cri_key, 934 macini->cri_klen / 8); 935 SHA1Update(&sha1ctx, hmac_ipad_buffer, 936 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 937 bcopy(sha1ctx.h.b32, ses->ses_hminner, 938 sizeof(sha1ctx.h.b32)); 939 } 940 941 for (i = 0; i < macini->cri_klen / 8; i++) 942 macini->cri_key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); 943 944 if (macini->cri_alg == CRYPTO_MD5_HMAC) { 945 MD5Init(&md5ctx); 946 MD5Update(&md5ctx, macini->cri_key, 947 macini->cri_klen / 8); 948 MD5Update(&md5ctx, hmac_opad_buffer, 949 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 950 bcopy(md5ctx.state, ses->ses_hmouter, 951 sizeof(md5ctx.state)); 952 } else { 953 SHA1Init(&sha1ctx); 954 SHA1Update(&sha1ctx, macini->cri_key, 955 macini->cri_klen / 8); 956 SHA1Update(&sha1ctx, hmac_opad_buffer, 957 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 958 bcopy(sha1ctx.h.b32, ses->ses_hmouter, 959 sizeof(sha1ctx.h.b32)); 960 } 961 962 for (i = 0; i < macini->cri_klen / 8; i++) 963 macini->cri_key[i] ^= HMAC_OPAD_VAL; 964 } 965 966 *sidp = UBSEC_SID(device_get_unit(sc->sc_dev), sesn); 967 return (0); 968} 969 970/* 971 * Deallocate a session. 972 */ 973static int 974ubsec_freesession(void *arg, u_int64_t tid) 975{ 976 struct ubsec_softc *sc = arg; 977 int session, ret; 978 u_int32_t sid = CRYPTO_SESID2LID(tid); 979 980 if (sc == NULL) 981 return (EINVAL); 982 983 session = UBSEC_SESSION(sid); 984 if (session < sc->sc_nsessions) { 985 bzero(&sc->sc_sessions[session], 986 sizeof(sc->sc_sessions[session])); 987 ret = 0; 988 } else 989 ret = EINVAL; 990 991 return (ret); 992} 993 994static void 995ubsec_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error) 996{ 997 struct ubsec_operand *op = arg; 998 999 KASSERT(nsegs <= UBS_MAX_SCATTER, 1000 ("Too many DMA segments returned when mapping operand")); 1001#ifdef UBSEC_DEBUG 1002 if (ubsec_debug) 1003 printf("ubsec_op_cb: mapsize %u nsegs %d\n", 1004 (u_int) mapsize, nsegs); 1005#endif 1006 op->mapsize = mapsize; 1007 op->nsegs = nsegs; 1008 bcopy(seg, op->segs, nsegs * sizeof (seg[0])); 1009} 1010 1011static int 1012ubsec_process(void *arg, struct cryptop *crp, int hint) 1013{ 1014 struct ubsec_q *q = NULL; 1015 int err = 0, i, j, nicealign; 1016 struct ubsec_softc *sc = arg; 1017 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 1018 int encoffset = 0, macoffset = 0, cpskip, cpoffset; 1019 int sskip, dskip, stheend, dtheend; 1020 int16_t coffset; 1021 struct ubsec_session *ses; 1022 struct ubsec_pktctx ctx; 1023 struct ubsec_dma *dmap = NULL; 1024 1025 if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { 1026 ubsecstats.hst_invalid++; 1027 return (EINVAL); 1028 } 1029 if (UBSEC_SESSION(crp->crp_sid) >= sc->sc_nsessions) { 1030 ubsecstats.hst_badsession++; 1031 return (EINVAL); 1032 } 1033 1034 mtx_lock(&sc->sc_freeqlock); 1035 if (SIMPLEQ_EMPTY(&sc->sc_freequeue)) { 1036 ubsecstats.hst_queuefull++; 1037 sc->sc_needwakeup |= CRYPTO_SYMQ; 1038 mtx_unlock(&sc->sc_freeqlock); 1039 return (ERESTART); 1040 } 1041 q = SIMPLEQ_FIRST(&sc->sc_freequeue); 1042 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q, q_next); 1043 mtx_unlock(&sc->sc_freeqlock); 1044 1045 dmap = q->q_dma; /* Save dma pointer */ 1046 bzero(q, sizeof(struct ubsec_q)); 1047 bzero(&ctx, sizeof(ctx)); 1048 1049 q->q_sesn = UBSEC_SESSION(crp->crp_sid); 1050 q->q_dma = dmap; 1051 ses = &sc->sc_sessions[q->q_sesn]; 1052 1053 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1054 q->q_src_m = (struct mbuf *)crp->crp_buf; 1055 q->q_dst_m = (struct mbuf *)crp->crp_buf; 1056 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1057 q->q_src_io = (struct uio *)crp->crp_buf; 1058 q->q_dst_io = (struct uio *)crp->crp_buf; 1059 } else { 1060 ubsecstats.hst_badflags++; 1061 err = EINVAL; 1062 goto errout; /* XXX we don't handle contiguous blocks! */ 1063 } 1064 1065 bzero(&dmap->d_dma->d_mcr, sizeof(struct ubsec_mcr)); 1066 1067 dmap->d_dma->d_mcr.mcr_pkts = htole16(1); 1068 dmap->d_dma->d_mcr.mcr_flags = 0; 1069 q->q_crp = crp; 1070 1071 crd1 = crp->crp_desc; 1072 if (crd1 == NULL) { 1073 ubsecstats.hst_nodesc++; 1074 err = EINVAL; 1075 goto errout; 1076 } 1077 crd2 = crd1->crd_next; 1078 1079 if (crd2 == NULL) { 1080 if (crd1->crd_alg == CRYPTO_MD5_HMAC || 1081 crd1->crd_alg == CRYPTO_SHA1_HMAC) { 1082 maccrd = crd1; 1083 enccrd = NULL; 1084 } else if (crd1->crd_alg == CRYPTO_DES_CBC || 1085 crd1->crd_alg == CRYPTO_3DES_CBC) { 1086 maccrd = NULL; 1087 enccrd = crd1; 1088 } else { 1089 ubsecstats.hst_badalg++; 1090 err = EINVAL; 1091 goto errout; 1092 } 1093 } else { 1094 if ((crd1->crd_alg == CRYPTO_MD5_HMAC || 1095 crd1->crd_alg == CRYPTO_SHA1_HMAC) && 1096 (crd2->crd_alg == CRYPTO_DES_CBC || 1097 crd2->crd_alg == CRYPTO_3DES_CBC) && 1098 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 1099 maccrd = crd1; 1100 enccrd = crd2; 1101 } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 1102 crd1->crd_alg == CRYPTO_3DES_CBC) && 1103 (crd2->crd_alg == CRYPTO_MD5_HMAC || 1104 crd2->crd_alg == CRYPTO_SHA1_HMAC) && 1105 (crd1->crd_flags & CRD_F_ENCRYPT)) { 1106 enccrd = crd1; 1107 maccrd = crd2; 1108 } else { 1109 /* 1110 * We cannot order the ubsec as requested 1111 */ 1112 ubsecstats.hst_badalg++; 1113 err = EINVAL; 1114 goto errout; 1115 } 1116 } 1117 1118 if (enccrd) { 1119 encoffset = enccrd->crd_skip; 1120 ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_3DES); 1121 1122 if (enccrd->crd_flags & CRD_F_ENCRYPT) { 1123 q->q_flags |= UBSEC_QFLAGS_COPYOUTIV; 1124 1125 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1126 bcopy(enccrd->crd_iv, ctx.pc_iv, 8); 1127 else { 1128 ctx.pc_iv[0] = ses->ses_iv[0]; 1129 ctx.pc_iv[1] = ses->ses_iv[1]; 1130 } 1131 1132 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { 1133 if (crp->crp_flags & CRYPTO_F_IMBUF) 1134 m_copyback(q->q_src_m, 1135 enccrd->crd_inject, 1136 8, (caddr_t)ctx.pc_iv); 1137 else if (crp->crp_flags & CRYPTO_F_IOV) 1138 cuio_copyback(q->q_src_io, 1139 enccrd->crd_inject, 1140 8, (caddr_t)ctx.pc_iv); 1141 } 1142 } else { 1143 ctx.pc_flags |= htole16(UBS_PKTCTX_INBOUND); 1144 1145 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1146 bcopy(enccrd->crd_iv, ctx.pc_iv, 8); 1147 else if (crp->crp_flags & CRYPTO_F_IMBUF) 1148 m_copydata(q->q_src_m, enccrd->crd_inject, 1149 8, (caddr_t)ctx.pc_iv); 1150 else if (crp->crp_flags & CRYPTO_F_IOV) 1151 cuio_copydata(q->q_src_io, 1152 enccrd->crd_inject, 8, 1153 (caddr_t)ctx.pc_iv); 1154 } 1155 1156 ctx.pc_deskey[0] = ses->ses_deskey[0]; 1157 ctx.pc_deskey[1] = ses->ses_deskey[1]; 1158 ctx.pc_deskey[2] = ses->ses_deskey[2]; 1159 ctx.pc_deskey[3] = ses->ses_deskey[3]; 1160 ctx.pc_deskey[4] = ses->ses_deskey[4]; 1161 ctx.pc_deskey[5] = ses->ses_deskey[5]; 1162 SWAP32(ctx.pc_iv[0]); 1163 SWAP32(ctx.pc_iv[1]); 1164 } 1165 1166 if (maccrd) { 1167 macoffset = maccrd->crd_skip; 1168 1169 if (maccrd->crd_alg == CRYPTO_MD5_HMAC) 1170 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_MD5); 1171 else 1172 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_SHA1); 1173 1174 for (i = 0; i < 5; i++) { 1175 ctx.pc_hminner[i] = ses->ses_hminner[i]; 1176 ctx.pc_hmouter[i] = ses->ses_hmouter[i]; 1177 1178 HTOLE32(ctx.pc_hminner[i]); 1179 HTOLE32(ctx.pc_hmouter[i]); 1180 } 1181 } 1182 1183 if (enccrd && maccrd) { 1184 /* 1185 * ubsec cannot handle packets where the end of encryption 1186 * and authentication are not the same, or where the 1187 * encrypted part begins before the authenticated part. 1188 */ 1189 if ((encoffset + enccrd->crd_len) != 1190 (macoffset + maccrd->crd_len)) { 1191 ubsecstats.hst_lenmismatch++; 1192 err = EINVAL; 1193 goto errout; 1194 } 1195 if (enccrd->crd_skip < maccrd->crd_skip) { 1196 ubsecstats.hst_skipmismatch++; 1197 err = EINVAL; 1198 goto errout; 1199 } 1200 sskip = maccrd->crd_skip; 1201 cpskip = dskip = enccrd->crd_skip; 1202 stheend = maccrd->crd_len; 1203 dtheend = enccrd->crd_len; 1204 coffset = enccrd->crd_skip - maccrd->crd_skip; 1205 cpoffset = cpskip + dtheend; 1206#ifdef UBSEC_DEBUG 1207 if (ubsec_debug) { 1208 printf("mac: skip %d, len %d, inject %d\n", 1209 maccrd->crd_skip, maccrd->crd_len, maccrd->crd_inject); 1210 printf("enc: skip %d, len %d, inject %d\n", 1211 enccrd->crd_skip, enccrd->crd_len, enccrd->crd_inject); 1212 printf("src: skip %d, len %d\n", sskip, stheend); 1213 printf("dst: skip %d, len %d\n", dskip, dtheend); 1214 printf("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n", 1215 coffset, stheend, cpskip, cpoffset); 1216 } 1217#endif 1218 } else { 1219 cpskip = dskip = sskip = macoffset + encoffset; 1220 dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len; 1221 cpoffset = cpskip + dtheend; 1222 coffset = 0; 1223 } 1224 ctx.pc_offset = htole16(coffset >> 2); 1225 1226 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &q->q_src_map)) { 1227 ubsecstats.hst_nomap++; 1228 err = ENOMEM; 1229 goto errout; 1230 } 1231 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1232 if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map, 1233 q->q_src_m, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) { 1234 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1235 q->q_src_map = NULL; 1236 ubsecstats.hst_noload++; 1237 err = ENOMEM; 1238 goto errout; 1239 } 1240 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1241 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map, 1242 q->q_src_io, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) { 1243 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1244 q->q_src_map = NULL; 1245 ubsecstats.hst_noload++; 1246 err = ENOMEM; 1247 goto errout; 1248 } 1249 } 1250 nicealign = ubsec_dmamap_aligned(&q->q_src); 1251 1252 dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend); 1253 1254#ifdef UBSEC_DEBUG 1255 if (ubsec_debug) 1256 printf("src skip: %d nicealign: %u\n", sskip, nicealign); 1257#endif 1258 for (i = j = 0; i < q->q_src_nsegs; i++) { 1259 struct ubsec_pktbuf *pb; 1260 bus_size_t packl = q->q_src_segs[i].ds_len; 1261 bus_addr_t packp = q->q_src_segs[i].ds_addr; 1262 1263 if (sskip >= packl) { 1264 sskip -= packl; 1265 continue; 1266 } 1267 1268 packl -= sskip; 1269 packp += sskip; 1270 sskip = 0; 1271 1272 if (packl > 0xfffc) { 1273 err = EIO; 1274 goto errout; 1275 } 1276 1277 if (j == 0) 1278 pb = &dmap->d_dma->d_mcr.mcr_ipktbuf; 1279 else 1280 pb = &dmap->d_dma->d_sbuf[j - 1]; 1281 1282 pb->pb_addr = htole32(packp); 1283 1284 if (stheend) { 1285 if (packl > stheend) { 1286 pb->pb_len = htole32(stheend); 1287 stheend = 0; 1288 } else { 1289 pb->pb_len = htole32(packl); 1290 stheend -= packl; 1291 } 1292 } else 1293 pb->pb_len = htole32(packl); 1294 1295 if ((i + 1) == q->q_src_nsegs) 1296 pb->pb_next = 0; 1297 else 1298 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1299 offsetof(struct ubsec_dmachunk, d_sbuf[j])); 1300 j++; 1301 } 1302 1303 if (enccrd == NULL && maccrd != NULL) { 1304 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0; 1305 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0; 1306 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next = htole32(dmap->d_alloc.dma_paddr + 1307 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1308#ifdef UBSEC_DEBUG 1309 if (ubsec_debug) 1310 printf("opkt: %x %x %x\n", 1311 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr, 1312 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len, 1313 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next); 1314#endif 1315 } else { 1316 if (crp->crp_flags & CRYPTO_F_IOV) { 1317 if (!nicealign) { 1318 ubsecstats.hst_iovmisaligned++; 1319 err = EINVAL; 1320 goto errout; 1321 } 1322 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 1323 &q->q_dst_map)) { 1324 ubsecstats.hst_nomap++; 1325 err = ENOMEM; 1326 goto errout; 1327 } 1328 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map, 1329 q->q_dst_io, ubsec_op_cb, &q->q_dst, BUS_DMA_NOWAIT) != 0) { 1330 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1331 q->q_dst_map = NULL; 1332 ubsecstats.hst_noload++; 1333 err = ENOMEM; 1334 goto errout; 1335 } 1336 } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1337 if (nicealign) { 1338 q->q_dst = q->q_src; 1339 } else { 1340 int totlen, len; 1341 struct mbuf *m, *top, **mp; 1342 1343 ubsecstats.hst_unaligned++; 1344 totlen = q->q_src_mapsize; 1345 if (q->q_src_m->m_flags & M_PKTHDR) { 1346 len = MHLEN; 1347 MGETHDR(m, M_DONTWAIT, MT_DATA); 1348 if (m && !m_dup_pkthdr(m, q->q_src_m, M_DONTWAIT)) { 1349 m_free(m); 1350 m = NULL; 1351 } 1352 } else { 1353 len = MLEN; 1354 MGET(m, M_DONTWAIT, MT_DATA); 1355 } 1356 if (m == NULL) { 1357 ubsecstats.hst_nombuf++; 1358 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1359 goto errout; 1360 } 1361 if (totlen >= MINCLSIZE) { 1362 MCLGET(m, M_DONTWAIT); 1363 if ((m->m_flags & M_EXT) == 0) { 1364 m_free(m); 1365 ubsecstats.hst_nomcl++; 1366 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1367 goto errout; 1368 } 1369 len = MCLBYTES; 1370 } 1371 m->m_len = len; 1372 top = NULL; 1373 mp = ⊤ 1374 1375 while (totlen > 0) { 1376 if (top) { 1377 MGET(m, M_DONTWAIT, MT_DATA); 1378 if (m == NULL) { 1379 m_freem(top); 1380 ubsecstats.hst_nombuf++; 1381 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1382 goto errout; 1383 } 1384 len = MLEN; 1385 } 1386 if (top && totlen >= MINCLSIZE) { 1387 MCLGET(m, M_DONTWAIT); 1388 if ((m->m_flags & M_EXT) == 0) { 1389 *mp = m; 1390 m_freem(top); 1391 ubsecstats.hst_nomcl++; 1392 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1393 goto errout; 1394 } 1395 len = MCLBYTES; 1396 } 1397 m->m_len = len = min(totlen, len); 1398 totlen -= len; 1399 *mp = m; 1400 mp = &m->m_next; 1401 } 1402 q->q_dst_m = top; 1403 ubsec_mcopy(q->q_src_m, q->q_dst_m, 1404 cpskip, cpoffset); 1405 if (bus_dmamap_create(sc->sc_dmat, 1406 BUS_DMA_NOWAIT, &q->q_dst_map) != 0) { 1407 ubsecstats.hst_nomap++; 1408 err = ENOMEM; 1409 goto errout; 1410 } 1411 if (bus_dmamap_load_mbuf(sc->sc_dmat, 1412 q->q_dst_map, q->q_dst_m, 1413 ubsec_op_cb, &q->q_dst, 1414 BUS_DMA_NOWAIT) != 0) { 1415 bus_dmamap_destroy(sc->sc_dmat, 1416 q->q_dst_map); 1417 q->q_dst_map = NULL; 1418 ubsecstats.hst_noload++; 1419 err = ENOMEM; 1420 goto errout; 1421 } 1422 } 1423 } else { 1424 ubsecstats.hst_badflags++; 1425 err = EINVAL; 1426 goto errout; 1427 } 1428 1429#ifdef UBSEC_DEBUG 1430 if (ubsec_debug) 1431 printf("dst skip: %d\n", dskip); 1432#endif 1433 for (i = j = 0; i < q->q_dst_nsegs; i++) { 1434 struct ubsec_pktbuf *pb; 1435 bus_size_t packl = q->q_dst_segs[i].ds_len; 1436 bus_addr_t packp = q->q_dst_segs[i].ds_addr; 1437 1438 if (dskip >= packl) { 1439 dskip -= packl; 1440 continue; 1441 } 1442 1443 packl -= dskip; 1444 packp += dskip; 1445 dskip = 0; 1446 1447 if (packl > 0xfffc) { 1448 err = EIO; 1449 goto errout; 1450 } 1451 1452 if (j == 0) 1453 pb = &dmap->d_dma->d_mcr.mcr_opktbuf; 1454 else 1455 pb = &dmap->d_dma->d_dbuf[j - 1]; 1456 1457 pb->pb_addr = htole32(packp); 1458 1459 if (dtheend) { 1460 if (packl > dtheend) { 1461 pb->pb_len = htole32(dtheend); 1462 dtheend = 0; 1463 } else { 1464 pb->pb_len = htole32(packl); 1465 dtheend -= packl; 1466 } 1467 } else 1468 pb->pb_len = htole32(packl); 1469 1470 if ((i + 1) == q->q_dst_nsegs) { 1471 if (maccrd) 1472 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1473 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1474 else 1475 pb->pb_next = 0; 1476 } else 1477 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1478 offsetof(struct ubsec_dmachunk, d_dbuf[j])); 1479 j++; 1480 } 1481 } 1482 1483 dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr + 1484 offsetof(struct ubsec_dmachunk, d_ctx)); 1485 1486 if (sc->sc_flags & UBS_FLAGS_LONGCTX) { 1487 struct ubsec_pktctx_long *ctxl; 1488 1489 ctxl = (struct ubsec_pktctx_long *)(dmap->d_alloc.dma_vaddr + 1490 offsetof(struct ubsec_dmachunk, d_ctx)); 1491 1492 /* transform small context into long context */ 1493 ctxl->pc_len = htole16(sizeof(struct ubsec_pktctx_long)); 1494 ctxl->pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC); 1495 ctxl->pc_flags = ctx.pc_flags; 1496 ctxl->pc_offset = ctx.pc_offset; 1497 for (i = 0; i < 6; i++) 1498 ctxl->pc_deskey[i] = ctx.pc_deskey[i]; 1499 for (i = 0; i < 5; i++) 1500 ctxl->pc_hminner[i] = ctx.pc_hminner[i]; 1501 for (i = 0; i < 5; i++) 1502 ctxl->pc_hmouter[i] = ctx.pc_hmouter[i]; 1503 ctxl->pc_iv[0] = ctx.pc_iv[0]; 1504 ctxl->pc_iv[1] = ctx.pc_iv[1]; 1505 } else 1506 bcopy(&ctx, dmap->d_alloc.dma_vaddr + 1507 offsetof(struct ubsec_dmachunk, d_ctx), 1508 sizeof(struct ubsec_pktctx)); 1509 1510 mtx_lock(&sc->sc_mcr1lock); 1511 SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next); 1512 sc->sc_nqueue++; 1513 ubsecstats.hst_ipackets++; 1514 ubsecstats.hst_ibytes += dmap->d_alloc.dma_size; 1515 if ((hint & CRYPTO_HINT_MORE) == 0 || sc->sc_nqueue >= UBS_MAX_AGGR) 1516 ubsec_feed(sc); 1517 mtx_unlock(&sc->sc_mcr1lock); 1518 return (0); 1519 1520errout: 1521 if (q != NULL) { 1522 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 1523 m_freem(q->q_dst_m); 1524 1525 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1526 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1527 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1528 } 1529 if (q->q_src_map != NULL) { 1530 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1531 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1532 } 1533 1534 mtx_lock(&sc->sc_freeqlock); 1535 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1536 mtx_unlock(&sc->sc_freeqlock); 1537 } 1538 if (err != ERESTART) { 1539 crp->crp_etype = err; 1540 crypto_done(crp); 1541 } else { 1542 sc->sc_needwakeup |= CRYPTO_SYMQ; 1543 } 1544 return (err); 1545} 1546 1547static void 1548ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q) 1549{ 1550 struct cryptop *crp = (struct cryptop *)q->q_crp; 1551 struct cryptodesc *crd; 1552 struct ubsec_dma *dmap = q->q_dma; 1553 1554 ubsecstats.hst_opackets++; 1555 ubsecstats.hst_obytes += dmap->d_alloc.dma_size; 1556 1557 ubsec_dma_sync(&dmap->d_alloc, 1558 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1559 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1560 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, 1561 BUS_DMASYNC_POSTREAD); 1562 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1563 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1564 } 1565 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_POSTWRITE); 1566 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1567 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1568 1569 if ((crp->crp_flags & CRYPTO_F_IMBUF) && (q->q_src_m != q->q_dst_m)) { 1570 m_freem(q->q_src_m); 1571 crp->crp_buf = (caddr_t)q->q_dst_m; 1572 } 1573 ubsecstats.hst_obytes += ((struct mbuf *)crp->crp_buf)->m_len; 1574 1575 /* copy out IV for future use */ 1576 if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) { 1577 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1578 if (crd->crd_alg != CRYPTO_DES_CBC && 1579 crd->crd_alg != CRYPTO_3DES_CBC) 1580 continue; 1581 if (crp->crp_flags & CRYPTO_F_IMBUF) 1582 m_copydata((struct mbuf *)crp->crp_buf, 1583 crd->crd_skip + crd->crd_len - 8, 8, 1584 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); 1585 else if (crp->crp_flags & CRYPTO_F_IOV) { 1586 cuio_copydata((struct uio *)crp->crp_buf, 1587 crd->crd_skip + crd->crd_len - 8, 8, 1588 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); 1589 } 1590 break; 1591 } 1592 } 1593 1594 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1595 if (crd->crd_alg != CRYPTO_MD5_HMAC && 1596 crd->crd_alg != CRYPTO_SHA1_HMAC) 1597 continue; 1598 if (crp->crp_flags & CRYPTO_F_IMBUF) 1599 m_copyback((struct mbuf *)crp->crp_buf, 1600 crd->crd_inject, 12, 1601 (caddr_t)dmap->d_dma->d_macbuf); 1602 else if (crp->crp_flags & CRYPTO_F_IOV && crp->crp_mac) 1603 bcopy((caddr_t)dmap->d_dma->d_macbuf, 1604 crp->crp_mac, 12); 1605 break; 1606 } 1607 mtx_lock(&sc->sc_freeqlock); 1608 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1609 mtx_unlock(&sc->sc_freeqlock); 1610 crypto_done(crp); 1611} 1612 1613static void 1614ubsec_mcopy(struct mbuf *srcm, struct mbuf *dstm, int hoffset, int toffset) 1615{ 1616 int i, j, dlen, slen; 1617 caddr_t dptr, sptr; 1618 1619 j = 0; 1620 sptr = srcm->m_data; 1621 slen = srcm->m_len; 1622 dptr = dstm->m_data; 1623 dlen = dstm->m_len; 1624 1625 while (1) { 1626 for (i = 0; i < min(slen, dlen); i++) { 1627 if (j < hoffset || j >= toffset) 1628 *dptr++ = *sptr++; 1629 slen--; 1630 dlen--; 1631 j++; 1632 } 1633 if (slen == 0) { 1634 srcm = srcm->m_next; 1635 if (srcm == NULL) 1636 return; 1637 sptr = srcm->m_data; 1638 slen = srcm->m_len; 1639 } 1640 if (dlen == 0) { 1641 dstm = dstm->m_next; 1642 if (dstm == NULL) 1643 return; 1644 dptr = dstm->m_data; 1645 dlen = dstm->m_len; 1646 } 1647 } 1648} 1649 1650/* 1651 * feed the key generator, must be called at splimp() or higher. 1652 */ 1653static int 1654ubsec_feed2(struct ubsec_softc *sc) 1655{ 1656 struct ubsec_q2 *q; 1657 1658 while (!SIMPLEQ_EMPTY(&sc->sc_queue2)) { 1659 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR2_FULL) 1660 break; 1661 q = SIMPLEQ_FIRST(&sc->sc_queue2); 1662 1663 ubsec_dma_sync(&q->q_mcr, 1664 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1665 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_PREWRITE); 1666 1667 WRITE_REG(sc, BS_MCR2, q->q_mcr.dma_paddr); 1668 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue2, q, q_next); 1669 --sc->sc_nqueue2; 1670 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip2, q, q_next); 1671 } 1672 return (0); 1673} 1674 1675/* 1676 * Callback for handling random numbers 1677 */ 1678static void 1679ubsec_callback2(struct ubsec_softc *sc, struct ubsec_q2 *q) 1680{ 1681 struct cryptkop *krp; 1682 struct ubsec_ctx_keyop *ctx; 1683 1684 ctx = (struct ubsec_ctx_keyop *)q->q_ctx.dma_vaddr; 1685 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_POSTWRITE); 1686 1687 switch (q->q_type) { 1688#ifndef UBSEC_NO_RNG 1689 case UBS_CTXOP_RNGBYPASS: { 1690 struct ubsec_q2_rng *rng = (struct ubsec_q2_rng *)q; 1691 1692 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_POSTREAD); 1693 (*sc->sc_harvest)(sc->sc_rndtest, 1694 rng->rng_buf.dma_vaddr, 1695 UBSEC_RNG_BUFSIZ*sizeof (u_int32_t)); 1696 rng->rng_used = 0; 1697 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 1698 break; 1699 } 1700#endif 1701 case UBS_CTXOP_MODEXP: { 1702 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 1703 u_int rlen, clen; 1704 1705 krp = me->me_krp; 1706 rlen = (me->me_modbits + 7) / 8; 1707 clen = (krp->krp_param[krp->krp_iparams].crp_nbits + 7) / 8; 1708 1709 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_POSTWRITE); 1710 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_POSTWRITE); 1711 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_POSTREAD); 1712 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_POSTWRITE); 1713 1714 if (clen < rlen) 1715 krp->krp_status = E2BIG; 1716 else { 1717 if (sc->sc_flags & UBS_FLAGS_HWNORM) { 1718 bzero(krp->krp_param[krp->krp_iparams].crp_p, 1719 (krp->krp_param[krp->krp_iparams].crp_nbits 1720 + 7) / 8); 1721 bcopy(me->me_C.dma_vaddr, 1722 krp->krp_param[krp->krp_iparams].crp_p, 1723 (me->me_modbits + 7) / 8); 1724 } else 1725 ubsec_kshift_l(me->me_shiftbits, 1726 me->me_C.dma_vaddr, me->me_normbits, 1727 krp->krp_param[krp->krp_iparams].crp_p, 1728 krp->krp_param[krp->krp_iparams].crp_nbits); 1729 } 1730 1731 crypto_kdone(krp); 1732 1733 /* bzero all potentially sensitive data */ 1734 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 1735 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 1736 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 1737 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 1738 1739 /* Can't free here, so put us on the free list. */ 1740 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &me->me_q, q_next); 1741 break; 1742 } 1743 case UBS_CTXOP_RSAPRIV: { 1744 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 1745 u_int len; 1746 1747 krp = rp->rpr_krp; 1748 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_POSTWRITE); 1749 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_POSTREAD); 1750 1751 len = (krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_nbits + 7) / 8; 1752 bcopy(rp->rpr_msgout.dma_vaddr, 1753 krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_p, len); 1754 1755 crypto_kdone(krp); 1756 1757 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size); 1758 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size); 1759 bzero(rp->rpr_q.q_ctx.dma_vaddr, rp->rpr_q.q_ctx.dma_size); 1760 1761 /* Can't free here, so put us on the free list. */ 1762 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &rp->rpr_q, q_next); 1763 break; 1764 } 1765 default: 1766 device_printf(sc->sc_dev, "unknown ctx op: %x\n", 1767 letoh16(ctx->ctx_op)); 1768 break; 1769 } 1770} 1771 1772#ifndef UBSEC_NO_RNG 1773static void 1774ubsec_rng(void *vsc) 1775{ 1776 struct ubsec_softc *sc = vsc; 1777 struct ubsec_q2_rng *rng = &sc->sc_rng; 1778 struct ubsec_mcr *mcr; 1779 struct ubsec_ctx_rngbypass *ctx; 1780 1781 mtx_lock(&sc->sc_mcr2lock); 1782 if (rng->rng_used) { 1783 mtx_unlock(&sc->sc_mcr2lock); 1784 return; 1785 } 1786 sc->sc_nqueue2++; 1787 if (sc->sc_nqueue2 >= UBS_MAX_NQUEUE) 1788 goto out; 1789 1790 mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr; 1791 ctx = (struct ubsec_ctx_rngbypass *)rng->rng_q.q_ctx.dma_vaddr; 1792 1793 mcr->mcr_pkts = htole16(1); 1794 mcr->mcr_flags = 0; 1795 mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr); 1796 mcr->mcr_ipktbuf.pb_addr = mcr->mcr_ipktbuf.pb_next = 0; 1797 mcr->mcr_ipktbuf.pb_len = 0; 1798 mcr->mcr_reserved = mcr->mcr_pktlen = 0; 1799 mcr->mcr_opktbuf.pb_addr = htole32(rng->rng_buf.dma_paddr); 1800 mcr->mcr_opktbuf.pb_len = htole32(((sizeof(u_int32_t) * UBSEC_RNG_BUFSIZ)) & 1801 UBS_PKTBUF_LEN); 1802 mcr->mcr_opktbuf.pb_next = 0; 1803 1804 ctx->rbp_len = htole16(sizeof(struct ubsec_ctx_rngbypass)); 1805 ctx->rbp_op = htole16(UBS_CTXOP_RNGBYPASS); 1806 rng->rng_q.q_type = UBS_CTXOP_RNGBYPASS; 1807 1808 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_PREREAD); 1809 1810 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rng->rng_q, q_next); 1811 rng->rng_used = 1; 1812 ubsec_feed2(sc); 1813 ubsecstats.hst_rng++; 1814 mtx_unlock(&sc->sc_mcr2lock); 1815 1816 return; 1817 1818out: 1819 /* 1820 * Something weird happened, generate our own call back. 1821 */ 1822 sc->sc_nqueue2--; 1823 mtx_unlock(&sc->sc_mcr2lock); 1824 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 1825} 1826#endif /* UBSEC_NO_RNG */ 1827 1828static void 1829ubsec_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1830{ 1831 bus_addr_t *paddr = (bus_addr_t*) arg; 1832 *paddr = segs->ds_addr; 1833} 1834 1835static int 1836ubsec_dma_malloc( 1837 struct ubsec_softc *sc, 1838 bus_size_t size, 1839 struct ubsec_dma_alloc *dma, 1840 int mapflags 1841) 1842{ 1843 int r; 1844 1845 /* XXX could specify sc_dmat as parent but that just adds overhead */ 1846 r = bus_dma_tag_create(NULL, /* parent */ 1847 1, 0, /* alignment, bounds */ 1848 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1849 BUS_SPACE_MAXADDR, /* highaddr */ 1850 NULL, NULL, /* filter, filterarg */ 1851 size, /* maxsize */ 1852 1, /* nsegments */ 1853 size, /* maxsegsize */ 1854 BUS_DMA_ALLOCNOW, /* flags */ 1855 NULL, NULL, /* lockfunc, lockarg */ 1856 &dma->dma_tag); 1857 if (r != 0) { 1858 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1859 "bus_dma_tag_create failed; error %u\n", r); 1860 goto fail_0; 1861 } 1862 1863 r = bus_dmamap_create(dma->dma_tag, BUS_DMA_NOWAIT, &dma->dma_map); 1864 if (r != 0) { 1865 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1866 "bus_dmamap_create failed; error %u\n", r); 1867 goto fail_1; 1868 } 1869 1870 r = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr, 1871 BUS_DMA_NOWAIT, &dma->dma_map); 1872 if (r != 0) { 1873 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1874 "bus_dmammem_alloc failed; size %zu, error %u\n", 1875 size, r); 1876 goto fail_2; 1877 } 1878 1879 r = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, 1880 size, 1881 ubsec_dmamap_cb, 1882 &dma->dma_paddr, 1883 mapflags | BUS_DMA_NOWAIT); 1884 if (r != 0) { 1885 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1886 "bus_dmamap_load failed; error %u\n", r); 1887 goto fail_3; 1888 } 1889 1890 dma->dma_size = size; 1891 return (0); 1892 1893fail_3: 1894 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1895fail_2: 1896 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1897fail_1: 1898 bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1899 bus_dma_tag_destroy(dma->dma_tag); 1900fail_0: 1901 dma->dma_map = NULL; 1902 dma->dma_tag = NULL; 1903 return (r); 1904} 1905 1906static void 1907ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma) 1908{ 1909 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1910 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1911 bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1912 bus_dma_tag_destroy(dma->dma_tag); 1913} 1914 1915/* 1916 * Resets the board. Values in the regesters are left as is 1917 * from the reset (i.e. initial values are assigned elsewhere). 1918 */ 1919static void 1920ubsec_reset_board(struct ubsec_softc *sc) 1921{ 1922 volatile u_int32_t ctrl; 1923 1924 ctrl = READ_REG(sc, BS_CTRL); 1925 ctrl |= BS_CTRL_RESET; 1926 WRITE_REG(sc, BS_CTRL, ctrl); 1927 1928 /* 1929 * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us 1930 */ 1931 DELAY(10); 1932} 1933 1934/* 1935 * Init Broadcom registers 1936 */ 1937static void 1938ubsec_init_board(struct ubsec_softc *sc) 1939{ 1940 u_int32_t ctrl; 1941 1942 ctrl = READ_REG(sc, BS_CTRL); 1943 ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64); 1944 ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT; 1945 1946 if (sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) 1947 ctrl |= BS_CTRL_MCR2INT; 1948 else 1949 ctrl &= ~BS_CTRL_MCR2INT; 1950 1951 if (sc->sc_flags & UBS_FLAGS_HWNORM) 1952 ctrl &= ~BS_CTRL_SWNORM; 1953 1954 WRITE_REG(sc, BS_CTRL, ctrl); 1955} 1956 1957/* 1958 * Init Broadcom PCI registers 1959 */ 1960static void 1961ubsec_init_pciregs(device_t dev) 1962{ 1963#if 0 1964 u_int32_t misc; 1965 1966 misc = pci_conf_read(pc, pa->pa_tag, BS_RTY_TOUT); 1967 misc = (misc & ~(UBS_PCI_RTY_MASK << UBS_PCI_RTY_SHIFT)) 1968 | ((UBS_DEF_RTY & 0xff) << UBS_PCI_RTY_SHIFT); 1969 misc = (misc & ~(UBS_PCI_TOUT_MASK << UBS_PCI_TOUT_SHIFT)) 1970 | ((UBS_DEF_TOUT & 0xff) << UBS_PCI_TOUT_SHIFT); 1971 pci_conf_write(pc, pa->pa_tag, BS_RTY_TOUT, misc); 1972#endif 1973 1974 /* 1975 * This will set the cache line size to 1, this will 1976 * force the BCM58xx chip just to do burst read/writes. 1977 * Cache line read/writes are to slow 1978 */ 1979 pci_write_config(dev, PCIR_CACHELNSZ, UBS_DEF_CACHELINE, 1); 1980} 1981 1982/* 1983 * Clean up after a chip crash. 1984 * It is assumed that the caller in splimp() 1985 */ 1986static void 1987ubsec_cleanchip(struct ubsec_softc *sc) 1988{ 1989 struct ubsec_q *q; 1990 1991 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 1992 q = SIMPLEQ_FIRST(&sc->sc_qchip); 1993 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q, q_next); 1994 ubsec_free_q(sc, q); 1995 } 1996 sc->sc_nqchip = 0; 1997} 1998 1999/* 2000 * free a ubsec_q 2001 * It is assumed that the caller is within splimp(). 2002 */ 2003static int 2004ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q) 2005{ 2006 struct ubsec_q *q2; 2007 struct cryptop *crp; 2008 int npkts; 2009 int i; 2010 2011 npkts = q->q_nstacked_mcrs; 2012 2013 for (i = 0; i < npkts; i++) { 2014 if(q->q_stacked_mcr[i]) { 2015 q2 = q->q_stacked_mcr[i]; 2016 2017 if ((q2->q_dst_m != NULL) && (q2->q_src_m != q2->q_dst_m)) 2018 m_freem(q2->q_dst_m); 2019 2020 crp = (struct cryptop *)q2->q_crp; 2021 2022 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next); 2023 2024 crp->crp_etype = EFAULT; 2025 crypto_done(crp); 2026 } else { 2027 break; 2028 } 2029 } 2030 2031 /* 2032 * Free header MCR 2033 */ 2034 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 2035 m_freem(q->q_dst_m); 2036 2037 crp = (struct cryptop *)q->q_crp; 2038 2039 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 2040 2041 crp->crp_etype = EFAULT; 2042 crypto_done(crp); 2043 return(0); 2044} 2045 2046/* 2047 * Routine to reset the chip and clean up. 2048 * It is assumed that the caller is in splimp() 2049 */ 2050static void 2051ubsec_totalreset(struct ubsec_softc *sc) 2052{ 2053 ubsec_reset_board(sc); 2054 ubsec_init_board(sc); 2055 ubsec_cleanchip(sc); 2056} 2057 2058static int 2059ubsec_dmamap_aligned(struct ubsec_operand *op) 2060{ 2061 int i; 2062 2063 for (i = 0; i < op->nsegs; i++) { 2064 if (op->segs[i].ds_addr & 3) 2065 return (0); 2066 if ((i != (op->nsegs - 1)) && 2067 (op->segs[i].ds_len & 3)) 2068 return (0); 2069 } 2070 return (1); 2071} 2072 2073static void 2074ubsec_kfree(struct ubsec_softc *sc, struct ubsec_q2 *q) 2075{ 2076 switch (q->q_type) { 2077 case UBS_CTXOP_MODEXP: { 2078 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 2079 2080 ubsec_dma_free(sc, &me->me_q.q_mcr); 2081 ubsec_dma_free(sc, &me->me_q.q_ctx); 2082 ubsec_dma_free(sc, &me->me_M); 2083 ubsec_dma_free(sc, &me->me_E); 2084 ubsec_dma_free(sc, &me->me_C); 2085 ubsec_dma_free(sc, &me->me_epb); 2086 free(me, M_DEVBUF); 2087 break; 2088 } 2089 case UBS_CTXOP_RSAPRIV: { 2090 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 2091 2092 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 2093 ubsec_dma_free(sc, &rp->rpr_q.q_ctx); 2094 ubsec_dma_free(sc, &rp->rpr_msgin); 2095 ubsec_dma_free(sc, &rp->rpr_msgout); 2096 free(rp, M_DEVBUF); 2097 break; 2098 } 2099 default: 2100 device_printf(sc->sc_dev, "invalid kfree 0x%x\n", q->q_type); 2101 break; 2102 } 2103} 2104 2105static int 2106ubsec_kprocess(void *arg, struct cryptkop *krp, int hint) 2107{ 2108 struct ubsec_softc *sc = arg; 2109 int r; 2110 2111 if (krp == NULL || krp->krp_callback == NULL) 2112 return (EINVAL); 2113 2114 while (!SIMPLEQ_EMPTY(&sc->sc_q2free)) { 2115 struct ubsec_q2 *q; 2116 2117 q = SIMPLEQ_FIRST(&sc->sc_q2free); 2118 SIMPLEQ_REMOVE_HEAD(&sc->sc_q2free, q, q_next); 2119 ubsec_kfree(sc, q); 2120 } 2121 2122 switch (krp->krp_op) { 2123 case CRK_MOD_EXP: 2124 if (sc->sc_flags & UBS_FLAGS_HWNORM) 2125 r = ubsec_kprocess_modexp_hw(sc, krp, hint); 2126 else 2127 r = ubsec_kprocess_modexp_sw(sc, krp, hint); 2128 break; 2129 case CRK_MOD_EXP_CRT: 2130 return (ubsec_kprocess_rsapriv(sc, krp, hint)); 2131 default: 2132 device_printf(sc->sc_dev, "kprocess: invalid op 0x%x\n", 2133 krp->krp_op); 2134 krp->krp_status = EOPNOTSUPP; 2135 crypto_kdone(krp); 2136 return (0); 2137 } 2138 return (0); /* silence compiler */ 2139} 2140 2141/* 2142 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (sw normalization) 2143 */ 2144static int 2145ubsec_kprocess_modexp_sw(struct ubsec_softc *sc, struct cryptkop *krp, int hint) 2146{ 2147 struct ubsec_q2_modexp *me; 2148 struct ubsec_mcr *mcr; 2149 struct ubsec_ctx_modexp *ctx; 2150 struct ubsec_pktbuf *epb; 2151 int err = 0; 2152 u_int nbits, normbits, mbits, shiftbits, ebits; 2153 2154 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT); 2155 if (me == NULL) { 2156 err = ENOMEM; 2157 goto errout; 2158 } 2159 bzero(me, sizeof *me); 2160 me->me_krp = krp; 2161 me->me_q.q_type = UBS_CTXOP_MODEXP; 2162 2163 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2164 if (nbits <= 512) 2165 normbits = 512; 2166 else if (nbits <= 768) 2167 normbits = 768; 2168 else if (nbits <= 1024) 2169 normbits = 1024; 2170 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2171 normbits = 1536; 2172 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2173 normbits = 2048; 2174 else { 2175 err = E2BIG; 2176 goto errout; 2177 } 2178 2179 shiftbits = normbits - nbits; 2180 2181 me->me_modbits = nbits; 2182 me->me_shiftbits = shiftbits; 2183 me->me_normbits = normbits; 2184 2185 /* Sanity check: result bits must be >= true modulus bits. */ 2186 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2187 err = ERANGE; 2188 goto errout; 2189 } 2190 2191 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2192 &me->me_q.q_mcr, 0)) { 2193 err = ENOMEM; 2194 goto errout; 2195 } 2196 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2197 2198 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2199 &me->me_q.q_ctx, 0)) { 2200 err = ENOMEM; 2201 goto errout; 2202 } 2203 2204 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2205 if (mbits > nbits) { 2206 err = E2BIG; 2207 goto errout; 2208 } 2209 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2210 err = ENOMEM; 2211 goto errout; 2212 } 2213 ubsec_kshift_r(shiftbits, 2214 krp->krp_param[UBS_MODEXP_PAR_M].crp_p, mbits, 2215 me->me_M.dma_vaddr, normbits); 2216 2217 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2218 err = ENOMEM; 2219 goto errout; 2220 } 2221 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2222 2223 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2224 if (ebits > nbits) { 2225 err = E2BIG; 2226 goto errout; 2227 } 2228 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2229 err = ENOMEM; 2230 goto errout; 2231 } 2232 ubsec_kshift_r(shiftbits, 2233 krp->krp_param[UBS_MODEXP_PAR_E].crp_p, ebits, 2234 me->me_E.dma_vaddr, normbits); 2235 2236 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2237 &me->me_epb, 0)) { 2238 err = ENOMEM; 2239 goto errout; 2240 } 2241 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2242 epb->pb_addr = htole32(me->me_E.dma_paddr); 2243 epb->pb_next = 0; 2244 epb->pb_len = htole32(normbits / 8); 2245 2246#ifdef UBSEC_DEBUG 2247 if (ubsec_debug) { 2248 printf("Epb "); 2249 ubsec_dump_pb(epb); 2250 } 2251#endif 2252 2253 mcr->mcr_pkts = htole16(1); 2254 mcr->mcr_flags = 0; 2255 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2256 mcr->mcr_reserved = 0; 2257 mcr->mcr_pktlen = 0; 2258 2259 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2260 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2261 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2262 2263 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2264 mcr->mcr_opktbuf.pb_next = 0; 2265 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2266 2267#ifdef DIAGNOSTIC 2268 /* Misaligned output buffer will hang the chip. */ 2269 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2270 panic("%s: modexp invalid addr 0x%x\n", 2271 device_get_nameunit(sc->sc_dev), 2272 letoh32(mcr->mcr_opktbuf.pb_addr)); 2273 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2274 panic("%s: modexp invalid len 0x%x\n", 2275 device_get_nameunit(sc->sc_dev), 2276 letoh32(mcr->mcr_opktbuf.pb_len)); 2277#endif 2278 2279 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2280 bzero(ctx, sizeof(*ctx)); 2281 ubsec_kshift_r(shiftbits, 2282 krp->krp_param[UBS_MODEXP_PAR_N].crp_p, nbits, 2283 ctx->me_N, normbits); 2284 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2285 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2286 ctx->me_E_len = htole16(nbits); 2287 ctx->me_N_len = htole16(nbits); 2288 2289#ifdef UBSEC_DEBUG 2290 if (ubsec_debug) { 2291 ubsec_dump_mcr(mcr); 2292 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2293 } 2294#endif 2295 2296 /* 2297 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2298 * everything else. 2299 */ 2300 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE); 2301 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE); 2302 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD); 2303 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE); 2304 2305 /* Enqueue and we're done... */ 2306 mtx_lock(&sc->sc_mcr2lock); 2307 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2308 ubsec_feed2(sc); 2309 ubsecstats.hst_modexp++; 2310 mtx_unlock(&sc->sc_mcr2lock); 2311 2312 return (0); 2313 2314errout: 2315 if (me != NULL) { 2316 if (me->me_q.q_mcr.dma_map != NULL) 2317 ubsec_dma_free(sc, &me->me_q.q_mcr); 2318 if (me->me_q.q_ctx.dma_map != NULL) { 2319 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 2320 ubsec_dma_free(sc, &me->me_q.q_ctx); 2321 } 2322 if (me->me_M.dma_map != NULL) { 2323 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 2324 ubsec_dma_free(sc, &me->me_M); 2325 } 2326 if (me->me_E.dma_map != NULL) { 2327 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 2328 ubsec_dma_free(sc, &me->me_E); 2329 } 2330 if (me->me_C.dma_map != NULL) { 2331 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2332 ubsec_dma_free(sc, &me->me_C); 2333 } 2334 if (me->me_epb.dma_map != NULL) 2335 ubsec_dma_free(sc, &me->me_epb); 2336 free(me, M_DEVBUF); 2337 } 2338 krp->krp_status = err; 2339 crypto_kdone(krp); 2340 return (0); 2341} 2342 2343/* 2344 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (hw normalization) 2345 */ 2346static int 2347ubsec_kprocess_modexp_hw(struct ubsec_softc *sc, struct cryptkop *krp, int hint) 2348{ 2349 struct ubsec_q2_modexp *me; 2350 struct ubsec_mcr *mcr; 2351 struct ubsec_ctx_modexp *ctx; 2352 struct ubsec_pktbuf *epb; 2353 int err = 0; 2354 u_int nbits, normbits, mbits, shiftbits, ebits; 2355 2356 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT); 2357 if (me == NULL) { 2358 err = ENOMEM; 2359 goto errout; 2360 } 2361 bzero(me, sizeof *me); 2362 me->me_krp = krp; 2363 me->me_q.q_type = UBS_CTXOP_MODEXP; 2364 2365 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2366 if (nbits <= 512) 2367 normbits = 512; 2368 else if (nbits <= 768) 2369 normbits = 768; 2370 else if (nbits <= 1024) 2371 normbits = 1024; 2372 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2373 normbits = 1536; 2374 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2375 normbits = 2048; 2376 else { 2377 err = E2BIG; 2378 goto errout; 2379 } 2380 2381 shiftbits = normbits - nbits; 2382 2383 /* XXX ??? */ 2384 me->me_modbits = nbits; 2385 me->me_shiftbits = shiftbits; 2386 me->me_normbits = normbits; 2387 2388 /* Sanity check: result bits must be >= true modulus bits. */ 2389 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2390 err = ERANGE; 2391 goto errout; 2392 } 2393 2394 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2395 &me->me_q.q_mcr, 0)) { 2396 err = ENOMEM; 2397 goto errout; 2398 } 2399 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2400 2401 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2402 &me->me_q.q_ctx, 0)) { 2403 err = ENOMEM; 2404 goto errout; 2405 } 2406 2407 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2408 if (mbits > nbits) { 2409 err = E2BIG; 2410 goto errout; 2411 } 2412 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2413 err = ENOMEM; 2414 goto errout; 2415 } 2416 bzero(me->me_M.dma_vaddr, normbits / 8); 2417 bcopy(krp->krp_param[UBS_MODEXP_PAR_M].crp_p, 2418 me->me_M.dma_vaddr, (mbits + 7) / 8); 2419 2420 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2421 err = ENOMEM; 2422 goto errout; 2423 } 2424 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2425 2426 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2427 if (ebits > nbits) { 2428 err = E2BIG; 2429 goto errout; 2430 } 2431 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2432 err = ENOMEM; 2433 goto errout; 2434 } 2435 bzero(me->me_E.dma_vaddr, normbits / 8); 2436 bcopy(krp->krp_param[UBS_MODEXP_PAR_E].crp_p, 2437 me->me_E.dma_vaddr, (ebits + 7) / 8); 2438 2439 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2440 &me->me_epb, 0)) { 2441 err = ENOMEM; 2442 goto errout; 2443 } 2444 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2445 epb->pb_addr = htole32(me->me_E.dma_paddr); 2446 epb->pb_next = 0; 2447 epb->pb_len = htole32((ebits + 7) / 8); 2448 2449#ifdef UBSEC_DEBUG 2450 if (ubsec_debug) { 2451 printf("Epb "); 2452 ubsec_dump_pb(epb); 2453 } 2454#endif 2455 2456 mcr->mcr_pkts = htole16(1); 2457 mcr->mcr_flags = 0; 2458 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2459 mcr->mcr_reserved = 0; 2460 mcr->mcr_pktlen = 0; 2461 2462 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2463 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2464 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2465 2466 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2467 mcr->mcr_opktbuf.pb_next = 0; 2468 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2469 2470#ifdef DIAGNOSTIC 2471 /* Misaligned output buffer will hang the chip. */ 2472 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2473 panic("%s: modexp invalid addr 0x%x\n", 2474 device_get_nameunit(sc->sc_dev), 2475 letoh32(mcr->mcr_opktbuf.pb_addr)); 2476 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2477 panic("%s: modexp invalid len 0x%x\n", 2478 device_get_nameunit(sc->sc_dev), 2479 letoh32(mcr->mcr_opktbuf.pb_len)); 2480#endif 2481 2482 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2483 bzero(ctx, sizeof(*ctx)); 2484 bcopy(krp->krp_param[UBS_MODEXP_PAR_N].crp_p, ctx->me_N, 2485 (nbits + 7) / 8); 2486 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2487 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2488 ctx->me_E_len = htole16(ebits); 2489 ctx->me_N_len = htole16(nbits); 2490 2491#ifdef UBSEC_DEBUG 2492 if (ubsec_debug) { 2493 ubsec_dump_mcr(mcr); 2494 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2495 } 2496#endif 2497 2498 /* 2499 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2500 * everything else. 2501 */ 2502 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE); 2503 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE); 2504 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD); 2505 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE); 2506 2507 /* Enqueue and we're done... */ 2508 mtx_lock(&sc->sc_mcr2lock); 2509 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2510 ubsec_feed2(sc); 2511 mtx_unlock(&sc->sc_mcr2lock); 2512 2513 return (0); 2514 2515errout: 2516 if (me != NULL) { 2517 if (me->me_q.q_mcr.dma_map != NULL) 2518 ubsec_dma_free(sc, &me->me_q.q_mcr); 2519 if (me->me_q.q_ctx.dma_map != NULL) { 2520 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 2521 ubsec_dma_free(sc, &me->me_q.q_ctx); 2522 } 2523 if (me->me_M.dma_map != NULL) { 2524 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 2525 ubsec_dma_free(sc, &me->me_M); 2526 } 2527 if (me->me_E.dma_map != NULL) { 2528 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 2529 ubsec_dma_free(sc, &me->me_E); 2530 } 2531 if (me->me_C.dma_map != NULL) { 2532 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2533 ubsec_dma_free(sc, &me->me_C); 2534 } 2535 if (me->me_epb.dma_map != NULL) 2536 ubsec_dma_free(sc, &me->me_epb); 2537 free(me, M_DEVBUF); 2538 } 2539 krp->krp_status = err; 2540 crypto_kdone(krp); 2541 return (0); 2542} 2543 2544static int 2545ubsec_kprocess_rsapriv(struct ubsec_softc *sc, struct cryptkop *krp, int hint) 2546{ 2547 struct ubsec_q2_rsapriv *rp = NULL; 2548 struct ubsec_mcr *mcr; 2549 struct ubsec_ctx_rsapriv *ctx; 2550 int err = 0; 2551 u_int padlen, msglen; 2552 2553 msglen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_P]); 2554 padlen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_Q]); 2555 if (msglen > padlen) 2556 padlen = msglen; 2557 2558 if (padlen <= 256) 2559 padlen = 256; 2560 else if (padlen <= 384) 2561 padlen = 384; 2562 else if (padlen <= 512) 2563 padlen = 512; 2564 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 768) 2565 padlen = 768; 2566 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 1024) 2567 padlen = 1024; 2568 else { 2569 err = E2BIG; 2570 goto errout; 2571 } 2572 2573 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DP]) > padlen) { 2574 err = E2BIG; 2575 goto errout; 2576 } 2577 2578 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DQ]) > padlen) { 2579 err = E2BIG; 2580 goto errout; 2581 } 2582 2583 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_PINV]) > padlen) { 2584 err = E2BIG; 2585 goto errout; 2586 } 2587 2588 rp = (struct ubsec_q2_rsapriv *)malloc(sizeof *rp, M_DEVBUF, M_NOWAIT); 2589 if (rp == NULL) 2590 return (ENOMEM); 2591 bzero(rp, sizeof *rp); 2592 rp->rpr_krp = krp; 2593 rp->rpr_q.q_type = UBS_CTXOP_RSAPRIV; 2594 2595 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2596 &rp->rpr_q.q_mcr, 0)) { 2597 err = ENOMEM; 2598 goto errout; 2599 } 2600 mcr = (struct ubsec_mcr *)rp->rpr_q.q_mcr.dma_vaddr; 2601 2602 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rsapriv), 2603 &rp->rpr_q.q_ctx, 0)) { 2604 err = ENOMEM; 2605 goto errout; 2606 } 2607 ctx = (struct ubsec_ctx_rsapriv *)rp->rpr_q.q_ctx.dma_vaddr; 2608 bzero(ctx, sizeof *ctx); 2609 2610 /* Copy in p */ 2611 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_P].crp_p, 2612 &ctx->rpr_buf[0 * (padlen / 8)], 2613 (krp->krp_param[UBS_RSAPRIV_PAR_P].crp_nbits + 7) / 8); 2614 2615 /* Copy in q */ 2616 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_p, 2617 &ctx->rpr_buf[1 * (padlen / 8)], 2618 (krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_nbits + 7) / 8); 2619 2620 /* Copy in dp */ 2621 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_p, 2622 &ctx->rpr_buf[2 * (padlen / 8)], 2623 (krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_nbits + 7) / 8); 2624 2625 /* Copy in dq */ 2626 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_p, 2627 &ctx->rpr_buf[3 * (padlen / 8)], 2628 (krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_nbits + 7) / 8); 2629 2630 /* Copy in pinv */ 2631 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_p, 2632 &ctx->rpr_buf[4 * (padlen / 8)], 2633 (krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_nbits + 7) / 8); 2634 2635 msglen = padlen * 2; 2636 2637 /* Copy in input message (aligned buffer/length). */ 2638 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGIN]) > msglen) { 2639 /* Is this likely? */ 2640 err = E2BIG; 2641 goto errout; 2642 } 2643 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgin, 0)) { 2644 err = ENOMEM; 2645 goto errout; 2646 } 2647 bzero(rp->rpr_msgin.dma_vaddr, (msglen + 7) / 8); 2648 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_p, 2649 rp->rpr_msgin.dma_vaddr, 2650 (krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_nbits + 7) / 8); 2651 2652 /* Prepare space for output message (aligned buffer/length). */ 2653 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT]) < msglen) { 2654 /* Is this likely? */ 2655 err = E2BIG; 2656 goto errout; 2657 } 2658 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgout, 0)) { 2659 err = ENOMEM; 2660 goto errout; 2661 } 2662 bzero(rp->rpr_msgout.dma_vaddr, (msglen + 7) / 8); 2663 2664 mcr->mcr_pkts = htole16(1); 2665 mcr->mcr_flags = 0; 2666 mcr->mcr_cmdctxp = htole32(rp->rpr_q.q_ctx.dma_paddr); 2667 mcr->mcr_ipktbuf.pb_addr = htole32(rp->rpr_msgin.dma_paddr); 2668 mcr->mcr_ipktbuf.pb_next = 0; 2669 mcr->mcr_ipktbuf.pb_len = htole32(rp->rpr_msgin.dma_size); 2670 mcr->mcr_reserved = 0; 2671 mcr->mcr_pktlen = htole16(msglen); 2672 mcr->mcr_opktbuf.pb_addr = htole32(rp->rpr_msgout.dma_paddr); 2673 mcr->mcr_opktbuf.pb_next = 0; 2674 mcr->mcr_opktbuf.pb_len = htole32(rp->rpr_msgout.dma_size); 2675 2676#ifdef DIAGNOSTIC 2677 if (rp->rpr_msgin.dma_paddr & 3 || rp->rpr_msgin.dma_size & 3) { 2678 panic("%s: rsapriv: invalid msgin %x(0x%jx)", 2679 device_get_nameunit(sc->sc_dev), 2680 rp->rpr_msgin.dma_paddr, (uintmax_t)rp->rpr_msgin.dma_size); 2681 } 2682 if (rp->rpr_msgout.dma_paddr & 3 || rp->rpr_msgout.dma_size & 3) { 2683 panic("%s: rsapriv: invalid msgout %x(0x%jx)", 2684 device_get_nameunit(sc->sc_dev), 2685 rp->rpr_msgout.dma_paddr, (uintmax_t)rp->rpr_msgout.dma_size); 2686 } 2687#endif 2688 2689 ctx->rpr_len = (sizeof(u_int16_t) * 4) + (5 * (padlen / 8)); 2690 ctx->rpr_op = htole16(UBS_CTXOP_RSAPRIV); 2691 ctx->rpr_q_len = htole16(padlen); 2692 ctx->rpr_p_len = htole16(padlen); 2693 2694 /* 2695 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2696 * everything else. 2697 */ 2698 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_PREWRITE); 2699 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_PREREAD); 2700 2701 /* Enqueue and we're done... */ 2702 mtx_lock(&sc->sc_mcr2lock); 2703 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rp->rpr_q, q_next); 2704 ubsec_feed2(sc); 2705 ubsecstats.hst_modexpcrt++; 2706 mtx_unlock(&sc->sc_mcr2lock); 2707 return (0); 2708 2709errout: 2710 if (rp != NULL) { 2711 if (rp->rpr_q.q_mcr.dma_map != NULL) 2712 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 2713 if (rp->rpr_msgin.dma_map != NULL) { 2714 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size); 2715 ubsec_dma_free(sc, &rp->rpr_msgin); 2716 } 2717 if (rp->rpr_msgout.dma_map != NULL) { 2718 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size); 2719 ubsec_dma_free(sc, &rp->rpr_msgout); 2720 } 2721 free(rp, M_DEVBUF); 2722 } 2723 krp->krp_status = err; 2724 crypto_kdone(krp); 2725 return (0); 2726} 2727 2728#ifdef UBSEC_DEBUG 2729static void 2730ubsec_dump_pb(volatile struct ubsec_pktbuf *pb) 2731{ 2732 printf("addr 0x%x (0x%x) next 0x%x\n", 2733 pb->pb_addr, pb->pb_len, pb->pb_next); 2734} 2735 2736static void 2737ubsec_dump_ctx2(struct ubsec_ctx_keyop *c) 2738{ 2739 printf("CTX (0x%x):\n", c->ctx_len); 2740 switch (letoh16(c->ctx_op)) { 2741 case UBS_CTXOP_RNGBYPASS: 2742 case UBS_CTXOP_RNGSHA1: 2743 break; 2744 case UBS_CTXOP_MODEXP: 2745 { 2746 struct ubsec_ctx_modexp *cx = (void *)c; 2747 int i, len; 2748 2749 printf(" Elen %u, Nlen %u\n", 2750 letoh16(cx->me_E_len), letoh16(cx->me_N_len)); 2751 len = (cx->me_N_len + 7)/8; 2752 for (i = 0; i < len; i++) 2753 printf("%s%02x", (i == 0) ? " N: " : ":", cx->me_N[i]); 2754 printf("\n"); 2755 break; 2756 } 2757 default: 2758 printf("unknown context: %x\n", c->ctx_op); 2759 } 2760 printf("END CTX\n"); 2761} 2762 2763static void 2764ubsec_dump_mcr(struct ubsec_mcr *mcr) 2765{ 2766 volatile struct ubsec_mcr_add *ma; 2767 int i; 2768 2769 printf("MCR:\n"); 2770 printf(" pkts: %u, flags 0x%x\n", 2771 letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags)); 2772 ma = (volatile struct ubsec_mcr_add *)&mcr->mcr_cmdctxp; 2773 for (i = 0; i < letoh16(mcr->mcr_pkts); i++) { 2774 printf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i, 2775 letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen), 2776 letoh16(ma->mcr_reserved)); 2777 printf(" %d: ipkt ", i); 2778 ubsec_dump_pb(&ma->mcr_ipktbuf); 2779 printf(" %d: opkt ", i); 2780 ubsec_dump_pb(&ma->mcr_opktbuf); 2781 ma++; 2782 } 2783 printf("END MCR\n"); 2784} 2785#endif /* UBSEC_DEBUG */ 2786 2787/* 2788 * Return the number of significant bits of a big number. 2789 */ 2790static int 2791ubsec_ksigbits(struct crparam *cr) 2792{ 2793 u_int plen = (cr->crp_nbits + 7) / 8; 2794 int i, sig = plen * 8; 2795 u_int8_t c, *p = cr->crp_p; 2796 2797 for (i = plen - 1; i >= 0; i--) { 2798 c = p[i]; 2799 if (c != 0) { 2800 while ((c & 0x80) == 0) { 2801 sig--; 2802 c <<= 1; 2803 } 2804 break; 2805 } 2806 sig -= 8; 2807 } 2808 return (sig); 2809} 2810 2811static void 2812ubsec_kshift_r( 2813 u_int shiftbits, 2814 u_int8_t *src, u_int srcbits, 2815 u_int8_t *dst, u_int dstbits) 2816{ 2817 u_int slen, dlen; 2818 int i, si, di, n; 2819 2820 slen = (srcbits + 7) / 8; 2821 dlen = (dstbits + 7) / 8; 2822 2823 for (i = 0; i < slen; i++) 2824 dst[i] = src[i]; 2825 for (i = 0; i < dlen - slen; i++) 2826 dst[slen + i] = 0; 2827 2828 n = shiftbits / 8; 2829 if (n != 0) { 2830 si = dlen - n - 1; 2831 di = dlen - 1; 2832 while (si >= 0) 2833 dst[di--] = dst[si--]; 2834 while (di >= 0) 2835 dst[di--] = 0; 2836 } 2837 2838 n = shiftbits % 8; 2839 if (n != 0) { 2840 for (i = dlen - 1; i > 0; i--) 2841 dst[i] = (dst[i] << n) | 2842 (dst[i - 1] >> (8 - n)); 2843 dst[0] = dst[0] << n; 2844 } 2845} 2846 2847static void 2848ubsec_kshift_l( 2849 u_int shiftbits, 2850 u_int8_t *src, u_int srcbits, 2851 u_int8_t *dst, u_int dstbits) 2852{ 2853 int slen, dlen, i, n; 2854 2855 slen = (srcbits + 7) / 8; 2856 dlen = (dstbits + 7) / 8; 2857 2858 n = shiftbits / 8; 2859 for (i = 0; i < slen; i++) 2860 dst[i] = src[i + n]; 2861 for (i = 0; i < dlen - slen; i++) 2862 dst[slen + i] = 0; 2863 2864 n = shiftbits % 8; 2865 if (n != 0) { 2866 for (i = 0; i < (dlen - 1); i++) 2867 dst[i] = (dst[i] >> n) | (dst[i + 1] << (8 - n)); 2868 dst[dlen - 1] = dst[dlen - 1] >> n; 2869 } 2870} 2871