uart_bus.h revision 120143
1/* 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/uart/uart_bus.h 120143 2003-09-17 01:41:21Z marcel $ 27 */ 28 29#ifndef _DEV_UART_BUS_H_ 30#define _DEV_UART_BUS_H_ 31 32#ifndef KLD_MODULE 33#include "opt_uart.h" 34#endif 35 36#include <sys/timepps.h> 37 38/* Drain and flush targets. */ 39#define UART_DRAIN_RECEIVER 0x0001 40#define UART_DRAIN_TRANSMITTER 0x0002 41#define UART_FLUSH_RECEIVER UART_DRAIN_RECEIVER 42#define UART_FLUSH_TRANSMITTER UART_DRAIN_TRANSMITTER 43 44/* 45 * Interrupt sources (in priority order). See also uart_core.c 46 * Note that the low order 16 bits are used to pass modem signals 47 * from the hardware interrupt handler to the software interrupt 48 * handler. See UART_SIG_* and UART_SIGMASK_* below. 49 */ 50#define UART_IPEND_OVERRUN 0x010000 51#define UART_IPEND_BREAK 0x020000 52#define UART_IPEND_RXREADY 0x040000 53#define UART_IPEND_SIGCHG 0x080000 54#define UART_IPEND_TXIDLE 0x100000 55 56#define UART_IPEND_MASK 0x1f0000 57#define UART_IPEND_SIGMASK 0x00ffff 58 59/* Received character status bits. */ 60#define UART_STAT_BREAK 0x0100 61#define UART_STAT_FRAMERR 0x0200 62#define UART_STAT_OVERRUN 0x0400 63#define UART_STAT_PARERR 0x0800 64 65/* Modem and line signals. */ 66#define UART_SIG_DTR 0x0001 67#define UART_SIG_RTS 0x0002 68#define UART_SIG_DSR 0x0004 69#define UART_SIG_CTS 0x0008 70#define UART_SIG_DCD 0x0010 71#define UART_SIG_RI 0x0020 72#define UART_SIG_DDTR 0x0100 73#define UART_SIG_DRTS 0x0200 74#define UART_SIG_DDSR 0x0400 75#define UART_SIG_DCTS 0x0800 76#define UART_SIG_DDCD 0x1000 77#define UART_SIG_DRI 0x2000 78 79#define UART_SIGMASK_DTE 0x0003 80#define UART_SIGMASK_DCE 0x003c 81#define UART_SIGMASK_STATE 0x003f 82#define UART_SIGMASK_DELTA 0x3f00 83 84#ifdef UART_PPS_ON_CTS 85#define UART_SIG_DPPS UART_SIG_DCTS 86#define UART_SIG_PPS UART_SIG_CTS 87#else 88#define UART_SIG_DPPS UART_SIG_DDCD 89#define UART_SIG_PPS UART_SIG_DCD 90#endif 91 92/* UART_IOCTL() requests */ 93#define UART_IOCTL_BREAK 1 94#define UART_IOCTL_IFLOW 2 95#define UART_IOCTL_OFLOW 3 96 97/* 98 * UART class & instance (=softc) 99 */ 100struct uart_class { 101 KOBJ_CLASS_FIELDS; 102 u_int uc_range; /* Bus space address range. */ 103 u_int uc_rclk; /* Default rclk for this device. */ 104}; 105 106extern struct uart_class uart_ns8250_class; 107extern struct uart_class uart_sab82532_class; 108extern struct uart_class uart_z8530_class; 109 110struct uart_softc { 111 KOBJ_FIELDS; 112 struct uart_class *sc_class; 113 struct uart_bas sc_bas; 114 device_t sc_dev; 115 116 struct mtx sc_hwmtx; /* Spinlock protecting hardware. */ 117 118 struct resource *sc_rres; /* Register resource. */ 119 int sc_rrid; 120 int sc_rtype; /* SYS_RES_{IOPORT|MEMORY}. */ 121 struct resource *sc_ires; /* Interrupt resource. */ 122 void *sc_icookie; 123 int sc_irid; 124 125 int sc_callout:1; /* This UART is opened for callout. */ 126 int sc_fastintr:1; /* This UART uses fast interrupts. */ 127 int sc_hasfifo:1; /* This UART has FIFOs. */ 128 int sc_hwiflow:1; /* This UART has HW input flow ctl. */ 129 int sc_hwoflow:1; /* This UART has HW output flow ctl. */ 130 int sc_leaving:1; /* This UART is going away. */ 131 int sc_opened:1; /* This UART is open for business. */ 132 int sc_polled:1; /* This UART has no interrupts. */ 133 int sc_txbusy:1; /* This UART is transmitting. */ 134 135 struct uart_devinfo *sc_sysdev; /* System device (or NULL). */ 136 137 int sc_altbrk; /* State for alt break sequence. */ 138 uint32_t sc_hwsig; /* Signal state. Used by HW driver. */ 139 140 /* Receiver data. */ 141 uint16_t *sc_rxbuf; 142 int sc_rxbufsz; 143 int sc_rxput; 144 int sc_rxget; 145 int sc_rxfifosz; /* Size of RX FIFO. */ 146 147 /* Transmitter data. */ 148 uint8_t *sc_txbuf; 149 int sc_txdatasz; 150 int sc_txfifosz; /* Size of TX FIFO and buffer. */ 151 152 /* Pulse capturing support (PPS). */ 153 struct pps_state sc_pps; 154 155 /* Upper layer data. */ 156 void *sc_softih; 157 uint32_t sc_ttypend; 158 union { 159 /* TTY specific data. */ 160 struct { 161 dev_t si[2]; /* We have 2 device special files. */ 162 struct tty *tp; 163 } u_tty; 164 /* Keyboard specific data. */ 165 struct { 166 } u_kbd; 167 } sc_u; 168}; 169 170extern devclass_t uart_devclass; 171extern char uart_driver_name[]; 172 173int uart_bus_attach(device_t dev); 174int uart_bus_detach(device_t dev); 175int uart_bus_probe(device_t dev, int regshft, int rclk, int rid); 176 177int uart_tty_attach(struct uart_softc *); 178int uart_tty_detach(struct uart_softc *); 179void uart_tty_intr(void *arg); 180 181/* 182 * Receive buffer operations. 183 */ 184static __inline int 185uart_rx_empty(struct uart_softc *sc) 186{ 187 return ((sc->sc_rxget == sc->sc_rxput) ? 1 : 0); 188} 189 190static __inline int 191uart_rx_full(struct uart_softc *sc) 192{ 193 return ((sc->sc_rxput + 1 < sc->sc_rxbufsz) 194 ? (sc->sc_rxput + 1 == sc->sc_rxget) : (sc->sc_rxget == 0)); 195} 196 197static __inline int 198uart_rx_get(struct uart_softc *sc) 199{ 200 int ptr, xc; 201 202 ptr = sc->sc_rxget; 203 if (ptr == sc->sc_rxput) 204 return (-1); 205 xc = sc->sc_rxbuf[ptr++]; 206 sc->sc_rxget = (ptr < sc->sc_rxbufsz) ? ptr : 0; 207 return (xc); 208} 209 210static __inline int 211uart_rx_put(struct uart_softc *sc, int xc) 212{ 213 int ptr; 214 215 ptr = (sc->sc_rxput + 1 < sc->sc_rxbufsz) ? sc->sc_rxput + 1 : 0; 216 if (ptr == sc->sc_rxget) 217 return (ENOSPC); 218 sc->sc_rxbuf[sc->sc_rxput] = xc; 219 sc->sc_rxput = ptr; 220 return (0); 221} 222 223#endif /* _DEV_UART_BUS_H_ */ 224