if_txp.c revision 93818
1/* $OpenBSD: if_txp.c,v 1.48 2001/06/27 06:34:50 kjc Exp $ */ 2/* $FreeBSD: head/sys/dev/txp/if_txp.c 93818 2002-04-04 21:03:38Z jhb $ */ 3 4/* 5 * Copyright (c) 2001 6 * Jason L. Wright <jason@thought.net>, Theo de Raadt, and 7 * Aaron Campbell <aaron@monkey.org>. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Jason L. Wright, 20 * Theo de Raadt and Aaron Campbell. 21 * 4. Neither the name of the author nor the names of any co-contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 35 * THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38/* 39 * Driver for 3c990 (Typhoon) Ethernet ASIC 40 */ 41 42#include <sys/param.h> 43#include <sys/systm.h> 44#include <sys/sockio.h> 45#include <sys/mbuf.h> 46#include <sys/malloc.h> 47#include <sys/kernel.h> 48#include <sys/socket.h> 49 50#include <net/if.h> 51#include <net/if_arp.h> 52#include <net/ethernet.h> 53#include <net/if_dl.h> 54#include <net/if_types.h> 55#include <net/if_vlan_var.h> 56 57#include <netinet/in.h> 58#include <netinet/in_systm.h> 59#include <netinet/in_var.h> 60#include <netinet/ip.h> 61#include <netinet/if_ether.h> 62#include <machine/in_cksum.h> 63 64#include <net/if_media.h> 65 66#include <net/bpf.h> 67 68#include <vm/vm.h> /* for vtophys */ 69#include <vm/pmap.h> /* for vtophys */ 70#include <machine/clock.h> /* for DELAY */ 71#include <machine/bus_pio.h> 72#include <machine/bus_memio.h> 73#include <machine/bus.h> 74#include <machine/resource.h> 75#include <sys/bus.h> 76#include <sys/rman.h> 77 78#include <dev/mii/mii.h> 79#include <dev/mii/miivar.h> 80#include <dev/pci/pcireg.h> 81#include <dev/pci/pcivar.h> 82 83#define TXP_USEIOSPACE 84#define __STRICT_ALIGNMENT 85 86#include <dev/txp/if_txpreg.h> 87#include <dev/txp/3c990img.h> 88 89#ifndef lint 90static const char rcsid[] = 91 "$FreeBSD: head/sys/dev/txp/if_txp.c 93818 2002-04-04 21:03:38Z jhb $"; 92#endif 93 94/* 95 * Various supported device vendors/types and their names. 96 */ 97static struct txp_type txp_devs[] = { 98 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_TX_95, 99 "3Com 3cR990-TX-95 Etherlink with 3XP Processor" }, 100 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_TX_97, 101 "3Com 3cR990-TX-97 Etherlink with 3XP Processor" }, 102 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990B_TXM, 103 "3Com 3cR990B-TXM Etherlink with 3XP Processor" }, 104 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_SRV_95, 105 "3Com 3cR990-SRV-95 Etherlink Server with 3XP Processor" }, 106 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_SRV_97, 107 "3Com 3cR990-SRV-97 Etherlink Server with 3XP Processor" }, 108 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990B_SRV, 109 "3Com 3cR990B-SRV Etherlink Server with 3XP Processor" }, 110 { 0, 0, NULL } 111}; 112 113static int txp_probe (device_t); 114static int txp_attach (device_t); 115static int txp_detach (device_t); 116static void txp_intr (void *); 117static void txp_tick (void *); 118static int txp_shutdown (device_t); 119static int txp_ioctl (struct ifnet *, u_long, caddr_t); 120static void txp_start (struct ifnet *); 121static void txp_stop (struct txp_softc *); 122static void txp_init (void *); 123static void txp_watchdog (struct ifnet *); 124 125static void txp_release_resources(struct txp_softc *); 126static int txp_chip_init(struct txp_softc *); 127static int txp_reset_adapter(struct txp_softc *); 128static int txp_download_fw(struct txp_softc *); 129static int txp_download_fw_wait(struct txp_softc *); 130static int txp_download_fw_section (struct txp_softc *, 131 struct txp_fw_section_header *, int); 132static int txp_alloc_rings(struct txp_softc *); 133static int txp_rxring_fill(struct txp_softc *); 134static void txp_rxring_empty(struct txp_softc *); 135static void txp_set_filter(struct txp_softc *); 136 137static int txp_cmd_desc_numfree(struct txp_softc *); 138static int txp_command (struct txp_softc *, u_int16_t, u_int16_t, u_int32_t, 139 u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int); 140static int txp_command2 (struct txp_softc *, u_int16_t, u_int16_t, 141 u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t, 142 struct txp_rsp_desc **, int); 143static int txp_response (struct txp_softc *, u_int32_t, u_int16_t, u_int16_t, 144 struct txp_rsp_desc **); 145static void txp_rsp_fixup (struct txp_softc *, struct txp_rsp_desc *, 146 struct txp_rsp_desc *); 147static void txp_capabilities(struct txp_softc *); 148 149static void txp_ifmedia_sts(struct ifnet *, struct ifmediareq *); 150static int txp_ifmedia_upd(struct ifnet *); 151#ifdef TXP_DEBUG 152static void txp_show_descriptor(void *); 153#endif 154static void txp_tx_reclaim(struct txp_softc *, struct txp_tx_ring *); 155static void txp_rxbuf_reclaim(struct txp_softc *); 156static void txp_rx_reclaim(struct txp_softc *, struct txp_rx_ring *); 157 158#ifdef TXP_USEIOSPACE 159#define TXP_RES SYS_RES_IOPORT 160#define TXP_RID TXP_PCI_LOIO 161#else 162#define TXP_RES SYS_RES_MEMORY 163#define TXP_RID TXP_PCI_LOMEM 164#endif 165 166static device_method_t txp_methods[] = { 167 /* Device interface */ 168 DEVMETHOD(device_probe, txp_probe), 169 DEVMETHOD(device_attach, txp_attach), 170 DEVMETHOD(device_detach, txp_detach), 171 DEVMETHOD(device_shutdown, txp_shutdown), 172 { 0, 0 } 173}; 174 175static driver_t txp_driver = { 176 "txp", 177 txp_methods, 178 sizeof(struct txp_softc) 179}; 180 181static devclass_t txp_devclass; 182 183DRIVER_MODULE(if_txp, pci, txp_driver, txp_devclass, 0, 0); 184 185static int 186txp_probe(dev) 187 device_t dev; 188{ 189 struct txp_type *t; 190 191 t = txp_devs; 192 193 while(t->txp_name != NULL) { 194 if ((pci_get_vendor(dev) == t->txp_vid) && 195 (pci_get_device(dev) == t->txp_did)) { 196 device_set_desc(dev, t->txp_name); 197 return(0); 198 } 199 t++; 200 } 201 202 return(ENXIO); 203} 204 205static int 206txp_attach(dev) 207 device_t dev; 208{ 209 struct txp_softc *sc; 210 struct ifnet *ifp; 211 u_int32_t command; 212 u_int16_t p1; 213 u_int32_t p2; 214 int unit, error = 0, rid; 215 216 sc = device_get_softc(dev); 217 unit = device_get_unit(dev); 218 sc->sc_dev = dev; 219 sc->sc_cold = 1; 220 221 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 222 MTX_DEF | MTX_RECURSE); 223 224 /* 225 * Handle power management nonsense. 226 */ 227 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 228 u_int32_t iobase, membase, irq; 229 230 /* Save important PCI config data. */ 231 iobase = pci_read_config(dev, TXP_PCI_LOIO, 4); 232 membase = pci_read_config(dev, TXP_PCI_LOMEM, 4); 233 irq = pci_read_config(dev, TXP_PCI_INTLINE, 4); 234 235 /* Reset the power state. */ 236 device_printf(dev, "chip is in D%d power mode " 237 "-- setting to D0\n", pci_get_powerstate(dev)); 238 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 239 240 /* Restore PCI config data. */ 241 pci_write_config(dev, TXP_PCI_LOIO, iobase, 4); 242 pci_write_config(dev, TXP_PCI_LOMEM, membase, 4); 243 pci_write_config(dev, TXP_PCI_INTLINE, irq, 4); 244 } 245 246 /* 247 * Map control/status registers. 248 */ 249 pci_enable_busmaster(dev); 250 pci_enable_io(dev, SYS_RES_IOPORT); 251 pci_enable_io(dev, SYS_RES_MEMORY); 252 command = pci_read_config(dev, PCIR_COMMAND, 4); 253 254#ifdef TXP_USEIOSPACE 255 if (!(command & PCIM_CMD_PORTEN)) { 256 device_printf(dev, "failed to enable I/O ports!\n"); 257 error = ENXIO; 258 goto fail; 259 } 260#else 261 if (!(command & PCIM_CMD_MEMEN)) { 262 device_printf(dev, "failed to enable memory mapping!\n"); 263 error = ENXIO; 264 goto fail; 265 } 266#endif 267 268 rid = TXP_RID; 269 sc->sc_res = bus_alloc_resource(dev, TXP_RES, &rid, 270 0, ~0, 1, RF_ACTIVE); 271 272 if (sc->sc_res == NULL) { 273 device_printf(dev, "couldn't map ports/memory\n"); 274 error = ENXIO; 275 goto fail; 276 } 277 278 sc->sc_bt = rman_get_bustag(sc->sc_res); 279 sc->sc_bh = rman_get_bushandle(sc->sc_res); 280 281 /* Allocate interrupt */ 282 rid = 0; 283 sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 284 RF_SHAREABLE | RF_ACTIVE); 285 286 if (sc->sc_irq == NULL) { 287 device_printf(dev, "couldn't map interrupt\n"); 288 txp_release_resources(sc); 289 error = ENXIO; 290 goto fail; 291 } 292 293 error = bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET, 294 txp_intr, sc, &sc->sc_intrhand); 295 296 if (error) { 297 txp_release_resources(sc); 298 device_printf(dev, "couldn't set up irq\n"); 299 goto fail; 300 } 301 302 if (txp_chip_init(sc)) { 303 txp_release_resources(sc); 304 goto fail; 305 } 306 307 sc->sc_fwbuf = contigmalloc(32768, M_DEVBUF, 308 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 309 error = txp_download_fw(sc); 310 contigfree(sc->sc_fwbuf, 32768, M_DEVBUF); 311 sc->sc_fwbuf = NULL; 312 313 if (error) { 314 txp_release_resources(sc); 315 goto fail; 316 } 317 318 sc->sc_ldata = contigmalloc(sizeof(struct txp_ldata), M_DEVBUF, 319 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 320 bzero(sc->sc_ldata, sizeof(struct txp_ldata)); 321 322 if (txp_alloc_rings(sc)) { 323 txp_release_resources(sc); 324 goto fail; 325 } 326 327 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 328 NULL, NULL, NULL, 1)) { 329 txp_release_resources(sc); 330 goto fail; 331 } 332 333 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0, 334 &p1, &p2, NULL, 1)) { 335 txp_release_resources(sc); 336 goto fail; 337 } 338 339 txp_set_filter(sc); 340 341 sc->sc_arpcom.ac_enaddr[0] = ((u_int8_t *)&p1)[1]; 342 sc->sc_arpcom.ac_enaddr[1] = ((u_int8_t *)&p1)[0]; 343 sc->sc_arpcom.ac_enaddr[2] = ((u_int8_t *)&p2)[3]; 344 sc->sc_arpcom.ac_enaddr[3] = ((u_int8_t *)&p2)[2]; 345 sc->sc_arpcom.ac_enaddr[4] = ((u_int8_t *)&p2)[1]; 346 sc->sc_arpcom.ac_enaddr[5] = ((u_int8_t *)&p2)[0]; 347 348 printf("txp%d: Ethernet address %6D\n", unit, 349 sc->sc_arpcom.ac_enaddr, ":"); 350 351 sc->sc_cold = 0; 352 353 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts); 354 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 355 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 356 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 357 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 358 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL); 359 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 360 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 361 362 sc->sc_xcvr = TXP_XCVR_AUTO; 363 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0, 364 NULL, NULL, NULL, 0); 365 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 366 367 ifp = &sc->sc_arpcom.ac_if; 368 ifp->if_softc = sc; 369 ifp->if_unit = unit; 370 ifp->if_name = "txp"; 371 ifp->if_mtu = ETHERMTU; 372 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 373 ifp->if_ioctl = txp_ioctl; 374 ifp->if_output = ether_output; 375 ifp->if_start = txp_start; 376 ifp->if_watchdog = txp_watchdog; 377 ifp->if_init = txp_init; 378 ifp->if_baudrate = 100000000; 379 ifp->if_snd.ifq_maxlen = TX_ENTRIES; 380 ifp->if_hwassist = 0; 381 txp_capabilities(sc); 382 383 /* 384 * Attach us everywhere 385 */ 386 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 387 callout_handle_init(&sc->sc_tick); 388 return(0); 389 390fail: 391 txp_release_resources(sc); 392 mtx_destroy(&sc->sc_mtx); 393 return(error); 394} 395 396static int 397txp_detach(dev) 398 device_t dev; 399{ 400 struct txp_softc *sc; 401 struct ifnet *ifp; 402 int i; 403 404 sc = device_get_softc(dev); 405 ifp = &sc->sc_arpcom.ac_if; 406 407 txp_stop(sc); 408 txp_shutdown(dev); 409 410 ifmedia_removeall(&sc->sc_ifmedia); 411 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 412 413 for (i = 0; i < RXBUF_ENTRIES; i++) 414 free(sc->sc_rxbufs[i].rb_sd, M_DEVBUF); 415 416 txp_release_resources(sc); 417 418 mtx_destroy(&sc->sc_mtx); 419 return(0); 420} 421 422static void 423txp_release_resources(sc) 424 struct txp_softc *sc; 425{ 426 device_t dev; 427 428 dev = sc->sc_dev; 429 430 if (sc->sc_intrhand != NULL) 431 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand); 432 433 if (sc->sc_irq != NULL) 434 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 435 436 if (sc->sc_res != NULL) 437 bus_release_resource(dev, TXP_RES, TXP_RID, sc->sc_res); 438 439 if (sc->sc_ldata != NULL) 440 contigfree(sc->sc_ldata, sizeof(struct txp_ldata), M_DEVBUF); 441 442 return; 443} 444 445static int 446txp_chip_init(sc) 447 struct txp_softc *sc; 448{ 449 /* disable interrupts */ 450 WRITE_REG(sc, TXP_IER, 0); 451 WRITE_REG(sc, TXP_IMR, 452 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 453 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 454 TXP_INT_LATCH); 455 456 /* ack all interrupts */ 457 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 458 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 459 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 460 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 461 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 462 463 if (txp_reset_adapter(sc)) 464 return (-1); 465 466 /* disable interrupts */ 467 WRITE_REG(sc, TXP_IER, 0); 468 WRITE_REG(sc, TXP_IMR, 469 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 470 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 471 TXP_INT_LATCH); 472 473 /* ack all interrupts */ 474 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 475 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 476 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 477 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 478 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 479 480 return (0); 481} 482 483static int 484txp_reset_adapter(sc) 485 struct txp_softc *sc; 486{ 487 u_int32_t r; 488 int i; 489 490 r = 0; 491 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL); 492 DELAY(1000); 493 WRITE_REG(sc, TXP_SRR, 0); 494 495 /* Should wait max 6 seconds */ 496 for (i = 0; i < 6000; i++) { 497 r = READ_REG(sc, TXP_A2H_0); 498 if (r == STAT_WAITING_FOR_HOST_REQUEST) 499 break; 500 DELAY(1000); 501 } 502 503 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 504 device_printf(sc->sc_dev, "reset hung\n"); 505 return (-1); 506 } 507 508 return (0); 509} 510 511static int 512txp_download_fw(sc) 513 struct txp_softc *sc; 514{ 515 struct txp_fw_file_header *fileheader; 516 struct txp_fw_section_header *secthead; 517 int sect; 518 u_int32_t r, i, ier, imr; 519 520 r = 0; 521 ier = READ_REG(sc, TXP_IER); 522 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0); 523 524 imr = READ_REG(sc, TXP_IMR); 525 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0); 526 527 for (i = 0; i < 10000; i++) { 528 r = READ_REG(sc, TXP_A2H_0); 529 if (r == STAT_WAITING_FOR_HOST_REQUEST) 530 break; 531 DELAY(50); 532 } 533 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 534 device_printf(sc->sc_dev, "not waiting for host request\n"); 535 return (-1); 536 } 537 538 /* Ack the status */ 539 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 540 541 fileheader = (struct txp_fw_file_header *)tc990image; 542 if (bcmp("TYPHOON", fileheader->magicid, sizeof(fileheader->magicid))) { 543 device_printf(sc->sc_dev, "fw invalid magic\n"); 544 return (-1); 545 } 546 547 /* Tell boot firmware to get ready for image */ 548 WRITE_REG(sc, TXP_H2A_1, fileheader->addr); 549 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE); 550 551 if (txp_download_fw_wait(sc)) { 552 device_printf(sc->sc_dev, "fw wait failed, initial\n"); 553 return (-1); 554 } 555 556 secthead = (struct txp_fw_section_header *)(((u_int8_t *)tc990image) + 557 sizeof(struct txp_fw_file_header)); 558 559 for (sect = 0; sect < fileheader->nsections; sect++) { 560 if (txp_download_fw_section(sc, secthead, sect)) 561 return (-1); 562 secthead = (struct txp_fw_section_header *) 563 (((u_int8_t *)secthead) + secthead->nbytes + 564 sizeof(*secthead)); 565 } 566 567 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE); 568 569 for (i = 0; i < 10000; i++) { 570 r = READ_REG(sc, TXP_A2H_0); 571 if (r == STAT_WAITING_FOR_BOOT) 572 break; 573 DELAY(50); 574 } 575 if (r != STAT_WAITING_FOR_BOOT) { 576 device_printf(sc->sc_dev, "not waiting for boot\n"); 577 return (-1); 578 } 579 580 WRITE_REG(sc, TXP_IER, ier); 581 WRITE_REG(sc, TXP_IMR, imr); 582 583 return (0); 584} 585 586static int 587txp_download_fw_wait(sc) 588 struct txp_softc *sc; 589{ 590 u_int32_t i, r; 591 592 r = 0; 593 for (i = 0; i < 10000; i++) { 594 r = READ_REG(sc, TXP_ISR); 595 if (r & TXP_INT_A2H_0) 596 break; 597 DELAY(50); 598 } 599 600 if (!(r & TXP_INT_A2H_0)) { 601 device_printf(sc->sc_dev, "fw wait failed comm0\n"); 602 return (-1); 603 } 604 605 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 606 607 r = READ_REG(sc, TXP_A2H_0); 608 if (r != STAT_WAITING_FOR_SEGMENT) { 609 device_printf(sc->sc_dev, "fw not waiting for segment\n"); 610 return (-1); 611 } 612 return (0); 613} 614 615static int 616txp_download_fw_section(sc, sect, sectnum) 617 struct txp_softc *sc; 618 struct txp_fw_section_header *sect; 619 int sectnum; 620{ 621 vm_offset_t dma; 622 int rseg, err = 0; 623 struct mbuf m; 624 u_int16_t csum; 625 626 /* Skip zero length sections */ 627 if (sect->nbytes == 0) 628 return (0); 629 630 /* Make sure we aren't past the end of the image */ 631 rseg = ((u_int8_t *)sect) - ((u_int8_t *)tc990image); 632 if (rseg >= sizeof(tc990image)) { 633 device_printf(sc->sc_dev, "fw invalid section address, " 634 "section %d\n", sectnum); 635 return (-1); 636 } 637 638 /* Make sure this section doesn't go past the end */ 639 rseg += sect->nbytes; 640 if (rseg >= sizeof(tc990image)) { 641 device_printf(sc->sc_dev, "fw truncated section %d\n", 642 sectnum); 643 return (-1); 644 } 645 646 bcopy(((u_int8_t *)sect) + sizeof(*sect), sc->sc_fwbuf, sect->nbytes); 647 dma = vtophys(sc->sc_fwbuf); 648 649 /* 650 * dummy up mbuf and verify section checksum 651 */ 652 m.m_type = MT_DATA; 653 m.m_next = m.m_nextpkt = NULL; 654 m.m_len = sect->nbytes; 655 m.m_data = sc->sc_fwbuf; 656 m.m_flags = 0; 657 csum = in_cksum(&m, sect->nbytes); 658 if (csum != sect->cksum) { 659 device_printf(sc->sc_dev, "fw section %d, bad " 660 "cksum (expected 0x%x got 0x%x)\n", 661 sectnum, sect->cksum, csum); 662 err = -1; 663 goto bail; 664 } 665 666 WRITE_REG(sc, TXP_H2A_1, sect->nbytes); 667 WRITE_REG(sc, TXP_H2A_2, sect->cksum); 668 WRITE_REG(sc, TXP_H2A_3, sect->addr); 669 WRITE_REG(sc, TXP_H2A_4, 0); 670 WRITE_REG(sc, TXP_H2A_5, dma & 0xffffffff); 671 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE); 672 673 if (txp_download_fw_wait(sc)) { 674 device_printf(sc->sc_dev, "fw wait failed, " 675 "section %d\n", sectnum); 676 err = -1; 677 } 678 679bail: 680 return (err); 681} 682 683static void 684txp_intr(vsc) 685 void *vsc; 686{ 687 struct txp_softc *sc = vsc; 688 struct txp_hostvar *hv = sc->sc_hostvar; 689 u_int32_t isr; 690 691 /* mask all interrupts */ 692 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF | 693 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 694 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 695 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 696 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 697 698 isr = READ_REG(sc, TXP_ISR); 699 while (isr) { 700 WRITE_REG(sc, TXP_ISR, isr); 701 702 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff)) 703 txp_rx_reclaim(sc, &sc->sc_rxhir); 704 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff)) 705 txp_rx_reclaim(sc, &sc->sc_rxlor); 706 707 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx) 708 txp_rxbuf_reclaim(sc); 709 710 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons != 711 TXP_OFFSET2IDX(*(sc->sc_txhir.r_off)))) 712 txp_tx_reclaim(sc, &sc->sc_txhir); 713 714 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons != 715 TXP_OFFSET2IDX(*(sc->sc_txlor.r_off)))) 716 txp_tx_reclaim(sc, &sc->sc_txlor); 717 718 isr = READ_REG(sc, TXP_ISR); 719 } 720 721 /* unmask all interrupts */ 722 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 723 724 txp_start(&sc->sc_arpcom.ac_if); 725 726 return; 727} 728 729static void 730txp_rx_reclaim(sc, r) 731 struct txp_softc *sc; 732 struct txp_rx_ring *r; 733{ 734 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 735 struct txp_rx_desc *rxd; 736 struct mbuf *m; 737 struct txp_swdesc *sd = NULL; 738 u_int32_t roff, woff; 739 struct ether_header *eh = NULL; 740 741 roff = *r->r_roff; 742 woff = *r->r_woff; 743 rxd = r->r_desc + (roff / sizeof(struct txp_rx_desc)); 744 745 while (roff != woff) { 746 747 if (rxd->rx_flags & RX_FLAGS_ERROR) { 748 device_printf(sc->sc_dev, "error 0x%x\n", 749 rxd->rx_stat); 750 ifp->if_ierrors++; 751 goto next; 752 } 753 754 /* retrieve stashed pointer */ 755 sd = rxd->rx_sd; 756 757 m = sd->sd_mbuf; 758 sd->sd_mbuf = NULL; 759 760 m->m_pkthdr.len = m->m_len = rxd->rx_len; 761 762#ifdef __STRICT_ALIGNMENT 763 { 764 /* 765 * XXX Nice chip, except it won't accept "off by 2" 766 * buffers, so we're force to copy. Supposedly 767 * this will be fixed in a newer firmware rev 768 * and this will be temporary. 769 */ 770 struct mbuf *mnew; 771 772 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 773 if (mnew == NULL) { 774 m_freem(m); 775 goto next; 776 } 777 if (m->m_len > (MHLEN - 2)) { 778 MCLGET(mnew, M_DONTWAIT); 779 if (!(mnew->m_flags & M_EXT)) { 780 m_freem(mnew); 781 m_freem(m); 782 goto next; 783 } 784 } 785 mnew->m_pkthdr.rcvif = ifp; 786 m_adj(mnew, 2); 787 mnew->m_pkthdr.len = mnew->m_len = m->m_len; 788 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, caddr_t)); 789 m_freem(m); 790 m = mnew; 791 } 792#endif 793 794 if (rxd->rx_stat & RX_STAT_IPCKSUMBAD) 795 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 796 else if (rxd->rx_stat & RX_STAT_IPCKSUMGOOD) 797 m->m_pkthdr.csum_flags |= 798 CSUM_IP_CHECKED|CSUM_IP_VALID; 799 800 if ((rxd->rx_stat & RX_STAT_TCPCKSUMGOOD) || 801 (rxd->rx_stat & RX_STAT_UDPCKSUMGOOD)) { 802 m->m_pkthdr.csum_flags |= 803 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 804 m->m_pkthdr.csum_data = 0xffff; 805 } 806 807 eh = mtod(m, struct ether_header *); 808 /* Remove header from mbuf and pass it on. */ 809 m_adj(m, sizeof(struct ether_header)); 810 811 if (rxd->rx_stat & RX_STAT_VLAN) { 812 VLAN_INPUT_TAG(eh, m, htons(rxd->rx_vlan >> 16)); 813 goto next; 814 } 815 816 ether_input(ifp, eh, m); 817 818next: 819 820 roff += sizeof(struct txp_rx_desc); 821 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) { 822 roff = 0; 823 rxd = r->r_desc; 824 } else 825 rxd++; 826 woff = *r->r_woff; 827 } 828 829 *r->r_roff = woff; 830 831 return; 832} 833 834static void 835txp_rxbuf_reclaim(sc) 836 struct txp_softc *sc; 837{ 838 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 839 struct txp_hostvar *hv = sc->sc_hostvar; 840 struct txp_rxbuf_desc *rbd; 841 struct txp_swdesc *sd; 842 u_int32_t i; 843 844 if (!(ifp->if_flags & IFF_RUNNING)) 845 return; 846 847 i = sc->sc_rxbufprod; 848 rbd = sc->sc_rxbufs + i; 849 850 while (1) { 851 sd = rbd->rb_sd; 852 if (sd->sd_mbuf != NULL) 853 break; 854 855 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 856 if (sd->sd_mbuf == NULL) 857 goto err_sd; 858 859 MCLGET(sd->sd_mbuf, M_DONTWAIT); 860 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) 861 goto err_mbuf; 862 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 863 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 864 865 rbd->rb_paddrlo = vtophys(mtod(sd->sd_mbuf, vm_offset_t)) 866 & 0xffffffff; 867 rbd->rb_paddrhi = 0; 868 869 hv->hv_rx_buf_write_idx = TXP_IDX2OFFSET(i); 870 871 if (++i == RXBUF_ENTRIES) { 872 i = 0; 873 rbd = sc->sc_rxbufs; 874 } else 875 rbd++; 876 } 877 878 sc->sc_rxbufprod = i; 879 880 return; 881 882err_mbuf: 883 m_freem(sd->sd_mbuf); 884err_sd: 885 free(sd, M_DEVBUF); 886} 887 888/* 889 * Reclaim mbufs and entries from a transmit ring. 890 */ 891static void 892txp_tx_reclaim(sc, r) 893 struct txp_softc *sc; 894 struct txp_tx_ring *r; 895{ 896 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 897 u_int32_t idx = TXP_OFFSET2IDX(*(r->r_off)); 898 u_int32_t cons = r->r_cons, cnt = r->r_cnt; 899 struct txp_tx_desc *txd = r->r_desc + cons; 900 struct txp_swdesc *sd = sc->sc_txd + cons; 901 struct mbuf *m; 902 903 while (cons != idx) { 904 if (cnt == 0) 905 break; 906 907 if ((txd->tx_flags & TX_FLAGS_TYPE_M) == 908 TX_FLAGS_TYPE_DATA) { 909 m = sd->sd_mbuf; 910 if (m != NULL) { 911 m_freem(m); 912 txd->tx_addrlo = 0; 913 txd->tx_addrhi = 0; 914 ifp->if_opackets++; 915 } 916 } 917 ifp->if_flags &= ~IFF_OACTIVE; 918 919 if (++cons == TX_ENTRIES) { 920 txd = r->r_desc; 921 cons = 0; 922 sd = sc->sc_txd; 923 } else { 924 txd++; 925 sd++; 926 } 927 928 cnt--; 929 } 930 931 r->r_cons = cons; 932 r->r_cnt = cnt; 933 if (cnt == 0) 934 ifp->if_timer = 0; 935} 936 937static int 938txp_shutdown(dev) 939 device_t dev; 940{ 941 struct txp_softc *sc; 942 943 sc = device_get_softc(dev); 944 945 /* mask all interrupts */ 946 WRITE_REG(sc, TXP_IMR, 947 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 948 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 949 TXP_INT_LATCH); 950 951 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 952 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 953 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0); 954 955 return(0); 956} 957 958static int 959txp_alloc_rings(sc) 960 struct txp_softc *sc; 961{ 962 struct txp_boot_record *boot; 963 struct txp_ldata *ld; 964 u_int32_t r; 965 int i; 966 967 r = 0; 968 ld = sc->sc_ldata; 969 boot = &ld->txp_boot; 970 971 /* boot record */ 972 sc->sc_boot = boot; 973 974 /* host variables */ 975 bzero(&ld->txp_hostvar, sizeof(struct txp_hostvar)); 976 boot->br_hostvar_lo = vtophys(&ld->txp_hostvar); 977 boot->br_hostvar_hi = 0; 978 sc->sc_hostvar = (struct txp_hostvar *)&ld->txp_hostvar; 979 980 /* hi priority tx ring */ 981 boot->br_txhipri_lo = vtophys(&ld->txp_txhiring);; 982 boot->br_txhipri_hi = 0; 983 boot->br_txhipri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc); 984 sc->sc_txhir.r_reg = TXP_H2A_1; 985 sc->sc_txhir.r_desc = (struct txp_tx_desc *)&ld->txp_txhiring; 986 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0; 987 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx; 988 989 /* lo priority tx ring */ 990 boot->br_txlopri_lo = vtophys(&ld->txp_txloring); 991 boot->br_txlopri_hi = 0; 992 boot->br_txlopri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc); 993 sc->sc_txlor.r_reg = TXP_H2A_3; 994 sc->sc_txlor.r_desc = (struct txp_tx_desc *)&ld->txp_txloring; 995 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0; 996 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx; 997 998 /* high priority rx ring */ 999 boot->br_rxhipri_lo = vtophys(&ld->txp_rxhiring); 1000 boot->br_rxhipri_hi = 0; 1001 boot->br_rxhipri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc); 1002 sc->sc_rxhir.r_desc = (struct txp_rx_desc *)&ld->txp_rxhiring; 1003 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx; 1004 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx; 1005 1006 /* low priority rx ring */ 1007 boot->br_rxlopri_lo = vtophys(&ld->txp_rxloring); 1008 boot->br_rxlopri_hi = 0; 1009 boot->br_rxlopri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc); 1010 sc->sc_rxlor.r_desc = (struct txp_rx_desc *)&ld->txp_rxloring; 1011 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx; 1012 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx; 1013 1014 /* command ring */ 1015 bzero(&ld->txp_cmdring, sizeof(struct txp_cmd_desc) * CMD_ENTRIES); 1016 boot->br_cmd_lo = vtophys(&ld->txp_cmdring); 1017 boot->br_cmd_hi = 0; 1018 boot->br_cmd_siz = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 1019 sc->sc_cmdring.base = (struct txp_cmd_desc *)&ld->txp_cmdring; 1020 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 1021 sc->sc_cmdring.lastwrite = 0; 1022 1023 /* response ring */ 1024 bzero(&ld->txp_rspring, sizeof(struct txp_rsp_desc) * RSP_ENTRIES); 1025 boot->br_resp_lo = vtophys(&ld->txp_rspring); 1026 boot->br_resp_hi = 0; 1027 boot->br_resp_siz = CMD_ENTRIES * sizeof(struct txp_rsp_desc); 1028 sc->sc_rspring.base = (struct txp_rsp_desc *)&ld->txp_rspring; 1029 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc); 1030 sc->sc_rspring.lastwrite = 0; 1031 1032 /* receive buffer ring */ 1033 boot->br_rxbuf_lo = vtophys(&ld->txp_rxbufs); 1034 boot->br_rxbuf_hi = 0; 1035 boot->br_rxbuf_siz = RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc); 1036 sc->sc_rxbufs = (struct txp_rxbuf_desc *)&ld->txp_rxbufs; 1037 1038 for (i = 0; i < RXBUF_ENTRIES; i++) { 1039 struct txp_swdesc *sd; 1040 if (sc->sc_rxbufs[i].rb_sd != NULL) 1041 continue; 1042 sc->sc_rxbufs[i].rb_sd = malloc(sizeof(struct txp_swdesc), 1043 M_DEVBUF, M_NOWAIT); 1044 if (sc->sc_rxbufs[i].rb_sd == NULL) 1045 return(ENOBUFS); 1046 sd = sc->sc_rxbufs[i].rb_sd; 1047 sd->sd_mbuf = NULL; 1048 } 1049 sc->sc_rxbufprod = 0; 1050 1051 /* zero dma */ 1052 bzero(&ld->txp_zero, sizeof(u_int32_t)); 1053 boot->br_zero_lo = vtophys(&ld->txp_zero); 1054 boot->br_zero_hi = 0; 1055 1056 /* See if it's waiting for boot, and try to boot it */ 1057 for (i = 0; i < 10000; i++) { 1058 r = READ_REG(sc, TXP_A2H_0); 1059 if (r == STAT_WAITING_FOR_BOOT) 1060 break; 1061 DELAY(50); 1062 } 1063 1064 if (r != STAT_WAITING_FOR_BOOT) { 1065 device_printf(sc->sc_dev, "not waiting for boot\n"); 1066 return(ENXIO); 1067 } 1068 1069 WRITE_REG(sc, TXP_H2A_2, 0); 1070 WRITE_REG(sc, TXP_H2A_1, vtophys(sc->sc_boot)); 1071 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD); 1072 1073 /* See if it booted */ 1074 for (i = 0; i < 10000; i++) { 1075 r = READ_REG(sc, TXP_A2H_0); 1076 if (r == STAT_RUNNING) 1077 break; 1078 DELAY(50); 1079 } 1080 if (r != STAT_RUNNING) { 1081 device_printf(sc->sc_dev, "fw not running\n"); 1082 return(ENXIO); 1083 } 1084 1085 /* Clear TX and CMD ring write registers */ 1086 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL); 1087 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL); 1088 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL); 1089 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL); 1090 1091 return (0); 1092} 1093 1094static int 1095txp_ioctl(ifp, command, data) 1096 struct ifnet *ifp; 1097 u_long command; 1098 caddr_t data; 1099{ 1100 struct txp_softc *sc = ifp->if_softc; 1101 struct ifreq *ifr = (struct ifreq *)data; 1102 int s, error = 0; 1103 1104 s = splnet(); 1105 1106 if ((error = ether_ioctl(ifp, command, data)) > 0) { 1107 splx(s); 1108 return error; 1109 } 1110 1111 switch(command) { 1112 case SIOCSIFADDR: 1113 case SIOCGIFADDR: 1114 case SIOCSIFMTU: 1115 error = ether_ioctl(ifp, command, data); 1116 break; 1117 case SIOCSIFFLAGS: 1118 if (ifp->if_flags & IFF_UP) { 1119 txp_init(sc); 1120 } else { 1121 if (ifp->if_flags & IFF_RUNNING) 1122 txp_stop(sc); 1123 } 1124 break; 1125 case SIOCADDMULTI: 1126 case SIOCDELMULTI: 1127 /* 1128 * Multicast list has changed; set the hardware 1129 * filter accordingly. 1130 */ 1131 txp_set_filter(sc); 1132 error = 0; 1133 break; 1134 case SIOCGIFMEDIA: 1135 case SIOCSIFMEDIA: 1136 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command); 1137 break; 1138 default: 1139 error = EINVAL; 1140 break; 1141 } 1142 1143 (void)splx(s); 1144 1145 return(error); 1146} 1147 1148static int 1149txp_rxring_fill(sc) 1150 struct txp_softc *sc; 1151{ 1152 int i; 1153 struct ifnet *ifp; 1154 struct txp_swdesc *sd; 1155 1156 ifp = &sc->sc_arpcom.ac_if; 1157 1158 for (i = 0; i < RXBUF_ENTRIES; i++) { 1159 sd = sc->sc_rxbufs[i].rb_sd; 1160 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 1161 if (sd->sd_mbuf == NULL) 1162 return(ENOBUFS); 1163 1164 MCLGET(sd->sd_mbuf, M_DONTWAIT); 1165 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) { 1166 m_freem(sd->sd_mbuf); 1167 return(ENOBUFS); 1168 } 1169 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 1170 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 1171 1172 sc->sc_rxbufs[i].rb_paddrlo = 1173 vtophys(mtod(sd->sd_mbuf, vm_offset_t)); 1174 sc->sc_rxbufs[i].rb_paddrhi = 0; 1175 } 1176 1177 sc->sc_hostvar->hv_rx_buf_write_idx = (RXBUF_ENTRIES - 1) * 1178 sizeof(struct txp_rxbuf_desc); 1179 1180 return(0); 1181} 1182 1183static void 1184txp_rxring_empty(sc) 1185 struct txp_softc *sc; 1186{ 1187 int i; 1188 struct txp_swdesc *sd; 1189 1190 if (sc->sc_rxbufs == NULL) 1191 return; 1192 1193 for (i = 0; i < RXBUF_ENTRIES; i++) { 1194 if (&sc->sc_rxbufs[i] == NULL) 1195 continue; 1196 sd = sc->sc_rxbufs[i].rb_sd; 1197 if (sd == NULL) 1198 continue; 1199 if (sd->sd_mbuf != NULL) { 1200 m_freem(sd->sd_mbuf); 1201 sd->sd_mbuf = NULL; 1202 } 1203 } 1204 1205 return; 1206} 1207 1208static void 1209txp_init(xsc) 1210 void *xsc; 1211{ 1212 struct txp_softc *sc; 1213 struct ifnet *ifp; 1214 u_int16_t p1; 1215 u_int32_t p2; 1216 int s; 1217 1218 sc = xsc; 1219 ifp = &sc->sc_arpcom.ac_if; 1220 1221 if (ifp->if_flags & IFF_RUNNING) 1222 return; 1223 1224 txp_stop(sc); 1225 1226 s = splnet(); 1227 1228 txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 1229 NULL, NULL, NULL, 1); 1230 1231 /* Set station address. */ 1232 ((u_int8_t *)&p1)[1] = sc->sc_arpcom.ac_enaddr[0]; 1233 ((u_int8_t *)&p1)[0] = sc->sc_arpcom.ac_enaddr[1]; 1234 ((u_int8_t *)&p2)[3] = sc->sc_arpcom.ac_enaddr[2]; 1235 ((u_int8_t *)&p2)[2] = sc->sc_arpcom.ac_enaddr[3]; 1236 ((u_int8_t *)&p2)[1] = sc->sc_arpcom.ac_enaddr[4]; 1237 ((u_int8_t *)&p2)[0] = sc->sc_arpcom.ac_enaddr[5]; 1238 txp_command(sc, TXP_CMD_STATION_ADDRESS_WRITE, p1, p2, 0, 1239 NULL, NULL, NULL, 1); 1240 1241 txp_set_filter(sc); 1242 1243 txp_rxring_fill(sc); 1244 1245 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1246 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1247 1248 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF | 1249 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 1250 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 1251 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 1252 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 1253 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 1254 1255 ifp->if_flags |= IFF_RUNNING; 1256 ifp->if_flags &= ~IFF_OACTIVE; 1257 ifp->if_timer = 0; 1258 1259 sc->sc_tick = timeout(txp_tick, sc, hz); 1260 1261 splx(s); 1262} 1263 1264static void 1265txp_tick(vsc) 1266 void *vsc; 1267{ 1268 struct txp_softc *sc = vsc; 1269 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1270 struct txp_rsp_desc *rsp = NULL; 1271 struct txp_ext_desc *ext; 1272 int s; 1273 1274 s = splnet(); 1275 txp_rxbuf_reclaim(sc); 1276 1277 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0, 1278 &rsp, 1)) 1279 goto out; 1280 if (rsp->rsp_numdesc != 6) 1281 goto out; 1282 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0, 1283 NULL, NULL, NULL, 1)) 1284 goto out; 1285 ext = (struct txp_ext_desc *)(rsp + 1); 1286 1287 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 + 1288 ext[4].ext_1 + ext[4].ext_4; 1289 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 + 1290 ext[2].ext_1; 1291 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 + 1292 ext[1].ext_3; 1293 ifp->if_opackets += rsp->rsp_par2; 1294 ifp->if_ipackets += ext[2].ext_3; 1295 1296out: 1297 if (rsp != NULL) 1298 free(rsp, M_DEVBUF); 1299 1300 splx(s); 1301 sc->sc_tick = timeout(txp_tick, sc, hz); 1302 1303 return; 1304} 1305 1306static void 1307txp_start(ifp) 1308 struct ifnet *ifp; 1309{ 1310 struct txp_softc *sc = ifp->if_softc; 1311 struct txp_tx_ring *r = &sc->sc_txhir; 1312 struct txp_tx_desc *txd; 1313 struct txp_frag_desc *fxd; 1314 struct mbuf *m, *m0; 1315 struct txp_swdesc *sd; 1316 u_int32_t firstprod, firstcnt, prod, cnt; 1317 struct ifvlan *ifv; 1318 1319 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1320 return; 1321 1322 prod = r->r_prod; 1323 cnt = r->r_cnt; 1324 1325 while (1) { 1326 IF_DEQUEUE(&ifp->if_snd, m); 1327 if (m == NULL) 1328 break; 1329 1330 firstprod = prod; 1331 firstcnt = cnt; 1332 1333 sd = sc->sc_txd + prod; 1334 sd->sd_mbuf = m; 1335 1336 if ((TX_ENTRIES - cnt) < 4) 1337 goto oactive; 1338 1339 txd = r->r_desc + prod; 1340 1341 txd->tx_flags = TX_FLAGS_TYPE_DATA; 1342 txd->tx_numdesc = 0; 1343 txd->tx_addrlo = 0; 1344 txd->tx_addrhi = 0; 1345 txd->tx_totlen = 0; 1346 txd->tx_pflags = 0; 1347 1348 if (++prod == TX_ENTRIES) 1349 prod = 0; 1350 1351 if (++cnt >= (TX_ENTRIES - 4)) 1352 goto oactive; 1353 1354 if ((m->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1355 m->m_pkthdr.rcvif != NULL) { 1356 ifv = m->m_pkthdr.rcvif->if_softc; 1357 txd->tx_pflags = TX_PFLAGS_VLAN | 1358 (htons(ifv->ifv_tag) << TX_PFLAGS_VLANTAG_S); 1359 } 1360 1361 if (m->m_pkthdr.csum_flags & CSUM_IP) 1362 txd->tx_pflags |= TX_PFLAGS_IPCKSUM; 1363 1364#if 0 1365 if (m->m_pkthdr.csum_flags & CSUM_TCP) 1366 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM; 1367 if (m->m_pkthdr.csum_flags & CSUM_UDP) 1368 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM; 1369#endif 1370 1371 fxd = (struct txp_frag_desc *)(r->r_desc + prod); 1372 for (m0 = m; m0 != NULL; m0 = m0->m_next) { 1373 if (m0->m_len == 0) 1374 continue; 1375 if (++cnt >= (TX_ENTRIES - 4)) 1376 goto oactive; 1377 1378 txd->tx_numdesc++; 1379 1380 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG; 1381 fxd->frag_rsvd1 = 0; 1382 fxd->frag_len = m0->m_len; 1383 fxd->frag_addrlo = vtophys(mtod(m0, vm_offset_t)); 1384 fxd->frag_addrhi = 0; 1385 fxd->frag_rsvd2 = 0; 1386 1387 if (++prod == TX_ENTRIES) { 1388 fxd = (struct txp_frag_desc *)r->r_desc; 1389 prod = 0; 1390 } else 1391 fxd++; 1392 1393 } 1394 1395 ifp->if_timer = 5; 1396 1397 if (ifp->if_bpf) 1398 bpf_mtap(ifp, m); 1399 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod)); 1400 } 1401 1402 r->r_prod = prod; 1403 r->r_cnt = cnt; 1404 return; 1405 1406oactive: 1407 ifp->if_flags |= IFF_OACTIVE; 1408 r->r_prod = firstprod; 1409 r->r_cnt = firstcnt; 1410 IF_PREPEND(&ifp->if_snd, m); 1411 return; 1412} 1413 1414/* 1415 * Handle simple commands sent to the typhoon 1416 */ 1417static int 1418txp_command(sc, id, in1, in2, in3, out1, out2, out3, wait) 1419 struct txp_softc *sc; 1420 u_int16_t id, in1, *out1; 1421 u_int32_t in2, in3, *out2, *out3; 1422 int wait; 1423{ 1424 struct txp_rsp_desc *rsp = NULL; 1425 1426 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait)) 1427 return (-1); 1428 1429 if (!wait) 1430 return (0); 1431 1432 if (out1 != NULL) 1433 *out1 = rsp->rsp_par1; 1434 if (out2 != NULL) 1435 *out2 = rsp->rsp_par2; 1436 if (out3 != NULL) 1437 *out3 = rsp->rsp_par3; 1438 free(rsp, M_DEVBUF); 1439 return (0); 1440} 1441 1442static int 1443txp_command2(sc, id, in1, in2, in3, in_extp, in_extn, rspp, wait) 1444 struct txp_softc *sc; 1445 u_int16_t id, in1; 1446 u_int32_t in2, in3; 1447 struct txp_ext_desc *in_extp; 1448 u_int8_t in_extn; 1449 struct txp_rsp_desc **rspp; 1450 int wait; 1451{ 1452 struct txp_hostvar *hv = sc->sc_hostvar; 1453 struct txp_cmd_desc *cmd; 1454 struct txp_ext_desc *ext; 1455 u_int32_t idx, i; 1456 u_int16_t seq; 1457 1458 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) { 1459 device_printf(sc->sc_dev, "no free cmd descriptors\n"); 1460 return (-1); 1461 } 1462 1463 idx = sc->sc_cmdring.lastwrite; 1464 cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1465 bzero(cmd, sizeof(*cmd)); 1466 1467 cmd->cmd_numdesc = in_extn; 1468 cmd->cmd_seq = seq = sc->sc_seq++; 1469 cmd->cmd_id = id; 1470 cmd->cmd_par1 = in1; 1471 cmd->cmd_par2 = in2; 1472 cmd->cmd_par3 = in3; 1473 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD | 1474 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID; 1475 1476 idx += sizeof(struct txp_cmd_desc); 1477 if (idx == sc->sc_cmdring.size) 1478 idx = 0; 1479 1480 for (i = 0; i < in_extn; i++) { 1481 ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1482 bcopy(in_extp, ext, sizeof(struct txp_ext_desc)); 1483 in_extp++; 1484 idx += sizeof(struct txp_cmd_desc); 1485 if (idx == sc->sc_cmdring.size) 1486 idx = 0; 1487 } 1488 1489 sc->sc_cmdring.lastwrite = idx; 1490 1491 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite); 1492 1493 if (!wait) 1494 return (0); 1495 1496 for (i = 0; i < 10000; i++) { 1497 idx = hv->hv_resp_read_idx; 1498 if (idx != hv->hv_resp_write_idx) { 1499 *rspp = NULL; 1500 if (txp_response(sc, idx, id, seq, rspp)) 1501 return (-1); 1502 if (*rspp != NULL) 1503 break; 1504 } 1505 DELAY(50); 1506 } 1507 if (i == 1000 || (*rspp) == NULL) { 1508 device_printf(sc->sc_dev, "0x%x command failed\n", id); 1509 return (-1); 1510 } 1511 1512 return (0); 1513} 1514 1515static int 1516txp_response(sc, ridx, id, seq, rspp) 1517 struct txp_softc *sc; 1518 u_int32_t ridx; 1519 u_int16_t id; 1520 u_int16_t seq; 1521 struct txp_rsp_desc **rspp; 1522{ 1523 struct txp_hostvar *hv = sc->sc_hostvar; 1524 struct txp_rsp_desc *rsp; 1525 1526 while (ridx != hv->hv_resp_write_idx) { 1527 rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx); 1528 1529 if (id == rsp->rsp_id && rsp->rsp_seq == seq) { 1530 *rspp = (struct txp_rsp_desc *)malloc( 1531 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1), 1532 M_DEVBUF, M_NOWAIT); 1533 if ((*rspp) == NULL) 1534 return (-1); 1535 txp_rsp_fixup(sc, rsp, *rspp); 1536 return (0); 1537 } 1538 1539 if (rsp->rsp_flags & RSP_FLAGS_ERROR) { 1540 device_printf(sc->sc_dev, "response error!\n"); 1541 txp_rsp_fixup(sc, rsp, NULL); 1542 ridx = hv->hv_resp_read_idx; 1543 continue; 1544 } 1545 1546 switch (rsp->rsp_id) { 1547 case TXP_CMD_CYCLE_STATISTICS: 1548 case TXP_CMD_MEDIA_STATUS_READ: 1549 break; 1550 case TXP_CMD_HELLO_RESPONSE: 1551 device_printf(sc->sc_dev, "hello\n"); 1552 break; 1553 default: 1554 device_printf(sc->sc_dev, "unknown id(0x%x)\n", 1555 rsp->rsp_id); 1556 } 1557 1558 txp_rsp_fixup(sc, rsp, NULL); 1559 ridx = hv->hv_resp_read_idx; 1560 hv->hv_resp_read_idx = ridx; 1561 } 1562 1563 return (0); 1564} 1565 1566static void 1567txp_rsp_fixup(sc, rsp, dst) 1568 struct txp_softc *sc; 1569 struct txp_rsp_desc *rsp, *dst; 1570{ 1571 struct txp_rsp_desc *src = rsp; 1572 struct txp_hostvar *hv = sc->sc_hostvar; 1573 u_int32_t i, ridx; 1574 1575 ridx = hv->hv_resp_read_idx; 1576 1577 for (i = 0; i < rsp->rsp_numdesc + 1; i++) { 1578 if (dst != NULL) 1579 bcopy(src, dst++, sizeof(struct txp_rsp_desc)); 1580 ridx += sizeof(struct txp_rsp_desc); 1581 if (ridx == sc->sc_rspring.size) { 1582 src = sc->sc_rspring.base; 1583 ridx = 0; 1584 } else 1585 src++; 1586 sc->sc_rspring.lastwrite = hv->hv_resp_read_idx = ridx; 1587 } 1588 1589 hv->hv_resp_read_idx = ridx; 1590} 1591 1592static int 1593txp_cmd_desc_numfree(sc) 1594 struct txp_softc *sc; 1595{ 1596 struct txp_hostvar *hv = sc->sc_hostvar; 1597 struct txp_boot_record *br = sc->sc_boot; 1598 u_int32_t widx, ridx, nfree; 1599 1600 widx = sc->sc_cmdring.lastwrite; 1601 ridx = hv->hv_cmd_read_idx; 1602 1603 if (widx == ridx) { 1604 /* Ring is completely free */ 1605 nfree = br->br_cmd_siz - sizeof(struct txp_cmd_desc); 1606 } else { 1607 if (widx > ridx) 1608 nfree = br->br_cmd_siz - 1609 (widx - ridx + sizeof(struct txp_cmd_desc)); 1610 else 1611 nfree = ridx - widx - sizeof(struct txp_cmd_desc); 1612 } 1613 1614 return (nfree / sizeof(struct txp_cmd_desc)); 1615} 1616 1617static void 1618txp_stop(sc) 1619 struct txp_softc *sc; 1620{ 1621 struct ifnet *ifp; 1622 1623 ifp = &sc->sc_arpcom.ac_if; 1624 1625 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1626 1627 untimeout(txp_tick, sc, sc->sc_tick); 1628 1629 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1630 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1631 1632 txp_rxring_empty(sc); 1633 1634 return; 1635} 1636 1637static void 1638txp_watchdog(ifp) 1639 struct ifnet *ifp; 1640{ 1641 return; 1642} 1643 1644static int 1645txp_ifmedia_upd(ifp) 1646 struct ifnet *ifp; 1647{ 1648 struct txp_softc *sc = ifp->if_softc; 1649 struct ifmedia *ifm = &sc->sc_ifmedia; 1650 u_int16_t new_xcvr; 1651 1652 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1653 return (EINVAL); 1654 1655 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) { 1656 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1657 new_xcvr = TXP_XCVR_10_FDX; 1658 else 1659 new_xcvr = TXP_XCVR_10_HDX; 1660 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 1661 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1662 new_xcvr = TXP_XCVR_100_FDX; 1663 else 1664 new_xcvr = TXP_XCVR_100_HDX; 1665 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1666 new_xcvr = TXP_XCVR_AUTO; 1667 } else 1668 return (EINVAL); 1669 1670 /* nothing to do */ 1671 if (sc->sc_xcvr == new_xcvr) 1672 return (0); 1673 1674 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0, 1675 NULL, NULL, NULL, 0); 1676 sc->sc_xcvr = new_xcvr; 1677 1678 return (0); 1679} 1680 1681static void 1682txp_ifmedia_sts(ifp, ifmr) 1683 struct ifnet *ifp; 1684 struct ifmediareq *ifmr; 1685{ 1686 struct txp_softc *sc = ifp->if_softc; 1687 struct ifmedia *ifm = &sc->sc_ifmedia; 1688 u_int16_t bmsr, bmcr, anlpar; 1689 1690 ifmr->ifm_status = IFM_AVALID; 1691 ifmr->ifm_active = IFM_ETHER; 1692 1693 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1694 &bmsr, NULL, NULL, 1)) 1695 goto bail; 1696 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1697 &bmsr, NULL, NULL, 1)) 1698 goto bail; 1699 1700 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0, 1701 &bmcr, NULL, NULL, 1)) 1702 goto bail; 1703 1704 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0, 1705 &anlpar, NULL, NULL, 1)) 1706 goto bail; 1707 1708 if (bmsr & BMSR_LINK) 1709 ifmr->ifm_status |= IFM_ACTIVE; 1710 1711 if (bmcr & BMCR_ISO) { 1712 ifmr->ifm_active |= IFM_NONE; 1713 ifmr->ifm_status = 0; 1714 return; 1715 } 1716 1717 if (bmcr & BMCR_LOOP) 1718 ifmr->ifm_active |= IFM_LOOP; 1719 1720 if (bmcr & BMCR_AUTOEN) { 1721 if ((bmsr & BMSR_ACOMP) == 0) { 1722 ifmr->ifm_active |= IFM_NONE; 1723 return; 1724 } 1725 1726 if (anlpar & ANLPAR_T4) 1727 ifmr->ifm_active |= IFM_100_T4; 1728 else if (anlpar & ANLPAR_TX_FD) 1729 ifmr->ifm_active |= IFM_100_TX|IFM_FDX; 1730 else if (anlpar & ANLPAR_TX) 1731 ifmr->ifm_active |= IFM_100_TX; 1732 else if (anlpar & ANLPAR_10_FD) 1733 ifmr->ifm_active |= IFM_10_T|IFM_FDX; 1734 else if (anlpar & ANLPAR_10) 1735 ifmr->ifm_active |= IFM_10_T; 1736 else 1737 ifmr->ifm_active |= IFM_NONE; 1738 } else 1739 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 1740 return; 1741 1742bail: 1743 ifmr->ifm_active |= IFM_NONE; 1744 ifmr->ifm_status &= ~IFM_AVALID; 1745} 1746 1747#ifdef TXP_DEBUG 1748static void 1749txp_show_descriptor(d) 1750 void *d; 1751{ 1752 struct txp_cmd_desc *cmd = d; 1753 struct txp_rsp_desc *rsp = d; 1754 struct txp_tx_desc *txd = d; 1755 struct txp_frag_desc *frgd = d; 1756 1757 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) { 1758 case CMD_FLAGS_TYPE_CMD: 1759 /* command descriptor */ 1760 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1761 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq, 1762 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3); 1763 break; 1764 case CMD_FLAGS_TYPE_RESP: 1765 /* response descriptor */ 1766 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1767 rsp->rsp_flags, rsp->rsp_numdesc, rsp->rsp_id, rsp->rsp_seq, 1768 rsp->rsp_par1, rsp->rsp_par2, rsp->rsp_par3); 1769 break; 1770 case CMD_FLAGS_TYPE_DATA: 1771 /* data header (assuming tx for now) */ 1772 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]", 1773 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1774 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags); 1775 break; 1776 case CMD_FLAGS_TYPE_FRAG: 1777 /* fragment descriptor */ 1778 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]", 1779 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len, 1780 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2); 1781 break; 1782 default: 1783 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1784 cmd->cmd_flags & CMD_FLAGS_TYPE_M, 1785 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq, 1786 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3); 1787 break; 1788 } 1789} 1790#endif 1791 1792static void 1793txp_set_filter(sc) 1794 struct txp_softc *sc; 1795{ 1796 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1797 u_int32_t crc, carry, hashbit, hash[2]; 1798 u_int16_t filter; 1799 u_int8_t octet; 1800 int i, j, mcnt = 0; 1801 struct ifmultiaddr *ifma; 1802 char *enm; 1803 1804 if (ifp->if_flags & IFF_PROMISC) { 1805 filter = TXP_RXFILT_PROMISC; 1806 goto setit; 1807 } 1808 1809 filter = TXP_RXFILT_DIRECT; 1810 1811 if (ifp->if_flags & IFF_BROADCAST) 1812 filter |= TXP_RXFILT_BROADCAST; 1813 1814 if (ifp->if_flags & IFF_ALLMULTI) 1815 filter |= TXP_RXFILT_ALLMULTI; 1816 else { 1817 hash[0] = hash[1] = 0; 1818 1819 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1820 if (ifma->ifma_addr->sa_family != AF_LINK) 1821 continue; 1822 1823 enm = LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 1824 mcnt++; 1825 crc = 0xffffffff; 1826 1827 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1828 octet = enm[i]; 1829 for (j = 0; j < 8; j++) { 1830 carry = ((crc & 0x80000000) ? 1 : 0) ^ 1831 (octet & 1); 1832 crc <<= 1; 1833 octet >>= 1; 1834 if (carry) 1835 crc = (crc ^ TXP_POLYNOMIAL) | 1836 carry; 1837 } 1838 } 1839 hashbit = (u_int16_t)(crc & (64 - 1)); 1840 hash[hashbit / 32] |= (1 << hashbit % 32); 1841 } 1842 1843 if (mcnt > 0) { 1844 filter |= TXP_RXFILT_HASHMULTI; 1845 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE, 1846 2, hash[0], hash[1], NULL, NULL, NULL, 0); 1847 } 1848 } 1849 1850setit: 1851 1852 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0, 1853 NULL, NULL, NULL, 1); 1854 1855 return; 1856} 1857 1858static void 1859txp_capabilities(sc) 1860 struct txp_softc *sc; 1861{ 1862 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1863 struct txp_rsp_desc *rsp = NULL; 1864 struct txp_ext_desc *ext; 1865 1866 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1)) 1867 goto out; 1868 1869 if (rsp->rsp_numdesc != 1) 1870 goto out; 1871 ext = (struct txp_ext_desc *)(rsp + 1); 1872 1873 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK; 1874 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK; 1875 ifp->if_capabilities = 0; 1876 1877 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) { 1878 sc->sc_tx_capability |= OFFLOAD_VLAN; 1879 sc->sc_rx_capability |= OFFLOAD_VLAN; 1880 } 1881 1882#if 0 1883 /* not ready yet */ 1884 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) { 1885 sc->sc_tx_capability |= OFFLOAD_IPSEC; 1886 sc->sc_rx_capability |= OFFLOAD_IPSEC; 1887 ifp->if_capabilities |= IFCAP_IPSEC; 1888 } 1889#endif 1890 1891 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) { 1892 sc->sc_tx_capability |= OFFLOAD_IPCKSUM; 1893 sc->sc_rx_capability |= OFFLOAD_IPCKSUM; 1894 ifp->if_capabilities |= IFCAP_HWCSUM; 1895 ifp->if_hwassist |= CSUM_IP; 1896 } 1897 1898 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) { 1899#if 0 1900 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM; 1901#endif 1902 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM; 1903 ifp->if_capabilities |= IFCAP_HWCSUM; 1904 } 1905 1906 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) { 1907#if 0 1908 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM; 1909#endif 1910 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM; 1911 ifp->if_capabilities |= IFCAP_HWCSUM; 1912 } 1913 ifp->if_capenable = ifp->if_capabilities; 1914 1915 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0, 1916 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1)) 1917 goto out; 1918 1919out: 1920 if (rsp != NULL) 1921 free(rsp, M_DEVBUF); 1922 1923 return; 1924} 1925