if_txp.c revision 92739
1/* $OpenBSD: if_txp.c,v 1.48 2001/06/27 06:34:50 kjc Exp $ */ 2/* $FreeBSD: head/sys/dev/txp/if_txp.c 92739 2002-03-20 02:08:01Z alfred $ */ 3 4/* 5 * Copyright (c) 2001 6 * Jason L. Wright <jason@thought.net>, Theo de Raadt, and 7 * Aaron Campbell <aaron@monkey.org>. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Jason L. Wright, 20 * Theo de Raadt and Aaron Campbell. 21 * 4. Neither the name of the author nor the names of any co-contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 35 * THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38/* 39 * Driver for 3c990 (Typhoon) Ethernet ASIC 40 */ 41 42#include <sys/param.h> 43#include <sys/systm.h> 44#include <sys/sockio.h> 45#include <sys/mbuf.h> 46#include <sys/malloc.h> 47#include <sys/kernel.h> 48#include <sys/socket.h> 49 50#include <net/if.h> 51#include <net/if_arp.h> 52#include <net/ethernet.h> 53#include <net/if_dl.h> 54#include <net/if_types.h> 55#include <net/if_vlan_var.h> 56 57#include <netinet/in.h> 58#include <netinet/in_systm.h> 59#include <netinet/in_var.h> 60#include <netinet/ip.h> 61#include <netinet/if_ether.h> 62#include <machine/in_cksum.h> 63 64#include <net/if_media.h> 65 66#include <net/bpf.h> 67 68#include <vm/vm.h> /* for vtophys */ 69#include <vm/pmap.h> /* for vtophys */ 70#include <machine/clock.h> /* for DELAY */ 71#include <machine/bus_pio.h> 72#include <machine/bus_memio.h> 73#include <machine/bus.h> 74#include <machine/resource.h> 75#include <sys/bus.h> 76#include <sys/rman.h> 77 78#include <dev/mii/mii.h> 79#include <dev/mii/miivar.h> 80#include <dev/pci/pcireg.h> 81#include <dev/pci/pcivar.h> 82 83#define TXP_USEIOSPACE 84#define __STRICT_ALIGNMENT 85 86#include <dev/txp/if_txpreg.h> 87#include <dev/txp/3c990img.h> 88 89#ifndef lint 90static const char rcsid[] = 91 "$FreeBSD: head/sys/dev/txp/if_txp.c 92739 2002-03-20 02:08:01Z alfred $"; 92#endif 93 94/* 95 * Various supported device vendors/types and their names. 96 */ 97static struct txp_type txp_devs[] = { 98 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_TX_95, 99 "3Com 3cR990-TX-95 Etherlink with 3XP Processor" }, 100 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_TX_97, 101 "3Com 3cR990-TX-97 Etherlink with 3XP Processor" }, 102 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990B_TXM, 103 "3Com 3cR990B-TXM Etherlink with 3XP Processor" }, 104 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_SRV_95, 105 "3Com 3cR990-SRV-95 Etherlink Server with 3XP Processor" }, 106 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_SRV_97, 107 "3Com 3cR990-SRV-97 Etherlink Server with 3XP Processor" }, 108 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990B_SRV, 109 "3Com 3cR990B-SRV Etherlink Server with 3XP Processor" }, 110 { 0, 0, NULL } 111}; 112 113static int txp_probe (device_t); 114static int txp_attach (device_t); 115static int txp_detach (device_t); 116static void txp_intr (void *); 117static void txp_tick (void *); 118static int txp_shutdown (device_t); 119static int txp_ioctl (struct ifnet *, u_long, caddr_t); 120static void txp_start (struct ifnet *); 121static void txp_stop (struct txp_softc *); 122static void txp_init (void *); 123static void txp_watchdog (struct ifnet *); 124 125static void txp_release_resources(struct txp_softc *); 126static int txp_chip_init(struct txp_softc *); 127static int txp_reset_adapter(struct txp_softc *); 128static int txp_download_fw(struct txp_softc *); 129static int txp_download_fw_wait(struct txp_softc *); 130static int txp_download_fw_section (struct txp_softc *, 131 struct txp_fw_section_header *, int); 132static int txp_alloc_rings(struct txp_softc *); 133static int txp_rxring_fill(struct txp_softc *); 134static void txp_rxring_empty(struct txp_softc *); 135static void txp_set_filter(struct txp_softc *); 136 137static int txp_cmd_desc_numfree(struct txp_softc *); 138static int txp_command (struct txp_softc *, u_int16_t, u_int16_t, u_int32_t, 139 u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int); 140static int txp_command2 (struct txp_softc *, u_int16_t, u_int16_t, 141 u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t, 142 struct txp_rsp_desc **, int); 143static int txp_response (struct txp_softc *, u_int32_t, u_int16_t, u_int16_t, 144 struct txp_rsp_desc **); 145static void txp_rsp_fixup (struct txp_softc *, struct txp_rsp_desc *, 146 struct txp_rsp_desc *); 147static void txp_capabilities(struct txp_softc *); 148 149static void txp_ifmedia_sts(struct ifnet *, struct ifmediareq *); 150static int txp_ifmedia_upd(struct ifnet *); 151#ifdef TXP_DEBUG 152static void txp_show_descriptor(void *); 153#endif 154static void txp_tx_reclaim(struct txp_softc *, struct txp_tx_ring *); 155static void txp_rxbuf_reclaim(struct txp_softc *); 156static void txp_rx_reclaim(struct txp_softc *, struct txp_rx_ring *); 157 158#ifdef TXP_USEIOSPACE 159#define TXP_RES SYS_RES_IOPORT 160#define TXP_RID TXP_PCI_LOIO 161#else 162#define TXP_RES SYS_RES_MEMORY 163#define TXP_RID TXP_PCI_LOMEM 164#endif 165 166static device_method_t txp_methods[] = { 167 /* Device interface */ 168 DEVMETHOD(device_probe, txp_probe), 169 DEVMETHOD(device_attach, txp_attach), 170 DEVMETHOD(device_detach, txp_detach), 171 DEVMETHOD(device_shutdown, txp_shutdown), 172 { 0, 0 } 173}; 174 175static driver_t txp_driver = { 176 "txp", 177 txp_methods, 178 sizeof(struct txp_softc) 179}; 180 181static devclass_t txp_devclass; 182 183DRIVER_MODULE(if_txp, pci, txp_driver, txp_devclass, 0, 0); 184 185static int 186txp_probe(dev) 187 device_t dev; 188{ 189 struct txp_type *t; 190 191 t = txp_devs; 192 193 while(t->txp_name != NULL) { 194 if ((pci_get_vendor(dev) == t->txp_vid) && 195 (pci_get_device(dev) == t->txp_did)) { 196 device_set_desc(dev, t->txp_name); 197 return(0); 198 } 199 t++; 200 } 201 202 return(ENXIO); 203} 204 205static int 206txp_attach(dev) 207 device_t dev; 208{ 209 struct txp_softc *sc; 210 struct ifnet *ifp; 211 u_int32_t command; 212 u_int16_t p1; 213 u_int32_t p2; 214 int unit, error = 0, rid; 215 216 sc = device_get_softc(dev); 217 unit = device_get_unit(dev); 218 sc->sc_dev = dev; 219 sc->sc_cold = 1; 220 221 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_DEF|MTX_RECURSE); 222 223 /* 224 * Handle power management nonsense. 225 */ 226 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 227 u_int32_t iobase, membase, irq; 228 229 /* Save important PCI config data. */ 230 iobase = pci_read_config(dev, TXP_PCI_LOIO, 4); 231 membase = pci_read_config(dev, TXP_PCI_LOMEM, 4); 232 irq = pci_read_config(dev, TXP_PCI_INTLINE, 4); 233 234 /* Reset the power state. */ 235 device_printf(dev, "chip is in D%d power mode " 236 "-- setting to D0\n", pci_get_powerstate(dev)); 237 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 238 239 /* Restore PCI config data. */ 240 pci_write_config(dev, TXP_PCI_LOIO, iobase, 4); 241 pci_write_config(dev, TXP_PCI_LOMEM, membase, 4); 242 pci_write_config(dev, TXP_PCI_INTLINE, irq, 4); 243 } 244 245 /* 246 * Map control/status registers. 247 */ 248 pci_enable_busmaster(dev); 249 pci_enable_io(dev, SYS_RES_IOPORT); 250 pci_enable_io(dev, SYS_RES_MEMORY); 251 command = pci_read_config(dev, PCIR_COMMAND, 4); 252 253#ifdef TXP_USEIOSPACE 254 if (!(command & PCIM_CMD_PORTEN)) { 255 device_printf(dev, "failed to enable I/O ports!\n"); 256 error = ENXIO; 257 goto fail; 258 } 259#else 260 if (!(command & PCIM_CMD_MEMEN)) { 261 device_printf(dev, "failed to enable memory mapping!\n"); 262 error = ENXIO; 263 goto fail; 264 } 265#endif 266 267 rid = TXP_RID; 268 sc->sc_res = bus_alloc_resource(dev, TXP_RES, &rid, 269 0, ~0, 1, RF_ACTIVE); 270 271 if (sc->sc_res == NULL) { 272 device_printf(dev, "couldn't map ports/memory\n"); 273 error = ENXIO; 274 goto fail; 275 } 276 277 sc->sc_bt = rman_get_bustag(sc->sc_res); 278 sc->sc_bh = rman_get_bushandle(sc->sc_res); 279 280 /* Allocate interrupt */ 281 rid = 0; 282 sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 283 RF_SHAREABLE | RF_ACTIVE); 284 285 if (sc->sc_irq == NULL) { 286 device_printf(dev, "couldn't map interrupt\n"); 287 txp_release_resources(sc); 288 error = ENXIO; 289 goto fail; 290 } 291 292 error = bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET, 293 txp_intr, sc, &sc->sc_intrhand); 294 295 if (error) { 296 txp_release_resources(sc); 297 device_printf(dev, "couldn't set up irq\n"); 298 goto fail; 299 } 300 301 if (txp_chip_init(sc)) { 302 txp_release_resources(sc); 303 goto fail; 304 } 305 306 sc->sc_fwbuf = contigmalloc(32768, M_DEVBUF, 307 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 308 error = txp_download_fw(sc); 309 contigfree(sc->sc_fwbuf, 32768, M_DEVBUF); 310 sc->sc_fwbuf = NULL; 311 312 if (error) { 313 txp_release_resources(sc); 314 goto fail; 315 } 316 317 sc->sc_ldata = contigmalloc(sizeof(struct txp_ldata), M_DEVBUF, 318 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 319 bzero(sc->sc_ldata, sizeof(struct txp_ldata)); 320 321 if (txp_alloc_rings(sc)) { 322 txp_release_resources(sc); 323 goto fail; 324 } 325 326 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 327 NULL, NULL, NULL, 1)) { 328 txp_release_resources(sc); 329 goto fail; 330 } 331 332 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0, 333 &p1, &p2, NULL, 1)) { 334 txp_release_resources(sc); 335 goto fail; 336 } 337 338 txp_set_filter(sc); 339 340 sc->sc_arpcom.ac_enaddr[0] = ((u_int8_t *)&p1)[1]; 341 sc->sc_arpcom.ac_enaddr[1] = ((u_int8_t *)&p1)[0]; 342 sc->sc_arpcom.ac_enaddr[2] = ((u_int8_t *)&p2)[3]; 343 sc->sc_arpcom.ac_enaddr[3] = ((u_int8_t *)&p2)[2]; 344 sc->sc_arpcom.ac_enaddr[4] = ((u_int8_t *)&p2)[1]; 345 sc->sc_arpcom.ac_enaddr[5] = ((u_int8_t *)&p2)[0]; 346 347 printf("txp%d: Ethernet address %6D\n", unit, 348 sc->sc_arpcom.ac_enaddr, ":"); 349 350 sc->sc_cold = 0; 351 352 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts); 353 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 354 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 355 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 356 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 357 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL); 358 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 359 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 360 361 sc->sc_xcvr = TXP_XCVR_AUTO; 362 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0, 363 NULL, NULL, NULL, 0); 364 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 365 366 ifp = &sc->sc_arpcom.ac_if; 367 ifp->if_softc = sc; 368 ifp->if_unit = unit; 369 ifp->if_name = "txp"; 370 ifp->if_mtu = ETHERMTU; 371 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 372 ifp->if_ioctl = txp_ioctl; 373 ifp->if_output = ether_output; 374 ifp->if_start = txp_start; 375 ifp->if_watchdog = txp_watchdog; 376 ifp->if_init = txp_init; 377 ifp->if_baudrate = 100000000; 378 ifp->if_snd.ifq_maxlen = TX_ENTRIES; 379 ifp->if_hwassist = 0; 380 txp_capabilities(sc); 381 382 /* 383 * Attach us everywhere 384 */ 385 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 386 callout_handle_init(&sc->sc_tick); 387 return(0); 388 389fail: 390 txp_release_resources(sc); 391 mtx_destroy(&sc->sc_mtx); 392 return(error); 393} 394 395static int 396txp_detach(dev) 397 device_t dev; 398{ 399 struct txp_softc *sc; 400 struct ifnet *ifp; 401 int i; 402 403 sc = device_get_softc(dev); 404 ifp = &sc->sc_arpcom.ac_if; 405 406 txp_stop(sc); 407 txp_shutdown(dev); 408 409 ifmedia_removeall(&sc->sc_ifmedia); 410 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 411 412 for (i = 0; i < RXBUF_ENTRIES; i++) 413 free(sc->sc_rxbufs[i].rb_sd, M_DEVBUF); 414 415 txp_release_resources(sc); 416 417 mtx_destroy(&sc->sc_mtx); 418 return(0); 419} 420 421static void 422txp_release_resources(sc) 423 struct txp_softc *sc; 424{ 425 device_t dev; 426 427 dev = sc->sc_dev; 428 429 if (sc->sc_intrhand != NULL) 430 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand); 431 432 if (sc->sc_irq != NULL) 433 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 434 435 if (sc->sc_res != NULL) 436 bus_release_resource(dev, TXP_RES, TXP_RID, sc->sc_res); 437 438 if (sc->sc_ldata != NULL) 439 contigfree(sc->sc_ldata, sizeof(struct txp_ldata), M_DEVBUF); 440 441 return; 442} 443 444static int 445txp_chip_init(sc) 446 struct txp_softc *sc; 447{ 448 /* disable interrupts */ 449 WRITE_REG(sc, TXP_IER, 0); 450 WRITE_REG(sc, TXP_IMR, 451 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 452 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 453 TXP_INT_LATCH); 454 455 /* ack all interrupts */ 456 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 457 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 458 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 459 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 460 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 461 462 if (txp_reset_adapter(sc)) 463 return (-1); 464 465 /* disable interrupts */ 466 WRITE_REG(sc, TXP_IER, 0); 467 WRITE_REG(sc, TXP_IMR, 468 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 469 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 470 TXP_INT_LATCH); 471 472 /* ack all interrupts */ 473 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 474 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 475 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 476 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 477 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 478 479 return (0); 480} 481 482static int 483txp_reset_adapter(sc) 484 struct txp_softc *sc; 485{ 486 u_int32_t r; 487 int i; 488 489 r = 0; 490 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL); 491 DELAY(1000); 492 WRITE_REG(sc, TXP_SRR, 0); 493 494 /* Should wait max 6 seconds */ 495 for (i = 0; i < 6000; i++) { 496 r = READ_REG(sc, TXP_A2H_0); 497 if (r == STAT_WAITING_FOR_HOST_REQUEST) 498 break; 499 DELAY(1000); 500 } 501 502 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 503 device_printf(sc->sc_dev, "reset hung\n"); 504 return (-1); 505 } 506 507 return (0); 508} 509 510static int 511txp_download_fw(sc) 512 struct txp_softc *sc; 513{ 514 struct txp_fw_file_header *fileheader; 515 struct txp_fw_section_header *secthead; 516 int sect; 517 u_int32_t r, i, ier, imr; 518 519 r = 0; 520 ier = READ_REG(sc, TXP_IER); 521 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0); 522 523 imr = READ_REG(sc, TXP_IMR); 524 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0); 525 526 for (i = 0; i < 10000; i++) { 527 r = READ_REG(sc, TXP_A2H_0); 528 if (r == STAT_WAITING_FOR_HOST_REQUEST) 529 break; 530 DELAY(50); 531 } 532 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 533 device_printf(sc->sc_dev, "not waiting for host request\n"); 534 return (-1); 535 } 536 537 /* Ack the status */ 538 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 539 540 fileheader = (struct txp_fw_file_header *)tc990image; 541 if (bcmp("TYPHOON", fileheader->magicid, sizeof(fileheader->magicid))) { 542 device_printf(sc->sc_dev, "fw invalid magic\n"); 543 return (-1); 544 } 545 546 /* Tell boot firmware to get ready for image */ 547 WRITE_REG(sc, TXP_H2A_1, fileheader->addr); 548 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE); 549 550 if (txp_download_fw_wait(sc)) { 551 device_printf(sc->sc_dev, "fw wait failed, initial\n"); 552 return (-1); 553 } 554 555 secthead = (struct txp_fw_section_header *)(((u_int8_t *)tc990image) + 556 sizeof(struct txp_fw_file_header)); 557 558 for (sect = 0; sect < fileheader->nsections; sect++) { 559 if (txp_download_fw_section(sc, secthead, sect)) 560 return (-1); 561 secthead = (struct txp_fw_section_header *) 562 (((u_int8_t *)secthead) + secthead->nbytes + 563 sizeof(*secthead)); 564 } 565 566 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE); 567 568 for (i = 0; i < 10000; i++) { 569 r = READ_REG(sc, TXP_A2H_0); 570 if (r == STAT_WAITING_FOR_BOOT) 571 break; 572 DELAY(50); 573 } 574 if (r != STAT_WAITING_FOR_BOOT) { 575 device_printf(sc->sc_dev, "not waiting for boot\n"); 576 return (-1); 577 } 578 579 WRITE_REG(sc, TXP_IER, ier); 580 WRITE_REG(sc, TXP_IMR, imr); 581 582 return (0); 583} 584 585static int 586txp_download_fw_wait(sc) 587 struct txp_softc *sc; 588{ 589 u_int32_t i, r; 590 591 r = 0; 592 for (i = 0; i < 10000; i++) { 593 r = READ_REG(sc, TXP_ISR); 594 if (r & TXP_INT_A2H_0) 595 break; 596 DELAY(50); 597 } 598 599 if (!(r & TXP_INT_A2H_0)) { 600 device_printf(sc->sc_dev, "fw wait failed comm0\n"); 601 return (-1); 602 } 603 604 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 605 606 r = READ_REG(sc, TXP_A2H_0); 607 if (r != STAT_WAITING_FOR_SEGMENT) { 608 device_printf(sc->sc_dev, "fw not waiting for segment\n"); 609 return (-1); 610 } 611 return (0); 612} 613 614static int 615txp_download_fw_section(sc, sect, sectnum) 616 struct txp_softc *sc; 617 struct txp_fw_section_header *sect; 618 int sectnum; 619{ 620 vm_offset_t dma; 621 int rseg, err = 0; 622 struct mbuf m; 623 u_int16_t csum; 624 625 /* Skip zero length sections */ 626 if (sect->nbytes == 0) 627 return (0); 628 629 /* Make sure we aren't past the end of the image */ 630 rseg = ((u_int8_t *)sect) - ((u_int8_t *)tc990image); 631 if (rseg >= sizeof(tc990image)) { 632 device_printf(sc->sc_dev, "fw invalid section address, " 633 "section %d\n", sectnum); 634 return (-1); 635 } 636 637 /* Make sure this section doesn't go past the end */ 638 rseg += sect->nbytes; 639 if (rseg >= sizeof(tc990image)) { 640 device_printf(sc->sc_dev, "fw truncated section %d\n", 641 sectnum); 642 return (-1); 643 } 644 645 bcopy(((u_int8_t *)sect) + sizeof(*sect), sc->sc_fwbuf, sect->nbytes); 646 dma = vtophys(sc->sc_fwbuf); 647 648 /* 649 * dummy up mbuf and verify section checksum 650 */ 651 m.m_type = MT_DATA; 652 m.m_next = m.m_nextpkt = NULL; 653 m.m_len = sect->nbytes; 654 m.m_data = sc->sc_fwbuf; 655 m.m_flags = 0; 656 csum = in_cksum(&m, sect->nbytes); 657 if (csum != sect->cksum) { 658 device_printf(sc->sc_dev, "fw section %d, bad " 659 "cksum (expected 0x%x got 0x%x)\n", 660 sectnum, sect->cksum, csum); 661 err = -1; 662 goto bail; 663 } 664 665 WRITE_REG(sc, TXP_H2A_1, sect->nbytes); 666 WRITE_REG(sc, TXP_H2A_2, sect->cksum); 667 WRITE_REG(sc, TXP_H2A_3, sect->addr); 668 WRITE_REG(sc, TXP_H2A_4, 0); 669 WRITE_REG(sc, TXP_H2A_5, dma & 0xffffffff); 670 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE); 671 672 if (txp_download_fw_wait(sc)) { 673 device_printf(sc->sc_dev, "fw wait failed, " 674 "section %d\n", sectnum); 675 err = -1; 676 } 677 678bail: 679 return (err); 680} 681 682static void 683txp_intr(vsc) 684 void *vsc; 685{ 686 struct txp_softc *sc = vsc; 687 struct txp_hostvar *hv = sc->sc_hostvar; 688 u_int32_t isr; 689 690 /* mask all interrupts */ 691 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF | 692 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 693 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 694 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 695 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 696 697 isr = READ_REG(sc, TXP_ISR); 698 while (isr) { 699 WRITE_REG(sc, TXP_ISR, isr); 700 701 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff)) 702 txp_rx_reclaim(sc, &sc->sc_rxhir); 703 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff)) 704 txp_rx_reclaim(sc, &sc->sc_rxlor); 705 706 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx) 707 txp_rxbuf_reclaim(sc); 708 709 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons != 710 TXP_OFFSET2IDX(*(sc->sc_txhir.r_off)))) 711 txp_tx_reclaim(sc, &sc->sc_txhir); 712 713 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons != 714 TXP_OFFSET2IDX(*(sc->sc_txlor.r_off)))) 715 txp_tx_reclaim(sc, &sc->sc_txlor); 716 717 isr = READ_REG(sc, TXP_ISR); 718 } 719 720 /* unmask all interrupts */ 721 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 722 723 txp_start(&sc->sc_arpcom.ac_if); 724 725 return; 726} 727 728static void 729txp_rx_reclaim(sc, r) 730 struct txp_softc *sc; 731 struct txp_rx_ring *r; 732{ 733 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 734 struct txp_rx_desc *rxd; 735 struct mbuf *m; 736 struct txp_swdesc *sd = NULL; 737 u_int32_t roff, woff; 738 struct ether_header *eh = NULL; 739 740 roff = *r->r_roff; 741 woff = *r->r_woff; 742 rxd = r->r_desc + (roff / sizeof(struct txp_rx_desc)); 743 744 while (roff != woff) { 745 746 if (rxd->rx_flags & RX_FLAGS_ERROR) { 747 device_printf(sc->sc_dev, "error 0x%x\n", 748 rxd->rx_stat); 749 ifp->if_ierrors++; 750 goto next; 751 } 752 753 /* retrieve stashed pointer */ 754 sd = rxd->rx_sd; 755 756 m = sd->sd_mbuf; 757 sd->sd_mbuf = NULL; 758 759 m->m_pkthdr.len = m->m_len = rxd->rx_len; 760 761#ifdef __STRICT_ALIGNMENT 762 { 763 /* 764 * XXX Nice chip, except it won't accept "off by 2" 765 * buffers, so we're force to copy. Supposedly 766 * this will be fixed in a newer firmware rev 767 * and this will be temporary. 768 */ 769 struct mbuf *mnew; 770 771 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 772 if (mnew == NULL) { 773 m_freem(m); 774 goto next; 775 } 776 if (m->m_len > (MHLEN - 2)) { 777 MCLGET(mnew, M_DONTWAIT); 778 if (!(mnew->m_flags & M_EXT)) { 779 m_freem(mnew); 780 m_freem(m); 781 goto next; 782 } 783 } 784 mnew->m_pkthdr.rcvif = ifp; 785 m_adj(mnew, 2); 786 mnew->m_pkthdr.len = mnew->m_len = m->m_len; 787 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, caddr_t)); 788 m_freem(m); 789 m = mnew; 790 } 791#endif 792 793 if (rxd->rx_stat & RX_STAT_IPCKSUMBAD) 794 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 795 else if (rxd->rx_stat & RX_STAT_IPCKSUMGOOD) 796 m->m_pkthdr.csum_flags |= 797 CSUM_IP_CHECKED|CSUM_IP_VALID; 798 799 if ((rxd->rx_stat & RX_STAT_TCPCKSUMGOOD) || 800 (rxd->rx_stat & RX_STAT_UDPCKSUMGOOD)) { 801 m->m_pkthdr.csum_flags |= 802 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 803 m->m_pkthdr.csum_data = 0xffff; 804 } 805 806 eh = mtod(m, struct ether_header *); 807 /* Remove header from mbuf and pass it on. */ 808 m_adj(m, sizeof(struct ether_header)); 809 810 if (rxd->rx_stat & RX_STAT_VLAN) { 811 VLAN_INPUT_TAG(eh, m, htons(rxd->rx_vlan >> 16)); 812 goto next; 813 } 814 815 ether_input(ifp, eh, m); 816 817next: 818 819 roff += sizeof(struct txp_rx_desc); 820 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) { 821 roff = 0; 822 rxd = r->r_desc; 823 } else 824 rxd++; 825 woff = *r->r_woff; 826 } 827 828 *r->r_roff = woff; 829 830 return; 831} 832 833static void 834txp_rxbuf_reclaim(sc) 835 struct txp_softc *sc; 836{ 837 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 838 struct txp_hostvar *hv = sc->sc_hostvar; 839 struct txp_rxbuf_desc *rbd; 840 struct txp_swdesc *sd; 841 u_int32_t i; 842 843 if (!(ifp->if_flags & IFF_RUNNING)) 844 return; 845 846 i = sc->sc_rxbufprod; 847 rbd = sc->sc_rxbufs + i; 848 849 while (1) { 850 sd = rbd->rb_sd; 851 if (sd->sd_mbuf != NULL) 852 break; 853 854 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 855 if (sd->sd_mbuf == NULL) 856 goto err_sd; 857 858 MCLGET(sd->sd_mbuf, M_DONTWAIT); 859 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) 860 goto err_mbuf; 861 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 862 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 863 864 rbd->rb_paddrlo = vtophys(mtod(sd->sd_mbuf, vm_offset_t)) 865 & 0xffffffff; 866 rbd->rb_paddrhi = 0; 867 868 hv->hv_rx_buf_write_idx = TXP_IDX2OFFSET(i); 869 870 if (++i == RXBUF_ENTRIES) { 871 i = 0; 872 rbd = sc->sc_rxbufs; 873 } else 874 rbd++; 875 } 876 877 sc->sc_rxbufprod = i; 878 879 return; 880 881err_mbuf: 882 m_freem(sd->sd_mbuf); 883err_sd: 884 free(sd, M_DEVBUF); 885} 886 887/* 888 * Reclaim mbufs and entries from a transmit ring. 889 */ 890static void 891txp_tx_reclaim(sc, r) 892 struct txp_softc *sc; 893 struct txp_tx_ring *r; 894{ 895 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 896 u_int32_t idx = TXP_OFFSET2IDX(*(r->r_off)); 897 u_int32_t cons = r->r_cons, cnt = r->r_cnt; 898 struct txp_tx_desc *txd = r->r_desc + cons; 899 struct txp_swdesc *sd = sc->sc_txd + cons; 900 struct mbuf *m; 901 902 while (cons != idx) { 903 if (cnt == 0) 904 break; 905 906 if ((txd->tx_flags & TX_FLAGS_TYPE_M) == 907 TX_FLAGS_TYPE_DATA) { 908 m = sd->sd_mbuf; 909 if (m != NULL) { 910 m_freem(m); 911 txd->tx_addrlo = 0; 912 txd->tx_addrhi = 0; 913 ifp->if_opackets++; 914 } 915 } 916 ifp->if_flags &= ~IFF_OACTIVE; 917 918 if (++cons == TX_ENTRIES) { 919 txd = r->r_desc; 920 cons = 0; 921 sd = sc->sc_txd; 922 } else { 923 txd++; 924 sd++; 925 } 926 927 cnt--; 928 } 929 930 r->r_cons = cons; 931 r->r_cnt = cnt; 932 if (cnt == 0) 933 ifp->if_timer = 0; 934} 935 936static int 937txp_shutdown(dev) 938 device_t dev; 939{ 940 struct txp_softc *sc; 941 942 sc = device_get_softc(dev); 943 944 /* mask all interrupts */ 945 WRITE_REG(sc, TXP_IMR, 946 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 947 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 948 TXP_INT_LATCH); 949 950 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 951 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 952 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0); 953 954 return(0); 955} 956 957static int 958txp_alloc_rings(sc) 959 struct txp_softc *sc; 960{ 961 struct txp_boot_record *boot; 962 struct txp_ldata *ld; 963 u_int32_t r; 964 int i; 965 966 r = 0; 967 ld = sc->sc_ldata; 968 boot = &ld->txp_boot; 969 970 /* boot record */ 971 sc->sc_boot = boot; 972 973 /* host variables */ 974 bzero(&ld->txp_hostvar, sizeof(struct txp_hostvar)); 975 boot->br_hostvar_lo = vtophys(&ld->txp_hostvar); 976 boot->br_hostvar_hi = 0; 977 sc->sc_hostvar = (struct txp_hostvar *)&ld->txp_hostvar; 978 979 /* hi priority tx ring */ 980 boot->br_txhipri_lo = vtophys(&ld->txp_txhiring);; 981 boot->br_txhipri_hi = 0; 982 boot->br_txhipri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc); 983 sc->sc_txhir.r_reg = TXP_H2A_1; 984 sc->sc_txhir.r_desc = (struct txp_tx_desc *)&ld->txp_txhiring; 985 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0; 986 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx; 987 988 /* lo priority tx ring */ 989 boot->br_txlopri_lo = vtophys(&ld->txp_txloring); 990 boot->br_txlopri_hi = 0; 991 boot->br_txlopri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc); 992 sc->sc_txlor.r_reg = TXP_H2A_3; 993 sc->sc_txlor.r_desc = (struct txp_tx_desc *)&ld->txp_txloring; 994 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0; 995 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx; 996 997 /* high priority rx ring */ 998 boot->br_rxhipri_lo = vtophys(&ld->txp_rxhiring); 999 boot->br_rxhipri_hi = 0; 1000 boot->br_rxhipri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc); 1001 sc->sc_rxhir.r_desc = (struct txp_rx_desc *)&ld->txp_rxhiring; 1002 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx; 1003 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx; 1004 1005 /* low priority rx ring */ 1006 boot->br_rxlopri_lo = vtophys(&ld->txp_rxloring); 1007 boot->br_rxlopri_hi = 0; 1008 boot->br_rxlopri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc); 1009 sc->sc_rxlor.r_desc = (struct txp_rx_desc *)&ld->txp_rxloring; 1010 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx; 1011 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx; 1012 1013 /* command ring */ 1014 bzero(&ld->txp_cmdring, sizeof(struct txp_cmd_desc) * CMD_ENTRIES); 1015 boot->br_cmd_lo = vtophys(&ld->txp_cmdring); 1016 boot->br_cmd_hi = 0; 1017 boot->br_cmd_siz = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 1018 sc->sc_cmdring.base = (struct txp_cmd_desc *)&ld->txp_cmdring; 1019 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 1020 sc->sc_cmdring.lastwrite = 0; 1021 1022 /* response ring */ 1023 bzero(&ld->txp_rspring, sizeof(struct txp_rsp_desc) * RSP_ENTRIES); 1024 boot->br_resp_lo = vtophys(&ld->txp_rspring); 1025 boot->br_resp_hi = 0; 1026 boot->br_resp_siz = CMD_ENTRIES * sizeof(struct txp_rsp_desc); 1027 sc->sc_rspring.base = (struct txp_rsp_desc *)&ld->txp_rspring; 1028 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc); 1029 sc->sc_rspring.lastwrite = 0; 1030 1031 /* receive buffer ring */ 1032 boot->br_rxbuf_lo = vtophys(&ld->txp_rxbufs); 1033 boot->br_rxbuf_hi = 0; 1034 boot->br_rxbuf_siz = RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc); 1035 sc->sc_rxbufs = (struct txp_rxbuf_desc *)&ld->txp_rxbufs; 1036 1037 for (i = 0; i < RXBUF_ENTRIES; i++) { 1038 struct txp_swdesc *sd; 1039 if (sc->sc_rxbufs[i].rb_sd != NULL) 1040 continue; 1041 sc->sc_rxbufs[i].rb_sd = malloc(sizeof(struct txp_swdesc), 1042 M_DEVBUF, M_NOWAIT); 1043 if (sc->sc_rxbufs[i].rb_sd == NULL) 1044 return(ENOBUFS); 1045 sd = sc->sc_rxbufs[i].rb_sd; 1046 sd->sd_mbuf = NULL; 1047 } 1048 sc->sc_rxbufprod = 0; 1049 1050 /* zero dma */ 1051 bzero(&ld->txp_zero, sizeof(u_int32_t)); 1052 boot->br_zero_lo = vtophys(&ld->txp_zero); 1053 boot->br_zero_hi = 0; 1054 1055 /* See if it's waiting for boot, and try to boot it */ 1056 for (i = 0; i < 10000; i++) { 1057 r = READ_REG(sc, TXP_A2H_0); 1058 if (r == STAT_WAITING_FOR_BOOT) 1059 break; 1060 DELAY(50); 1061 } 1062 1063 if (r != STAT_WAITING_FOR_BOOT) { 1064 device_printf(sc->sc_dev, "not waiting for boot\n"); 1065 return(ENXIO); 1066 } 1067 1068 WRITE_REG(sc, TXP_H2A_2, 0); 1069 WRITE_REG(sc, TXP_H2A_1, vtophys(sc->sc_boot)); 1070 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD); 1071 1072 /* See if it booted */ 1073 for (i = 0; i < 10000; i++) { 1074 r = READ_REG(sc, TXP_A2H_0); 1075 if (r == STAT_RUNNING) 1076 break; 1077 DELAY(50); 1078 } 1079 if (r != STAT_RUNNING) { 1080 device_printf(sc->sc_dev, "fw not running\n"); 1081 return(ENXIO); 1082 } 1083 1084 /* Clear TX and CMD ring write registers */ 1085 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL); 1086 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL); 1087 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL); 1088 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL); 1089 1090 return (0); 1091} 1092 1093static int 1094txp_ioctl(ifp, command, data) 1095 struct ifnet *ifp; 1096 u_long command; 1097 caddr_t data; 1098{ 1099 struct txp_softc *sc = ifp->if_softc; 1100 struct ifreq *ifr = (struct ifreq *)data; 1101 int s, error = 0; 1102 1103 s = splnet(); 1104 1105 if ((error = ether_ioctl(ifp, command, data)) > 0) { 1106 splx(s); 1107 return error; 1108 } 1109 1110 switch(command) { 1111 case SIOCSIFADDR: 1112 case SIOCGIFADDR: 1113 case SIOCSIFMTU: 1114 error = ether_ioctl(ifp, command, data); 1115 break; 1116 case SIOCSIFFLAGS: 1117 if (ifp->if_flags & IFF_UP) { 1118 txp_init(sc); 1119 } else { 1120 if (ifp->if_flags & IFF_RUNNING) 1121 txp_stop(sc); 1122 } 1123 break; 1124 case SIOCADDMULTI: 1125 case SIOCDELMULTI: 1126 /* 1127 * Multicast list has changed; set the hardware 1128 * filter accordingly. 1129 */ 1130 txp_set_filter(sc); 1131 error = 0; 1132 break; 1133 case SIOCGIFMEDIA: 1134 case SIOCSIFMEDIA: 1135 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command); 1136 break; 1137 default: 1138 error = EINVAL; 1139 break; 1140 } 1141 1142 (void)splx(s); 1143 1144 return(error); 1145} 1146 1147static int 1148txp_rxring_fill(sc) 1149 struct txp_softc *sc; 1150{ 1151 int i; 1152 struct ifnet *ifp; 1153 struct txp_swdesc *sd; 1154 1155 ifp = &sc->sc_arpcom.ac_if; 1156 1157 for (i = 0; i < RXBUF_ENTRIES; i++) { 1158 sd = sc->sc_rxbufs[i].rb_sd; 1159 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 1160 if (sd->sd_mbuf == NULL) 1161 return(ENOBUFS); 1162 1163 MCLGET(sd->sd_mbuf, M_DONTWAIT); 1164 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) { 1165 m_freem(sd->sd_mbuf); 1166 return(ENOBUFS); 1167 } 1168 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 1169 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 1170 1171 sc->sc_rxbufs[i].rb_paddrlo = 1172 vtophys(mtod(sd->sd_mbuf, vm_offset_t)); 1173 sc->sc_rxbufs[i].rb_paddrhi = 0; 1174 } 1175 1176 sc->sc_hostvar->hv_rx_buf_write_idx = (RXBUF_ENTRIES - 1) * 1177 sizeof(struct txp_rxbuf_desc); 1178 1179 return(0); 1180} 1181 1182static void 1183txp_rxring_empty(sc) 1184 struct txp_softc *sc; 1185{ 1186 int i; 1187 struct txp_swdesc *sd; 1188 1189 if (sc->sc_rxbufs == NULL) 1190 return; 1191 1192 for (i = 0; i < RXBUF_ENTRIES; i++) { 1193 if (&sc->sc_rxbufs[i] == NULL) 1194 continue; 1195 sd = sc->sc_rxbufs[i].rb_sd; 1196 if (sd == NULL) 1197 continue; 1198 if (sd->sd_mbuf != NULL) { 1199 m_freem(sd->sd_mbuf); 1200 sd->sd_mbuf = NULL; 1201 } 1202 } 1203 1204 return; 1205} 1206 1207static void 1208txp_init(xsc) 1209 void *xsc; 1210{ 1211 struct txp_softc *sc; 1212 struct ifnet *ifp; 1213 u_int16_t p1; 1214 u_int32_t p2; 1215 int s; 1216 1217 sc = xsc; 1218 ifp = &sc->sc_arpcom.ac_if; 1219 1220 if (ifp->if_flags & IFF_RUNNING) 1221 return; 1222 1223 txp_stop(sc); 1224 1225 s = splnet(); 1226 1227 txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 1228 NULL, NULL, NULL, 1); 1229 1230 /* Set station address. */ 1231 ((u_int8_t *)&p1)[1] = sc->sc_arpcom.ac_enaddr[0]; 1232 ((u_int8_t *)&p1)[0] = sc->sc_arpcom.ac_enaddr[1]; 1233 ((u_int8_t *)&p2)[3] = sc->sc_arpcom.ac_enaddr[2]; 1234 ((u_int8_t *)&p2)[2] = sc->sc_arpcom.ac_enaddr[3]; 1235 ((u_int8_t *)&p2)[1] = sc->sc_arpcom.ac_enaddr[4]; 1236 ((u_int8_t *)&p2)[0] = sc->sc_arpcom.ac_enaddr[5]; 1237 txp_command(sc, TXP_CMD_STATION_ADDRESS_WRITE, p1, p2, 0, 1238 NULL, NULL, NULL, 1); 1239 1240 txp_set_filter(sc); 1241 1242 txp_rxring_fill(sc); 1243 1244 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1245 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1246 1247 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF | 1248 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 1249 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 1250 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 1251 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 1252 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 1253 1254 ifp->if_flags |= IFF_RUNNING; 1255 ifp->if_flags &= ~IFF_OACTIVE; 1256 ifp->if_timer = 0; 1257 1258 sc->sc_tick = timeout(txp_tick, sc, hz); 1259 1260 splx(s); 1261} 1262 1263static void 1264txp_tick(vsc) 1265 void *vsc; 1266{ 1267 struct txp_softc *sc = vsc; 1268 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1269 struct txp_rsp_desc *rsp = NULL; 1270 struct txp_ext_desc *ext; 1271 int s; 1272 1273 s = splnet(); 1274 txp_rxbuf_reclaim(sc); 1275 1276 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0, 1277 &rsp, 1)) 1278 goto out; 1279 if (rsp->rsp_numdesc != 6) 1280 goto out; 1281 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0, 1282 NULL, NULL, NULL, 1)) 1283 goto out; 1284 ext = (struct txp_ext_desc *)(rsp + 1); 1285 1286 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 + 1287 ext[4].ext_1 + ext[4].ext_4; 1288 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 + 1289 ext[2].ext_1; 1290 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 + 1291 ext[1].ext_3; 1292 ifp->if_opackets += rsp->rsp_par2; 1293 ifp->if_ipackets += ext[2].ext_3; 1294 1295out: 1296 if (rsp != NULL) 1297 free(rsp, M_DEVBUF); 1298 1299 splx(s); 1300 sc->sc_tick = timeout(txp_tick, sc, hz); 1301 1302 return; 1303} 1304 1305static void 1306txp_start(ifp) 1307 struct ifnet *ifp; 1308{ 1309 struct txp_softc *sc = ifp->if_softc; 1310 struct txp_tx_ring *r = &sc->sc_txhir; 1311 struct txp_tx_desc *txd; 1312 struct txp_frag_desc *fxd; 1313 struct mbuf *m, *m0; 1314 struct txp_swdesc *sd; 1315 u_int32_t firstprod, firstcnt, prod, cnt; 1316 struct ifvlan *ifv; 1317 1318 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1319 return; 1320 1321 prod = r->r_prod; 1322 cnt = r->r_cnt; 1323 1324 while (1) { 1325 IF_DEQUEUE(&ifp->if_snd, m); 1326 if (m == NULL) 1327 break; 1328 1329 firstprod = prod; 1330 firstcnt = cnt; 1331 1332 sd = sc->sc_txd + prod; 1333 sd->sd_mbuf = m; 1334 1335 if ((TX_ENTRIES - cnt) < 4) 1336 goto oactive; 1337 1338 txd = r->r_desc + prod; 1339 1340 txd->tx_flags = TX_FLAGS_TYPE_DATA; 1341 txd->tx_numdesc = 0; 1342 txd->tx_addrlo = 0; 1343 txd->tx_addrhi = 0; 1344 txd->tx_totlen = 0; 1345 txd->tx_pflags = 0; 1346 1347 if (++prod == TX_ENTRIES) 1348 prod = 0; 1349 1350 if (++cnt >= (TX_ENTRIES - 4)) 1351 goto oactive; 1352 1353 if ((m->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1354 m->m_pkthdr.rcvif != NULL) { 1355 ifv = m->m_pkthdr.rcvif->if_softc; 1356 txd->tx_pflags = TX_PFLAGS_VLAN | 1357 (htons(ifv->ifv_tag) << TX_PFLAGS_VLANTAG_S); 1358 } 1359 1360 if (m->m_pkthdr.csum_flags & CSUM_IP) 1361 txd->tx_pflags |= TX_PFLAGS_IPCKSUM; 1362 1363#if 0 1364 if (m->m_pkthdr.csum_flags & CSUM_TCP) 1365 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM; 1366 if (m->m_pkthdr.csum_flags & CSUM_UDP) 1367 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM; 1368#endif 1369 1370 fxd = (struct txp_frag_desc *)(r->r_desc + prod); 1371 for (m0 = m; m0 != NULL; m0 = m0->m_next) { 1372 if (m0->m_len == 0) 1373 continue; 1374 if (++cnt >= (TX_ENTRIES - 4)) 1375 goto oactive; 1376 1377 txd->tx_numdesc++; 1378 1379 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG; 1380 fxd->frag_rsvd1 = 0; 1381 fxd->frag_len = m0->m_len; 1382 fxd->frag_addrlo = vtophys(mtod(m0, vm_offset_t)); 1383 fxd->frag_addrhi = 0; 1384 fxd->frag_rsvd2 = 0; 1385 1386 if (++prod == TX_ENTRIES) { 1387 fxd = (struct txp_frag_desc *)r->r_desc; 1388 prod = 0; 1389 } else 1390 fxd++; 1391 1392 } 1393 1394 ifp->if_timer = 5; 1395 1396 if (ifp->if_bpf) 1397 bpf_mtap(ifp, m); 1398 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod)); 1399 } 1400 1401 r->r_prod = prod; 1402 r->r_cnt = cnt; 1403 return; 1404 1405oactive: 1406 ifp->if_flags |= IFF_OACTIVE; 1407 r->r_prod = firstprod; 1408 r->r_cnt = firstcnt; 1409 IF_PREPEND(&ifp->if_snd, m); 1410 return; 1411} 1412 1413/* 1414 * Handle simple commands sent to the typhoon 1415 */ 1416static int 1417txp_command(sc, id, in1, in2, in3, out1, out2, out3, wait) 1418 struct txp_softc *sc; 1419 u_int16_t id, in1, *out1; 1420 u_int32_t in2, in3, *out2, *out3; 1421 int wait; 1422{ 1423 struct txp_rsp_desc *rsp = NULL; 1424 1425 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait)) 1426 return (-1); 1427 1428 if (!wait) 1429 return (0); 1430 1431 if (out1 != NULL) 1432 *out1 = rsp->rsp_par1; 1433 if (out2 != NULL) 1434 *out2 = rsp->rsp_par2; 1435 if (out3 != NULL) 1436 *out3 = rsp->rsp_par3; 1437 free(rsp, M_DEVBUF); 1438 return (0); 1439} 1440 1441static int 1442txp_command2(sc, id, in1, in2, in3, in_extp, in_extn, rspp, wait) 1443 struct txp_softc *sc; 1444 u_int16_t id, in1; 1445 u_int32_t in2, in3; 1446 struct txp_ext_desc *in_extp; 1447 u_int8_t in_extn; 1448 struct txp_rsp_desc **rspp; 1449 int wait; 1450{ 1451 struct txp_hostvar *hv = sc->sc_hostvar; 1452 struct txp_cmd_desc *cmd; 1453 struct txp_ext_desc *ext; 1454 u_int32_t idx, i; 1455 u_int16_t seq; 1456 1457 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) { 1458 device_printf(sc->sc_dev, "no free cmd descriptors\n"); 1459 return (-1); 1460 } 1461 1462 idx = sc->sc_cmdring.lastwrite; 1463 cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1464 bzero(cmd, sizeof(*cmd)); 1465 1466 cmd->cmd_numdesc = in_extn; 1467 cmd->cmd_seq = seq = sc->sc_seq++; 1468 cmd->cmd_id = id; 1469 cmd->cmd_par1 = in1; 1470 cmd->cmd_par2 = in2; 1471 cmd->cmd_par3 = in3; 1472 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD | 1473 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID; 1474 1475 idx += sizeof(struct txp_cmd_desc); 1476 if (idx == sc->sc_cmdring.size) 1477 idx = 0; 1478 1479 for (i = 0; i < in_extn; i++) { 1480 ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1481 bcopy(in_extp, ext, sizeof(struct txp_ext_desc)); 1482 in_extp++; 1483 idx += sizeof(struct txp_cmd_desc); 1484 if (idx == sc->sc_cmdring.size) 1485 idx = 0; 1486 } 1487 1488 sc->sc_cmdring.lastwrite = idx; 1489 1490 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite); 1491 1492 if (!wait) 1493 return (0); 1494 1495 for (i = 0; i < 10000; i++) { 1496 idx = hv->hv_resp_read_idx; 1497 if (idx != hv->hv_resp_write_idx) { 1498 *rspp = NULL; 1499 if (txp_response(sc, idx, id, seq, rspp)) 1500 return (-1); 1501 if (*rspp != NULL) 1502 break; 1503 } 1504 DELAY(50); 1505 } 1506 if (i == 1000 || (*rspp) == NULL) { 1507 device_printf(sc->sc_dev, "0x%x command failed\n", id); 1508 return (-1); 1509 } 1510 1511 return (0); 1512} 1513 1514static int 1515txp_response(sc, ridx, id, seq, rspp) 1516 struct txp_softc *sc; 1517 u_int32_t ridx; 1518 u_int16_t id; 1519 u_int16_t seq; 1520 struct txp_rsp_desc **rspp; 1521{ 1522 struct txp_hostvar *hv = sc->sc_hostvar; 1523 struct txp_rsp_desc *rsp; 1524 1525 while (ridx != hv->hv_resp_write_idx) { 1526 rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx); 1527 1528 if (id == rsp->rsp_id && rsp->rsp_seq == seq) { 1529 *rspp = (struct txp_rsp_desc *)malloc( 1530 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1), 1531 M_DEVBUF, M_NOWAIT); 1532 if ((*rspp) == NULL) 1533 return (-1); 1534 txp_rsp_fixup(sc, rsp, *rspp); 1535 return (0); 1536 } 1537 1538 if (rsp->rsp_flags & RSP_FLAGS_ERROR) { 1539 device_printf(sc->sc_dev, "response error!\n"); 1540 txp_rsp_fixup(sc, rsp, NULL); 1541 ridx = hv->hv_resp_read_idx; 1542 continue; 1543 } 1544 1545 switch (rsp->rsp_id) { 1546 case TXP_CMD_CYCLE_STATISTICS: 1547 case TXP_CMD_MEDIA_STATUS_READ: 1548 break; 1549 case TXP_CMD_HELLO_RESPONSE: 1550 device_printf(sc->sc_dev, "hello\n"); 1551 break; 1552 default: 1553 device_printf(sc->sc_dev, "unknown id(0x%x)\n", 1554 rsp->rsp_id); 1555 } 1556 1557 txp_rsp_fixup(sc, rsp, NULL); 1558 ridx = hv->hv_resp_read_idx; 1559 hv->hv_resp_read_idx = ridx; 1560 } 1561 1562 return (0); 1563} 1564 1565static void 1566txp_rsp_fixup(sc, rsp, dst) 1567 struct txp_softc *sc; 1568 struct txp_rsp_desc *rsp, *dst; 1569{ 1570 struct txp_rsp_desc *src = rsp; 1571 struct txp_hostvar *hv = sc->sc_hostvar; 1572 u_int32_t i, ridx; 1573 1574 ridx = hv->hv_resp_read_idx; 1575 1576 for (i = 0; i < rsp->rsp_numdesc + 1; i++) { 1577 if (dst != NULL) 1578 bcopy(src, dst++, sizeof(struct txp_rsp_desc)); 1579 ridx += sizeof(struct txp_rsp_desc); 1580 if (ridx == sc->sc_rspring.size) { 1581 src = sc->sc_rspring.base; 1582 ridx = 0; 1583 } else 1584 src++; 1585 sc->sc_rspring.lastwrite = hv->hv_resp_read_idx = ridx; 1586 } 1587 1588 hv->hv_resp_read_idx = ridx; 1589} 1590 1591static int 1592txp_cmd_desc_numfree(sc) 1593 struct txp_softc *sc; 1594{ 1595 struct txp_hostvar *hv = sc->sc_hostvar; 1596 struct txp_boot_record *br = sc->sc_boot; 1597 u_int32_t widx, ridx, nfree; 1598 1599 widx = sc->sc_cmdring.lastwrite; 1600 ridx = hv->hv_cmd_read_idx; 1601 1602 if (widx == ridx) { 1603 /* Ring is completely free */ 1604 nfree = br->br_cmd_siz - sizeof(struct txp_cmd_desc); 1605 } else { 1606 if (widx > ridx) 1607 nfree = br->br_cmd_siz - 1608 (widx - ridx + sizeof(struct txp_cmd_desc)); 1609 else 1610 nfree = ridx - widx - sizeof(struct txp_cmd_desc); 1611 } 1612 1613 return (nfree / sizeof(struct txp_cmd_desc)); 1614} 1615 1616static void 1617txp_stop(sc) 1618 struct txp_softc *sc; 1619{ 1620 struct ifnet *ifp; 1621 1622 ifp = &sc->sc_arpcom.ac_if; 1623 1624 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1625 1626 untimeout(txp_tick, sc, sc->sc_tick); 1627 1628 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1629 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1630 1631 txp_rxring_empty(sc); 1632 1633 return; 1634} 1635 1636static void 1637txp_watchdog(ifp) 1638 struct ifnet *ifp; 1639{ 1640 return; 1641} 1642 1643static int 1644txp_ifmedia_upd(ifp) 1645 struct ifnet *ifp; 1646{ 1647 struct txp_softc *sc = ifp->if_softc; 1648 struct ifmedia *ifm = &sc->sc_ifmedia; 1649 u_int16_t new_xcvr; 1650 1651 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1652 return (EINVAL); 1653 1654 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) { 1655 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1656 new_xcvr = TXP_XCVR_10_FDX; 1657 else 1658 new_xcvr = TXP_XCVR_10_HDX; 1659 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 1660 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1661 new_xcvr = TXP_XCVR_100_FDX; 1662 else 1663 new_xcvr = TXP_XCVR_100_HDX; 1664 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1665 new_xcvr = TXP_XCVR_AUTO; 1666 } else 1667 return (EINVAL); 1668 1669 /* nothing to do */ 1670 if (sc->sc_xcvr == new_xcvr) 1671 return (0); 1672 1673 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0, 1674 NULL, NULL, NULL, 0); 1675 sc->sc_xcvr = new_xcvr; 1676 1677 return (0); 1678} 1679 1680static void 1681txp_ifmedia_sts(ifp, ifmr) 1682 struct ifnet *ifp; 1683 struct ifmediareq *ifmr; 1684{ 1685 struct txp_softc *sc = ifp->if_softc; 1686 struct ifmedia *ifm = &sc->sc_ifmedia; 1687 u_int16_t bmsr, bmcr, anlpar; 1688 1689 ifmr->ifm_status = IFM_AVALID; 1690 ifmr->ifm_active = IFM_ETHER; 1691 1692 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1693 &bmsr, NULL, NULL, 1)) 1694 goto bail; 1695 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1696 &bmsr, NULL, NULL, 1)) 1697 goto bail; 1698 1699 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0, 1700 &bmcr, NULL, NULL, 1)) 1701 goto bail; 1702 1703 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0, 1704 &anlpar, NULL, NULL, 1)) 1705 goto bail; 1706 1707 if (bmsr & BMSR_LINK) 1708 ifmr->ifm_status |= IFM_ACTIVE; 1709 1710 if (bmcr & BMCR_ISO) { 1711 ifmr->ifm_active |= IFM_NONE; 1712 ifmr->ifm_status = 0; 1713 return; 1714 } 1715 1716 if (bmcr & BMCR_LOOP) 1717 ifmr->ifm_active |= IFM_LOOP; 1718 1719 if (bmcr & BMCR_AUTOEN) { 1720 if ((bmsr & BMSR_ACOMP) == 0) { 1721 ifmr->ifm_active |= IFM_NONE; 1722 return; 1723 } 1724 1725 if (anlpar & ANLPAR_T4) 1726 ifmr->ifm_active |= IFM_100_T4; 1727 else if (anlpar & ANLPAR_TX_FD) 1728 ifmr->ifm_active |= IFM_100_TX|IFM_FDX; 1729 else if (anlpar & ANLPAR_TX) 1730 ifmr->ifm_active |= IFM_100_TX; 1731 else if (anlpar & ANLPAR_10_FD) 1732 ifmr->ifm_active |= IFM_10_T|IFM_FDX; 1733 else if (anlpar & ANLPAR_10) 1734 ifmr->ifm_active |= IFM_10_T; 1735 else 1736 ifmr->ifm_active |= IFM_NONE; 1737 } else 1738 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 1739 return; 1740 1741bail: 1742 ifmr->ifm_active |= IFM_NONE; 1743 ifmr->ifm_status &= ~IFM_AVALID; 1744} 1745 1746#ifdef TXP_DEBUG 1747static void 1748txp_show_descriptor(d) 1749 void *d; 1750{ 1751 struct txp_cmd_desc *cmd = d; 1752 struct txp_rsp_desc *rsp = d; 1753 struct txp_tx_desc *txd = d; 1754 struct txp_frag_desc *frgd = d; 1755 1756 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) { 1757 case CMD_FLAGS_TYPE_CMD: 1758 /* command descriptor */ 1759 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1760 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq, 1761 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3); 1762 break; 1763 case CMD_FLAGS_TYPE_RESP: 1764 /* response descriptor */ 1765 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1766 rsp->rsp_flags, rsp->rsp_numdesc, rsp->rsp_id, rsp->rsp_seq, 1767 rsp->rsp_par1, rsp->rsp_par2, rsp->rsp_par3); 1768 break; 1769 case CMD_FLAGS_TYPE_DATA: 1770 /* data header (assuming tx for now) */ 1771 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]", 1772 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1773 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags); 1774 break; 1775 case CMD_FLAGS_TYPE_FRAG: 1776 /* fragment descriptor */ 1777 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]", 1778 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len, 1779 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2); 1780 break; 1781 default: 1782 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1783 cmd->cmd_flags & CMD_FLAGS_TYPE_M, 1784 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq, 1785 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3); 1786 break; 1787 } 1788} 1789#endif 1790 1791static void 1792txp_set_filter(sc) 1793 struct txp_softc *sc; 1794{ 1795 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1796 u_int32_t crc, carry, hashbit, hash[2]; 1797 u_int16_t filter; 1798 u_int8_t octet; 1799 int i, j, mcnt = 0; 1800 struct ifmultiaddr *ifma; 1801 char *enm; 1802 1803 if (ifp->if_flags & IFF_PROMISC) { 1804 filter = TXP_RXFILT_PROMISC; 1805 goto setit; 1806 } 1807 1808 filter = TXP_RXFILT_DIRECT; 1809 1810 if (ifp->if_flags & IFF_BROADCAST) 1811 filter |= TXP_RXFILT_BROADCAST; 1812 1813 if (ifp->if_flags & IFF_ALLMULTI) 1814 filter |= TXP_RXFILT_ALLMULTI; 1815 else { 1816 hash[0] = hash[1] = 0; 1817 1818 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1819 if (ifma->ifma_addr->sa_family != AF_LINK) 1820 continue; 1821 1822 enm = LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 1823 mcnt++; 1824 crc = 0xffffffff; 1825 1826 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1827 octet = enm[i]; 1828 for (j = 0; j < 8; j++) { 1829 carry = ((crc & 0x80000000) ? 1 : 0) ^ 1830 (octet & 1); 1831 crc <<= 1; 1832 octet >>= 1; 1833 if (carry) 1834 crc = (crc ^ TXP_POLYNOMIAL) | 1835 carry; 1836 } 1837 } 1838 hashbit = (u_int16_t)(crc & (64 - 1)); 1839 hash[hashbit / 32] |= (1 << hashbit % 32); 1840 } 1841 1842 if (mcnt > 0) { 1843 filter |= TXP_RXFILT_HASHMULTI; 1844 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE, 1845 2, hash[0], hash[1], NULL, NULL, NULL, 0); 1846 } 1847 } 1848 1849setit: 1850 1851 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0, 1852 NULL, NULL, NULL, 1); 1853 1854 return; 1855} 1856 1857static void 1858txp_capabilities(sc) 1859 struct txp_softc *sc; 1860{ 1861 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1862 struct txp_rsp_desc *rsp = NULL; 1863 struct txp_ext_desc *ext; 1864 1865 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1)) 1866 goto out; 1867 1868 if (rsp->rsp_numdesc != 1) 1869 goto out; 1870 ext = (struct txp_ext_desc *)(rsp + 1); 1871 1872 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK; 1873 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK; 1874 ifp->if_capabilities = 0; 1875 1876 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) { 1877 sc->sc_tx_capability |= OFFLOAD_VLAN; 1878 sc->sc_rx_capability |= OFFLOAD_VLAN; 1879 } 1880 1881#if 0 1882 /* not ready yet */ 1883 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) { 1884 sc->sc_tx_capability |= OFFLOAD_IPSEC; 1885 sc->sc_rx_capability |= OFFLOAD_IPSEC; 1886 ifp->if_capabilities |= IFCAP_IPSEC; 1887 } 1888#endif 1889 1890 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) { 1891 sc->sc_tx_capability |= OFFLOAD_IPCKSUM; 1892 sc->sc_rx_capability |= OFFLOAD_IPCKSUM; 1893 ifp->if_capabilities |= IFCAP_HWCSUM; 1894 ifp->if_hwassist |= CSUM_IP; 1895 } 1896 1897 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) { 1898#if 0 1899 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM; 1900#endif 1901 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM; 1902 ifp->if_capabilities |= IFCAP_HWCSUM; 1903 } 1904 1905 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) { 1906#if 0 1907 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM; 1908#endif 1909 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM; 1910 ifp->if_capabilities |= IFCAP_HWCSUM; 1911 } 1912 ifp->if_capenable = ifp->if_capabilities; 1913 1914 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0, 1915 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1)) 1916 goto out; 1917 1918out: 1919 if (rsp != NULL) 1920 free(rsp, M_DEVBUF); 1921 1922 return; 1923} 1924