sym_fw2.h revision 59743
1/* 2 * Device driver optimized for the Symbios/LSI 53C896/53C895A/53C1010 3 * PCI-SCSI controllers. 4 * 5 * Copyright (C) 1999-2000 Gerard Roudier <groudier@club-internet.fr> 6 * 7 * This driver also supports the following Symbios/LSI PCI-SCSI chips: 8 * 53C810A, 53C825A, 53C860, 53C875, 53C876, 53C885, 53C895, 9 * 53C810, 53C815, 53C825 and the 53C1510D is 53C8XX mode. 10 * 11 * 12 * This driver for FreeBSD-CAM is derived from the Linux sym53c8xx driver. 13 * Copyright (C) 1998-1999 Gerard Roudier 14 * 15 * The sym53c8xx driver is derived from the ncr53c8xx driver that had been 16 * a port of the FreeBSD ncr driver to Linux-1.2.13. 17 * 18 * The original ncr driver has been written for 386bsd and FreeBSD by 19 * Wolfgang Stanglmeier <wolf@cologne.de> 20 * Stefan Esser <se@mi.Uni-Koeln.de> 21 * Copyright (C) 1994 Wolfgang Stanglmeier 22 * 23 * The initialisation code, and part of the code that addresses 24 * FreeBSD-CAM services is based on the aic7xxx driver for FreeBSD-CAM 25 * written by Justin T. Gibbs. 26 * 27 * Other major contributions: 28 * 29 * NVRAM detection and reading. 30 * Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk> 31 * 32 *----------------------------------------------------------------------------- 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. The name of the author may not be used to endorse or promote products 43 * derived from this software without specific prior written permission. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 49 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58/* $FreeBSD: head/sys/dev/sym/sym_fw2.h 59743 2000-04-29 10:20:16Z groudier $ */ 59 60/* 61 * Scripts for SYMBIOS-Processor 62 * 63 * We have to know the offsets of all labels before we reach 64 * them (for forward jumps). Therefore we declare a struct 65 * here. If you make changes inside the script, 66 * 67 * DONT FORGET TO CHANGE THE LENGTHS HERE! 68 */ 69 70/* 71 * Script fragments which are loaded into the on-chip RAM 72 * of 825A, 875, 876, 895, 895A, 896 and 1010 chips. 73 * Must not exceed 4K bytes. 74 */ 75struct SYM_FWA_SCR { 76 u32 start [ 14]; 77 u32 getjob_begin [ 4]; 78 u32 getjob_end [ 4]; 79 u32 select [ 8]; 80 u32 wf_sel_done [ 2]; 81 u32 send_ident [ 2]; 82#ifdef SYM_CONF_IARB_SUPPORT 83 u32 select2 [ 8]; 84#else 85 u32 select2 [ 2]; 86#endif 87 u32 command [ 2]; 88 u32 dispatch [ 28]; 89 u32 sel_no_cmd [ 10]; 90 u32 init [ 6]; 91 u32 clrack [ 4]; 92 u32 disp_status [ 4]; 93 u32 datai_done [ 26]; 94 u32 datao_done [ 12]; 95 u32 datai_phase [ 2]; 96 u32 datao_phase [ 2]; 97 u32 msg_in [ 2]; 98 u32 msg_in2 [ 10]; 99#ifdef SYM_CONF_IARB_SUPPORT 100 u32 status [ 14]; 101#else 102 u32 status [ 10]; 103#endif 104 u32 complete [ 8]; 105 u32 complete2 [ 12]; 106 u32 complete_error [ 4]; 107 u32 done [ 14]; 108 u32 done_end [ 2]; 109 u32 save_dp [ 8]; 110 u32 restore_dp [ 4]; 111 u32 disconnect [ 20]; 112#ifdef SYM_CONF_IARB_SUPPORT 113 u32 idle [ 4]; 114#else 115 u32 idle [ 2]; 116#endif 117#ifdef SYM_CONF_IARB_SUPPORT 118 u32 ungetjob [ 6]; 119#else 120 u32 ungetjob [ 4]; 121#endif 122 u32 reselect [ 4]; 123 u32 reselected [ 22]; 124 u32 resel_scntl4 [ 20]; 125 u32 resel_lun0 [ 6]; 126#if SYM_CONF_MAX_TASK*4 > 512 127 u32 resel_tag [ 26]; 128#elif SYM_CONF_MAX_TASK*4 > 256 129 u32 resel_tag [ 20]; 130#else 131 u32 resel_tag [ 16]; 132#endif 133 u32 resel_dsa [ 2]; 134 u32 resel_dsa1 [ 6]; 135 u32 resel_no_tag [ 6]; 136 u32 data_in [SYM_CONF_MAX_SG * 2]; 137 u32 data_in2 [ 4]; 138 u32 data_out [SYM_CONF_MAX_SG * 2]; 139 u32 data_out2 [ 4]; 140 u32 pm0_data [ 12]; 141 u32 pm0_data_out [ 6]; 142 u32 pm0_data_end [ 6]; 143 u32 pm1_data [ 12]; 144 u32 pm1_data_out [ 6]; 145 u32 pm1_data_end [ 6]; 146}; 147 148/* 149 * Script fragments which stay in main memory for all chips 150 * except for chips that support 8K on-chip RAM. 151 */ 152struct SYM_FWB_SCR { 153 u32 start64 [ 2]; 154 u32 no_data [ 2]; 155 u32 sel_for_abort [ 18]; 156 u32 sel_for_abort_1 [ 2]; 157 u32 msg_in_etc [ 12]; 158 u32 msg_received [ 4]; 159 u32 msg_weird_seen [ 4]; 160 u32 msg_extended [ 20]; 161 u32 msg_bad [ 6]; 162 u32 msg_weird [ 4]; 163 u32 msg_weird1 [ 8]; 164 165 u32 wdtr_resp [ 6]; 166 u32 send_wdtr [ 4]; 167 u32 sdtr_resp [ 6]; 168 u32 send_sdtr [ 4]; 169 u32 ppr_resp [ 6]; 170 u32 send_ppr [ 4]; 171 u32 nego_bad_phase [ 4]; 172 u32 msg_out [ 4]; 173 u32 msg_out_done [ 4]; 174 u32 data_ovrun [ 2]; 175 u32 data_ovrun1 [ 22]; 176 u32 data_ovrun2 [ 8]; 177 u32 abort_resel [ 16]; 178 u32 resend_ident [ 4]; 179 u32 ident_break [ 4]; 180 u32 ident_break_atn [ 4]; 181 u32 sdata_in [ 6]; 182 u32 resel_bad_lun [ 4]; 183 u32 bad_i_t_l [ 4]; 184 u32 bad_i_t_l_q [ 4]; 185 u32 bad_status [ 6]; 186 u32 pm_handle [ 20]; 187 u32 pm_handle1 [ 4]; 188 u32 pm_save [ 4]; 189 u32 pm0_save [ 14]; 190 u32 pm1_save [ 14]; 191 192 /* WSR handling */ 193 u32 pm_wsr_handle [ 42]; 194 u32 wsr_ma_helper [ 4]; 195 196 /* Data area */ 197 u32 zero [ 1]; 198 u32 scratch [ 1]; 199 u32 pm0_data_addr [ 1]; 200 u32 pm1_data_addr [ 1]; 201 u32 saved_dsa [ 1]; 202 u32 saved_drs [ 1]; 203 u32 done_pos [ 1]; 204 u32 startpos [ 1]; 205 u32 targtbl [ 1]; 206 /* End of data area */ 207 208 u32 snooptest [ 6]; 209 u32 snoopend [ 2]; 210}; 211 212static struct SYM_FWA_SCR SYM_FWA_SCR = { 213/*--------------------------< START >----------------------------*/ { 214 /* 215 * Switch the LED on. 216 * Will be patched with a NO_OP if LED 217 * not needed or not desired. 218 */ 219 SCR_REG_REG (gpreg, SCR_AND, 0xfe), 220 0, 221 /* 222 * Clear SIGP. 223 */ 224 SCR_FROM_REG (ctest2), 225 0, 226 /* 227 * Stop here if the C code wants to perform 228 * some error recovery procedure manually. 229 * (Indicate this by setting SEM in ISTAT) 230 */ 231 SCR_FROM_REG (istat), 232 0, 233 /* 234 * Report to the C code the next position in 235 * the start queue the SCRIPTS will schedule. 236 * The C code must not change SCRATCHA. 237 */ 238 SCR_LOAD_ABS (scratcha, 4), 239 PADDR_B (startpos), 240 SCR_INT ^ IFTRUE (MASK (SEM, SEM)), 241 SIR_SCRIPT_STOPPED, 242 /* 243 * Start the next job. 244 * 245 * @DSA = start point for this job. 246 * SCRATCHA = address of this job in the start queue. 247 * 248 * We will restore startpos with SCRATCHA if we fails the 249 * arbitration or if it is the idle job. 250 * 251 * The below GETJOB_BEGIN to GETJOB_END section of SCRIPTS 252 * is a critical path. If it is partially executed, it then 253 * may happen that the job address is not yet in the DSA 254 * and the the next queue position points to the next JOB. 255 */ 256 SCR_LOAD_ABS (dsa, 4), 257 PADDR_B (startpos), 258 SCR_LOAD_REL (temp, 4), 259 4, 260}/*-------------------------< GETJOB_BEGIN >---------------------*/,{ 261 SCR_STORE_ABS (temp, 4), 262 PADDR_B (startpos), 263 SCR_LOAD_REL (dsa, 4), 264 0, 265}/*-------------------------< GETJOB_END >-----------------------*/,{ 266 SCR_LOAD_REL (temp, 4), 267 0, 268 SCR_RETURN, 269 0, 270}/*-------------------------< SELECT >---------------------------*/,{ 271 /* 272 * DSA contains the address of a scheduled 273 * data structure. 274 * 275 * SCRATCHA contains the address of the start queue 276 * entry which points to the next job. 277 * 278 * Set Initiator mode. 279 * 280 * (Target mode is left as an exercise for the reader) 281 */ 282 SCR_CLR (SCR_TRG), 283 0, 284 /* 285 * And try to select this target. 286 */ 287 SCR_SEL_TBL_ATN ^ offsetof (struct sym_dsb, select), 288 PADDR_A (ungetjob), 289 /* 290 * Now there are 4 possibilities: 291 * 292 * (1) The chip looses arbitration. 293 * This is ok, because it will try again, 294 * when the bus becomes idle. 295 * (But beware of the timeout function!) 296 * 297 * (2) The chip is reselected. 298 * Then the script processor takes the jump 299 * to the RESELECT label. 300 * 301 * (3) The chip wins arbitration. 302 * Then it will execute SCRIPTS instruction until 303 * the next instruction that checks SCSI phase. 304 * Then will stop and wait for selection to be 305 * complete or selection time-out to occur. 306 * 307 * After having won arbitration, the SCRIPTS 308 * processor is able to execute instructions while 309 * the SCSI core is performing SCSI selection. 310 */ 311 /* 312 * load the savep (saved data pointer) into 313 * the actual data pointer. 314 */ 315 SCR_LOAD_REL (temp, 4), 316 offsetof (struct sym_ccb, phys.head.savep), 317 /* 318 * Initialize the status registers 319 */ 320 SCR_LOAD_REL (scr0, 4), 321 offsetof (struct sym_ccb, phys.head.status), 322}/*-------------------------< WF_SEL_DONE >----------------------*/,{ 323 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_OUT)), 324 SIR_SEL_ATN_NO_MSG_OUT, 325}/*-------------------------< SEND_IDENT >-----------------------*/,{ 326 /* 327 * Selection complete. 328 * Send the IDENTIFY and possibly the TAG message 329 * and negotiation message if present. 330 */ 331 SCR_MOVE_TBL ^ SCR_MSG_OUT, 332 offsetof (struct sym_dsb, smsg), 333}/*-------------------------< SELECT2 >--------------------------*/,{ 334#ifdef SYM_CONF_IARB_SUPPORT 335 /* 336 * Set IMMEDIATE ARBITRATION if we have been given 337 * a hint to do so. (Some job to do after this one). 338 */ 339 SCR_FROM_REG (HF_REG), 340 0, 341 SCR_JUMPR ^ IFFALSE (MASK (HF_HINT_IARB, HF_HINT_IARB)), 342 8, 343 SCR_REG_REG (scntl1, SCR_OR, IARB), 344 0, 345#endif 346 /* 347 * Anticipate the COMMAND phase. 348 * This is the PHASE we expect at this point. 349 */ 350 SCR_JUMP ^ IFFALSE (WHEN (SCR_COMMAND)), 351 PADDR_A (sel_no_cmd), 352}/*-------------------------< COMMAND >--------------------------*/,{ 353 /* 354 * ... and send the command 355 */ 356 SCR_MOVE_TBL ^ SCR_COMMAND, 357 offsetof (struct sym_dsb, cmd), 358}/*-------------------------< DISPATCH >-------------------------*/,{ 359 /* 360 * MSG_IN is the only phase that shall be 361 * entered at least once for each (re)selection. 362 * So we test it first. 363 */ 364 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)), 365 PADDR_A (msg_in), 366 SCR_JUMP ^ IFTRUE (IF (SCR_DATA_OUT)), 367 PADDR_A (datao_phase), 368 SCR_JUMP ^ IFTRUE (IF (SCR_DATA_IN)), 369 PADDR_A (datai_phase), 370 SCR_JUMP ^ IFTRUE (IF (SCR_STATUS)), 371 PADDR_A (status), 372 SCR_JUMP ^ IFTRUE (IF (SCR_COMMAND)), 373 PADDR_A (command), 374 SCR_JUMP ^ IFTRUE (IF (SCR_MSG_OUT)), 375 PADDR_B (msg_out), 376 /* 377 * Discard as many illegal phases as 378 * required and tell the C code about. 379 */ 380 SCR_JUMPR ^ IFFALSE (WHEN (SCR_ILG_OUT)), 381 16, 382 SCR_MOVE_ABS (1) ^ SCR_ILG_OUT, 383 HADDR_1 (scratch), 384 SCR_JUMPR ^ IFTRUE (WHEN (SCR_ILG_OUT)), 385 -16, 386 SCR_JUMPR ^ IFFALSE (WHEN (SCR_ILG_IN)), 387 16, 388 SCR_MOVE_ABS (1) ^ SCR_ILG_IN, 389 HADDR_1 (scratch), 390 SCR_JUMPR ^ IFTRUE (WHEN (SCR_ILG_IN)), 391 -16, 392 SCR_INT, 393 SIR_BAD_PHASE, 394 SCR_JUMP, 395 PADDR_A (dispatch), 396}/*-------------------------< SEL_NO_CMD >-----------------------*/,{ 397 /* 398 * The target does not switch to command 399 * phase after IDENTIFY has been sent. 400 * 401 * If it stays in MSG OUT phase send it 402 * the IDENTIFY again. 403 */ 404 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_OUT)), 405 PADDR_B (resend_ident), 406 /* 407 * If target does not switch to MSG IN phase 408 * and we sent a negotiation, assert the 409 * failure immediately. 410 */ 411 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)), 412 PADDR_A (dispatch), 413 SCR_FROM_REG (HS_REG), 414 0, 415 SCR_INT ^ IFTRUE (DATA (HS_NEGOTIATE)), 416 SIR_NEGO_FAILED, 417 /* 418 * Jump to dispatcher. 419 */ 420 SCR_JUMP, 421 PADDR_A (dispatch), 422}/*-------------------------< INIT >-----------------------------*/,{ 423 /* 424 * Wait for the SCSI RESET signal to be 425 * inactive before restarting operations, 426 * since the chip may hang on SEL_ATN 427 * if SCSI RESET is active. 428 */ 429 SCR_FROM_REG (sstat0), 430 0, 431 SCR_JUMPR ^ IFTRUE (MASK (IRST, IRST)), 432 -16, 433 SCR_JUMP, 434 PADDR_A (start), 435}/*-------------------------< CLRACK >---------------------------*/,{ 436 /* 437 * Terminate possible pending message phase. 438 */ 439 SCR_CLR (SCR_ACK), 440 0, 441 SCR_JUMP, 442 PADDR_A (dispatch), 443}/*-------------------------< DISP_STATUS >----------------------*/,{ 444 /* 445 * Anticipate STATUS phase. 446 * 447 * Does spare 3 SCRIPTS instructions when we have 448 * completed the INPUT of the data. 449 */ 450 SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS)), 451 PADDR_A (status), 452 SCR_JUMP, 453 PADDR_A (dispatch), 454}/*-------------------------< DATAI_DONE >-----------------------*/,{ 455 /* 456 * If the device still wants to send us data, 457 * we must count the extra bytes. 458 */ 459 SCR_JUMP ^ IFTRUE (WHEN (SCR_DATA_IN)), 460 PADDR_B (data_ovrun), 461 /* 462 * If the SWIDE is not full, jump to dispatcher. 463 * We anticipate a STATUS phase. 464 */ 465 SCR_FROM_REG (scntl2), 466 0, 467 SCR_JUMP ^ IFFALSE (MASK (WSR, WSR)), 468 PADDR_A (disp_status), 469 /* 470 * The SWIDE is full. 471 * Clear this condition. 472 */ 473 SCR_REG_REG (scntl2, SCR_OR, WSR), 474 0, 475 /* 476 * We are expecting an IGNORE RESIDUE message 477 * from the device, otherwise we are in data 478 * overrun condition. Check against MSG_IN phase. 479 */ 480 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_IN)), 481 SIR_SWIDE_OVERRUN, 482 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)), 483 PADDR_A (disp_status), 484 /* 485 * We are in MSG_IN phase, 486 * Read the first byte of the message. 487 * If it is not an IGNORE RESIDUE message, 488 * signal overrun and jump to message 489 * processing. 490 */ 491 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 492 HADDR_1 (msgin[0]), 493 SCR_INT ^ IFFALSE (DATA (M_IGN_RESIDUE)), 494 SIR_SWIDE_OVERRUN, 495 SCR_JUMP ^ IFFALSE (DATA (M_IGN_RESIDUE)), 496 PADDR_A (msg_in2), 497 /* 498 * We got the message we expected. 499 * Read the 2nd byte, and jump to dispatcher. 500 */ 501 SCR_CLR (SCR_ACK), 502 0, 503 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 504 HADDR_1 (msgin[1]), 505 SCR_CLR (SCR_ACK), 506 0, 507 SCR_JUMP, 508 PADDR_A (disp_status), 509}/*-------------------------< DATAO_DONE >-----------------------*/,{ 510 /* 511 * If the device wants us to send more data, 512 * we must count the extra bytes. 513 */ 514 SCR_JUMP ^ IFTRUE (WHEN (SCR_DATA_OUT)), 515 PADDR_B (data_ovrun), 516 /* 517 * If the SODL is not full jump to dispatcher. 518 * We anticipate a STATUS phase. 519 */ 520 SCR_FROM_REG (scntl2), 521 0, 522 SCR_JUMP ^ IFFALSE (MASK (WSS, WSS)), 523 PADDR_A (disp_status), 524 /* 525 * The SODL is full, clear this condition. 526 */ 527 SCR_REG_REG (scntl2, SCR_OR, WSS), 528 0, 529 /* 530 * And signal a DATA UNDERRUN condition 531 * to the C code. 532 */ 533 SCR_INT, 534 SIR_SODL_UNDERRUN, 535 SCR_JUMP, 536 PADDR_A (dispatch), 537}/*-------------------------< DATAI_PHASE >----------------------*/,{ 538 SCR_RETURN, 539 0, 540}/*-------------------------< DATAO_PHASE >----------------------*/,{ 541 SCR_RETURN, 542 0, 543}/*-------------------------< MSG_IN >---------------------------*/,{ 544 /* 545 * Get the first byte of the message. 546 * 547 * The script processor doesn't negate the 548 * ACK signal after this transfer. 549 */ 550 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 551 HADDR_1 (msgin[0]), 552}/*-------------------------< MSG_IN2 >--------------------------*/,{ 553 /* 554 * Check first against 1 byte messages 555 * that we handle from SCRIPTS. 556 */ 557 SCR_JUMP ^ IFTRUE (DATA (M_COMPLETE)), 558 PADDR_A (complete), 559 SCR_JUMP ^ IFTRUE (DATA (M_DISCONNECT)), 560 PADDR_A (disconnect), 561 SCR_JUMP ^ IFTRUE (DATA (M_SAVE_DP)), 562 PADDR_A (save_dp), 563 SCR_JUMP ^ IFTRUE (DATA (M_RESTORE_DP)), 564 PADDR_A (restore_dp), 565 /* 566 * We handle all other messages from the 567 * C code, so no need to waste on-chip RAM 568 * for those ones. 569 */ 570 SCR_JUMP, 571 PADDR_B (msg_in_etc), 572}/*-------------------------< STATUS >---------------------------*/,{ 573 /* 574 * get the status 575 */ 576 SCR_MOVE_ABS (1) ^ SCR_STATUS, 577 HADDR_1 (scratch), 578#ifdef SYM_CONF_IARB_SUPPORT 579 /* 580 * If STATUS is not GOOD, clear IMMEDIATE ARBITRATION, 581 * since we may have to tamper the start queue from 582 * the C code. 583 */ 584 SCR_JUMPR ^ IFTRUE (DATA (S_GOOD)), 585 8, 586 SCR_REG_REG (scntl1, SCR_AND, ~IARB), 587 0, 588#endif 589 /* 590 * save status to scsi_status. 591 * mark as complete. 592 */ 593 SCR_TO_REG (SS_REG), 594 0, 595 SCR_LOAD_REG (HS_REG, HS_COMPLETE), 596 0, 597 /* 598 * Anticipate the MESSAGE PHASE for 599 * the TASK COMPLETE message. 600 */ 601 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)), 602 PADDR_A (msg_in), 603 SCR_JUMP, 604 PADDR_A (dispatch), 605}/*-------------------------< COMPLETE >-------------------------*/,{ 606 /* 607 * Complete message. 608 * 609 * Copy the data pointer to LASTP. 610 */ 611 SCR_STORE_REL (temp, 4), 612 offsetof (struct sym_ccb, phys.head.lastp), 613 /* 614 * When we terminate the cycle by clearing ACK, 615 * the target may disconnect immediately. 616 * 617 * We don't want to be told of an "unexpected disconnect", 618 * so we disable this feature. 619 */ 620 SCR_REG_REG (scntl2, SCR_AND, 0x7f), 621 0, 622 /* 623 * Terminate cycle ... 624 */ 625 SCR_CLR (SCR_ACK|SCR_ATN), 626 0, 627 /* 628 * ... and wait for the disconnect. 629 */ 630 SCR_WAIT_DISC, 631 0, 632}/*-------------------------< COMPLETE2 >------------------------*/,{ 633 /* 634 * Save host status. 635 */ 636 SCR_STORE_REL (scr0, 4), 637 offsetof (struct sym_ccb, phys.head.status), 638 /* 639 * Some bridges may reorder DMA writes to memory. 640 * We donnot want the CPU to deal with completions 641 * without all the posted write having been flushed 642 * to memory. This DUMMY READ should flush posted 643 * buffers prior to the CPU having to deal with 644 * completions. 645 */ 646 SCR_LOAD_REL (scr0, 4), /* DUMMY READ */ 647 offsetof (struct sym_ccb, phys.head.status), 648 649 /* 650 * If command resulted in not GOOD status, 651 * call the C code if needed. 652 */ 653 SCR_FROM_REG (SS_REG), 654 0, 655 SCR_CALL ^ IFFALSE (DATA (S_GOOD)), 656 PADDR_B (bad_status), 657 /* 658 * If we performed an auto-sense, call 659 * the C code to synchronyze task aborts 660 * with UNIT ATTENTION conditions. 661 */ 662 SCR_FROM_REG (HF_REG), 663 0, 664 SCR_JUMPR ^ IFTRUE (MASK (0 ,(HF_SENSE|HF_EXT_ERR))), 665 16, 666}/*-------------------------< COMPLETE_ERROR >-------------------*/,{ 667 SCR_LOAD_ABS (scratcha, 4), 668 PADDR_B (startpos), 669 SCR_INT, 670 SIR_COMPLETE_ERROR, 671}/*-------------------------< DONE >-----------------------------*/,{ 672 /* 673 * Copy the DSA to the DONE QUEUE and 674 * signal completion to the host. 675 * If we are interrupted between DONE 676 * and DONE_END, we must reset, otherwise 677 * the completed CCB may be lost. 678 */ 679 SCR_STORE_ABS (dsa, 4), 680 PADDR_B (saved_dsa), 681 SCR_LOAD_ABS (dsa, 4), 682 PADDR_B (done_pos), 683 SCR_LOAD_ABS (scratcha, 4), 684 PADDR_B (saved_dsa), 685 SCR_STORE_REL (scratcha, 4), 686 0, 687 /* 688 * The instruction below reads the DONE QUEUE next 689 * free position from memory. 690 * In addition it ensures that all PCI posted writes 691 * are flushed and so the DSA value of the done 692 * CCB is visible by the CPU before INTFLY is raised. 693 */ 694 SCR_LOAD_REL (temp, 4), 695 4, 696 SCR_INT_FLY, 697 0, 698 SCR_STORE_ABS (temp, 4), 699 PADDR_B (done_pos), 700}/*-------------------------< DONE_END >-------------------------*/,{ 701 SCR_JUMP, 702 PADDR_A (start), 703}/*-------------------------< SAVE_DP >--------------------------*/,{ 704 /* 705 * Clear ACK immediately. 706 * No need to delay it. 707 */ 708 SCR_CLR (SCR_ACK), 709 0, 710 /* 711 * Keep track we received a SAVE DP, so 712 * we will switch to the other PM context 713 * on the next PM since the DP may point 714 * to the current PM context. 715 */ 716 SCR_REG_REG (HF_REG, SCR_OR, HF_DP_SAVED), 717 0, 718 /* 719 * SAVE_DP message: 720 * Copy the data pointer to SAVEP. 721 */ 722 SCR_STORE_REL (temp, 4), 723 offsetof (struct sym_ccb, phys.head.savep), 724 SCR_JUMP, 725 PADDR_A (dispatch), 726}/*-------------------------< RESTORE_DP >-----------------------*/,{ 727 /* 728 * RESTORE_DP message: 729 * Copy SAVEP to actual data pointer. 730 */ 731 SCR_LOAD_REL (temp, 4), 732 offsetof (struct sym_ccb, phys.head.savep), 733 SCR_JUMP, 734 PADDR_A (clrack), 735}/*-------------------------< DISCONNECT >-----------------------*/,{ 736 /* 737 * DISCONNECTing ... 738 * 739 * disable the "unexpected disconnect" feature, 740 * and remove the ACK signal. 741 */ 742 SCR_REG_REG (scntl2, SCR_AND, 0x7f), 743 0, 744 SCR_CLR (SCR_ACK|SCR_ATN), 745 0, 746 /* 747 * Wait for the disconnect. 748 */ 749 SCR_WAIT_DISC, 750 0, 751 /* 752 * Status is: DISCONNECTED. 753 */ 754 SCR_LOAD_REG (HS_REG, HS_DISCONNECT), 755 0, 756 /* 757 * Save host status. 758 */ 759 SCR_STORE_REL (scr0, 4), 760 offsetof (struct sym_ccb, phys.head.status), 761 /* 762 * If QUIRK_AUTOSAVE is set, 763 * do an "save pointer" operation. 764 */ 765 SCR_FROM_REG (QU_REG), 766 0, 767 SCR_JUMP ^ IFFALSE (MASK (SYM_QUIRK_AUTOSAVE, SYM_QUIRK_AUTOSAVE)), 768 PADDR_A (start), 769 /* 770 * like SAVE_DP message: 771 * Remember we saved the data pointer. 772 * Copy data pointer to SAVEP. 773 */ 774 SCR_REG_REG (HF_REG, SCR_OR, HF_DP_SAVED), 775 0, 776 SCR_STORE_REL (temp, 4), 777 offsetof (struct sym_ccb, phys.head.savep), 778 SCR_JUMP, 779 PADDR_A (start), 780}/*-------------------------< IDLE >-----------------------------*/,{ 781 /* 782 * Nothing to do? 783 * Switch the LED off and wait for reselect. 784 * Will be patched with a NO_OP if LED 785 * not needed or not desired. 786 */ 787 SCR_REG_REG (gpreg, SCR_OR, 0x01), 788 0, 789#ifdef SYM_CONF_IARB_SUPPORT 790 SCR_JUMPR, 791 8, 792#endif 793}/*-------------------------< UNGETJOB >-------------------------*/,{ 794#ifdef SYM_CONF_IARB_SUPPORT 795 /* 796 * Set IMMEDIATE ARBITRATION, for the next time. 797 * This will give us better chance to win arbitration 798 * for the job we just wanted to do. 799 */ 800 SCR_REG_REG (scntl1, SCR_OR, IARB), 801 0, 802#endif 803 /* 804 * We are not able to restart the SCRIPTS if we are 805 * interrupted and these instruction haven't been 806 * all executed. BTW, this is very unlikely to 807 * happen, but we check that from the C code. 808 */ 809 SCR_LOAD_REG (dsa, 0xff), 810 0, 811 SCR_STORE_ABS (scratcha, 4), 812 PADDR_B (startpos), 813}/*-------------------------< RESELECT >-------------------------*/,{ 814 /* 815 * Make sure we are in initiator mode. 816 */ 817 SCR_CLR (SCR_TRG), 818 0, 819 /* 820 * Sleep waiting for a reselection. 821 */ 822 SCR_WAIT_RESEL, 823 PADDR_A(start), 824}/*-------------------------< RESELECTED >-----------------------*/,{ 825 /* 826 * Switch the LED on. 827 * Will be patched with a NO_OP if LED 828 * not needed or not desired. 829 */ 830 SCR_REG_REG (gpreg, SCR_AND, 0xfe), 831 0, 832 /* 833 * load the target id into the sdid 834 */ 835 SCR_REG_SFBR (ssid, SCR_AND, 0x8F), 836 0, 837 SCR_TO_REG (sdid), 838 0, 839 /* 840 * Load the target control block address 841 */ 842 SCR_LOAD_ABS (dsa, 4), 843 PADDR_B (targtbl), 844 SCR_SFBR_REG (dsa, SCR_SHL, 0), 845 0, 846 SCR_REG_REG (dsa, SCR_SHL, 0), 847 0, 848 SCR_REG_REG (dsa, SCR_AND, 0x3c), 849 0, 850 SCR_LOAD_REL (dsa, 4), 851 0, 852 /* 853 * We expect MESSAGE IN phase. 854 * If not, get help from the C code. 855 */ 856 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_IN)), 857 SIR_RESEL_NO_MSG_IN, 858 /* 859 * Load the legacy synchronous transfer registers. 860 */ 861 SCR_LOAD_REL (scntl3, 1), 862 offsetof(struct sym_tcb, head.wval), 863 SCR_LOAD_REL (sxfer, 1), 864 offsetof(struct sym_tcb, head.sval), 865}/*-------------------------< RESEL_SCNTL4 >---------------------*/,{ 866 /* 867 * The C1010 uses a new synchronous timing scheme. 868 * Will be patched with a NO_OP if not a C1010. 869 */ 870 SCR_LOAD_REL (scntl4, 1), 871 offsetof(struct sym_tcb, head.uval), 872 /* 873 * Get the IDENTIFY message. 874 */ 875 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 876 HADDR_1 (msgin), 877 /* 878 * If IDENTIFY LUN #0, use a faster path 879 * to find the LCB structure. 880 */ 881 SCR_JUMP ^ IFTRUE (MASK (0x80, 0xbf)), 882 PADDR_A (resel_lun0), 883 /* 884 * If message isn't an IDENTIFY, 885 * tell the C code about. 886 */ 887 SCR_INT ^ IFFALSE (MASK (0x80, 0x80)), 888 SIR_RESEL_NO_IDENTIFY, 889 /* 890 * It is an IDENTIFY message, 891 * Load the LUN control block address. 892 */ 893 SCR_LOAD_REL (dsa, 4), 894 offsetof(struct sym_tcb, head.luntbl_sa), 895 SCR_SFBR_REG (dsa, SCR_SHL, 0), 896 0, 897 SCR_REG_REG (dsa, SCR_SHL, 0), 898 0, 899 SCR_REG_REG (dsa, SCR_AND, 0xfc), 900 0, 901 SCR_LOAD_REL (dsa, 4), 902 0, 903 SCR_JUMPR, 904 8, 905}/*-------------------------< RESEL_LUN0 >-----------------------*/,{ 906 /* 907 * LUN 0 special case (but usual one :)) 908 */ 909 SCR_LOAD_REL (dsa, 4), 910 offsetof(struct sym_tcb, head.lun0_sa), 911 /* 912 * Jump indirectly to the reselect action for this LUN. 913 */ 914 SCR_LOAD_REL (temp, 4), 915 offsetof(struct sym_lcb, head.resel_sa), 916 SCR_RETURN, 917 0, 918 /* In normal situations, we jump to RESEL_TAG or RESEL_NO_TAG */ 919}/*-------------------------< RESEL_TAG >------------------------*/,{ 920 /* 921 * ACK the IDENTIFY or TAG previously received. 922 */ 923 SCR_CLR (SCR_ACK), 924 0, 925 /* 926 * It shall be a tagged command. 927 * Read SIMPLE+TAG. 928 * The C code will deal with errors. 929 * Agressive optimization, is'nt it? :) 930 */ 931 SCR_MOVE_ABS (2) ^ SCR_MSG_IN, 932 HADDR_1 (msgin), 933 /* 934 * Load the pointer to the tagged task 935 * table for this LUN. 936 */ 937 SCR_LOAD_REL (dsa, 4), 938 offsetof(struct sym_lcb, head.itlq_tbl_sa), 939 /* 940 * The SIDL still contains the TAG value. 941 * Agressive optimization, isn't it? :):) 942 */ 943 SCR_REG_SFBR (sidl, SCR_SHL, 0), 944 0, 945#if SYM_CONF_MAX_TASK*4 > 512 946 SCR_JUMPR ^ IFFALSE (CARRYSET), 947 8, 948 SCR_REG_REG (dsa1, SCR_OR, 2), 949 0, 950 SCR_REG_REG (sfbr, SCR_SHL, 0), 951 0, 952 SCR_JUMPR ^ IFFALSE (CARRYSET), 953 8, 954 SCR_REG_REG (dsa1, SCR_OR, 1), 955 0, 956#elif SYM_CONF_MAX_TASK*4 > 256 957 SCR_JUMPR ^ IFFALSE (CARRYSET), 958 8, 959 SCR_REG_REG (dsa1, SCR_OR, 1), 960 0, 961#endif 962 /* 963 * Retrieve the DSA of this task. 964 * JUMP indirectly to the restart point of the CCB. 965 */ 966 SCR_SFBR_REG (dsa, SCR_AND, 0xfc), 967 0, 968 SCR_LOAD_REL (dsa, 4), 969 0, 970 SCR_LOAD_REL (temp, 4), 971 offsetof(struct sym_ccb, phys.head.go.restart), 972 SCR_RETURN, 973 0, 974 /* In normal situations we branch to RESEL_DSA */ 975}/*-------------------------< RESEL_DSA >------------------------*/,{ 976 /* 977 * ACK the IDENTIFY or TAG previously received. 978 */ 979 SCR_CLR (SCR_ACK), 980 0, 981}/*-------------------------< RESEL_DSA1 >-----------------------*/,{ 982 /* 983 * load the savep (saved pointer) into 984 * the actual data pointer. 985 */ 986 SCR_LOAD_REL (temp, 4), 987 offsetof (struct sym_ccb, phys.head.savep), 988 /* 989 * Initialize the status registers 990 */ 991 SCR_LOAD_REL (scr0, 4), 992 offsetof (struct sym_ccb, phys.head.status), 993 /* 994 * Jump to dispatcher. 995 */ 996 SCR_JUMP, 997 PADDR_A (dispatch), 998}/*-------------------------< RESEL_NO_TAG >---------------------*/,{ 999 /* 1000 * Load the DSA with the unique ITL task. 1001 */ 1002 SCR_LOAD_REL (dsa, 4), 1003 offsetof(struct sym_lcb, head.itl_task_sa), 1004 /* 1005 * JUMP indirectly to the restart point of the CCB. 1006 */ 1007 SCR_LOAD_REL (temp, 4), 1008 offsetof(struct sym_ccb, phys.head.go.restart), 1009 SCR_RETURN, 1010 0, 1011 /* In normal situations we branch to RESEL_DSA */ 1012}/*-------------------------< DATA_IN >--------------------------*/,{ 1013/* 1014 * Because the size depends on the 1015 * #define SYM_CONF_MAX_SG parameter, 1016 * it is filled in at runtime. 1017 * 1018 * ##===========< i=0; i<SYM_CONF_MAX_SG >========= 1019 * || SCR_CHMOV_TBL ^ SCR_DATA_IN, 1020 * || offsetof (struct sym_dsb, data[ i]), 1021 * ##========================================== 1022 */ 10230 1024}/*-------------------------< DATA_IN2 >-------------------------*/,{ 1025 SCR_CALL, 1026 PADDR_A (datai_done), 1027 SCR_JUMP, 1028 PADDR_B (data_ovrun), 1029}/*-------------------------< DATA_OUT >-------------------------*/,{ 1030/* 1031 * Because the size depends on the 1032 * #define SYM_CONF_MAX_SG parameter, 1033 * it is filled in at runtime. 1034 * 1035 * ##===========< i=0; i<SYM_CONF_MAX_SG >========= 1036 * || SCR_CHMOV_TBL ^ SCR_DATA_OUT, 1037 * || offsetof (struct sym_dsb, data[ i]), 1038 * ##========================================== 1039 */ 10400 1041}/*-------------------------< DATA_OUT2 >------------------------*/,{ 1042 SCR_CALL, 1043 PADDR_A (datao_done), 1044 SCR_JUMP, 1045 PADDR_B (data_ovrun), 1046}/*-------------------------< PM0_DATA >-------------------------*/,{ 1047 /* 1048 * Read our host flags to SFBR, so we will be able 1049 * to check against the data direction we expect. 1050 */ 1051 SCR_FROM_REG (HF_REG), 1052 0, 1053 /* 1054 * Check against actual DATA PHASE. 1055 */ 1056 SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)), 1057 PADDR_A (pm0_data_out), 1058 /* 1059 * Actual phase is DATA IN. 1060 * Check against expected direction. 1061 */ 1062 SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)), 1063 PADDR_B (data_ovrun), 1064 /* 1065 * Keep track we are moving data from the 1066 * PM0 DATA mini-script. 1067 */ 1068 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM0), 1069 0, 1070 /* 1071 * Move the data to memory. 1072 */ 1073 SCR_CHMOV_TBL ^ SCR_DATA_IN, 1074 offsetof (struct sym_ccb, phys.pm0.sg), 1075 SCR_JUMP, 1076 PADDR_A (pm0_data_end), 1077}/*-------------------------< PM0_DATA_OUT >---------------------*/,{ 1078 /* 1079 * Actual phase is DATA OUT. 1080 * Check against expected direction. 1081 */ 1082 SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)), 1083 PADDR_B (data_ovrun), 1084 /* 1085 * Keep track we are moving data from the 1086 * PM0 DATA mini-script. 1087 */ 1088 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM0), 1089 0, 1090 /* 1091 * Move the data from memory. 1092 */ 1093 SCR_CHMOV_TBL ^ SCR_DATA_OUT, 1094 offsetof (struct sym_ccb, phys.pm0.sg), 1095}/*-------------------------< PM0_DATA_END >---------------------*/,{ 1096 /* 1097 * Clear the flag that told we were moving 1098 * data from the PM0 DATA mini-script. 1099 */ 1100 SCR_REG_REG (HF_REG, SCR_AND, (~HF_IN_PM0)), 1101 0, 1102 /* 1103 * Return to the previous DATA script which 1104 * is guaranteed by design (if no bug) to be 1105 * the main DATA script for this transfer. 1106 */ 1107 SCR_LOAD_REL (temp, 4), 1108 offsetof (struct sym_ccb, phys.pm0.ret), 1109 SCR_RETURN, 1110 0, 1111}/*-------------------------< PM1_DATA >-------------------------*/,{ 1112 /* 1113 * Read our host flags to SFBR, so we will be able 1114 * to check against the data direction we expect. 1115 */ 1116 SCR_FROM_REG (HF_REG), 1117 0, 1118 /* 1119 * Check against actual DATA PHASE. 1120 */ 1121 SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)), 1122 PADDR_A (pm1_data_out), 1123 /* 1124 * Actual phase is DATA IN. 1125 * Check against expected direction. 1126 */ 1127 SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)), 1128 PADDR_B (data_ovrun), 1129 /* 1130 * Keep track we are moving data from the 1131 * PM1 DATA mini-script. 1132 */ 1133 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM1), 1134 0, 1135 /* 1136 * Move the data to memory. 1137 */ 1138 SCR_CHMOV_TBL ^ SCR_DATA_IN, 1139 offsetof (struct sym_ccb, phys.pm1.sg), 1140 SCR_JUMP, 1141 PADDR_A (pm1_data_end), 1142}/*-------------------------< PM1_DATA_OUT >---------------------*/,{ 1143 /* 1144 * Actual phase is DATA OUT. 1145 * Check against expected direction. 1146 */ 1147 SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)), 1148 PADDR_B (data_ovrun), 1149 /* 1150 * Keep track we are moving data from the 1151 * PM1 DATA mini-script. 1152 */ 1153 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM1), 1154 0, 1155 /* 1156 * Move the data from memory. 1157 */ 1158 SCR_CHMOV_TBL ^ SCR_DATA_OUT, 1159 offsetof (struct sym_ccb, phys.pm1.sg), 1160}/*-------------------------< PM1_DATA_END >---------------------*/,{ 1161 /* 1162 * Clear the flag that told we were moving 1163 * data from the PM1 DATA mini-script. 1164 */ 1165 SCR_REG_REG (HF_REG, SCR_AND, (~HF_IN_PM1)), 1166 0, 1167 /* 1168 * Return to the previous DATA script which 1169 * is guaranteed by design (if no bug) to be 1170 * the main DATA script for this transfer. 1171 */ 1172 SCR_LOAD_REL (temp, 4), 1173 offsetof (struct sym_ccb, phys.pm1.ret), 1174 SCR_RETURN, 1175 0, 1176}/*-------------------------<>-----------------------------------*/ 1177}; 1178 1179static struct SYM_FWB_SCR SYM_FWB_SCR = { 1180/*--------------------------< START64 >--------------------------*/ { 1181 /* 1182 * SCRIPT entry point for the 895A, 896 and 1010. 1183 * For now, there is no specific stuff for those 1184 * chips at this point, but this may come. 1185 */ 1186 SCR_JUMP, 1187 PADDR_A (init), 1188}/*-------------------------< NO_DATA >--------------------------*/,{ 1189 SCR_JUMP, 1190 PADDR_B (data_ovrun), 1191}/*-------------------------< SEL_FOR_ABORT >--------------------*/,{ 1192 /* 1193 * We are jumped here by the C code, if we have 1194 * some target to reset or some disconnected 1195 * job to abort. Since error recovery is a serious 1196 * busyness, we will really reset the SCSI BUS, if 1197 * case of a SCSI interrupt occuring in this path. 1198 */ 1199 1200 /* 1201 * Set initiator mode. 1202 */ 1203 SCR_CLR (SCR_TRG), 1204 0, 1205 /* 1206 * And try to select this target. 1207 */ 1208 SCR_SEL_TBL_ATN ^ offsetof (struct sym_hcb, abrt_sel), 1209 PADDR_A (reselect), 1210 /* 1211 * Wait for the selection to complete or 1212 * the selection to time out. 1213 */ 1214 SCR_JUMPR ^ IFFALSE (WHEN (SCR_MSG_OUT)), 1215 -8, 1216 /* 1217 * Call the C code. 1218 */ 1219 SCR_INT, 1220 SIR_TARGET_SELECTED, 1221 /* 1222 * The C code should let us continue here. 1223 * Send the 'kiss of death' message. 1224 * We expect an immediate disconnect once 1225 * the target has eaten the message. 1226 */ 1227 SCR_REG_REG (scntl2, SCR_AND, 0x7f), 1228 0, 1229 SCR_MOVE_TBL ^ SCR_MSG_OUT, 1230 offsetof (struct sym_hcb, abrt_tbl), 1231 SCR_CLR (SCR_ACK|SCR_ATN), 1232 0, 1233 SCR_WAIT_DISC, 1234 0, 1235 /* 1236 * Tell the C code that we are done. 1237 */ 1238 SCR_INT, 1239 SIR_ABORT_SENT, 1240}/*-------------------------< SEL_FOR_ABORT_1 >------------------*/,{ 1241 /* 1242 * Jump at scheduler. 1243 */ 1244 SCR_JUMP, 1245 PADDR_A (start), 1246}/*-------------------------< MSG_IN_ETC >-----------------------*/,{ 1247 /* 1248 * If it is an EXTENDED (variable size message) 1249 * Handle it. 1250 */ 1251 SCR_JUMP ^ IFTRUE (DATA (M_EXTENDED)), 1252 PADDR_B (msg_extended), 1253 /* 1254 * Let the C code handle any other 1255 * 1 byte message. 1256 */ 1257 SCR_JUMP ^ IFTRUE (MASK (0x00, 0xf0)), 1258 PADDR_B (msg_received), 1259 SCR_JUMP ^ IFTRUE (MASK (0x10, 0xf0)), 1260 PADDR_B (msg_received), 1261 /* 1262 * We donnot handle 2 bytes messages from SCRIPTS. 1263 * So, let the C code deal with these ones too. 1264 */ 1265 SCR_INT ^ IFFALSE (MASK (0x20, 0xf0)), 1266 SIR_MSG_WEIRD, 1267 SCR_CLR (SCR_ACK), 1268 0, 1269 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 1270 HADDR_1 (msgin[1]), 1271}/*-------------------------< MSG_RECEIVED >---------------------*/,{ 1272 SCR_LOAD_REL (scratcha, 4), /* DUMMY READ */ 1273 0, 1274 SCR_INT, 1275 SIR_MSG_RECEIVED, 1276}/*-------------------------< MSG_WEIRD_SEEN >-------------------*/,{ 1277 SCR_LOAD_REL (scratcha, 4), /* DUMMY READ */ 1278 0, 1279 SCR_INT, 1280 SIR_MSG_WEIRD, 1281}/*-------------------------< MSG_EXTENDED >---------------------*/,{ 1282 /* 1283 * Clear ACK and get the next byte 1284 * assumed to be the message length. 1285 */ 1286 SCR_CLR (SCR_ACK), 1287 0, 1288 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 1289 HADDR_1 (msgin[1]), 1290 /* 1291 * Try to catch some unlikely situations as 0 length 1292 * or too large the length. 1293 */ 1294 SCR_JUMP ^ IFTRUE (DATA (0)), 1295 PADDR_B (msg_weird_seen), 1296 SCR_TO_REG (scratcha), 1297 0, 1298 SCR_REG_REG (sfbr, SCR_ADD, (256-8)), 1299 0, 1300 SCR_JUMP ^ IFTRUE (CARRYSET), 1301 PADDR_B (msg_weird_seen), 1302 /* 1303 * We donnot handle extended messages from SCRIPTS. 1304 * Read the amount of data correponding to the 1305 * message length and call the C code. 1306 */ 1307 SCR_STORE_REL (scratcha, 1), 1308 offsetof (struct sym_dsb, smsg_ext.size), 1309 SCR_CLR (SCR_ACK), 1310 0, 1311 SCR_MOVE_TBL ^ SCR_MSG_IN, 1312 offsetof (struct sym_dsb, smsg_ext), 1313 SCR_JUMP, 1314 PADDR_B (msg_received), 1315}/*-------------------------< MSG_BAD >--------------------------*/,{ 1316 /* 1317 * unimplemented message - reject it. 1318 */ 1319 SCR_INT, 1320 SIR_REJECT_TO_SEND, 1321 SCR_SET (SCR_ATN), 1322 0, 1323 SCR_JUMP, 1324 PADDR_A (clrack), 1325}/*-------------------------< MSG_WEIRD >------------------------*/,{ 1326 /* 1327 * weird message received 1328 * ignore all MSG IN phases and reject it. 1329 */ 1330 SCR_INT, 1331 SIR_REJECT_TO_SEND, 1332 SCR_SET (SCR_ATN), 1333 0, 1334}/*-------------------------< MSG_WEIRD1 >-----------------------*/,{ 1335 SCR_CLR (SCR_ACK), 1336 0, 1337 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)), 1338 PADDR_A (dispatch), 1339 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 1340 HADDR_1 (scratch), 1341 SCR_JUMP, 1342 PADDR_B (msg_weird1), 1343}/*-------------------------< WDTR_RESP >------------------------*/,{ 1344 /* 1345 * let the target fetch our answer. 1346 */ 1347 SCR_SET (SCR_ATN), 1348 0, 1349 SCR_CLR (SCR_ACK), 1350 0, 1351 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)), 1352 PADDR_B (nego_bad_phase), 1353}/*-------------------------< SEND_WDTR >------------------------*/,{ 1354 /* 1355 * Send the M_X_WIDE_REQ 1356 */ 1357 SCR_MOVE_ABS (4) ^ SCR_MSG_OUT, 1358 HADDR_1 (msgout), 1359 SCR_JUMP, 1360 PADDR_B (msg_out_done), 1361}/*-------------------------< SDTR_RESP >------------------------*/,{ 1362 /* 1363 * let the target fetch our answer. 1364 */ 1365 SCR_SET (SCR_ATN), 1366 0, 1367 SCR_CLR (SCR_ACK), 1368 0, 1369 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)), 1370 PADDR_B (nego_bad_phase), 1371}/*-------------------------< SEND_SDTR >------------------------*/,{ 1372 /* 1373 * Send the M_X_SYNC_REQ 1374 */ 1375 SCR_MOVE_ABS (5) ^ SCR_MSG_OUT, 1376 HADDR_1 (msgout), 1377 SCR_JUMP, 1378 PADDR_B (msg_out_done), 1379}/*-------------------------< PPR_RESP >-------------------------*/,{ 1380 /* 1381 * let the target fetch our answer. 1382 */ 1383 SCR_SET (SCR_ATN), 1384 0, 1385 SCR_CLR (SCR_ACK), 1386 0, 1387 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)), 1388 PADDR_B (nego_bad_phase), 1389}/*-------------------------< SEND_PPR >-------------------------*/,{ 1390 /* 1391 * Send the M_X_PPR_REQ 1392 */ 1393 SCR_MOVE_ABS (8) ^ SCR_MSG_OUT, 1394 HADDR_1 (msgout), 1395 SCR_JUMP, 1396 PADDR_B (msg_out_done), 1397}/*-------------------------< NEGO_BAD_PHASE >-------------------*/,{ 1398 SCR_INT, 1399 SIR_NEGO_PROTO, 1400 SCR_JUMP, 1401 PADDR_A (dispatch), 1402}/*-------------------------< MSG_OUT >--------------------------*/,{ 1403 /* 1404 * The target requests a message. 1405 * We donnot send messages that may 1406 * require the device to go to bus free. 1407 */ 1408 SCR_MOVE_ABS (1) ^ SCR_MSG_OUT, 1409 HADDR_1 (msgout), 1410 /* 1411 * ... wait for the next phase 1412 * if it's a message out, send it again, ... 1413 */ 1414 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_OUT)), 1415 PADDR_B (msg_out), 1416}/*-------------------------< MSG_OUT_DONE >---------------------*/,{ 1417 /* 1418 * Let the C code be aware of the 1419 * sent message and clear the message. 1420 */ 1421 SCR_INT, 1422 SIR_MSG_OUT_DONE, 1423 /* 1424 * ... and process the next phase 1425 */ 1426 SCR_JUMP, 1427 PADDR_A (dispatch), 1428}/*-------------------------< DATA_OVRUN >-----------------------*/,{ 1429 /* 1430 * Use scratcha to count the extra bytes. 1431 */ 1432 SCR_LOAD_ABS (scratcha, 4), 1433 PADDR_B (zero), 1434}/*-------------------------< DATA_OVRUN1 >----------------------*/,{ 1435 /* 1436 * The target may want to transfer too much data. 1437 * 1438 * If phase is DATA OUT write 1 byte and count it. 1439 */ 1440 SCR_JUMPR ^ IFFALSE (WHEN (SCR_DATA_OUT)), 1441 16, 1442 SCR_CHMOV_ABS (1) ^ SCR_DATA_OUT, 1443 HADDR_1 (scratch), 1444 SCR_JUMP, 1445 PADDR_B (data_ovrun2), 1446 /* 1447 * If WSR is set, clear this condition, and 1448 * count this byte. 1449 */ 1450 SCR_FROM_REG (scntl2), 1451 0, 1452 SCR_JUMPR ^ IFFALSE (MASK (WSR, WSR)), 1453 16, 1454 SCR_REG_REG (scntl2, SCR_OR, WSR), 1455 0, 1456 SCR_JUMP, 1457 PADDR_B (data_ovrun2), 1458 /* 1459 * Finally check against DATA IN phase. 1460 * Signal data overrun to the C code 1461 * and jump to dispatcher if not so. 1462 * Read 1 byte otherwise and count it. 1463 */ 1464 SCR_JUMPR ^ IFTRUE (WHEN (SCR_DATA_IN)), 1465 16, 1466 SCR_INT, 1467 SIR_DATA_OVERRUN, 1468 SCR_JUMP, 1469 PADDR_A (dispatch), 1470 SCR_CHMOV_ABS (1) ^ SCR_DATA_IN, 1471 HADDR_1 (scratch), 1472}/*-------------------------< DATA_OVRUN2 >----------------------*/,{ 1473 /* 1474 * Count this byte. 1475 * This will allow to return a negative 1476 * residual to user. 1477 */ 1478 SCR_REG_REG (scratcha, SCR_ADD, 0x01), 1479 0, 1480 SCR_REG_REG (scratcha1, SCR_ADDC, 0), 1481 0, 1482 SCR_REG_REG (scratcha2, SCR_ADDC, 0), 1483 0, 1484 /* 1485 * .. and repeat as required. 1486 */ 1487 SCR_JUMP, 1488 PADDR_B (data_ovrun1), 1489}/*-------------------------< ABORT_RESEL >----------------------*/,{ 1490 SCR_SET (SCR_ATN), 1491 0, 1492 SCR_CLR (SCR_ACK), 1493 0, 1494 /* 1495 * send the abort/abortag/reset message 1496 * we expect an immediate disconnect 1497 */ 1498 SCR_REG_REG (scntl2, SCR_AND, 0x7f), 1499 0, 1500 SCR_MOVE_ABS (1) ^ SCR_MSG_OUT, 1501 HADDR_1 (msgout), 1502 SCR_CLR (SCR_ACK|SCR_ATN), 1503 0, 1504 SCR_WAIT_DISC, 1505 0, 1506 SCR_INT, 1507 SIR_RESEL_ABORTED, 1508 SCR_JUMP, 1509 PADDR_A (start), 1510}/*-------------------------< RESEND_IDENT >---------------------*/,{ 1511 /* 1512 * The target stays in MSG OUT phase after having acked 1513 * Identify [+ Tag [+ Extended message ]]. Targets shall 1514 * behave this way on parity error. 1515 * We must send it again all the messages. 1516 */ 1517 SCR_SET (SCR_ATN), /* Shall be asserted 2 deskew delays before the */ 1518 0, /* 1rst ACK = 90 ns. Hope the chip isn't too fast */ 1519 SCR_JUMP, 1520 PADDR_A (send_ident), 1521}/*-------------------------< IDENT_BREAK >----------------------*/,{ 1522 SCR_CLR (SCR_ATN), 1523 0, 1524 SCR_JUMP, 1525 PADDR_A (select2), 1526}/*-------------------------< IDENT_BREAK_ATN >------------------*/,{ 1527 SCR_SET (SCR_ATN), 1528 0, 1529 SCR_JUMP, 1530 PADDR_A (select2), 1531}/*-------------------------< SDATA_IN >-------------------------*/,{ 1532 SCR_CHMOV_TBL ^ SCR_DATA_IN, 1533 offsetof (struct sym_dsb, sense), 1534 SCR_CALL, 1535 PADDR_A (datai_done), 1536 SCR_JUMP, 1537 PADDR_B (data_ovrun), 1538}/*-------------------------< RESEL_BAD_LUN >--------------------*/,{ 1539 /* 1540 * Message is an IDENTIFY, but lun is unknown. 1541 * Signal problem to C code for logging the event. 1542 * Send a M_ABORT to clear all pending tasks. 1543 */ 1544 SCR_INT, 1545 SIR_RESEL_BAD_LUN, 1546 SCR_JUMP, 1547 PADDR_B (abort_resel), 1548}/*-------------------------< BAD_I_T_L >------------------------*/,{ 1549 /* 1550 * We donnot have a task for that I_T_L. 1551 * Signal problem to C code for logging the event. 1552 * Send a M_ABORT message. 1553 */ 1554 SCR_INT, 1555 SIR_RESEL_BAD_I_T_L, 1556 SCR_JUMP, 1557 PADDR_B (abort_resel), 1558}/*-------------------------< BAD_I_T_L_Q >----------------------*/,{ 1559 /* 1560 * We donnot have a task that matches the tag. 1561 * Signal problem to C code for logging the event. 1562 * Send a M_ABORTTAG message. 1563 */ 1564 SCR_INT, 1565 SIR_RESEL_BAD_I_T_L_Q, 1566 SCR_JUMP, 1567 PADDR_B (abort_resel), 1568}/*-------------------------< BAD_STATUS >-----------------------*/,{ 1569 /* 1570 * Anything different from INTERMEDIATE 1571 * CONDITION MET should be a bad SCSI status, 1572 * given that GOOD status has already been tested. 1573 * Call the C code. 1574 */ 1575 SCR_LOAD_ABS (scratcha, 4), 1576 PADDR_B (startpos), 1577 SCR_INT ^ IFFALSE (DATA (S_COND_MET)), 1578 SIR_BAD_SCSI_STATUS, 1579 SCR_RETURN, 1580 0, 1581}/*-------------------------< PM_HANDLE >------------------------*/,{ 1582 /* 1583 * Phase mismatch handling. 1584 * 1585 * Since we have to deal with 2 SCSI data pointers 1586 * (current and saved), we need at least 2 contexts. 1587 * Each context (pm0 and pm1) has a saved area, a 1588 * SAVE mini-script and a DATA phase mini-script. 1589 */ 1590 /* 1591 * Get the PM handling flags. 1592 */ 1593 SCR_FROM_REG (HF_REG), 1594 0, 1595 /* 1596 * If no flags (1rst PM for example), avoid 1597 * all the below heavy flags testing. 1598 * This makes the normal case a bit faster. 1599 */ 1600 SCR_JUMP ^ IFTRUE (MASK (0, (HF_IN_PM0 | HF_IN_PM1 | HF_DP_SAVED))), 1601 PADDR_B (pm_handle1), 1602 /* 1603 * If we received a SAVE DP, switch to the 1604 * other PM context since the savep may point 1605 * to the current PM context. 1606 */ 1607 SCR_JUMPR ^ IFFALSE (MASK (HF_DP_SAVED, HF_DP_SAVED)), 1608 8, 1609 SCR_REG_REG (sfbr, SCR_XOR, HF_ACT_PM), 1610 0, 1611 /* 1612 * If we have been interrupt in a PM DATA mini-script, 1613 * we take the return address from the corresponding 1614 * saved area. 1615 * This ensure the return address always points to the 1616 * main DATA script for this transfer. 1617 */ 1618 SCR_JUMP ^ IFTRUE (MASK (0, (HF_IN_PM0 | HF_IN_PM1))), 1619 PADDR_B (pm_handle1), 1620 SCR_JUMPR ^ IFFALSE (MASK (HF_IN_PM0, HF_IN_PM0)), 1621 16, 1622 SCR_LOAD_REL (ia, 4), 1623 offsetof(struct sym_ccb, phys.pm0.ret), 1624 SCR_JUMP, 1625 PADDR_B (pm_save), 1626 SCR_LOAD_REL (ia, 4), 1627 offsetof(struct sym_ccb, phys.pm1.ret), 1628 SCR_JUMP, 1629 PADDR_B (pm_save), 1630}/*-------------------------< PM_HANDLE1 >-----------------------*/,{ 1631 /* 1632 * Normal case. 1633 * Update the return address so that it 1634 * will point after the interrupted MOVE. 1635 */ 1636 SCR_REG_REG (ia, SCR_ADD, 8), 1637 0, 1638 SCR_REG_REG (ia1, SCR_ADDC, 0), 1639 0, 1640}/*-------------------------< PM_SAVE >--------------------------*/,{ 1641 /* 1642 * Clear all the flags that told us if we were 1643 * interrupted in a PM DATA mini-script and/or 1644 * we received a SAVE DP. 1645 */ 1646 SCR_SFBR_REG (HF_REG, SCR_AND, (~(HF_IN_PM0|HF_IN_PM1|HF_DP_SAVED))), 1647 0, 1648 /* 1649 * Choose the current PM context. 1650 */ 1651 SCR_JUMP ^ IFTRUE (MASK (HF_ACT_PM, HF_ACT_PM)), 1652 PADDR_B (pm1_save), 1653}/*-------------------------< PM0_SAVE >-------------------------*/,{ 1654 SCR_STORE_REL (ia, 4), 1655 offsetof(struct sym_ccb, phys.pm0.ret), 1656 /* 1657 * If WSR bit is set, either UA and RBC may 1658 * have to be changed whether the device wants 1659 * to ignore this residue or not. 1660 */ 1661 SCR_FROM_REG (scntl2), 1662 0, 1663 SCR_CALL ^ IFTRUE (MASK (WSR, WSR)), 1664 PADDR_B (pm_wsr_handle), 1665 /* 1666 * Save the remaining byte count, the updated 1667 * address and the return address. 1668 */ 1669 SCR_STORE_REL (rbc, 4), 1670 offsetof(struct sym_ccb, phys.pm0.sg.size), 1671 SCR_STORE_REL (ua, 4), 1672 offsetof(struct sym_ccb, phys.pm0.sg.addr), 1673 /* 1674 * Set the current pointer at the PM0 DATA mini-script. 1675 */ 1676 SCR_LOAD_ABS (temp, 4), 1677 PADDR_B (pm0_data_addr), 1678 SCR_JUMP, 1679 PADDR_A (dispatch), 1680}/*-------------------------< PM1_SAVE >-------------------------*/,{ 1681 SCR_STORE_REL (ia, 4), 1682 offsetof(struct sym_ccb, phys.pm1.ret), 1683 /* 1684 * If WSR bit is set, either UA and RBC may 1685 * have to be changed whether the device wants 1686 * to ignore this residue or not. 1687 */ 1688 SCR_FROM_REG (scntl2), 1689 0, 1690 SCR_CALL ^ IFTRUE (MASK (WSR, WSR)), 1691 PADDR_B (pm_wsr_handle), 1692 /* 1693 * Save the remaining byte count, the updated 1694 * address and the return address. 1695 */ 1696 SCR_STORE_REL (rbc, 4), 1697 offsetof(struct sym_ccb, phys.pm1.sg.size), 1698 SCR_STORE_REL (ua, 4), 1699 offsetof(struct sym_ccb, phys.pm1.sg.addr), 1700 /* 1701 * Set the current pointer at the PM1 DATA mini-script. 1702 */ 1703 SCR_LOAD_ABS (temp, 4), 1704 PADDR_B (pm1_data_addr), 1705 SCR_JUMP, 1706 PADDR_A (dispatch), 1707}/*-------------------------< PM_WSR_HANDLE >--------------------*/,{ 1708 /* 1709 * Phase mismatch handling from SCRIPT with WSR set. 1710 * Such a condition can occur if the chip wants to 1711 * execute a CHMOV(size > 1) when the WSR bit is 1712 * set and the target changes PHASE. 1713 * 1714 * We must move the residual byte to memory. 1715 * 1716 * UA contains bit 0..31 of the address to 1717 * move the residual byte. 1718 * Move it to the table indirect. 1719 */ 1720 SCR_STORE_REL (ua, 4), 1721 offsetof (struct sym_ccb, phys.wresid.addr), 1722 /* 1723 * Increment UA (move address to next position). 1724 */ 1725 SCR_REG_REG (ua, SCR_ADD, 1), 1726 0, 1727 SCR_REG_REG (ua1, SCR_ADDC, 0), 1728 0, 1729 SCR_REG_REG (ua2, SCR_ADDC, 0), 1730 0, 1731 SCR_REG_REG (ua3, SCR_ADDC, 0), 1732 0, 1733 /* 1734 * Compute SCRATCHA as: 1735 * - size to transfer = 1 byte. 1736 * - bit 24..31 = high address bit [32...39]. 1737 */ 1738 SCR_LOAD_ABS (scratcha, 4), 1739 PADDR_B (zero), 1740 SCR_REG_REG (scratcha, SCR_OR, 1), 1741 0, 1742 SCR_FROM_REG (rbc3), 1743 0, 1744 SCR_TO_REG (scratcha3), 1745 0, 1746 /* 1747 * Move this value to the table indirect. 1748 */ 1749 SCR_STORE_REL (scratcha, 4), 1750 offsetof (struct sym_ccb, phys.wresid.size), 1751 /* 1752 * Wait for a valid phase. 1753 * While testing with bogus QUANTUM drives, the C1010 1754 * sometimes raised a spurious phase mismatch with 1755 * WSR and the CHMOV(1) triggered another PM. 1756 * Waiting explicitely for the PHASE seemed to avoid 1757 * the nested phase mismatch. Btw, this didn't happen 1758 * using my IBM drives. 1759 */ 1760 SCR_JUMPR ^ IFFALSE (WHEN (SCR_DATA_IN)), 1761 0, 1762 /* 1763 * Perform the move of the residual byte. 1764 */ 1765 SCR_CHMOV_TBL ^ SCR_DATA_IN, 1766 offsetof (struct sym_ccb, phys.wresid), 1767 /* 1768 * We can now handle the phase mismatch with UA fixed. 1769 * RBC[0..23]=0 is a special case that does not require 1770 * a PM context. The C code also checks against this. 1771 */ 1772 SCR_FROM_REG (rbc), 1773 0, 1774 SCR_RETURN ^ IFFALSE (DATA (0)), 1775 0, 1776 SCR_FROM_REG (rbc1), 1777 0, 1778 SCR_RETURN ^ IFFALSE (DATA (0)), 1779 0, 1780 SCR_FROM_REG (rbc2), 1781 0, 1782 SCR_RETURN ^ IFFALSE (DATA (0)), 1783 0, 1784 /* 1785 * RBC[0..23]=0. 1786 * Not only we donnot need a PM context, but this would 1787 * lead to a bogus CHMOV(0). This condition means that 1788 * the residual was the last byte to move from this CHMOV. 1789 * So, we just have to move the current data script pointer 1790 * (i.e. TEMP) to the SCRIPTS address following the 1791 * interrupted CHMOV and jump to dispatcher. 1792 */ 1793 SCR_STORE_ABS (ia, 4), 1794 PADDR_B (scratch), 1795 SCR_LOAD_ABS (temp, 4), 1796 PADDR_B (scratch), 1797 SCR_JUMP, 1798 PADDR_A (dispatch), 1799}/*-------------------------< WSR_MA_HELPER >--------------------*/,{ 1800 /* 1801 * Helper for the C code when WSR bit is set. 1802 * Perform the move of the residual byte. 1803 */ 1804 SCR_CHMOV_TBL ^ SCR_DATA_IN, 1805 offsetof (struct sym_ccb, phys.wresid), 1806 SCR_JUMP, 1807 PADDR_A (dispatch), 1808}/*-------------------------< ZERO >-----------------------------*/,{ 1809 SCR_DATA_ZERO, 1810}/*-------------------------< SCRATCH >--------------------------*/,{ 1811 SCR_DATA_ZERO, 1812}/*-------------------------< PM0_DATA_ADDR >--------------------*/,{ 1813 SCR_DATA_ZERO, 1814}/*-------------------------< PM1_DATA_ADDR >--------------------*/,{ 1815 SCR_DATA_ZERO, 1816}/*-------------------------< SAVED_DSA >------------------------*/,{ 1817 SCR_DATA_ZERO, 1818}/*-------------------------< SAVED_DRS >------------------------*/,{ 1819 SCR_DATA_ZERO, 1820}/*-------------------------< DONE_POS >-------------------------*/,{ 1821 SCR_DATA_ZERO, 1822}/*-------------------------< STARTPOS >-------------------------*/,{ 1823 SCR_DATA_ZERO, 1824}/*-------------------------< TARGTBL >--------------------------*/,{ 1825 SCR_DATA_ZERO, 1826 1827}/*-------------------------< SNOOPTEST >------------------------*/,{ 1828 /* 1829 * Read the variable from memory. 1830 */ 1831 SCR_LOAD_REL (scratcha, 4), 1832 offsetof(struct sym_hcb, cache), 1833 /* 1834 * Write the variable to memory. 1835 */ 1836 SCR_STORE_REL (temp, 4), 1837 offsetof(struct sym_hcb, cache), 1838 /* 1839 * Read back the variable from memory. 1840 */ 1841 SCR_LOAD_REL (temp, 4), 1842 offsetof(struct sym_hcb, cache), 1843}/*-------------------------< SNOOPEND >-------------------------*/,{ 1844 /* 1845 * And stop. 1846 */ 1847 SCR_INT, 1848 99, 1849}/*-------------------------<>-----------------------------------*/ 1850}; 1851