ich.c revision 139749
1190214Srpaulo/*- 2190214Srpaulo * Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp> 3190214Srpaulo * Copyright (c) 2001 Cameron Grant <cg@freebsd.org> 4190214Srpaulo * All rights reserved. 5190214Srpaulo * 6190214Srpaulo * Redistribution and use in source and binary forms, with or without 7190214Srpaulo * modification, are permitted provided that the following conditions 8190214Srpaulo * are met: 9190214Srpaulo * 1. Redistributions of source code must retain the above copyright 10190214Srpaulo * notice, this list of conditions and the following disclaimer. 11190214Srpaulo * 2. Redistributions in binary form must reproduce the above copyright 12190214Srpaulo * notice, this list of conditions and the following disclaimer in the 13190214Srpaulo * documentation and/or other materials provided with the distribution. 14190214Srpaulo * 15190214Srpaulo * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16190214Srpaulo * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17190214Srpaulo * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18190214Srpaulo * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19190214Srpaulo * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20190214Srpaulo * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21190214Srpaulo * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22190214Srpaulo * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 23190214Srpaulo * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24190214Srpaulo * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 25190214Srpaulo * SUCH DAMAGE. 26190214Srpaulo */ 27190214Srpaulo 28190214Srpaulo#include <dev/sound/pcm/sound.h> 29190214Srpaulo#include <dev/sound/pcm/ac97.h> 30190214Srpaulo#include <dev/sound/pci/ich.h> 31190214Srpaulo 32190214Srpaulo#include <dev/pci/pcireg.h> 33190214Srpaulo#include <dev/pci/pcivar.h> 34190214Srpaulo 35190214SrpauloSND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/ich.c 139749 2005-01-06 01:43:34Z imp $"); 36190214Srpaulo 37214518Srpaulo/* -------------------------------------------------------------------- */ 38190214Srpaulo 39190214Srpaulo#define ICH_TIMEOUT 1000 /* semaphore timeout polling count */ 40190214Srpaulo#define ICH_DTBL_LENGTH 32 41190214Srpaulo#define ICH_DEFAULT_BUFSZ 16384 42190214Srpaulo#define ICH_MAX_BUFSZ 65536 43190214Srpaulo 44190214Srpaulo#define SIS7012ID 0x70121039 /* SiS 7012 needs special handling */ 45190214Srpaulo#define ICH4ID 0x24c58086 /* ICH4 needs special handling too */ 46190214Srpaulo#define ICH5ID 0x24d58086 /* ICH5 needs to be treated as ICH4 */ 47190214Srpaulo#define ICH6ID 0x266e8086 /* ICH6 needs to be treated as ICH4 */ 48190214Srpaulo 49190214Srpaulo/* buffer descriptor */ 50190214Srpaulostruct ich_desc { 51190214Srpaulo volatile u_int32_t buffer; 52190214Srpaulo volatile u_int32_t length; 53190214Srpaulo}; 54190214Srpaulo 55190214Srpaulostruct sc_info; 56190214Srpaulo 57190214Srpaulo/* channel registers */ 58190214Srpaulostruct sc_chinfo { 59190214Srpaulo u_int32_t num:8, run:1, run_save:1; 60190214Srpaulo u_int32_t blksz, blkcnt, spd; 61190214Srpaulo u_int32_t regbase, spdreg; 62190214Srpaulo u_int32_t imask; 63214518Srpaulo u_int32_t civ; 64235426Sdelphij 65235426Sdelphij struct snd_dbuf *buffer; 66235426Sdelphij struct pcm_channel *channel; 67235426Sdelphij struct sc_info *parent; 68235426Sdelphij 69235426Sdelphij struct ich_desc *dtbl; 70235426Sdelphij bus_addr_t desc_addr; 71214518Srpaulo}; 72235426Sdelphij 73190214Srpaulo/* device private data */ 74214518Srpaulostruct sc_info { 75214518Srpaulo device_t dev; 76214518Srpaulo int hasvra, hasvrm, hasmic; 77214518Srpaulo unsigned int chnum, bufsz; 78214518Srpaulo int sample_size, swap_reg; 79190214Srpaulo 80190214Srpaulo struct resource *nambar, *nabmbar, *irq; 81190214Srpaulo int regtype, nambarid, nabmbarid, irqid; 82190214Srpaulo bus_space_tag_t nambart, nabmbart; 83190214Srpaulo bus_space_handle_t nambarh, nabmbarh; 84190214Srpaulo bus_dma_tag_t dmat; 85190214Srpaulo bus_dmamap_t dtmap; 86190214Srpaulo void *ih; 87190214Srpaulo 88190214Srpaulo struct ac97_info *codec; 89190214Srpaulo struct sc_chinfo ch[3]; 90190214Srpaulo int ac97rate; 91190214Srpaulo struct ich_desc *dtbl; 92190214Srpaulo bus_addr_t desc_addr; 93190214Srpaulo struct intr_config_hook intrhook; 94190214Srpaulo int use_intrhook; 95190214Srpaulo}; 96190214Srpaulo 97190214Srpaulo/* -------------------------------------------------------------------- */ 98190214Srpaulo 99190214Srpaulostatic u_int32_t ich_fmt[] = { 100190214Srpaulo AFMT_STEREO | AFMT_S16_LE, 101190214Srpaulo 0 102190214Srpaulo}; 103190214Srpaulostatic struct pcmchan_caps ich_vrcaps = {8000, 48000, ich_fmt, 0}; 104190214Srpaulostatic struct pcmchan_caps ich_caps = {48000, 48000, ich_fmt, 0}; 105190214Srpaulo 106190214Srpaulo/* -------------------------------------------------------------------- */ 107190214Srpaulo/* Hardware */ 108190214Srpaulostatic u_int32_t 109190214Srpauloich_rd(struct sc_info *sc, int regno, int size) 110190214Srpaulo{ 111190214Srpaulo switch (size) { 112190214Srpaulo case 1: 113190214Srpaulo return bus_space_read_1(sc->nabmbart, sc->nabmbarh, regno); 114190214Srpaulo case 2: 115190214Srpaulo return bus_space_read_2(sc->nabmbart, sc->nabmbarh, regno); 116190214Srpaulo case 4: 117190214Srpaulo return bus_space_read_4(sc->nabmbart, sc->nabmbarh, regno); 118190214Srpaulo default: 119190214Srpaulo return 0xffffffff; 120190214Srpaulo } 121190214Srpaulo} 122190214Srpaulo 123190214Srpaulostatic void 124190214Srpauloich_wr(struct sc_info *sc, int regno, u_int32_t data, int size) 125190214Srpaulo{ 126190214Srpaulo switch (size) { 127190214Srpaulo case 1: 128190214Srpaulo bus_space_write_1(sc->nabmbart, sc->nabmbarh, regno, data); 129190214Srpaulo break; 130190214Srpaulo case 2: 131190214Srpaulo bus_space_write_2(sc->nabmbart, sc->nabmbarh, regno, data); 132190214Srpaulo break; 133190214Srpaulo case 4: 134190214Srpaulo bus_space_write_4(sc->nabmbart, sc->nabmbarh, regno, data); 135190214Srpaulo break; 136190214Srpaulo } 137190214Srpaulo} 138190214Srpaulo 139190214Srpaulo/* ac97 codec */ 140190214Srpaulostatic int 141190214Srpauloich_waitcd(void *devinfo) 142190214Srpaulo{ 143190214Srpaulo int i; 144190214Srpaulo u_int32_t data; 145190214Srpaulo struct sc_info *sc = (struct sc_info *)devinfo; 146190214Srpaulo 147190214Srpaulo for (i = 0; i < ICH_TIMEOUT; i++) { 148190214Srpaulo data = ich_rd(sc, ICH_REG_ACC_SEMA, 1); 149190214Srpaulo if ((data & 0x01) == 0) 150190214Srpaulo return 0; 151251129Sdelphij } 152190214Srpaulo device_printf(sc->dev, "CODEC semaphore timeout\n"); 153190214Srpaulo return ETIMEDOUT; 154190214Srpaulo} 155190214Srpaulo 156214518Srpaulostatic int 157214518Srpauloich_rdcd(kobj_t obj, void *devinfo, int regno) 158214518Srpaulo{ 159190214Srpaulo struct sc_info *sc = (struct sc_info *)devinfo; 160214518Srpaulo 161214518Srpaulo regno &= 0xff; 162214518Srpaulo ich_waitcd(sc); 163214518Srpaulo 164214518Srpaulo return bus_space_read_2(sc->nambart, sc->nambarh, regno); 165190214Srpaulo} 166214518Srpaulo 167214518Srpaulostatic int 168190214Srpauloich_wrcd(kobj_t obj, void *devinfo, int regno, u_int16_t data) 169214518Srpaulo{ 170214518Srpaulo struct sc_info *sc = (struct sc_info *)devinfo; 171214518Srpaulo 172214518Srpaulo regno &= 0xff; 173214518Srpaulo ich_waitcd(sc); 174214518Srpaulo bus_space_write_2(sc->nambart, sc->nambarh, regno, data); 175214518Srpaulo 176214518Srpaulo return 0; 177190214Srpaulo} 178190214Srpaulo 179214518Srpaulostatic kobj_method_t ich_ac97_methods[] = { 180214518Srpaulo KOBJMETHOD(ac97_read, ich_rdcd), 181214518Srpaulo KOBJMETHOD(ac97_write, ich_wrcd), 182214518Srpaulo { 0, 0 } 183214518Srpaulo}; 184214518SrpauloAC97_DECLARE(ich_ac97); 185214518Srpaulo 186214518Srpaulo/* -------------------------------------------------------------------- */ 187214518Srpaulo/* common routines */ 188214518Srpaulo 189214518Srpaulostatic void 190214518Srpauloich_filldtbl(struct sc_chinfo *ch) 191214518Srpaulo{ 192214518Srpaulo u_int32_t base; 193214518Srpaulo int i; 194214518Srpaulo 195214518Srpaulo base = sndbuf_getbufaddr(ch->buffer); 196214518Srpaulo ch->blkcnt = sndbuf_getsize(ch->buffer) / ch->blksz; 197214518Srpaulo if (ch->blkcnt != 2 && ch->blkcnt != 4 && ch->blkcnt != 8 && ch->blkcnt != 16 && ch->blkcnt != 32) { 198214518Srpaulo ch->blkcnt = 2; 199214518Srpaulo ch->blksz = sndbuf_getsize(ch->buffer) / ch->blkcnt; 200214518Srpaulo } 201214518Srpaulo 202190214Srpaulo for (i = 0; i < ICH_DTBL_LENGTH; i++) { 203190214Srpaulo ch->dtbl[i].buffer = base + (ch->blksz * (i % ch->blkcnt)); 204190214Srpaulo ch->dtbl[i].length = ICH_BDC_IOC 205190214Srpaulo | (ch->blksz / ch->parent->sample_size); 206190214Srpaulo } 207190214Srpaulo} 208190214Srpaulo 209190214Srpaulostatic int 210190214Srpauloich_resetchan(struct sc_info *sc, int num) 211214518Srpaulo{ 212214518Srpaulo int i, cr, regbase; 213214518Srpaulo 214214518Srpaulo if (num == 0) 215190214Srpaulo regbase = ICH_REG_PO_BASE; 216190214Srpaulo else if (num == 1) 217214518Srpaulo regbase = ICH_REG_PI_BASE; 218214518Srpaulo else if (num == 2) 219214518Srpaulo regbase = ICH_REG_MC_BASE; 220214518Srpaulo else 221214518Srpaulo return ENXIO; 222214518Srpaulo 223214518Srpaulo ich_wr(sc, regbase + ICH_REG_X_CR, 0, 1); 224214518Srpaulo DELAY(100); 225214518Srpaulo ich_wr(sc, regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 226214518Srpaulo for (i = 0; i < ICH_TIMEOUT; i++) { 227214518Srpaulo cr = ich_rd(sc, regbase + ICH_REG_X_CR, 1); 228214518Srpaulo if (cr == 0) 229214518Srpaulo return 0; 230214518Srpaulo } 231214518Srpaulo 232214518Srpaulo device_printf(sc->dev, "cannot reset channel %d\n", num); 233214518Srpaulo return ENXIO; 234214518Srpaulo} 235214518Srpaulo 236214518Srpaulo/* -------------------------------------------------------------------- */ 237214518Srpaulo/* channel interface */ 238214518Srpaulo 239214518Srpaulostatic void * 240214518Srpauloichchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 241214518Srpaulo{ 242214518Srpaulo struct sc_info *sc = devinfo; 243214518Srpaulo struct sc_chinfo *ch; 244214518Srpaulo unsigned int num; 245214518Srpaulo 246214518Srpaulo num = sc->chnum++; 247214518Srpaulo ch = &sc->ch[num]; 248214518Srpaulo ch->num = num; 249214518Srpaulo ch->buffer = b; 250214518Srpaulo ch->channel = c; 251214518Srpaulo ch->parent = sc; 252214518Srpaulo ch->run = 0; 253214518Srpaulo ch->dtbl = sc->dtbl + (ch->num * ICH_DTBL_LENGTH); 254214518Srpaulo ch->desc_addr = sc->desc_addr + (ch->num * ICH_DTBL_LENGTH) * 255214518Srpaulo sizeof(struct ich_desc); 256214518Srpaulo ch->blkcnt = 2; 257214518Srpaulo ch->blksz = sc->bufsz / ch->blkcnt; 258214518Srpaulo 259214518Srpaulo switch(ch->num) { 260214518Srpaulo case 0: /* play */ 261214518Srpaulo KASSERT(dir == PCMDIR_PLAY, ("wrong direction")); 262214518Srpaulo ch->regbase = ICH_REG_PO_BASE; 263214518Srpaulo ch->spdreg = sc->hasvra? AC97_REGEXT_FDACRATE : 0; 264214518Srpaulo ch->imask = ICH_GLOB_STA_POINT; 265214518Srpaulo break; 266214518Srpaulo 267214518Srpaulo case 1: /* record */ 268214518Srpaulo KASSERT(dir == PCMDIR_REC, ("wrong direction")); 269214518Srpaulo ch->regbase = ICH_REG_PI_BASE; 270214518Srpaulo ch->spdreg = sc->hasvra? AC97_REGEXT_LADCRATE : 0; 271214518Srpaulo ch->imask = ICH_GLOB_STA_PIINT; 272214518Srpaulo break; 273214518Srpaulo 274214518Srpaulo case 2: /* mic */ 275214518Srpaulo KASSERT(dir == PCMDIR_REC, ("wrong direction")); 276214518Srpaulo ch->regbase = ICH_REG_MC_BASE; 277214518Srpaulo ch->spdreg = sc->hasvrm? AC97_REGEXT_MADCRATE : 0; 278214518Srpaulo ch->imask = ICH_GLOB_STA_MINT; 279214518Srpaulo break; 280214518Srpaulo 281214518Srpaulo default: 282214518Srpaulo return NULL; 283214518Srpaulo } 284214518Srpaulo 285214518Srpaulo if (sndbuf_alloc(ch->buffer, sc->dmat, sc->bufsz) != 0) 286190214Srpaulo return NULL; 287251129Sdelphij 288190214Srpaulo ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)(ch->desc_addr), 4); 289251129Sdelphij 290251129Sdelphij return ch; 291251129Sdelphij} 292190214Srpaulo 293190214Srpaulostatic int 294251129Sdelphijichchan_setformat(kobj_t obj, void *data, u_int32_t format) 295251129Sdelphij{ 296251129Sdelphij return 0; 297251129Sdelphij} 298251129Sdelphij 299251129Sdelphijstatic int 300251129Sdelphijichchan_setspeed(kobj_t obj, void *data, u_int32_t speed) 301251129Sdelphij{ 302251129Sdelphij struct sc_chinfo *ch = data; 303251129Sdelphij struct sc_info *sc = ch->parent; 304251129Sdelphij 305251129Sdelphij if (ch->spdreg) { 306251129Sdelphij int r; 307251129Sdelphij if (sc->ac97rate <= 32000 || sc->ac97rate >= 64000) 308251129Sdelphij sc->ac97rate = 48000; 309251129Sdelphij r = (speed * 48000) / sc->ac97rate; 310251129Sdelphij /* 311251129Sdelphij * Cast the return value of ac97_setrate() to u_int so that 312251129Sdelphij * the math don't overflow into the negative range. 313251129Sdelphij */ 314251129Sdelphij ch->spd = ((u_int)ac97_setrate(sc->codec, ch->spdreg, r) * 315251129Sdelphij sc->ac97rate) / 48000; 316251129Sdelphij } else { 317251129Sdelphij ch->spd = 48000; 318251129Sdelphij } 319251129Sdelphij return ch->spd; 320251129Sdelphij} 321190214Srpaulo 322190214Srpaulostatic int 323190214Srpauloichchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 324190214Srpaulo{ 325190214Srpaulo struct sc_chinfo *ch = data; 326190214Srpaulo struct sc_info *sc = ch->parent; 327190214Srpaulo 328190214Srpaulo ch->blksz = blocksize; 329190214Srpaulo ich_filldtbl(ch); 330190214Srpaulo ich_wr(sc, ch->regbase + ICH_REG_X_LVI, ch->blkcnt - 1, 1); 331190214Srpaulo 332190214Srpaulo return ch->blksz; 333190214Srpaulo} 334190214Srpaulo 335190214Srpaulostatic int 336190214Srpauloichchan_trigger(kobj_t obj, void *data, int go) 337190214Srpaulo{ 338190214Srpaulo struct sc_chinfo *ch = data; 339190214Srpaulo struct sc_info *sc = ch->parent; 340235426Sdelphij 341190214Srpaulo switch (go) { 342190214Srpaulo case PCMTRIG_START: 343190214Srpaulo ch->run = 1; 344190214Srpaulo ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)(ch->desc_addr), 4); 345190214Srpaulo ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM | ICH_X_CR_LVBIE | ICH_X_CR_IOCE, 1); 346190214Srpaulo break; 347190214Srpaulo 348190214Srpaulo case PCMTRIG_ABORT: 349190214Srpaulo ich_resetchan(sc, ch->num); 350190214Srpaulo ch->run = 0; 351190214Srpaulo break; 352190214Srpaulo } 353190214Srpaulo return 0; 354190214Srpaulo} 355190214Srpaulo 356190214Srpaulostatic int 357190214Srpauloichchan_getptr(kobj_t obj, void *data) 358190214Srpaulo{ 359190214Srpaulo struct sc_chinfo *ch = data; 360190214Srpaulo struct sc_info *sc = ch->parent; 361190214Srpaulo u_int32_t pos; 362190214Srpaulo 363214518Srpaulo ch->civ = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1) % ch->blkcnt; 364190214Srpaulo 365190214Srpaulo pos = ch->civ * ch->blksz; 366190214Srpaulo 367190214Srpaulo return pos; 368190214Srpaulo} 369214518Srpaulo 370190214Srpaulostatic struct pcmchan_caps * 371190214Srpauloichchan_getcaps(kobj_t obj, void *data) 372190214Srpaulo{ 373214518Srpaulo struct sc_chinfo *ch = data; 374190214Srpaulo 375190214Srpaulo return ch->spdreg? &ich_vrcaps : &ich_caps; 376190214Srpaulo} 377190214Srpaulo 378190214Srpaulostatic kobj_method_t ichchan_methods[] = { 379190214Srpaulo KOBJMETHOD(channel_init, ichchan_init), 380190214Srpaulo KOBJMETHOD(channel_setformat, ichchan_setformat), 381190214Srpaulo KOBJMETHOD(channel_setspeed, ichchan_setspeed), 382190214Srpaulo KOBJMETHOD(channel_setblocksize, ichchan_setblocksize), 383190214Srpaulo KOBJMETHOD(channel_trigger, ichchan_trigger), 384190214Srpaulo KOBJMETHOD(channel_getptr, ichchan_getptr), 385190214Srpaulo KOBJMETHOD(channel_getcaps, ichchan_getcaps), 386214518Srpaulo { 0, 0 } 387190214Srpaulo}; 388190214SrpauloCHANNEL_DECLARE(ichchan); 389190214Srpaulo 390190214Srpaulo/* -------------------------------------------------------------------- */ 391190214Srpaulo/* The interrupt handler */ 392190214Srpaulo 393190214Srpaulostatic void 394214518Srpauloich_intr(void *p) 395214518Srpaulo{ 396214518Srpaulo struct sc_info *sc = (struct sc_info *)p; 397214518Srpaulo struct sc_chinfo *ch; 398214518Srpaulo u_int32_t cbi, lbi, lvi, st, gs; 399214518Srpaulo int i; 400214518Srpaulo 401214518Srpaulo gs = ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_IMASK; 402214518Srpaulo if (gs & (ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES)) { 403214518Srpaulo /* Clear resume interrupt(s) - nothing doing with them */ 404214518Srpaulo ich_wr(sc, ICH_REG_GLOB_STA, gs, 4); 405214518Srpaulo } 406214518Srpaulo gs &= ~(ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES); 407214518Srpaulo 408214518Srpaulo for (i = 0; i < 3; i++) { 409190214Srpaulo ch = &sc->ch[i]; 410214518Srpaulo if ((ch->imask & gs) == 0) 411214518Srpaulo continue; 412214518Srpaulo gs &= ~ch->imask; 413214518Srpaulo st = ich_rd(sc, ch->regbase + 414214518Srpaulo (sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR), 415214518Srpaulo 2); 416214518Srpaulo st &= ICH_X_SR_FIFOE | ICH_X_SR_BCIS | ICH_X_SR_LVBCI; 417214518Srpaulo if (st & (ICH_X_SR_BCIS | ICH_X_SR_LVBCI)) { 418214518Srpaulo /* block complete - update buffer */ 419190214Srpaulo if (ch->run) 420190214Srpaulo chn_intr(ch->channel); 421190214Srpaulo lvi = ich_rd(sc, ch->regbase + ICH_REG_X_LVI, 1); 422190214Srpaulo cbi = ch->civ % ch->blkcnt; 423190214Srpaulo if (cbi == 0) 424190214Srpaulo cbi = ch->blkcnt - 1; 425190214Srpaulo else 426190214Srpaulo cbi--; 427190214Srpaulo lbi = lvi % ch->blkcnt; 428190214Srpaulo if (cbi >= lbi) 429190214Srpaulo lvi += cbi - lbi; 430190214Srpaulo else 431190214Srpaulo lvi += cbi + ch->blkcnt - lbi; 432190214Srpaulo lvi %= ICH_DTBL_LENGTH; 433190214Srpaulo ich_wr(sc, ch->regbase + ICH_REG_X_LVI, lvi, 1); 434190214Srpaulo 435214518Srpaulo } 436190214Srpaulo /* clear status bit */ 437190214Srpaulo ich_wr(sc, ch->regbase + 438190214Srpaulo (sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR), 439190214Srpaulo st, 2); 440190214Srpaulo } 441190214Srpaulo if (gs != 0) { 442190214Srpaulo device_printf(sc->dev, 443190214Srpaulo "Unhandled interrupt, gs_intr = %x\n", gs); 444190214Srpaulo } 445190214Srpaulo} 446190214Srpaulo 447190214Srpaulo/* ------------------------------------------------------------------------- */ 448190214Srpaulo/* Sysctl to control ac97 speed (some boards appear to end up using 449190214Srpaulo * XTAL_IN rather than BIT_CLK for link timing). 450190214Srpaulo */ 451190214Srpaulo 452190214Srpaulostatic int 453190214Srpauloich_initsys(struct sc_info* sc) 454190214Srpaulo{ 455190214Srpaulo#ifdef SND_DYNSYSCTL 456190214Srpaulo SYSCTL_ADD_INT(snd_sysctl_tree(sc->dev), 457190214Srpaulo SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), 458190214Srpaulo OID_AUTO, "ac97rate", CTLFLAG_RW, 459190214Srpaulo &sc->ac97rate, 48000, 460190214Srpaulo "AC97 link rate (default = 48000)"); 461190214Srpaulo#endif /* SND_DYNSYSCTL */ 462190214Srpaulo return 0; 463190214Srpaulo} 464190214Srpaulo 465190214Srpaulo/* -------------------------------------------------------------------- */ 466190214Srpaulo/* Calibrate card to determine the clock source. The source maybe a 467190214Srpaulo * function of the ac97 codec initialization code (to be investigated). 468190214Srpaulo */ 469190214Srpaulo 470190214Srpaulostatic 471190214Srpaulovoid ich_calibrate(void *arg) 472190214Srpaulo{ 473190214Srpaulo struct sc_info *sc; 474190214Srpaulo struct sc_chinfo *ch; 475190214Srpaulo struct timeval t1, t2; 476190214Srpaulo u_int8_t ociv, nciv; 477190214Srpaulo u_int32_t wait_us, actual_48k_rate, bytes; 478190214Srpaulo 479190214Srpaulo sc = (struct sc_info *)arg; 480190214Srpaulo ch = &sc->ch[1]; 481190214Srpaulo 482190214Srpaulo if (sc->use_intrhook) 483190214Srpaulo config_intrhook_disestablish(&sc->intrhook); 484190214Srpaulo 485190214Srpaulo /* 486190214Srpaulo * Grab audio from input for fixed interval and compare how 487190214Srpaulo * much we actually get with what we expect. Interval needs 488190214Srpaulo * to be sufficiently short that no interrupts are 489190214Srpaulo * generated. 490190214Srpaulo */ 491190214Srpaulo 492190214Srpaulo KASSERT(ch->regbase == ICH_REG_PI_BASE, ("wrong direction")); 493190214Srpaulo 494190214Srpaulo bytes = sndbuf_getsize(ch->buffer) / 2; 495190214Srpaulo ichchan_setblocksize(0, ch, bytes); 496190214Srpaulo 497190214Srpaulo /* 498190214Srpaulo * our data format is stereo, 16 bit so each sample is 4 bytes. 499190214Srpaulo * assuming we get 48000 samples per second, we get 192000 bytes/sec. 500190214Srpaulo * we're going to start recording with interrupts disabled and measure 501190214Srpaulo * the time taken for one block to complete. we know the block size, 502190214Srpaulo * we know the time in microseconds, we calculate the sample rate: 503190214Srpaulo * 504190214Srpaulo * actual_rate [bps] = bytes / (time [s] * 4) 505190214Srpaulo * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 506190214Srpaulo * actual_rate [Hz] = (bytes * 250000) / time [us] 507190214Srpaulo */ 508190214Srpaulo 509190214Srpaulo /* prepare */ 510190214Srpaulo ociv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 511190214Srpaulo nciv = ociv; 512190214Srpaulo ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)(ch->desc_addr), 4); 513190214Srpaulo 514190214Srpaulo /* start */ 515190214Srpaulo microtime(&t1); 516190214Srpaulo ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM, 1); 517190214Srpaulo 518190214Srpaulo /* wait */ 519190214Srpaulo while (nciv == ociv) { 520190214Srpaulo microtime(&t2); 521190214Srpaulo if (t2.tv_sec - t1.tv_sec > 1) 522190214Srpaulo break; 523190214Srpaulo nciv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 524190214Srpaulo } 525190214Srpaulo microtime(&t2); 526190214Srpaulo 527190214Srpaulo /* stop */ 528214518Srpaulo ich_wr(sc, ch->regbase + ICH_REG_X_CR, 0, 1); 529190214Srpaulo 530190214Srpaulo /* reset */ 531190214Srpaulo DELAY(100); 532190214Srpaulo ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 533190214Srpaulo 534190214Srpaulo /* turn time delta into us */ 535190214Srpaulo wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 536190214Srpaulo 537190214Srpaulo if (nciv == ociv) { 538190214Srpaulo device_printf(sc->dev, "ac97 link rate calibration timed out after %d us\n", wait_us); 539190214Srpaulo return; 540190214Srpaulo } 541190214Srpaulo 542190214Srpaulo actual_48k_rate = (bytes * 250000) / wait_us; 543190214Srpaulo 544190214Srpaulo if (actual_48k_rate < 47500 || actual_48k_rate > 48500) { 545214518Srpaulo sc->ac97rate = actual_48k_rate; 546190214Srpaulo } else { 547190214Srpaulo sc->ac97rate = 48000; 548190214Srpaulo } 549190214Srpaulo 550190214Srpaulo if (bootverbose || sc->ac97rate != 48000) { 551190214Srpaulo device_printf(sc->dev, "measured ac97 link rate at %d Hz", actual_48k_rate); 552190214Srpaulo if (sc->ac97rate != actual_48k_rate) 553190214Srpaulo printf(", will use %d Hz", sc->ac97rate); 554190214Srpaulo printf("\n"); 555190214Srpaulo } 556190214Srpaulo 557190214Srpaulo return; 558190214Srpaulo} 559190214Srpaulo 560190214Srpaulo/* -------------------------------------------------------------------- */ 561190214Srpaulo/* Probe and attach the card */ 562190214Srpaulo 563190214Srpaulostatic void 564190214Srpauloich_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error) 565190214Srpaulo{ 566190214Srpaulo struct sc_info *sc = (struct sc_info *)arg; 567190214Srpaulo sc->desc_addr = segs->ds_addr; 568190214Srpaulo return; 569190214Srpaulo} 570190214Srpaulo 571190214Srpaulostatic int 572190214Srpauloich_init(struct sc_info *sc) 573190214Srpaulo{ 574190214Srpaulo u_int32_t stat; 575190214Srpaulo int sz; 576190214Srpaulo 577190214Srpaulo ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4); 578190214Srpaulo DELAY(600000); 579190214Srpaulo stat = ich_rd(sc, ICH_REG_GLOB_STA, 4); 580190214Srpaulo 581190214Srpaulo if ((stat & ICH_GLOB_STA_PCR) == 0) { 582190214Srpaulo /* ICH4/ICH5 may fail when busmastering is enabled. Continue */ 583190214Srpaulo if ((pci_get_devid(sc->dev) != ICH4ID) && 584190214Srpaulo (pci_get_devid(sc->dev) != ICH5ID) && 585190214Srpaulo (pci_get_devid(sc->dev) != ICH6ID)) { 586190214Srpaulo return ENXIO; 587190214Srpaulo } 588190214Srpaulo } 589190214Srpaulo 590190214Srpaulo ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD | ICH_GLOB_CTL_PRES, 4); 591190214Srpaulo 592190214Srpaulo if (ich_resetchan(sc, 0) || ich_resetchan(sc, 1)) 593190214Srpaulo return ENXIO; 594190214Srpaulo if (sc->hasmic && ich_resetchan(sc, 2)) 595190214Srpaulo return ENXIO; 596190214Srpaulo 597190214Srpaulo if (bus_dmamem_alloc(sc->dmat, (void **)&sc->dtbl, BUS_DMA_NOWAIT, &sc->dtmap)) 598214518Srpaulo return ENOSPC; 599190214Srpaulo 600190214Srpaulo sz = sizeof(struct ich_desc) * ICH_DTBL_LENGTH * 3; 601190214Srpaulo if (bus_dmamap_load(sc->dmat, sc->dtmap, sc->dtbl, sz, ich_setmap, sc, 0)) { 602190214Srpaulo bus_dmamem_free(sc->dmat, (void **)&sc->dtbl, sc->dtmap); 603190214Srpaulo return ENOSPC; 604190214Srpaulo } 605190214Srpaulo 606190214Srpaulo return 0; 607190214Srpaulo} 608190214Srpaulo 609190214Srpaulostatic int 610190214Srpauloich_pci_probe(device_t dev) 611190214Srpaulo{ 612190214Srpaulo switch(pci_get_devid(dev)) { 613190214Srpaulo case 0x71958086: 614190214Srpaulo device_set_desc(dev, "Intel 443MX"); 615190214Srpaulo return 0; 616190214Srpaulo 617190214Srpaulo case 0x24158086: 618190214Srpaulo device_set_desc(dev, "Intel ICH (82801AA)"); 619190214Srpaulo return 0; 620190214Srpaulo 621190214Srpaulo case 0x24258086: 622190214Srpaulo device_set_desc(dev, "Intel ICH (82801AB)"); 623190214Srpaulo return 0; 624190214Srpaulo 625190214Srpaulo case 0x24458086: 626190214Srpaulo device_set_desc(dev, "Intel ICH2 (82801BA)"); 627190214Srpaulo return 0; 628190214Srpaulo 629190214Srpaulo case 0x24858086: 630190214Srpaulo device_set_desc(dev, "Intel ICH3 (82801CA)"); 631190214Srpaulo return 0; 632190214Srpaulo 633190214Srpaulo case ICH4ID: 634190214Srpaulo device_set_desc(dev, "Intel ICH4 (82801DB)"); 635190214Srpaulo return -1000; /* allow a better driver to override us */ 636190214Srpaulo 637190214Srpaulo case ICH5ID: 638190214Srpaulo device_set_desc(dev, "Intel ICH5 (82801EB)"); 639235426Sdelphij return -1000; /* allow a better driver to override us */ 640235426Sdelphij 641235426Sdelphij case ICH6ID: 642235426Sdelphij device_set_desc(dev, "Intel ICH6 (82801FB)"); 643235426Sdelphij return -1000; /* allow a better driver to override us */ 644235426Sdelphij 645235426Sdelphij case SIS7012ID: 646235426Sdelphij device_set_desc(dev, "SiS 7012"); 647190214Srpaulo return 0; 648190214Srpaulo 649190214Srpaulo case 0x01b110de: 650190214Srpaulo device_set_desc(dev, "nVidia nForce"); 651190214Srpaulo return 0; 652190214Srpaulo 653190214Srpaulo case 0x006a10de: 654190214Srpaulo device_set_desc(dev, "nVidia nForce2"); 655190214Srpaulo return 0; 656190214Srpaulo 657190214Srpaulo case 0x008a10de: 658190214Srpaulo device_set_desc(dev, "nVidia nForce2 400"); 659190214Srpaulo return 0; 660190214Srpaulo 661190214Srpaulo case 0x00da10de: 662190214Srpaulo device_set_desc(dev, "nVidia nForce3"); 663190214Srpaulo return 0; 664214518Srpaulo 665214518Srpaulo case 0x00ea10de: 666190214Srpaulo device_set_desc(dev, "nVidia nForce3 250"); 667214518Srpaulo return 0; 668190214Srpaulo 669190214Srpaulo case 0x74451022: 670214518Srpaulo device_set_desc(dev, "AMD-768"); 671214518Srpaulo return 0; 672214518Srpaulo 673214518Srpaulo case 0x746d1022: 674214518Srpaulo device_set_desc(dev, "AMD-8111"); 675214518Srpaulo return 0; 676214518Srpaulo 677214518Srpaulo default: 678214518Srpaulo return ENXIO; 679214518Srpaulo } 680214518Srpaulo} 681214518Srpaulo 682214518Srpaulostatic int 683214518Srpauloich_pci_attach(device_t dev) 684214518Srpaulo{ 685190214Srpaulo u_int16_t extcaps; 686190214Srpaulo struct sc_info *sc; 687190214Srpaulo char status[SND_STATUSLEN]; 688190214Srpaulo 689190214Srpaulo if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT)) == NULL) { 690190214Srpaulo device_printf(dev, "cannot allocate softc\n"); 691190214Srpaulo return ENXIO; 692190214Srpaulo } 693190214Srpaulo 694190214Srpaulo bzero(sc, sizeof(*sc)); 695190214Srpaulo sc->dev = dev; 696190214Srpaulo 697190214Srpaulo /* 698190214Srpaulo * The SiS 7012 register set isn't quite like the standard ich. 699190214Srpaulo * There really should be a general "quirks" mechanism. 700190214Srpaulo */ 701190214Srpaulo if (pci_get_devid(dev) == SIS7012ID) { 702190214Srpaulo sc->swap_reg = 1; 703190214Srpaulo sc->sample_size = 1; 704190214Srpaulo } else { 705190214Srpaulo sc->swap_reg = 0; 706190214Srpaulo sc->sample_size = 2; 707190214Srpaulo } 708190214Srpaulo 709214518Srpaulo /* 710214518Srpaulo * By default, ich4 has NAMBAR and NABMBAR i/o spaces as 711190214Srpaulo * read-only. Need to enable "legacy support", by poking into 712214518Srpaulo * pci config space. The driver should use MMBAR and MBBAR, 713190214Srpaulo * but doing so will mess things up here. ich4 has enough new 714190214Srpaulo * features it warrants it's own driver. 715190214Srpaulo */ 716190214Srpaulo if (pci_get_devid(dev) == ICH4ID) { 717190214Srpaulo pci_write_config(dev, PCIR_ICH_LEGACY, ICH_LEGACY_ENABLE, 1); 718190214Srpaulo } 719190214Srpaulo 720190214Srpaulo /* 721190214Srpaulo * Enable bus master. On ich4/5 this may prevent the detection of 722190214Srpaulo * the primary codec becoming ready in ich_init(). 723190214Srpaulo */ 724190214Srpaulo pci_enable_busmaster(dev); 725190214Srpaulo 726190214Srpaulo if (pci_get_devid(dev) == ICH5ID || pci_get_devid(dev) == ICH6ID) { 727190214Srpaulo sc->nambarid = PCIR_MMBAR; 728190214Srpaulo sc->nabmbarid = PCIR_MBBAR; 729190214Srpaulo sc->regtype = SYS_RES_MEMORY; 730190214Srpaulo } else { 731190214Srpaulo sc->nambarid = PCIR_NAMBAR; 732190214Srpaulo sc->nabmbarid = PCIR_NABMBAR; 733190214Srpaulo sc->regtype = SYS_RES_IOPORT; 734190214Srpaulo } 735190214Srpaulo 736190214Srpaulo sc->nambar = bus_alloc_resource_any(dev, sc->regtype, 737190214Srpaulo &sc->nambarid, RF_ACTIVE); 738190214Srpaulo sc->nabmbar = bus_alloc_resource_any(dev, sc->regtype, 739190214Srpaulo &sc->nabmbarid, RF_ACTIVE); 740190214Srpaulo 741190214Srpaulo if (!sc->nambar || !sc->nabmbar) { 742190214Srpaulo device_printf(dev, "unable to map IO port space\n"); 743190214Srpaulo goto bad; 744190214Srpaulo } 745190214Srpaulo 746190214Srpaulo sc->nambart = rman_get_bustag(sc->nambar); 747190214Srpaulo sc->nambarh = rman_get_bushandle(sc->nambar); 748190214Srpaulo sc->nabmbart = rman_get_bustag(sc->nabmbar); 749190214Srpaulo sc->nabmbarh = rman_get_bushandle(sc->nabmbar); 750190214Srpaulo 751190214Srpaulo sc->bufsz = pcm_getbuffersize(dev, 4096, ICH_DEFAULT_BUFSZ, ICH_MAX_BUFSZ); 752190214Srpaulo if (bus_dma_tag_create(NULL, 8, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 753190214Srpaulo NULL, NULL, sc->bufsz, 1, 0x3ffff, 0, 754214518Srpaulo busdma_lock_mutex, &Giant, &sc->dmat) != 0) { 755214518Srpaulo device_printf(dev, "unable to create dma tag\n"); 756190214Srpaulo goto bad; 757190214Srpaulo } 758190214Srpaulo 759190214Srpaulo sc->irqid = 0; 760190214Srpaulo sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid, 761190214Srpaulo RF_ACTIVE | RF_SHAREABLE); 762190214Srpaulo if (!sc->irq || snd_setup_intr(dev, sc->irq, 0, ich_intr, sc, &sc->ih)) { 763190214Srpaulo device_printf(dev, "unable to map interrupt\n"); 764190214Srpaulo goto bad; 765190214Srpaulo } 766190214Srpaulo 767190214Srpaulo if (ich_init(sc)) { 768190214Srpaulo device_printf(dev, "unable to initialize the card\n"); 769190214Srpaulo goto bad; 770190214Srpaulo } 771190214Srpaulo 772190214Srpaulo sc->codec = AC97_CREATE(dev, sc, ich_ac97); 773190214Srpaulo if (sc->codec == NULL) 774190214Srpaulo goto bad; 775190214Srpaulo mixer_init(dev, ac97_getmixerclass(), sc->codec); 776190214Srpaulo 777190214Srpaulo /* check and set VRA function */ 778190214Srpaulo extcaps = ac97_getextcaps(sc->codec); 779190214Srpaulo sc->hasvra = extcaps & AC97_EXTCAP_VRA; 780190214Srpaulo sc->hasvrm = extcaps & AC97_EXTCAP_VRM; 781190214Srpaulo sc->hasmic = ac97_getcaps(sc->codec) & AC97_CAP_MICCHANNEL; 782190214Srpaulo ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm); 783190214Srpaulo 784190214Srpaulo if (pcm_register(dev, sc, 1, sc->hasmic? 2 : 1)) 785190214Srpaulo goto bad; 786190214Srpaulo 787190214Srpaulo pcm_addchan(dev, PCMDIR_PLAY, &ichchan_class, sc); /* play */ 788190214Srpaulo pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record */ 789190214Srpaulo if (sc->hasmic) 790190214Srpaulo pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record mic */ 791190214Srpaulo 792190214Srpaulo snprintf(status, SND_STATUSLEN, "at io 0x%lx, 0x%lx irq %ld bufsz %u %s", 793190214Srpaulo rman_get_start(sc->nambar), rman_get_start(sc->nabmbar), rman_get_start(sc->irq), sc->bufsz,PCM_KLDSTRING(snd_ich)); 794190214Srpaulo 795190214Srpaulo pcm_setstatus(dev, status); 796190214Srpaulo 797190214Srpaulo ich_initsys(sc); 798190214Srpaulo 799190214Srpaulo sc->intrhook.ich_func = ich_calibrate; 800190214Srpaulo sc->intrhook.ich_arg = sc; 801214518Srpaulo sc->use_intrhook = 1; 802190214Srpaulo if (config_intrhook_establish(&sc->intrhook) != 0) { 803190214Srpaulo device_printf(dev, "Cannot establish calibration hook, will calibrate now\n"); 804190214Srpaulo sc->use_intrhook = 0; 805235426Sdelphij ich_calibrate(sc); 806235426Sdelphij } 807235426Sdelphij 808235426Sdelphij return 0; 809235426Sdelphij 810235426Sdelphijbad: 811235426Sdelphij if (sc->codec) 812235426Sdelphij ac97_destroy(sc->codec); 813235426Sdelphij if (sc->ih) 814190214Srpaulo bus_teardown_intr(dev, sc->irq, sc->ih); 815190214Srpaulo if (sc->irq) 816190214Srpaulo bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 817190214Srpaulo if (sc->nambar) 818190214Srpaulo bus_release_resource(dev, sc->regtype, 819190214Srpaulo sc->nambarid, sc->nambar); 820190214Srpaulo if (sc->nabmbar) 821190214Srpaulo bus_release_resource(dev, sc->regtype, 822190214Srpaulo sc->nabmbarid, sc->nabmbar); 823190214Srpaulo free(sc, M_DEVBUF); 824190214Srpaulo return ENXIO; 825190214Srpaulo} 826190214Srpaulo 827190214Srpaulostatic int 828190214Srpauloich_pci_detach(device_t dev) 829190214Srpaulo{ 830214518Srpaulo struct sc_info *sc; 831190214Srpaulo int r; 832214518Srpaulo 833214518Srpaulo r = pcm_unregister(dev); 834190214Srpaulo if (r) 835190214Srpaulo return r; 836190214Srpaulo sc = pcm_getdevinfo(dev); 837190214Srpaulo 838190214Srpaulo bus_teardown_intr(dev, sc->irq, sc->ih); 839190214Srpaulo bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 840190214Srpaulo bus_release_resource(dev, sc->regtype, sc->nambarid, sc->nambar); 841190214Srpaulo bus_release_resource(dev, sc->regtype, sc->nabmbarid, sc->nabmbar); 842190214Srpaulo bus_dma_tag_destroy(sc->dmat); 843190214Srpaulo free(sc, M_DEVBUF); 844190214Srpaulo return 0; 845190214Srpaulo} 846190214Srpaulo 847190214Srpaulostatic void 848190214Srpauloich_pci_codec_reset(struct sc_info *sc) 849190214Srpaulo{ 850190214Srpaulo int i; 851190214Srpaulo uint32_t control; 852190214Srpaulo 853190214Srpaulo control = ich_rd(sc, ICH_REG_GLOB_CNT, 4); 854190214Srpaulo control &= ~(ICH_GLOB_CTL_SHUT); 855190214Srpaulo control |= (control & ICH_GLOB_CTL_COLD) ? 856190214Srpaulo ICH_GLOB_CTL_WARM : ICH_GLOB_CTL_COLD; 857190214Srpaulo ich_wr(sc, ICH_REG_GLOB_CNT, control, 4); 858190214Srpaulo 859190214Srpaulo for (i = 500000; i; i--) { 860190214Srpaulo if (ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_PCR) 861190214Srpaulo break; /* or ICH_SCR? */ 862190214Srpaulo DELAY(1); 863190214Srpaulo } 864190214Srpaulo 865190214Srpaulo if (i <= 0) 866190214Srpaulo printf("%s: time out\n", __func__); 867190214Srpaulo} 868190214Srpaulo 869214518Srpaulostatic int 870190214Srpauloich_pci_suspend(device_t dev) 871190214Srpaulo{ 872190214Srpaulo struct sc_info *sc; 873214518Srpaulo int i; 874214518Srpaulo 875214518Srpaulo sc = pcm_getdevinfo(dev); 876214518Srpaulo for (i = 0 ; i < 3; i++) { 877214518Srpaulo sc->ch[i].run_save = sc->ch[i].run; 878214518Srpaulo if (sc->ch[i].run) { 879190214Srpaulo ichchan_trigger(0, &sc->ch[i], PCMTRIG_ABORT); 880214518Srpaulo } 881214518Srpaulo } 882190214Srpaulo return 0; 883190214Srpaulo} 884190214Srpaulo 885235426Sdelphijstatic int 886235426Sdelphijich_pci_resume(device_t dev) 887235426Sdelphij{ 888235426Sdelphij struct sc_info *sc; 889235426Sdelphij int i; 890235426Sdelphij 891235426Sdelphij sc = pcm_getdevinfo(dev); 892190214Srpaulo 893190214Srpaulo if (sc->regtype == SYS_RES_IOPORT) 894190214Srpaulo pci_enable_io(dev, SYS_RES_IOPORT); 895190214Srpaulo else 896190214Srpaulo pci_enable_io(dev, SYS_RES_MEMORY); 897190214Srpaulo pci_enable_busmaster(dev); 898190214Srpaulo 899190214Srpaulo /* Reinit audio device */ 900190214Srpaulo if (ich_init(sc) == -1) { 901190214Srpaulo device_printf(dev, "unable to reinitialize the card\n"); 902190214Srpaulo return ENXIO; 903190214Srpaulo } 904190214Srpaulo /* Reinit mixer */ 905190214Srpaulo ich_pci_codec_reset(sc); 906190214Srpaulo ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm); 907214518Srpaulo if (mixer_reinit(dev) == -1) { 908214518Srpaulo device_printf(dev, "unable to reinitialize the mixer\n"); 909214518Srpaulo return ENXIO; 910214518Srpaulo } 911214518Srpaulo /* Re-start DMA engines */ 912190214Srpaulo for (i = 0 ; i < 3; i++) { 913190214Srpaulo struct sc_chinfo *ch = &sc->ch[i]; 914 if (sc->ch[i].run_save) { 915 ichchan_setblocksize(0, ch, ch->blksz); 916 ichchan_setspeed(0, ch, ch->spd); 917 ichchan_trigger(0, ch, PCMTRIG_START); 918 } 919 } 920 return 0; 921} 922 923static device_method_t ich_methods[] = { 924 /* Device interface */ 925 DEVMETHOD(device_probe, ich_pci_probe), 926 DEVMETHOD(device_attach, ich_pci_attach), 927 DEVMETHOD(device_detach, ich_pci_detach), 928 DEVMETHOD(device_suspend, ich_pci_suspend), 929 DEVMETHOD(device_resume, ich_pci_resume), 930 { 0, 0 } 931}; 932 933static driver_t ich_driver = { 934 "pcm", 935 ich_methods, 936 PCM_SOFTC_SIZE, 937}; 938 939DRIVER_MODULE(snd_ich, pci, ich_driver, pcm_devclass, 0, 0); 940MODULE_DEPEND(snd_ich, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 941MODULE_VERSION(snd_ich, 1); 942