emu10k1.c revision 167608
1/*- 2 * Copyright (c) 2004 David O'Brien <obrien@FreeBSD.org> 3 * Copyright (c) 2003 Orlando Bassotto <orlando.bassotto@ieo-research.it> 4 * Copyright (c) 1999 Cameron Grant <cg@freebsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29#include <dev/sound/pcm/sound.h> 30#include <dev/sound/pcm/ac97.h> 31#include "emu10k1-alsa%diked.h" 32 33#include <dev/pci/pcireg.h> 34#include <dev/pci/pcivar.h> 35#include <sys/queue.h> 36 37#include <dev/sound/midi/mpu401.h> 38#include "mpufoi_if.h" 39 40SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/emu10k1.c 167608 2007-03-15 16:41:27Z ariff $"); 41 42/* -------------------------------------------------------------------- */ 43 44#define NUM_G 64 /* use all channels */ 45#define WAVEOUT_MAXBUFSIZE 32768 46#define EMUPAGESIZE 4096 /* don't change */ 47#define EMUMAXPAGES (WAVEOUT_MAXBUFSIZE * NUM_G / EMUPAGESIZE) 48#define EMU10K1_PCI_ID 0x00021102 /* 1102 => Creative Labs Vendor ID */ 49#define EMU10K2_PCI_ID 0x00041102 50#define EMU10K3_PCI_ID 0x00081102 51#define EMU_DEFAULT_BUFSZ 4096 52#define EMU_MAX_CHANS 8 53#define EMU_CHANS 4 54 55#define MAXREQVOICES 8 56#define RESERVED 0 57#define NUM_MIDI 16 58#define NUM_FXSENDS 4 59 60#define TMEMSIZE 256*1024 61#define TMEMSIZEREG 4 62 63#define ENABLE 0xffffffff 64#define DISABLE 0x00000000 65#define ENV_ON DCYSUSV_CHANNELENABLE_MASK 66#define ENV_OFF 0x00 /* XXX: should this be 1? */ 67 68#define A_IOCFG_GPOUT_A 0x40 /* Analog Output */ 69#define A_IOCFG_GPOUT_D 0x04 /* Digital Output */ 70#define A_IOCFG_GPOUT_AD (A_IOCFG_GPOUT_A|A_IOCFG_GPOUT_D) /* A_IOCFG_GPOUT0 */ 71 72struct emu_memblk { 73 SLIST_ENTRY(emu_memblk) link; 74 void *buf; 75 bus_addr_t buf_addr; 76 u_int32_t pte_start, pte_size; 77}; 78 79struct emu_mem { 80 u_int8_t bmap[EMUMAXPAGES / 8]; 81 u_int32_t *ptb_pages; 82 void *silent_page; 83 bus_addr_t silent_page_addr; 84 bus_addr_t ptb_pages_addr; 85 SLIST_HEAD(, emu_memblk) blocks; 86}; 87 88struct emu_voice { 89 int vnum; 90 int b16:1, stereo:1, busy:1, running:1, ismaster:1; 91 int speed; 92 int start, end, vol; 93 int fxrt1; /* FX routing */ 94 int fxrt2; /* FX routing (only for audigy) */ 95 u_int32_t buf; 96 struct emu_voice *slave; 97 struct pcm_channel *channel; 98}; 99 100struct sc_info; 101 102/* channel registers */ 103struct sc_pchinfo { 104 int spd, fmt, blksz, run; 105 struct emu_voice *master, *slave; 106 struct snd_dbuf *buffer; 107 struct pcm_channel *channel; 108 struct sc_info *parent; 109}; 110 111struct sc_rchinfo { 112 int spd, fmt, run, blksz, num; 113 u_int32_t idxreg, basereg, sizereg, setupreg, irqmask; 114 struct snd_dbuf *buffer; 115 struct pcm_channel *channel; 116 struct sc_info *parent; 117}; 118 119/* device private data */ 120struct sc_info { 121 device_t dev; 122 u_int32_t type, rev; 123 u_int32_t tos_link:1, APS:1, audigy:1, audigy2:1; 124 u_int32_t addrmask; /* wider if audigy */ 125 126 bus_space_tag_t st; 127 bus_space_handle_t sh; 128 bus_dma_tag_t parent_dmat; 129 130 struct resource *reg, *irq; 131 void *ih; 132 struct mtx *lock; 133 134 unsigned int bufsz; 135 int timer, timerinterval; 136 int pnum, rnum; 137 int nchans; 138 struct emu_mem mem; 139 struct emu_voice voice[64]; 140 struct sc_pchinfo pch[EMU_MAX_CHANS]; 141 struct sc_rchinfo rch[3]; 142 struct mpu401 *mpu; 143 mpu401_intr_t *mpu_intr; 144 int mputx; 145}; 146 147/* -------------------------------------------------------------------- */ 148 149/* 150 * prototypes 151 */ 152 153/* stuff */ 154static int emu_init(struct sc_info *); 155static void emu_intr(void *); 156static void *emu_malloc(struct sc_info *sc, u_int32_t sz, bus_addr_t *addr); 157static void *emu_memalloc(struct sc_info *sc, u_int32_t sz, bus_addr_t *addr); 158static int emu_memfree(struct sc_info *sc, void *buf); 159static int emu_memstart(struct sc_info *sc, void *buf); 160#ifdef EMUDEBUG 161static void emu_vdump(struct sc_info *sc, struct emu_voice *v); 162#endif 163 164/* talk to the card */ 165static u_int32_t emu_rd(struct sc_info *, int, int); 166static void emu_wr(struct sc_info *, int, u_int32_t, int); 167 168/* -------------------------------------------------------------------- */ 169 170static u_int32_t emu_rfmt_ac97[] = { 171 AFMT_S16_LE, 172 AFMT_STEREO | AFMT_S16_LE, 173 0 174}; 175 176static u_int32_t emu_rfmt_mic[] = { 177 AFMT_U8, 178 0 179}; 180 181static u_int32_t emu_rfmt_efx[] = { 182 AFMT_STEREO | AFMT_S16_LE, 183 0 184}; 185 186static struct pcmchan_caps emu_reccaps[3] = { 187 {8000, 48000, emu_rfmt_ac97, 0}, 188 {8000, 8000, emu_rfmt_mic, 0}, 189 {48000, 48000, emu_rfmt_efx, 0}, 190}; 191 192static u_int32_t emu_pfmt[] = { 193 AFMT_U8, 194 AFMT_STEREO | AFMT_U8, 195 AFMT_S16_LE, 196 AFMT_STEREO | AFMT_S16_LE, 197 0 198}; 199 200static struct pcmchan_caps emu_playcaps = {4000, 48000, emu_pfmt, 0}; 201 202static int adcspeed[8] = {48000, 44100, 32000, 24000, 22050, 16000, 11025, 8000}; 203/* audigy supports 12kHz. */ 204static int audigy_adcspeed[9] = { 205 48000, 44100, 32000, 24000, 22050, 16000, 12000, 11025, 8000 206}; 207 208/* -------------------------------------------------------------------- */ 209/* Hardware */ 210static u_int32_t 211emu_rd(struct sc_info *sc, int regno, int size) 212{ 213 switch (size) { 214 case 1: 215 return bus_space_read_1(sc->st, sc->sh, regno); 216 case 2: 217 return bus_space_read_2(sc->st, sc->sh, regno); 218 case 4: 219 return bus_space_read_4(sc->st, sc->sh, regno); 220 default: 221 return 0xffffffff; 222 } 223} 224 225static void 226emu_wr(struct sc_info *sc, int regno, u_int32_t data, int size) 227{ 228 switch (size) { 229 case 1: 230 bus_space_write_1(sc->st, sc->sh, regno, data); 231 break; 232 case 2: 233 bus_space_write_2(sc->st, sc->sh, regno, data); 234 break; 235 case 4: 236 bus_space_write_4(sc->st, sc->sh, regno, data); 237 break; 238 } 239} 240 241static u_int32_t 242emu_rdptr(struct sc_info *sc, int chn, int reg) 243{ 244 u_int32_t ptr, val, mask, size, offset; 245 246 ptr = ((reg << 16) & sc->addrmask) | (chn & PTR_CHANNELNUM_MASK); 247 emu_wr(sc, PTR, ptr, 4); 248 val = emu_rd(sc, DATA, 4); 249 if (reg & 0xff000000) { 250 size = (reg >> 24) & 0x3f; 251 offset = (reg >> 16) & 0x1f; 252 mask = ((1 << size) - 1) << offset; 253 val &= mask; 254 val >>= offset; 255 } 256 return val; 257} 258 259static void 260emu_wrptr(struct sc_info *sc, int chn, int reg, u_int32_t data) 261{ 262 u_int32_t ptr, mask, size, offset; 263 264 ptr = ((reg << 16) & sc->addrmask) | (chn & PTR_CHANNELNUM_MASK); 265 emu_wr(sc, PTR, ptr, 4); 266 if (reg & 0xff000000) { 267 size = (reg >> 24) & 0x3f; 268 offset = (reg >> 16) & 0x1f; 269 mask = ((1 << size) - 1) << offset; 270 data <<= offset; 271 data &= mask; 272 data |= emu_rd(sc, DATA, 4) & ~mask; 273 } 274 emu_wr(sc, DATA, data, 4); 275} 276 277static void 278emu_wrefx(struct sc_info *sc, unsigned int pc, unsigned int data) 279{ 280 pc += sc->audigy ? A_MICROCODEBASE : MICROCODEBASE; 281 emu_wrptr(sc, 0, pc, data); 282} 283 284/* -------------------------------------------------------------------- */ 285/* ac97 codec */ 286/* no locking needed */ 287 288static int 289emu_rdcd(kobj_t obj, void *devinfo, int regno) 290{ 291 struct sc_info *sc = (struct sc_info *)devinfo; 292 293 emu_wr(sc, AC97ADDRESS, regno, 1); 294 return emu_rd(sc, AC97DATA, 2); 295} 296 297static int 298emu_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data) 299{ 300 struct sc_info *sc = (struct sc_info *)devinfo; 301 302 emu_wr(sc, AC97ADDRESS, regno, 1); 303 emu_wr(sc, AC97DATA, data, 2); 304 return 0; 305} 306 307static kobj_method_t emu_ac97_methods[] = { 308 KOBJMETHOD(ac97_read, emu_rdcd), 309 KOBJMETHOD(ac97_write, emu_wrcd), 310 { 0, 0 } 311}; 312AC97_DECLARE(emu_ac97); 313 314/* -------------------------------------------------------------------- */ 315/* stuff */ 316static int 317emu_settimer(struct sc_info *sc) 318{ 319 struct sc_pchinfo *pch; 320 struct sc_rchinfo *rch; 321 int i, tmp, rate; 322 323 rate = 0; 324 for (i = 0; i < sc->nchans; i++) { 325 pch = &sc->pch[i]; 326 if (pch->buffer) { 327 tmp = (pch->spd * sndbuf_getbps(pch->buffer)) 328 / pch->blksz; 329 if (tmp > rate) 330 rate = tmp; 331 } 332 } 333 334 for (i = 0; i < 3; i++) { 335 rch = &sc->rch[i]; 336 if (rch->buffer) { 337 tmp = (rch->spd * sndbuf_getbps(rch->buffer)) 338 / rch->blksz; 339 if (tmp > rate) 340 rate = tmp; 341 } 342 } 343 RANGE(rate, 48, 9600); 344 sc->timerinterval = 48000 / rate; 345 emu_wr(sc, TIMER, sc->timerinterval & 0x03ff, 2); 346 347 return sc->timerinterval; 348} 349 350static int 351emu_enatimer(struct sc_info *sc, int go) 352{ 353 u_int32_t x; 354 if (go) { 355 if (sc->timer++ == 0) { 356 x = emu_rd(sc, INTE, 4); 357 x |= INTE_INTERVALTIMERENB; 358 emu_wr(sc, INTE, x, 4); 359 } 360 } else { 361 sc->timer = 0; 362 x = emu_rd(sc, INTE, 4); 363 x &= ~INTE_INTERVALTIMERENB; 364 emu_wr(sc, INTE, x, 4); 365 } 366 return 0; 367} 368 369static void 370emu_enastop(struct sc_info *sc, char channel, int enable) 371{ 372 int reg = (channel & 0x20) ? SOLEH : SOLEL; 373 channel &= 0x1f; 374 reg |= 1 << 24; 375 reg |= channel << 16; 376 emu_wrptr(sc, 0, reg, enable); 377} 378 379static int 380emu_recval(int speed) { 381 int val; 382 383 val = 0; 384 while (val < 7 && speed < adcspeed[val]) 385 val++; 386 return val; 387} 388 389static int 390audigy_recval(int speed) { 391 int val; 392 393 val = 0; 394 while (val < 8 && speed < audigy_adcspeed[val]) 395 val++; 396 return val; 397} 398 399static u_int32_t 400emu_rate_to_pitch(u_int32_t rate) 401{ 402 static u_int32_t logMagTable[128] = { 403 0x00000, 0x02dfc, 0x05b9e, 0x088e6, 0x0b5d6, 0x0e26f, 0x10eb3, 0x13aa2, 404 0x1663f, 0x1918a, 0x1bc84, 0x1e72e, 0x2118b, 0x23b9a, 0x2655d, 0x28ed5, 405 0x2b803, 0x2e0e8, 0x30985, 0x331db, 0x359eb, 0x381b6, 0x3a93d, 0x3d081, 406 0x3f782, 0x41e42, 0x444c1, 0x46b01, 0x49101, 0x4b6c4, 0x4dc49, 0x50191, 407 0x5269e, 0x54b6f, 0x57006, 0x59463, 0x5b888, 0x5dc74, 0x60029, 0x623a7, 408 0x646ee, 0x66a00, 0x68cdd, 0x6af86, 0x6d1fa, 0x6f43c, 0x7164b, 0x73829, 409 0x759d4, 0x77b4f, 0x79c9a, 0x7bdb5, 0x7dea1, 0x7ff5e, 0x81fed, 0x8404e, 410 0x86082, 0x88089, 0x8a064, 0x8c014, 0x8df98, 0x8fef1, 0x91e20, 0x93d26, 411 0x95c01, 0x97ab4, 0x9993e, 0x9b79f, 0x9d5d9, 0x9f3ec, 0xa11d8, 0xa2f9d, 412 0xa4d3c, 0xa6ab5, 0xa8808, 0xaa537, 0xac241, 0xadf26, 0xafbe7, 0xb1885, 413 0xb3500, 0xb5157, 0xb6d8c, 0xb899f, 0xba58f, 0xbc15e, 0xbdd0c, 0xbf899, 414 0xc1404, 0xc2f50, 0xc4a7b, 0xc6587, 0xc8073, 0xc9b3f, 0xcb5ed, 0xcd07c, 415 0xceaec, 0xd053f, 0xd1f73, 0xd398a, 0xd5384, 0xd6d60, 0xd8720, 0xda0c3, 416 0xdba4a, 0xdd3b4, 0xded03, 0xe0636, 0xe1f4e, 0xe384a, 0xe512c, 0xe69f3, 417 0xe829f, 0xe9b31, 0xeb3a9, 0xecc08, 0xee44c, 0xefc78, 0xf148a, 0xf2c83, 418 0xf4463, 0xf5c2a, 0xf73da, 0xf8b71, 0xfa2f0, 0xfba57, 0xfd1a7, 0xfe8df 419 }; 420 static char logSlopeTable[128] = { 421 0x5c, 0x5c, 0x5b, 0x5a, 0x5a, 0x59, 0x58, 0x58, 422 0x57, 0x56, 0x56, 0x55, 0x55, 0x54, 0x53, 0x53, 423 0x52, 0x52, 0x51, 0x51, 0x50, 0x50, 0x4f, 0x4f, 424 0x4e, 0x4d, 0x4d, 0x4d, 0x4c, 0x4c, 0x4b, 0x4b, 425 0x4a, 0x4a, 0x49, 0x49, 0x48, 0x48, 0x47, 0x47, 426 0x47, 0x46, 0x46, 0x45, 0x45, 0x45, 0x44, 0x44, 427 0x43, 0x43, 0x43, 0x42, 0x42, 0x42, 0x41, 0x41, 428 0x41, 0x40, 0x40, 0x40, 0x3f, 0x3f, 0x3f, 0x3e, 429 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 0x3c, 430 0x3b, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 431 0x39, 0x39, 0x39, 0x38, 0x38, 0x38, 0x38, 0x37, 432 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x36, 0x35, 433 0x35, 0x35, 0x35, 0x34, 0x34, 0x34, 0x34, 0x34, 434 0x33, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x32, 435 0x32, 0x31, 0x31, 0x31, 0x31, 0x31, 0x30, 0x30, 436 0x30, 0x30, 0x30, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f 437 }; 438 int i; 439 440 if (rate == 0) 441 return 0; /* Bail out if no leading "1" */ 442 rate *= 11185; /* Scale 48000 to 0x20002380 */ 443 for (i = 31; i > 0; i--) { 444 if (rate & 0x80000000) { /* Detect leading "1" */ 445 return (((u_int32_t) (i - 15) << 20) + 446 logMagTable[0x7f & (rate >> 24)] + 447 (0x7f & (rate >> 17)) * 448 logSlopeTable[0x7f & (rate >> 24)]); 449 } 450 rate <<= 1; 451 } 452 453 return 0; /* Should never reach this point */ 454} 455 456static u_int32_t 457emu_rate_to_linearpitch(u_int32_t rate) 458{ 459 rate = (rate << 8) / 375; 460 return (rate >> 1) + (rate & 1); 461} 462 463static struct emu_voice * 464emu_valloc(struct sc_info *sc) 465{ 466 struct emu_voice *v; 467 int i; 468 469 v = NULL; 470 for (i = 0; i < 64 && sc->voice[i].busy; i++); 471 if (i < 64) { 472 v = &sc->voice[i]; 473 v->busy = 1; 474 } 475 return v; 476} 477 478static int 479emu_vinit(struct sc_info *sc, struct emu_voice *m, struct emu_voice *s, 480 u_int32_t sz, struct snd_dbuf *b) 481{ 482 void *buf; 483 bus_addr_t tmp_addr; 484 485 buf = emu_memalloc(sc, sz, &tmp_addr); 486 if (buf == NULL) 487 return -1; 488 if (b != NULL) 489 sndbuf_setup(b, buf, sz); 490 m->start = emu_memstart(sc, buf) * EMUPAGESIZE; 491 m->end = m->start + sz; 492 m->channel = NULL; 493 m->speed = 0; 494 m->b16 = 0; 495 m->stereo = 0; 496 m->running = 0; 497 m->ismaster = 1; 498 m->vol = 0xff; 499 m->buf = tmp_addr; 500 m->slave = s; 501 if (sc->audigy) { 502 m->fxrt1 = FXBUS_MIDI_CHORUS | FXBUS_PCM_RIGHT << 8 | 503 FXBUS_PCM_LEFT << 16 | FXBUS_MIDI_REVERB << 24; 504 m->fxrt2 = 0x3f3f3f3f; /* No effects on second route */ 505 } else { 506 m->fxrt1 = FXBUS_MIDI_CHORUS | FXBUS_PCM_RIGHT << 4 | 507 FXBUS_PCM_LEFT << 8 | FXBUS_MIDI_REVERB << 12; 508 m->fxrt2 = 0; 509 } 510 511 if (s != NULL) { 512 s->start = m->start; 513 s->end = m->end; 514 s->channel = NULL; 515 s->speed = 0; 516 s->b16 = 0; 517 s->stereo = 0; 518 s->running = 0; 519 s->ismaster = 0; 520 s->vol = m->vol; 521 s->buf = m->buf; 522 s->fxrt1 = m->fxrt1; 523 s->fxrt2 = m->fxrt2; 524 s->slave = NULL; 525 } 526 return 0; 527} 528 529static void 530emu_vsetup(struct sc_pchinfo *ch) 531{ 532 struct emu_voice *v = ch->master; 533 534 if (ch->fmt) { 535 v->b16 = (ch->fmt & AFMT_16BIT) ? 1 : 0; 536 v->stereo = (ch->fmt & AFMT_STEREO) ? 1 : 0; 537 if (v->slave != NULL) { 538 v->slave->b16 = v->b16; 539 v->slave->stereo = v->stereo; 540 } 541 } 542 if (ch->spd) { 543 v->speed = ch->spd; 544 if (v->slave != NULL) 545 v->slave->speed = v->speed; 546 } 547} 548 549static void 550emu_vwrite(struct sc_info *sc, struct emu_voice *v) 551{ 552 int s; 553 int l, r, x, y; 554 u_int32_t sa, ea, start, val, silent_page; 555 556 s = (v->stereo ? 1 : 0) + (v->b16 ? 1 : 0); 557 558 sa = v->start >> s; 559 ea = v->end >> s; 560 561 l = r = x = y = v->vol; 562 if (v->stereo) { 563 l = v->ismaster ? l : 0; 564 r = v->ismaster ? 0 : r; 565 } 566 567 emu_wrptr(sc, v->vnum, CPF, v->stereo ? CPF_STEREO_MASK : 0); 568 val = v->stereo ? 28 : 30; 569 val *= v->b16 ? 1 : 2; 570 start = sa + val; 571 572 if (sc->audigy) { 573 emu_wrptr(sc, v->vnum, A_FXRT1, v->fxrt1); 574 emu_wrptr(sc, v->vnum, A_FXRT2, v->fxrt2); 575 emu_wrptr(sc, v->vnum, A_SENDAMOUNTS, 0); 576 } 577 else 578 emu_wrptr(sc, v->vnum, FXRT, v->fxrt1 << 16); 579 580 emu_wrptr(sc, v->vnum, PTRX, (x << 8) | r); 581 emu_wrptr(sc, v->vnum, DSL, ea | (y << 24)); 582 emu_wrptr(sc, v->vnum, PSST, sa | (l << 24)); 583 emu_wrptr(sc, v->vnum, CCCA, start | (v->b16 ? 0 : CCCA_8BITSELECT)); 584 585 emu_wrptr(sc, v->vnum, Z1, 0); 586 emu_wrptr(sc, v->vnum, Z2, 0); 587 588 silent_page = ((u_int32_t)(sc->mem.silent_page_addr) << 1) 589 | MAP_PTI_MASK; 590 emu_wrptr(sc, v->vnum, MAPA, silent_page); 591 emu_wrptr(sc, v->vnum, MAPB, silent_page); 592 593 emu_wrptr(sc, v->vnum, CVCF, CVCF_CURRENTFILTER_MASK); 594 emu_wrptr(sc, v->vnum, VTFT, VTFT_FILTERTARGET_MASK); 595 emu_wrptr(sc, v->vnum, ATKHLDM, 0); 596 emu_wrptr(sc, v->vnum, DCYSUSM, DCYSUSM_DECAYTIME_MASK); 597 emu_wrptr(sc, v->vnum, LFOVAL1, 0x8000); 598 emu_wrptr(sc, v->vnum, LFOVAL2, 0x8000); 599 emu_wrptr(sc, v->vnum, FMMOD, 0); 600 emu_wrptr(sc, v->vnum, TREMFRQ, 0); 601 emu_wrptr(sc, v->vnum, FM2FRQ2, 0); 602 emu_wrptr(sc, v->vnum, ENVVAL, 0x8000); 603 604 emu_wrptr(sc, v->vnum, ATKHLDV, 605 ATKHLDV_HOLDTIME_MASK | ATKHLDV_ATTACKTIME_MASK); 606 emu_wrptr(sc, v->vnum, ENVVOL, 0x8000); 607 608 emu_wrptr(sc, v->vnum, PEFE_FILTERAMOUNT, 0x7f); 609 emu_wrptr(sc, v->vnum, PEFE_PITCHAMOUNT, 0); 610 611 if (v->slave != NULL) 612 emu_vwrite(sc, v->slave); 613} 614 615static void 616emu_vtrigger(struct sc_info *sc, struct emu_voice *v, int go) 617{ 618 u_int32_t pitch_target, initial_pitch; 619 u_int32_t cra, cs, ccis; 620 u_int32_t sample, i; 621 622 if (go) { 623 cra = 64; 624 cs = v->stereo ? 4 : 2; 625 ccis = v->stereo ? 28 : 30; 626 ccis *= v->b16 ? 1 : 2; 627 sample = v->b16 ? 0x00000000 : 0x80808080; 628 629 for (i = 0; i < cs; i++) 630 emu_wrptr(sc, v->vnum, CD0 + i, sample); 631 emu_wrptr(sc, v->vnum, CCR_CACHEINVALIDSIZE, 0); 632 emu_wrptr(sc, v->vnum, CCR_READADDRESS, cra); 633 emu_wrptr(sc, v->vnum, CCR_CACHEINVALIDSIZE, ccis); 634 635 emu_wrptr(sc, v->vnum, IFATN, 0xff00); 636 emu_wrptr(sc, v->vnum, VTFT, 0xffffffff); 637 emu_wrptr(sc, v->vnum, CVCF, 0xffffffff); 638 emu_wrptr(sc, v->vnum, DCYSUSV, 0x00007f7f); 639 emu_enastop(sc, v->vnum, 0); 640 641 pitch_target = emu_rate_to_linearpitch(v->speed); 642 initial_pitch = emu_rate_to_pitch(v->speed) >> 8; 643 emu_wrptr(sc, v->vnum, PTRX_PITCHTARGET, pitch_target); 644 emu_wrptr(sc, v->vnum, CPF_CURRENTPITCH, pitch_target); 645 emu_wrptr(sc, v->vnum, IP, initial_pitch); 646 } else { 647 emu_wrptr(sc, v->vnum, PTRX_PITCHTARGET, 0); 648 emu_wrptr(sc, v->vnum, CPF_CURRENTPITCH, 0); 649 emu_wrptr(sc, v->vnum, IFATN, 0xffff); 650 emu_wrptr(sc, v->vnum, VTFT, 0x0000ffff); 651 emu_wrptr(sc, v->vnum, CVCF, 0x0000ffff); 652 emu_wrptr(sc, v->vnum, IP, 0); 653 emu_enastop(sc, v->vnum, 1); 654 } 655 if (v->slave != NULL) 656 emu_vtrigger(sc, v->slave, go); 657} 658 659static int 660emu_vpos(struct sc_info *sc, struct emu_voice *v) 661{ 662 int s, ptr; 663 664 s = (v->b16 ? 1 : 0) + (v->stereo ? 1 : 0); 665 ptr = (emu_rdptr(sc, v->vnum, CCCA_CURRADDR) - (v->start >> s)) << s; 666 return ptr & ~0x0000001f; 667} 668 669#ifdef EMUDEBUG 670static void 671emu_vdump(struct sc_info *sc, struct emu_voice *v) 672{ 673 char *regname[] = { 674 "cpf", "ptrx", "cvcf", "vtft", "z2", "z1", "psst", "dsl", 675 "ccca", "ccr", "clp", "fxrt", "mapa", "mapb", NULL, NULL, 676 "envvol", "atkhldv", "dcysusv", "lfoval1", 677 "envval", "atkhldm", "dcysusm", "lfoval2", 678 "ip", "ifatn", "pefe", "fmmod", "tremfrq", "fmfrq2", 679 "tempenv" 680 }; 681 char *regname2[] = { 682 "mudata1", "mustat1", "mudata2", "mustat2", 683 "fxwc1", "fxwc2", "spdrate", NULL, NULL, 684 NULL, NULL, NULL, "fxrt2", "sndamnt", "fxrt1", 685 NULL, NULL 686 }; 687 int i, x; 688 689 printf("voice number %d\n", v->vnum); 690 for (i = 0, x = 0; i <= 0x1e; i++) { 691 if (regname[i] == NULL) 692 continue; 693 printf("%s\t[%08x]", regname[i], emu_rdptr(sc, v->vnum, i)); 694 printf("%s", (x == 2) ? "\n" : "\t"); 695 x++; 696 if (x > 2) 697 x = 0; 698 } 699 700 /* Print out audigy extra registers */ 701 if (sc->audigy) { 702 for (i = 0; i <= 0xe; i++) { 703 if (regname2[i] == NULL) 704 continue; 705 printf("%s\t[%08x]", regname2[i], 706 emu_rdptr(sc, v->vnum, i + 0x70)); 707 printf("%s", (x == 2)? "\n" : "\t"); 708 x++; 709 if (x > 2) 710 x = 0; 711 } 712 } 713 printf("\n\n"); 714} 715#endif 716 717/* channel interface */ 718static void * 719emupchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, 720 struct pcm_channel *c, int dir) 721{ 722 struct sc_info *sc = devinfo; 723 struct sc_pchinfo *ch; 724 void *r; 725 726 KASSERT(dir == PCMDIR_PLAY, ("emupchan_init: bad direction")); 727 ch = &sc->pch[sc->pnum++]; 728 ch->buffer = b; 729 ch->parent = sc; 730 ch->channel = c; 731 ch->blksz = sc->bufsz / 2; 732 ch->fmt = AFMT_U8; 733 ch->spd = 8000; 734 snd_mtxlock(sc->lock); 735 ch->master = emu_valloc(sc); 736 ch->slave = emu_valloc(sc); 737 snd_mtxunlock(sc->lock); 738 r = (emu_vinit(sc, ch->master, ch->slave, sc->bufsz, ch->buffer)) 739 ? NULL : ch; 740 741 return r; 742} 743 744static int 745emupchan_free(kobj_t obj, void *data) 746{ 747 struct sc_pchinfo *ch = data; 748 struct sc_info *sc = ch->parent; 749 int r; 750 751 snd_mtxlock(sc->lock); 752 r = emu_memfree(sc, sndbuf_getbuf(ch->buffer)); 753 snd_mtxunlock(sc->lock); 754 755 return r; 756} 757 758static int 759emupchan_setformat(kobj_t obj, void *data, u_int32_t format) 760{ 761 struct sc_pchinfo *ch = data; 762 763 ch->fmt = format; 764 return 0; 765} 766 767static int 768emupchan_setspeed(kobj_t obj, void *data, u_int32_t speed) 769{ 770 struct sc_pchinfo *ch = data; 771 772 ch->spd = speed; 773 return ch->spd; 774} 775 776static int 777emupchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 778{ 779 struct sc_pchinfo *ch = data; 780 struct sc_info *sc = ch->parent; 781 int irqrate, blksz; 782 783 ch->blksz = blocksize; 784 snd_mtxlock(sc->lock); 785 emu_settimer(sc); 786 irqrate = 48000 / sc->timerinterval; 787 snd_mtxunlock(sc->lock); 788 blksz = (ch->spd * sndbuf_getbps(ch->buffer)) / irqrate; 789 return blocksize; 790} 791 792static int 793emupchan_trigger(kobj_t obj, void *data, int go) 794{ 795 struct sc_pchinfo *ch = data; 796 struct sc_info *sc = ch->parent; 797 798 if (go == PCMTRIG_EMLDMAWR || go == PCMTRIG_EMLDMARD) 799 return 0; 800 801 snd_mtxlock(sc->lock); 802 if (go == PCMTRIG_START) { 803 emu_vsetup(ch); 804 emu_vwrite(sc, ch->master); 805 emu_settimer(sc); 806 emu_enatimer(sc, 1); 807#ifdef EMUDEBUG 808 printf("start [%d bit, %s, %d hz]\n", 809 ch->master->b16 ? 16 : 8, 810 ch->master->stereo ? "stereo" : "mono", 811 ch->master->speed); 812 emu_vdump(sc, ch->master); 813 emu_vdump(sc, ch->slave); 814#endif 815 } 816 ch->run = (go == PCMTRIG_START) ? 1 : 0; 817 emu_vtrigger(sc, ch->master, ch->run); 818 snd_mtxunlock(sc->lock); 819 return 0; 820} 821 822static int 823emupchan_getptr(kobj_t obj, void *data) 824{ 825 struct sc_pchinfo *ch = data; 826 struct sc_info *sc = ch->parent; 827 int r; 828 829 snd_mtxlock(sc->lock); 830 r = emu_vpos(sc, ch->master); 831 snd_mtxunlock(sc->lock); 832 833 return r; 834} 835 836static struct pcmchan_caps * 837emupchan_getcaps(kobj_t obj, void *data) 838{ 839 return &emu_playcaps; 840} 841 842static kobj_method_t emupchan_methods[] = { 843 KOBJMETHOD(channel_init, emupchan_init), 844 KOBJMETHOD(channel_free, emupchan_free), 845 KOBJMETHOD(channel_setformat, emupchan_setformat), 846 KOBJMETHOD(channel_setspeed, emupchan_setspeed), 847 KOBJMETHOD(channel_setblocksize, emupchan_setblocksize), 848 KOBJMETHOD(channel_trigger, emupchan_trigger), 849 KOBJMETHOD(channel_getptr, emupchan_getptr), 850 KOBJMETHOD(channel_getcaps, emupchan_getcaps), 851 { 0, 0 } 852}; 853CHANNEL_DECLARE(emupchan); 854 855/* channel interface */ 856static void * 857emurchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, 858 struct pcm_channel *c, int dir) 859{ 860 struct sc_info *sc = devinfo; 861 struct sc_rchinfo *ch; 862 863 KASSERT(dir == PCMDIR_REC, ("emurchan_init: bad direction")); 864 ch = &sc->rch[sc->rnum]; 865 ch->buffer = b; 866 ch->parent = sc; 867 ch->channel = c; 868 ch->blksz = sc->bufsz / 2; 869 ch->fmt = AFMT_U8; 870 ch->spd = 8000; 871 ch->num = sc->rnum; 872 switch(sc->rnum) { 873 case 0: 874 ch->idxreg = sc->audigy ? A_ADCIDX : ADCIDX; 875 ch->basereg = ADCBA; 876 ch->sizereg = ADCBS; 877 ch->setupreg = ADCCR; 878 ch->irqmask = INTE_ADCBUFENABLE; 879 break; 880 881 case 1: 882 ch->idxreg = FXIDX; 883 ch->basereg = FXBA; 884 ch->sizereg = FXBS; 885 ch->setupreg = FXWC; 886 ch->irqmask = INTE_EFXBUFENABLE; 887 break; 888 889 case 2: 890 ch->idxreg = MICIDX; 891 ch->basereg = MICBA; 892 ch->sizereg = MICBS; 893 ch->setupreg = 0; 894 ch->irqmask = INTE_MICBUFENABLE; 895 break; 896 } 897 sc->rnum++; 898 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, sc->bufsz) != 0) 899 return NULL; 900 else { 901 snd_mtxlock(sc->lock); 902 emu_wrptr(sc, 0, ch->basereg, sndbuf_getbufaddr(ch->buffer)); 903 emu_wrptr(sc, 0, ch->sizereg, 0); /* off */ 904 snd_mtxunlock(sc->lock); 905 return ch; 906 } 907} 908 909static int 910emurchan_setformat(kobj_t obj, void *data, u_int32_t format) 911{ 912 struct sc_rchinfo *ch = data; 913 914 ch->fmt = format; 915 return 0; 916} 917 918static int 919emurchan_setspeed(kobj_t obj, void *data, u_int32_t speed) 920{ 921 struct sc_rchinfo *ch = data; 922 923 if (ch->num == 0) { 924 if (ch->parent->audigy) 925 speed = audigy_adcspeed[audigy_recval(speed)]; 926 else 927 speed = adcspeed[emu_recval(speed)]; 928 } 929 if (ch->num == 1) 930 speed = 48000; 931 if (ch->num == 2) 932 speed = 8000; 933 ch->spd = speed; 934 return ch->spd; 935} 936 937static int 938emurchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 939{ 940 struct sc_rchinfo *ch = data; 941 struct sc_info *sc = ch->parent; 942 int irqrate, blksz; 943 944 ch->blksz = blocksize; 945 snd_mtxlock(sc->lock); 946 emu_settimer(sc); 947 irqrate = 48000 / sc->timerinterval; 948 snd_mtxunlock(sc->lock); 949 blksz = (ch->spd * sndbuf_getbps(ch->buffer)) / irqrate; 950 return blocksize; 951} 952 953/* semantic note: must start at beginning of buffer */ 954static int 955emurchan_trigger(kobj_t obj, void *data, int go) 956{ 957 struct sc_rchinfo *ch = data; 958 struct sc_info *sc = ch->parent; 959 u_int32_t val, sz; 960 961 switch(sc->bufsz) { 962 case 4096: 963 sz = ADCBS_BUFSIZE_4096; 964 break; 965 966 case 8192: 967 sz = ADCBS_BUFSIZE_8192; 968 break; 969 970 case 16384: 971 sz = ADCBS_BUFSIZE_16384; 972 break; 973 974 case 32768: 975 sz = ADCBS_BUFSIZE_32768; 976 break; 977 978 case 65536: 979 sz = ADCBS_BUFSIZE_65536; 980 break; 981 982 default: 983 sz = ADCBS_BUFSIZE_4096; 984 } 985 986 snd_mtxlock(sc->lock); 987 switch(go) { 988 case PCMTRIG_START: 989 ch->run = 1; 990 emu_wrptr(sc, 0, ch->sizereg, sz); 991 if (ch->num == 0) { 992 if (sc->audigy) { 993 val = A_ADCCR_LCHANENABLE; 994 if (ch->fmt & AFMT_STEREO) 995 val |= A_ADCCR_RCHANENABLE; 996 val |= audigy_recval(ch->spd); 997 } else { 998 val = ADCCR_LCHANENABLE; 999 if (ch->fmt & AFMT_STEREO) 1000 val |= ADCCR_RCHANENABLE; 1001 val |= emu_recval(ch->spd); 1002 } 1003 1004 emu_wrptr(sc, 0, ch->setupreg, 0); 1005 emu_wrptr(sc, 0, ch->setupreg, val); 1006 } 1007 val = emu_rd(sc, INTE, 4); 1008 val |= ch->irqmask; 1009 emu_wr(sc, INTE, val, 4); 1010 break; 1011 1012 case PCMTRIG_STOP: 1013 case PCMTRIG_ABORT: 1014 ch->run = 0; 1015 emu_wrptr(sc, 0, ch->sizereg, 0); 1016 if (ch->setupreg) 1017 emu_wrptr(sc, 0, ch->setupreg, 0); 1018 val = emu_rd(sc, INTE, 4); 1019 val &= ~ch->irqmask; 1020 emu_wr(sc, INTE, val, 4); 1021 break; 1022 1023 case PCMTRIG_EMLDMAWR: 1024 case PCMTRIG_EMLDMARD: 1025 default: 1026 break; 1027 } 1028 snd_mtxunlock(sc->lock); 1029 1030 return 0; 1031} 1032 1033static int 1034emurchan_getptr(kobj_t obj, void *data) 1035{ 1036 struct sc_rchinfo *ch = data; 1037 struct sc_info *sc = ch->parent; 1038 int r; 1039 1040 snd_mtxlock(sc->lock); 1041 r = emu_rdptr(sc, 0, ch->idxreg) & 0x0000ffff; 1042 snd_mtxunlock(sc->lock); 1043 1044 return r; 1045} 1046 1047static struct pcmchan_caps * 1048emurchan_getcaps(kobj_t obj, void *data) 1049{ 1050 struct sc_rchinfo *ch = data; 1051 1052 return &emu_reccaps[ch->num]; 1053} 1054 1055static kobj_method_t emurchan_methods[] = { 1056 KOBJMETHOD(channel_init, emurchan_init), 1057 KOBJMETHOD(channel_setformat, emurchan_setformat), 1058 KOBJMETHOD(channel_setspeed, emurchan_setspeed), 1059 KOBJMETHOD(channel_setblocksize, emurchan_setblocksize), 1060 KOBJMETHOD(channel_trigger, emurchan_trigger), 1061 KOBJMETHOD(channel_getptr, emurchan_getptr), 1062 KOBJMETHOD(channel_getcaps, emurchan_getcaps), 1063 { 0, 0 } 1064}; 1065CHANNEL_DECLARE(emurchan); 1066 1067static unsigned char 1068emu_mread(void *arg, struct sc_info *sc, int reg) 1069{ 1070 unsigned int d; 1071 1072 d = emu_rd(sc, 0x18 + reg, 1); 1073 return d; 1074} 1075 1076static void 1077emu_mwrite(void *arg, struct sc_info *sc, int reg, unsigned char b) 1078{ 1079 1080 emu_wr(sc, 0x18 + reg, b, 1); 1081} 1082 1083static int 1084emu_muninit(void *arg, struct sc_info *sc) 1085{ 1086 1087 snd_mtxlock(sc->lock); 1088 sc->mpu_intr = 0; 1089 snd_mtxunlock(sc->lock); 1090 1091 return 0; 1092} 1093 1094static kobj_method_t emu_mpu_methods[] = { 1095 KOBJMETHOD(mpufoi_read, emu_mread), 1096 KOBJMETHOD(mpufoi_write, emu_mwrite), 1097 KOBJMETHOD(mpufoi_uninit, emu_muninit), 1098 { 0, 0 } 1099}; 1100 1101static DEFINE_CLASS(emu_mpu, emu_mpu_methods, 0); 1102 1103static void 1104emu_intr2(void *p) 1105{ 1106 struct sc_info *sc = (struct sc_info *)p; 1107 1108 if (sc->mpu_intr) 1109 (sc->mpu_intr)(sc->mpu); 1110} 1111 1112static void 1113emu_midiattach(struct sc_info *sc) 1114{ 1115 int i; 1116 1117 i = emu_rd(sc, INTE, 4); 1118 i |= INTE_MIDIRXENABLE; 1119 emu_wr(sc, INTE, i, 4); 1120 1121 sc->mpu = mpu401_init(&emu_mpu_class, sc, emu_intr2, &sc->mpu_intr); 1122} 1123/* -------------------------------------------------------------------- */ 1124/* The interrupt handler */ 1125 1126static void 1127emu_intr(void *data) 1128{ 1129 struct sc_info *sc = data; 1130 u_int32_t stat, ack, i, x; 1131 1132 snd_mtxlock(sc->lock); 1133 while (1) { 1134 stat = emu_rd(sc, IPR, 4); 1135 if (stat == 0) 1136 break; 1137 ack = 0; 1138 1139 /* process irq */ 1140 if (stat & IPR_INTERVALTIMER) 1141 ack |= IPR_INTERVALTIMER; 1142 1143 if (stat & (IPR_ADCBUFFULL | IPR_ADCBUFHALFFULL)) 1144 ack |= stat & (IPR_ADCBUFFULL | IPR_ADCBUFHALFFULL); 1145 1146 if (stat & (IPR_EFXBUFFULL | IPR_EFXBUFHALFFULL)) 1147 ack |= stat & (IPR_EFXBUFFULL | IPR_EFXBUFHALFFULL); 1148 1149 if (stat & (IPR_MICBUFFULL | IPR_MICBUFHALFFULL)) 1150 ack |= stat & (IPR_MICBUFFULL | IPR_MICBUFHALFFULL); 1151 1152 if (stat & IPR_PCIERROR) { 1153 ack |= IPR_PCIERROR; 1154 device_printf(sc->dev, "pci error\n"); 1155 /* we still get an nmi with ecc ram even if we ack this */ 1156 } 1157 if (stat & IPR_SAMPLERATETRACKER) { 1158 ack |= IPR_SAMPLERATETRACKER; 1159#ifdef EMUDEBUG 1160 device_printf(sc->dev, 1161 "sample rate tracker lock status change\n"); 1162#endif 1163 } 1164 1165 if (stat & IPR_MIDIRECVBUFEMPTY) 1166 if (sc->mpu_intr) { 1167 (sc->mpu_intr)(sc->mpu); 1168 ack |= IPR_MIDIRECVBUFEMPTY | IPR_MIDITRANSBUFEMPTY; 1169 } 1170 if (stat & ~ack) 1171 device_printf(sc->dev, "dodgy irq: %x (harmless)\n", 1172 stat & ~ack); 1173 1174 emu_wr(sc, IPR, stat, 4); 1175 1176 if (ack) { 1177 snd_mtxunlock(sc->lock); 1178 1179 if (ack & IPR_INTERVALTIMER) { 1180 x = 0; 1181 for (i = 0; i < sc->nchans; i++) { 1182 if (sc->pch[i].run) { 1183 x = 1; 1184 chn_intr(sc->pch[i].channel); 1185 } 1186 } 1187 if (x == 0) 1188 emu_enatimer(sc, 0); 1189 } 1190 1191 1192 if (ack & (IPR_ADCBUFFULL | IPR_ADCBUFHALFFULL)) { 1193 if (sc->rch[0].channel) 1194 chn_intr(sc->rch[0].channel); 1195 } 1196 if (ack & (IPR_EFXBUFFULL | IPR_EFXBUFHALFFULL)) { 1197 if (sc->rch[1].channel) 1198 chn_intr(sc->rch[1].channel); 1199 } 1200 if (ack & (IPR_MICBUFFULL | IPR_MICBUFHALFFULL)) { 1201 if (sc->rch[2].channel) 1202 chn_intr(sc->rch[2].channel); 1203 } 1204 1205 snd_mtxlock(sc->lock); 1206 } 1207 } 1208 snd_mtxunlock(sc->lock); 1209} 1210 1211/* -------------------------------------------------------------------- */ 1212 1213static void 1214emu_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1215{ 1216 bus_addr_t *phys = arg; 1217 1218 *phys = error ? 0 : (bus_addr_t)segs->ds_addr; 1219 1220 if (bootverbose) { 1221 printf("emu: setmap (%lx, %lx), nseg=%d, error=%d\n", 1222 (unsigned long)segs->ds_addr, (unsigned long)segs->ds_len, 1223 nseg, error); 1224 } 1225} 1226 1227static void * 1228emu_malloc(struct sc_info *sc, u_int32_t sz, bus_addr_t *addr) 1229{ 1230 void *buf; 1231 bus_dmamap_t map; 1232 1233 *addr = 0; 1234 if (bus_dmamem_alloc(sc->parent_dmat, &buf, BUS_DMA_NOWAIT, &map)) 1235 return NULL; 1236 if (bus_dmamap_load(sc->parent_dmat, map, buf, sz, emu_setmap, addr, 0) 1237 || !*addr) 1238 return NULL; 1239 return buf; 1240} 1241 1242static void 1243emu_free(struct sc_info *sc, void *buf) 1244{ 1245 bus_dmamem_free(sc->parent_dmat, buf, NULL); 1246} 1247 1248static void * 1249emu_memalloc(struct sc_info *sc, u_int32_t sz, bus_addr_t *addr) 1250{ 1251 u_int32_t blksz, start, idx, ofs, tmp, found; 1252 struct emu_mem *mem = &sc->mem; 1253 struct emu_memblk *blk; 1254 void *buf; 1255 1256 blksz = sz / EMUPAGESIZE; 1257 if (sz > (blksz * EMUPAGESIZE)) 1258 blksz++; 1259 /* find a free block in the bitmap */ 1260 found = 0; 1261 start = 1; 1262 while (!found && start + blksz < EMUMAXPAGES) { 1263 found = 1; 1264 for (idx = start; idx < start + blksz; idx++) 1265 if (mem->bmap[idx >> 3] & (1 << (idx & 7))) 1266 found = 0; 1267 if (!found) 1268 start++; 1269 } 1270 if (!found) 1271 return NULL; 1272 blk = malloc(sizeof(*blk), M_DEVBUF, M_NOWAIT); 1273 if (blk == NULL) 1274 return NULL; 1275 buf = emu_malloc(sc, sz, &blk->buf_addr); 1276 *addr = blk->buf_addr; 1277 if (buf == NULL) { 1278 free(blk, M_DEVBUF); 1279 return NULL; 1280 } 1281 blk->buf = buf; 1282 blk->pte_start = start; 1283 blk->pte_size = blksz; 1284#ifdef EMUDEBUG 1285 printf("buf %p, pte_start %d, pte_size %d\n", blk->buf, 1286 blk->pte_start, blk->pte_size); 1287#endif 1288 ofs = 0; 1289 for (idx = start; idx < start + blksz; idx++) { 1290 mem->bmap[idx >> 3] |= 1 << (idx & 7); 1291 tmp = (u_int32_t)(u_long)((u_int8_t *)blk->buf_addr + ofs); 1292#ifdef EMUDEBUG 1293 printf("pte[%d] -> %x phys, %x virt\n", idx, tmp, 1294 ((u_int32_t)buf) + ofs); 1295#endif 1296 mem->ptb_pages[idx] = (tmp << 1) | idx; 1297 ofs += EMUPAGESIZE; 1298 } 1299 SLIST_INSERT_HEAD(&mem->blocks, blk, link); 1300 return buf; 1301} 1302 1303static int 1304emu_memfree(struct sc_info *sc, void *buf) 1305{ 1306 u_int32_t idx, tmp; 1307 struct emu_mem *mem = &sc->mem; 1308 struct emu_memblk *blk, *i; 1309 1310 blk = NULL; 1311 SLIST_FOREACH(i, &mem->blocks, link) { 1312 if (i->buf == buf) 1313 blk = i; 1314 } 1315 if (blk == NULL) 1316 return EINVAL; 1317 SLIST_REMOVE(&mem->blocks, blk, emu_memblk, link); 1318 emu_free(sc, buf); 1319 tmp = (u_int32_t)(sc->mem.silent_page_addr) << 1; 1320 for (idx = blk->pte_start; idx < blk->pte_start + blk->pte_size; idx++) { 1321 mem->bmap[idx >> 3] &= ~(1 << (idx & 7)); 1322 mem->ptb_pages[idx] = tmp | idx; 1323 } 1324 free(blk, M_DEVBUF); 1325 return 0; 1326} 1327 1328static int 1329emu_memstart(struct sc_info *sc, void *buf) 1330{ 1331 struct emu_mem *mem = &sc->mem; 1332 struct emu_memblk *blk, *i; 1333 1334 blk = NULL; 1335 SLIST_FOREACH(i, &mem->blocks, link) { 1336 if (i->buf == buf) 1337 blk = i; 1338 } 1339 if (blk == NULL) 1340 return -EINVAL; 1341 return blk->pte_start; 1342} 1343 1344static void 1345emu_addefxop(struct sc_info *sc, int op, int z, int w, int x, int y, 1346 u_int32_t *pc) 1347{ 1348 emu_wrefx(sc, (*pc) * 2, (x << 10) | y); 1349 emu_wrefx(sc, (*pc) * 2 + 1, (op << 20) | (z << 10) | w); 1350 (*pc)++; 1351} 1352 1353static void 1354audigy_addefxop(struct sc_info *sc, int op, int z, int w, int x, int y, 1355 u_int32_t *pc) 1356{ 1357 emu_wrefx(sc, (*pc) * 2, (x << 12) | y); 1358 emu_wrefx(sc, (*pc) * 2 + 1, (op << 24) | (z << 12) | w); 1359 (*pc)++; 1360} 1361 1362static void 1363audigy_initefx(struct sc_info *sc) 1364{ 1365 int i; 1366 u_int32_t pc = 0; 1367 1368 /* skip 0, 0, -1, 0 - NOPs */ 1369 for (i = 0; i < 512; i++) 1370 audigy_addefxop(sc, 0x0f, 0x0c0, 0x0c0, 0x0cf, 0x0c0, &pc); 1371 1372 for (i = 0; i < 512; i++) 1373 emu_wrptr(sc, 0, A_FXGPREGBASE + i, 0x0); 1374 1375 pc = 16; 1376 1377 /* stop fx processor */ 1378 emu_wrptr(sc, 0, A_DBG, A_DBG_SINGLE_STEP); 1379 1380 /* Audigy 2 (EMU10K2) DSP Registers: 1381 FX Bus 1382 0x000-0x00f : 16 registers (?) 1383 Input 1384 0x040/0x041 : AC97 Codec (l/r) 1385 0x042/0x043 : ADC, S/PDIF (l/r) 1386 0x044/0x045 : Optical S/PDIF in (l/r) 1387 0x046/0x047 : ? 1388 0x048/0x049 : Line/Mic 2 (l/r) 1389 0x04a/0x04b : RCA S/PDIF (l/r) 1390 0x04c/0x04d : Aux 2 (l/r) 1391 Output 1392 0x060/0x061 : Digital Front (l/r) 1393 0x062/0x063 : Digital Center/LFE 1394 0x064/0x065 : AudigyDrive Heaphone (l/r) 1395 0x066/0x067 : Digital Rear (l/r) 1396 0x068/0x069 : Analog Front (l/r) 1397 0x06a/0x06b : Analog Center/LFE 1398 0x06c/0x06d : ? 1399 0x06e/0x06f : Analog Rear (l/r) 1400 0x070/0x071 : AC97 Output (l/r) 1401 0x072/0x073 : ? 1402 0x074/0x075 : ? 1403 0x076/0x077 : ADC Recording Buffer (l/r) 1404 Constants 1405 0x0c0 - 0x0c4 = 0 - 4 1406 0x0c5 = 0x8, 0x0c6 = 0x10, 0x0c7 = 0x20 1407 0x0c8 = 0x100, 0x0c9 = 0x10000, 0x0ca = 0x80000 1408 0x0cb = 0x10000000, 0x0cc = 0x20000000, 0x0cd = 0x40000000 1409 0x0ce = 0x80000000, 0x0cf = 0x7fffffff, 0x0d0 = 0xffffffff 1410 0x0d1 = 0xfffffffe, 0x0d2 = 0xc0000000, 0x0d3 = 0x41fbbcdc 1411 0x0d4 = 0x5a7ef9db, 0x0d5 = 0x00100000, 0x0dc = 0x00000001 (?) 1412 Temporary Values 1413 0x0d6 : Accumulator (?) 1414 0x0d7 : Condition Register 1415 0x0d8 : Noise source 1416 0x0d9 : Noise source 1417 Tank Memory Data Registers 1418 0x200 - 0x2ff 1419 Tank Memory Address Registers 1420 0x300 - 0x3ff 1421 General Purpose Registers 1422 0x400 - 0x5ff 1423 */ 1424 1425 /* AC97Output[l/r] = FXBus PCM[l/r] */ 1426 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AC97_L), A_C_00000000, 1427 A_C_00000000, A_FXBUS(FXBUS_PCM_LEFT), &pc); 1428 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AC97_R), A_C_00000000, 1429 A_C_00000000, A_FXBUS(FXBUS_PCM_RIGHT), &pc); 1430 1431 /* GPR[0/1] = RCA S/PDIF[l/r] -- Master volume */ 1432 audigy_addefxop(sc, iACC3, A_GPR(0), A_C_00000000, 1433 A_C_00000000, A_EXTIN(EXTIN_COAX_SPDIF_L), &pc); 1434 audigy_addefxop(sc, iACC3, A_GPR(1), A_C_00000000, 1435 A_C_00000000, A_EXTIN(EXTIN_COAX_SPDIF_R), &pc); 1436 1437 /* GPR[2] = GPR[0] (Left) / 2 + GPR[1] (Right) / 2 -- Central volume */ 1438 audigy_addefxop(sc, iINTERP, A_GPR(2), A_GPR(1), 1439 A_C_40000000, A_GPR(0), &pc); 1440 1441 /* Headphones[l/r] = GPR[0/1] */ 1442 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_HEADPHONE_L), 1443 A_C_00000000, A_C_00000000, A_GPR(0), &pc); 1444 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_HEADPHONE_R), 1445 A_C_00000000, A_C_00000000, A_GPR(1), &pc); 1446 1447 /* Analog Front[l/r] = GPR[0/1] */ 1448 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AFRONT_L), A_C_00000000, 1449 A_C_00000000, A_GPR(0), &pc); 1450 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AFRONT_R), A_C_00000000, 1451 A_C_00000000, A_GPR(1), &pc); 1452 1453 /* Digital Front[l/r] = GPR[0/1] */ 1454 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L), A_C_00000000, 1455 A_C_00000000, A_GPR(0), &pc); 1456 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_FRONT_R), A_C_00000000, 1457 A_C_00000000, A_GPR(1), &pc); 1458 1459 /* Center and Subwoofer configuration */ 1460 /* Analog Center = GPR[0] + GPR[2] */ 1461 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ACENTER), A_C_00000000, 1462 A_GPR(0), A_GPR(2), &pc); 1463 /* Analog Sub = GPR[1] + GPR[2] */ 1464 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ALFE), A_C_00000000, 1465 A_GPR(1), A_GPR(2), &pc); 1466 1467 /* Digital Center = GPR[0] + GPR[2] */ 1468 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_CENTER), A_C_00000000, 1469 A_GPR(0), A_GPR(2), &pc); 1470 /* Digital Sub = GPR[1] + GPR[2] */ 1471 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_LFE), A_C_00000000, 1472 A_GPR(1), A_GPR(2), &pc); 1473 1474#if 0 1475 /* Analog Rear[l/r] = (GPR[0/1] * RearVolume[l/r]) >> 31 */ 1476 /* RearVolume = GPR[0x10/0x11] (Will this ever be implemented?) */ 1477 audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_AREAR_L), A_C_00000000, 1478 A_GPR(16), A_GPR(0), &pc); 1479 audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_AREAR_R), A_C_00000000, 1480 A_GPR(17), A_GPR(1), &pc); 1481 1482 /* Digital Rear[l/r] = (GPR[0/1] * RearVolume[l/r]) >> 31 */ 1483 /* RearVolume = GPR[0x10/0x11] (Will this ever be implemented?) */ 1484 audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_REAR_L), A_C_00000000, 1485 A_GPR(16), A_GPR(0), &pc); 1486 audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_REAR_R), A_C_00000000, 1487 A_GPR(17), A_GPR(1), &pc); 1488#else 1489 /* XXX This is just a copy to the channel, since we do not have 1490 * a patch manager, it is useful for have another output enabled. 1491 */ 1492 1493 /* Analog Rear[l/r] = GPR[0/1] */ 1494 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AREAR_L), A_C_00000000, 1495 A_C_00000000, A_GPR(0), &pc); 1496 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AREAR_R), A_C_00000000, 1497 A_C_00000000, A_GPR(1), &pc); 1498 1499 /* Digital Rear[l/r] = GPR[0/1] */ 1500 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_REAR_L), A_C_00000000, 1501 A_C_00000000, A_GPR(0), &pc); 1502 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_REAR_R), A_C_00000000, 1503 A_C_00000000, A_GPR(1), &pc); 1504#endif 1505 1506 /* ADC Recording buffer[l/r] = AC97Input[l/r] */ 1507 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ADC_CAP_L), A_C_00000000, 1508 A_C_00000000, A_EXTIN(A_EXTIN_AC97_L), &pc); 1509 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ADC_CAP_R), A_C_00000000, 1510 A_C_00000000, A_EXTIN(A_EXTIN_AC97_R), &pc); 1511 1512 /* resume normal operations */ 1513 emu_wrptr(sc, 0, A_DBG, 0); 1514} 1515 1516static void 1517emu_initefx(struct sc_info *sc) 1518{ 1519 int i; 1520 u_int32_t pc = 16; 1521 1522 /* acc3 0,0,0,0 - NOPs */ 1523 for (i = 0; i < 512; i++) { 1524 emu_wrefx(sc, i * 2, 0x10040); 1525 emu_wrefx(sc, i * 2 + 1, 0x610040); 1526 } 1527 1528 for (i = 0; i < 256; i++) 1529 emu_wrptr(sc, 0, FXGPREGBASE + i, 0); 1530 1531 /* FX-8010 DSP Registers: 1532 FX Bus 1533 0x000-0x00f : 16 registers 1534 Input 1535 0x010/0x011 : AC97 Codec (l/r) 1536 0x012/0x013 : ADC, S/PDIF (l/r) 1537 0x014/0x015 : Mic(left), Zoom (l/r) 1538 0x016/0x017 : TOS link in (l/r) 1539 0x018/0x019 : Line/Mic 1 (l/r) 1540 0x01a/0x01b : COAX S/PDIF (l/r) 1541 0x01c/0x01d : Line/Mic 2 (l/r) 1542 Output 1543 0x020/0x021 : AC97 Output (l/r) 1544 0x022/0x023 : TOS link out (l/r) 1545 0x024/0x025 : Center/LFE 1546 0x026/0x027 : LiveDrive Headphone (l/r) 1547 0x028/0x029 : Rear Channel (l/r) 1548 0x02a/0x02b : ADC Recording Buffer (l/r) 1549 0x02c : Mic Recording Buffer 1550 0x031/0x032 : Analog Center/LFE 1551 Constants 1552 0x040 - 0x044 = 0 - 4 1553 0x045 = 0x8, 0x046 = 0x10, 0x047 = 0x20 1554 0x048 = 0x100, 0x049 = 0x10000, 0x04a = 0x80000 1555 0x04b = 0x10000000, 0x04c = 0x20000000, 0x04d = 0x40000000 1556 0x04e = 0x80000000, 0x04f = 0x7fffffff, 0x050 = 0xffffffff 1557 0x051 = 0xfffffffe, 0x052 = 0xc0000000, 0x053 = 0x41fbbcdc 1558 0x054 = 0x5a7ef9db, 0x055 = 0x00100000 1559 Temporary Values 1560 0x056 : Accumulator 1561 0x057 : Condition Register 1562 0x058 : Noise source 1563 0x059 : Noise source 1564 0x05a : IRQ Register 1565 0x05b : TRAM Delay Base Address Count 1566 General Purpose Registers 1567 0x100 - 0x1ff 1568 Tank Memory Data Registers 1569 0x200 - 0x2ff 1570 Tank Memory Address Registers 1571 0x300 - 0x3ff 1572 */ 1573 1574 /* Routing - this will be configurable in later version */ 1575 1576 /* GPR[0/1] = FX * 4 + SPDIF-in */ 1577 emu_addefxop(sc, iMACINT0, GPR(0), EXTIN(EXTIN_SPDIF_CD_L), 1578 FXBUS(FXBUS_PCM_LEFT), C_00000004, &pc); 1579 emu_addefxop(sc, iMACINT0, GPR(1), EXTIN(EXTIN_SPDIF_CD_R), 1580 FXBUS(FXBUS_PCM_RIGHT), C_00000004, &pc); 1581 1582 /* GPR[0/1] += APS-input */ 1583 emu_addefxop(sc, iACC3, GPR(0), GPR(0), C_00000000, 1584 sc->APS ? EXTIN(EXTIN_TOSLINK_L) : C_00000000, &pc); 1585 emu_addefxop(sc, iACC3, GPR(1), GPR(1), C_00000000, 1586 sc->APS ? EXTIN(EXTIN_TOSLINK_R) : C_00000000, &pc); 1587 1588 /* FrontOut (AC97) = GPR[0/1] */ 1589 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_AC97_L), C_00000000, 1590 C_00000000, GPR(0), &pc); 1591 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_AC97_R), C_00000000, 1592 C_00000001, GPR(1), &pc); 1593 1594 /* GPR[2] = GPR[0] (Left) / 2 + GPR[1] (Right) / 2 -- Central volume */ 1595 emu_addefxop(sc, iINTERP, GPR(2), GPR(1), C_40000000, GPR(0), &pc); 1596 1597#if 0 1598 /* RearOut = (GPR[0/1] * RearVolume) >> 31 */ 1599 /* RearVolume = GPR[0x10/0x11] */ 1600 emu_addefxop(sc, iMAC0, EXTOUT(EXTOUT_REAR_L), C_00000000, 1601 GPR(16), GPR(0), &pc); 1602 emu_addefxop(sc, iMAC0, EXTOUT(EXTOUT_REAR_R), C_00000000, 1603 GPR(17), GPR(1), &pc); 1604#else 1605 /* XXX This is just a copy to the channel, since we do not have 1606 * a patch manager, it is useful for have another output enabled. 1607 */ 1608 1609 /* Rear[l/r] = GPR[0/1] */ 1610 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_REAR_L), C_00000000, 1611 C_00000000, GPR(0), &pc); 1612 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_REAR_R), C_00000000, 1613 C_00000000, GPR(1), &pc); 1614#endif 1615 1616 /* TOS out[l/r] = GPR[0/1] */ 1617 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_TOSLINK_L), C_00000000, 1618 C_00000000, GPR(0), &pc); 1619 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_TOSLINK_R), C_00000000, 1620 C_00000000, GPR(1), &pc); 1621 1622 /* Center and Subwoofer configuration */ 1623 /* Analog Center = GPR[0] + GPR[2] */ 1624 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ACENTER), C_00000000, 1625 GPR(0), GPR(2), &pc); 1626 /* Analog Sub = GPR[1] + GPR[2] */ 1627 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ALFE), C_00000000, 1628 GPR(1), GPR(2), &pc); 1629 /* Digital Center = GPR[0] + GPR[2] */ 1630 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_AC97_CENTER), C_00000000, 1631 GPR(0), GPR(2), &pc); 1632 /* Digital Sub = GPR[1] + GPR[2] */ 1633 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_AC97_LFE), C_00000000, 1634 GPR(1), GPR(2), &pc); 1635 1636 /* Headphones[l/r] = GPR[0/1] */ 1637 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_HEADPHONE_L), C_00000000, 1638 C_00000000, GPR(0), &pc); 1639 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_HEADPHONE_R), C_00000000, 1640 C_00000000, GPR(1), &pc); 1641 1642 /* ADC Recording buffer[l/r] = AC97Input[l/r] */ 1643 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ADC_CAP_L), C_00000000, 1644 C_00000000, EXTIN(EXTIN_AC97_L), &pc); 1645 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ADC_CAP_R), C_00000000, 1646 C_00000000, EXTIN(EXTIN_AC97_R), &pc); 1647 1648 /* resume normal operations */ 1649 emu_wrptr(sc, 0, DBG, 0); 1650} 1651 1652/* Probe and attach the card */ 1653static int 1654emu_init(struct sc_info *sc) 1655{ 1656 u_int32_t spcs, ch, tmp, i; 1657 1658 if (sc->audigy) { 1659 /* enable additional AC97 slots */ 1660 emu_wrptr(sc, 0, AC97SLOT, AC97SLOT_CNTR | AC97SLOT_LFE); 1661 } 1662 1663 /* disable audio and lock cache */ 1664 emu_wr(sc, HCFG, 1665 HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | HCFG_MUTEBUTTONENABLE, 1666 4); 1667 1668 /* reset recording buffers */ 1669 emu_wrptr(sc, 0, MICBS, ADCBS_BUFSIZE_NONE); 1670 emu_wrptr(sc, 0, MICBA, 0); 1671 emu_wrptr(sc, 0, FXBS, ADCBS_BUFSIZE_NONE); 1672 emu_wrptr(sc, 0, FXBA, 0); 1673 emu_wrptr(sc, 0, ADCBS, ADCBS_BUFSIZE_NONE); 1674 emu_wrptr(sc, 0, ADCBA, 0); 1675 1676 /* disable channel interrupt */ 1677 emu_wr(sc, INTE, 1678 INTE_INTERVALTIMERENB | INTE_SAMPLERATETRACKER | INTE_PCIERRORENABLE, 1679 4); 1680 emu_wrptr(sc, 0, CLIEL, 0); 1681 emu_wrptr(sc, 0, CLIEH, 0); 1682 emu_wrptr(sc, 0, SOLEL, 0); 1683 emu_wrptr(sc, 0, SOLEH, 0); 1684 1685 /* wonder what these do... */ 1686 if (sc->audigy) { 1687 emu_wrptr(sc, 0, SPBYPASS, 0xf00); 1688 emu_wrptr(sc, 0, AC97SLOT, 0x3); 1689 } 1690 1691 /* init envelope engine */ 1692 for (ch = 0; ch < NUM_G; ch++) { 1693 emu_wrptr(sc, ch, DCYSUSV, ENV_OFF); 1694 emu_wrptr(sc, ch, IP, 0); 1695 emu_wrptr(sc, ch, VTFT, 0xffff); 1696 emu_wrptr(sc, ch, CVCF, 0xffff); 1697 emu_wrptr(sc, ch, PTRX, 0); 1698 emu_wrptr(sc, ch, CPF, 0); 1699 emu_wrptr(sc, ch, CCR, 0); 1700 1701 emu_wrptr(sc, ch, PSST, 0); 1702 emu_wrptr(sc, ch, DSL, 0x10); 1703 emu_wrptr(sc, ch, CCCA, 0); 1704 emu_wrptr(sc, ch, Z1, 0); 1705 emu_wrptr(sc, ch, Z2, 0); 1706 emu_wrptr(sc, ch, FXRT, 0xd01c0000); 1707 1708 emu_wrptr(sc, ch, ATKHLDM, 0); 1709 emu_wrptr(sc, ch, DCYSUSM, 0); 1710 emu_wrptr(sc, ch, IFATN, 0xffff); 1711 emu_wrptr(sc, ch, PEFE, 0); 1712 emu_wrptr(sc, ch, FMMOD, 0); 1713 emu_wrptr(sc, ch, TREMFRQ, 24); /* 1 Hz */ 1714 emu_wrptr(sc, ch, FM2FRQ2, 24); /* 1 Hz */ 1715 emu_wrptr(sc, ch, TEMPENV, 0); 1716 1717 /*** these are last so OFF prevents writing ***/ 1718 emu_wrptr(sc, ch, LFOVAL2, 0); 1719 emu_wrptr(sc, ch, LFOVAL1, 0); 1720 emu_wrptr(sc, ch, ATKHLDV, 0); 1721 emu_wrptr(sc, ch, ENVVOL, 0); 1722 emu_wrptr(sc, ch, ENVVAL, 0); 1723 1724 if (sc->audigy) { 1725 /* audigy cards need this to initialize correctly */ 1726 emu_wrptr(sc, ch, 0x4c, 0); 1727 emu_wrptr(sc, ch, 0x4d, 0); 1728 emu_wrptr(sc, ch, 0x4e, 0); 1729 emu_wrptr(sc, ch, 0x4f, 0); 1730 /* set default routing */ 1731 emu_wrptr(sc, ch, A_FXRT1, 0x03020100); 1732 emu_wrptr(sc, ch, A_FXRT2, 0x3f3f3f3f); 1733 emu_wrptr(sc, ch, A_SENDAMOUNTS, 0); 1734 } 1735 1736 sc->voice[ch].vnum = ch; 1737 sc->voice[ch].slave = NULL; 1738 sc->voice[ch].busy = 0; 1739 sc->voice[ch].ismaster = 0; 1740 sc->voice[ch].running = 0; 1741 sc->voice[ch].b16 = 0; 1742 sc->voice[ch].stereo = 0; 1743 sc->voice[ch].speed = 0; 1744 sc->voice[ch].start = 0; 1745 sc->voice[ch].end = 0; 1746 sc->voice[ch].channel = NULL; 1747 } 1748 sc->pnum = sc->rnum = 0; 1749 1750 /* 1751 * Init to 0x02109204 : 1752 * Clock accuracy = 0 (1000ppm) 1753 * Sample Rate = 2 (48kHz) 1754 * Audio Channel = 1 (Left of 2) 1755 * Source Number = 0 (Unspecified) 1756 * Generation Status = 1 (Original for Cat Code 12) 1757 * Cat Code = 12 (Digital Signal Mixer) 1758 * Mode = 0 (Mode 0) 1759 * Emphasis = 0 (None) 1760 * CP = 1 (Copyright unasserted) 1761 * AN = 0 (Audio data) 1762 * P = 0 (Consumer) 1763 */ 1764 spcs = SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 | 1765 SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC | 1766 SPCS_GENERATIONSTATUS | 0x00001200 | 0x00000000 | 1767 SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT; 1768 emu_wrptr(sc, 0, SPCS0, spcs); 1769 emu_wrptr(sc, 0, SPCS1, spcs); 1770 emu_wrptr(sc, 0, SPCS2, spcs); 1771 1772 if (!sc->audigy) 1773 emu_initefx(sc); 1774 else if (sc->audigy2) { /* Audigy 2 */ 1775 /* from ALSA initialization code: */ 1776 1777 /* Hack for Alice3 to work independent of haP16V driver */ 1778 u_int32_t tmp; 1779 1780 /* Setup SRCMulti_I2S SamplingRate */ 1781 tmp = emu_rdptr(sc, 0, A_SPDIF_SAMPLERATE) & 0xfffff1ff; 1782 emu_wrptr(sc, 0, A_SPDIF_SAMPLERATE, tmp | 0x400); 1783 1784 /* Setup SRCSel (Enable SPDIF, I2S SRCMulti) */ 1785 emu_wr(sc, 0x20, 0x00600000, 4); 1786 emu_wr(sc, 0x24, 0x00000014, 4); 1787 1788 /* Setup SRCMulti Input Audio Enable */ 1789 emu_wr(sc, 0x20, 0x006e0000, 4); 1790 emu_wr(sc, 0x24, 0xff00ff00, 4); 1791 } 1792 1793 SLIST_INIT(&sc->mem.blocks); 1794 sc->mem.ptb_pages = emu_malloc(sc, EMUMAXPAGES * sizeof(u_int32_t), 1795 &sc->mem.ptb_pages_addr); 1796 if (sc->mem.ptb_pages == NULL) 1797 return -1; 1798 1799 sc->mem.silent_page = emu_malloc(sc, EMUPAGESIZE, 1800 &sc->mem.silent_page_addr); 1801 if (sc->mem.silent_page == NULL) { 1802 emu_free(sc, sc->mem.ptb_pages); 1803 return -1; 1804 } 1805 /* Clear page with silence & setup all pointers to this page */ 1806 bzero(sc->mem.silent_page, EMUPAGESIZE); 1807 tmp = (u_int32_t)(sc->mem.silent_page_addr) << 1; 1808 for (i = 0; i < EMUMAXPAGES; i++) 1809 sc->mem.ptb_pages[i] = tmp | i; 1810 1811 emu_wrptr(sc, 0, PTB, (sc->mem.ptb_pages_addr)); 1812 emu_wrptr(sc, 0, TCB, 0); /* taken from original driver */ 1813 emu_wrptr(sc, 0, TCBS, 0); /* taken from original driver */ 1814 1815 for (ch = 0; ch < NUM_G; ch++) { 1816 emu_wrptr(sc, ch, MAPA, tmp | MAP_PTI_MASK); 1817 emu_wrptr(sc, ch, MAPB, tmp | MAP_PTI_MASK); 1818 } 1819 1820 /* emu_memalloc(sc, EMUPAGESIZE); */ 1821 /* 1822 * Hokay, now enable the AUD bit 1823 * 1824 * Audigy 1825 * Enable Audio = 0 (enabled after fx processor initialization) 1826 * Mute Disable Audio = 0 1827 * Joystick = 1 1828 * 1829 * Audigy 2 1830 * Enable Audio = 1 1831 * Mute Disable Audio = 0 1832 * Joystick = 1 1833 * GP S/PDIF AC3 Enable = 1 1834 * CD S/PDIF AC3 Enable = 1 1835 * 1836 * EMU10K1 1837 * Enable Audio = 1 1838 * Mute Disable Audio = 0 1839 * Lock Tank Memory = 1 1840 * Lock Sound Memory = 0 1841 * Auto Mute = 1 1842 */ 1843 1844 if (sc->audigy) { 1845 tmp = HCFG_AUTOMUTE | HCFG_JOYENABLE; 1846 if (sc->audigy2) /* Audigy 2 */ 1847 tmp = HCFG_AUDIOENABLE | HCFG_AC3ENABLE_CDSPDIF | 1848 HCFG_AC3ENABLE_GPSPDIF; 1849 emu_wr(sc, HCFG, tmp, 4); 1850 1851 audigy_initefx(sc); 1852 1853 /* from ALSA initialization code: */ 1854 1855 /* enable audio and disable both audio/digital outputs */ 1856 emu_wr(sc, HCFG, emu_rd(sc, HCFG, 4) | HCFG_AUDIOENABLE, 4); 1857 emu_wr(sc, A_IOCFG, emu_rd(sc, A_IOCFG, 4) & ~A_IOCFG_GPOUT_AD, 1858 4); 1859 if (sc->audigy2) { /* Audigy 2 */ 1860 /* Unmute Analog. 1861 * Set GPO6 to 1 for Apollo. This has to be done after 1862 * init Alice3 I2SOut beyond 48kHz. 1863 * So, sequence is important. 1864 */ 1865 emu_wr(sc, A_IOCFG, 1866 emu_rd(sc, A_IOCFG, 4) | A_IOCFG_GPOUT_A, 4); 1867 } 1868 } else { 1869 /* EMU10K1 initialization code */ 1870 tmp = HCFG_AUDIOENABLE | HCFG_LOCKTANKCACHE_MASK 1871 | HCFG_AUTOMUTE; 1872 if (sc->rev >= 6) 1873 tmp |= HCFG_JOYENABLE; 1874 1875 emu_wr(sc, HCFG, tmp, 4); 1876 1877 /* TOSLink detection */ 1878 sc->tos_link = 0; 1879 tmp = emu_rd(sc, HCFG, 4); 1880 if (tmp & (HCFG_GPINPUT0 | HCFG_GPINPUT1)) { 1881 emu_wr(sc, HCFG, tmp | HCFG_GPOUT1, 4); 1882 DELAY(50); 1883 if (tmp != (emu_rd(sc, HCFG, 4) & ~HCFG_GPOUT1)) { 1884 sc->tos_link = 1; 1885 emu_wr(sc, HCFG, tmp, 4); 1886 } 1887 } 1888 } 1889 1890 return 0; 1891} 1892 1893static int 1894emu_uninit(struct sc_info *sc) 1895{ 1896 u_int32_t ch; 1897 1898 emu_wr(sc, INTE, 0, 4); 1899 for (ch = 0; ch < NUM_G; ch++) 1900 emu_wrptr(sc, ch, DCYSUSV, ENV_OFF); 1901 for (ch = 0; ch < NUM_G; ch++) { 1902 emu_wrptr(sc, ch, VTFT, 0); 1903 emu_wrptr(sc, ch, CVCF, 0); 1904 emu_wrptr(sc, ch, PTRX, 0); 1905 emu_wrptr(sc, ch, CPF, 0); 1906 } 1907 1908 if (sc->audigy) { /* stop fx processor */ 1909 emu_wrptr(sc, 0, A_DBG, A_DBG_SINGLE_STEP); 1910 } 1911 1912 /* disable audio and lock cache */ 1913 emu_wr(sc, HCFG, 1914 HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | HCFG_MUTEBUTTONENABLE, 1915 4); 1916 1917 emu_wrptr(sc, 0, PTB, 0); 1918 /* reset recording buffers */ 1919 emu_wrptr(sc, 0, MICBS, ADCBS_BUFSIZE_NONE); 1920 emu_wrptr(sc, 0, MICBA, 0); 1921 emu_wrptr(sc, 0, FXBS, ADCBS_BUFSIZE_NONE); 1922 emu_wrptr(sc, 0, FXBA, 0); 1923 emu_wrptr(sc, 0, FXWC, 0); 1924 emu_wrptr(sc, 0, ADCBS, ADCBS_BUFSIZE_NONE); 1925 emu_wrptr(sc, 0, ADCBA, 0); 1926 emu_wrptr(sc, 0, TCB, 0); 1927 emu_wrptr(sc, 0, TCBS, 0); 1928 1929 /* disable channel interrupt */ 1930 emu_wrptr(sc, 0, CLIEL, 0); 1931 emu_wrptr(sc, 0, CLIEH, 0); 1932 emu_wrptr(sc, 0, SOLEL, 0); 1933 emu_wrptr(sc, 0, SOLEH, 0); 1934 1935 /* init envelope engine */ 1936 if (!SLIST_EMPTY(&sc->mem.blocks)) 1937 device_printf(sc->dev, "warning: memblock list not empty\n"); 1938 emu_free(sc, sc->mem.ptb_pages); 1939 emu_free(sc, sc->mem.silent_page); 1940 1941 if(sc->mpu) 1942 mpu401_uninit(sc->mpu); 1943 return 0; 1944} 1945 1946static int 1947emu_pci_probe(device_t dev) 1948{ 1949 char *s = NULL; 1950 1951 switch (pci_get_devid(dev)) { 1952 case EMU10K1_PCI_ID: 1953 s = "Creative EMU10K1"; 1954 break; 1955 1956 case EMU10K2_PCI_ID: 1957 if (pci_get_revid(dev) == 0x04) 1958 s = "Creative Audigy 2 (EMU10K2)"; 1959 else 1960 s = "Creative Audigy (EMU10K2)"; 1961 break; 1962 1963 case EMU10K3_PCI_ID: 1964 s = "Creative Audigy 2 (EMU10K3)"; 1965 break; 1966 1967 default: 1968 return ENXIO; 1969 } 1970 1971 device_set_desc(dev, s); 1972 return BUS_PROBE_LOW_PRIORITY; 1973} 1974 1975static int 1976emu_pci_attach(device_t dev) 1977{ 1978 struct ac97_info *codec = NULL; 1979 struct sc_info *sc; 1980 u_int32_t data; 1981 int i, gotmic; 1982 char status[SND_STATUSLEN]; 1983 1984 if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) { 1985 device_printf(dev, "cannot allocate softc\n"); 1986 return ENXIO; 1987 } 1988 1989 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "snd_emu10k1 softc"); 1990 sc->dev = dev; 1991 sc->type = pci_get_devid(dev); 1992 sc->rev = pci_get_revid(dev); 1993 sc->audigy = sc->type == EMU10K2_PCI_ID || sc->type == EMU10K3_PCI_ID; 1994 sc->audigy2 = (sc->audigy && sc->rev == 0x04); 1995 sc->nchans = sc->audigy ? 8 : 4; 1996 sc->addrmask = sc->audigy ? A_PTR_ADDRESS_MASK : PTR_ADDRESS_MASK; 1997 1998 data = pci_read_config(dev, PCIR_COMMAND, 2); 1999 data |= (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN); 2000 pci_write_config(dev, PCIR_COMMAND, data, 2); 2001 data = pci_read_config(dev, PCIR_COMMAND, 2); 2002 2003 i = PCIR_BAR(0); 2004 sc->reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &i, RF_ACTIVE); 2005 if (sc->reg == NULL) { 2006 device_printf(dev, "unable to map register space\n"); 2007 goto bad; 2008 } 2009 sc->st = rman_get_bustag(sc->reg); 2010 sc->sh = rman_get_bushandle(sc->reg); 2011 2012 sc->bufsz = pcm_getbuffersize(dev, 4096, EMU_DEFAULT_BUFSZ, 65536); 2013 2014 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2, 2015 /*boundary*/0, 2016 /*lowaddr*/1 << 31, /* can only access 0-2gb */ 2017 /*highaddr*/BUS_SPACE_MAXADDR, 2018 /*filter*/NULL, /*filterarg*/NULL, 2019 /*maxsize*/sc->bufsz, /*nsegments*/1, /*maxsegz*/0x3ffff, 2020 /*flags*/0, /*lockfunc*/busdma_lock_mutex, 2021 /*lockarg*/&Giant, &sc->parent_dmat) != 0) { 2022 device_printf(dev, "unable to create dma tag\n"); 2023 goto bad; 2024 } 2025 2026 if (emu_init(sc) == -1) { 2027 device_printf(dev, "unable to initialize the card\n"); 2028 goto bad; 2029 } 2030 2031 codec = AC97_CREATE(dev, sc, emu_ac97); 2032 if (codec == NULL) goto bad; 2033 gotmic = (ac97_getcaps(codec) & AC97_CAP_MICCHANNEL) ? 1 : 0; 2034 if (mixer_init(dev, ac97_getmixerclass(), codec) == -1) goto bad; 2035 2036 emu_midiattach(sc); 2037 2038 i = 0; 2039 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, 2040 RF_ACTIVE | RF_SHAREABLE); 2041 if (!sc->irq || 2042 snd_setup_intr(dev, sc->irq, INTR_MPSAFE, emu_intr, sc, &sc->ih)) { 2043 device_printf(dev, "unable to map interrupt\n"); 2044 goto bad; 2045 } 2046 2047 snprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld %s", 2048 rman_get_start(sc->reg), rman_get_start(sc->irq), 2049 PCM_KLDSTRING(snd_emu10k1)); 2050 2051 if (pcm_register(dev, sc, sc->nchans, gotmic ? 3 : 2)) goto bad; 2052 for (i = 0; i < sc->nchans; i++) 2053 pcm_addchan(dev, PCMDIR_PLAY, &emupchan_class, sc); 2054 for (i = 0; i < (gotmic ? 3 : 2); i++) 2055 pcm_addchan(dev, PCMDIR_REC, &emurchan_class, sc); 2056 2057 pcm_setstatus(dev, status); 2058 2059 return 0; 2060 2061bad: 2062 if (codec) ac97_destroy(codec); 2063 if (sc->reg) bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), sc->reg); 2064 if (sc->ih) bus_teardown_intr(dev, sc->irq, sc->ih); 2065 if (sc->irq) bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 2066 if (sc->parent_dmat) bus_dma_tag_destroy(sc->parent_dmat); 2067 if (sc->lock) snd_mtxfree(sc->lock); 2068 free(sc, M_DEVBUF); 2069 return ENXIO; 2070} 2071 2072static int 2073emu_pci_detach(device_t dev) 2074{ 2075 int r; 2076 struct sc_info *sc; 2077 2078 r = pcm_unregister(dev); 2079 if (r) 2080 return r; 2081 2082 sc = pcm_getdevinfo(dev); 2083 /* shutdown chip */ 2084 emu_uninit(sc); 2085 2086 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), sc->reg); 2087 bus_teardown_intr(dev, sc->irq, sc->ih); 2088 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 2089 bus_dma_tag_destroy(sc->parent_dmat); 2090 snd_mtxfree(sc->lock); 2091 free(sc, M_DEVBUF); 2092 2093 return 0; 2094} 2095 2096/* add suspend, resume */ 2097static device_method_t emu_methods[] = { 2098 /* Device interface */ 2099 DEVMETHOD(device_probe, emu_pci_probe), 2100 DEVMETHOD(device_attach, emu_pci_attach), 2101 DEVMETHOD(device_detach, emu_pci_detach), 2102 2103 { 0, 0 } 2104}; 2105 2106static driver_t emu_driver = { 2107 "pcm", 2108 emu_methods, 2109 PCM_SOFTC_SIZE, 2110}; 2111 2112DRIVER_MODULE(snd_emu10k1, pci, emu_driver, pcm_devclass, 0, 0); 2113DRIVER_MODULE(snd_emu10k1, cardbus, emu_driver, pcm_devclass, 0, 0); 2114MODULE_DEPEND(snd_emu10k1, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 2115MODULE_VERSION(snd_emu10k1, 1); 2116MODULE_DEPEND(snd_emu10k1, midi, 1, 1, 1); 2117 2118/* dummy driver to silence the joystick device */ 2119static int 2120emujoy_pci_probe(device_t dev) 2121{ 2122 char *s = NULL; 2123 2124 switch (pci_get_devid(dev)) { 2125 case 0x70021102: 2126 s = "Creative EMU10K1 Joystick"; 2127 device_quiet(dev); 2128 break; 2129 case 0x70031102: 2130 s = "Creative EMU10K2 Joystick"; 2131 device_quiet(dev); 2132 break; 2133 } 2134 2135 if (s) device_set_desc(dev, s); 2136 return s ? -1000 : ENXIO; 2137} 2138 2139static int 2140emujoy_pci_attach(device_t dev) 2141{ 2142 return 0; 2143} 2144 2145static int 2146emujoy_pci_detach(device_t dev) 2147{ 2148 return 0; 2149} 2150 2151static device_method_t emujoy_methods[] = { 2152 DEVMETHOD(device_probe, emujoy_pci_probe), 2153 DEVMETHOD(device_attach, emujoy_pci_attach), 2154 DEVMETHOD(device_detach, emujoy_pci_detach), 2155 2156 { 0, 0 } 2157}; 2158 2159static driver_t emujoy_driver = { 2160 "emujoy", 2161 emujoy_methods, 2162 8, 2163}; 2164 2165static devclass_t emujoy_devclass; 2166 2167DRIVER_MODULE(emujoy, pci, emujoy_driver, emujoy_devclass, 0, 0); 2168 2169