csareg.h revision 54377
1/*- 2 * Copyright (c) 1999 Seigo Tanimura 3 * All rights reserved. 4 * 5 * Portions of this source are based on hwdefs.h in cwcealdr1.zip, the 6 * sample source by Crystal Semiconductor. 7 * Copyright (c) 1996-1998 Crystal Semiconductor Corp. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD: head/sys/dev/sound/pci/csareg.h 54377 1999-12-10 01:20:08Z tanimura $ 31 */ 32 33#ifndef _CSA_REG_H 34#define _CSA_REG_H 35 36/* This is the pci device id. */ 37#define CS4610_PCI_ID 0x60011013 38#define CS4614_PCI_ID 0x60031013 39#define CS4615_PCI_ID 0x60041013 40#define CS4281_PCI_ID 0x60051013 41 42/* And the offsets in pci configuration space. */ 43#define CS461x_IO_OFFSET 0x10 44#define CS461x_IO_SIZE (4 * 1024) 45#define CS461x_MEM_OFFSET 0x14 46#define CS461x_MEM_SIZE (1024 * 1024) 47 48/* Buffer size on dma transfer. Fixed for CS416x. */ 49#define CS461x_BUFFSIZE (4 * 1024) 50 51#define GOF_PER_SEC 200 52 53/* 54 * The following constats are orginally in the sample by Crystal Semiconductor. 55 * Copyright (c) 1996-1998 Crystal Semiconductor Corp. 56 */ 57 58/***************************************************************************** 59 * 60 * The following define the offsets of the registers accessed via base address 61 * register zero on the CS461x part. 62 * 63 *****************************************************************************/ 64#define BA0_HISR 0x00000000L 65#define BA0_HSR0 0x00000004L 66#define BA0_HICR 0x00000008L 67#define BA0_DMSR 0x00000100L 68#define BA0_HSAR 0x00000110L 69#define BA0_HDAR 0x00000114L 70#define BA0_HDMR 0x00000118L 71#define BA0_HDCR 0x0000011CL 72#define BA0_PFMC 0x00000200L 73#define BA0_PFCV1 0x00000204L 74#define BA0_PFCV2 0x00000208L 75#define BA0_PCICFG00 0x00000300L 76#define BA0_PCICFG04 0x00000304L 77#define BA0_PCICFG08 0x00000308L 78#define BA0_PCICFG0C 0x0000030CL 79#define BA0_PCICFG10 0x00000310L 80#define BA0_PCICFG14 0x00000314L 81#define BA0_PCICFG18 0x00000318L 82#define BA0_PCICFG1C 0x0000031CL 83#define BA0_PCICFG20 0x00000320L 84#define BA0_PCICFG24 0x00000324L 85#define BA0_PCICFG28 0x00000328L 86#define BA0_PCICFG2C 0x0000032CL 87#define BA0_PCICFG30 0x00000330L 88#define BA0_PCICFG34 0x00000334L 89#define BA0_PCICFG38 0x00000338L 90#define BA0_PCICFG3C 0x0000033CL 91#define BA0_CLKCR1 0x00000400L 92#define BA0_CLKCR2 0x00000404L 93#define BA0_PLLM 0x00000408L 94#define BA0_PLLCC 0x0000040CL 95#define BA0_FRR 0x00000410L 96#define BA0_CFL1 0x00000414L 97#define BA0_CFL2 0x00000418L 98#define BA0_SERMC1 0x00000420L 99#define BA0_SERMC2 0x00000424L 100#define BA0_SERC1 0x00000428L 101#define BA0_SERC2 0x0000042CL 102#define BA0_SERC3 0x00000430L 103#define BA0_SERC4 0x00000434L 104#define BA0_SERC5 0x00000438L 105#define BA0_SERBSP 0x0000043CL 106#define BA0_SERBST 0x00000440L 107#define BA0_SERBCM 0x00000444L 108#define BA0_SERBAD 0x00000448L 109#define BA0_SERBCF 0x0000044CL 110#define BA0_SERBWP 0x00000450L 111#define BA0_SERBRP 0x00000454L 112#ifndef NO_CS4612 113#define BA0_ASER_FADDR 0x00000458L 114#endif 115#define BA0_ACCTL 0x00000460L 116#define BA0_ACSTS 0x00000464L 117#define BA0_ACOSV 0x00000468L 118#define BA0_ACCAD 0x0000046CL 119#define BA0_ACCDA 0x00000470L 120#define BA0_ACISV 0x00000474L 121#define BA0_ACSAD 0x00000478L 122#define BA0_ACSDA 0x0000047CL 123#define BA0_JSPT 0x00000480L 124#define BA0_JSCTL 0x00000484L 125#define BA0_JSC1 0x00000488L 126#define BA0_JSC2 0x0000048CL 127#define BA0_MIDCR 0x00000490L 128#define BA0_MIDSR 0x00000494L 129#define BA0_MIDWP 0x00000498L 130#define BA0_MIDRP 0x0000049CL 131#define BA0_JSIO 0x000004A0L 132#ifndef NO_CS4612 133#define BA0_ASER_MASTER 0x000004A4L 134#endif 135#define BA0_CFGI 0x000004B0L 136#define BA0_SSVID 0x000004B4L 137#define BA0_GPIOR 0x000004B8L 138#ifndef NO_CS4612 139#define BA0_EGPIODR 0x000004BCL 140#define BA0_EGPIOPTR 0x000004C0L 141#define BA0_EGPIOTR 0x000004C4L 142#define BA0_EGPIOWR 0x000004C8L 143#define BA0_EGPIOSR 0x000004CCL 144#define BA0_SERC6 0x000004D0L 145#define BA0_SERC7 0x000004D4L 146#define BA0_SERACC 0x000004D8L 147#define BA0_ACCTL2 0x000004E0L 148#define BA0_ACSTS2 0x000004E4L 149#define BA0_ACOSV2 0x000004E8L 150#define BA0_ACCAD2 0x000004ECL 151#define BA0_ACCDA2 0x000004F0L 152#define BA0_ACISV2 0x000004F4L 153#define BA0_ACSAD2 0x000004F8L 154#define BA0_ACSDA2 0x000004FCL 155#define BA0_IOTAC0 0x00000500L 156#define BA0_IOTAC1 0x00000504L 157#define BA0_IOTAC2 0x00000508L 158#define BA0_IOTAC3 0x0000050CL 159#define BA0_IOTAC4 0x00000510L 160#define BA0_IOTAC5 0x00000514L 161#define BA0_IOTAC6 0x00000518L 162#define BA0_IOTAC7 0x0000051CL 163#define BA0_IOTAC8 0x00000520L 164#define BA0_IOTAC9 0x00000524L 165#define BA0_IOTAC10 0x00000528L 166#define BA0_IOTAC11 0x0000052CL 167#define BA0_IOTFR0 0x00000540L 168#define BA0_IOTFR1 0x00000544L 169#define BA0_IOTFR2 0x00000548L 170#define BA0_IOTFR3 0x0000054CL 171#define BA0_IOTFR4 0x00000550L 172#define BA0_IOTFR5 0x00000554L 173#define BA0_IOTFR6 0x00000558L 174#define BA0_IOTFR7 0x0000055CL 175#define BA0_IOTFIFO 0x00000580L 176#define BA0_IOTRRD 0x00000584L 177#define BA0_IOTFP 0x00000588L 178#define BA0_IOTCR 0x0000058CL 179#define BA0_DPCID 0x00000590L 180#define BA0_DPCIA 0x00000594L 181#define BA0_DPCIC 0x00000598L 182#define BA0_PCPCIR 0x00000600L 183#define BA0_PCPCIG 0x00000604L 184#define BA0_PCPCIEN 0x00000608L 185#define BA0_EPCIPMC 0x00000610L 186#endif 187 188/***************************************************************************** 189 * 190 * The following define the offsets of the AC97 shadow registers, which appear 191 * as a virtual extension to the base address register zero memory range. 192 * 193 *****************************************************************************/ 194#define BA0_AC97_RESET 0x00001000L 195#define BA0_AC97_MASTER_VOLUME 0x00001002L 196#define BA0_AC97_HEADPHONE_VOLUME 0x00001004L 197#define BA0_AC97_MASTER_VOLUME_MONO 0x00001006L 198#define BA0_AC97_MASTER_TONE 0x00001008L 199#define BA0_AC97_PC_BEEP_VOLUME 0x0000100AL 200#define BA0_AC97_PHONE_VOLUME 0x0000100CL 201#define BA0_AC97_MIC_VOLUME 0x0000100EL 202#define BA0_AC97_LINE_IN_VOLUME 0x00001010L 203#define BA0_AC97_CD_VOLUME 0x00001012L 204#define BA0_AC97_VIDEO_VOLUME 0x00001014L 205#define BA0_AC97_AUX_VOLUME 0x00001016L 206#define BA0_AC97_PCM_OUT_VOLUME 0x00001018L 207#define BA0_AC97_RECORD_SELECT 0x0000101AL 208#define BA0_AC97_RECORD_GAIN 0x0000101CL 209#define BA0_AC97_RECORD_GAIN_MIC 0x0000101EL 210#define BA0_AC97_GENERAL_PURPOSE 0x00001020L 211#define BA0_AC97_3D_CONTROL 0x00001022L 212#define BA0_AC97_MODEM_RATE 0x00001024L 213#define BA0_AC97_POWERDOWN 0x00001026L 214#define BA0_AC97_RESERVED_28 0x00001028L 215#define BA0_AC97_RESERVED_2A 0x0000102AL 216#define BA0_AC97_RESERVED_2C 0x0000102CL 217#define BA0_AC97_RESERVED_2E 0x0000102EL 218#define BA0_AC97_RESERVED_30 0x00001030L 219#define BA0_AC97_RESERVED_32 0x00001032L 220#define BA0_AC97_RESERVED_34 0x00001034L 221#define BA0_AC97_RESERVED_36 0x00001036L 222#define BA0_AC97_RESERVED_38 0x00001038L 223#define BA0_AC97_RESERVED_3A 0x0000103AL 224#define BA0_AC97_RESERVED_3C 0x0000103CL 225#define BA0_AC97_RESERVED_3E 0x0000103EL 226#define BA0_AC97_RESERVED_40 0x00001040L 227#define BA0_AC97_RESERVED_42 0x00001042L 228#define BA0_AC97_RESERVED_44 0x00001044L 229#define BA0_AC97_RESERVED_46 0x00001046L 230#define BA0_AC97_RESERVED_48 0x00001048L 231#define BA0_AC97_RESERVED_4A 0x0000104AL 232#define BA0_AC97_RESERVED_4C 0x0000104CL 233#define BA0_AC97_RESERVED_4E 0x0000104EL 234#define BA0_AC97_RESERVED_50 0x00001050L 235#define BA0_AC97_RESERVED_52 0x00001052L 236#define BA0_AC97_RESERVED_54 0x00001054L 237#define BA0_AC97_RESERVED_56 0x00001056L 238#define BA0_AC97_RESERVED_58 0x00001058L 239#define BA0_AC97_VENDOR_RESERVED_5A 0x0000105AL 240#define BA0_AC97_VENDOR_RESERVED_5C 0x0000105CL 241#define BA0_AC97_VENDOR_RESERVED_5E 0x0000105EL 242#define BA0_AC97_VENDOR_RESERVED_60 0x00001060L 243#define BA0_AC97_VENDOR_RESERVED_62 0x00001062L 244#define BA0_AC97_VENDOR_RESERVED_64 0x00001064L 245#define BA0_AC97_VENDOR_RESERVED_66 0x00001066L 246#define BA0_AC97_VENDOR_RESERVED_68 0x00001068L 247#define BA0_AC97_VENDOR_RESERVED_6A 0x0000106AL 248#define BA0_AC97_VENDOR_RESERVED_6C 0x0000106CL 249#define BA0_AC97_VENDOR_RESERVED_6E 0x0000106EL 250#define BA0_AC97_VENDOR_RESERVED_70 0x00001070L 251#define BA0_AC97_VENDOR_RESERVED_72 0x00001072L 252#define BA0_AC97_VENDOR_RESERVED_74 0x00001074L 253#define BA0_AC97_VENDOR_RESERVED_76 0x00001076L 254#define BA0_AC97_VENDOR_RESERVED_78 0x00001078L 255#define BA0_AC97_VENDOR_RESERVED_7A 0x0000107AL 256#define BA0_AC97_VENDOR_ID1 0x0000107CL 257#define BA0_AC97_VENDOR_ID2 0x0000107EL 258 259/***************************************************************************** 260 * 261 * The following define the offsets of the registers and memories accessed via 262 * base address register one on the CS461x part. 263 * 264 *****************************************************************************/ 265#define BA1_SP_DMEM0 0x00000000L 266#define BA1_SP_DMEM1 0x00010000L 267#define BA1_SP_PMEM 0x00020000L 268#define BA1_SPCR 0x00030000L 269#define BA1_DREG 0x00030004L 270#define BA1_DSRWP 0x00030008L 271#define BA1_TWPR 0x0003000CL 272#define BA1_SPWR 0x00030010L 273#define BA1_SPIR 0x00030014L 274#define BA1_FGR1 0x00030020L 275#define BA1_SPCS 0x00030028L 276#define BA1_SDSR 0x0003002CL 277#define BA1_FRMT 0x00030030L 278#define BA1_FRCC 0x00030034L 279#define BA1_FRSC 0x00030038L 280#define BA1_OMNI_MEM 0x000E0000L 281 282/***************************************************************************** 283 * 284 * The following defines are for the flags in the PCI interrupt register. 285 * 286 *****************************************************************************/ 287#define PI_LINE_MASK 0x000000FFL 288#define PI_PIN_MASK 0x0000FF00L 289#define PI_MIN_GRANT_MASK 0x00FF0000L 290#define PI_MAX_LATENCY_MASK 0xFF000000L 291#define PI_LINE_SHIFT 0L 292#define PI_PIN_SHIFT 8L 293#define PI_MIN_GRANT_SHIFT 16L 294#define PI_MAX_LATENCY_SHIFT 24L 295 296/***************************************************************************** 297 * 298 * The following defines are for the flags in the host interrupt status 299 * register. 300 * 301 *****************************************************************************/ 302#define HISR_VC_MASK 0x0000FFFFL 303#define HISR_VC0 0x00000001L 304#define HISR_VC1 0x00000002L 305#define HISR_VC2 0x00000004L 306#define HISR_VC3 0x00000008L 307#define HISR_VC4 0x00000010L 308#define HISR_VC5 0x00000020L 309#define HISR_VC6 0x00000040L 310#define HISR_VC7 0x00000080L 311#define HISR_VC8 0x00000100L 312#define HISR_VC9 0x00000200L 313#define HISR_VC10 0x00000400L 314#define HISR_VC11 0x00000800L 315#define HISR_VC12 0x00001000L 316#define HISR_VC13 0x00002000L 317#define HISR_VC14 0x00004000L 318#define HISR_VC15 0x00008000L 319#define HISR_INT0 0x00010000L 320#define HISR_INT1 0x00020000L 321#define HISR_DMAI 0x00040000L 322#define HISR_FROVR 0x00080000L 323#define HISR_MIDI 0x00100000L 324#ifdef NO_CS4612 325#define HISR_RESERVED 0x0FE00000L 326#else 327#define HISR_SBINT 0x00200000L 328#define HISR_RESERVED 0x0FC00000L 329#endif 330#define HISR_H0P 0x40000000L 331#define HISR_INTENA 0x80000000L 332 333/***************************************************************************** 334 * 335 * The following defines are for the flags in the host signal register 0. 336 * 337 *****************************************************************************/ 338#define HSR0_VC_MASK 0xFFFFFFFFL 339#define HSR0_VC16 0x00000001L 340#define HSR0_VC17 0x00000002L 341#define HSR0_VC18 0x00000004L 342#define HSR0_VC19 0x00000008L 343#define HSR0_VC20 0x00000010L 344#define HSR0_VC21 0x00000020L 345#define HSR0_VC22 0x00000040L 346#define HSR0_VC23 0x00000080L 347#define HSR0_VC24 0x00000100L 348#define HSR0_VC25 0x00000200L 349#define HSR0_VC26 0x00000400L 350#define HSR0_VC27 0x00000800L 351#define HSR0_VC28 0x00001000L 352#define HSR0_VC29 0x00002000L 353#define HSR0_VC30 0x00004000L 354#define HSR0_VC31 0x00008000L 355#define HSR0_VC32 0x00010000L 356#define HSR0_VC33 0x00020000L 357#define HSR0_VC34 0x00040000L 358#define HSR0_VC35 0x00080000L 359#define HSR0_VC36 0x00100000L 360#define HSR0_VC37 0x00200000L 361#define HSR0_VC38 0x00400000L 362#define HSR0_VC39 0x00800000L 363#define HSR0_VC40 0x01000000L 364#define HSR0_VC41 0x02000000L 365#define HSR0_VC42 0x04000000L 366#define HSR0_VC43 0x08000000L 367#define HSR0_VC44 0x10000000L 368#define HSR0_VC45 0x20000000L 369#define HSR0_VC46 0x40000000L 370#define HSR0_VC47 0x80000000L 371 372/***************************************************************************** 373 * 374 * The following defines are for the flags in the host interrupt control 375 * register. 376 * 377 *****************************************************************************/ 378#define HICR_IEV 0x00000001L 379#define HICR_CHGM 0x00000002L 380 381/***************************************************************************** 382 * 383 * The following defines are for the flags in the DMA status register. 384 * 385 *****************************************************************************/ 386#define DMSR_HP 0x00000001L 387#define DMSR_HR 0x00000002L 388#define DMSR_SP 0x00000004L 389#define DMSR_SR 0x00000008L 390 391/***************************************************************************** 392 * 393 * The following defines are for the flags in the host DMA source address 394 * register. 395 * 396 *****************************************************************************/ 397#define HSAR_HOST_ADDR_MASK 0xFFFFFFFFL 398#define HSAR_DSP_ADDR_MASK 0x0000FFFFL 399#define HSAR_MEMID_MASK 0x000F0000L 400#define HSAR_MEMID_SP_DMEM0 0x00000000L 401#define HSAR_MEMID_SP_DMEM1 0x00010000L 402#define HSAR_MEMID_SP_PMEM 0x00020000L 403#define HSAR_MEMID_SP_DEBUG 0x00030000L 404#define HSAR_MEMID_OMNI_MEM 0x000E0000L 405#define HSAR_END 0x40000000L 406#define HSAR_ERR 0x80000000L 407 408/***************************************************************************** 409 * 410 * The following defines are for the flags in the host DMA destination address 411 * register. 412 * 413 *****************************************************************************/ 414#define HDAR_HOST_ADDR_MASK 0xFFFFFFFFL 415#define HDAR_DSP_ADDR_MASK 0x0000FFFFL 416#define HDAR_MEMID_MASK 0x000F0000L 417#define HDAR_MEMID_SP_DMEM0 0x00000000L 418#define HDAR_MEMID_SP_DMEM1 0x00010000L 419#define HDAR_MEMID_SP_PMEM 0x00020000L 420#define HDAR_MEMID_SP_DEBUG 0x00030000L 421#define HDAR_MEMID_OMNI_MEM 0x000E0000L 422#define HDAR_END 0x40000000L 423#define HDAR_ERR 0x80000000L 424 425/***************************************************************************** 426 * 427 * The following defines are for the flags in the host DMA control register. 428 * 429 *****************************************************************************/ 430#define HDMR_AC_MASK 0x0000F000L 431#define HDMR_AC_8_16 0x00001000L 432#define HDMR_AC_M_S 0x00002000L 433#define HDMR_AC_B_L 0x00004000L 434#define HDMR_AC_S_U 0x00008000L 435 436/***************************************************************************** 437 * 438 * The following defines are for the flags in the host DMA control register. 439 * 440 *****************************************************************************/ 441#define HDCR_COUNT_MASK 0x000003FFL 442#define HDCR_DONE 0x00004000L 443#define HDCR_OPT 0x00008000L 444#define HDCR_WBD 0x00400000L 445#define HDCR_WBS 0x00800000L 446#define HDCR_DMS_MASK 0x07000000L 447#define HDCR_DMS_LINEAR 0x00000000L 448#define HDCR_DMS_16_DWORDS 0x01000000L 449#define HDCR_DMS_32_DWORDS 0x02000000L 450#define HDCR_DMS_64_DWORDS 0x03000000L 451#define HDCR_DMS_128_DWORDS 0x04000000L 452#define HDCR_DMS_256_DWORDS 0x05000000L 453#define HDCR_DMS_512_DWORDS 0x06000000L 454#define HDCR_DMS_1024_DWORDS 0x07000000L 455#define HDCR_DH 0x08000000L 456#define HDCR_SMS_MASK 0x70000000L 457#define HDCR_SMS_LINEAR 0x00000000L 458#define HDCR_SMS_16_DWORDS 0x10000000L 459#define HDCR_SMS_32_DWORDS 0x20000000L 460#define HDCR_SMS_64_DWORDS 0x30000000L 461#define HDCR_SMS_128_DWORDS 0x40000000L 462#define HDCR_SMS_256_DWORDS 0x50000000L 463#define HDCR_SMS_512_DWORDS 0x60000000L 464#define HDCR_SMS_1024_DWORDS 0x70000000L 465#define HDCR_SH 0x80000000L 466#define HDCR_COUNT_SHIFT 0L 467 468/***************************************************************************** 469 * 470 * The following defines are for the flags in the performance monitor control 471 * register. 472 * 473 *****************************************************************************/ 474#define PFMC_C1SS_MASK 0x0000001FL 475#define PFMC_C1EV 0x00000020L 476#define PFMC_C1RS 0x00008000L 477#define PFMC_C2SS_MASK 0x001F0000L 478#define PFMC_C2EV 0x00200000L 479#define PFMC_C2RS 0x80000000L 480#define PFMC_C1SS_SHIFT 0L 481#define PFMC_C2SS_SHIFT 16L 482#define PFMC_BUS_GRANT 0L 483#define PFMC_GRANT_AFTER_REQ 1L 484#define PFMC_TRANSACTION 2L 485#define PFMC_DWORD_TRANSFER 3L 486#define PFMC_SLAVE_READ 4L 487#define PFMC_SLAVE_WRITE 5L 488#define PFMC_PREEMPTION 6L 489#define PFMC_DISCONNECT_RETRY 7L 490#define PFMC_INTERRUPT 8L 491#define PFMC_BUS_OWNERSHIP 9L 492#define PFMC_TRANSACTION_LAG 10L 493#define PFMC_PCI_CLOCK 11L 494#define PFMC_SERIAL_CLOCK 12L 495#define PFMC_SP_CLOCK 13L 496 497/***************************************************************************** 498 * 499 * The following defines are for the flags in the performance counter value 1 500 * register. 501 * 502 *****************************************************************************/ 503#define PFCV1_PC1V_MASK 0xFFFFFFFFL 504#define PFCV1_PC1V_SHIFT 0L 505 506/***************************************************************************** 507 * 508 * The following defines are for the flags in the performance counter value 2 509 * register. 510 * 511 *****************************************************************************/ 512#define PFCV2_PC2V_MASK 0xFFFFFFFFL 513#define PFCV2_PC2V_SHIFT 0L 514 515/***************************************************************************** 516 * 517 * The following defines are for the flags in the clock control register 1. 518 * 519 *****************************************************************************/ 520#define CLKCR1_OSCS 0x00000001L 521#define CLKCR1_OSCP 0x00000002L 522#define CLKCR1_PLLSS_MASK 0x0000000CL 523#define CLKCR1_PLLSS_SERIAL 0x00000000L 524#define CLKCR1_PLLSS_CRYSTAL 0x00000004L 525#define CLKCR1_PLLSS_PCI 0x00000008L 526#define CLKCR1_PLLSS_RESERVED 0x0000000CL 527#define CLKCR1_PLLP 0x00000010L 528#define CLKCR1_SWCE 0x00000020L 529#define CLKCR1_PLLOS 0x00000040L 530 531/***************************************************************************** 532 * 533 * The following defines are for the flags in the clock control register 2. 534 * 535 *****************************************************************************/ 536#define CLKCR2_PDIVS_MASK 0x0000000FL 537#define CLKCR2_PDIVS_1 0x00000001L 538#define CLKCR2_PDIVS_2 0x00000002L 539#define CLKCR2_PDIVS_4 0x00000004L 540#define CLKCR2_PDIVS_7 0x00000007L 541#define CLKCR2_PDIVS_8 0x00000008L 542#define CLKCR2_PDIVS_16 0x00000000L 543 544/***************************************************************************** 545 * 546 * The following defines are for the flags in the PLL multiplier register. 547 * 548 *****************************************************************************/ 549#define PLLM_MASK 0x000000FFL 550#define PLLM_SHIFT 0L 551 552/***************************************************************************** 553 * 554 * The following defines are for the flags in the PLL capacitor coefficient 555 * register. 556 * 557 *****************************************************************************/ 558#define PLLCC_CDR_MASK 0x00000007L 559#ifndef NO_CS4610 560#define PLLCC_CDR_240_350_MHZ 0x00000000L 561#define PLLCC_CDR_184_265_MHZ 0x00000001L 562#define PLLCC_CDR_144_205_MHZ 0x00000002L 563#define PLLCC_CDR_111_160_MHZ 0x00000003L 564#define PLLCC_CDR_87_123_MHZ 0x00000004L 565#define PLLCC_CDR_67_96_MHZ 0x00000005L 566#define PLLCC_CDR_52_74_MHZ 0x00000006L 567#define PLLCC_CDR_45_58_MHZ 0x00000007L 568#endif 569#ifndef NO_CS4612 570#define PLLCC_CDR_271_398_MHZ 0x00000000L 571#define PLLCC_CDR_227_330_MHZ 0x00000001L 572#define PLLCC_CDR_167_239_MHZ 0x00000002L 573#define PLLCC_CDR_150_215_MHZ 0x00000003L 574#define PLLCC_CDR_107_154_MHZ 0x00000004L 575#define PLLCC_CDR_98_140_MHZ 0x00000005L 576#define PLLCC_CDR_73_104_MHZ 0x00000006L 577#define PLLCC_CDR_63_90_MHZ 0x00000007L 578#endif 579#define PLLCC_LPF_MASK 0x000000F8L 580#ifndef NO_CS4610 581#define PLLCC_LPF_23850_60000_KHZ 0x00000000L 582#define PLLCC_LPF_7960_26290_KHZ 0x00000008L 583#define PLLCC_LPF_4160_10980_KHZ 0x00000018L 584#define PLLCC_LPF_1740_4580_KHZ 0x00000038L 585#define PLLCC_LPF_724_1910_KHZ 0x00000078L 586#define PLLCC_LPF_317_798_KHZ 0x000000F8L 587#endif 588#ifndef NO_CS4612 589#define PLLCC_LPF_25580_64530_KHZ 0x00000000L 590#define PLLCC_LPF_14360_37270_KHZ 0x00000008L 591#define PLLCC_LPF_6100_16020_KHZ 0x00000018L 592#define PLLCC_LPF_2540_6690_KHZ 0x00000038L 593#define PLLCC_LPF_1050_2780_KHZ 0x00000078L 594#define PLLCC_LPF_450_1160_KHZ 0x000000F8L 595#endif 596 597/***************************************************************************** 598 * 599 * The following defines are for the flags in the feature reporting register. 600 * 601 *****************************************************************************/ 602#define FRR_FAB_MASK 0x00000003L 603#define FRR_MASK_MASK 0x0000001CL 604#ifdef NO_CS4612 605#define FRR_CFOP_MASK 0x000000E0L 606#else 607#define FRR_CFOP_MASK 0x00000FE0L 608#endif 609#define FRR_CFOP_NOT_DVD 0x00000020L 610#define FRR_CFOP_A3D 0x00000040L 611#define FRR_CFOP_128_PIN 0x00000080L 612#ifndef NO_CS4612 613#define FRR_CFOP_CS4280 0x00000800L 614#endif 615#define FRR_FAB_SHIFT 0L 616#define FRR_MASK_SHIFT 2L 617#define FRR_CFOP_SHIFT 5L 618 619/***************************************************************************** 620 * 621 * The following defines are for the flags in the configuration load 1 622 * register. 623 * 624 *****************************************************************************/ 625#define CFL1_CLOCK_SOURCE_MASK 0x00000003L 626#define CFL1_CLOCK_SOURCE_CS423X 0x00000000L 627#define CFL1_CLOCK_SOURCE_AC97 0x00000001L 628#define CFL1_CLOCK_SOURCE_CRYSTAL 0x00000002L 629#define CFL1_CLOCK_SOURCE_DUAL_AC97 0x00000003L 630#define CFL1_VALID_DATA_MASK 0x000000FFL 631 632/***************************************************************************** 633 * 634 * The following defines are for the flags in the configuration load 2 635 * register. 636 * 637 *****************************************************************************/ 638#define CFL2_VALID_DATA_MASK 0x000000FFL 639 640/***************************************************************************** 641 * 642 * The following defines are for the flags in the serial port master control 643 * register 1. 644 * 645 *****************************************************************************/ 646#define SERMC1_MSPE 0x00000001L 647#define SERMC1_PTC_MASK 0x0000000EL 648#define SERMC1_PTC_CS423X 0x00000000L 649#define SERMC1_PTC_AC97 0x00000002L 650#define SERMC1_PTC_DAC 0x00000004L 651#define SERMC1_PLB 0x00000010L 652#define SERMC1_XLB 0x00000020L 653 654/***************************************************************************** 655 * 656 * The following defines are for the flags in the serial port master control 657 * register 2. 658 * 659 *****************************************************************************/ 660#define SERMC2_LROE 0x00000001L 661#define SERMC2_MCOE 0x00000002L 662#define SERMC2_MCDIV 0x00000004L 663 664/***************************************************************************** 665 * 666 * The following defines are for the flags in the serial port 1 configuration 667 * register. 668 * 669 *****************************************************************************/ 670#define SERC1_SO1EN 0x00000001L 671#define SERC1_SO1F_MASK 0x0000000EL 672#define SERC1_SO1F_CS423X 0x00000000L 673#define SERC1_SO1F_AC97 0x00000002L 674#define SERC1_SO1F_DAC 0x00000004L 675#define SERC1_SO1F_SPDIF 0x00000006L 676 677/***************************************************************************** 678 * 679 * The following defines are for the flags in the serial port 2 configuration 680 * register. 681 * 682 *****************************************************************************/ 683#define SERC2_SI1EN 0x00000001L 684#define SERC2_SI1F_MASK 0x0000000EL 685#define SERC2_SI1F_CS423X 0x00000000L 686#define SERC2_SI1F_AC97 0x00000002L 687#define SERC2_SI1F_ADC 0x00000004L 688#define SERC2_SI1F_SPDIF 0x00000006L 689 690/***************************************************************************** 691 * 692 * The following defines are for the flags in the serial port 3 configuration 693 * register. 694 * 695 *****************************************************************************/ 696#define SERC3_SO2EN 0x00000001L 697#define SERC3_SO2F_MASK 0x00000006L 698#define SERC3_SO2F_DAC 0x00000000L 699#define SERC3_SO2F_SPDIF 0x00000002L 700 701/***************************************************************************** 702 * 703 * The following defines are for the flags in the serial port 4 configuration 704 * register. 705 * 706 *****************************************************************************/ 707#define SERC4_SO3EN 0x00000001L 708#define SERC4_SO3F_MASK 0x00000006L 709#define SERC4_SO3F_DAC 0x00000000L 710#define SERC4_SO3F_SPDIF 0x00000002L 711 712/***************************************************************************** 713 * 714 * The following defines are for the flags in the serial port 5 configuration 715 * register. 716 * 717 *****************************************************************************/ 718#define SERC5_SI2EN 0x00000001L 719#define SERC5_SI2F_MASK 0x00000006L 720#define SERC5_SI2F_ADC 0x00000000L 721#define SERC5_SI2F_SPDIF 0x00000002L 722 723/***************************************************************************** 724 * 725 * The following defines are for the flags in the serial port backdoor sample 726 * pointer register. 727 * 728 *****************************************************************************/ 729#define SERBSP_FSP_MASK 0x0000000FL 730#define SERBSP_FSP_SHIFT 0L 731 732/***************************************************************************** 733 * 734 * The following defines are for the flags in the serial port backdoor status 735 * register. 736 * 737 *****************************************************************************/ 738#define SERBST_RRDY 0x00000001L 739#define SERBST_WBSY 0x00000002L 740 741/***************************************************************************** 742 * 743 * The following defines are for the flags in the serial port backdoor command 744 * register. 745 * 746 *****************************************************************************/ 747#define SERBCM_RDC 0x00000001L 748#define SERBCM_WRC 0x00000002L 749 750/***************************************************************************** 751 * 752 * The following defines are for the flags in the serial port backdoor address 753 * register. 754 * 755 *****************************************************************************/ 756#ifdef NO_CS4612 757#define SERBAD_FAD_MASK 0x000000FFL 758#else 759#define SERBAD_FAD_MASK 0x000001FFL 760#endif 761#define SERBAD_FAD_SHIFT 0L 762 763/***************************************************************************** 764 * 765 * The following defines are for the flags in the serial port backdoor 766 * configuration register. 767 * 768 *****************************************************************************/ 769#define SERBCF_HBP 0x00000001L 770 771/***************************************************************************** 772 * 773 * The following defines are for the flags in the serial port backdoor write 774 * port register. 775 * 776 *****************************************************************************/ 777#define SERBWP_FWD_MASK 0x000FFFFFL 778#define SERBWP_FWD_SHIFT 0L 779 780/***************************************************************************** 781 * 782 * The following defines are for the flags in the serial port backdoor read 783 * port register. 784 * 785 *****************************************************************************/ 786#define SERBRP_FRD_MASK 0x000FFFFFL 787#define SERBRP_FRD_SHIFT 0L 788 789/***************************************************************************** 790 * 791 * The following defines are for the flags in the async FIFO address register. 792 * 793 *****************************************************************************/ 794#ifndef NO_CS4612 795#define ASER_FADDR_A1_MASK 0x000001FFL 796#define ASER_FADDR_EN1 0x00008000L 797#define ASER_FADDR_A2_MASK 0x01FF0000L 798#define ASER_FADDR_EN2 0x80000000L 799#define ASER_FADDR_A1_SHIFT 0L 800#define ASER_FADDR_A2_SHIFT 16L 801#endif 802 803/***************************************************************************** 804 * 805 * The following defines are for the flags in the AC97 control register. 806 * 807 *****************************************************************************/ 808#define ACCTL_RSTN 0x00000001L 809#define ACCTL_ESYN 0x00000002L 810#define ACCTL_VFRM 0x00000004L 811#define ACCTL_DCV 0x00000008L 812#define ACCTL_CRW 0x00000010L 813#define ACCTL_ASYN 0x00000020L 814#ifndef NO_CS4612 815#define ACCTL_TC 0x00000040L 816#endif 817 818/***************************************************************************** 819 * 820 * The following defines are for the flags in the AC97 status register. 821 * 822 *****************************************************************************/ 823#define ACSTS_CRDY 0x00000001L 824#define ACSTS_VSTS 0x00000002L 825#ifndef NO_CS4612 826#define ACSTS_WKUP 0x00000004L 827#endif 828 829/***************************************************************************** 830 * 831 * The following defines are for the flags in the AC97 output slot valid 832 * register. 833 * 834 *****************************************************************************/ 835#define ACOSV_SLV3 0x00000001L 836#define ACOSV_SLV4 0x00000002L 837#define ACOSV_SLV5 0x00000004L 838#define ACOSV_SLV6 0x00000008L 839#define ACOSV_SLV7 0x00000010L 840#define ACOSV_SLV8 0x00000020L 841#define ACOSV_SLV9 0x00000040L 842#define ACOSV_SLV10 0x00000080L 843#define ACOSV_SLV11 0x00000100L 844#define ACOSV_SLV12 0x00000200L 845 846/***************************************************************************** 847 * 848 * The following defines are for the flags in the AC97 command address 849 * register. 850 * 851 *****************************************************************************/ 852#define ACCAD_CI_MASK 0x0000007FL 853#define ACCAD_CI_SHIFT 0L 854 855/***************************************************************************** 856 * 857 * The following defines are for the flags in the AC97 command data register. 858 * 859 *****************************************************************************/ 860#define ACCDA_CD_MASK 0x0000FFFFL 861#define ACCDA_CD_SHIFT 0L 862 863/***************************************************************************** 864 * 865 * The following defines are for the flags in the AC97 input slot valid 866 * register. 867 * 868 *****************************************************************************/ 869#define ACISV_ISV3 0x00000001L 870#define ACISV_ISV4 0x00000002L 871#define ACISV_ISV5 0x00000004L 872#define ACISV_ISV6 0x00000008L 873#define ACISV_ISV7 0x00000010L 874#define ACISV_ISV8 0x00000020L 875#define ACISV_ISV9 0x00000040L 876#define ACISV_ISV10 0x00000080L 877#define ACISV_ISV11 0x00000100L 878#define ACISV_ISV12 0x00000200L 879 880/***************************************************************************** 881 * 882 * The following defines are for the flags in the AC97 status address 883 * register. 884 * 885 *****************************************************************************/ 886#define ACSAD_SI_MASK 0x0000007FL 887#define ACSAD_SI_SHIFT 0L 888 889/***************************************************************************** 890 * 891 * The following defines are for the flags in the AC97 status data register. 892 * 893 *****************************************************************************/ 894#define ACSDA_SD_MASK 0x0000FFFFL 895#define ACSDA_SD_SHIFT 0L 896 897/***************************************************************************** 898 * 899 * The following defines are for the flags in the joystick poll/trigger 900 * register. 901 * 902 *****************************************************************************/ 903#define JSPT_CAX 0x00000001L 904#define JSPT_CAY 0x00000002L 905#define JSPT_CBX 0x00000004L 906#define JSPT_CBY 0x00000008L 907#define JSPT_BA1 0x00000010L 908#define JSPT_BA2 0x00000020L 909#define JSPT_BB1 0x00000040L 910#define JSPT_BB2 0x00000080L 911 912/***************************************************************************** 913 * 914 * The following defines are for the flags in the joystick control register. 915 * 916 *****************************************************************************/ 917#define JSCTL_SP_MASK 0x00000003L 918#define JSCTL_SP_SLOW 0x00000000L 919#define JSCTL_SP_MEDIUM_SLOW 0x00000001L 920#define JSCTL_SP_MEDIUM_FAST 0x00000002L 921#define JSCTL_SP_FAST 0x00000003L 922#define JSCTL_ARE 0x00000004L 923 924/***************************************************************************** 925 * 926 * The following defines are for the flags in the joystick coordinate pair 1 927 * readback register. 928 * 929 *****************************************************************************/ 930#define JSC1_Y1V_MASK 0x0000FFFFL 931#define JSC1_X1V_MASK 0xFFFF0000L 932#define JSC1_Y1V_SHIFT 0L 933#define JSC1_X1V_SHIFT 16L 934 935/***************************************************************************** 936 * 937 * The following defines are for the flags in the joystick coordinate pair 2 938 * readback register. 939 * 940 *****************************************************************************/ 941#define JSC2_Y2V_MASK 0x0000FFFFL 942#define JSC2_X2V_MASK 0xFFFF0000L 943#define JSC2_Y2V_SHIFT 0L 944#define JSC2_X2V_SHIFT 16L 945 946/***************************************************************************** 947 * 948 * The following defines are for the flags in the MIDI control register. 949 * 950 *****************************************************************************/ 951#define MIDCR_TXE 0x00000001L 952#define MIDCR_RXE 0x00000002L 953#define MIDCR_RIE 0x00000004L 954#define MIDCR_TIE 0x00000008L 955#define MIDCR_MLB 0x00000010L 956#define MIDCR_MRST 0x00000020L 957 958/***************************************************************************** 959 * 960 * The following defines are for the flags in the MIDI status register. 961 * 962 *****************************************************************************/ 963#define MIDSR_TBF 0x00000001L 964#define MIDSR_RBE 0x00000002L 965 966/***************************************************************************** 967 * 968 * The following defines are for the flags in the MIDI write port register. 969 * 970 *****************************************************************************/ 971#define MIDWP_MWD_MASK 0x000000FFL 972#define MIDWP_MWD_SHIFT 0L 973 974/***************************************************************************** 975 * 976 * The following defines are for the flags in the MIDI read port register. 977 * 978 *****************************************************************************/ 979#define MIDRP_MRD_MASK 0x000000FFL 980#define MIDRP_MRD_SHIFT 0L 981 982/***************************************************************************** 983 * 984 * The following defines are for the flags in the joystick GPIO register. 985 * 986 *****************************************************************************/ 987#define JSIO_DAX 0x00000001L 988#define JSIO_DAY 0x00000002L 989#define JSIO_DBX 0x00000004L 990#define JSIO_DBY 0x00000008L 991#define JSIO_AXOE 0x00000010L 992#define JSIO_AYOE 0x00000020L 993#define JSIO_BXOE 0x00000040L 994#define JSIO_BYOE 0x00000080L 995 996/***************************************************************************** 997 * 998 * The following defines are for the flags in the master async/sync serial 999 * port enable register. 1000 * 1001 *****************************************************************************/ 1002#ifndef NO_CS4612 1003#define ASER_MASTER_ME 0x00000001L 1004#endif 1005 1006/***************************************************************************** 1007 * 1008 * The following defines are for the flags in the configuration interface 1009 * register. 1010 * 1011 *****************************************************************************/ 1012#define CFGI_CLK 0x00000001L 1013#define CFGI_DOUT 0x00000002L 1014#define CFGI_DIN_EEN 0x00000004L 1015#define CFGI_EELD 0x00000008L 1016 1017/***************************************************************************** 1018 * 1019 * The following defines are for the flags in the subsystem ID and vendor ID 1020 * register. 1021 * 1022 *****************************************************************************/ 1023#define SSVID_VID_MASK 0x0000FFFFL 1024#define SSVID_SID_MASK 0xFFFF0000L 1025#define SSVID_VID_SHIFT 0L 1026#define SSVID_SID_SHIFT 16L 1027 1028/***************************************************************************** 1029 * 1030 * The following defines are for the flags in the GPIO pin interface register. 1031 * 1032 *****************************************************************************/ 1033#define GPIOR_VOLDN 0x00000001L 1034#define GPIOR_VOLUP 0x00000002L 1035#define GPIOR_SI2D 0x00000004L 1036#define GPIOR_SI2OE 0x00000008L 1037 1038/***************************************************************************** 1039 * 1040 * The following defines are for the flags in the extended GPIO pin direction 1041 * register. 1042 * 1043 *****************************************************************************/ 1044#ifndef NO_CS4612 1045#define EGPIODR_GPOE0 0x00000001L 1046#define EGPIODR_GPOE1 0x00000002L 1047#define EGPIODR_GPOE2 0x00000004L 1048#define EGPIODR_GPOE3 0x00000008L 1049#define EGPIODR_GPOE4 0x00000010L 1050#define EGPIODR_GPOE5 0x00000020L 1051#define EGPIODR_GPOE6 0x00000040L 1052#define EGPIODR_GPOE7 0x00000080L 1053#define EGPIODR_GPOE8 0x00000100L 1054#endif 1055 1056/***************************************************************************** 1057 * 1058 * The following defines are for the flags in the extended GPIO pin polarity/ 1059 * type register. 1060 * 1061 *****************************************************************************/ 1062#ifndef NO_CS4612 1063#define EGPIOPTR_GPPT0 0x00000001L 1064#define EGPIOPTR_GPPT1 0x00000002L 1065#define EGPIOPTR_GPPT2 0x00000004L 1066#define EGPIOPTR_GPPT3 0x00000008L 1067#define EGPIOPTR_GPPT4 0x00000010L 1068#define EGPIOPTR_GPPT5 0x00000020L 1069#define EGPIOPTR_GPPT6 0x00000040L 1070#define EGPIOPTR_GPPT7 0x00000080L 1071#define EGPIOPTR_GPPT8 0x00000100L 1072#endif 1073 1074/***************************************************************************** 1075 * 1076 * The following defines are for the flags in the extended GPIO pin sticky 1077 * register. 1078 * 1079 *****************************************************************************/ 1080#ifndef NO_CS4612 1081#define EGPIOTR_GPS0 0x00000001L 1082#define EGPIOTR_GPS1 0x00000002L 1083#define EGPIOTR_GPS2 0x00000004L 1084#define EGPIOTR_GPS3 0x00000008L 1085#define EGPIOTR_GPS4 0x00000010L 1086#define EGPIOTR_GPS5 0x00000020L 1087#define EGPIOTR_GPS6 0x00000040L 1088#define EGPIOTR_GPS7 0x00000080L 1089#define EGPIOTR_GPS8 0x00000100L 1090#endif 1091 1092/***************************************************************************** 1093 * 1094 * The following defines are for the flags in the extended GPIO ping wakeup 1095 * register. 1096 * 1097 *****************************************************************************/ 1098#ifndef NO_CS4612 1099#define EGPIOWR_GPW0 0x00000001L 1100#define EGPIOWR_GPW1 0x00000002L 1101#define EGPIOWR_GPW2 0x00000004L 1102#define EGPIOWR_GPW3 0x00000008L 1103#define EGPIOWR_GPW4 0x00000010L 1104#define EGPIOWR_GPW5 0x00000020L 1105#define EGPIOWR_GPW6 0x00000040L 1106#define EGPIOWR_GPW7 0x00000080L 1107#define EGPIOWR_GPW8 0x00000100L 1108#endif 1109 1110/***************************************************************************** 1111 * 1112 * The following defines are for the flags in the extended GPIO pin status 1113 * register. 1114 * 1115 *****************************************************************************/ 1116#ifndef NO_CS4612 1117#define EGPIOSR_GPS0 0x00000001L 1118#define EGPIOSR_GPS1 0x00000002L 1119#define EGPIOSR_GPS2 0x00000004L 1120#define EGPIOSR_GPS3 0x00000008L 1121#define EGPIOSR_GPS4 0x00000010L 1122#define EGPIOSR_GPS5 0x00000020L 1123#define EGPIOSR_GPS6 0x00000040L 1124#define EGPIOSR_GPS7 0x00000080L 1125#define EGPIOSR_GPS8 0x00000100L 1126#endif 1127 1128/***************************************************************************** 1129 * 1130 * The following defines are for the flags in the serial port 6 configuration 1131 * register. 1132 * 1133 *****************************************************************************/ 1134#ifndef NO_CS4612 1135#define SERC6_ASDO2EN 0x00000001L 1136#endif 1137 1138/***************************************************************************** 1139 * 1140 * The following defines are for the flags in the serial port 7 configuration 1141 * register. 1142 * 1143 *****************************************************************************/ 1144#ifndef NO_CS4612 1145#define SERC7_ASDI2EN 0x00000001L 1146#define SERC7_POSILB 0x00000002L 1147#define SERC7_SIPOLB 0x00000004L 1148#define SERC7_SOSILB 0x00000008L 1149#define SERC7_SISOLB 0x00000010L 1150#endif 1151 1152/***************************************************************************** 1153 * 1154 * The following defines are for the flags in the serial port AC link 1155 * configuration register. 1156 * 1157 *****************************************************************************/ 1158#ifndef NO_CS4612 1159#define SERACC_CODEC_TYPE_MASK 0x00000001L 1160#define SERACC_CODEC_TYPE_1_03 0x00000000L 1161#define SERACC_CODEC_TYPE_2_0 0x00000001L 1162#define SERACC_TWO_CODECS 0x00000002L 1163#define SERACC_MDM 0x00000004L 1164#define SERACC_HSP 0x00000008L 1165#endif 1166 1167/***************************************************************************** 1168 * 1169 * The following defines are for the flags in the AC97 control register 2. 1170 * 1171 *****************************************************************************/ 1172#ifndef NO_CS4612 1173#define ACCTL2_RSTN 0x00000001L 1174#define ACCTL2_ESYN 0x00000002L 1175#define ACCTL2_VFRM 0x00000004L 1176#define ACCTL2_DCV 0x00000008L 1177#define ACCTL2_CRW 0x00000010L 1178#define ACCTL2_ASYN 0x00000020L 1179#endif 1180 1181/***************************************************************************** 1182 * 1183 * The following defines are for the flags in the AC97 status register 2. 1184 * 1185 *****************************************************************************/ 1186#ifndef NO_CS4612 1187#define ACSTS2_CRDY 0x00000001L 1188#define ACSTS2_VSTS 0x00000002L 1189#endif 1190 1191/***************************************************************************** 1192 * 1193 * The following defines are for the flags in the AC97 output slot valid 1194 * register 2. 1195 * 1196 *****************************************************************************/ 1197#ifndef NO_CS4612 1198#define ACOSV2_SLV3 0x00000001L 1199#define ACOSV2_SLV4 0x00000002L 1200#define ACOSV2_SLV5 0x00000004L 1201#define ACOSV2_SLV6 0x00000008L 1202#define ACOSV2_SLV7 0x00000010L 1203#define ACOSV2_SLV8 0x00000020L 1204#define ACOSV2_SLV9 0x00000040L 1205#define ACOSV2_SLV10 0x00000080L 1206#define ACOSV2_SLV11 0x00000100L 1207#define ACOSV2_SLV12 0x00000200L 1208#endif 1209 1210/***************************************************************************** 1211 * 1212 * The following defines are for the flags in the AC97 command address 1213 * register 2. 1214 * 1215 *****************************************************************************/ 1216#ifndef NO_CS4612 1217#define ACCAD2_CI_MASK 0x0000007FL 1218#define ACCAD2_CI_SHIFT 0L 1219#endif 1220 1221/***************************************************************************** 1222 * 1223 * The following defines are for the flags in the AC97 command data register 1224 * 2. 1225 * 1226 *****************************************************************************/ 1227#ifndef NO_CS4612 1228#define ACCDA2_CD_MASK 0x0000FFFFL 1229#define ACCDA2_CD_SHIFT 0L 1230#endif 1231 1232/***************************************************************************** 1233 * 1234 * The following defines are for the flags in the AC97 input slot valid 1235 * register 2. 1236 * 1237 *****************************************************************************/ 1238#ifndef NO_CS4612 1239#define ACISV2_ISV3 0x00000001L 1240#define ACISV2_ISV4 0x00000002L 1241#define ACISV2_ISV5 0x00000004L 1242#define ACISV2_ISV6 0x00000008L 1243#define ACISV2_ISV7 0x00000010L 1244#define ACISV2_ISV8 0x00000020L 1245#define ACISV2_ISV9 0x00000040L 1246#define ACISV2_ISV10 0x00000080L 1247#define ACISV2_ISV11 0x00000100L 1248#define ACISV2_ISV12 0x00000200L 1249#endif 1250 1251/***************************************************************************** 1252 * 1253 * The following defines are for the flags in the AC97 status address 1254 * register 2. 1255 * 1256 *****************************************************************************/ 1257#ifndef NO_CS4612 1258#define ACSAD2_SI_MASK 0x0000007FL 1259#define ACSAD2_SI_SHIFT 0L 1260#endif 1261 1262/***************************************************************************** 1263 * 1264 * The following defines are for the flags in the AC97 status data register 2. 1265 * 1266 *****************************************************************************/ 1267#ifndef NO_CS4612 1268#define ACSDA2_SD_MASK 0x0000FFFFL 1269#define ACSDA2_SD_SHIFT 0L 1270#endif 1271 1272/***************************************************************************** 1273 * 1274 * The following defines are for the flags in the I/O trap address and control 1275 * registers (all 12). 1276 * 1277 *****************************************************************************/ 1278#ifndef NO_CS4612 1279#define IOTAC_SA_MASK 0x0000FFFFL 1280#define IOTAC_MSK_MASK 0x000F0000L 1281#define IOTAC_IODC_MASK 0x06000000L 1282#define IOTAC_IODC_16_BIT 0x00000000L 1283#define IOTAC_IODC_10_BIT 0x02000000L 1284#define IOTAC_IODC_12_BIT 0x04000000L 1285#define IOTAC_WSPI 0x08000000L 1286#define IOTAC_RSPI 0x10000000L 1287#define IOTAC_WSE 0x20000000L 1288#define IOTAC_WE 0x40000000L 1289#define IOTAC_RE 0x80000000L 1290#define IOTAC_SA_SHIFT 0L 1291#define IOTAC_MSK_SHIFT 16L 1292#endif 1293 1294/***************************************************************************** 1295 * 1296 * The following defines are for the flags in the I/O trap fast read registers 1297 * (all 8). 1298 * 1299 *****************************************************************************/ 1300#ifndef NO_CS4612 1301#define IOTFR_D_MASK 0x0000FFFFL 1302#define IOTFR_A_MASK 0x000F0000L 1303#define IOTFR_R_MASK 0x0F000000L 1304#define IOTFR_ALL 0x40000000L 1305#define IOTFR_VL 0x80000000L 1306#define IOTFR_D_SHIFT 0L 1307#define IOTFR_A_SHIFT 16L 1308#define IOTFR_R_SHIFT 24L 1309#endif 1310 1311/***************************************************************************** 1312 * 1313 * The following defines are for the flags in the I/O trap FIFO register. 1314 * 1315 *****************************************************************************/ 1316#ifndef NO_CS4612 1317#define IOTFIFO_BA_MASK 0x00003FFFL 1318#define IOTFIFO_S_MASK 0x00FF0000L 1319#define IOTFIFO_OF 0x40000000L 1320#define IOTFIFO_SPIOF 0x80000000L 1321#define IOTFIFO_BA_SHIFT 0L 1322#define IOTFIFO_S_SHIFT 16L 1323#endif 1324 1325/***************************************************************************** 1326 * 1327 * The following defines are for the flags in the I/O trap retry read data 1328 * register. 1329 * 1330 *****************************************************************************/ 1331#ifndef NO_CS4612 1332#define IOTRRD_D_MASK 0x0000FFFFL 1333#define IOTRRD_RDV 0x80000000L 1334#define IOTRRD_D_SHIFT 0L 1335#endif 1336 1337/***************************************************************************** 1338 * 1339 * The following defines are for the flags in the I/O trap FIFO pointer 1340 * register. 1341 * 1342 *****************************************************************************/ 1343#ifndef NO_CS4612 1344#define IOTFP_CA_MASK 0x00003FFFL 1345#define IOTFP_PA_MASK 0x3FFF0000L 1346#define IOTFP_CA_SHIFT 0L 1347#define IOTFP_PA_SHIFT 16L 1348#endif 1349 1350/***************************************************************************** 1351 * 1352 * The following defines are for the flags in the I/O trap control register. 1353 * 1354 *****************************************************************************/ 1355#ifndef NO_CS4612 1356#define IOTCR_ITD 0x00000001L 1357#define IOTCR_HRV 0x00000002L 1358#define IOTCR_SRV 0x00000004L 1359#define IOTCR_DTI 0x00000008L 1360#define IOTCR_DFI 0x00000010L 1361#define IOTCR_DDP 0x00000020L 1362#define IOTCR_JTE 0x00000040L 1363#define IOTCR_PPE 0x00000080L 1364#endif 1365 1366/***************************************************************************** 1367 * 1368 * The following defines are for the flags in the direct PCI data register. 1369 * 1370 *****************************************************************************/ 1371#ifndef NO_CS4612 1372#define DPCID_D_MASK 0xFFFFFFFFL 1373#define DPCID_D_SHIFT 0L 1374#endif 1375 1376/***************************************************************************** 1377 * 1378 * The following defines are for the flags in the direct PCI address register. 1379 * 1380 *****************************************************************************/ 1381#ifndef NO_CS4612 1382#define DPCIA_A_MASK 0xFFFFFFFFL 1383#define DPCIA_A_SHIFT 0L 1384#endif 1385 1386/***************************************************************************** 1387 * 1388 * The following defines are for the flags in the direct PCI command register. 1389 * 1390 *****************************************************************************/ 1391#ifndef NO_CS4612 1392#define DPCIC_C_MASK 0x0000000FL 1393#define DPCIC_C_IOREAD 0x00000002L 1394#define DPCIC_C_IOWRITE 0x00000003L 1395#define DPCIC_BE_MASK 0x000000F0L 1396#endif 1397 1398/***************************************************************************** 1399 * 1400 * The following defines are for the flags in the PC/PCI request register. 1401 * 1402 *****************************************************************************/ 1403#ifndef NO_CS4612 1404#define PCPCIR_RDC_MASK 0x00000007L 1405#define PCPCIR_C_MASK 0x00007000L 1406#define PCPCIR_REQ 0x00008000L 1407#define PCPCIR_RDC_SHIFT 0L 1408#define PCPCIR_C_SHIFT 12L 1409#endif 1410 1411/***************************************************************************** 1412 * 1413 * The following defines are for the flags in the PC/PCI grant register. 1414 * 1415 *****************************************************************************/ 1416#ifndef NO_CS4612 1417#define PCPCIG_GDC_MASK 0x00000007L 1418#define PCPCIG_VL 0x00008000L 1419#define PCPCIG_GDC_SHIFT 0L 1420#endif 1421 1422/***************************************************************************** 1423 * 1424 * The following defines are for the flags in the PC/PCI master enable 1425 * register. 1426 * 1427 *****************************************************************************/ 1428#ifndef NO_CS4612 1429#define PCPCIEN_EN 0x00000001L 1430#endif 1431 1432/***************************************************************************** 1433 * 1434 * The following defines are for the flags in the extended PCI power 1435 * management control register. 1436 * 1437 *****************************************************************************/ 1438#ifndef NO_CS4612 1439#define EPCIPMC_GWU 0x00000001L 1440#define EPCIPMC_FSPC 0x00000002L 1441#endif 1442 1443/***************************************************************************** 1444 * 1445 * The following defines are for the flags in the SP control register. 1446 * 1447 *****************************************************************************/ 1448#define SPCR_RUN 0x00000001L 1449#define SPCR_STPFR 0x00000002L 1450#define SPCR_RUNFR 0x00000004L 1451#define SPCR_TICK 0x00000008L 1452#define SPCR_DRQEN 0x00000020L 1453#define SPCR_RSTSP 0x00000040L 1454#define SPCR_OREN 0x00000080L 1455#ifndef NO_CS4612 1456#define SPCR_PCIINT 0x00000100L 1457#define SPCR_OINTD 0x00000200L 1458#define SPCR_CRE 0x00008000L 1459#endif 1460 1461/***************************************************************************** 1462 * 1463 * The following defines are for the flags in the debug index register. 1464 * 1465 *****************************************************************************/ 1466#define DREG_REGID_MASK 0x0000007FL 1467#define DREG_DEBUG 0x00000080L 1468#define DREG_RGBK_MASK 0x00000700L 1469#define DREG_TRAP 0x00000800L 1470#if !defined(NO_CS4612) 1471#if !defined(NO_CS4615) 1472#define DREG_TRAPX 0x00001000L 1473#endif 1474#endif 1475#define DREG_REGID_SHIFT 0L 1476#define DREG_RGBK_SHIFT 8L 1477#define DREG_RGBK_REGID_MASK 0x0000077FL 1478#define DREG_REGID_R0 0x00000010L 1479#define DREG_REGID_R1 0x00000011L 1480#define DREG_REGID_R2 0x00000012L 1481#define DREG_REGID_R3 0x00000013L 1482#define DREG_REGID_R4 0x00000014L 1483#define DREG_REGID_R5 0x00000015L 1484#define DREG_REGID_R6 0x00000016L 1485#define DREG_REGID_R7 0x00000017L 1486#define DREG_REGID_R8 0x00000018L 1487#define DREG_REGID_R9 0x00000019L 1488#define DREG_REGID_RA 0x0000001AL 1489#define DREG_REGID_RB 0x0000001BL 1490#define DREG_REGID_RC 0x0000001CL 1491#define DREG_REGID_RD 0x0000001DL 1492#define DREG_REGID_RE 0x0000001EL 1493#define DREG_REGID_RF 0x0000001FL 1494#define DREG_REGID_RA_BUS_LOW 0x00000020L 1495#define DREG_REGID_RA_BUS_HIGH 0x00000038L 1496#define DREG_REGID_YBUS_LOW 0x00000050L 1497#define DREG_REGID_YBUS_HIGH 0x00000058L 1498#define DREG_REGID_TRAP_0 0x00000100L 1499#define DREG_REGID_TRAP_1 0x00000101L 1500#define DREG_REGID_TRAP_2 0x00000102L 1501#define DREG_REGID_TRAP_3 0x00000103L 1502#define DREG_REGID_TRAP_4 0x00000104L 1503#define DREG_REGID_TRAP_5 0x00000105L 1504#define DREG_REGID_TRAP_6 0x00000106L 1505#define DREG_REGID_TRAP_7 0x00000107L 1506#define DREG_REGID_INDIRECT_ADDRESS 0x0000010EL 1507#define DREG_REGID_TOP_OF_STACK 0x0000010FL 1508#if !defined(NO_CS4612) 1509#if !defined(NO_CS4615) 1510#define DREG_REGID_TRAP_8 0x00000110L 1511#define DREG_REGID_TRAP_9 0x00000111L 1512#define DREG_REGID_TRAP_10 0x00000112L 1513#define DREG_REGID_TRAP_11 0x00000113L 1514#define DREG_REGID_TRAP_12 0x00000114L 1515#define DREG_REGID_TRAP_13 0x00000115L 1516#define DREG_REGID_TRAP_14 0x00000116L 1517#define DREG_REGID_TRAP_15 0x00000117L 1518#define DREG_REGID_TRAP_16 0x00000118L 1519#define DREG_REGID_TRAP_17 0x00000119L 1520#define DREG_REGID_TRAP_18 0x0000011AL 1521#define DREG_REGID_TRAP_19 0x0000011BL 1522#define DREG_REGID_TRAP_20 0x0000011CL 1523#define DREG_REGID_TRAP_21 0x0000011DL 1524#define DREG_REGID_TRAP_22 0x0000011EL 1525#define DREG_REGID_TRAP_23 0x0000011FL 1526#endif 1527#endif 1528#define DREG_REGID_RSA0_LOW 0x00000200L 1529#define DREG_REGID_RSA0_HIGH 0x00000201L 1530#define DREG_REGID_RSA1_LOW 0x00000202L 1531#define DREG_REGID_RSA1_HIGH 0x00000203L 1532#define DREG_REGID_RSA2 0x00000204L 1533#define DREG_REGID_RSA3 0x00000205L 1534#define DREG_REGID_RSI0_LOW 0x00000206L 1535#define DREG_REGID_RSI0_HIGH 0x00000207L 1536#define DREG_REGID_RSI1 0x00000208L 1537#define DREG_REGID_RSI2 0x00000209L 1538#define DREG_REGID_SAGUSTATUS 0x0000020AL 1539#define DREG_REGID_RSCONFIG01_LOW 0x0000020BL 1540#define DREG_REGID_RSCONFIG01_HIGH 0x0000020CL 1541#define DREG_REGID_RSCONFIG23_LOW 0x0000020DL 1542#define DREG_REGID_RSCONFIG23_HIGH 0x0000020EL 1543#define DREG_REGID_RSDMA01E 0x0000020FL 1544#define DREG_REGID_RSDMA23E 0x00000210L 1545#define DREG_REGID_RSD0_LOW 0x00000211L 1546#define DREG_REGID_RSD0_HIGH 0x00000212L 1547#define DREG_REGID_RSD1_LOW 0x00000213L 1548#define DREG_REGID_RSD1_HIGH 0x00000214L 1549#define DREG_REGID_RSD2_LOW 0x00000215L 1550#define DREG_REGID_RSD2_HIGH 0x00000216L 1551#define DREG_REGID_RSD3_LOW 0x00000217L 1552#define DREG_REGID_RSD3_HIGH 0x00000218L 1553#define DREG_REGID_SRAR_HIGH 0x0000021AL 1554#define DREG_REGID_SRAR_LOW 0x0000021BL 1555#define DREG_REGID_DMA_STATE 0x0000021CL 1556#define DREG_REGID_CURRENT_DMA_STREAM 0x0000021DL 1557#define DREG_REGID_NEXT_DMA_STREAM 0x0000021EL 1558#define DREG_REGID_CPU_STATUS 0x00000300L 1559#define DREG_REGID_MAC_MODE 0x00000301L 1560#define DREG_REGID_STACK_AND_REPEAT 0x00000302L 1561#define DREG_REGID_INDEX0 0x00000304L 1562#define DREG_REGID_INDEX1 0x00000305L 1563#define DREG_REGID_DMA_STATE_0_3 0x00000400L 1564#define DREG_REGID_DMA_STATE_4_7 0x00000404L 1565#define DREG_REGID_DMA_STATE_8_11 0x00000408L 1566#define DREG_REGID_DMA_STATE_12_15 0x0000040CL 1567#define DREG_REGID_DMA_STATE_16_19 0x00000410L 1568#define DREG_REGID_DMA_STATE_20_23 0x00000414L 1569#define DREG_REGID_DMA_STATE_24_27 0x00000418L 1570#define DREG_REGID_DMA_STATE_28_31 0x0000041CL 1571#define DREG_REGID_DMA_STATE_32_35 0x00000420L 1572#define DREG_REGID_DMA_STATE_36_39 0x00000424L 1573#define DREG_REGID_DMA_STATE_40_43 0x00000428L 1574#define DREG_REGID_DMA_STATE_44_47 0x0000042CL 1575#define DREG_REGID_DMA_STATE_48_51 0x00000430L 1576#define DREG_REGID_DMA_STATE_52_55 0x00000434L 1577#define DREG_REGID_DMA_STATE_56_59 0x00000438L 1578#define DREG_REGID_DMA_STATE_60_63 0x0000043CL 1579#define DREG_REGID_DMA_STATE_64_67 0x00000440L 1580#define DREG_REGID_DMA_STATE_68_71 0x00000444L 1581#define DREG_REGID_DMA_STATE_72_75 0x00000448L 1582#define DREG_REGID_DMA_STATE_76_79 0x0000044CL 1583#define DREG_REGID_DMA_STATE_80_83 0x00000450L 1584#define DREG_REGID_DMA_STATE_84_87 0x00000454L 1585#define DREG_REGID_DMA_STATE_88_91 0x00000458L 1586#define DREG_REGID_DMA_STATE_92_95 0x0000045CL 1587#define DREG_REGID_TRAP_SELECT 0x00000500L 1588#define DREG_REGID_TRAP_WRITE_0 0x00000500L 1589#define DREG_REGID_TRAP_WRITE_1 0x00000501L 1590#define DREG_REGID_TRAP_WRITE_2 0x00000502L 1591#define DREG_REGID_TRAP_WRITE_3 0x00000503L 1592#define DREG_REGID_TRAP_WRITE_4 0x00000504L 1593#define DREG_REGID_TRAP_WRITE_5 0x00000505L 1594#define DREG_REGID_TRAP_WRITE_6 0x00000506L 1595#define DREG_REGID_TRAP_WRITE_7 0x00000507L 1596#if !defined(NO_CS4612) 1597#if !defined(NO_CS4615) 1598#define DREG_REGID_TRAP_WRITE_8 0x00000510L 1599#define DREG_REGID_TRAP_WRITE_9 0x00000511L 1600#define DREG_REGID_TRAP_WRITE_10 0x00000512L 1601#define DREG_REGID_TRAP_WRITE_11 0x00000513L 1602#define DREG_REGID_TRAP_WRITE_12 0x00000514L 1603#define DREG_REGID_TRAP_WRITE_13 0x00000515L 1604#define DREG_REGID_TRAP_WRITE_14 0x00000516L 1605#define DREG_REGID_TRAP_WRITE_15 0x00000517L 1606#define DREG_REGID_TRAP_WRITE_16 0x00000518L 1607#define DREG_REGID_TRAP_WRITE_17 0x00000519L 1608#define DREG_REGID_TRAP_WRITE_18 0x0000051AL 1609#define DREG_REGID_TRAP_WRITE_19 0x0000051BL 1610#define DREG_REGID_TRAP_WRITE_20 0x0000051CL 1611#define DREG_REGID_TRAP_WRITE_21 0x0000051DL 1612#define DREG_REGID_TRAP_WRITE_22 0x0000051EL 1613#define DREG_REGID_TRAP_WRITE_23 0x0000051FL 1614#endif 1615#endif 1616#define DREG_REGID_MAC0_ACC0_LOW 0x00000600L 1617#define DREG_REGID_MAC0_ACC1_LOW 0x00000601L 1618#define DREG_REGID_MAC0_ACC2_LOW 0x00000602L 1619#define DREG_REGID_MAC0_ACC3_LOW 0x00000603L 1620#define DREG_REGID_MAC1_ACC0_LOW 0x00000604L 1621#define DREG_REGID_MAC1_ACC1_LOW 0x00000605L 1622#define DREG_REGID_MAC1_ACC2_LOW 0x00000606L 1623#define DREG_REGID_MAC1_ACC3_LOW 0x00000607L 1624#define DREG_REGID_MAC0_ACC0_MID 0x00000608L 1625#define DREG_REGID_MAC0_ACC1_MID 0x00000609L 1626#define DREG_REGID_MAC0_ACC2_MID 0x0000060AL 1627#define DREG_REGID_MAC0_ACC3_MID 0x0000060BL 1628#define DREG_REGID_MAC1_ACC0_MID 0x0000060CL 1629#define DREG_REGID_MAC1_ACC1_MID 0x0000060DL 1630#define DREG_REGID_MAC1_ACC2_MID 0x0000060EL 1631#define DREG_REGID_MAC1_ACC3_MID 0x0000060FL 1632#define DREG_REGID_MAC0_ACC0_HIGH 0x00000610L 1633#define DREG_REGID_MAC0_ACC1_HIGH 0x00000611L 1634#define DREG_REGID_MAC0_ACC2_HIGH 0x00000612L 1635#define DREG_REGID_MAC0_ACC3_HIGH 0x00000613L 1636#define DREG_REGID_MAC1_ACC0_HIGH 0x00000614L 1637#define DREG_REGID_MAC1_ACC1_HIGH 0x00000615L 1638#define DREG_REGID_MAC1_ACC2_HIGH 0x00000616L 1639#define DREG_REGID_MAC1_ACC3_HIGH 0x00000617L 1640#define DREG_REGID_RSHOUT_LOW 0x00000620L 1641#define DREG_REGID_RSHOUT_MID 0x00000628L 1642#define DREG_REGID_RSHOUT_HIGH 0x00000630L 1643 1644/***************************************************************************** 1645 * 1646 * The following defines are for the flags in the DMA stream requestor write 1647 * port register. 1648 * 1649 *****************************************************************************/ 1650#define DSRWP_DSR_MASK 0x0000000FL 1651#define DSRWP_DSR_BG_RQ 0x00000001L 1652#define DSRWP_DSR_PRIORITY_MASK 0x00000006L 1653#define DSRWP_DSR_PRIORITY_0 0x00000000L 1654#define DSRWP_DSR_PRIORITY_1 0x00000002L 1655#define DSRWP_DSR_PRIORITY_2 0x00000004L 1656#define DSRWP_DSR_PRIORITY_3 0x00000006L 1657#define DSRWP_DSR_RQ_PENDING 0x00000008L 1658 1659/***************************************************************************** 1660 * 1661 * The following defines are for the flags in the trap write port register. 1662 * 1663 *****************************************************************************/ 1664#define TWPR_TW_MASK 0x0000FFFFL 1665#define TWPR_TW_SHIFT 0L 1666 1667/***************************************************************************** 1668 * 1669 * The following defines are for the flags in the stack pointer write 1670 * register. 1671 * 1672 *****************************************************************************/ 1673#define SPWR_STKP_MASK 0x0000000FL 1674#define SPWR_STKP_SHIFT 0L 1675 1676/***************************************************************************** 1677 * 1678 * The following defines are for the flags in the SP interrupt register. 1679 * 1680 *****************************************************************************/ 1681#define SPIR_FRI 0x00000001L 1682#define SPIR_DOI 0x00000002L 1683#define SPIR_GPI2 0x00000004L 1684#define SPIR_GPI3 0x00000008L 1685#define SPIR_IP0 0x00000010L 1686#define SPIR_IP1 0x00000020L 1687#define SPIR_IP2 0x00000040L 1688#define SPIR_IP3 0x00000080L 1689 1690/***************************************************************************** 1691 * 1692 * The following defines are for the flags in the functional group 1 register. 1693 * 1694 *****************************************************************************/ 1695#define FGR1_F1S_MASK 0x0000FFFFL 1696#define FGR1_F1S_SHIFT 0L 1697 1698/***************************************************************************** 1699 * 1700 * The following defines are for the flags in the SP clock status register. 1701 * 1702 *****************************************************************************/ 1703#define SPCS_FRI 0x00000001L 1704#define SPCS_DOI 0x00000002L 1705#define SPCS_GPI2 0x00000004L 1706#define SPCS_GPI3 0x00000008L 1707#define SPCS_IP0 0x00000010L 1708#define SPCS_IP1 0x00000020L 1709#define SPCS_IP2 0x00000040L 1710#define SPCS_IP3 0x00000080L 1711#define SPCS_SPRUN 0x00000100L 1712#define SPCS_SLEEP 0x00000200L 1713#define SPCS_FG 0x00000400L 1714#define SPCS_ORUN 0x00000800L 1715#define SPCS_IRQ 0x00001000L 1716#define SPCS_FGN_MASK 0x0000E000L 1717#define SPCS_FGN_SHIFT 13L 1718 1719/***************************************************************************** 1720 * 1721 * The following defines are for the flags in the SP DMA requestor status 1722 * register. 1723 * 1724 *****************************************************************************/ 1725#define SDSR_DCS_MASK 0x000000FFL 1726#define SDSR_DCS_SHIFT 0L 1727#define SDSR_DCS_NONE 0x00000007L 1728 1729/***************************************************************************** 1730 * 1731 * The following defines are for the flags in the frame timer register. 1732 * 1733 *****************************************************************************/ 1734#define FRMT_FTV_MASK 0x0000FFFFL 1735#define FRMT_FTV_SHIFT 0L 1736 1737/***************************************************************************** 1738 * 1739 * The following defines are for the flags in the frame timer current count 1740 * register. 1741 * 1742 *****************************************************************************/ 1743#define FRCC_FCC_MASK 0x0000FFFFL 1744#define FRCC_FCC_SHIFT 0L 1745 1746/***************************************************************************** 1747 * 1748 * The following defines are for the flags in the frame timer save count 1749 * register. 1750 * 1751 *****************************************************************************/ 1752#define FRSC_FCS_MASK 0x0000FFFFL 1753#define FRSC_FCS_SHIFT 0L 1754 1755/***************************************************************************** 1756 * 1757 * The following define the various flags stored in the scatter/gather 1758 * descriptors. 1759 * 1760 *****************************************************************************/ 1761#define DMA_SG_NEXT_ENTRY_MASK 0x00000FF8L 1762#define DMA_SG_SAMPLE_END_MASK 0x0FFF0000L 1763#define DMA_SG_SAMPLE_END_FLAG 0x10000000L 1764#define DMA_SG_LOOP_END_FLAG 0x20000000L 1765#define DMA_SG_SIGNAL_END_FLAG 0x40000000L 1766#define DMA_SG_SIGNAL_PAGE_FLAG 0x80000000L 1767#define DMA_SG_NEXT_ENTRY_SHIFT 3L 1768#define DMA_SG_SAMPLE_END_SHIFT 16L 1769 1770/***************************************************************************** 1771 * 1772 * The following define the offsets of the fields within the on-chip generic 1773 * DMA requestor. 1774 * 1775 *****************************************************************************/ 1776#define DMA_RQ_CONTROL1 0x00000000L 1777#define DMA_RQ_CONTROL2 0x00000004L 1778#define DMA_RQ_SOURCE_ADDR 0x00000008L 1779#define DMA_RQ_DESTINATION_ADDR 0x0000000CL 1780#define DMA_RQ_NEXT_PAGE_ADDR 0x00000010L 1781#define DMA_RQ_NEXT_PAGE_SGDESC 0x00000014L 1782#define DMA_RQ_LOOP_START_ADDR 0x00000018L 1783#define DMA_RQ_POST_LOOP_ADDR 0x0000001CL 1784#define DMA_RQ_PAGE_MAP_ADDR 0x00000020L 1785 1786/***************************************************************************** 1787 * 1788 * The following defines are for the flags in the first control word of the 1789 * on-chip generic DMA requestor. 1790 * 1791 *****************************************************************************/ 1792#define DMA_RQ_C1_COUNT_MASK 0x000003FFL 1793#define DMA_RQ_C1_DESTINATION_SCATTER 0x00001000L 1794#define DMA_RQ_C1_SOURCE_GATHER 0x00002000L 1795#define DMA_RQ_C1_DONE_FLAG 0x00004000L 1796#define DMA_RQ_C1_OPTIMIZE_STATE 0x00008000L 1797#define DMA_RQ_C1_SAMPLE_END_STATE_MASK 0x00030000L 1798#define DMA_RQ_C1_FULL_PAGE 0x00000000L 1799#define DMA_RQ_C1_BEFORE_SAMPLE_END 0x00010000L 1800#define DMA_RQ_C1_PAGE_MAP_ERROR 0x00020000L 1801#define DMA_RQ_C1_AT_SAMPLE_END 0x00030000L 1802#define DMA_RQ_C1_LOOP_END_STATE_MASK 0x000C0000L 1803#define DMA_RQ_C1_NOT_LOOP_END 0x00000000L 1804#define DMA_RQ_C1_BEFORE_LOOP_END 0x00040000L 1805#define DMA_RQ_C1_2PAGE_LOOP_BEGIN 0x00080000L 1806#define DMA_RQ_C1_LOOP_BEGIN 0x000C0000L 1807#define DMA_RQ_C1_PAGE_MAP_MASK 0x00300000L 1808#define DMA_RQ_C1_PM_NONE_PENDING 0x00000000L 1809#define DMA_RQ_C1_PM_NEXT_PENDING 0x00100000L 1810#define DMA_RQ_C1_PM_RESERVED 0x00200000L 1811#define DMA_RQ_C1_PM_LOOP_NEXT_PENDING 0x00300000L 1812#define DMA_RQ_C1_WRITEBACK_DEST_FLAG 0x00400000L 1813#define DMA_RQ_C1_WRITEBACK_SRC_FLAG 0x00800000L 1814#define DMA_RQ_C1_DEST_SIZE_MASK 0x07000000L 1815#define DMA_RQ_C1_DEST_LINEAR 0x00000000L 1816#define DMA_RQ_C1_DEST_MOD16 0x01000000L 1817#define DMA_RQ_C1_DEST_MOD32 0x02000000L 1818#define DMA_RQ_C1_DEST_MOD64 0x03000000L 1819#define DMA_RQ_C1_DEST_MOD128 0x04000000L 1820#define DMA_RQ_C1_DEST_MOD256 0x05000000L 1821#define DMA_RQ_C1_DEST_MOD512 0x06000000L 1822#define DMA_RQ_C1_DEST_MOD1024 0x07000000L 1823#define DMA_RQ_C1_DEST_ON_HOST 0x08000000L 1824#define DMA_RQ_C1_SOURCE_SIZE_MASK 0x70000000L 1825#define DMA_RQ_C1_SOURCE_LINEAR 0x00000000L 1826#define DMA_RQ_C1_SOURCE_MOD16 0x10000000L 1827#define DMA_RQ_C1_SOURCE_MOD32 0x20000000L 1828#define DMA_RQ_C1_SOURCE_MOD64 0x30000000L 1829#define DMA_RQ_C1_SOURCE_MOD128 0x40000000L 1830#define DMA_RQ_C1_SOURCE_MOD256 0x50000000L 1831#define DMA_RQ_C1_SOURCE_MOD512 0x60000000L 1832#define DMA_RQ_C1_SOURCE_MOD1024 0x70000000L 1833#define DMA_RQ_C1_SOURCE_ON_HOST 0x80000000L 1834#define DMA_RQ_C1_COUNT_SHIFT 0L 1835 1836/***************************************************************************** 1837 * 1838 * The following defines are for the flags in the second control word of the 1839 * on-chip generic DMA requestor. 1840 * 1841 *****************************************************************************/ 1842#define DMA_RQ_C2_VIRTUAL_CHANNEL_MASK 0x0000003FL 1843#define DMA_RQ_C2_VIRTUAL_SIGNAL_MASK 0x00000300L 1844#define DMA_RQ_C2_NO_VIRTUAL_SIGNAL 0x00000000L 1845#define DMA_RQ_C2_SIGNAL_EVERY_DMA 0x00000100L 1846#define DMA_RQ_C2_SIGNAL_SOURCE_PINGPONG 0x00000200L 1847#define DMA_RQ_C2_SIGNAL_DEST_PINGPONG 0x00000300L 1848#define DMA_RQ_C2_AUDIO_CONVERT_MASK 0x0000F000L 1849#define DMA_RQ_C2_AC_NONE 0x00000000L 1850#define DMA_RQ_C2_AC_8_TO_16_BIT 0x00001000L 1851#define DMA_RQ_C2_AC_MONO_TO_STEREO 0x00002000L 1852#define DMA_RQ_C2_AC_ENDIAN_CONVERT 0x00004000L 1853#define DMA_RQ_C2_AC_SIGNED_CONVERT 0x00008000L 1854#define DMA_RQ_C2_LOOP_END_MASK 0x0FFF0000L 1855#define DMA_RQ_C2_LOOP_MASK 0x30000000L 1856#define DMA_RQ_C2_NO_LOOP 0x00000000L 1857#define DMA_RQ_C2_ONE_PAGE_LOOP 0x10000000L 1858#define DMA_RQ_C2_TWO_PAGE_LOOP 0x20000000L 1859#define DMA_RQ_C2_MULTI_PAGE_LOOP 0x30000000L 1860#define DMA_RQ_C2_SIGNAL_LOOP_BACK 0x40000000L 1861#define DMA_RQ_C2_SIGNAL_POST_BEGIN_PAGE 0x80000000L 1862#define DMA_RQ_C2_VIRTUAL_CHANNEL_SHIFT 0L 1863#define DMA_RQ_C2_LOOP_END_SHIFT 16L 1864 1865/***************************************************************************** 1866 * 1867 * The following defines are for the flags in the source and destination words 1868 * of the on-chip generic DMA requestor. 1869 * 1870 *****************************************************************************/ 1871#define DMA_RQ_SD_ADDRESS_MASK 0x0000FFFFL 1872#define DMA_RQ_SD_MEMORY_ID_MASK 0x000F0000L 1873#define DMA_RQ_SD_SP_PARAM_ADDR 0x00000000L 1874#define DMA_RQ_SD_SP_SAMPLE_ADDR 0x00010000L 1875#define DMA_RQ_SD_SP_PROGRAM_ADDR 0x00020000L 1876#define DMA_RQ_SD_SP_DEBUG_ADDR 0x00030000L 1877#define DMA_RQ_SD_OMNIMEM_ADDR 0x000E0000L 1878#define DMA_RQ_SD_END_FLAG 0x40000000L 1879#define DMA_RQ_SD_ERROR_FLAG 0x80000000L 1880#define DMA_RQ_SD_ADDRESS_SHIFT 0L 1881 1882/***************************************************************************** 1883 * 1884 * The following defines are for the flags in the page map address word of the 1885 * on-chip generic DMA requestor. 1886 * 1887 *****************************************************************************/ 1888#define DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_MASK 0x00000FF8L 1889#define DMA_RQ_PMA_PAGE_TABLE_MASK 0xFFFFF000L 1890#define DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_SHIFT 3L 1891#define DMA_RQ_PMA_PAGE_TABLE_SHIFT 12L 1892 1893/***************************************************************************** 1894 * 1895 * The following defines are for the flags in the rsConfig01/23 registers of 1896 * the SP. 1897 * 1898 *****************************************************************************/ 1899#define RSCONFIG_MODULO_SIZE_MASK 0x0000000FL 1900#define RSCONFIG_MODULO_16 0x00000001L 1901#define RSCONFIG_MODULO_32 0x00000002L 1902#define RSCONFIG_MODULO_64 0x00000003L 1903#define RSCONFIG_MODULO_128 0x00000004L 1904#define RSCONFIG_MODULO_256 0x00000005L 1905#define RSCONFIG_MODULO_512 0x00000006L 1906#define RSCONFIG_MODULO_1024 0x00000007L 1907#define RSCONFIG_MODULO_4 0x00000008L 1908#define RSCONFIG_MODULO_8 0x00000009L 1909#define RSCONFIG_SAMPLE_SIZE_MASK 0x000000C0L 1910#define RSCONFIG_SAMPLE_8MONO 0x00000000L 1911#define RSCONFIG_SAMPLE_8STEREO 0x00000040L 1912#define RSCONFIG_SAMPLE_16MONO 0x00000080L 1913#define RSCONFIG_SAMPLE_16STEREO 0x000000C0L 1914#define RSCONFIG_UNDERRUN_ZERO 0x00004000L 1915#define RSCONFIG_DMA_TO_HOST 0x00008000L 1916#define RSCONFIG_STREAM_NUM_MASK 0x00FF0000L 1917#define RSCONFIG_MAX_DMA_SIZE_MASK 0x1F000000L 1918#define RSCONFIG_DMA_ENABLE 0x20000000L 1919#define RSCONFIG_PRIORITY_MASK 0xC0000000L 1920#define RSCONFIG_PRIORITY_HIGH 0x00000000L 1921#define RSCONFIG_PRIORITY_MEDIUM_HIGH 0x40000000L 1922#define RSCONFIG_PRIORITY_MEDIUM_LOW 0x80000000L 1923#define RSCONFIG_PRIORITY_LOW 0xC0000000L 1924#define RSCONFIG_STREAM_NUM_SHIFT 16L 1925#define RSCONFIG_MAX_DMA_SIZE_SHIFT 24L 1926 1927#define BA1_VARIDEC_BUF_1 0x000 1928 1929#define BA1_PDTC 0x0c0 /* BA1_PLAY_DMA_TRANSACTION_COUNT_REG */ 1930#define BA1_PFIE 0x0c4 /* BA1_PLAY_FORMAT_&_INTERRUPT_ENABLE_REG */ 1931#define BA1_PBA 0x0c8 /* BA1_PLAY_BUFFER_ADDRESS */ 1932#define BA1_PVOL 0x0f8 /* BA1_PLAY_VOLUME_REG */ 1933#define BA1_PSRC 0x288 /* BA1_PLAY_SAMPLE_RATE_CORRECTION_REG */ 1934#define BA1_PCTL 0x2a4 /* BA1_PLAY_CONTROL_REG */ 1935#define BA1_PPI 0x2b4 /* BA1_PLAY_PHASE_INCREMENT_REG */ 1936 1937#define BA1_CCTL 0x064 /* BA1_CAPTURE_CONTROL_REG */ 1938#define BA1_CIE 0x104 /* BA1_CAPTURE_INTERRUPT_ENABLE_REG */ 1939#define BA1_CBA 0x10c /* BA1_CAPTURE_BUFFER_ADDRESS */ 1940#define BA1_CSRC 0x2c8 /* BA1_CAPTURE_SAMPLE_RATE_CORRECTION_REG */ 1941#define BA1_CCI 0x2d8 /* BA1_CAPTURE_COEFFICIENT_INCREMENT_REG */ 1942#define BA1_CD 0x2e0 /* BA1_CAPTURE_DELAY_REG */ 1943#define BA1_CPI 0x2f4 /* BA1_CAPTURE_PHASE_INCREMENT_REG */ 1944#define BA1_CVOL 0x2f8 /* BA1_CAPTURE_VOLUME_REG */ 1945 1946#define BA1_CFG1 0x134 /* BA1_CAPTURE_FRAME_GROUP_1_REG */ 1947#define BA1_CFG2 0x138 /* BA1_CAPTURE_FRAME_GROUP_2_REG */ 1948#define BA1_CCST 0x13c /* BA1_CAPTURE_CONSTANT_REG */ 1949#define BA1_CSPB 0x340 /* BA1_CAPTURE_SPB_ADDRESS */ 1950 1951/* The following struct holds the initialization array. */ 1952 1953/* 1954 * this is 3*1024 for parameter, 3.5*1024 for sample and 2*3.5*1024 for code since 1955 * each instruction is 40 bits and takes two dwords 1956 */ 1957#define INKY_BA1_DWORD_SIZE (13 * 1024 + 512) 1958#define INKY_MEMORY_COUNT 3 1959 1960struct BA1struct 1961{ 1962 struct 1963 { 1964 u_long ulDestByteOffset, 1965 ulSourceByteSize; 1966 } MemoryStat[INKY_MEMORY_COUNT]; 1967 1968 u_long BA1Array[INKY_BA1_DWORD_SIZE]; 1969}; 1970 1971#endif /* _CSA_REG_H */ 1972