csareg.h revision 53553
1/*- 2 * Copyright (c) 1999 Seigo Tanimura 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/sound/pci/csareg.h 53553 1999-11-22 06:07:49Z tanimura $ 27 */ 28 29#ifndef _CSA_REG_H 30#define _CSA_REG_H 31 32/* This is the pci device id. */ 33#define CS4610_PCI_ID 0x60011013 34#define CS4614_PCI_ID 0x60031013 35#define CS4615_PCI_ID 0x60041013 36#define CS4281_PCI_ID 0x60051013 37 38/* And the offsets in pci configuration space. */ 39#define CS461x_IO_OFFSET 0x10 40#define CS461x_IO_SIZE (4 * 1024) 41#define CS461x_MEM_OFFSET 0x14 42#define CS461x_MEM_SIZE (1024 * 1024) 43 44/* Buffer size on dma transfer. Fixed for CS416x. */ 45#define CS461x_BUFFSIZE (4 * 1024) 46 47#define GOF_PER_SEC 200 48 49/* 50 * The following constats are orginally in the sample by Crystal Semiconductor. 51 * Copyright (c) 1996-1998 Crystal Semiconductor Corp. 52 */ 53 54/***************************************************************************** 55 * 56 * The following define the offsets of the registers accessed via base address 57 * register zero on the CS461x part. 58 * 59 *****************************************************************************/ 60#define BA0_HISR 0x00000000L 61#define BA0_HSR0 0x00000004L 62#define BA0_HICR 0x00000008L 63#define BA0_DMSR 0x00000100L 64#define BA0_HSAR 0x00000110L 65#define BA0_HDAR 0x00000114L 66#define BA0_HDMR 0x00000118L 67#define BA0_HDCR 0x0000011CL 68#define BA0_PFMC 0x00000200L 69#define BA0_PFCV1 0x00000204L 70#define BA0_PFCV2 0x00000208L 71#define BA0_PCICFG00 0x00000300L 72#define BA0_PCICFG04 0x00000304L 73#define BA0_PCICFG08 0x00000308L 74#define BA0_PCICFG0C 0x0000030CL 75#define BA0_PCICFG10 0x00000310L 76#define BA0_PCICFG14 0x00000314L 77#define BA0_PCICFG18 0x00000318L 78#define BA0_PCICFG1C 0x0000031CL 79#define BA0_PCICFG20 0x00000320L 80#define BA0_PCICFG24 0x00000324L 81#define BA0_PCICFG28 0x00000328L 82#define BA0_PCICFG2C 0x0000032CL 83#define BA0_PCICFG30 0x00000330L 84#define BA0_PCICFG34 0x00000334L 85#define BA0_PCICFG38 0x00000338L 86#define BA0_PCICFG3C 0x0000033CL 87#define BA0_CLKCR1 0x00000400L 88#define BA0_CLKCR2 0x00000404L 89#define BA0_PLLM 0x00000408L 90#define BA0_PLLCC 0x0000040CL 91#define BA0_FRR 0x00000410L 92#define BA0_CFL1 0x00000414L 93#define BA0_CFL2 0x00000418L 94#define BA0_SERMC1 0x00000420L 95#define BA0_SERMC2 0x00000424L 96#define BA0_SERC1 0x00000428L 97#define BA0_SERC2 0x0000042CL 98#define BA0_SERC3 0x00000430L 99#define BA0_SERC4 0x00000434L 100#define BA0_SERC5 0x00000438L 101#define BA0_SERBSP 0x0000043CL 102#define BA0_SERBST 0x00000440L 103#define BA0_SERBCM 0x00000444L 104#define BA0_SERBAD 0x00000448L 105#define BA0_SERBCF 0x0000044CL 106#define BA0_SERBWP 0x00000450L 107#define BA0_SERBRP 0x00000454L 108#ifndef NO_CS4612 109#define BA0_ASER_FADDR 0x00000458L 110#endif 111#define BA0_ACCTL 0x00000460L 112#define BA0_ACSTS 0x00000464L 113#define BA0_ACOSV 0x00000468L 114#define BA0_ACCAD 0x0000046CL 115#define BA0_ACCDA 0x00000470L 116#define BA0_ACISV 0x00000474L 117#define BA0_ACSAD 0x00000478L 118#define BA0_ACSDA 0x0000047CL 119#define BA0_JSPT 0x00000480L 120#define BA0_JSCTL 0x00000484L 121#define BA0_JSC1 0x00000488L 122#define BA0_JSC2 0x0000048CL 123#define BA0_MIDCR 0x00000490L 124#define BA0_MIDSR 0x00000494L 125#define BA0_MIDWP 0x00000498L 126#define BA0_MIDRP 0x0000049CL 127#define BA0_JSIO 0x000004A0L 128#ifndef NO_CS4612 129#define BA0_ASER_MASTER 0x000004A4L 130#endif 131#define BA0_CFGI 0x000004B0L 132#define BA0_SSVID 0x000004B4L 133#define BA0_GPIOR 0x000004B8L 134#ifndef NO_CS4612 135#define BA0_EGPIODR 0x000004BCL 136#define BA0_EGPIOPTR 0x000004C0L 137#define BA0_EGPIOTR 0x000004C4L 138#define BA0_EGPIOWR 0x000004C8L 139#define BA0_EGPIOSR 0x000004CCL 140#define BA0_SERC6 0x000004D0L 141#define BA0_SERC7 0x000004D4L 142#define BA0_SERACC 0x000004D8L 143#define BA0_ACCTL2 0x000004E0L 144#define BA0_ACSTS2 0x000004E4L 145#define BA0_ACOSV2 0x000004E8L 146#define BA0_ACCAD2 0x000004ECL 147#define BA0_ACCDA2 0x000004F0L 148#define BA0_ACISV2 0x000004F4L 149#define BA0_ACSAD2 0x000004F8L 150#define BA0_ACSDA2 0x000004FCL 151#define BA0_IOTAC0 0x00000500L 152#define BA0_IOTAC1 0x00000504L 153#define BA0_IOTAC2 0x00000508L 154#define BA0_IOTAC3 0x0000050CL 155#define BA0_IOTAC4 0x00000510L 156#define BA0_IOTAC5 0x00000514L 157#define BA0_IOTAC6 0x00000518L 158#define BA0_IOTAC7 0x0000051CL 159#define BA0_IOTAC8 0x00000520L 160#define BA0_IOTAC9 0x00000524L 161#define BA0_IOTAC10 0x00000528L 162#define BA0_IOTAC11 0x0000052CL 163#define BA0_IOTFR0 0x00000540L 164#define BA0_IOTFR1 0x00000544L 165#define BA0_IOTFR2 0x00000548L 166#define BA0_IOTFR3 0x0000054CL 167#define BA0_IOTFR4 0x00000550L 168#define BA0_IOTFR5 0x00000554L 169#define BA0_IOTFR6 0x00000558L 170#define BA0_IOTFR7 0x0000055CL 171#define BA0_IOTFIFO 0x00000580L 172#define BA0_IOTRRD 0x00000584L 173#define BA0_IOTFP 0x00000588L 174#define BA0_IOTCR 0x0000058CL 175#define BA0_DPCID 0x00000590L 176#define BA0_DPCIA 0x00000594L 177#define BA0_DPCIC 0x00000598L 178#define BA0_PCPCIR 0x00000600L 179#define BA0_PCPCIG 0x00000604L 180#define BA0_PCPCIEN 0x00000608L 181#define BA0_EPCIPMC 0x00000610L 182#endif 183 184/***************************************************************************** 185 * 186 * The following define the offsets of the AC97 shadow registers, which appear 187 * as a virtual extension to the base address register zero memory range. 188 * 189 *****************************************************************************/ 190#define BA0_AC97_RESET 0x00001000L 191#define BA0_AC97_MASTER_VOLUME 0x00001002L 192#define BA0_AC97_HEADPHONE_VOLUME 0x00001004L 193#define BA0_AC97_MASTER_VOLUME_MONO 0x00001006L 194#define BA0_AC97_MASTER_TONE 0x00001008L 195#define BA0_AC97_PC_BEEP_VOLUME 0x0000100AL 196#define BA0_AC97_PHONE_VOLUME 0x0000100CL 197#define BA0_AC97_MIC_VOLUME 0x0000100EL 198#define BA0_AC97_LINE_IN_VOLUME 0x00001010L 199#define BA0_AC97_CD_VOLUME 0x00001012L 200#define BA0_AC97_VIDEO_VOLUME 0x00001014L 201#define BA0_AC97_AUX_VOLUME 0x00001016L 202#define BA0_AC97_PCM_OUT_VOLUME 0x00001018L 203#define BA0_AC97_RECORD_SELECT 0x0000101AL 204#define BA0_AC97_RECORD_GAIN 0x0000101CL 205#define BA0_AC97_RECORD_GAIN_MIC 0x0000101EL 206#define BA0_AC97_GENERAL_PURPOSE 0x00001020L 207#define BA0_AC97_3D_CONTROL 0x00001022L 208#define BA0_AC97_MODEM_RATE 0x00001024L 209#define BA0_AC97_POWERDOWN 0x00001026L 210#define BA0_AC97_RESERVED_28 0x00001028L 211#define BA0_AC97_RESERVED_2A 0x0000102AL 212#define BA0_AC97_RESERVED_2C 0x0000102CL 213#define BA0_AC97_RESERVED_2E 0x0000102EL 214#define BA0_AC97_RESERVED_30 0x00001030L 215#define BA0_AC97_RESERVED_32 0x00001032L 216#define BA0_AC97_RESERVED_34 0x00001034L 217#define BA0_AC97_RESERVED_36 0x00001036L 218#define BA0_AC97_RESERVED_38 0x00001038L 219#define BA0_AC97_RESERVED_3A 0x0000103AL 220#define BA0_AC97_RESERVED_3C 0x0000103CL 221#define BA0_AC97_RESERVED_3E 0x0000103EL 222#define BA0_AC97_RESERVED_40 0x00001040L 223#define BA0_AC97_RESERVED_42 0x00001042L 224#define BA0_AC97_RESERVED_44 0x00001044L 225#define BA0_AC97_RESERVED_46 0x00001046L 226#define BA0_AC97_RESERVED_48 0x00001048L 227#define BA0_AC97_RESERVED_4A 0x0000104AL 228#define BA0_AC97_RESERVED_4C 0x0000104CL 229#define BA0_AC97_RESERVED_4E 0x0000104EL 230#define BA0_AC97_RESERVED_50 0x00001050L 231#define BA0_AC97_RESERVED_52 0x00001052L 232#define BA0_AC97_RESERVED_54 0x00001054L 233#define BA0_AC97_RESERVED_56 0x00001056L 234#define BA0_AC97_RESERVED_58 0x00001058L 235#define BA0_AC97_VENDOR_RESERVED_5A 0x0000105AL 236#define BA0_AC97_VENDOR_RESERVED_5C 0x0000105CL 237#define BA0_AC97_VENDOR_RESERVED_5E 0x0000105EL 238#define BA0_AC97_VENDOR_RESERVED_60 0x00001060L 239#define BA0_AC97_VENDOR_RESERVED_62 0x00001062L 240#define BA0_AC97_VENDOR_RESERVED_64 0x00001064L 241#define BA0_AC97_VENDOR_RESERVED_66 0x00001066L 242#define BA0_AC97_VENDOR_RESERVED_68 0x00001068L 243#define BA0_AC97_VENDOR_RESERVED_6A 0x0000106AL 244#define BA0_AC97_VENDOR_RESERVED_6C 0x0000106CL 245#define BA0_AC97_VENDOR_RESERVED_6E 0x0000106EL 246#define BA0_AC97_VENDOR_RESERVED_70 0x00001070L 247#define BA0_AC97_VENDOR_RESERVED_72 0x00001072L 248#define BA0_AC97_VENDOR_RESERVED_74 0x00001074L 249#define BA0_AC97_VENDOR_RESERVED_76 0x00001076L 250#define BA0_AC97_VENDOR_RESERVED_78 0x00001078L 251#define BA0_AC97_VENDOR_RESERVED_7A 0x0000107AL 252#define BA0_AC97_VENDOR_ID1 0x0000107CL 253#define BA0_AC97_VENDOR_ID2 0x0000107EL 254 255/***************************************************************************** 256 * 257 * The following define the offsets of the registers and memories accessed via 258 * base address register one on the CS461x part. 259 * 260 *****************************************************************************/ 261#define BA1_SP_DMEM0 0x00000000L 262#define BA1_SP_DMEM1 0x00010000L 263#define BA1_SP_PMEM 0x00020000L 264#define BA1_SPCR 0x00030000L 265#define BA1_DREG 0x00030004L 266#define BA1_DSRWP 0x00030008L 267#define BA1_TWPR 0x0003000CL 268#define BA1_SPWR 0x00030010L 269#define BA1_SPIR 0x00030014L 270#define BA1_FGR1 0x00030020L 271#define BA1_SPCS 0x00030028L 272#define BA1_SDSR 0x0003002CL 273#define BA1_FRMT 0x00030030L 274#define BA1_FRCC 0x00030034L 275#define BA1_FRSC 0x00030038L 276#define BA1_OMNI_MEM 0x000E0000L 277 278/***************************************************************************** 279 * 280 * The following defines are for the flags in the PCI interrupt register. 281 * 282 *****************************************************************************/ 283#define PI_LINE_MASK 0x000000FFL 284#define PI_PIN_MASK 0x0000FF00L 285#define PI_MIN_GRANT_MASK 0x00FF0000L 286#define PI_MAX_LATENCY_MASK 0xFF000000L 287#define PI_LINE_SHIFT 0L 288#define PI_PIN_SHIFT 8L 289#define PI_MIN_GRANT_SHIFT 16L 290#define PI_MAX_LATENCY_SHIFT 24L 291 292/***************************************************************************** 293 * 294 * The following defines are for the flags in the host interrupt status 295 * register. 296 * 297 *****************************************************************************/ 298#define HISR_VC_MASK 0x0000FFFFL 299#define HISR_VC0 0x00000001L 300#define HISR_VC1 0x00000002L 301#define HISR_VC2 0x00000004L 302#define HISR_VC3 0x00000008L 303#define HISR_VC4 0x00000010L 304#define HISR_VC5 0x00000020L 305#define HISR_VC6 0x00000040L 306#define HISR_VC7 0x00000080L 307#define HISR_VC8 0x00000100L 308#define HISR_VC9 0x00000200L 309#define HISR_VC10 0x00000400L 310#define HISR_VC11 0x00000800L 311#define HISR_VC12 0x00001000L 312#define HISR_VC13 0x00002000L 313#define HISR_VC14 0x00004000L 314#define HISR_VC15 0x00008000L 315#define HISR_INT0 0x00010000L 316#define HISR_INT1 0x00020000L 317#define HISR_DMAI 0x00040000L 318#define HISR_FROVR 0x00080000L 319#define HISR_MIDI 0x00100000L 320#ifdef NO_CS4612 321#define HISR_RESERVED 0x0FE00000L 322#else 323#define HISR_SBINT 0x00200000L 324#define HISR_RESERVED 0x0FC00000L 325#endif 326#define HISR_H0P 0x40000000L 327#define HISR_INTENA 0x80000000L 328 329/***************************************************************************** 330 * 331 * The following defines are for the flags in the host signal register 0. 332 * 333 *****************************************************************************/ 334#define HSR0_VC_MASK 0xFFFFFFFFL 335#define HSR0_VC16 0x00000001L 336#define HSR0_VC17 0x00000002L 337#define HSR0_VC18 0x00000004L 338#define HSR0_VC19 0x00000008L 339#define HSR0_VC20 0x00000010L 340#define HSR0_VC21 0x00000020L 341#define HSR0_VC22 0x00000040L 342#define HSR0_VC23 0x00000080L 343#define HSR0_VC24 0x00000100L 344#define HSR0_VC25 0x00000200L 345#define HSR0_VC26 0x00000400L 346#define HSR0_VC27 0x00000800L 347#define HSR0_VC28 0x00001000L 348#define HSR0_VC29 0x00002000L 349#define HSR0_VC30 0x00004000L 350#define HSR0_VC31 0x00008000L 351#define HSR0_VC32 0x00010000L 352#define HSR0_VC33 0x00020000L 353#define HSR0_VC34 0x00040000L 354#define HSR0_VC35 0x00080000L 355#define HSR0_VC36 0x00100000L 356#define HSR0_VC37 0x00200000L 357#define HSR0_VC38 0x00400000L 358#define HSR0_VC39 0x00800000L 359#define HSR0_VC40 0x01000000L 360#define HSR0_VC41 0x02000000L 361#define HSR0_VC42 0x04000000L 362#define HSR0_VC43 0x08000000L 363#define HSR0_VC44 0x10000000L 364#define HSR0_VC45 0x20000000L 365#define HSR0_VC46 0x40000000L 366#define HSR0_VC47 0x80000000L 367 368/***************************************************************************** 369 * 370 * The following defines are for the flags in the host interrupt control 371 * register. 372 * 373 *****************************************************************************/ 374#define HICR_IEV 0x00000001L 375#define HICR_CHGM 0x00000002L 376 377/***************************************************************************** 378 * 379 * The following defines are for the flags in the DMA status register. 380 * 381 *****************************************************************************/ 382#define DMSR_HP 0x00000001L 383#define DMSR_HR 0x00000002L 384#define DMSR_SP 0x00000004L 385#define DMSR_SR 0x00000008L 386 387/***************************************************************************** 388 * 389 * The following defines are for the flags in the host DMA source address 390 * register. 391 * 392 *****************************************************************************/ 393#define HSAR_HOST_ADDR_MASK 0xFFFFFFFFL 394#define HSAR_DSP_ADDR_MASK 0x0000FFFFL 395#define HSAR_MEMID_MASK 0x000F0000L 396#define HSAR_MEMID_SP_DMEM0 0x00000000L 397#define HSAR_MEMID_SP_DMEM1 0x00010000L 398#define HSAR_MEMID_SP_PMEM 0x00020000L 399#define HSAR_MEMID_SP_DEBUG 0x00030000L 400#define HSAR_MEMID_OMNI_MEM 0x000E0000L 401#define HSAR_END 0x40000000L 402#define HSAR_ERR 0x80000000L 403 404/***************************************************************************** 405 * 406 * The following defines are for the flags in the host DMA destination address 407 * register. 408 * 409 *****************************************************************************/ 410#define HDAR_HOST_ADDR_MASK 0xFFFFFFFFL 411#define HDAR_DSP_ADDR_MASK 0x0000FFFFL 412#define HDAR_MEMID_MASK 0x000F0000L 413#define HDAR_MEMID_SP_DMEM0 0x00000000L 414#define HDAR_MEMID_SP_DMEM1 0x00010000L 415#define HDAR_MEMID_SP_PMEM 0x00020000L 416#define HDAR_MEMID_SP_DEBUG 0x00030000L 417#define HDAR_MEMID_OMNI_MEM 0x000E0000L 418#define HDAR_END 0x40000000L 419#define HDAR_ERR 0x80000000L 420 421/***************************************************************************** 422 * 423 * The following defines are for the flags in the host DMA control register. 424 * 425 *****************************************************************************/ 426#define HDMR_AC_MASK 0x0000F000L 427#define HDMR_AC_8_16 0x00001000L 428#define HDMR_AC_M_S 0x00002000L 429#define HDMR_AC_B_L 0x00004000L 430#define HDMR_AC_S_U 0x00008000L 431 432/***************************************************************************** 433 * 434 * The following defines are for the flags in the host DMA control register. 435 * 436 *****************************************************************************/ 437#define HDCR_COUNT_MASK 0x000003FFL 438#define HDCR_DONE 0x00004000L 439#define HDCR_OPT 0x00008000L 440#define HDCR_WBD 0x00400000L 441#define HDCR_WBS 0x00800000L 442#define HDCR_DMS_MASK 0x07000000L 443#define HDCR_DMS_LINEAR 0x00000000L 444#define HDCR_DMS_16_DWORDS 0x01000000L 445#define HDCR_DMS_32_DWORDS 0x02000000L 446#define HDCR_DMS_64_DWORDS 0x03000000L 447#define HDCR_DMS_128_DWORDS 0x04000000L 448#define HDCR_DMS_256_DWORDS 0x05000000L 449#define HDCR_DMS_512_DWORDS 0x06000000L 450#define HDCR_DMS_1024_DWORDS 0x07000000L 451#define HDCR_DH 0x08000000L 452#define HDCR_SMS_MASK 0x70000000L 453#define HDCR_SMS_LINEAR 0x00000000L 454#define HDCR_SMS_16_DWORDS 0x10000000L 455#define HDCR_SMS_32_DWORDS 0x20000000L 456#define HDCR_SMS_64_DWORDS 0x30000000L 457#define HDCR_SMS_128_DWORDS 0x40000000L 458#define HDCR_SMS_256_DWORDS 0x50000000L 459#define HDCR_SMS_512_DWORDS 0x60000000L 460#define HDCR_SMS_1024_DWORDS 0x70000000L 461#define HDCR_SH 0x80000000L 462#define HDCR_COUNT_SHIFT 0L 463 464/***************************************************************************** 465 * 466 * The following defines are for the flags in the performance monitor control 467 * register. 468 * 469 *****************************************************************************/ 470#define PFMC_C1SS_MASK 0x0000001FL 471#define PFMC_C1EV 0x00000020L 472#define PFMC_C1RS 0x00008000L 473#define PFMC_C2SS_MASK 0x001F0000L 474#define PFMC_C2EV 0x00200000L 475#define PFMC_C2RS 0x80000000L 476#define PFMC_C1SS_SHIFT 0L 477#define PFMC_C2SS_SHIFT 16L 478#define PFMC_BUS_GRANT 0L 479#define PFMC_GRANT_AFTER_REQ 1L 480#define PFMC_TRANSACTION 2L 481#define PFMC_DWORD_TRANSFER 3L 482#define PFMC_SLAVE_READ 4L 483#define PFMC_SLAVE_WRITE 5L 484#define PFMC_PREEMPTION 6L 485#define PFMC_DISCONNECT_RETRY 7L 486#define PFMC_INTERRUPT 8L 487#define PFMC_BUS_OWNERSHIP 9L 488#define PFMC_TRANSACTION_LAG 10L 489#define PFMC_PCI_CLOCK 11L 490#define PFMC_SERIAL_CLOCK 12L 491#define PFMC_SP_CLOCK 13L 492 493/***************************************************************************** 494 * 495 * The following defines are for the flags in the performance counter value 1 496 * register. 497 * 498 *****************************************************************************/ 499#define PFCV1_PC1V_MASK 0xFFFFFFFFL 500#define PFCV1_PC1V_SHIFT 0L 501 502/***************************************************************************** 503 * 504 * The following defines are for the flags in the performance counter value 2 505 * register. 506 * 507 *****************************************************************************/ 508#define PFCV2_PC2V_MASK 0xFFFFFFFFL 509#define PFCV2_PC2V_SHIFT 0L 510 511/***************************************************************************** 512 * 513 * The following defines are for the flags in the clock control register 1. 514 * 515 *****************************************************************************/ 516#define CLKCR1_OSCS 0x00000001L 517#define CLKCR1_OSCP 0x00000002L 518#define CLKCR1_PLLSS_MASK 0x0000000CL 519#define CLKCR1_PLLSS_SERIAL 0x00000000L 520#define CLKCR1_PLLSS_CRYSTAL 0x00000004L 521#define CLKCR1_PLLSS_PCI 0x00000008L 522#define CLKCR1_PLLSS_RESERVED 0x0000000CL 523#define CLKCR1_PLLP 0x00000010L 524#define CLKCR1_SWCE 0x00000020L 525#define CLKCR1_PLLOS 0x00000040L 526 527/***************************************************************************** 528 * 529 * The following defines are for the flags in the clock control register 2. 530 * 531 *****************************************************************************/ 532#define CLKCR2_PDIVS_MASK 0x0000000FL 533#define CLKCR2_PDIVS_1 0x00000001L 534#define CLKCR2_PDIVS_2 0x00000002L 535#define CLKCR2_PDIVS_4 0x00000004L 536#define CLKCR2_PDIVS_7 0x00000007L 537#define CLKCR2_PDIVS_8 0x00000008L 538#define CLKCR2_PDIVS_16 0x00000000L 539 540/***************************************************************************** 541 * 542 * The following defines are for the flags in the PLL multiplier register. 543 * 544 *****************************************************************************/ 545#define PLLM_MASK 0x000000FFL 546#define PLLM_SHIFT 0L 547 548/***************************************************************************** 549 * 550 * The following defines are for the flags in the PLL capacitor coefficient 551 * register. 552 * 553 *****************************************************************************/ 554#define PLLCC_CDR_MASK 0x00000007L 555#ifndef NO_CS4610 556#define PLLCC_CDR_240_350_MHZ 0x00000000L 557#define PLLCC_CDR_184_265_MHZ 0x00000001L 558#define PLLCC_CDR_144_205_MHZ 0x00000002L 559#define PLLCC_CDR_111_160_MHZ 0x00000003L 560#define PLLCC_CDR_87_123_MHZ 0x00000004L 561#define PLLCC_CDR_67_96_MHZ 0x00000005L 562#define PLLCC_CDR_52_74_MHZ 0x00000006L 563#define PLLCC_CDR_45_58_MHZ 0x00000007L 564#endif 565#ifndef NO_CS4612 566#define PLLCC_CDR_271_398_MHZ 0x00000000L 567#define PLLCC_CDR_227_330_MHZ 0x00000001L 568#define PLLCC_CDR_167_239_MHZ 0x00000002L 569#define PLLCC_CDR_150_215_MHZ 0x00000003L 570#define PLLCC_CDR_107_154_MHZ 0x00000004L 571#define PLLCC_CDR_98_140_MHZ 0x00000005L 572#define PLLCC_CDR_73_104_MHZ 0x00000006L 573#define PLLCC_CDR_63_90_MHZ 0x00000007L 574#endif 575#define PLLCC_LPF_MASK 0x000000F8L 576#ifndef NO_CS4610 577#define PLLCC_LPF_23850_60000_KHZ 0x00000000L 578#define PLLCC_LPF_7960_26290_KHZ 0x00000008L 579#define PLLCC_LPF_4160_10980_KHZ 0x00000018L 580#define PLLCC_LPF_1740_4580_KHZ 0x00000038L 581#define PLLCC_LPF_724_1910_KHZ 0x00000078L 582#define PLLCC_LPF_317_798_KHZ 0x000000F8L 583#endif 584#ifndef NO_CS4612 585#define PLLCC_LPF_25580_64530_KHZ 0x00000000L 586#define PLLCC_LPF_14360_37270_KHZ 0x00000008L 587#define PLLCC_LPF_6100_16020_KHZ 0x00000018L 588#define PLLCC_LPF_2540_6690_KHZ 0x00000038L 589#define PLLCC_LPF_1050_2780_KHZ 0x00000078L 590#define PLLCC_LPF_450_1160_KHZ 0x000000F8L 591#endif 592 593/***************************************************************************** 594 * 595 * The following defines are for the flags in the feature reporting register. 596 * 597 *****************************************************************************/ 598#define FRR_FAB_MASK 0x00000003L 599#define FRR_MASK_MASK 0x0000001CL 600#ifdef NO_CS4612 601#define FRR_CFOP_MASK 0x000000E0L 602#else 603#define FRR_CFOP_MASK 0x00000FE0L 604#endif 605#define FRR_CFOP_NOT_DVD 0x00000020L 606#define FRR_CFOP_A3D 0x00000040L 607#define FRR_CFOP_128_PIN 0x00000080L 608#ifndef NO_CS4612 609#define FRR_CFOP_CS4280 0x00000800L 610#endif 611#define FRR_FAB_SHIFT 0L 612#define FRR_MASK_SHIFT 2L 613#define FRR_CFOP_SHIFT 5L 614 615/***************************************************************************** 616 * 617 * The following defines are for the flags in the configuration load 1 618 * register. 619 * 620 *****************************************************************************/ 621#define CFL1_CLOCK_SOURCE_MASK 0x00000003L 622#define CFL1_CLOCK_SOURCE_CS423X 0x00000000L 623#define CFL1_CLOCK_SOURCE_AC97 0x00000001L 624#define CFL1_CLOCK_SOURCE_CRYSTAL 0x00000002L 625#define CFL1_CLOCK_SOURCE_DUAL_AC97 0x00000003L 626#define CFL1_VALID_DATA_MASK 0x000000FFL 627 628/***************************************************************************** 629 * 630 * The following defines are for the flags in the configuration load 2 631 * register. 632 * 633 *****************************************************************************/ 634#define CFL2_VALID_DATA_MASK 0x000000FFL 635 636/***************************************************************************** 637 * 638 * The following defines are for the flags in the serial port master control 639 * register 1. 640 * 641 *****************************************************************************/ 642#define SERMC1_MSPE 0x00000001L 643#define SERMC1_PTC_MASK 0x0000000EL 644#define SERMC1_PTC_CS423X 0x00000000L 645#define SERMC1_PTC_AC97 0x00000002L 646#define SERMC1_PTC_DAC 0x00000004L 647#define SERMC1_PLB 0x00000010L 648#define SERMC1_XLB 0x00000020L 649 650/***************************************************************************** 651 * 652 * The following defines are for the flags in the serial port master control 653 * register 2. 654 * 655 *****************************************************************************/ 656#define SERMC2_LROE 0x00000001L 657#define SERMC2_MCOE 0x00000002L 658#define SERMC2_MCDIV 0x00000004L 659 660/***************************************************************************** 661 * 662 * The following defines are for the flags in the serial port 1 configuration 663 * register. 664 * 665 *****************************************************************************/ 666#define SERC1_SO1EN 0x00000001L 667#define SERC1_SO1F_MASK 0x0000000EL 668#define SERC1_SO1F_CS423X 0x00000000L 669#define SERC1_SO1F_AC97 0x00000002L 670#define SERC1_SO1F_DAC 0x00000004L 671#define SERC1_SO1F_SPDIF 0x00000006L 672 673/***************************************************************************** 674 * 675 * The following defines are for the flags in the serial port 2 configuration 676 * register. 677 * 678 *****************************************************************************/ 679#define SERC2_SI1EN 0x00000001L 680#define SERC2_SI1F_MASK 0x0000000EL 681#define SERC2_SI1F_CS423X 0x00000000L 682#define SERC2_SI1F_AC97 0x00000002L 683#define SERC2_SI1F_ADC 0x00000004L 684#define SERC2_SI1F_SPDIF 0x00000006L 685 686/***************************************************************************** 687 * 688 * The following defines are for the flags in the serial port 3 configuration 689 * register. 690 * 691 *****************************************************************************/ 692#define SERC3_SO2EN 0x00000001L 693#define SERC3_SO2F_MASK 0x00000006L 694#define SERC3_SO2F_DAC 0x00000000L 695#define SERC3_SO2F_SPDIF 0x00000002L 696 697/***************************************************************************** 698 * 699 * The following defines are for the flags in the serial port 4 configuration 700 * register. 701 * 702 *****************************************************************************/ 703#define SERC4_SO3EN 0x00000001L 704#define SERC4_SO3F_MASK 0x00000006L 705#define SERC4_SO3F_DAC 0x00000000L 706#define SERC4_SO3F_SPDIF 0x00000002L 707 708/***************************************************************************** 709 * 710 * The following defines are for the flags in the serial port 5 configuration 711 * register. 712 * 713 *****************************************************************************/ 714#define SERC5_SI2EN 0x00000001L 715#define SERC5_SI2F_MASK 0x00000006L 716#define SERC5_SI2F_ADC 0x00000000L 717#define SERC5_SI2F_SPDIF 0x00000002L 718 719/***************************************************************************** 720 * 721 * The following defines are for the flags in the serial port backdoor sample 722 * pointer register. 723 * 724 *****************************************************************************/ 725#define SERBSP_FSP_MASK 0x0000000FL 726#define SERBSP_FSP_SHIFT 0L 727 728/***************************************************************************** 729 * 730 * The following defines are for the flags in the serial port backdoor status 731 * register. 732 * 733 *****************************************************************************/ 734#define SERBST_RRDY 0x00000001L 735#define SERBST_WBSY 0x00000002L 736 737/***************************************************************************** 738 * 739 * The following defines are for the flags in the serial port backdoor command 740 * register. 741 * 742 *****************************************************************************/ 743#define SERBCM_RDC 0x00000001L 744#define SERBCM_WRC 0x00000002L 745 746/***************************************************************************** 747 * 748 * The following defines are for the flags in the serial port backdoor address 749 * register. 750 * 751 *****************************************************************************/ 752#ifdef NO_CS4612 753#define SERBAD_FAD_MASK 0x000000FFL 754#else 755#define SERBAD_FAD_MASK 0x000001FFL 756#endif 757#define SERBAD_FAD_SHIFT 0L 758 759/***************************************************************************** 760 * 761 * The following defines are for the flags in the serial port backdoor 762 * configuration register. 763 * 764 *****************************************************************************/ 765#define SERBCF_HBP 0x00000001L 766 767/***************************************************************************** 768 * 769 * The following defines are for the flags in the serial port backdoor write 770 * port register. 771 * 772 *****************************************************************************/ 773#define SERBWP_FWD_MASK 0x000FFFFFL 774#define SERBWP_FWD_SHIFT 0L 775 776/***************************************************************************** 777 * 778 * The following defines are for the flags in the serial port backdoor read 779 * port register. 780 * 781 *****************************************************************************/ 782#define SERBRP_FRD_MASK 0x000FFFFFL 783#define SERBRP_FRD_SHIFT 0L 784 785/***************************************************************************** 786 * 787 * The following defines are for the flags in the async FIFO address register. 788 * 789 *****************************************************************************/ 790#ifndef NO_CS4612 791#define ASER_FADDR_A1_MASK 0x000001FFL 792#define ASER_FADDR_EN1 0x00008000L 793#define ASER_FADDR_A2_MASK 0x01FF0000L 794#define ASER_FADDR_EN2 0x80000000L 795#define ASER_FADDR_A1_SHIFT 0L 796#define ASER_FADDR_A2_SHIFT 16L 797#endif 798 799/***************************************************************************** 800 * 801 * The following defines are for the flags in the AC97 control register. 802 * 803 *****************************************************************************/ 804#define ACCTL_RSTN 0x00000001L 805#define ACCTL_ESYN 0x00000002L 806#define ACCTL_VFRM 0x00000004L 807#define ACCTL_DCV 0x00000008L 808#define ACCTL_CRW 0x00000010L 809#define ACCTL_ASYN 0x00000020L 810#ifndef NO_CS4612 811#define ACCTL_TC 0x00000040L 812#endif 813 814/***************************************************************************** 815 * 816 * The following defines are for the flags in the AC97 status register. 817 * 818 *****************************************************************************/ 819#define ACSTS_CRDY 0x00000001L 820#define ACSTS_VSTS 0x00000002L 821#ifndef NO_CS4612 822#define ACSTS_WKUP 0x00000004L 823#endif 824 825/***************************************************************************** 826 * 827 * The following defines are for the flags in the AC97 output slot valid 828 * register. 829 * 830 *****************************************************************************/ 831#define ACOSV_SLV3 0x00000001L 832#define ACOSV_SLV4 0x00000002L 833#define ACOSV_SLV5 0x00000004L 834#define ACOSV_SLV6 0x00000008L 835#define ACOSV_SLV7 0x00000010L 836#define ACOSV_SLV8 0x00000020L 837#define ACOSV_SLV9 0x00000040L 838#define ACOSV_SLV10 0x00000080L 839#define ACOSV_SLV11 0x00000100L 840#define ACOSV_SLV12 0x00000200L 841 842/***************************************************************************** 843 * 844 * The following defines are for the flags in the AC97 command address 845 * register. 846 * 847 *****************************************************************************/ 848#define ACCAD_CI_MASK 0x0000007FL 849#define ACCAD_CI_SHIFT 0L 850 851/***************************************************************************** 852 * 853 * The following defines are for the flags in the AC97 command data register. 854 * 855 *****************************************************************************/ 856#define ACCDA_CD_MASK 0x0000FFFFL 857#define ACCDA_CD_SHIFT 0L 858 859/***************************************************************************** 860 * 861 * The following defines are for the flags in the AC97 input slot valid 862 * register. 863 * 864 *****************************************************************************/ 865#define ACISV_ISV3 0x00000001L 866#define ACISV_ISV4 0x00000002L 867#define ACISV_ISV5 0x00000004L 868#define ACISV_ISV6 0x00000008L 869#define ACISV_ISV7 0x00000010L 870#define ACISV_ISV8 0x00000020L 871#define ACISV_ISV9 0x00000040L 872#define ACISV_ISV10 0x00000080L 873#define ACISV_ISV11 0x00000100L 874#define ACISV_ISV12 0x00000200L 875 876/***************************************************************************** 877 * 878 * The following defines are for the flags in the AC97 status address 879 * register. 880 * 881 *****************************************************************************/ 882#define ACSAD_SI_MASK 0x0000007FL 883#define ACSAD_SI_SHIFT 0L 884 885/***************************************************************************** 886 * 887 * The following defines are for the flags in the AC97 status data register. 888 * 889 *****************************************************************************/ 890#define ACSDA_SD_MASK 0x0000FFFFL 891#define ACSDA_SD_SHIFT 0L 892 893/***************************************************************************** 894 * 895 * The following defines are for the flags in the joystick poll/trigger 896 * register. 897 * 898 *****************************************************************************/ 899#define JSPT_CAX 0x00000001L 900#define JSPT_CAY 0x00000002L 901#define JSPT_CBX 0x00000004L 902#define JSPT_CBY 0x00000008L 903#define JSPT_BA1 0x00000010L 904#define JSPT_BA2 0x00000020L 905#define JSPT_BB1 0x00000040L 906#define JSPT_BB2 0x00000080L 907 908/***************************************************************************** 909 * 910 * The following defines are for the flags in the joystick control register. 911 * 912 *****************************************************************************/ 913#define JSCTL_SP_MASK 0x00000003L 914#define JSCTL_SP_SLOW 0x00000000L 915#define JSCTL_SP_MEDIUM_SLOW 0x00000001L 916#define JSCTL_SP_MEDIUM_FAST 0x00000002L 917#define JSCTL_SP_FAST 0x00000003L 918#define JSCTL_ARE 0x00000004L 919 920/***************************************************************************** 921 * 922 * The following defines are for the flags in the joystick coordinate pair 1 923 * readback register. 924 * 925 *****************************************************************************/ 926#define JSC1_Y1V_MASK 0x0000FFFFL 927#define JSC1_X1V_MASK 0xFFFF0000L 928#define JSC1_Y1V_SHIFT 0L 929#define JSC1_X1V_SHIFT 16L 930 931/***************************************************************************** 932 * 933 * The following defines are for the flags in the joystick coordinate pair 2 934 * readback register. 935 * 936 *****************************************************************************/ 937#define JSC2_Y2V_MASK 0x0000FFFFL 938#define JSC2_X2V_MASK 0xFFFF0000L 939#define JSC2_Y2V_SHIFT 0L 940#define JSC2_X2V_SHIFT 16L 941 942/***************************************************************************** 943 * 944 * The following defines are for the flags in the MIDI control register. 945 * 946 *****************************************************************************/ 947#define MIDCR_TXE 0x00000001L 948#define MIDCR_RXE 0x00000002L 949#define MIDCR_RIE 0x00000004L 950#define MIDCR_TIE 0x00000008L 951#define MIDCR_MLB 0x00000010L 952#define MIDCR_MRST 0x00000020L 953 954/***************************************************************************** 955 * 956 * The following defines are for the flags in the MIDI status register. 957 * 958 *****************************************************************************/ 959#define MIDSR_TBF 0x00000001L 960#define MIDSR_RBE 0x00000002L 961 962/***************************************************************************** 963 * 964 * The following defines are for the flags in the MIDI write port register. 965 * 966 *****************************************************************************/ 967#define MIDWP_MWD_MASK 0x000000FFL 968#define MIDWP_MWD_SHIFT 0L 969 970/***************************************************************************** 971 * 972 * The following defines are for the flags in the MIDI read port register. 973 * 974 *****************************************************************************/ 975#define MIDRP_MRD_MASK 0x000000FFL 976#define MIDRP_MRD_SHIFT 0L 977 978/***************************************************************************** 979 * 980 * The following defines are for the flags in the joystick GPIO register. 981 * 982 *****************************************************************************/ 983#define JSIO_DAX 0x00000001L 984#define JSIO_DAY 0x00000002L 985#define JSIO_DBX 0x00000004L 986#define JSIO_DBY 0x00000008L 987#define JSIO_AXOE 0x00000010L 988#define JSIO_AYOE 0x00000020L 989#define JSIO_BXOE 0x00000040L 990#define JSIO_BYOE 0x00000080L 991 992/***************************************************************************** 993 * 994 * The following defines are for the flags in the master async/sync serial 995 * port enable register. 996 * 997 *****************************************************************************/ 998#ifndef NO_CS4612 999#define ASER_MASTER_ME 0x00000001L 1000#endif 1001 1002/***************************************************************************** 1003 * 1004 * The following defines are for the flags in the configuration interface 1005 * register. 1006 * 1007 *****************************************************************************/ 1008#define CFGI_CLK 0x00000001L 1009#define CFGI_DOUT 0x00000002L 1010#define CFGI_DIN_EEN 0x00000004L 1011#define CFGI_EELD 0x00000008L 1012 1013/***************************************************************************** 1014 * 1015 * The following defines are for the flags in the subsystem ID and vendor ID 1016 * register. 1017 * 1018 *****************************************************************************/ 1019#define SSVID_VID_MASK 0x0000FFFFL 1020#define SSVID_SID_MASK 0xFFFF0000L 1021#define SSVID_VID_SHIFT 0L 1022#define SSVID_SID_SHIFT 16L 1023 1024/***************************************************************************** 1025 * 1026 * The following defines are for the flags in the GPIO pin interface register. 1027 * 1028 *****************************************************************************/ 1029#define GPIOR_VOLDN 0x00000001L 1030#define GPIOR_VOLUP 0x00000002L 1031#define GPIOR_SI2D 0x00000004L 1032#define GPIOR_SI2OE 0x00000008L 1033 1034/***************************************************************************** 1035 * 1036 * The following defines are for the flags in the extended GPIO pin direction 1037 * register. 1038 * 1039 *****************************************************************************/ 1040#ifndef NO_CS4612 1041#define EGPIODR_GPOE0 0x00000001L 1042#define EGPIODR_GPOE1 0x00000002L 1043#define EGPIODR_GPOE2 0x00000004L 1044#define EGPIODR_GPOE3 0x00000008L 1045#define EGPIODR_GPOE4 0x00000010L 1046#define EGPIODR_GPOE5 0x00000020L 1047#define EGPIODR_GPOE6 0x00000040L 1048#define EGPIODR_GPOE7 0x00000080L 1049#define EGPIODR_GPOE8 0x00000100L 1050#endif 1051 1052/***************************************************************************** 1053 * 1054 * The following defines are for the flags in the extended GPIO pin polarity/ 1055 * type register. 1056 * 1057 *****************************************************************************/ 1058#ifndef NO_CS4612 1059#define EGPIOPTR_GPPT0 0x00000001L 1060#define EGPIOPTR_GPPT1 0x00000002L 1061#define EGPIOPTR_GPPT2 0x00000004L 1062#define EGPIOPTR_GPPT3 0x00000008L 1063#define EGPIOPTR_GPPT4 0x00000010L 1064#define EGPIOPTR_GPPT5 0x00000020L 1065#define EGPIOPTR_GPPT6 0x00000040L 1066#define EGPIOPTR_GPPT7 0x00000080L 1067#define EGPIOPTR_GPPT8 0x00000100L 1068#endif 1069 1070/***************************************************************************** 1071 * 1072 * The following defines are for the flags in the extended GPIO pin sticky 1073 * register. 1074 * 1075 *****************************************************************************/ 1076#ifndef NO_CS4612 1077#define EGPIOTR_GPS0 0x00000001L 1078#define EGPIOTR_GPS1 0x00000002L 1079#define EGPIOTR_GPS2 0x00000004L 1080#define EGPIOTR_GPS3 0x00000008L 1081#define EGPIOTR_GPS4 0x00000010L 1082#define EGPIOTR_GPS5 0x00000020L 1083#define EGPIOTR_GPS6 0x00000040L 1084#define EGPIOTR_GPS7 0x00000080L 1085#define EGPIOTR_GPS8 0x00000100L 1086#endif 1087 1088/***************************************************************************** 1089 * 1090 * The following defines are for the flags in the extended GPIO ping wakeup 1091 * register. 1092 * 1093 *****************************************************************************/ 1094#ifndef NO_CS4612 1095#define EGPIOWR_GPW0 0x00000001L 1096#define EGPIOWR_GPW1 0x00000002L 1097#define EGPIOWR_GPW2 0x00000004L 1098#define EGPIOWR_GPW3 0x00000008L 1099#define EGPIOWR_GPW4 0x00000010L 1100#define EGPIOWR_GPW5 0x00000020L 1101#define EGPIOWR_GPW6 0x00000040L 1102#define EGPIOWR_GPW7 0x00000080L 1103#define EGPIOWR_GPW8 0x00000100L 1104#endif 1105 1106/***************************************************************************** 1107 * 1108 * The following defines are for the flags in the extended GPIO pin status 1109 * register. 1110 * 1111 *****************************************************************************/ 1112#ifndef NO_CS4612 1113#define EGPIOSR_GPS0 0x00000001L 1114#define EGPIOSR_GPS1 0x00000002L 1115#define EGPIOSR_GPS2 0x00000004L 1116#define EGPIOSR_GPS3 0x00000008L 1117#define EGPIOSR_GPS4 0x00000010L 1118#define EGPIOSR_GPS5 0x00000020L 1119#define EGPIOSR_GPS6 0x00000040L 1120#define EGPIOSR_GPS7 0x00000080L 1121#define EGPIOSR_GPS8 0x00000100L 1122#endif 1123 1124/***************************************************************************** 1125 * 1126 * The following defines are for the flags in the serial port 6 configuration 1127 * register. 1128 * 1129 *****************************************************************************/ 1130#ifndef NO_CS4612 1131#define SERC6_ASDO2EN 0x00000001L 1132#endif 1133 1134/***************************************************************************** 1135 * 1136 * The following defines are for the flags in the serial port 7 configuration 1137 * register. 1138 * 1139 *****************************************************************************/ 1140#ifndef NO_CS4612 1141#define SERC7_ASDI2EN 0x00000001L 1142#define SERC7_POSILB 0x00000002L 1143#define SERC7_SIPOLB 0x00000004L 1144#define SERC7_SOSILB 0x00000008L 1145#define SERC7_SISOLB 0x00000010L 1146#endif 1147 1148/***************************************************************************** 1149 * 1150 * The following defines are for the flags in the serial port AC link 1151 * configuration register. 1152 * 1153 *****************************************************************************/ 1154#ifndef NO_CS4612 1155#define SERACC_CODEC_TYPE_MASK 0x00000001L 1156#define SERACC_CODEC_TYPE_1_03 0x00000000L 1157#define SERACC_CODEC_TYPE_2_0 0x00000001L 1158#define SERACC_TWO_CODECS 0x00000002L 1159#define SERACC_MDM 0x00000004L 1160#define SERACC_HSP 0x00000008L 1161#endif 1162 1163/***************************************************************************** 1164 * 1165 * The following defines are for the flags in the AC97 control register 2. 1166 * 1167 *****************************************************************************/ 1168#ifndef NO_CS4612 1169#define ACCTL2_RSTN 0x00000001L 1170#define ACCTL2_ESYN 0x00000002L 1171#define ACCTL2_VFRM 0x00000004L 1172#define ACCTL2_DCV 0x00000008L 1173#define ACCTL2_CRW 0x00000010L 1174#define ACCTL2_ASYN 0x00000020L 1175#endif 1176 1177/***************************************************************************** 1178 * 1179 * The following defines are for the flags in the AC97 status register 2. 1180 * 1181 *****************************************************************************/ 1182#ifndef NO_CS4612 1183#define ACSTS2_CRDY 0x00000001L 1184#define ACSTS2_VSTS 0x00000002L 1185#endif 1186 1187/***************************************************************************** 1188 * 1189 * The following defines are for the flags in the AC97 output slot valid 1190 * register 2. 1191 * 1192 *****************************************************************************/ 1193#ifndef NO_CS4612 1194#define ACOSV2_SLV3 0x00000001L 1195#define ACOSV2_SLV4 0x00000002L 1196#define ACOSV2_SLV5 0x00000004L 1197#define ACOSV2_SLV6 0x00000008L 1198#define ACOSV2_SLV7 0x00000010L 1199#define ACOSV2_SLV8 0x00000020L 1200#define ACOSV2_SLV9 0x00000040L 1201#define ACOSV2_SLV10 0x00000080L 1202#define ACOSV2_SLV11 0x00000100L 1203#define ACOSV2_SLV12 0x00000200L 1204#endif 1205 1206/***************************************************************************** 1207 * 1208 * The following defines are for the flags in the AC97 command address 1209 * register 2. 1210 * 1211 *****************************************************************************/ 1212#ifndef NO_CS4612 1213#define ACCAD2_CI_MASK 0x0000007FL 1214#define ACCAD2_CI_SHIFT 0L 1215#endif 1216 1217/***************************************************************************** 1218 * 1219 * The following defines are for the flags in the AC97 command data register 1220 * 2. 1221 * 1222 *****************************************************************************/ 1223#ifndef NO_CS4612 1224#define ACCDA2_CD_MASK 0x0000FFFFL 1225#define ACCDA2_CD_SHIFT 0L 1226#endif 1227 1228/***************************************************************************** 1229 * 1230 * The following defines are for the flags in the AC97 input slot valid 1231 * register 2. 1232 * 1233 *****************************************************************************/ 1234#ifndef NO_CS4612 1235#define ACISV2_ISV3 0x00000001L 1236#define ACISV2_ISV4 0x00000002L 1237#define ACISV2_ISV5 0x00000004L 1238#define ACISV2_ISV6 0x00000008L 1239#define ACISV2_ISV7 0x00000010L 1240#define ACISV2_ISV8 0x00000020L 1241#define ACISV2_ISV9 0x00000040L 1242#define ACISV2_ISV10 0x00000080L 1243#define ACISV2_ISV11 0x00000100L 1244#define ACISV2_ISV12 0x00000200L 1245#endif 1246 1247/***************************************************************************** 1248 * 1249 * The following defines are for the flags in the AC97 status address 1250 * register 2. 1251 * 1252 *****************************************************************************/ 1253#ifndef NO_CS4612 1254#define ACSAD2_SI_MASK 0x0000007FL 1255#define ACSAD2_SI_SHIFT 0L 1256#endif 1257 1258/***************************************************************************** 1259 * 1260 * The following defines are for the flags in the AC97 status data register 2. 1261 * 1262 *****************************************************************************/ 1263#ifndef NO_CS4612 1264#define ACSDA2_SD_MASK 0x0000FFFFL 1265#define ACSDA2_SD_SHIFT 0L 1266#endif 1267 1268/***************************************************************************** 1269 * 1270 * The following defines are for the flags in the I/O trap address and control 1271 * registers (all 12). 1272 * 1273 *****************************************************************************/ 1274#ifndef NO_CS4612 1275#define IOTAC_SA_MASK 0x0000FFFFL 1276#define IOTAC_MSK_MASK 0x000F0000L 1277#define IOTAC_IODC_MASK 0x06000000L 1278#define IOTAC_IODC_16_BIT 0x00000000L 1279#define IOTAC_IODC_10_BIT 0x02000000L 1280#define IOTAC_IODC_12_BIT 0x04000000L 1281#define IOTAC_WSPI 0x08000000L 1282#define IOTAC_RSPI 0x10000000L 1283#define IOTAC_WSE 0x20000000L 1284#define IOTAC_WE 0x40000000L 1285#define IOTAC_RE 0x80000000L 1286#define IOTAC_SA_SHIFT 0L 1287#define IOTAC_MSK_SHIFT 16L 1288#endif 1289 1290/***************************************************************************** 1291 * 1292 * The following defines are for the flags in the I/O trap fast read registers 1293 * (all 8). 1294 * 1295 *****************************************************************************/ 1296#ifndef NO_CS4612 1297#define IOTFR_D_MASK 0x0000FFFFL 1298#define IOTFR_A_MASK 0x000F0000L 1299#define IOTFR_R_MASK 0x0F000000L 1300#define IOTFR_ALL 0x40000000L 1301#define IOTFR_VL 0x80000000L 1302#define IOTFR_D_SHIFT 0L 1303#define IOTFR_A_SHIFT 16L 1304#define IOTFR_R_SHIFT 24L 1305#endif 1306 1307/***************************************************************************** 1308 * 1309 * The following defines are for the flags in the I/O trap FIFO register. 1310 * 1311 *****************************************************************************/ 1312#ifndef NO_CS4612 1313#define IOTFIFO_BA_MASK 0x00003FFFL 1314#define IOTFIFO_S_MASK 0x00FF0000L 1315#define IOTFIFO_OF 0x40000000L 1316#define IOTFIFO_SPIOF 0x80000000L 1317#define IOTFIFO_BA_SHIFT 0L 1318#define IOTFIFO_S_SHIFT 16L 1319#endif 1320 1321/***************************************************************************** 1322 * 1323 * The following defines are for the flags in the I/O trap retry read data 1324 * register. 1325 * 1326 *****************************************************************************/ 1327#ifndef NO_CS4612 1328#define IOTRRD_D_MASK 0x0000FFFFL 1329#define IOTRRD_RDV 0x80000000L 1330#define IOTRRD_D_SHIFT 0L 1331#endif 1332 1333/***************************************************************************** 1334 * 1335 * The following defines are for the flags in the I/O trap FIFO pointer 1336 * register. 1337 * 1338 *****************************************************************************/ 1339#ifndef NO_CS4612 1340#define IOTFP_CA_MASK 0x00003FFFL 1341#define IOTFP_PA_MASK 0x3FFF0000L 1342#define IOTFP_CA_SHIFT 0L 1343#define IOTFP_PA_SHIFT 16L 1344#endif 1345 1346/***************************************************************************** 1347 * 1348 * The following defines are for the flags in the I/O trap control register. 1349 * 1350 *****************************************************************************/ 1351#ifndef NO_CS4612 1352#define IOTCR_ITD 0x00000001L 1353#define IOTCR_HRV 0x00000002L 1354#define IOTCR_SRV 0x00000004L 1355#define IOTCR_DTI 0x00000008L 1356#define IOTCR_DFI 0x00000010L 1357#define IOTCR_DDP 0x00000020L 1358#define IOTCR_JTE 0x00000040L 1359#define IOTCR_PPE 0x00000080L 1360#endif 1361 1362/***************************************************************************** 1363 * 1364 * The following defines are for the flags in the direct PCI data register. 1365 * 1366 *****************************************************************************/ 1367#ifndef NO_CS4612 1368#define DPCID_D_MASK 0xFFFFFFFFL 1369#define DPCID_D_SHIFT 0L 1370#endif 1371 1372/***************************************************************************** 1373 * 1374 * The following defines are for the flags in the direct PCI address register. 1375 * 1376 *****************************************************************************/ 1377#ifndef NO_CS4612 1378#define DPCIA_A_MASK 0xFFFFFFFFL 1379#define DPCIA_A_SHIFT 0L 1380#endif 1381 1382/***************************************************************************** 1383 * 1384 * The following defines are for the flags in the direct PCI command register. 1385 * 1386 *****************************************************************************/ 1387#ifndef NO_CS4612 1388#define DPCIC_C_MASK 0x0000000FL 1389#define DPCIC_C_IOREAD 0x00000002L 1390#define DPCIC_C_IOWRITE 0x00000003L 1391#define DPCIC_BE_MASK 0x000000F0L 1392#endif 1393 1394/***************************************************************************** 1395 * 1396 * The following defines are for the flags in the PC/PCI request register. 1397 * 1398 *****************************************************************************/ 1399#ifndef NO_CS4612 1400#define PCPCIR_RDC_MASK 0x00000007L 1401#define PCPCIR_C_MASK 0x00007000L 1402#define PCPCIR_REQ 0x00008000L 1403#define PCPCIR_RDC_SHIFT 0L 1404#define PCPCIR_C_SHIFT 12L 1405#endif 1406 1407/***************************************************************************** 1408 * 1409 * The following defines are for the flags in the PC/PCI grant register. 1410 * 1411 *****************************************************************************/ 1412#ifndef NO_CS4612 1413#define PCPCIG_GDC_MASK 0x00000007L 1414#define PCPCIG_VL 0x00008000L 1415#define PCPCIG_GDC_SHIFT 0L 1416#endif 1417 1418/***************************************************************************** 1419 * 1420 * The following defines are for the flags in the PC/PCI master enable 1421 * register. 1422 * 1423 *****************************************************************************/ 1424#ifndef NO_CS4612 1425#define PCPCIEN_EN 0x00000001L 1426#endif 1427 1428/***************************************************************************** 1429 * 1430 * The following defines are for the flags in the extended PCI power 1431 * management control register. 1432 * 1433 *****************************************************************************/ 1434#ifndef NO_CS4612 1435#define EPCIPMC_GWU 0x00000001L 1436#define EPCIPMC_FSPC 0x00000002L 1437#endif 1438 1439/***************************************************************************** 1440 * 1441 * The following defines are for the flags in the SP control register. 1442 * 1443 *****************************************************************************/ 1444#define SPCR_RUN 0x00000001L 1445#define SPCR_STPFR 0x00000002L 1446#define SPCR_RUNFR 0x00000004L 1447#define SPCR_TICK 0x00000008L 1448#define SPCR_DRQEN 0x00000020L 1449#define SPCR_RSTSP 0x00000040L 1450#define SPCR_OREN 0x00000080L 1451#ifndef NO_CS4612 1452#define SPCR_PCIINT 0x00000100L 1453#define SPCR_OINTD 0x00000200L 1454#define SPCR_CRE 0x00008000L 1455#endif 1456 1457/***************************************************************************** 1458 * 1459 * The following defines are for the flags in the debug index register. 1460 * 1461 *****************************************************************************/ 1462#define DREG_REGID_MASK 0x0000007FL 1463#define DREG_DEBUG 0x00000080L 1464#define DREG_RGBK_MASK 0x00000700L 1465#define DREG_TRAP 0x00000800L 1466#if !defined(NO_CS4612) 1467#if !defined(NO_CS4615) 1468#define DREG_TRAPX 0x00001000L 1469#endif 1470#endif 1471#define DREG_REGID_SHIFT 0L 1472#define DREG_RGBK_SHIFT 8L 1473#define DREG_RGBK_REGID_MASK 0x0000077FL 1474#define DREG_REGID_R0 0x00000010L 1475#define DREG_REGID_R1 0x00000011L 1476#define DREG_REGID_R2 0x00000012L 1477#define DREG_REGID_R3 0x00000013L 1478#define DREG_REGID_R4 0x00000014L 1479#define DREG_REGID_R5 0x00000015L 1480#define DREG_REGID_R6 0x00000016L 1481#define DREG_REGID_R7 0x00000017L 1482#define DREG_REGID_R8 0x00000018L 1483#define DREG_REGID_R9 0x00000019L 1484#define DREG_REGID_RA 0x0000001AL 1485#define DREG_REGID_RB 0x0000001BL 1486#define DREG_REGID_RC 0x0000001CL 1487#define DREG_REGID_RD 0x0000001DL 1488#define DREG_REGID_RE 0x0000001EL 1489#define DREG_REGID_RF 0x0000001FL 1490#define DREG_REGID_RA_BUS_LOW 0x00000020L 1491#define DREG_REGID_RA_BUS_HIGH 0x00000038L 1492#define DREG_REGID_YBUS_LOW 0x00000050L 1493#define DREG_REGID_YBUS_HIGH 0x00000058L 1494#define DREG_REGID_TRAP_0 0x00000100L 1495#define DREG_REGID_TRAP_1 0x00000101L 1496#define DREG_REGID_TRAP_2 0x00000102L 1497#define DREG_REGID_TRAP_3 0x00000103L 1498#define DREG_REGID_TRAP_4 0x00000104L 1499#define DREG_REGID_TRAP_5 0x00000105L 1500#define DREG_REGID_TRAP_6 0x00000106L 1501#define DREG_REGID_TRAP_7 0x00000107L 1502#define DREG_REGID_INDIRECT_ADDRESS 0x0000010EL 1503#define DREG_REGID_TOP_OF_STACK 0x0000010FL 1504#if !defined(NO_CS4612) 1505#if !defined(NO_CS4615) 1506#define DREG_REGID_TRAP_8 0x00000110L 1507#define DREG_REGID_TRAP_9 0x00000111L 1508#define DREG_REGID_TRAP_10 0x00000112L 1509#define DREG_REGID_TRAP_11 0x00000113L 1510#define DREG_REGID_TRAP_12 0x00000114L 1511#define DREG_REGID_TRAP_13 0x00000115L 1512#define DREG_REGID_TRAP_14 0x00000116L 1513#define DREG_REGID_TRAP_15 0x00000117L 1514#define DREG_REGID_TRAP_16 0x00000118L 1515#define DREG_REGID_TRAP_17 0x00000119L 1516#define DREG_REGID_TRAP_18 0x0000011AL 1517#define DREG_REGID_TRAP_19 0x0000011BL 1518#define DREG_REGID_TRAP_20 0x0000011CL 1519#define DREG_REGID_TRAP_21 0x0000011DL 1520#define DREG_REGID_TRAP_22 0x0000011EL 1521#define DREG_REGID_TRAP_23 0x0000011FL 1522#endif 1523#endif 1524#define DREG_REGID_RSA0_LOW 0x00000200L 1525#define DREG_REGID_RSA0_HIGH 0x00000201L 1526#define DREG_REGID_RSA1_LOW 0x00000202L 1527#define DREG_REGID_RSA1_HIGH 0x00000203L 1528#define DREG_REGID_RSA2 0x00000204L 1529#define DREG_REGID_RSA3 0x00000205L 1530#define DREG_REGID_RSI0_LOW 0x00000206L 1531#define DREG_REGID_RSI0_HIGH 0x00000207L 1532#define DREG_REGID_RSI1 0x00000208L 1533#define DREG_REGID_RSI2 0x00000209L 1534#define DREG_REGID_SAGUSTATUS 0x0000020AL 1535#define DREG_REGID_RSCONFIG01_LOW 0x0000020BL 1536#define DREG_REGID_RSCONFIG01_HIGH 0x0000020CL 1537#define DREG_REGID_RSCONFIG23_LOW 0x0000020DL 1538#define DREG_REGID_RSCONFIG23_HIGH 0x0000020EL 1539#define DREG_REGID_RSDMA01E 0x0000020FL 1540#define DREG_REGID_RSDMA23E 0x00000210L 1541#define DREG_REGID_RSD0_LOW 0x00000211L 1542#define DREG_REGID_RSD0_HIGH 0x00000212L 1543#define DREG_REGID_RSD1_LOW 0x00000213L 1544#define DREG_REGID_RSD1_HIGH 0x00000214L 1545#define DREG_REGID_RSD2_LOW 0x00000215L 1546#define DREG_REGID_RSD2_HIGH 0x00000216L 1547#define DREG_REGID_RSD3_LOW 0x00000217L 1548#define DREG_REGID_RSD3_HIGH 0x00000218L 1549#define DREG_REGID_SRAR_HIGH 0x0000021AL 1550#define DREG_REGID_SRAR_LOW 0x0000021BL 1551#define DREG_REGID_DMA_STATE 0x0000021CL 1552#define DREG_REGID_CURRENT_DMA_STREAM 0x0000021DL 1553#define DREG_REGID_NEXT_DMA_STREAM 0x0000021EL 1554#define DREG_REGID_CPU_STATUS 0x00000300L 1555#define DREG_REGID_MAC_MODE 0x00000301L 1556#define DREG_REGID_STACK_AND_REPEAT 0x00000302L 1557#define DREG_REGID_INDEX0 0x00000304L 1558#define DREG_REGID_INDEX1 0x00000305L 1559#define DREG_REGID_DMA_STATE_0_3 0x00000400L 1560#define DREG_REGID_DMA_STATE_4_7 0x00000404L 1561#define DREG_REGID_DMA_STATE_8_11 0x00000408L 1562#define DREG_REGID_DMA_STATE_12_15 0x0000040CL 1563#define DREG_REGID_DMA_STATE_16_19 0x00000410L 1564#define DREG_REGID_DMA_STATE_20_23 0x00000414L 1565#define DREG_REGID_DMA_STATE_24_27 0x00000418L 1566#define DREG_REGID_DMA_STATE_28_31 0x0000041CL 1567#define DREG_REGID_DMA_STATE_32_35 0x00000420L 1568#define DREG_REGID_DMA_STATE_36_39 0x00000424L 1569#define DREG_REGID_DMA_STATE_40_43 0x00000428L 1570#define DREG_REGID_DMA_STATE_44_47 0x0000042CL 1571#define DREG_REGID_DMA_STATE_48_51 0x00000430L 1572#define DREG_REGID_DMA_STATE_52_55 0x00000434L 1573#define DREG_REGID_DMA_STATE_56_59 0x00000438L 1574#define DREG_REGID_DMA_STATE_60_63 0x0000043CL 1575#define DREG_REGID_DMA_STATE_64_67 0x00000440L 1576#define DREG_REGID_DMA_STATE_68_71 0x00000444L 1577#define DREG_REGID_DMA_STATE_72_75 0x00000448L 1578#define DREG_REGID_DMA_STATE_76_79 0x0000044CL 1579#define DREG_REGID_DMA_STATE_80_83 0x00000450L 1580#define DREG_REGID_DMA_STATE_84_87 0x00000454L 1581#define DREG_REGID_DMA_STATE_88_91 0x00000458L 1582#define DREG_REGID_DMA_STATE_92_95 0x0000045CL 1583#define DREG_REGID_TRAP_SELECT 0x00000500L 1584#define DREG_REGID_TRAP_WRITE_0 0x00000500L 1585#define DREG_REGID_TRAP_WRITE_1 0x00000501L 1586#define DREG_REGID_TRAP_WRITE_2 0x00000502L 1587#define DREG_REGID_TRAP_WRITE_3 0x00000503L 1588#define DREG_REGID_TRAP_WRITE_4 0x00000504L 1589#define DREG_REGID_TRAP_WRITE_5 0x00000505L 1590#define DREG_REGID_TRAP_WRITE_6 0x00000506L 1591#define DREG_REGID_TRAP_WRITE_7 0x00000507L 1592#if !defined(NO_CS4612) 1593#if !defined(NO_CS4615) 1594#define DREG_REGID_TRAP_WRITE_8 0x00000510L 1595#define DREG_REGID_TRAP_WRITE_9 0x00000511L 1596#define DREG_REGID_TRAP_WRITE_10 0x00000512L 1597#define DREG_REGID_TRAP_WRITE_11 0x00000513L 1598#define DREG_REGID_TRAP_WRITE_12 0x00000514L 1599#define DREG_REGID_TRAP_WRITE_13 0x00000515L 1600#define DREG_REGID_TRAP_WRITE_14 0x00000516L 1601#define DREG_REGID_TRAP_WRITE_15 0x00000517L 1602#define DREG_REGID_TRAP_WRITE_16 0x00000518L 1603#define DREG_REGID_TRAP_WRITE_17 0x00000519L 1604#define DREG_REGID_TRAP_WRITE_18 0x0000051AL 1605#define DREG_REGID_TRAP_WRITE_19 0x0000051BL 1606#define DREG_REGID_TRAP_WRITE_20 0x0000051CL 1607#define DREG_REGID_TRAP_WRITE_21 0x0000051DL 1608#define DREG_REGID_TRAP_WRITE_22 0x0000051EL 1609#define DREG_REGID_TRAP_WRITE_23 0x0000051FL 1610#endif 1611#endif 1612#define DREG_REGID_MAC0_ACC0_LOW 0x00000600L 1613#define DREG_REGID_MAC0_ACC1_LOW 0x00000601L 1614#define DREG_REGID_MAC0_ACC2_LOW 0x00000602L 1615#define DREG_REGID_MAC0_ACC3_LOW 0x00000603L 1616#define DREG_REGID_MAC1_ACC0_LOW 0x00000604L 1617#define DREG_REGID_MAC1_ACC1_LOW 0x00000605L 1618#define DREG_REGID_MAC1_ACC2_LOW 0x00000606L 1619#define DREG_REGID_MAC1_ACC3_LOW 0x00000607L 1620#define DREG_REGID_MAC0_ACC0_MID 0x00000608L 1621#define DREG_REGID_MAC0_ACC1_MID 0x00000609L 1622#define DREG_REGID_MAC0_ACC2_MID 0x0000060AL 1623#define DREG_REGID_MAC0_ACC3_MID 0x0000060BL 1624#define DREG_REGID_MAC1_ACC0_MID 0x0000060CL 1625#define DREG_REGID_MAC1_ACC1_MID 0x0000060DL 1626#define DREG_REGID_MAC1_ACC2_MID 0x0000060EL 1627#define DREG_REGID_MAC1_ACC3_MID 0x0000060FL 1628#define DREG_REGID_MAC0_ACC0_HIGH 0x00000610L 1629#define DREG_REGID_MAC0_ACC1_HIGH 0x00000611L 1630#define DREG_REGID_MAC0_ACC2_HIGH 0x00000612L 1631#define DREG_REGID_MAC0_ACC3_HIGH 0x00000613L 1632#define DREG_REGID_MAC1_ACC0_HIGH 0x00000614L 1633#define DREG_REGID_MAC1_ACC1_HIGH 0x00000615L 1634#define DREG_REGID_MAC1_ACC2_HIGH 0x00000616L 1635#define DREG_REGID_MAC1_ACC3_HIGH 0x00000617L 1636#define DREG_REGID_RSHOUT_LOW 0x00000620L 1637#define DREG_REGID_RSHOUT_MID 0x00000628L 1638#define DREG_REGID_RSHOUT_HIGH 0x00000630L 1639 1640/***************************************************************************** 1641 * 1642 * The following defines are for the flags in the DMA stream requestor write 1643 * port register. 1644 * 1645 *****************************************************************************/ 1646#define DSRWP_DSR_MASK 0x0000000FL 1647#define DSRWP_DSR_BG_RQ 0x00000001L 1648#define DSRWP_DSR_PRIORITY_MASK 0x00000006L 1649#define DSRWP_DSR_PRIORITY_0 0x00000000L 1650#define DSRWP_DSR_PRIORITY_1 0x00000002L 1651#define DSRWP_DSR_PRIORITY_2 0x00000004L 1652#define DSRWP_DSR_PRIORITY_3 0x00000006L 1653#define DSRWP_DSR_RQ_PENDING 0x00000008L 1654 1655/***************************************************************************** 1656 * 1657 * The following defines are for the flags in the trap write port register. 1658 * 1659 *****************************************************************************/ 1660#define TWPR_TW_MASK 0x0000FFFFL 1661#define TWPR_TW_SHIFT 0L 1662 1663/***************************************************************************** 1664 * 1665 * The following defines are for the flags in the stack pointer write 1666 * register. 1667 * 1668 *****************************************************************************/ 1669#define SPWR_STKP_MASK 0x0000000FL 1670#define SPWR_STKP_SHIFT 0L 1671 1672/***************************************************************************** 1673 * 1674 * The following defines are for the flags in the SP interrupt register. 1675 * 1676 *****************************************************************************/ 1677#define SPIR_FRI 0x00000001L 1678#define SPIR_DOI 0x00000002L 1679#define SPIR_GPI2 0x00000004L 1680#define SPIR_GPI3 0x00000008L 1681#define SPIR_IP0 0x00000010L 1682#define SPIR_IP1 0x00000020L 1683#define SPIR_IP2 0x00000040L 1684#define SPIR_IP3 0x00000080L 1685 1686/***************************************************************************** 1687 * 1688 * The following defines are for the flags in the functional group 1 register. 1689 * 1690 *****************************************************************************/ 1691#define FGR1_F1S_MASK 0x0000FFFFL 1692#define FGR1_F1S_SHIFT 0L 1693 1694/***************************************************************************** 1695 * 1696 * The following defines are for the flags in the SP clock status register. 1697 * 1698 *****************************************************************************/ 1699#define SPCS_FRI 0x00000001L 1700#define SPCS_DOI 0x00000002L 1701#define SPCS_GPI2 0x00000004L 1702#define SPCS_GPI3 0x00000008L 1703#define SPCS_IP0 0x00000010L 1704#define SPCS_IP1 0x00000020L 1705#define SPCS_IP2 0x00000040L 1706#define SPCS_IP3 0x00000080L 1707#define SPCS_SPRUN 0x00000100L 1708#define SPCS_SLEEP 0x00000200L 1709#define SPCS_FG 0x00000400L 1710#define SPCS_ORUN 0x00000800L 1711#define SPCS_IRQ 0x00001000L 1712#define SPCS_FGN_MASK 0x0000E000L 1713#define SPCS_FGN_SHIFT 13L 1714 1715/***************************************************************************** 1716 * 1717 * The following defines are for the flags in the SP DMA requestor status 1718 * register. 1719 * 1720 *****************************************************************************/ 1721#define SDSR_DCS_MASK 0x000000FFL 1722#define SDSR_DCS_SHIFT 0L 1723#define SDSR_DCS_NONE 0x00000007L 1724 1725/***************************************************************************** 1726 * 1727 * The following defines are for the flags in the frame timer register. 1728 * 1729 *****************************************************************************/ 1730#define FRMT_FTV_MASK 0x0000FFFFL 1731#define FRMT_FTV_SHIFT 0L 1732 1733/***************************************************************************** 1734 * 1735 * The following defines are for the flags in the frame timer current count 1736 * register. 1737 * 1738 *****************************************************************************/ 1739#define FRCC_FCC_MASK 0x0000FFFFL 1740#define FRCC_FCC_SHIFT 0L 1741 1742/***************************************************************************** 1743 * 1744 * The following defines are for the flags in the frame timer save count 1745 * register. 1746 * 1747 *****************************************************************************/ 1748#define FRSC_FCS_MASK 0x0000FFFFL 1749#define FRSC_FCS_SHIFT 0L 1750 1751/***************************************************************************** 1752 * 1753 * The following define the various flags stored in the scatter/gather 1754 * descriptors. 1755 * 1756 *****************************************************************************/ 1757#define DMA_SG_NEXT_ENTRY_MASK 0x00000FF8L 1758#define DMA_SG_SAMPLE_END_MASK 0x0FFF0000L 1759#define DMA_SG_SAMPLE_END_FLAG 0x10000000L 1760#define DMA_SG_LOOP_END_FLAG 0x20000000L 1761#define DMA_SG_SIGNAL_END_FLAG 0x40000000L 1762#define DMA_SG_SIGNAL_PAGE_FLAG 0x80000000L 1763#define DMA_SG_NEXT_ENTRY_SHIFT 3L 1764#define DMA_SG_SAMPLE_END_SHIFT 16L 1765 1766/***************************************************************************** 1767 * 1768 * The following define the offsets of the fields within the on-chip generic 1769 * DMA requestor. 1770 * 1771 *****************************************************************************/ 1772#define DMA_RQ_CONTROL1 0x00000000L 1773#define DMA_RQ_CONTROL2 0x00000004L 1774#define DMA_RQ_SOURCE_ADDR 0x00000008L 1775#define DMA_RQ_DESTINATION_ADDR 0x0000000CL 1776#define DMA_RQ_NEXT_PAGE_ADDR 0x00000010L 1777#define DMA_RQ_NEXT_PAGE_SGDESC 0x00000014L 1778#define DMA_RQ_LOOP_START_ADDR 0x00000018L 1779#define DMA_RQ_POST_LOOP_ADDR 0x0000001CL 1780#define DMA_RQ_PAGE_MAP_ADDR 0x00000020L 1781 1782/***************************************************************************** 1783 * 1784 * The following defines are for the flags in the first control word of the 1785 * on-chip generic DMA requestor. 1786 * 1787 *****************************************************************************/ 1788#define DMA_RQ_C1_COUNT_MASK 0x000003FFL 1789#define DMA_RQ_C1_DESTINATION_SCATTER 0x00001000L 1790#define DMA_RQ_C1_SOURCE_GATHER 0x00002000L 1791#define DMA_RQ_C1_DONE_FLAG 0x00004000L 1792#define DMA_RQ_C1_OPTIMIZE_STATE 0x00008000L 1793#define DMA_RQ_C1_SAMPLE_END_STATE_MASK 0x00030000L 1794#define DMA_RQ_C1_FULL_PAGE 0x00000000L 1795#define DMA_RQ_C1_BEFORE_SAMPLE_END 0x00010000L 1796#define DMA_RQ_C1_PAGE_MAP_ERROR 0x00020000L 1797#define DMA_RQ_C1_AT_SAMPLE_END 0x00030000L 1798#define DMA_RQ_C1_LOOP_END_STATE_MASK 0x000C0000L 1799#define DMA_RQ_C1_NOT_LOOP_END 0x00000000L 1800#define DMA_RQ_C1_BEFORE_LOOP_END 0x00040000L 1801#define DMA_RQ_C1_2PAGE_LOOP_BEGIN 0x00080000L 1802#define DMA_RQ_C1_LOOP_BEGIN 0x000C0000L 1803#define DMA_RQ_C1_PAGE_MAP_MASK 0x00300000L 1804#define DMA_RQ_C1_PM_NONE_PENDING 0x00000000L 1805#define DMA_RQ_C1_PM_NEXT_PENDING 0x00100000L 1806#define DMA_RQ_C1_PM_RESERVED 0x00200000L 1807#define DMA_RQ_C1_PM_LOOP_NEXT_PENDING 0x00300000L 1808#define DMA_RQ_C1_WRITEBACK_DEST_FLAG 0x00400000L 1809#define DMA_RQ_C1_WRITEBACK_SRC_FLAG 0x00800000L 1810#define DMA_RQ_C1_DEST_SIZE_MASK 0x07000000L 1811#define DMA_RQ_C1_DEST_LINEAR 0x00000000L 1812#define DMA_RQ_C1_DEST_MOD16 0x01000000L 1813#define DMA_RQ_C1_DEST_MOD32 0x02000000L 1814#define DMA_RQ_C1_DEST_MOD64 0x03000000L 1815#define DMA_RQ_C1_DEST_MOD128 0x04000000L 1816#define DMA_RQ_C1_DEST_MOD256 0x05000000L 1817#define DMA_RQ_C1_DEST_MOD512 0x06000000L 1818#define DMA_RQ_C1_DEST_MOD1024 0x07000000L 1819#define DMA_RQ_C1_DEST_ON_HOST 0x08000000L 1820#define DMA_RQ_C1_SOURCE_SIZE_MASK 0x70000000L 1821#define DMA_RQ_C1_SOURCE_LINEAR 0x00000000L 1822#define DMA_RQ_C1_SOURCE_MOD16 0x10000000L 1823#define DMA_RQ_C1_SOURCE_MOD32 0x20000000L 1824#define DMA_RQ_C1_SOURCE_MOD64 0x30000000L 1825#define DMA_RQ_C1_SOURCE_MOD128 0x40000000L 1826#define DMA_RQ_C1_SOURCE_MOD256 0x50000000L 1827#define DMA_RQ_C1_SOURCE_MOD512 0x60000000L 1828#define DMA_RQ_C1_SOURCE_MOD1024 0x70000000L 1829#define DMA_RQ_C1_SOURCE_ON_HOST 0x80000000L 1830#define DMA_RQ_C1_COUNT_SHIFT 0L 1831 1832/***************************************************************************** 1833 * 1834 * The following defines are for the flags in the second control word of the 1835 * on-chip generic DMA requestor. 1836 * 1837 *****************************************************************************/ 1838#define DMA_RQ_C2_VIRTUAL_CHANNEL_MASK 0x0000003FL 1839#define DMA_RQ_C2_VIRTUAL_SIGNAL_MASK 0x00000300L 1840#define DMA_RQ_C2_NO_VIRTUAL_SIGNAL 0x00000000L 1841#define DMA_RQ_C2_SIGNAL_EVERY_DMA 0x00000100L 1842#define DMA_RQ_C2_SIGNAL_SOURCE_PINGPONG 0x00000200L 1843#define DMA_RQ_C2_SIGNAL_DEST_PINGPONG 0x00000300L 1844#define DMA_RQ_C2_AUDIO_CONVERT_MASK 0x0000F000L 1845#define DMA_RQ_C2_AC_NONE 0x00000000L 1846#define DMA_RQ_C2_AC_8_TO_16_BIT 0x00001000L 1847#define DMA_RQ_C2_AC_MONO_TO_STEREO 0x00002000L 1848#define DMA_RQ_C2_AC_ENDIAN_CONVERT 0x00004000L 1849#define DMA_RQ_C2_AC_SIGNED_CONVERT 0x00008000L 1850#define DMA_RQ_C2_LOOP_END_MASK 0x0FFF0000L 1851#define DMA_RQ_C2_LOOP_MASK 0x30000000L 1852#define DMA_RQ_C2_NO_LOOP 0x00000000L 1853#define DMA_RQ_C2_ONE_PAGE_LOOP 0x10000000L 1854#define DMA_RQ_C2_TWO_PAGE_LOOP 0x20000000L 1855#define DMA_RQ_C2_MULTI_PAGE_LOOP 0x30000000L 1856#define DMA_RQ_C2_SIGNAL_LOOP_BACK 0x40000000L 1857#define DMA_RQ_C2_SIGNAL_POST_BEGIN_PAGE 0x80000000L 1858#define DMA_RQ_C2_VIRTUAL_CHANNEL_SHIFT 0L 1859#define DMA_RQ_C2_LOOP_END_SHIFT 16L 1860 1861/***************************************************************************** 1862 * 1863 * The following defines are for the flags in the source and destination words 1864 * of the on-chip generic DMA requestor. 1865 * 1866 *****************************************************************************/ 1867#define DMA_RQ_SD_ADDRESS_MASK 0x0000FFFFL 1868#define DMA_RQ_SD_MEMORY_ID_MASK 0x000F0000L 1869#define DMA_RQ_SD_SP_PARAM_ADDR 0x00000000L 1870#define DMA_RQ_SD_SP_SAMPLE_ADDR 0x00010000L 1871#define DMA_RQ_SD_SP_PROGRAM_ADDR 0x00020000L 1872#define DMA_RQ_SD_SP_DEBUG_ADDR 0x00030000L 1873#define DMA_RQ_SD_OMNIMEM_ADDR 0x000E0000L 1874#define DMA_RQ_SD_END_FLAG 0x40000000L 1875#define DMA_RQ_SD_ERROR_FLAG 0x80000000L 1876#define DMA_RQ_SD_ADDRESS_SHIFT 0L 1877 1878/***************************************************************************** 1879 * 1880 * The following defines are for the flags in the page map address word of the 1881 * on-chip generic DMA requestor. 1882 * 1883 *****************************************************************************/ 1884#define DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_MASK 0x00000FF8L 1885#define DMA_RQ_PMA_PAGE_TABLE_MASK 0xFFFFF000L 1886#define DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_SHIFT 3L 1887#define DMA_RQ_PMA_PAGE_TABLE_SHIFT 12L 1888 1889/***************************************************************************** 1890 * 1891 * The following defines are for the flags in the rsConfig01/23 registers of 1892 * the SP. 1893 * 1894 *****************************************************************************/ 1895#define RSCONFIG_MODULO_SIZE_MASK 0x0000000FL 1896#define RSCONFIG_MODULO_16 0x00000001L 1897#define RSCONFIG_MODULO_32 0x00000002L 1898#define RSCONFIG_MODULO_64 0x00000003L 1899#define RSCONFIG_MODULO_128 0x00000004L 1900#define RSCONFIG_MODULO_256 0x00000005L 1901#define RSCONFIG_MODULO_512 0x00000006L 1902#define RSCONFIG_MODULO_1024 0x00000007L 1903#define RSCONFIG_MODULO_4 0x00000008L 1904#define RSCONFIG_MODULO_8 0x00000009L 1905#define RSCONFIG_SAMPLE_SIZE_MASK 0x000000C0L 1906#define RSCONFIG_SAMPLE_8MONO 0x00000000L 1907#define RSCONFIG_SAMPLE_8STEREO 0x00000040L 1908#define RSCONFIG_SAMPLE_16MONO 0x00000080L 1909#define RSCONFIG_SAMPLE_16STEREO 0x000000C0L 1910#define RSCONFIG_UNDERRUN_ZERO 0x00004000L 1911#define RSCONFIG_DMA_TO_HOST 0x00008000L 1912#define RSCONFIG_STREAM_NUM_MASK 0x00FF0000L 1913#define RSCONFIG_MAX_DMA_SIZE_MASK 0x1F000000L 1914#define RSCONFIG_DMA_ENABLE 0x20000000L 1915#define RSCONFIG_PRIORITY_MASK 0xC0000000L 1916#define RSCONFIG_PRIORITY_HIGH 0x00000000L 1917#define RSCONFIG_PRIORITY_MEDIUM_HIGH 0x40000000L 1918#define RSCONFIG_PRIORITY_MEDIUM_LOW 0x80000000L 1919#define RSCONFIG_PRIORITY_LOW 0xC0000000L 1920#define RSCONFIG_STREAM_NUM_SHIFT 16L 1921#define RSCONFIG_MAX_DMA_SIZE_SHIFT 24L 1922 1923#define BA1_VARIDEC_BUF_1 0x000 1924 1925#define BA1_PDTC 0x0c0 /* BA1_PLAY_DMA_TRANSACTION_COUNT_REG */ 1926#define BA1_PFIE 0x0c4 /* BA1_PLAY_FORMAT_&_INTERRUPT_ENABLE_REG */ 1927#define BA1_PBA 0x0c8 /* BA1_PLAY_BUFFER_ADDRESS */ 1928#define BA1_PVOL 0x0f8 /* BA1_PLAY_VOLUME_REG */ 1929#define BA1_PSRC 0x288 /* BA1_PLAY_SAMPLE_RATE_CORRECTION_REG */ 1930#define BA1_PCTL 0x2a4 /* BA1_PLAY_CONTROL_REG */ 1931#define BA1_PPI 0x2b4 /* BA1_PLAY_PHASE_INCREMENT_REG */ 1932 1933#define BA1_CCTL 0x064 /* BA1_CAPTURE_CONTROL_REG */ 1934#define BA1_CIE 0x104 /* BA1_CAPTURE_INTERRUPT_ENABLE_REG */ 1935#define BA1_CBA 0x10c /* BA1_CAPTURE_BUFFER_ADDRESS */ 1936#define BA1_CSRC 0x2c8 /* BA1_CAPTURE_SAMPLE_RATE_CORRECTION_REG */ 1937#define BA1_CCI 0x2d8 /* BA1_CAPTURE_COEFFICIENT_INCREMENT_REG */ 1938#define BA1_CD 0x2e0 /* BA1_CAPTURE_DELAY_REG */ 1939#define BA1_CPI 0x2f4 /* BA1_CAPTURE_PHASE_INCREMENT_REG */ 1940#define BA1_CVOL 0x2f8 /* BA1_CAPTURE_VOLUME_REG */ 1941 1942#define BA1_CFG1 0x134 /* BA1_CAPTURE_FRAME_GROUP_1_REG */ 1943#define BA1_CFG2 0x138 /* BA1_CAPTURE_FRAME_GROUP_2_REG */ 1944#define BA1_CCST 0x13c /* BA1_CAPTURE_CONSTANT_REG */ 1945#define BA1_CSPB 0x340 /* BA1_CAPTURE_SPB_ADDRESS */ 1946 1947/* The following struct holds the initialization array. */ 1948 1949/* 1950 * this is 3*1024 for parameter, 3.5*1024 for sample and 2*3.5*1024 for code since 1951 * each instruction is 40 bits and takes two dwords 1952 */ 1953#define INKY_BA1_DWORD_SIZE (13 * 1024 + 512) 1954#define INKY_MEMORY_COUNT 3 1955 1956struct BA1struct 1957{ 1958 struct 1959 { 1960 u_long ulDestByteOffset, 1961 ulSourceByteSize; 1962 } MemoryStat[INKY_MEMORY_COUNT]; 1963 1964 u_long BA1Array[INKY_BA1_DWORD_SIZE]; 1965}; 1966 1967#endif /* _CSA_REG_H */ 1968