cs4281.c revision 72017 
1/*
2 * Copyright (c) 2000 Orion Hodson <O.Hodson@cs.ucl.ac.uk>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/dev/sound/pci/cs4281.c 72017 2001-02-04 19:23:35Z cg $
27 *
28 * The order of pokes in the initiation sequence is based on Linux
29 * driver by Thomas Sailer, gw boynton (wesb@crystal.cirrus.com), tom
30 * woller (twoller@crystal.cirrus.com).  */
31
32#include <dev/sound/pcm/sound.h>
33#include <dev/sound/pcm/ac97.h>
34
35#include <pci/pcireg.h>
36#include <pci/pcivar.h>
37
38#include <dev/sound/pci/cs4281.h>
39
40#define CS4281_BUFFER_SIZE 16384
41
42/* Max fifo size for full duplex is 64 */
43#define CS4281_FIFO_SIZE 15
44
45/* DMA Engine Indices */
46#define CS4281_DMA_PLAY 0
47#define CS4281_DMA_REC  1
48
49/* Misc */
50
51#define MIN(x,y) (x) < (y) ? (x) : (y)
52#define MAX(x,y) (x) > (y) ? (x) : (y)
53
54#define inline __inline
55
56#ifndef DEB
57#define DEB(x) /* x */
58#endif /* DEB */
59
60/* ------------------------------------------------------------------------- */
61/* Structures */
62
63struct sc_info;
64
65/* channel registers */
66struct sc_chinfo {
67    struct sc_info *parent;
68
69    snd_dbuf *buffer;
70    pcm_channel *channel;
71
72    u_int32_t spd, fmt, bps;
73    int       dma_setup, dma_chan;
74};
75
76/* device private data */
77struct sc_info {
78    device_t dev;
79    u_int32_t type;
80
81    bus_space_tag_t st;
82    bus_space_handle_t sh;
83    bus_dma_tag_t parent_dmat;
84
85    struct resource *reg, *irq, *mem;
86    int regtype, regid, irqid, memid;
87    void *ih;
88
89    int power;
90    struct sc_chinfo pch;
91    struct sc_chinfo rch;
92};
93
94/* -------------------------------------------------------------------- */
95/* prototypes */
96
97/* ADC/DAC control */
98static u_int32_t adcdac_go(struct sc_chinfo *ch, u_int32_t go);
99static void      adcdac_prog(struct sc_chinfo *ch);
100
101/* stuff */
102static void      cs4281_intr(void *);
103static int       cs4281_power(struct sc_info *, int);
104static int       cs4281_init(struct sc_info *);
105static int       cs4281_uninit(struct sc_info *);
106static int       cs4281_reinit(struct sc_info *);
107
108/* talk to the card */
109static u_int32_t cs4281_rd(struct sc_info *, int);
110static void 	 cs4281_wr(struct sc_info *, int, u_int32_t);
111
112/* misc */
113static u_int8_t  cs4281_rate_to_rv(u_int32_t);
114static u_int32_t cs4281_format_to_dmr(u_int32_t);
115static u_int32_t cs4281_format_to_bps(u_int32_t);
116
117/* -------------------------------------------------------------------- */
118/* formats (do not add formats without editing cs_fmt_tab)              */
119
120static u_int32_t cs4281_fmts[] = {
121    AFMT_U8,
122    AFMT_U8 | AFMT_STEREO,
123    AFMT_S8,
124    AFMT_S8 | AFMT_STEREO,
125    AFMT_S16_LE,
126    AFMT_S16_LE | AFMT_STEREO,
127    AFMT_U16_LE,
128    AFMT_U16_LE | AFMT_STEREO,
129    AFMT_S16_BE,
130    AFMT_S16_BE | AFMT_STEREO,
131    AFMT_U16_BE,
132    AFMT_U16_BE | AFMT_STEREO,
133    0
134};
135
136static pcmchan_caps cs4281_caps = {6024, 48000, cs4281_fmts, 0};
137
138/* -------------------------------------------------------------------- */
139/* Hardware */
140
141static inline u_int32_t
142cs4281_rd(struct sc_info *sc, int regno)
143{
144    return bus_space_read_4(sc->st, sc->sh, regno);
145}
146
147static inline void
148cs4281_wr(struct sc_info *sc, int regno, u_int32_t data)
149{
150    bus_space_write_4(sc->st, sc->sh, regno, data);
151    DELAY(100);
152}
153
154static inline void
155cs4281_clr4(struct sc_info *sc, int regno, u_int32_t mask)
156{
157    u_int32_t r;
158    r = cs4281_rd(sc, regno);
159    cs4281_wr(sc, regno, r & ~mask);
160}
161
162static inline void
163cs4281_set4(struct sc_info *sc, int regno, u_int32_t mask)
164{
165    u_int32_t v;
166    v = cs4281_rd(sc, regno);
167    cs4281_wr(sc, regno, v | mask);
168}
169
170static int
171cs4281_waitset(struct sc_info *sc, int regno, u_int32_t mask, int tries)
172{
173    u_int32_t v;
174
175    while(tries > 0) {
176	DELAY(100);
177	v = cs4281_rd(sc, regno);
178	if ((v & mask) == mask) break;
179	tries --;
180    }
181    return tries;
182}
183
184static int
185cs4281_waitclr(struct sc_info *sc, int regno, u_int32_t mask, int tries)
186{
187    u_int32_t v;
188
189    while(tries > 0) {
190	DELAY(100);
191	v = ~ cs4281_rd(sc, regno);
192	if (v & mask) break;
193	tries --;
194    }
195    return tries;
196}
197
198/* ------------------------------------------------------------------------- */
199/* Register value mapping functions */
200
201static u_int32_t cs4281_rates[] = {48000, 44100, 22050, 16000, 11025, 8000};
202#define CS4281_NUM_RATES sizeof(cs4281_rates)/sizeof(cs4281_rates[0])
203
204static u_int8_t
205cs4281_rate_to_rv(u_int32_t rate)
206{
207    u_int32_t v;
208
209    for (v = 0; v < CS4281_NUM_RATES; v++) {
210	if (rate == cs4281_rates[v]) return v;
211    }
212
213    v = 1536000 / rate;
214    if (v > 255 || v < 32) v = 5; /* default to 8k */
215    return v;
216}
217
218static u_int32_t
219cs4281_rv_to_rate(u_int8_t rv)
220{
221    u_int32_t r;
222
223    if (rv < CS4281_NUM_RATES) return cs4281_rates[rv];
224    r = 1536000 / rv;
225    return r;
226}
227
228static inline u_int32_t
229cs4281_format_to_dmr(u_int32_t format)
230{
231    u_int32_t dmr = 0;
232    if (AFMT_8BIT & format)      dmr |= CS4281PCI_DMR_SIZE8;
233    if (!(AFMT_STEREO & format)) dmr |= CS4281PCI_DMR_MONO;
234    if (AFMT_BIGENDIAN & format) dmr |= CS4281PCI_DMR_BEND;
235    if (!(AFMT_SIGNED & format)) dmr |= CS4281PCI_DMR_USIGN;
236    return dmr;
237}
238
239static inline u_int32_t
240cs4281_format_to_bps(u_int32_t format)
241{
242    return ((AFMT_8BIT & format) ? 1 : 2) * ((AFMT_STEREO & format) ? 2 : 1);
243}
244
245/* -------------------------------------------------------------------- */
246/* ac97 codec */
247
248static u_int32_t
249cs4281_rdcd(kobj_t obj, void *devinfo, int regno)
250{
251    struct sc_info *sc = (struct sc_info *)devinfo;
252    int codecno;
253
254    codecno = regno >> 8;
255    regno &= 0xff;
256
257    /* Remove old state */
258    cs4281_rd(sc, CS4281PCI_ACSDA);
259
260    /* Fill in AC97 register value request form */
261    cs4281_wr(sc, CS4281PCI_ACCAD, regno);
262    cs4281_wr(sc, CS4281PCI_ACCDA, 0);
263    cs4281_wr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_ESYN |
264	      CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_DCV |
265	      CS4281PCI_ACCTL_CRW);
266
267    /* Wait for read to complete */
268    if (cs4281_waitclr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_DCV, 250) == 0) {
269	device_printf(sc->dev, "cs4281_rdcd: DCV did not go\n");
270	return 0xffffffff;
271    }
272
273    /* Wait for valid status */
274    if (cs4281_waitset(sc, CS4281PCI_ACSTS, CS4281PCI_ACSTS_VSTS, 250) == 0) {
275	device_printf(sc->dev,"cs4281_rdcd: VSTS did not come\n");
276	return 0xffffffff;
277    }
278
279    return cs4281_rd(sc, CS4281PCI_ACSDA);
280}
281
282static void
283cs4281_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data)
284{
285    struct sc_info *sc = (struct sc_info *)devinfo;
286    int codecno;
287
288    codecno = regno >> 8;
289    regno &= 0xff;
290
291    cs4281_wr(sc, CS4281PCI_ACCAD, regno);
292    cs4281_wr(sc, CS4281PCI_ACCDA, data);
293    cs4281_wr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_ESYN |
294	      CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_DCV);
295
296    if (cs4281_waitclr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_DCV, 250) == 0) {
297	device_printf(sc->dev,"cs4281_wrcd: DCV did not go\n");
298    }
299}
300
301static kobj_method_t cs4281_ac97_methods[] = {
302        KOBJMETHOD(ac97_read,           cs4281_rdcd),
303        KOBJMETHOD(ac97_write,          cs4281_wrcd),
304        { 0, 0 }
305};
306AC97_DECLARE(cs4281_ac97);
307
308/* ------------------------------------------------------------------------- */
309/* shared rec/play channel interface */
310
311static void *
312cs4281chan_init(kobj_t obj, void *devinfo, snd_dbuf *b, pcm_channel *c, int dir)
313{
314    struct sc_info *sc = devinfo;
315    struct sc_chinfo *ch = (dir == PCMDIR_PLAY) ? &sc->pch : &sc->rch;
316
317    ch->buffer = b;
318    if (sndbuf_alloc(ch->buffer, sc->parent_dmat, CS4281_BUFFER_SIZE) != 0) {
319	return NULL;
320    }
321    ch->parent = sc;
322    ch->channel = c;
323
324    ch->fmt = AFMT_U8;
325    ch->spd = DSP_DEFAULT_SPEED;
326    ch->bps = 1;
327
328    ch->dma_chan = (dir == PCMDIR_PLAY) ? CS4281_DMA_PLAY : CS4281_DMA_REC;
329    ch->dma_setup = 0;
330
331    adcdac_go(ch, 0);
332    adcdac_prog(ch);
333
334    return ch;
335}
336
337static int
338cs4281chan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
339{
340    struct sc_chinfo *ch = data;
341    u_int32_t blksz, go;
342
343    go = adcdac_go(ch, 0);
344
345    /* 2 interrupts are possible and used in buffer (half-empty,empty),
346     * hence factor of 2. */
347    blksz = MIN(blocksize, CS4281_BUFFER_SIZE / 2);
348    sndbuf_resize(ch->buffer, 2, blksz);
349
350    ch->dma_setup = 0;
351    adcdac_prog(ch);
352    adcdac_go(ch, go);
353
354    DEB(printf("cs4281chan_setblocksize: bufsz %d Setting %d\n", blocksize, blksz));
355
356    return sndbuf_getsize(ch->buffer);
357}
358
359static int
360cs4281chan_setspeed(kobj_t obj, void *data, u_int32_t speed)
361{
362    struct sc_chinfo *ch = data;
363    struct sc_info *sc = ch->parent;
364    u_int32_t go, v, r;
365
366    go = adcdac_go(ch, 0); /* pause */
367    r = (ch->dma_chan == CS4281_DMA_PLAY) ? CS4281PCI_DACSR : CS4281PCI_ADCSR;
368    v = cs4281_rate_to_rv(speed);
369    cs4281_wr(sc, r, v);
370    adcdac_go(ch, go); /* unpause */
371
372    ch->spd = cs4281_rv_to_rate(v);
373    return ch->spd;
374}
375
376static int
377cs4281chan_setformat(kobj_t obj, void *data, u_int32_t format)
378{
379    struct sc_chinfo *ch = data;
380    struct sc_info *sc = ch->parent;
381    u_int32_t v, go;
382
383    go = adcdac_go(ch, 0); /* pause */
384
385    if (ch->dma_chan == CS4281_DMA_PLAY)
386	v = CS4281PCI_DMR_TR_PLAY;
387    else
388	v = CS4281PCI_DMR_TR_REC;
389    v |= CS4281PCI_DMR_DMA | CS4281PCI_DMR_AUTO;
390    v |= cs4281_format_to_dmr(format);
391    cs4281_wr(sc, CS4281PCI_DMR(ch->dma_chan), v);
392
393    adcdac_go(ch, go); /* unpause */
394
395    ch->fmt = format;
396    ch->bps = cs4281_format_to_bps(format);
397    ch->dma_setup = 0;
398
399    return 0;
400}
401
402static int
403cs4281chan_getptr(kobj_t obj, void *data)
404{
405    struct sc_chinfo *ch = data;
406    struct sc_info *sc = ch->parent;
407    u_int32_t  dba, dca, ptr;
408    int sz;
409
410    sz  = sndbuf_getsize(ch->buffer);
411    dba = cs4281_rd(sc, CS4281PCI_DBA(ch->dma_chan));
412    dca = cs4281_rd(sc, CS4281PCI_DCA(ch->dma_chan));
413    ptr = (dca - dba + sz) % sz;
414
415    return ptr;
416}
417
418static int
419cs4281chan_trigger(kobj_t obj, void *data, int go)
420{
421    struct sc_chinfo *ch = data;
422
423    switch(go) {
424    case PCMTRIG_START:
425	adcdac_prog(ch);
426	adcdac_go(ch, 1);
427	break;
428    case PCMTRIG_ABORT:
429	adcdac_go(ch, 0);
430	break;
431    default:
432	break;
433    }
434
435    /* return 0 if ok */
436    return 0;
437}
438
439static pcmchan_caps *
440cs4281chan_getcaps(kobj_t obj, void *data)
441{
442    return &cs4281_caps;
443}
444
445static kobj_method_t cs4281chan_methods[] = {
446    	KOBJMETHOD(channel_init,		cs4281chan_init),
447    	KOBJMETHOD(channel_setformat,		cs4281chan_setformat),
448    	KOBJMETHOD(channel_setspeed,		cs4281chan_setspeed),
449    	KOBJMETHOD(channel_setblocksize,	cs4281chan_setblocksize),
450    	KOBJMETHOD(channel_trigger,		cs4281chan_trigger),
451    	KOBJMETHOD(channel_getptr,		cs4281chan_getptr),
452    	KOBJMETHOD(channel_getcaps,		cs4281chan_getcaps),
453	{ 0, 0 }
454};
455CHANNEL_DECLARE(cs4281chan);
456
457/* -------------------------------------------------------------------- */
458/* ADC/DAC control */
459
460/* adcdac_go enables/disable DMA channel, returns non-zero if DMA was
461 * active before call */
462
463static u_int32_t
464adcdac_go(struct sc_chinfo *ch, u_int32_t go)
465{
466    struct sc_info *sc = ch->parent;
467    u_int32_t going;
468
469    going = !(cs4281_rd(sc, CS4281PCI_DCR(ch->dma_chan)) & CS4281PCI_DCR_MSK);
470
471    if (go)
472	cs4281_clr4(sc, CS4281PCI_DCR(ch->dma_chan), CS4281PCI_DCR_MSK);
473    else
474	cs4281_set4(sc, CS4281PCI_DCR(ch->dma_chan), CS4281PCI_DCR_MSK);
475
476    cs4281_wr(sc, CS4281PCI_HICR, CS4281PCI_HICR_EOI);
477
478    return going;
479}
480
481static void
482adcdac_prog(struct sc_chinfo *ch)
483{
484    struct sc_info *sc = ch->parent;
485    u_int32_t go;
486
487    if (!ch->dma_setup) {
488	go = adcdac_go(ch, 0);
489	cs4281_wr(sc, CS4281PCI_DBA(ch->dma_chan),
490		  vtophys(sndbuf_getbuf(ch->buffer)));
491	cs4281_wr(sc, CS4281PCI_DBC(ch->dma_chan),
492		  sndbuf_getsize(ch->buffer) / ch->bps - 1);
493	ch->dma_setup = 1;
494	adcdac_go(ch, go);
495    }
496}
497
498/* -------------------------------------------------------------------- */
499/* The interrupt handler */
500
501static void
502cs4281_intr(void *p)
503{
504    struct sc_info *sc = (struct sc_info *)p;
505    u_int32_t hisr;
506
507    hisr = cs4281_rd(sc, CS4281PCI_HISR);
508
509    if (hisr == 0) return;
510
511    if (hisr & CS4281PCI_HISR_DMA(CS4281_DMA_PLAY)) {
512	chn_intr(sc->pch.channel);
513	cs4281_rd(sc, CS4281PCI_HDSR(CS4281_DMA_PLAY)); /* Clear interrupt */
514    }
515
516    if (hisr & CS4281PCI_HISR_DMA(CS4281_DMA_REC)) {
517	chn_intr(sc->rch.channel);
518	cs4281_rd(sc, CS4281PCI_HDSR(CS4281_DMA_REC)); /* Clear interrupt */
519    }
520
521    /* Signal End-of-Interrupt */
522    cs4281_wr(sc, CS4281PCI_HICR, CS4281PCI_HICR_EOI);
523}
524
525/* -------------------------------------------------------------------- */
526/* stuff */
527
528static int
529cs4281_power(struct sc_info *sc, int state)
530{
531    switch (state) {
532    case 0: /* full power */
533        break;
534    case 1:
535    case 2:
536    case 3: /* power off */
537        break;
538    }
539    sc->power = state;
540
541    return 0;
542}
543
544static int
545cs4281_init(struct sc_info *sc)
546{
547    u_int32_t i, v;
548
549    /* Permit r/w access to all BA0 registers */
550    cs4281_wr(sc, CS4281PCI_CWPR, CS4281PCI_CWPR_MAGIC);
551
552    /* (0) Blast clock register and serial port */
553    cs4281_wr(sc, CS4281PCI_CLKCR1, 0);
554    cs4281_wr(sc, CS4281PCI_SERMC,  0);
555
556    /* (1) Make ESYN 0 to turn sync pulse on AC97 link */
557    cs4281_wr(sc, CS4281PCI_ACCTL, 0);
558    DELAY(50);
559
560    /* (2) Effect Reset */
561    cs4281_wr(sc, CS4281PCI_SPMC, 0);
562    DELAY(100);
563    cs4281_wr(sc, CS4281PCI_SPMC, CS4281PCI_SPMC_RSTN);
564    /* Wait 50ms for ABITCLK to become stable */
565    DELAY(50000);
566
567    /* (3) Enable Sound System Clocks */
568    cs4281_wr(sc, CS4281PCI_CLKCR1, CS4281PCI_CLKCR1_DLLP);
569    DELAY(50000); /* Wait for PLL to stabilize */
570    cs4281_wr(sc, CS4281PCI_CLKCR1,
571	      CS4281PCI_CLKCR1_DLLP | CS4281PCI_CLKCR1_SWCE);
572
573    /* (4) Power Up - this combination is essential. */
574    cs4281_set4(sc, CS4281PCI_SSPM,
575		CS4281PCI_SSPM_ACLEN | CS4281PCI_SSPM_PSRCEN |
576		CS4281PCI_SSPM_CSRCEN | CS4281PCI_SSPM_MIXEN);
577
578    /* (5) Wait for clock stabilization */
579    if (cs4281_waitset(sc,
580		       CS4281PCI_CLKCR1,
581		       CS4281PCI_CLKCR1_DLLRDY,
582		       250) == 0) {
583	device_printf(sc->dev, "Clock stabilization failed\n");
584	return -1;
585    }
586
587    /* (6) Enable ASYNC generation. */
588    cs4281_wr(sc, CS4281PCI_ACCTL,CS4281PCI_ACCTL_ESYN);
589
590    /* Wait to allow AC97 to start generating clock bit */
591    DELAY(50000);
592
593    /* Set AC97 timing */
594    cs4281_wr(sc, CS4281PCI_SERMC, CS4281PCI_SERMC_PTC_AC97);
595
596    /* (7) Wait for AC97 ready signal */
597    if (cs4281_waitset(sc, CS4281PCI_ACSTS, CS4281PCI_ACSTS_CRDY, 250) == 0) {
598	device_printf(sc->dev, "codec did not avail\n");
599	return -1;
600    }
601
602    /* (8) Assert valid frame signal to begin sending commands to
603     *     AC97 codec */
604    cs4281_wr(sc,
605	      CS4281PCI_ACCTL,
606	      CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_ESYN);
607
608    /* (9) Wait for codec calibration */
609    for(i = 0 ; i < 1000; i++) {
610	DELAY(10000);
611	v = cs4281_rdcd(0, sc, AC97_REG_POWER);
612	if ((v & 0x0f) == 0x0f) {
613	    break;
614	}
615    }
616    if (i == 1000) {
617	device_printf(sc->dev, "codec failed to calibrate\n");
618	return -1;
619    }
620
621    /* (10) Set AC97 timing */
622    cs4281_wr(sc, CS4281PCI_SERMC, CS4281PCI_SERMC_PTC_AC97);
623
624    /* (11) Wait for valid data to arrive */
625    if (cs4281_waitset(sc,
626		       CS4281PCI_ACISV,
627		       CS4281PCI_ACISV_ISV(3) | CS4281PCI_ACISV_ISV(4),
628		       10000) == 0) {
629	device_printf(sc->dev, "cs4281 never got valid data\n");
630	return -1;
631    }
632
633    /* (12) Start digital data transfer of audio data to codec */
634    cs4281_wr(sc,
635	      CS4281PCI_ACOSV,
636	      CS4281PCI_ACOSV_SLV(3) | CS4281PCI_ACOSV_SLV(4));
637
638    /* Set Master and headphone to max */
639    cs4281_wrcd(0, sc, AC97_MIX_PHONES, 0);
640    cs4281_wrcd(0, sc, AC97_MIX_MASTER, 0);
641
642    /* Power on the DAC */
643    v = cs4281_rdcd(0, sc, AC97_REG_POWER) & 0xfdff;
644    cs4281_wrcd(0, sc, AC97_REG_POWER, v);
645
646    /* Wait until DAC state ready */
647    for(i = 0; i < 320; i++) {
648	DELAY(100);
649	v = cs4281_rdcd(0, sc, AC97_REG_POWER);
650	if (v & 0x02) break;
651    }
652
653    /* Power on the ADC */
654    v = cs4281_rdcd(0, sc, AC97_REG_POWER) & 0xfeff;
655    cs4281_wrcd(0, sc, AC97_REG_POWER, v);
656
657    /* Wait until ADC state ready */
658    for(i = 0; i < 320; i++) {
659	DELAY(100);
660	v = cs4281_rdcd(0, sc, AC97_REG_POWER);
661	if (v & 0x01) break;
662    }
663
664    /* FIFO configuration (driver is DMA orientated, implicit FIFO) */
665    /* Play FIFO */
666
667    v = CS4281PCI_FCR_RS(CS4281PCI_RPCM_PLAY_SLOT) |
668	CS4281PCI_FCR_LS(CS4281PCI_LPCM_PLAY_SLOT) |
669	CS4281PCI_FCR_SZ(CS4281_FIFO_SIZE)|
670	CS4281PCI_FCR_OF(0);
671    cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_PLAY), v);
672
673    cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_PLAY), v | CS4281PCI_FCR_FEN);
674
675    /* Record FIFO */
676    v = CS4281PCI_FCR_RS(CS4281PCI_RPCM_REC_SLOT) |
677	CS4281PCI_FCR_LS(CS4281PCI_LPCM_REC_SLOT) |
678	CS4281PCI_FCR_SZ(CS4281_FIFO_SIZE)|
679	CS4281PCI_FCR_OF(CS4281_FIFO_SIZE + 1);
680    cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_REC), v | CS4281PCI_FCR_PSH);
681    cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_REC), v | CS4281PCI_FCR_FEN);
682
683    /* Match AC97 slots to FIFOs */
684    v = CS4281PCI_SRCSA_PLSS(CS4281PCI_LPCM_PLAY_SLOT) |
685	CS4281PCI_SRCSA_PRSS(CS4281PCI_RPCM_PLAY_SLOT) |
686	CS4281PCI_SRCSA_CLSS(CS4281PCI_LPCM_REC_SLOT) |
687	CS4281PCI_SRCSA_CRSS(CS4281PCI_RPCM_REC_SLOT);
688    cs4281_wr(sc, CS4281PCI_SRCSA, v);
689
690    /* Set Auto-Initialize and set directions */
691    cs4281_wr(sc,
692	      CS4281PCI_DMR(CS4281_DMA_PLAY),
693	      CS4281PCI_DMR_DMA  |
694	      CS4281PCI_DMR_AUTO |
695	      CS4281PCI_DMR_TR_PLAY);
696    cs4281_wr(sc,
697	      CS4281PCI_DMR(CS4281_DMA_REC),
698	      CS4281PCI_DMR_DMA  |
699	      CS4281PCI_DMR_AUTO |
700	      CS4281PCI_DMR_TR_REC);
701
702    /* Enable half and empty buffer interrupts keeping DMA paused */
703    cs4281_wr(sc,
704	      CS4281PCI_DCR(CS4281_DMA_PLAY),
705	      CS4281PCI_DCR_TCIE | CS4281PCI_DCR_HTCIE | CS4281PCI_DCR_MSK);
706    cs4281_wr(sc,
707	      CS4281PCI_DCR(CS4281_DMA_REC),
708	      CS4281PCI_DCR_TCIE | CS4281PCI_DCR_HTCIE | CS4281PCI_DCR_MSK);
709
710    /* Enable Interrupts */
711    cs4281_clr4(sc,
712		CS4281PCI_HIMR,
713		CS4281PCI_HIMR_DMAI |
714		CS4281PCI_HIMR_DMA(CS4281_DMA_PLAY) |
715		CS4281PCI_HIMR_DMA(CS4281_DMA_REC));
716
717    /* Set playback volume */
718    cs4281_wr(sc, CS4281PCI_PPLVC, 7);
719    cs4281_wr(sc, CS4281PCI_PPRVC, 7);
720
721    return 0;
722}
723
724static int
725cs4281_uninit(struct sc_info *sc)
726{
727    return -1;
728}
729
730static int
731cs4281_reinit(struct sc_info *sc)
732{
733    return -1;
734}
735
736/* -------------------------------------------------------------------- */
737/* Probe and attach the card */
738
739static int
740cs4281_pci_probe(device_t dev)
741{
742    char *s = NULL;
743
744    switch (pci_get_devid(dev)) {
745    case CS4281_PCI_ID:
746	s = "Crystal Semiconductor CS4281";
747	break;
748    }
749
750    if (s)
751	device_set_desc(dev, s);
752    return s? 0 : ENXIO;
753}
754
755static int
756cs4281_pci_attach(device_t dev)
757{
758    struct sc_info *sc;
759    struct ac97_info *codec = NULL;
760    u_int32_t data;
761    char status[SND_STATUSLEN];
762
763    if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT)) == NULL) {
764	device_printf(dev, "cannot allocate softc\n");
765	return ENXIO;
766    }
767
768    bzero(sc, sizeof(*sc));
769    sc->dev = dev;
770    sc->type = pci_get_devid(dev);
771
772    data = pci_read_config(dev, PCIR_COMMAND, 2);
773    data |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
774    pci_write_config(dev, PCIR_COMMAND, data, 2);
775
776    data = pci_read_config(dev, PCIR_COMMAND, 2);
777
778    sc->regid   = PCIR_MAPS;
779    sc->regtype = SYS_RES_MEMORY;
780    sc->reg = bus_alloc_resource(dev, sc->regtype, &sc->regid,
781				 0, ~0, CS4281PCI_BA0_SIZE, RF_ACTIVE);
782    if (!sc->reg) {
783	sc->regtype = SYS_RES_IOPORT;
784	sc->reg = bus_alloc_resource(dev, sc->regtype, &sc->regid,
785				     0, ~0, CS4281PCI_BA0_SIZE, RF_ACTIVE);
786	if (!sc->reg) {
787	    device_printf(dev, "unable to allocate register space\n");
788	    goto bad;
789	}
790    }
791    sc->st = rman_get_bustag(sc->reg);
792    sc->sh = rman_get_bushandle(sc->reg);
793
794    sc->memid = PCIR_MAPS + 4;
795    sc->mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &sc->memid, 0,
796				 ~0, CS4281PCI_BA1_SIZE, RF_ACTIVE);
797    if (sc->mem == NULL) {
798	device_printf(dev, "unable to allocate fifo space\n");
799	goto bad;
800    }
801
802    sc->irqid = 0;
803    sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irqid,
804				 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
805    if (!sc->irq) {
806	device_printf(dev, "unable to allocate interrupt\n");
807	goto bad;
808    }
809
810    if (bus_setup_intr(dev, sc->irq, INTR_TYPE_TTY, cs4281_intr, sc, &sc->ih)) {
811	device_printf(dev, "unable to setup interrupt\n");
812	goto bad;
813    }
814
815    if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0,
816			   /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
817			   /*highaddr*/BUS_SPACE_MAXADDR,
818			   /*filter*/NULL, /*filterarg*/NULL,
819			   /*maxsize*/CS4281_BUFFER_SIZE, /*nsegments*/1,
820			   /*maxsegz*/0x3ffff,
821			   /*flags*/0, &sc->parent_dmat) != 0) {
822	device_printf(dev, "unable to create dma tag\n");
823	goto bad;
824    }
825
826    /* power up */
827    cs4281_power(sc, 0);
828
829    /* init chip */
830    if (cs4281_init(sc) == -1) {
831	device_printf(dev, "unable to initialize the card\n");
832	goto bad;
833    }
834
835    /* create/init mixer */
836    codec = AC97_CREATE(dev, sc, cs4281_ac97);
837    if (codec == NULL)
838        goto bad;
839
840    mixer_init(dev, ac97_getmixerclass(), codec);
841
842    if (pcm_register(dev, sc, 1, 1))
843	goto bad;
844
845    pcm_addchan(dev, PCMDIR_PLAY, &cs4281chan_class, sc);
846    pcm_addchan(dev, PCMDIR_REC, &cs4281chan_class, sc);
847
848    snprintf(status, SND_STATUSLEN, "at %s 0x%lx irq %ld",
849	     (sc->regtype == SYS_RES_IOPORT)? "io" : "memory",
850	     rman_get_start(sc->reg), rman_get_start(sc->irq));
851    pcm_setstatus(dev, status);
852
853    return 0;
854
855 bad:
856    if (codec)
857	ac97_destroy(codec);
858    if (sc->reg)
859	bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);
860    if (sc->mem)
861	bus_release_resource(dev, SYS_RES_MEMORY, sc->memid, sc->mem);
862    if (sc->ih)
863	bus_teardown_intr(dev, sc->irq, sc->ih);
864    if (sc->irq)
865	bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
866    if (sc->parent_dmat)
867	bus_dma_tag_destroy(sc->parent_dmat);
868    free(sc, M_DEVBUF);
869
870    return ENXIO;
871}
872
873static int
874cs4281_pci_detach(device_t dev)
875{
876    int r;
877    struct sc_info *sc;
878
879    r = pcm_unregister(dev);
880    if (r)
881	return r;
882
883    sc = pcm_getdevinfo(dev);
884    /* shutdown chip */
885    cs4281_uninit(sc);
886
887    /* power off */
888    cs4281_power(sc, 3);
889
890    bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);
891    bus_release_resource(dev, SYS_RES_MEMORY, sc->memid, sc->mem);
892    bus_teardown_intr(dev, sc->irq, sc->ih);
893    bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
894    bus_dma_tag_destroy(sc->parent_dmat);
895    free(sc, M_DEVBUF);
896
897    return 0;
898}
899
900static int
901cs4281_pci_suspend(device_t dev)
902{
903    struct sc_info *sc;
904
905    sc = pcm_getdevinfo(dev);
906    /* save chip state */
907
908    /* power off */
909    cs4281_power(sc, 3);
910
911    return 0;
912}
913
914static int
915cs4281_pci_resume(device_t dev)
916{
917    struct sc_info *sc;
918
919    sc = pcm_getdevinfo(dev);
920
921    /* power up */
922    /* cs4281_power(sc, 0); */
923
924    /* reinit chip */
925    if (cs4281_reinit(sc) == -1) {
926	device_printf(dev, "unable to reinitialize the card\n");
927	return ENXIO;
928    }
929
930    /* restore chip state */
931
932    /* restore mixer state */
933    if (mixer_reinit(dev) == -1) {
934	device_printf(dev, "unable to reinitialize the mixer\n");
935	return ENXIO;
936    }
937
938    return 0;
939}
940
941static device_method_t cs4281_methods[] = {
942    /* Device interface */
943    DEVMETHOD(device_probe,		cs4281_pci_probe),
944    DEVMETHOD(device_attach,		cs4281_pci_attach),
945    DEVMETHOD(device_detach,		cs4281_pci_detach),
946    DEVMETHOD(device_suspend,		cs4281_pci_suspend),
947    DEVMETHOD(device_resume,		cs4281_pci_resume),
948    { 0, 0 }
949};
950
951static driver_t cs4281_driver = {
952    "pcm",
953    cs4281_methods,
954    sizeof(snddev_info),
955};
956
957static devclass_t pcm_devclass;
958
959DRIVER_MODULE(snd_cs4281, pci, cs4281_driver, pcm_devclass, 0, 0);
960MODULE_DEPEND(snd_cs4281, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER);
961MODULE_VERSION(snd_cs4281, 1);
962