166550Snyan/* $FreeBSD$ */ 266550Snyan/* $NecBSD: dp83932var.h,v 1.3 1999/01/24 01:39:51 kmatsuda Exp $ */ 366550Snyan/* $NetBSD: if_snvar.h,v 1.12 1998/05/01 03:42:47 scottr Exp $ */ 466550Snyan 5139749Simp/*- 666550Snyan * [NetBSD for NEC PC-98 series] 766550Snyan * Copyright (c) 1997, 1998, 1999 866550Snyan * Kouichi Matsuda. All rights reserved. 9139749Simp * 1066550Snyan * Copyright (c) 1991 Algorithmics Ltd (http://www.algor.co.uk) 1166550Snyan * You may use, copy, and modify this program so long as you retain the 1266550Snyan * copyright line. 1366550Snyan */ 1466550Snyan 1566550Snyan/* 1666550Snyan * if_snvar.h -- National Semiconductor DP8393X (SONIC) NetBSD/mac68k vars 1766550Snyan */ 1866550Snyan/* 1966550Snyan * Modified for NetBSD/pc98 1.2.1 from NetBSD/mac68k 1.2D by Kouichi Matsuda. 2066550Snyan * Make adapted for NEC PC-9801-83, 84, PC-9801-103, 104, PC-9801N-25 and 2166550Snyan * PC-9801N-J02, J02R, which uses National Semiconductor DP83934AVQB as 2266550Snyan * Ethernet Controller and National Semiconductor NS46C46 as 2366550Snyan * (64 * 16 bits) Microwire Serial EEPROM. 2466550Snyan */ 2566550Snyan 2666550Snyan/* 2766550Snyan * Vendor types 2866550Snyan */ 2966550Snyan 3066550Snyan/* 3166550Snyan * SONIC buffers need to be aligned 16 or 32 bit aligned. 3266550Snyan * These macros calculate and verify alignment. 3366550Snyan */ 3466550Snyan#define ROUNDUP(p, N) (((int) p + N - 1) & ~(N - 1)) 3566550Snyan 3666550Snyan#define SOALIGN(m, array) (m ? (ROUNDUP(array, 4)) : (ROUNDUP(array, 2))) 3766550Snyan 3866550Snyan#define LOWER(x) ((unsigned)(x) & 0xffff) 3966550Snyan#define UPPER(x) ((unsigned)(x) >> 16) 4066550Snyan 4166550Snyan/* 4266550Snyan * Memory access macros. Since we handle SONIC in 16 bit mode (PB5X0) 4366550Snyan * and 32 bit mode (everything else) using a single GENERIC kernel 4466550Snyan * binary, all structures have to be accessed using macros which can 4566550Snyan * adjust the offsets appropriately. 4666550Snyan */ 4766550Snyan/* m is not sc->bitmode, we treat m as sc. */ 4866550Snyan#define SWO(m, a, o, x) (*(m)->sc_writetodesc)((m), (a), (o), (x)) 4966550Snyan#define SRO(m, a, o) (*(m)->sc_readfromdesc)((m), (a), (o)) 5066550Snyan 5166550Snyan/* 5266550Snyan * Register access macros. We use bus_space_* to talk to the Sonic 5366550Snyan * registers. A mapping table is used in case a particular configuration 5466550Snyan * hooked the regs up at non-word offsets. 5566550Snyan */ 5666550Snyan#define NIC_GET(sc, reg) (*(sc)->sc_nic_get)(sc, reg) 5766550Snyan#define NIC_PUT(sc, reg, val) (*(sc)->sc_nic_put)(sc, reg, val) 5866550Snyan 5966550Snyan#define SONIC_GETDMA(p) (p) 6066550Snyan 6166550Snyan/* pc98 does not have any write buffers to flush... */ 6266550Snyan#define wbflush() 6366550Snyan 6466550Snyan/* 6566550Snyan * buffer sizes in 32 bit mode 6666550Snyan * 1 TXpkt is 4 hdr words + (3 * FRAGMAX) + 1 link word == 23 words == 92 bytes 6766550Snyan * 6866550Snyan * 1 RxPkt is 7 words == 28 bytes 6966550Snyan * 1 Rda is 4 words == 16 bytes 7066550Snyan * 7166550Snyan * The CDA is 17 words == 68 bytes 7266550Snyan * 7366550Snyan * total space in page 0 = NTDA * 92 + NRRA * 16 + NRDA * 28 + 68 7466550Snyan */ 7566550Snyan 7666550Snyan#define NRBA 16 /* # receive buffers < NRRA */ 7766550Snyan#define RBAMASK (NRBA-1) 7866550Snyan#define NTDA 16 /* # transmit descriptors */ 7966550Snyan#define NRRA 64 /* # receive resource descriptors */ 8066550Snyan#define RRAMASK (NRRA-1) /* the reason why NRRA must be power of two */ 8166550Snyan 8266550Snyan#define FCSSIZE 4 /* size of FCS appended to packets */ 8366550Snyan 8466550Snyan/* 8566550Snyan * maximum receive packet size plus 2 byte pad to make each 8666550Snyan * one aligned. 4 byte slop (required for eobc) 8766550Snyan */ 8866550Snyan#define RBASIZE(sc) (sizeof(struct ether_header) + ETHERMTU + FCSSIZE + \ 8966550Snyan ((sc)->bitmode ? 6 : 2)) 9066550Snyan 9166550Snyan/* 9266550Snyan * transmit buffer area 9366550Snyan */ 9466550Snyan#define TXBSIZE 1536 /* 6*2^8 -- the same size as the 8390 TXBUF */ 9566550Snyan 9666550Snyan#define SN_NPAGES 2 + NRBA + (NTDA/2) 9766550Snyan 9866550Snyantypedef struct mtd { 9966550Snyan u_int32_t mtd_vtxp; 10066550Snyan u_int32_t mtd_vbuf; 10166550Snyan struct mbuf *mtd_mbuf; 10266550Snyan} mtd_t; 10366550Snyan 10466550Snyan/* 10566550Snyan * The snc_softc for PC-98 if_snc. 10666550Snyan */ 10766550Snyantypedef struct snc_softc { 108147256Sbrooks struct ifnet * sc_ifp; 10966550Snyan 11066550Snyan device_t sc_dev; 11166550Snyan 11266550Snyan struct resource * ioport; 11366550Snyan int ioport_rid; 11466550Snyan struct resource * iomem; 11566550Snyan int iomem_rid; 11666550Snyan struct resource * irq; 11766550Snyan int irq_rid; 11866550Snyan void * irq_handle; 11966550Snyan 12066550Snyan bus_space_tag_t sc_iot; /* bus identifier for io */ 12166550Snyan bus_space_tag_t sc_memt; /* bus identifier for mem */ 12266550Snyan bus_space_handle_t sc_ioh; /* io handle */ 12366550Snyan bus_space_handle_t sc_memh; /* bus memory handle */ 12466550Snyan 12566550Snyan int bitmode; /* 32 bit mode == 1, 16 == 0 */ 12666550Snyan 12766550Snyan u_int16_t sncr_dcr; /* DCR for this instance */ 12866550Snyan u_int16_t sncr_dcr2; /* DCR2 for this instance */ 12966550Snyan 13066550Snyan int sc_rramark; /* index into v_rra of wp */ 13166550Snyan u_int32_t v_rra[NRRA]; /* DMA addresses of v_rra */ 13266550Snyan u_int32_t v_rea; /* ptr to the end of the rra space */ 13366550Snyan 13466550Snyan int sc_rxmark; /* current hw pos in rda ring */ 13566550Snyan int sc_rdamark; /* current sw pos in rda ring */ 13666550Snyan int sc_nrda; /* total number of RDAs */ 13766550Snyan u_int32_t v_rda; 13866550Snyan 13966550Snyan u_int32_t rbuf[NRBA]; 14066550Snyan 14166550Snyan struct mtd mtda[NTDA]; 14266550Snyan int mtd_hw; /* idx of first mtd given to hw */ 14366550Snyan int mtd_prev; /* idx of last mtd given to hardware */ 14466550Snyan int mtd_free; /* next free mtd to use */ 14566550Snyan int mtd_tlinko; /* 14666550Snyan * offset of tlink of last txp given 14766550Snyan * to SONIC. Need to clear EOL on 14866550Snyan * this word to add a desc. 14966550Snyan */ 15066550Snyan int mtd_pint; /* Counter to set TXP_PINT */ 15166550Snyan 15266550Snyan u_int32_t v_cda; 15366550Snyan 15466550Snyan u_int8_t curbank; /* current window bank */ 15566550Snyan 15666550Snyan struct ifmedia sc_media; /* supported media information */ 15766550Snyan 15866550Snyan /* 15966550Snyan * NIC register access functions: 16066550Snyan */ 16166550Snyan u_int16_t (*sc_nic_get) 16292739Salfred (struct snc_softc *, u_int8_t); 16366550Snyan void (*sc_nic_put) 16492739Salfred (struct snc_softc *, u_int8_t, u_int16_t); 16566550Snyan 16666550Snyan /* 16766550Snyan * Memory functions: 16866550Snyan * 16966550Snyan * copy to/from descriptor 17066550Snyan * copy to/from buffer 17166550Snyan * zero bytes in buffer 17266550Snyan */ 17366550Snyan void (*sc_writetodesc) 17492739Salfred (struct snc_softc *, u_int32_t, u_int32_t, u_int16_t); 17566550Snyan u_int16_t (*sc_readfromdesc) 17692739Salfred (struct snc_softc *, u_int32_t, u_int32_t); 17766550Snyan void (*sc_copytobuf) 17892739Salfred (struct snc_softc *, void *, u_int32_t, size_t); 17966550Snyan void (*sc_copyfrombuf) 18092739Salfred (struct snc_softc *, void *, u_int32_t, size_t); 18166550Snyan void (*sc_zerobuf) 18292739Salfred (struct snc_softc *, u_int32_t, size_t); 18366550Snyan 18466550Snyan /* 18566550Snyan * Machine-dependent functions: 18666550Snyan * 18766550Snyan * hardware reset hook - may be NULL 18866550Snyan * hardware init hook - may be NULL 18966550Snyan * media change hook - may be NULL 19066550Snyan */ 19192739Salfred void (*sc_hwreset)(struct snc_softc *); 19292739Salfred void (*sc_hwinit)(struct snc_softc *); 19392739Salfred int (*sc_mediachange)(struct snc_softc *); 19492739Salfred void (*sc_mediastatus)(struct snc_softc *, struct ifmediareq *); 19566550Snyan 19666550Snyan int sc_enabled; /* boolean; power enabled on interface */ 19766550Snyan 19892739Salfred int (*sc_enable)(struct snc_softc *); 19992739Salfred void (*sc_disable)(struct snc_softc *); 20066550Snyan 20166550Snyan void *sc_sh; /* shutdownhook cookie */ 20266550Snyan int gone; 203181298Sjhb struct mtx sc_lock; 204181298Sjhb struct callout sc_timer; 205181298Sjhb int sc_tx_timeout; 20666550Snyan} snc_softc_t; 20766550Snyan 208181298Sjhb#define SNC_LOCK(sc) mtx_lock(&(sc)->sc_lock) 209181298Sjhb#define SNC_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 210181298Sjhb#define SNC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 211181298Sjhb 21266550Snyan/* 21366550Snyan * Accessing SONIC data structures and registers as 32 bit values 21466550Snyan * makes code endianess independent. The SONIC is however always in 21566550Snyan * bigendian mode so it is necessary to ensure that data structures shared 21666550Snyan * between the CPU and the SONIC are always in bigendian order. 21766550Snyan */ 21866550Snyan 21966550Snyan/* 22066550Snyan * Receive Resource Descriptor 22166550Snyan * This structure describes the buffers into which packets 22266550Snyan * will be received. Note that more than one packet may be 22366550Snyan * packed into a single buffer if constraints permit. 22466550Snyan */ 22566550Snyan#define RXRSRC_PTRLO 0 /* buffer address LO */ 22666550Snyan#define RXRSRC_PTRHI 1 /* buffer address HI */ 22766550Snyan#define RXRSRC_WCLO 2 /* buffer size (16bit words) LO */ 22866550Snyan#define RXRSRC_WCHI 3 /* buffer size (16bit words) HI */ 22966550Snyan 23066550Snyan#define RXRSRC_SIZE(sc) (sc->bitmode ? (4 * 4) : (4 * 2)) 23166550Snyan 23266550Snyan/* 23366550Snyan * Receive Descriptor 23466550Snyan * This structure holds information about packets received. 23566550Snyan */ 23666550Snyan#define RXPKT_STATUS 0 23766550Snyan#define RXPKT_BYTEC 1 23866550Snyan#define RXPKT_PTRLO 2 23966550Snyan#define RXPKT_PTRHI 3 24066550Snyan#define RXPKT_SEQNO 4 24166550Snyan#define RXPKT_RLINK 5 24266550Snyan#define RXPKT_INUSE 6 24366550Snyan#define RXPKT_SIZE(sc) (sc->bitmode ? (7 * 4) : (7 * 2)) 24466550Snyan 24566550Snyan#define RBASEQ(x) (((x)>>8)&0xff) 24666550Snyan#define PSNSEQ(x) ((x) & 0xff) 24766550Snyan 24866550Snyan/* 24966550Snyan * Transmit Descriptor 25066550Snyan * This structure holds information about packets to be transmitted. 25166550Snyan */ 25266550Snyan#define FRAGMAX 8 /* maximum number of fragments in a packet */ 25366550Snyan 25466550Snyan#define TXP_STATUS 0 /* + transmitted packet status */ 25566550Snyan#define TXP_CONFIG 1 /* transmission configuration */ 25666550Snyan#define TXP_PKTSIZE 2 /* entire packet size in bytes */ 25766550Snyan#define TXP_FRAGCNT 3 /* # fragments in packet */ 25866550Snyan 25966550Snyan#define TXP_FRAGOFF 4 /* offset to first fragment */ 26066550Snyan#define TXP_FRAGSIZE 3 /* size of each fragment desc */ 26166550Snyan#define TXP_FPTRLO 0 /* ptr to packet fragment LO */ 26266550Snyan#define TXP_FPTRHI 1 /* ptr to packet fragment HI */ 26366550Snyan#define TXP_FSIZE 2 /* fragment size */ 26466550Snyan 26566550Snyan#define TXP_WORDS (TXP_FRAGOFF + (FRAGMAX*TXP_FRAGSIZE) + 1) /* 1 for tlink */ 26666550Snyan#define TXP_SIZE(sc) ((sc->bitmode) ? (TXP_WORDS*4) : (TXP_WORDS*2)) 26766550Snyan 26866550Snyan#define EOL 0x0001 /* end of list marker for link fields */ 26966550Snyan 27066550Snyan/* 27166550Snyan * CDA, the CAM descriptor area. The SONIC has a 16 entry CAM to 27266550Snyan * match incoming addresses against. It is programmed via DMA 27366550Snyan * from a memory region. 27466550Snyan */ 27566550Snyan#define MAXCAM 16 /* number of user entries in CAM */ 27666550Snyan#define CDA_CAMDESC 4 /* # words i na descriptor */ 27766550Snyan#define CDA_CAMEP 0 /* CAM Address Port 0 xx-xx-xx-xx-YY-YY */ 27866550Snyan#define CDA_CAMAP0 1 /* CAM Address Port 1 xx-xx-YY-YY-xx-xx */ 27966550Snyan#define CDA_CAMAP1 2 /* CAM Address Port 2 YY-YY-xx-xx-xx-xx */ 28066550Snyan#define CDA_CAMAP2 3 28166550Snyan#define CDA_ENABLE 64 /* mask enabling CAM entries */ 28266550Snyan#define CDA_SIZE(sc) ((4*16 + 1) * ((sc->bitmode) ? 4 : 2)) 28366550Snyan 284181298Sjhbint sncconfig(struct snc_softc *, int *, int, int, u_int8_t *); 28592739Salfredvoid sncintr(void *); 28692739Salfredvoid sncshutdown(void *); 287