dp83932reg.h revision 66550
179697Snon/* $FreeBSD: head/sys/dev/snc/dp83932reg.h 66550 2000-10-02 14:27:20Z nyan $ */ 267468Snon/* $NecBSD: dp83932reg.h,v 1.2 1999/02/12 05:50:13 kmatsuda Exp $ */ 367468Snon/* $NetBSD: if_snreg.h,v 1.4 1997/06/15 20:20:12 scottr Exp $ */ 467468Snon 567468Snon/* 679697Snon * Copyright (c) 1991 Algorithmics Ltd (http://www.algor.co.uk) 767468Snon * You may use, copy, and modify this program so long as you retain the 8139749Simp * copyright line. 967468Snon */ 1079697Snon 1167468Snon/* 1279697Snon * if_snreg.h -- National Semiconductor DP8393X (SONIC) register defs 1367468Snon */ 1467468Snon 1567468Snon/* 1667468Snon * SONIC registers as seen by the processor 1767468Snon */ 1867468Snon#define SNCR_CR 0x00 /* Command */ 1967468Snon#define SNCR_DCR 0x01 /* Data Configuration */ 2067468Snon#define SNCR_RCR 0x02 /* Receive Control */ 2167468Snon#define SNCR_TCR 0x03 /* Transmit Control */ 2267468Snon#define SNCR_IMR 0x04 /* Interrupt Mask */ 2367468Snon#define SNCR_ISR 0x05 /* Interrupt Status */ 2467468Snon#define SNCR_UTDA 0x06 /* Upper Transmit Descriptor Address */ 2567468Snon#define SNCR_CTDA 0x07 /* Current Transmit Descriptor Address */ 2667468Snon#define SNCR_TPS 0x08 /* Transmit Packet Size */ 2767468Snon#define SNCR_TFC 0x09 /* Transmit Fragment Count */ 2867468Snon#define SNCR_TSA0 0x0a /* Transmit Start Address 0 */ 2967468Snon#define SNCR_TSA1 0x0b /* Transmit Start Address 1 */ 3067468Snon#define SNCR_TFS 0x0c /* Transmit Fragment Size */ 3167468Snon#define SNCR_URDA 0x0d /* Upper Receive Descriptor Address */ 3267468Snon#define SNCR_CRDA 0x0e /* Current Receive Descriptor Address */ 3367468Snon#define SNCR_CRBA0 0x0f /* Current Receive Buffer Address 0 */ 3467468Snon#define SNCR_CRBA1 0x10 /* Current Receive Buffer Address 1 */ 3567468Snon#define SNCR_RBWC0 0x11 /* Remaining Buffer Word Count 0 */ 3667468Snon#define SNCR_RBWC1 0x12 /* Remaining Buffer Word Count 1 */ 3767468Snon#define SNCR_EOBC 0x13 /* End Of Buffer Word Count */ 38119418Sobrien#define SNCR_URRA 0x14 /* Upper Receive Resource Address */ 39119418Sobrien#define SNCR_RSA 0x15 /* Resource Start Address */ 40119418Sobrien#define SNCR_REA 0x16 /* Resource End Address */ 4167468Snon#define SNCR_RRP 0x17 /* Resource Read Pointer */ 4267468Snon#define SNCR_RWP 0x18 /* Resource Write Pointer */ 4367468Snon#define SNCR_TRBA0 0x19 /* Temporary Receive Buffer Address 0 */ 4467468Snon#define SNCR_TRBA1 0x1a /* Temporary Receive Buffer Address 1 */ 4567468Snon#define SNCR_TBWC0 0x1b /* Temporary Buffer Word Count 0 */ 4667468Snon#define SNCR_TBWC1 0x1c /* Temporary Buffer Word Count 1 */ 4767468Snon#define SNCR_ADDR0 0x1d /* Address Generator 0 */ 4867468Snon#define SNCR_ADDR1 0x1e /* Address Generator 1 */ 4967468Snon#define SNCR_LLFA 0x1f /* Last Link Field Address */ 5067468Snon#define SNCR_TTDA 0x20 /* Temp Transmit Descriptor Address */ 5167468Snon#define SNCR_CEP 0x21 /* CAM Entry Pointer */ 5267468Snon#define SNCR_CAP2 0x22 /* CAM Address Port 2 */ 5367468Snon#define SNCR_CAP1 0x23 /* CAM Address Port 1 */ 54126928Speter#define SNCR_CAP0 0x24 /* CAM Address Port 0 */ 55126928Speter#define SNCR_CE 0x25 /* CAM Enable */ 5667468Snon#define SNCR_CDP 0x26 /* CAM Descriptor Pointer */ 5767468Snon#define SNCR_CDC 0x27 /* CAM Descriptor Count */ 5867468Snon#define SNCR_SR 0x28 /* Silicon Revision */ 5967468Snon#define SNCR_WT0 0x29 /* Watchdog Timer 0 */ 6067468Snon#define SNCR_WT1 0x2a /* Watchdog Timer 1 */ 6167468Snon#define SNCR_RSC 0x2b /* Receive Sequence Counter */ 6267468Snon#define SNCR_CRCT 0x2c /* CRC Error Tally */ 6367468Snon#define SNCR_FAET 0x2d /* FAE Tally */ 6467468Snon#define SNCR_MPT 0x2e /* Missed Packet Tally */ 6579697Snon#define SNCR_MDT 0x2f /* Maximum Deferral Timer */ 6679697Snon#define SNCR_RTC 0x30 /* Receive Test Control */ 6779697Snon#define SNCR_TTC 0x31 /* Transmit Test Control */ 6879697Snon#define SNCR_DTC 0x32 /* DMA Test Control */ 6979697Snon#define SNCR_CC0 0x33 /* CAM Comparison 0 */ 7067468Snon#define SNCR_CC1 0x34 /* CAM Comparison 1 */ 7179697Snon#define SNCR_CC2 0x35 /* CAM Comparison 2 */ 7279697Snon#define SNCR_CM 0x36 /* CAM Match */ 7379697Snon#define SNCR_RES1 0x37 /* reserved */ 7479697Snon#define SNCR_RES2 0x38 /* reserved */ 7579697Snon#define SNCR_RBC 0x39 /* Receiver Byte Count */ 7679697Snon#define SNCR_RES3 0x3a /* reserved */ 7779697Snon#define SNCR_TBO 0x3b /* Transmitter Backoff Counter */ 7879697Snon#define SNCR_TRC 0x3c /* Transmitter Random Counter */ 7979697Snon#define SNCR_TBM 0x3d /* Transmitter Backoff Mask */ 8079697Snon#define SNCR_RES4 0x3e /* Reserved */ 8179697Snon#define SNCR_DCR2 0x3f /* Data Configuration 2 (AVF) */ 8279697Snon 8367468Snon#define SNC_NREGS 0x40 8467468Snon 8567468Snon/* 8689093Smsmith * Register Interpretations 8767468Snon */ 8867468Snon 8967468Snon/* 9089093Smsmith * The command register is used for issuing commands to the SONIC. 9167468Snon * With the exception of CR_RST, the bit is reset when the operation 9267468Snon * completes. 9379697Snon */ 9467468Snon#define CR_LCAM 0x0200 /* load CAM with descriptor at s_cdp */ 9567468Snon#define CR_RRRA 0x0100 /* read next RRA descriptor at s_rrp */ 9667468Snon#define CR_RST 0x0080 /* software reset */ 9779697Snon#define CR_ST 0x0020 /* start timer */ 9867468Snon#define CR_STP 0x0010 /* stop timer */ 9967468Snon#define CR_RXEN 0x0008 /* receiver enable */ 10067468Snon#define CR_RXDIS 0x0004 /* receiver disable */ 10167468Snon#define CR_TXP 0x0002 /* transmit packets */ 10267468Snon#define CR_HTX 0x0001 /* halt transmission */ 10367468Snon 10467468Snon/* 10592739Salfred * The data configuration register establishes the SONIC's bus cycle 10692739Salfred * operation. This register can only be accessed when the SONIC is in 10792739Salfred * reset mode (s_cr.CR_RST is set.) 10892739Salfred */ 10992739Salfred#define DCR_EXBUS 0x8000 /* extended bus mode (AVF) */ 11067468Snon#define DCR_LBR 0x2000 /* latched bus retry */ 11192739Salfred#define DCR_PO1 0x1000 /* programmable output 1 */ 11292739Salfred#define DCR_PO0 0x0800 /* programmable output 0 */ 11392739Salfred#define DCR_STERM 0x0400 /* synchronous termination */ 11492739Salfred#define DCR_USR1 0x0200 /* reflects USR1 input pin */ 11592739Salfred#define DCR_USR0 0x0100 /* reflects USR0 input pin */ 11667468Snon#define DCR_WC1 0x0080 /* wait state control 1 */ 11792739Salfred#define DCR_WC0 0x0040 /* wait state control 0 */ 11892739Salfred#define DCR_DW 0x0020 /* data width select */ 11992739Salfred#define DCR_BMS 0x0010 /* DMA block mode select */ 12092739Salfred#define DCR_RFT1 0x0008 /* receive FIFO threshold control 1 */ 12192739Salfred#define DCR_RFT0 0x0004 /* receive FIFO threshold control 0 */ 12292739Salfred#define DCR_TFT1 0x0002 /* transmit FIFO threshold control 1 */ 12392739Salfred#define DCR_TFT0 0x0001 /* transmit FIFO threshold control 0 */ 12492739Salfred 12592739Salfred/* data configuration register aliases */ 12692739Salfred#define DCR_SYNC DCR_STERM /* synchronous (memory cycle 2 clocks) */ 12792739Salfred#define DCR_ASYNC 0 /* asynchronous (memory cycle 3 clocks) */ 12892739Salfred 12992739Salfred#define DCR_WAIT0 0 /* 0 wait states added */ 13067468Snon#define DCR_WAIT1 DCR_WC0 /* 1 wait state added */ 13192739Salfred#define DCR_WAIT2 DCR_WC1 /* 2 wait states added */ 13279697Snon#define DCR_WAIT3 (DCR_WC1|DCR_WC0) /* 3 wait states added */ 13392739Salfred 13467468Snon#define DCR_DW16 0 /* use 16-bit DMA accesses */ 13567468Snon#define DCR_DW32 DCR_DW /* use 32-bit DMA accesses */ 13667468Snon 13767468Snon#define DCR_DMAEF 0 /* DMA until TX/RX FIFO has emptied/filled */ 13873025Snon#define DCR_DMABLOCK DCR_BMS /* DMA until RX/TX threshold crossed */ 13979697Snon 14067468Snon#define DCR_RFT4 0 /* receive threshold 4 bytes */ 14167468Snon#define DCR_RFT8 DCR_RFT0 /* receive threshold 8 bytes */ 14279697Snon#define DCR_RFT16 DCR_RFT1 /* receive threshold 16 bytes */ 14379697Snon#define DCR_RFT24 (DCR_RFT1|DCR_RFT0) /* receive threshold 24 bytes */ 14467468Snon 14567468Snon#define DCR_TFT8 0 /* transmit threshold 8 bytes */ 14667468Snon#define DCR_TFT16 DCR_TFT0 /* transmit threshold 16 bytes */ 14767468Snon#define DCR_TFT24 DCR_TFT1 /* transmit threshold 24 bytes */ 14879697Snon#define DCR_TFT28 (DCR_TFT1|DCR_TFT0) /* transmit threshold 28 bytes */ 14967468Snon 15067468Snon/* 15167468Snon * The receive control register is used to filter incoming packets and 15267468Snon * provides status information on packets received. 15367468Snon * The contents of the register are copied into the RXpkt.status field 15467468Snon * when a packet is received. RCR_MC - RCR_PRX are then reset. 15567468Snon */ 15667468Snon#define RCR_ERR 0x8000 /* accept packets with CRC errors */ 15767468Snon#define RCR_RNT 0x4000 /* accept runt (length < 64) packets */ 15867468Snon#define RCR_BRD 0x2000 /* accept broadcast packets */ 15967468Snon#define RCR_PRO 0x1000 /* accept all physical address packets */ 16067468Snon#define RCR_AMC 0x0800 /* accept all multicast packets */ 16167468Snon#define RCR_LB1 0x0400 /* loopback control 1 */ 16267468Snon#define RCR_LB0 0x0200 /* loopback control 0 */ 16367468Snon#define RCR_MC 0x0100 /* multicast packet received */ 16479697Snon#define RCR_BC 0x0080 /* broadcast packet received */ 16567468Snon#define RCR_LPKT 0x0040 /* last packet in RBA (RBWC < EOBC) */ 16667468Snon#define RCR_CRS 0x0020 /* carrier sense activity */ 16767468Snon#define RCR_COL 0x0010 /* collision activity */ 16867468Snon#define RCR_CRC 0x0008 /* CRC error */ 16967468Snon#define RCR_FAE 0x0004 /* frame alignment error */ 17067468Snon#define RCR_LBK 0x0002 /* loopback packet received */ 17167468Snon#define RCR_PRX 0x0001 /* packet received without errors */ 17267468Snon 17367468Snon/* receiver control register aliases */ 17479697Snon/* the loopback control bits provide the following options */ 17567468Snon#define RCR_LBNONE 0 /* no loopback - normal operation */ 17667468Snon#define RCR_LBMAC RCR_LB0 /* MAC loopback */ 17767468Snon#define RCR_LBENDEC RCR_LB1 /* ENDEC loopback */ 17867468Snon#define RCR_LBTRANS (RCR_LB1|RCR_LB0) /* transceiver loopback */ 17967468Snon 18067468Snon/* 18167468Snon * The transmit control register controls the SONIC's transmit operations. 18267468Snon * TCR_PINT - TCR_EXDIS are loaded from the TXpkt.config field at the 18367468Snon * start of transmission. TCR_EXD-TCR_PTX are cleared at the beginning 18467468Snon * of transmission and updated when the transmission is completed. 18567468Snon */ 18667468Snon#define TCR_PINT 0x8000 /* interrupt when transmission starts */ 18767468Snon#define TCR_POWC 0x4000 /* program out of window collision timer */ 18867468Snon#define TCR_CRCI 0x2000 /* transmit packet without 4 byte FCS */ 18967468Snon#define TCR_EXDIS 0x1000 /* disable excessive deferral timer */ 19079697Snon#define TCR_EXD 0x0400 /* excessive deferrals occurred (>3.2ms) */ 19179697Snon#define TCR_DEF 0x0200 /* deferred transmissions occurred */ 19279697Snon#define TCR_NCRS 0x0100 /* carrier not present during transmission */ 19379697Snon#define TCR_CRSL 0x0080 /* carrier lost during transmission */ 19479697Snon#define TCR_EXC 0x0040 /* excessive collisions (>16) detected */ 19579697Snon#define TCR_OWC 0x0020 /* out of window (bad) collision occurred */ 19679697Snon#define TCR_PMB 0x0008 /* packet monitored bad - the tansmitted 19779697Snon * packet had a bad source address or CRC */ 19879697Snon#define TCR_FU 0x0004 /* FIFO underrun (memory access failed) */ 19979697Snon#define TCR_BCM 0x0002 /* byte count mismatch (TXpkt.pkt_size 20079697Snon * != sum(TXpkt.frag_size) */ 20179697Snon#define TCR_PTX 0x0001 /* packet transmitted without errors */ 20279697Snon#define TCR_NC 0xf000 /* after transmission, # of colls */ 20379697Snon 20479697Snon/* transmit control register aliases */ 20579697Snon#define TCR_OWCSFD 0 /* start after start of frame delimiter */ 20679697Snon#define TCR_OWCPRE TCR_POWC /* start after first bit of preamble */ 20779697Snon 20879697Snon 20979697Snon/* 21079697Snon * The interrupt mask register masks the interrupts that 21179697Snon * are generated from the interrupt status register. 21279697Snon * All reserved bits should be written with 0. 21379697Snon */ 21479697Snon#define IMR_BREN 0x4000 /* bus retry occurred enable */ 21567468Snon#define IMR_HBLEN 0x2000 /* heartbeat lost enable */ 21667468Snon#define IMR_LCDEN 0x1000 /* load CAM done interrupt enable */ 21767468Snon#define IMR_PINTEN 0x0800 /* programmable interrupt enable */ 21867468Snon#define IMR_PRXEN 0x0400 /* packet received enable */ 21967468Snon#define IMR_PTXEN 0x0200 /* packet transmitted enable */ 22067468Snon#define IMR_TXEREN 0x0100 /* transmit error enable */ 22167468Snon#define IMR_TCEN 0x0080 /* timer complete enable */ 22267468Snon#define IMR_RDEEN 0x0040 /* receive descriptors exhausted enable */ 22367468Snon#define IMR_RBEEN 0x0020 /* receive buffers exhausted enable */ 22467468Snon#define IMR_RBAEEN 0x0010 /* receive buffer area exceeded enable */ 22567468Snon#define IMR_CRCEN 0x0008 /* CRC tally counter rollover enable */ 22667468Snon#define IMR_FAEEN 0x0004 /* FAE tally counter rollover enable */ 22767468Snon#define IMR_MPEN 0x0002 /* MP tally counter rollover enable */ 22867468Snon#define IMR_RFOEN 0x0001 /* receive FIFO overrun enable */ 22967468Snon 23067468Snon 23167468Snon/* 23267468Snon * The interrupt status register indicates the source of an interrupt when 23367468Snon * the INT pin goes active. The interrupt is acknowledged by writing 23467468Snon * the appropriate bit(s) in this register. 23567468Snon */ 23667468Snon#define ISR_ALL 0x7fff /* all interrupts */ 23767468Snon#define ISR_BR 0x4000 /* bus retry occurred */ 23867468Snon#define ISR_HBL 0x2000 /* CD heartbeat lost */ 23967468Snon#define ISR_LCD 0x1000 /* load CAM command has completed */ 24067468Snon#define ISR_PINT 0x0800 /* programmed interrupt from TXpkt.config */ 24167468Snon#define ISR_PKTRX 0x0400 /* packet received */ 24267468Snon#define ISR_TXDN 0x0200 /* no remaining packets to be transmitted */ 24367468Snon#define ISR_TXER 0x0100 /* packet transmission caused error */ 24467468Snon#define ISR_TC 0x0080 /* timer complete */ 24567468Snon#define ISR_RDE 0x0040 /* receive descriptors exhausted */ 24667468Snon#define ISR_RBE 0x0020 /* receive buffers exhausted */ 24767468Snon#define ISR_RBAE 0x0010 /* receive buffer area exceeded */ 24867468Snon#define ISR_CRC 0x0008 /* CRC tally counter rollover */ 24967468Snon#define ISR_FAE 0x0004 /* FAE tally counter rollover */ 25067468Snon#define ISR_MP 0x0002 /* MP tally counter rollover */ 251240172Sjhb#define ISR_RFO 0x0001 /* receive FIFO overrun */ 25267468Snon 25367468Snon/* 25467468Snon * The second data configuration register allows additional user defined 25567468Snon * pins to be controlled. These bits are only available if s_dcr.DCR_EXBUS 256240172Sjhb * is set. 25767468Snon */ 25867468Snon#define DCR2_EXPO3 0x8000 /* EXUSR3 output */ 25967468Snon#define DCR2_EXPO2 0x4000 /* EXUSR2 output */ 26067468Snon#define DCR2_EXPO1 0x2000 /* EXUSR1 output */ 26167468Snon#define DCR2_EXPO0 0x1000 /* EXUSR0 output */ 26267468Snon#define DCR2_HD 0x0800 /* heart beat disable (83934/83936) */ 26367468Snon#define DCR2_JD 0x0200 /* TPI jabber timer disable (83934/83936) */ 26467468Snon#define DCR2_AUTO 0x0100 /* AUI/TPI auto selection (83934/83936) */ 26567468Snon#define DCR2_XWRAP 0x0040 /* TPI transceiver loopback (83934/83936) */ 26667468Snon#define DCR2_FD 0x0020 /* full duplex (83936) */ 26767468Snon#define DCR2_PHL 0x0010 /* extend HOLD signal by 1/2 clock */ 26867468Snon#define DCR2_LRDY 0x0008 /* set latched ready mode */ 26967468Snon#define DCR2_PCM 0x0004 /* packet compress on match */ 27067468Snon#define DCR2_PCNM 0x0002 /* packet compress on mismatch */ 27167468Snon#define DCR2_RJM 0x0001 /* reject on match */ 27267468Snon