1179592Sbenno/*-
2179592Sbenno * Copyright (c) 2006 Benno Rice.  All rights reserved.
3179592Sbenno *
4179592Sbenno * Redistribution and use in source and binary forms, with or without
5179592Sbenno * modification, are permitted provided that the following conditions
6179592Sbenno * are met:
7179592Sbenno * 1. Redistributions of source code must retain the above copyright
8179592Sbenno *    notice, this list of conditions and the following disclaimer.
9179592Sbenno * 2. Redistributions in binary form must reproduce the above copyright
10179592Sbenno *    notice, this list of conditions and the following disclaimer in the
11179592Sbenno *    documentation and/or other materials provided with the distribution.
12179592Sbenno *
13179592Sbenno * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14179592Sbenno * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15179592Sbenno * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16179592Sbenno * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17179592Sbenno * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18179592Sbenno * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19179592Sbenno * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20179592Sbenno * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21179592Sbenno * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22179592Sbenno * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23179592Sbenno *
24179592Sbenno * $FreeBSD$
25179592Sbenno *
26179592Sbenno */
27179592Sbenno
28179592Sbenno#ifndef	_IF_SMCREG_H_
29179592Sbenno#define	_IF_SMCREG_H_
30179592Sbenno
31179592Sbenno/* All Banks, Offset 0xe: Bank Select Register */
32179592Sbenno#define	BSR			0xe
33179592Sbenno#define	BSR_BANK_MASK		0x0007	/* Which bank is currently selected */
34179592Sbenno#define	BSR_IDENTIFY		0x3300	/* Static value for identification */
35179592Sbenno#define	BSR_IDENTIFY_MASK	0xff00
36179592Sbenno
37179592Sbenno/* Bank 0, Offset 0x0: Transmit Control Register */
38179592Sbenno#define	TCR			0x0
39179592Sbenno#define	TCR_TXENA		0x0001	/* Enable/disable transmitter */
40179592Sbenno#define	TCR_LOOP		0x0002	/* Put the PHY into loopback mode */
41179592Sbenno#define	TCR_FORCOL		0x0004	/* Force a collision */
42179592Sbenno#define	TCR_PAD_EN		0x0080	/* Pad TX frames to 64 bytes */
43179592Sbenno#define	TCR_NOCRC		0x0100	/* Disable/enable CRC */
44179592Sbenno#define	TCR_MON_CSN		0x0400	/* Monitor carrier signal */
45179592Sbenno#define	TCR_FDUPLX		0x0800	/* Enable/disable full duplex */
46179592Sbenno#define	TCR_STP_SQET		0x1000	/* Stop TX on signal quality error */
47179592Sbenno#define	TCR_EPH_LOOP		0x2000	/* Internal loopback */
48179592Sbenno#define	TCR_SWFDUP		0x8000	/* Switched full duplex */
49179592Sbenno
50179592Sbenno/* Bank 0, Offset 0x2: EPH Status Register */
51179592Sbenno#define	EPHSR			0x2
52179592Sbenno#define	EPHSR_TX_SUC		0x0001	/* Last TX was successful */
53179592Sbenno#define	EPHSR_SNGLCOL		0x0002	/* Single collision on last TX */
54179592Sbenno#define	EPHSR_MULCOL		0x0004	/* Multiple collisions on last TX */
55179592Sbenno#define	EPHSR_LTX_MULT		0x0008	/* Last TX was multicast */
56179592Sbenno#define	EPHSR_16COL		0x0010	/* 16 collisions on last TX */
57179592Sbenno#define	EPHSR_SQET		0x0020	/* Signal quality error test */
58179592Sbenno#define	EPHSR_LTX_BRD		0x0040	/* Last TX was broadcast */
59179592Sbenno#define	EPHSR_TX_DEFR		0x0080	/* Transmit deferred */
60179592Sbenno#define	EPHSR_LATCOL		0x0200	/* Late collision on last TX */
61179592Sbenno#define	EPHSR_LOST_CARR		0x0400	/* Lost carrier sense */
62179592Sbenno#define	EPHSR_EXC_DEF		0x0800	/* Excessive deferral */
63179592Sbenno#define	EPHSR_CTR_ROL		0x1000	/* Counter rollover */
64179592Sbenno#define	EPHSR_LINK_OK		0x4000	/* Inverse of nLNK pin */
65179592Sbenno#define	EPHSR_TXUNRN		0x8000	/* Transmit underrun */
66179592Sbenno
67179592Sbenno/* Bank 0, Offset 0x4: Receive Control Register */
68179592Sbenno#define	RCR			0x4
69179592Sbenno#define	RCR_RX_ABORT		0x0001	/* RX aborted */
70179592Sbenno#define	RCR_PRMS		0x0002	/* Enable/disable promiscuous mode */
71179592Sbenno#define	RCR_ALMUL		0x0004	/* Accept all multicast frames */
72179592Sbenno#define	RCR_RXEN		0x0100	/* Enable/disable receiver */
73179592Sbenno#define	RCR_STRIP_CRC		0x0200	/* Strip CRC from RX packets */
74179592Sbenno#define	RCR_ABORT_ENB		0x2000	/* Abort RX on collision */
75179592Sbenno#define	RCR_FILT_CAR		0x4000	/* Filter leading 12 bits of carrier */
76179592Sbenno#define	RCR_SOFT_RST		0x8000	/* Software reset */
77179592Sbenno
78179592Sbenno/* Bank 0, Offset 0x6: Counter Register */
79179592Sbenno#define	ECR			0x6
80179592Sbenno#define	ECR_SNGLCOL_MASK	0x000f	/* Single collisions */
81179592Sbenno#define	ECR_SNGLCOL_SHIFT	0
82179592Sbenno#define	ECR_MULCOL_MASK		0x00f0	/* Multiple collisions */
83179592Sbenno#define	ECR_MULCOL_SHIFT	4
84179592Sbenno#define	ECR_TX_DEFR_MASK	0x0f00	/* Transmit deferrals */
85179592Sbenno#define	ECR_TX_DEFR_SHIFT	8
86179592Sbenno#define	ECR_EXC_DEF_MASK	0xf000	/* Excessive deferrals */
87179592Sbenno#define	ECR_EXC_DEF_SHIFT	12
88179592Sbenno
89179592Sbenno/* Bank 0, Offset 0x8: Memory Information Register */
90179592Sbenno#define	MIR			0x8
91179592Sbenno#define	MIR_SIZE_MASK		0x00ff	/* Memory size (2k pages) */
92179592Sbenno#define	MIR_SIZE_SHIFT		0
93179592Sbenno#define	MIR_FREE_MASK		0xff00	/* Memory free (2k pages) */
94179592Sbenno#define	MIR_FREE_SHIFT		8
95179592Sbenno#define	MIR_PAGE_SIZE		2048
96179592Sbenno
97179592Sbenno/* Bank 0, Offset 0xa: Receive/PHY Control Reigster */
98179592Sbenno#define	RPCR			0xa
99179592Sbenno#define	RPCR_ANEG		0x0800	/* Put PHY in autonegotiation mode */
100179592Sbenno#define	RPCR_DPLX		0x1000	/* Put PHY in full-duplex mode */
101179592Sbenno#define	RPCR_SPEED		0x2000	/* Manual speed selection */
102179592Sbenno#define	RPCR_LSA_MASK		0x00e0	/* Select LED A function */
103179592Sbenno#define	RPCR_LSA_SHIFT		5
104179592Sbenno#define	RPCR_LSB_MASK		0x001c	/* Select LED B function */
105179592Sbenno#define	RPCR_LSB_SHIFT		2
106179592Sbenno#define	RPCR_LED_LINK_ANY	0x0	/* 10baseT or 100baseTX link detected */
107179592Sbenno#define	RPCR_LED_LINK_10	0x2	/* 10baseT link detected */
108179592Sbenno#define	RPCR_LED_LINK_FDX	0x3	/* Full-duplex link detected */
109179592Sbenno#define	RPCR_LED_LINK_100	0x5	/* 100baseTX link detected */
110179592Sbenno#define	RPCR_LED_ACT_ANY	0x4	/* TX or RX activity detected */
111179592Sbenno#define	RPCR_LED_ACT_RX		0x6	/* RX activity detected */
112179592Sbenno#define	RPCR_LED_ACT_TX		0x7	/* TX activity detected */
113179592Sbenno
114179592Sbenno/* Bank 1, Offset 0x0: Configuration Register */
115179592Sbenno#define	CR			0x0
116179592Sbenno#define	CR_EXT_PHY		0x0200	/* Enable/disable external PHY */
117179592Sbenno#define	CR_GPCNTRL		0x0400	/* Inverse drives nCNTRL pin */
118179592Sbenno#define	CR_NO_WAIT		0x1000	/* Do not request additional waits */
119179592Sbenno#define	CR_EPH_POWER_EN		0x8000	/* Disable/enable low power mode */
120179592Sbenno
121179592Sbenno/* Bank 1, Offset 0x2: Base Address Register */
122179592Sbenno#define	BAR			0x2
123179592Sbenno#define	BAR_HIGH_MASK		0xe000
124179592Sbenno#define	BAR_LOW_MASK		0x1f00
125179592Sbenno#define	BAR_LOW_SHIFT		4
126179592Sbenno#define	BAR_ADDRESS(val)	\
127179592Sbenno	((val & BAR_HIGH_MASK) | ((val & BAR_LOW_MASK) >> BAR_LOW_SHIFT))
128179592Sbenno
129179592Sbenno/* Bank 1, Offsets 0x4: Individual Address Registers */
130179592Sbenno#define	IAR0			0x4
131179592Sbenno#define	IAR1			0x5
132179592Sbenno#define	IAR2			0x6
133179592Sbenno#define	IAR3			0x7
134179592Sbenno#define	IAR4			0x8
135179592Sbenno#define	IAR5			0x9
136179592Sbenno
137179592Sbenno/* Bank 1, Offset 0xa: General Purpose Register */
138179592Sbenno#define	GPR			0xa
139179592Sbenno
140179592Sbenno/* Bank 1, Offset 0xc: Control Register */
141179592Sbenno#define	CTR			0xa
142179592Sbenno#define	CTR_STORE		0x0001	/* Store registers to EEPROM */
143179592Sbenno#define	CTR_RELOAD		0x0002	/* Reload registers from EEPROM */
144179592Sbenno#define	CTR_EEPROM_SELECT	0x0004	/* Select registers to store/reload */
145179592Sbenno#define	CTR_TE_ENABLE		0x0020	/* TX error causes EPH interrupt */
146179592Sbenno#define	CTR_CR_ENABLE		0x0040	/* Ctr rollover causes EPH interrupt */
147179592Sbenno#define	CTR_LE_ENABLE		0x0080	/* Link error causes EPH interrupt */
148179592Sbenno#define	CTR_AUTO_RELEASE	0x0800	/* Automatically release TX packets */
149179592Sbenno#define	CTR_RCV_BAD		0x4000	/* Receive/discard bad CRC packets */
150179592Sbenno
151179592Sbenno/* Bank 2, Offset 0x0: MMU Command Register */
152179592Sbenno#define	MMUCR			0x0
153179592Sbenno#define	MMUCR_BUSY		0x0001	/* MMU is busy */
154179592Sbenno#define	MMUCR_CMD_NOOP		(0<<5)	/* No operation */
155179592Sbenno#define	MMUCR_CMD_TX_ALLOC	(1<<5)	/* Alloc TX memory (256b chunks) */
156179592Sbenno#define	MMUCR_CMD_MMU_RESET	(2<<5)	/* Reset MMU */
157179592Sbenno#define	MMUCR_CMD_REMOVE	(3<<5)	/* Remove frame from RX FIFO */
158179592Sbenno#define	MMUCR_CMD_RELEASE	(4<<5)	/* Remove and release from RX FIFO */
159179592Sbenno#define	MMUCR_CMD_RELEASE_PKT	(5<<5)	/* Release packet specified in PNR */
160179592Sbenno#define	MMUCR_CMD_ENQUEUE	(6<<5)	/* Enqueue packet for TX */
161179592Sbenno#define	MMUCR_CMD_TX_RESET	(7<<5)	/* Reset TX FIFOs */
162179592Sbenno
163179592Sbenno/* Bank 2, Offset 0x2: Packet Number Register */
164179592Sbenno#define	PNR			0x2
165179592Sbenno#define	PNR_MASK		0x3fff
166179592Sbenno
167179592Sbenno/* Bank 2, Offset 0x3: Allocation Result Register */
168179592Sbenno#define	ARR			0x3
169179592Sbenno#define	ARR_FAILED		0x8000	/* Last allocation request failed */
170179592Sbenno#define	ARR_MASK		0x3000
171179592Sbenno
172179592Sbenno/* Bank 2, Offset 0x4: FIFO Ports Register */
173179592Sbenno#define	FIFO_TX			0x4
174179592Sbenno#define	FIFO_RX			0x5
175179592Sbenno#define	FIFO_EMPTY		0x80	/* FIFO empty */
176179592Sbenno#define	FIFO_PACKET_MASK	0x3f	/* Packet number mask */
177179592Sbenno
178179592Sbenno/* Bank 2, Offset 0x6: Pointer Register */
179179592Sbenno#define	PTR			0x6
180179592Sbenno#define	PTR_MASK		0x07ff	/* Address accessible within TX/RX */
181179592Sbenno#define	PTR_NOT_EMPTY		0x0800	/* Write Data FIFO not empty */
182179592Sbenno#define	PTR_ETEN		0x1000	/* Enable early TX underrun detection */
183179592Sbenno#define	PTR_READ		0x2000	/* Set read/write */
184179592Sbenno#define	PTR_AUTO_INCR		0x4000	/* Auto increment on read/write */
185179592Sbenno#define	PTR_RCV			0x8000	/* Read/write to/from RX/TX */
186179592Sbenno
187179592Sbenno/* Bank 2, Offset 0x8: Data Registers */
188179592Sbenno#define	DATA0			0x8
189179592Sbenno#define	DATA1			0xa
190179592Sbenno
191179592Sbenno/* Bank 2, Offset 0xc: Interrupt Status Registers */
192179592Sbenno#define	IST			0xc	/* read only */
193179592Sbenno#define	ACK			0xc	/* write only */
194179592Sbenno#define	MSK			0xd
195179592Sbenno
196179592Sbenno#define	RCV_INT			0x0001	/* RX */
197179592Sbenno#define	TX_INT			0x0002	/* TX */
198179592Sbenno#define	TX_EMPTY_INT		0x0004	/* TX empty */
199179592Sbenno#define	ALLOC_INT		0x0008	/* Allocation complete */
200179592Sbenno#define	RX_OVRN_INT		0x0010	/* RX overrun */
201179592Sbenno#define	EPH_INT			0x0020	/* EPH interrupt */
202179592Sbenno#define	ERCV_INT		0x0040	/* Early RX */
203179592Sbenno#define	MD_INT			0x0080	/* MII */
204179592Sbenno
205179592Sbenno#define	IST_PRINTF		"\20\01RCV\02TX\03TX_EMPTY\04ALLOC" \
206179592Sbenno				"\05RX_OVRN\06EPH\07ERCV\10MD"
207179592Sbenno
208179592Sbenno/* Bank 3, Offset 0x0: Multicast Table Registers */
209179592Sbenno#define	MT			0x0
210179592Sbenno
211179592Sbenno/* Bank 3, Offset 0x8: Management Interface */
212179592Sbenno#define	MGMT			0x8
213179592Sbenno#define	MGMT_MDO		0x0001	/* MII management output */
214179592Sbenno#define	MGMT_MDI		0x0002	/* MII management input */
215179592Sbenno#define	MGMT_MCLK		0x0004	/* MII management clock */
216179592Sbenno#define	MGMT_MDOE		0x0008	/* MII management output enable */
217179592Sbenno#define	MGMT_MSK_CRS100		0x4000	/* Disable CRS100 detection during TX */
218179592Sbenno
219179592Sbenno/* Bank 3, Offset 0xa: Revision Register */
220179592Sbenno#define	REV			0xa
221179592Sbenno#define	REV_CHIP_MASK		0x00f0	/* Chip ID */
222179592Sbenno#define	REV_CHIP_SHIFT		4
223179592Sbenno#define	REV_REV_MASK		0x000f	/* Revision ID */
224179592Sbenno#define	REV_REV_SHIFT		0
225179592Sbenno
226179592Sbenno#define	REV_CHIP_9192		3
227179592Sbenno#define	REV_CHIP_9194		4
228179592Sbenno#define	REV_CHIP_9195		5
229179592Sbenno#define	REV_CHIP_9196		6
230179592Sbenno#define	REV_CHIP_91100		7
231179592Sbenno#define	REV_CHIP_91100FD	8
232179592Sbenno#define	REV_CHIP_91110FD	9
233179592Sbenno
234179592Sbenno/* Bank 3, Offset 0xc: Early RCV Register */
235179592Sbenno#define	ERCV			0xc
236179592Sbenno#define	ERCV_THRESHOLD_MASK	0x001f	/* ERCV int threshold (64b chunks) */
237179592Sbenno#define	ERCV_RCV_DISCARD	0x0080	/* Discard packet being received */
238179592Sbenno
239179592Sbenno/* Control Byte */
240179592Sbenno#define	CTRL_CRC		0x10	/* Frame has CRC */
241179592Sbenno#define	CTRL_ODD		0x20	/* Frame has odd byte count */
242179592Sbenno
243179592Sbenno/* Receive Frame Status */
244179592Sbenno#define	RX_MULTCAST		0x0001	/* Frame was multicast */
245179592Sbenno#define	RX_HASH_MASK		0x007e	/* Hash value for multicast */
246179592Sbenno#define	RX_HASH_SHIFT		1
247179592Sbenno#define	RX_TOOSHORT		0x0400	/* Frame was too short */
248179592Sbenno#define	RX_TOOLNG		0x0800	/* Frame was too long */
249179592Sbenno#define	RX_ODDFRM		0x1000	/* Frame has odd number of bytes */
250179592Sbenno#define	RX_BADCRC		0x2000	/* Frame failed CRC */
251179592Sbenno#define	RX_BROADCAST		0x4000	/* Frame was broadcast */
252179592Sbenno#define	RX_ALGNERR		0x8000	/* Frame had alignment error */
253179592Sbenno#define	RX_LEN_MASK		0x07ff
254179592Sbenno
255179592Sbenno/* Length of status word + byte count + control bytes for packets */
256179592Sbenno#define	PKT_CTRL_DATA_LEN	6
257179592Sbenno
258179592Sbenno/* Number of times to spin on TX allocations */
259179592Sbenno#define	TX_ALLOC_WAIT_TIME	1000
260179592Sbenno
261179592Sbenno#endif /* IF_SMCREG_H_ */
262