if_sisreg.h revision 89296
150974Swpaul/* 250974Swpaul * Copyright (c) 1997, 1998, 1999 350974Swpaul * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 450974Swpaul * 550974Swpaul * Redistribution and use in source and binary forms, with or without 650974Swpaul * modification, are permitted provided that the following conditions 750974Swpaul * are met: 850974Swpaul * 1. Redistributions of source code must retain the above copyright 950974Swpaul * notice, this list of conditions and the following disclaimer. 1050974Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1150974Swpaul * notice, this list of conditions and the following disclaimer in the 1250974Swpaul * documentation and/or other materials provided with the distribution. 1350974Swpaul * 3. All advertising materials mentioning features or use of this software 1450974Swpaul * must display the following acknowledgement: 1550974Swpaul * This product includes software developed by Bill Paul. 1650974Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1750974Swpaul * may be used to endorse or promote products derived from this software 1850974Swpaul * without specific prior written permission. 1950974Swpaul * 2050974Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2150974Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2250974Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2350974Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2450974Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2550974Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2650974Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2750974Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2850974Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2950974Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3050974Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3150974Swpaul * 3250974Swpaul * $FreeBSD: head/sys/pci/if_sisreg.h 89296 2002-01-12 21:12:17Z wpaul $ 3350974Swpaul */ 3450974Swpaul 3550974Swpaul/* 3650974Swpaul * Register definitions for the SiS 900 and SiS 7016 chipsets. The 3750974Swpaul * 7016 is actually an older chip and some of its registers differ 3850974Swpaul * from the 900, however the core operational registers are the same: 3950974Swpaul * the differences lie in the OnNow/Wake on LAN stuff which we don't 4050974Swpaul * use anyway. The 7016 needs an external MII compliant PHY while the 4150974Swpaul * SiS 900 has one built in. All registers are 32-bits wide. 4250974Swpaul */ 4350974Swpaul 4450974Swpaul/* Registers common to SiS 900 and SiS 7016 */ 4550974Swpaul#define SIS_CSR 0x00 4650974Swpaul#define SIS_CFG 0x04 4750974Swpaul#define SIS_EECTL 0x08 4850974Swpaul#define SIS_PCICTL 0x0C 4950974Swpaul#define SIS_ISR 0x10 5050974Swpaul#define SIS_IMR 0x14 5150974Swpaul#define SIS_IER 0x18 5250974Swpaul#define SIS_PHYCTL 0x1C 5350974Swpaul#define SIS_TX_LISTPTR 0x20 5450974Swpaul#define SIS_TX_CFG 0x24 5550974Swpaul#define SIS_RX_LISTPTR 0x30 5650974Swpaul#define SIS_RX_CFG 0x34 5750974Swpaul#define SIS_FLOWCTL 0x38 5850974Swpaul#define SIS_RXFILT_CTL 0x48 5950974Swpaul#define SIS_RXFILT_DATA 0x4C 6050974Swpaul#define SIS_PWRMAN_CTL 0xB0 6150974Swpaul#define SIS_PWERMAN_WKUP_EVENT 0xB4 6250974Swpaul#define SIS_WKUP_FRAME_CRC 0xBC 6350974Swpaul#define SIS_WKUP_FRAME_MASK0 0xC0 6450974Swpaul#define SIS_WKUP_FRAME_MASKXX 0xEC 6550974Swpaul 6650974Swpaul/* SiS 7016 specific registers */ 6750974Swpaul#define SIS_SILICON_REV 0x5C 6850974Swpaul#define SIS_MIB_CTL0 0x60 6950974Swpaul#define SIS_MIB_CTL1 0x64 7050974Swpaul#define SIS_MIB_CTL2 0x68 7150974Swpaul#define SIS_MIB_CTL3 0x6C 7250974Swpaul#define SIS_MIB 0x80 7350974Swpaul#define SIS_LINKSTS 0xA0 7450974Swpaul#define SIS_TIMEUNIT 0xA4 7550974Swpaul#define SIS_GPIO 0xB8 7650974Swpaul 7762672Swpaul/* NS DP83815 registers */ 7872813Swpaul#define NS_CLKRUN 0x3C 7962672Swpaul#define NS_BMCR 0x80 8062672Swpaul#define NS_BMSR 0x84 8162672Swpaul#define NS_PHYIDR1 0x88 8262672Swpaul#define NS_PHYIDR2 0x8C 8362672Swpaul#define NS_ANAR 0x90 8462672Swpaul#define NS_ANLPAR 0x94 8562672Swpaul#define NS_ANER 0x98 8662672Swpaul#define NS_ANNPTR 0x9C 8762672Swpaul 8864963Swpaul#define NS_PHY_CR 0xE4 8964963Swpaul#define NS_PHY_10BTSCR 0xE8 9064963Swpaul#define NS_PHY_PAGE 0xCC 9164963Swpaul#define NS_PHY_EXTCFG 0xF0 9264963Swpaul#define NS_PHY_DSPCFG 0xF4 9364963Swpaul#define NS_PHY_SDCFG 0xF8 9464963Swpaul#define NS_PHY_TDATA 0xFC 9564963Swpaul 9672813Swpaul#define NS_CLKRUN_PMESTS 0x00008000 9772813Swpaul#define NS_CLKRUN_PMEENB 0x00000100 9872813Swpaul#define NS_CLNRUN_CLKRUN_ENB 0x00000001 9972813Swpaul 10050974Swpaul#define SIS_CSR_TX_ENABLE 0x00000001 10150974Swpaul#define SIS_CSR_TX_DISABLE 0x00000002 10250974Swpaul#define SIS_CSR_RX_ENABLE 0x00000004 10350974Swpaul#define SIS_CSR_RX_DISABLE 0x00000008 10450974Swpaul#define SIS_CSR_TX_RESET 0x00000010 10550974Swpaul#define SIS_CSR_RX_RESET 0x00000020 10650974Swpaul#define SIS_CSR_SOFTINTR 0x00000080 10750974Swpaul#define SIS_CSR_RESET 0x00000100 10889296Swpaul#define SIS_CSR_ACCESS_MODE 0x00000200 10989296Swpaul#define SIS_CSR_RELOAD 0x00000400 11050974Swpaul 11150974Swpaul#define SIS_CFG_BIGENDIAN 0x00000001 11250974Swpaul#define SIS_CFG_PERR_DETECT 0x00000008 11350974Swpaul#define SIS_CFG_DEFER_DISABLE 0x00000010 11450974Swpaul#define SIS_CFG_OUTOFWIN_TIMER 0x00000020 11550974Swpaul#define SIS_CFG_SINGLE_BACKOFF 0x00000040 11650974Swpaul#define SIS_CFG_PCIREQ_ALG 0x00000080 11750974Swpaul 11850974Swpaul#define SIS_EECTL_DIN 0x00000001 11950974Swpaul#define SIS_EECTL_DOUT 0x00000002 12050974Swpaul#define SIS_EECTL_CLK 0x00000004 12150974Swpaul#define SIS_EECTL_CSEL 0x00000008 12250974Swpaul 12350974Swpaul#define SIS_EECMD_WRITE 0x140 12450974Swpaul#define SIS_EECMD_READ 0x180 12550974Swpaul#define SIS_EECMD_ERASE 0x1c0 12650974Swpaul 12750974Swpaul#define SIS_EE_NODEADDR 0x8 12862672Swpaul#define NS_EE_NODEADDR 0x6 12950974Swpaul 13050974Swpaul#define SIS_PCICTL_SRAMADDR 0x0000001F 13150974Swpaul#define SIS_PCICTL_RAMTSTENB 0x00000020 13250974Swpaul#define SIS_PCICTL_TXTSTENB 0x00000040 13350974Swpaul#define SIS_PCICTL_RXTSTENB 0x00000080 13450974Swpaul#define SIS_PCICTL_BMTSTENB 0x00000200 13550974Swpaul#define SIS_PCICTL_RAMADDR 0x001F0000 13650974Swpaul#define SIS_PCICTL_ROMTIME 0x0F000000 13750974Swpaul#define SIS_PCICTL_DISCTEST 0x40000000 13850974Swpaul 13950974Swpaul#define SIS_ISR_RX_OK 0x00000001 14050974Swpaul#define SIS_ISR_RX_DESC_OK 0x00000002 14150974Swpaul#define SIS_ISR_RX_ERR 0x00000004 14250974Swpaul#define SIS_ISR_RX_EARLY 0x00000008 14350974Swpaul#define SIS_ISR_RX_IDLE 0x00000010 14450974Swpaul#define SIS_ISR_RX_OFLOW 0x00000020 14550974Swpaul#define SIS_ISR_TX_OK 0x00000040 14650974Swpaul#define SIS_ISR_TX_DESC_OK 0x00000080 14750974Swpaul#define SIS_ISR_TX_ERR 0x00000100 14850974Swpaul#define SIS_ISR_TX_IDLE 0x00000200 14950974Swpaul#define SIS_ISR_TX_UFLOW 0x00000400 15050974Swpaul#define SIS_ISR_SOFTINTR 0x00000800 15150974Swpaul#define SIS_ISR_HIBITS 0x00008000 15250974Swpaul#define SIS_ISR_RX_FIFO_OFLOW 0x00010000 15350974Swpaul#define SIS_ISR_TGT_ABRT 0x00100000 15450974Swpaul#define SIS_ISR_BM_ABRT 0x00200000 15550974Swpaul#define SIS_ISR_SYSERR 0x00400000 15650974Swpaul#define SIS_ISR_PARITY_ERR 0x00800000 15750974Swpaul#define SIS_ISR_RX_RESET_DONE 0x01000000 15850974Swpaul#define SIS_ISR_TX_RESET_DONE 0x02000000 15950974Swpaul#define SIS_ISR_TX_PAUSE_START 0x04000000 16050974Swpaul#define SIS_ISR_TX_PAUSE_DONE 0x08000000 16150974Swpaul#define SIS_ISR_WAKE_EVENT 0x10000000 16250974Swpaul 16350974Swpaul#define SIS_IMR_RX_OK 0x00000001 16450974Swpaul#define SIS_IMR_RX_DESC_OK 0x00000002 16550974Swpaul#define SIS_IMR_RX_ERR 0x00000004 16650974Swpaul#define SIS_IMR_RX_EARLY 0x00000008 16750974Swpaul#define SIS_IMR_RX_IDLE 0x00000010 16850974Swpaul#define SIS_IMR_RX_OFLOW 0x00000020 16950974Swpaul#define SIS_IMR_TX_OK 0x00000040 17050974Swpaul#define SIS_IMR_TX_DESC_OK 0x00000080 17150974Swpaul#define SIS_IMR_TX_ERR 0x00000100 17250974Swpaul#define SIS_IMR_TX_IDLE 0x00000200 17350974Swpaul#define SIS_IMR_TX_UFLOW 0x00000400 17450974Swpaul#define SIS_IMR_SOFTINTR 0x00000800 17550974Swpaul#define SIS_IMR_HIBITS 0x00008000 17650974Swpaul#define SIS_IMR_RX_FIFO_OFLOW 0x00010000 17750974Swpaul#define SIS_IMR_TGT_ABRT 0x00100000 17850974Swpaul#define SIS_IMR_BM_ABRT 0x00200000 17950974Swpaul#define SIS_IMR_SYSERR 0x00400000 18050974Swpaul#define SIS_IMR_PARITY_ERR 0x00800000 18150974Swpaul#define SIS_IMR_RX_RESET_DONE 0x01000000 18250974Swpaul#define SIS_IMR_TX_RESET_DONE 0x02000000 18350974Swpaul#define SIS_IMR_TX_PAUSE_START 0x04000000 18450974Swpaul#define SIS_IMR_TX_PAUSE_DONE 0x08000000 18550974Swpaul#define SIS_IMR_WAKE_EVENT 0x10000000 18650974Swpaul 18750974Swpaul#define SIS_INTRS \ 18850974Swpaul (SIS_IMR_RX_OFLOW|SIS_IMR_TX_UFLOW|SIS_IMR_TX_OK|\ 18950974Swpaul SIS_IMR_TX_IDLE|SIS_IMR_RX_OK|SIS_IMR_RX_ERR|\ 19086984Sluigi SIS_IMR_RX_IDLE|\ 19150974Swpaul SIS_IMR_SYSERR) 19250974Swpaul 19350974Swpaul#define SIS_IER_INTRENB 0x00000001 19450974Swpaul 19550974Swpaul#define SIS_PHYCTL_ACCESS 0x00000010 19650974Swpaul#define SIS_PHYCTL_OP 0x00000020 19750974Swpaul#define SIS_PHYCTL_REGADDR 0x000007C0 19850974Swpaul#define SIS_PHYCTL_PHYADDR 0x0000F800 19950974Swpaul#define SIS_PHYCTL_PHYDATA 0xFFFF0000 20050974Swpaul 20150974Swpaul#define SIS_PHYOP_READ 0x00000020 20250974Swpaul#define SIS_PHYOP_WRITE 0x00000000 20350974Swpaul 20450974Swpaul#define SIS_TXCFG_DRAIN_THRESH 0x0000003F /* 32-byte units */ 20550974Swpaul#define SIS_TXCFG_FILL_THRESH 0x00003F00 /* 32-byte units */ 20650974Swpaul#define SIS_TXCFG_DMABURST 0x00700000 20750974Swpaul#define SIS_TXCFG_AUTOPAD 0x10000000 20850974Swpaul#define SIS_TXCFG_LOOPBK 0x20000000 20950974Swpaul#define SIS_TXCFG_IGN_HBEAT 0x40000000 21050974Swpaul#define SIS_TXCFG_IGN_CARR 0x80000000 21150974Swpaul 21250974Swpaul#define SIS_TXCFG_DRAIN(x) (((x) >> 5) & SIS_TXCFG_DRAIN_THRESH) 21350974Swpaul#define SIS_TXCFG_FILL(x) ((((x) >> 5) << 8) & SIS_TXCFG_FILL_THRESH) 21450974Swpaul 21550974Swpaul#define SIS_TXDMA_512BYTES 0x00000000 21650974Swpaul#define SIS_TXDMA_4BYTES 0x00100000 21750974Swpaul#define SIS_TXDMA_8BYTES 0x00200000 21850974Swpaul#define SIS_TXDMA_16BYTES 0x00300000 21950974Swpaul#define SIS_TXDMA_32BYTES 0x00400000 22050974Swpaul#define SIS_TXDMA_64BYTES 0x00500000 22150974Swpaul#define SIS_TXDMA_128BYTES 0x00600000 22250974Swpaul#define SIS_TXDMA_256BYTES 0x00700000 22350974Swpaul 22464963Swpaul#define SIS_TXCFG_100 \ 22550974Swpaul (SIS_TXDMA_64BYTES|SIS_TXCFG_AUTOPAD|\ 22664963Swpaul SIS_TXCFG_FILL(64)|SIS_TXCFG_DRAIN(1536)) 22750974Swpaul 22864963Swpaul#define SIS_TXCFG_10 \ 22964963Swpaul (SIS_TXDMA_32BYTES|SIS_TXCFG_AUTOPAD|\ 23064963Swpaul SIS_TXCFG_FILL(64)|SIS_TXCFG_DRAIN(1536)) 23164963Swpaul 23250974Swpaul#define SIS_RXCFG_DRAIN_THRESH 0x0000003E /* 8-byte units */ 23350974Swpaul#define SIS_RXCFG_DMABURST 0x00700000 23450974Swpaul#define SIS_RXCFG_RX_JABBER 0x08000000 23550974Swpaul#define SIS_RXCFG_RX_TXPKTS 0x10000000 23650974Swpaul#define SIS_RXCFG_RX_RUNTS 0x40000000 23750974Swpaul#define SIS_RXCFG_RX_GIANTS 0x80000000 23850974Swpaul 23950974Swpaul#define SIS_RXCFG_DRAIN(x) ((((x) >> 3) << 1) & SIS_RXCFG_DRAIN_THRESH) 24050974Swpaul 24150974Swpaul#define SIS_RXDMA_512BYTES 0x00000000 24250974Swpaul#define SIS_RXDMA_4BYTES 0x00100000 24350974Swpaul#define SIS_RXDMA_8BYTES 0x00200000 24450974Swpaul#define SIS_RXDMA_16BYTES 0x00300000 24550974Swpaul#define SIS_RXDMA_32BYTES 0x00400000 24650974Swpaul#define SIS_RXDMA_64BYTES 0x00500000 24750974Swpaul#define SIS_RXDMA_128BYTES 0x00600000 24850974Swpaul#define SIS_RXDMA_256BYTES 0x00700000 24950974Swpaul 25050974Swpaul#define SIS_RXCFG \ 25150974Swpaul (SIS_RXCFG_DRAIN(64)|SIS_RXDMA_256BYTES) 25250974Swpaul 25350974Swpaul#define SIS_RXFILTCTL_ADDR 0x000F0000 25462672Swpaul#define NS_RXFILTCTL_MCHASH 0x00200000 25562672Swpaul#define NS_RXFILTCTL_ARP 0x00400000 25662672Swpaul#define NS_RXFILTCTL_PERFECT 0x08000000 25750974Swpaul#define SIS_RXFILTCTL_ALLPHYS 0x10000000 25850974Swpaul#define SIS_RXFILTCTL_ALLMULTI 0x20000000 25950974Swpaul#define SIS_RXFILTCTL_BROAD 0x40000000 26050974Swpaul#define SIS_RXFILTCTL_ENABLE 0x80000000 26150974Swpaul 26250974Swpaul#define SIS_FILTADDR_PAR0 0x00000000 26350974Swpaul#define SIS_FILTADDR_PAR1 0x00010000 26450974Swpaul#define SIS_FILTADDR_PAR2 0x00020000 26550974Swpaul#define SIS_FILTADDR_MAR0 0x00040000 26650974Swpaul#define SIS_FILTADDR_MAR1 0x00050000 26750974Swpaul#define SIS_FILTADDR_MAR2 0x00060000 26850974Swpaul#define SIS_FILTADDR_MAR3 0x00070000 26950974Swpaul#define SIS_FILTADDR_MAR4 0x00080000 27050974Swpaul#define SIS_FILTADDR_MAR5 0x00090000 27150974Swpaul#define SIS_FILTADDR_MAR6 0x000A0000 27250974Swpaul#define SIS_FILTADDR_MAR7 0x000B0000 27350974Swpaul 27462672Swpaul#define NS_FILTADDR_PAR0 0x00000000 27562672Swpaul#define NS_FILTADDR_PAR1 0x00000002 27662672Swpaul#define NS_FILTADDR_PAR2 0x00000004 27762672Swpaul 27862672Swpaul#define NS_FILTADDR_FMEM_LO 0x00000200 27962672Swpaul#define NS_FILTADDR_FMEM_HI 0x000003FE 28062672Swpaul 28150974Swpaul/* 28250974Swpaul * DMA descriptor structures. The first part of the descriptor 28350974Swpaul * is the hardware descriptor format, which is just three longwords. 28450974Swpaul * After this, we include some additional structure members for 28550974Swpaul * use by the driver. Note that for this structure will be a different 28650974Swpaul * size on the alpha, but that's okay as long as it's a multiple of 4 28750974Swpaul * bytes in size. 28850974Swpaul */ 28950974Swpaulstruct sis_desc { 29050974Swpaul /* SiS hardware descriptor section */ 29150974Swpaul u_int32_t sis_next; 29250974Swpaul u_int32_t sis_cmdsts; 29350974Swpaul#define sis_rxstat sis_cmdsts 29450974Swpaul#define sis_txstat sis_cmdsts 29550974Swpaul#define sis_ctl sis_cmdsts 29650974Swpaul u_int32_t sis_ptr; 29750974Swpaul /* Driver software section */ 29850974Swpaul struct mbuf *sis_mbuf; 29950974Swpaul struct sis_desc *sis_nextdesc; 30081713Swpaul bus_dmamap_t sis_map; 30150974Swpaul}; 30250974Swpaul 30350974Swpaul#define SIS_CMDSTS_BUFLEN 0x00000FFF 30450974Swpaul#define SIS_CMDSTS_PKT_OK 0x08000000 30550974Swpaul#define SIS_CMDSTS_CRC 0x10000000 30650974Swpaul#define SIS_CMDSTS_INTR 0x20000000 30750974Swpaul#define SIS_CMDSTS_MORE 0x40000000 30850974Swpaul#define SIS_CMDSTS_OWN 0x80000000 30950974Swpaul 31050974Swpaul#define SIS_LASTDESC(x) (!((x)->sis_ctl & SIS_CMDSTS_MORE))) 31150974Swpaul#define SIS_OWNDESC(x) ((x)->sis_ctl & SIS_CMDSTS_OWN) 31287973Speter#define SIS_INC(x, y) { if (++(x) == y) x = 0; } 31350974Swpaul#define SIS_RXBYTES(x) ((x)->sis_ctl & SIS_CMDSTS_BUFLEN) 31450974Swpaul 31550974Swpaul#define SIS_RXSTAT_COLL 0x00010000 31650974Swpaul#define SIS_RXSTAT_LOOPBK 0x00020000 31750974Swpaul#define SIS_RXSTAT_ALIGNERR 0x00040000 31850974Swpaul#define SIS_RXSTAT_CRCERR 0x00080000 31950974Swpaul#define SIS_RXSTAT_SYMBOLERR 0x00100000 32050974Swpaul#define SIS_RXSTAT_RUNT 0x00200000 32150974Swpaul#define SIS_RXSTAT_GIANT 0x00400000 32250974Swpaul#define SIS_RXSTAT_DSTCLASS 0x01800000 32350974Swpaul#define SIS_RXSTAT_OVERRUN 0x02000000 32450974Swpaul#define SIS_RXSTAT_RX_ABORT 0x04000000 32550974Swpaul 32650974Swpaul#define SIS_DSTCLASS_REJECT 0x00000000 32750974Swpaul#define SIS_DSTCLASS_UNICAST 0x00800000 32850974Swpaul#define SIS_DSTCLASS_MULTICAST 0x01000000 32950974Swpaul#define SIS_DSTCLASS_BROADCAST 0x02000000 33050974Swpaul 33150974Swpaul#define SIS_TXSTAT_COLLCNT 0x000F0000 33250974Swpaul#define SIS_TXSTAT_EXCESSCOLLS 0x00100000 33350974Swpaul#define SIS_TXSTAT_OUTOFWINCOLL 0x00200000 33450974Swpaul#define SIS_TXSTAT_EXCESS_DEFER 0x00400000 33550974Swpaul#define SIS_TXSTAT_DEFERED 0x00800000 33650974Swpaul#define SIS_TXSTAT_CARR_LOST 0x01000000 33750974Swpaul#define SIS_TXSTAT_UNDERRUN 0x02000000 33850974Swpaul#define SIS_TXSTAT_TX_ABORT 0x04000000 33950974Swpaul 34050974Swpaul#define SIS_RX_LIST_CNT 64 34150974Swpaul#define SIS_TX_LIST_CNT 128 34250974Swpaul 34381713Swpaul#define SIS_RX_LIST_SZ SIS_RX_LIST_CNT * sizeof(struct sis_desc) 34481713Swpaul#define SIS_TX_LIST_SZ SIS_TX_LIST_CNT * sizeof(struct sis_desc) 34581713Swpaul 34650974Swpaulstruct sis_list_data { 34781713Swpaul#ifdef foo 34850974Swpaul struct sis_desc sis_rx_list[SIS_RX_LIST_CNT]; 34950974Swpaul struct sis_desc sis_tx_list[SIS_TX_LIST_CNT]; 35081713Swpaul#endif 35181713Swpaul struct sis_desc *sis_rx_list; 35281713Swpaul struct sis_desc *sis_tx_list; 35381713Swpaul bus_dma_tag_t sis_rx_tag; 35481713Swpaul bus_dmamap_t sis_rx_dmamap; 35581713Swpaul bus_dma_tag_t sis_tx_tag; 35681713Swpaul bus_dmamap_t sis_tx_dmamap; 35750974Swpaul}; 35850974Swpaul 35950974Swpaulstruct sis_ring_data { 36050974Swpaul int sis_rx_prod; 36150974Swpaul int sis_tx_prod; 36250974Swpaul int sis_tx_cons; 36350974Swpaul int sis_tx_cnt; 36481713Swpaul u_int32_t sis_rx_paddr; 36581713Swpaul u_int32_t sis_tx_paddr; 36650974Swpaul}; 36750974Swpaul 36850974Swpaul 36950974Swpaul/* 37050974Swpaul * SiS PCI vendor ID. 37150974Swpaul */ 37250974Swpaul#define SIS_VENDORID 0x1039 37350974Swpaul 37450974Swpaul/* 37550974Swpaul * SiS PCI device IDs 37650974Swpaul */ 37750974Swpaul#define SIS_DEVICEID_900 0x0900 37850974Swpaul#define SIS_DEVICEID_7016 0x7016 37950974Swpaul 38062672Swpaul/* 38172197Swpaul * SiS 900 PCI revision codes. 38272197Swpaul */ 38372197Swpaul#define SIS_REV_630E 0x0081 38472197Swpaul#define SIS_REV_630S 0x0082 38572197Swpaul#define SIS_REV_630EA1 0x0083 38689296Swpaul#define SIS_REV_630ET 0x0083 38789296Swpaul#define SIS_REV_635 0x0090 38872197Swpaul 38972197Swpaul/* 39062672Swpaul * NatSemi vendor ID 39162672Swpaul */ 39262672Swpaul#define NS_VENDORID 0x100B 39362672Swpaul 39462672Swpaul/* 39562672Swpaul * DP83815 device ID 39662672Swpaul */ 39762672Swpaul#define NS_DEVICEID_DP83815 0x0020 39862672Swpaul 39950974Swpaulstruct sis_type { 40050974Swpaul u_int16_t sis_vid; 40150974Swpaul u_int16_t sis_did; 40250974Swpaul char *sis_name; 40350974Swpaul}; 40450974Swpaul 40550974Swpaul#define SIS_TYPE_900 1 40650974Swpaul#define SIS_TYPE_7016 2 40762672Swpaul#define SIS_TYPE_83815 3 40850974Swpaul 40950974Swpaulstruct sis_softc { 41050974Swpaul struct arpcom arpcom; /* interface info */ 41150974Swpaul bus_space_handle_t sis_bhandle; 41250974Swpaul bus_space_tag_t sis_btag; 41350974Swpaul struct resource *sis_res; 41450974Swpaul struct resource *sis_irq; 41550974Swpaul void *sis_intrhand; 41650974Swpaul device_t sis_miibus; 41750974Swpaul u_int8_t sis_unit; 41850974Swpaul u_int8_t sis_type; 41989296Swpaul u_int8_t sis_rev; 42064963Swpaul u_int8_t sis_link; 42181713Swpaul struct sis_list_data sis_ldata; 42281713Swpaul bus_dma_tag_t sis_parent_tag; 42381713Swpaul bus_dma_tag_t sis_tag; 42450974Swpaul struct sis_ring_data sis_cdata; 42550974Swpaul struct callout_handle sis_stat_ch; 42687902Sluigi#ifdef DEVICE_POLLING 42787902Sluigi int rxcycles; 42887902Sluigi#endif 42967087Swpaul struct mtx sis_mtx; 43050974Swpaul}; 43150974Swpaul 43272200Sbmilekic#define SIS_LOCK(_sc) mtx_lock(&(_sc)->sis_mtx) 43372200Sbmilekic#define SIS_UNLOCK(_sc) mtx_unlock(&(_sc)->sis_mtx) 43467087Swpaul 43550974Swpaul/* 43650974Swpaul * register space access macros 43750974Swpaul */ 43850974Swpaul#define CSR_WRITE_4(sc, reg, val) \ 43950974Swpaul bus_space_write_4(sc->sis_btag, sc->sis_bhandle, reg, val) 44050974Swpaul 44150974Swpaul#define CSR_READ_4(sc, reg) \ 44250974Swpaul bus_space_read_4(sc->sis_btag, sc->sis_bhandle, reg) 44350974Swpaul 44489296Swpaul#define CSR_READ_2(sc, reg) \ 44589296Swpaul bus_space_read_2(sc->sis_btag, sc->sis_bhandle, reg) 44689296Swpaul 44750974Swpaul#define SIS_TIMEOUT 1000 44850974Swpaul#define ETHER_ALIGN 2 44950974Swpaul#define SIS_RXLEN 1536 45050974Swpaul#define SIS_MIN_FRAMELEN 60 45150974Swpaul 45250974Swpaul/* 45350974Swpaul * PCI low memory base and low I/O base register, and 45450974Swpaul * other PCI registers. 45550974Swpaul */ 45650974Swpaul 45750974Swpaul#define SIS_PCI_VENDOR_ID 0x00 45850974Swpaul#define SIS_PCI_DEVICE_ID 0x02 45950974Swpaul#define SIS_PCI_COMMAND 0x04 46050974Swpaul#define SIS_PCI_STATUS 0x06 46150974Swpaul#define SIS_PCI_REVID 0x08 46250974Swpaul#define SIS_PCI_CLASSCODE 0x09 46350974Swpaul#define SIS_PCI_CACHELEN 0x0C 46450974Swpaul#define SIS_PCI_LATENCY_TIMER 0x0D 46550974Swpaul#define SIS_PCI_HEADER_TYPE 0x0E 46650974Swpaul#define SIS_PCI_LOIO 0x10 46750974Swpaul#define SIS_PCI_LOMEM 0x14 46850974Swpaul#define SIS_PCI_BIOSROM 0x30 46950974Swpaul#define SIS_PCI_INTLINE 0x3C 47050974Swpaul#define SIS_PCI_INTPIN 0x3D 47150974Swpaul#define SIS_PCI_MINGNT 0x3E 47250974Swpaul#define SIS_PCI_MINLAT 0x0F 47350974Swpaul#define SIS_PCI_RESETOPT 0x48 47450974Swpaul#define SIS_PCI_EEPROM_DATA 0x4C 47550974Swpaul 47650974Swpaul/* power management registers */ 47750974Swpaul#define SIS_PCI_CAPID 0x50 /* 8 bits */ 47850974Swpaul#define SIS_PCI_NEXTPTR 0x51 /* 8 bits */ 47950974Swpaul#define SIS_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 48050974Swpaul#define SIS_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 48150974Swpaul 48250974Swpaul#define SIS_PSTATE_MASK 0x0003 48350974Swpaul#define SIS_PSTATE_D0 0x0000 48450974Swpaul#define SIS_PSTATE_D1 0x0001 48550974Swpaul#define SIS_PSTATE_D2 0x0002 48650974Swpaul#define SIS_PSTATE_D3 0x0003 48750974Swpaul#define SIS_PME_EN 0x0010 48850974Swpaul#define SIS_PME_STATUS 0x8000 489