if_sisreg.h revision 62672
150974Swpaul/* 250974Swpaul * Copyright (c) 1997, 1998, 1999 350974Swpaul * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 450974Swpaul * 550974Swpaul * Redistribution and use in source and binary forms, with or without 650974Swpaul * modification, are permitted provided that the following conditions 750974Swpaul * are met: 850974Swpaul * 1. Redistributions of source code must retain the above copyright 950974Swpaul * notice, this list of conditions and the following disclaimer. 1050974Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1150974Swpaul * notice, this list of conditions and the following disclaimer in the 1250974Swpaul * documentation and/or other materials provided with the distribution. 1350974Swpaul * 3. All advertising materials mentioning features or use of this software 1450974Swpaul * must display the following acknowledgement: 1550974Swpaul * This product includes software developed by Bill Paul. 1650974Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1750974Swpaul * may be used to endorse or promote products derived from this software 1850974Swpaul * without specific prior written permission. 1950974Swpaul * 2050974Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2150974Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2250974Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2350974Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2450974Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2550974Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2650974Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2750974Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2850974Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2950974Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3050974Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3150974Swpaul * 3250974Swpaul * $FreeBSD: head/sys/pci/if_sisreg.h 62672 2000-07-06 06:02:04Z wpaul $ 3350974Swpaul */ 3450974Swpaul 3550974Swpaul/* 3650974Swpaul * Register definitions for the SiS 900 and SiS 7016 chipsets. The 3750974Swpaul * 7016 is actually an older chip and some of its registers differ 3850974Swpaul * from the 900, however the core operational registers are the same: 3950974Swpaul * the differences lie in the OnNow/Wake on LAN stuff which we don't 4050974Swpaul * use anyway. The 7016 needs an external MII compliant PHY while the 4150974Swpaul * SiS 900 has one built in. All registers are 32-bits wide. 4250974Swpaul */ 4350974Swpaul 4450974Swpaul/* Registers common to SiS 900 and SiS 7016 */ 4550974Swpaul#define SIS_CSR 0x00 4650974Swpaul#define SIS_CFG 0x04 4750974Swpaul#define SIS_EECTL 0x08 4850974Swpaul#define SIS_PCICTL 0x0C 4950974Swpaul#define SIS_ISR 0x10 5050974Swpaul#define SIS_IMR 0x14 5150974Swpaul#define SIS_IER 0x18 5250974Swpaul#define SIS_PHYCTL 0x1C 5350974Swpaul#define SIS_TX_LISTPTR 0x20 5450974Swpaul#define SIS_TX_CFG 0x24 5550974Swpaul#define SIS_RX_LISTPTR 0x30 5650974Swpaul#define SIS_RX_CFG 0x34 5750974Swpaul#define SIS_FLOWCTL 0x38 5850974Swpaul#define SIS_RXFILT_CTL 0x48 5950974Swpaul#define SIS_RXFILT_DATA 0x4C 6050974Swpaul#define SIS_PWRMAN_CTL 0xB0 6150974Swpaul#define SIS_PWERMAN_WKUP_EVENT 0xB4 6250974Swpaul#define SIS_WKUP_FRAME_CRC 0xBC 6350974Swpaul#define SIS_WKUP_FRAME_MASK0 0xC0 6450974Swpaul#define SIS_WKUP_FRAME_MASKXX 0xEC 6550974Swpaul 6650974Swpaul/* SiS 7016 specific registers */ 6750974Swpaul#define SIS_SILICON_REV 0x5C 6850974Swpaul#define SIS_MIB_CTL0 0x60 6950974Swpaul#define SIS_MIB_CTL1 0x64 7050974Swpaul#define SIS_MIB_CTL2 0x68 7150974Swpaul#define SIS_MIB_CTL3 0x6C 7250974Swpaul#define SIS_MIB 0x80 7350974Swpaul#define SIS_LINKSTS 0xA0 7450974Swpaul#define SIS_TIMEUNIT 0xA4 7550974Swpaul#define SIS_GPIO 0xB8 7650974Swpaul 7762672Swpaul/* NS DP83815 registers */ 7862672Swpaul#define NS_BMCR 0x80 7962672Swpaul#define NS_BMSR 0x84 8062672Swpaul#define NS_PHYIDR1 0x88 8162672Swpaul#define NS_PHYIDR2 0x8C 8262672Swpaul#define NS_ANAR 0x90 8362672Swpaul#define NS_ANLPAR 0x94 8462672Swpaul#define NS_ANER 0x98 8562672Swpaul#define NS_ANNPTR 0x9C 8662672Swpaul 8750974Swpaul#define SIS_CSR_TX_ENABLE 0x00000001 8850974Swpaul#define SIS_CSR_TX_DISABLE 0x00000002 8950974Swpaul#define SIS_CSR_RX_ENABLE 0x00000004 9050974Swpaul#define SIS_CSR_RX_DISABLE 0x00000008 9150974Swpaul#define SIS_CSR_TX_RESET 0x00000010 9250974Swpaul#define SIS_CSR_RX_RESET 0x00000020 9350974Swpaul#define SIS_CSR_SOFTINTR 0x00000080 9450974Swpaul#define SIS_CSR_RESET 0x00000100 9550974Swpaul 9650974Swpaul#define SIS_CFG_BIGENDIAN 0x00000001 9750974Swpaul#define SIS_CFG_PERR_DETECT 0x00000008 9850974Swpaul#define SIS_CFG_DEFER_DISABLE 0x00000010 9950974Swpaul#define SIS_CFG_OUTOFWIN_TIMER 0x00000020 10050974Swpaul#define SIS_CFG_SINGLE_BACKOFF 0x00000040 10150974Swpaul#define SIS_CFG_PCIREQ_ALG 0x00000080 10250974Swpaul 10350974Swpaul#define SIS_EECTL_DIN 0x00000001 10450974Swpaul#define SIS_EECTL_DOUT 0x00000002 10550974Swpaul#define SIS_EECTL_CLK 0x00000004 10650974Swpaul#define SIS_EECTL_CSEL 0x00000008 10750974Swpaul 10850974Swpaul#define SIS_EECMD_WRITE 0x140 10950974Swpaul#define SIS_EECMD_READ 0x180 11050974Swpaul#define SIS_EECMD_ERASE 0x1c0 11150974Swpaul 11250974Swpaul#define SIS_EE_NODEADDR 0x8 11362672Swpaul#define NS_EE_NODEADDR 0x6 11450974Swpaul 11550974Swpaul#define SIS_PCICTL_SRAMADDR 0x0000001F 11650974Swpaul#define SIS_PCICTL_RAMTSTENB 0x00000020 11750974Swpaul#define SIS_PCICTL_TXTSTENB 0x00000040 11850974Swpaul#define SIS_PCICTL_RXTSTENB 0x00000080 11950974Swpaul#define SIS_PCICTL_BMTSTENB 0x00000200 12050974Swpaul#define SIS_PCICTL_RAMADDR 0x001F0000 12150974Swpaul#define SIS_PCICTL_ROMTIME 0x0F000000 12250974Swpaul#define SIS_PCICTL_DISCTEST 0x40000000 12350974Swpaul 12450974Swpaul#define SIS_ISR_RX_OK 0x00000001 12550974Swpaul#define SIS_ISR_RX_DESC_OK 0x00000002 12650974Swpaul#define SIS_ISR_RX_ERR 0x00000004 12750974Swpaul#define SIS_ISR_RX_EARLY 0x00000008 12850974Swpaul#define SIS_ISR_RX_IDLE 0x00000010 12950974Swpaul#define SIS_ISR_RX_OFLOW 0x00000020 13050974Swpaul#define SIS_ISR_TX_OK 0x00000040 13150974Swpaul#define SIS_ISR_TX_DESC_OK 0x00000080 13250974Swpaul#define SIS_ISR_TX_ERR 0x00000100 13350974Swpaul#define SIS_ISR_TX_IDLE 0x00000200 13450974Swpaul#define SIS_ISR_TX_UFLOW 0x00000400 13550974Swpaul#define SIS_ISR_SOFTINTR 0x00000800 13650974Swpaul#define SIS_ISR_HIBITS 0x00008000 13750974Swpaul#define SIS_ISR_RX_FIFO_OFLOW 0x00010000 13850974Swpaul#define SIS_ISR_TGT_ABRT 0x00100000 13950974Swpaul#define SIS_ISR_BM_ABRT 0x00200000 14050974Swpaul#define SIS_ISR_SYSERR 0x00400000 14150974Swpaul#define SIS_ISR_PARITY_ERR 0x00800000 14250974Swpaul#define SIS_ISR_RX_RESET_DONE 0x01000000 14350974Swpaul#define SIS_ISR_TX_RESET_DONE 0x02000000 14450974Swpaul#define SIS_ISR_TX_PAUSE_START 0x04000000 14550974Swpaul#define SIS_ISR_TX_PAUSE_DONE 0x08000000 14650974Swpaul#define SIS_ISR_WAKE_EVENT 0x10000000 14750974Swpaul 14850974Swpaul#define SIS_IMR_RX_OK 0x00000001 14950974Swpaul#define SIS_IMR_RX_DESC_OK 0x00000002 15050974Swpaul#define SIS_IMR_RX_ERR 0x00000004 15150974Swpaul#define SIS_IMR_RX_EARLY 0x00000008 15250974Swpaul#define SIS_IMR_RX_IDLE 0x00000010 15350974Swpaul#define SIS_IMR_RX_OFLOW 0x00000020 15450974Swpaul#define SIS_IMR_TX_OK 0x00000040 15550974Swpaul#define SIS_IMR_TX_DESC_OK 0x00000080 15650974Swpaul#define SIS_IMR_TX_ERR 0x00000100 15750974Swpaul#define SIS_IMR_TX_IDLE 0x00000200 15850974Swpaul#define SIS_IMR_TX_UFLOW 0x00000400 15950974Swpaul#define SIS_IMR_SOFTINTR 0x00000800 16050974Swpaul#define SIS_IMR_HIBITS 0x00008000 16150974Swpaul#define SIS_IMR_RX_FIFO_OFLOW 0x00010000 16250974Swpaul#define SIS_IMR_TGT_ABRT 0x00100000 16350974Swpaul#define SIS_IMR_BM_ABRT 0x00200000 16450974Swpaul#define SIS_IMR_SYSERR 0x00400000 16550974Swpaul#define SIS_IMR_PARITY_ERR 0x00800000 16650974Swpaul#define SIS_IMR_RX_RESET_DONE 0x01000000 16750974Swpaul#define SIS_IMR_TX_RESET_DONE 0x02000000 16850974Swpaul#define SIS_IMR_TX_PAUSE_START 0x04000000 16950974Swpaul#define SIS_IMR_TX_PAUSE_DONE 0x08000000 17050974Swpaul#define SIS_IMR_WAKE_EVENT 0x10000000 17150974Swpaul 17250974Swpaul#define SIS_INTRS \ 17350974Swpaul (SIS_IMR_RX_OFLOW|SIS_IMR_TX_UFLOW|SIS_IMR_TX_OK|\ 17450974Swpaul SIS_IMR_TX_IDLE|SIS_IMR_RX_OK|SIS_IMR_RX_ERR|\ 17550974Swpaul SIS_IMR_SYSERR) 17650974Swpaul 17750974Swpaul#define SIS_IER_INTRENB 0x00000001 17850974Swpaul 17950974Swpaul#define SIS_PHYCTL_ACCESS 0x00000010 18050974Swpaul#define SIS_PHYCTL_OP 0x00000020 18150974Swpaul#define SIS_PHYCTL_REGADDR 0x000007C0 18250974Swpaul#define SIS_PHYCTL_PHYADDR 0x0000F800 18350974Swpaul#define SIS_PHYCTL_PHYDATA 0xFFFF0000 18450974Swpaul 18550974Swpaul#define SIS_PHYOP_READ 0x00000020 18650974Swpaul#define SIS_PHYOP_WRITE 0x00000000 18750974Swpaul 18850974Swpaul#define SIS_TXCFG_DRAIN_THRESH 0x0000003F /* 32-byte units */ 18950974Swpaul#define SIS_TXCFG_FILL_THRESH 0x00003F00 /* 32-byte units */ 19050974Swpaul#define SIS_TXCFG_DMABURST 0x00700000 19150974Swpaul#define SIS_TXCFG_AUTOPAD 0x10000000 19250974Swpaul#define SIS_TXCFG_LOOPBK 0x20000000 19350974Swpaul#define SIS_TXCFG_IGN_HBEAT 0x40000000 19450974Swpaul#define SIS_TXCFG_IGN_CARR 0x80000000 19550974Swpaul 19650974Swpaul#define SIS_TXCFG_DRAIN(x) (((x) >> 5) & SIS_TXCFG_DRAIN_THRESH) 19750974Swpaul#define SIS_TXCFG_FILL(x) ((((x) >> 5) << 8) & SIS_TXCFG_FILL_THRESH) 19850974Swpaul 19950974Swpaul#define SIS_TXDMA_512BYTES 0x00000000 20050974Swpaul#define SIS_TXDMA_4BYTES 0x00100000 20150974Swpaul#define SIS_TXDMA_8BYTES 0x00200000 20250974Swpaul#define SIS_TXDMA_16BYTES 0x00300000 20350974Swpaul#define SIS_TXDMA_32BYTES 0x00400000 20450974Swpaul#define SIS_TXDMA_64BYTES 0x00500000 20550974Swpaul#define SIS_TXDMA_128BYTES 0x00600000 20650974Swpaul#define SIS_TXDMA_256BYTES 0x00700000 20750974Swpaul 20850974Swpaul#define SIS_TXCFG \ 20950974Swpaul (SIS_TXDMA_64BYTES|SIS_TXCFG_AUTOPAD|\ 21050974Swpaul SIS_TXCFG_FILL(64)|SIS_TXCFG_DRAIN(1500)) 21150974Swpaul 21250974Swpaul#define SIS_RXCFG_DRAIN_THRESH 0x0000003E /* 8-byte units */ 21350974Swpaul#define SIS_RXCFG_DMABURST 0x00700000 21450974Swpaul#define SIS_RXCFG_RX_JABBER 0x08000000 21550974Swpaul#define SIS_RXCFG_RX_TXPKTS 0x10000000 21650974Swpaul#define SIS_RXCFG_RX_RUNTS 0x40000000 21750974Swpaul#define SIS_RXCFG_RX_GIANTS 0x80000000 21850974Swpaul 21950974Swpaul#define SIS_RXCFG_DRAIN(x) ((((x) >> 3) << 1) & SIS_RXCFG_DRAIN_THRESH) 22050974Swpaul 22150974Swpaul#define SIS_RXDMA_512BYTES 0x00000000 22250974Swpaul#define SIS_RXDMA_4BYTES 0x00100000 22350974Swpaul#define SIS_RXDMA_8BYTES 0x00200000 22450974Swpaul#define SIS_RXDMA_16BYTES 0x00300000 22550974Swpaul#define SIS_RXDMA_32BYTES 0x00400000 22650974Swpaul#define SIS_RXDMA_64BYTES 0x00500000 22750974Swpaul#define SIS_RXDMA_128BYTES 0x00600000 22850974Swpaul#define SIS_RXDMA_256BYTES 0x00700000 22950974Swpaul 23050974Swpaul#define SIS_RXCFG \ 23150974Swpaul (SIS_RXCFG_DRAIN(64)|SIS_RXDMA_256BYTES) 23250974Swpaul 23350974Swpaul#define SIS_RXFILTCTL_ADDR 0x000F0000 23462672Swpaul#define NS_RXFILTCTL_MCHASH 0x00200000 23562672Swpaul#define NS_RXFILTCTL_ARP 0x00400000 23662672Swpaul#define NS_RXFILTCTL_PERFECT 0x08000000 23750974Swpaul#define SIS_RXFILTCTL_ALLPHYS 0x10000000 23850974Swpaul#define SIS_RXFILTCTL_ALLMULTI 0x20000000 23950974Swpaul#define SIS_RXFILTCTL_BROAD 0x40000000 24050974Swpaul#define SIS_RXFILTCTL_ENABLE 0x80000000 24150974Swpaul 24250974Swpaul#define SIS_FILTADDR_PAR0 0x00000000 24350974Swpaul#define SIS_FILTADDR_PAR1 0x00010000 24450974Swpaul#define SIS_FILTADDR_PAR2 0x00020000 24550974Swpaul#define SIS_FILTADDR_MAR0 0x00040000 24650974Swpaul#define SIS_FILTADDR_MAR1 0x00050000 24750974Swpaul#define SIS_FILTADDR_MAR2 0x00060000 24850974Swpaul#define SIS_FILTADDR_MAR3 0x00070000 24950974Swpaul#define SIS_FILTADDR_MAR4 0x00080000 25050974Swpaul#define SIS_FILTADDR_MAR5 0x00090000 25150974Swpaul#define SIS_FILTADDR_MAR6 0x000A0000 25250974Swpaul#define SIS_FILTADDR_MAR7 0x000B0000 25350974Swpaul 25462672Swpaul#define NS_FILTADDR_PAR0 0x00000000 25562672Swpaul#define NS_FILTADDR_PAR1 0x00000002 25662672Swpaul#define NS_FILTADDR_PAR2 0x00000004 25762672Swpaul 25862672Swpaul#define NS_FILTADDR_FMEM_LO 0x00000200 25962672Swpaul#define NS_FILTADDR_FMEM_HI 0x000003FE 26062672Swpaul 26150974Swpaul/* 26250974Swpaul * DMA descriptor structures. The first part of the descriptor 26350974Swpaul * is the hardware descriptor format, which is just three longwords. 26450974Swpaul * After this, we include some additional structure members for 26550974Swpaul * use by the driver. Note that for this structure will be a different 26650974Swpaul * size on the alpha, but that's okay as long as it's a multiple of 4 26750974Swpaul * bytes in size. 26850974Swpaul */ 26950974Swpaulstruct sis_desc { 27050974Swpaul /* SiS hardware descriptor section */ 27150974Swpaul u_int32_t sis_next; 27250974Swpaul u_int32_t sis_cmdsts; 27350974Swpaul#define sis_rxstat sis_cmdsts 27450974Swpaul#define sis_txstat sis_cmdsts 27550974Swpaul#define sis_ctl sis_cmdsts 27650974Swpaul u_int32_t sis_ptr; 27750974Swpaul /* Driver software section */ 27850974Swpaul struct mbuf *sis_mbuf; 27950974Swpaul struct sis_desc *sis_nextdesc; 28050974Swpaul}; 28150974Swpaul 28250974Swpaul#define SIS_CMDSTS_BUFLEN 0x00000FFF 28350974Swpaul#define SIS_CMDSTS_PKT_OK 0x08000000 28450974Swpaul#define SIS_CMDSTS_CRC 0x10000000 28550974Swpaul#define SIS_CMDSTS_INTR 0x20000000 28650974Swpaul#define SIS_CMDSTS_MORE 0x40000000 28750974Swpaul#define SIS_CMDSTS_OWN 0x80000000 28850974Swpaul 28950974Swpaul#define SIS_LASTDESC(x) (!((x)->sis_ctl & SIS_CMDSTS_MORE))) 29050974Swpaul#define SIS_OWNDESC(x) ((x)->sis_ctl & SIS_CMDSTS_OWN) 29150974Swpaul#define SIS_INC(x, y) (x) = (x + 1) % y 29250974Swpaul#define SIS_RXBYTES(x) ((x)->sis_ctl & SIS_CMDSTS_BUFLEN) 29350974Swpaul 29450974Swpaul#define SIS_RXSTAT_COLL 0x00010000 29550974Swpaul#define SIS_RXSTAT_LOOPBK 0x00020000 29650974Swpaul#define SIS_RXSTAT_ALIGNERR 0x00040000 29750974Swpaul#define SIS_RXSTAT_CRCERR 0x00080000 29850974Swpaul#define SIS_RXSTAT_SYMBOLERR 0x00100000 29950974Swpaul#define SIS_RXSTAT_RUNT 0x00200000 30050974Swpaul#define SIS_RXSTAT_GIANT 0x00400000 30150974Swpaul#define SIS_RXSTAT_DSTCLASS 0x01800000 30250974Swpaul#define SIS_RXSTAT_OVERRUN 0x02000000 30350974Swpaul#define SIS_RXSTAT_RX_ABORT 0x04000000 30450974Swpaul 30550974Swpaul#define SIS_DSTCLASS_REJECT 0x00000000 30650974Swpaul#define SIS_DSTCLASS_UNICAST 0x00800000 30750974Swpaul#define SIS_DSTCLASS_MULTICAST 0x01000000 30850974Swpaul#define SIS_DSTCLASS_BROADCAST 0x02000000 30950974Swpaul 31050974Swpaul#define SIS_TXSTAT_COLLCNT 0x000F0000 31150974Swpaul#define SIS_TXSTAT_EXCESSCOLLS 0x00100000 31250974Swpaul#define SIS_TXSTAT_OUTOFWINCOLL 0x00200000 31350974Swpaul#define SIS_TXSTAT_EXCESS_DEFER 0x00400000 31450974Swpaul#define SIS_TXSTAT_DEFERED 0x00800000 31550974Swpaul#define SIS_TXSTAT_CARR_LOST 0x01000000 31650974Swpaul#define SIS_TXSTAT_UNDERRUN 0x02000000 31750974Swpaul#define SIS_TXSTAT_TX_ABORT 0x04000000 31850974Swpaul 31950974Swpaul#define SIS_RX_LIST_CNT 64 32050974Swpaul#define SIS_TX_LIST_CNT 128 32150974Swpaul 32250974Swpaulstruct sis_list_data { 32350974Swpaul struct sis_desc sis_rx_list[SIS_RX_LIST_CNT]; 32450974Swpaul struct sis_desc sis_tx_list[SIS_TX_LIST_CNT]; 32550974Swpaul}; 32650974Swpaul 32750974Swpaulstruct sis_ring_data { 32850974Swpaul int sis_rx_prod; 32950974Swpaul int sis_tx_prod; 33050974Swpaul int sis_tx_cons; 33150974Swpaul int sis_tx_cnt; 33250974Swpaul}; 33350974Swpaul 33450974Swpaul 33550974Swpaul/* 33650974Swpaul * SiS PCI vendor ID. 33750974Swpaul */ 33850974Swpaul#define SIS_VENDORID 0x1039 33950974Swpaul 34050974Swpaul/* 34150974Swpaul * SiS PCI device IDs 34250974Swpaul */ 34350974Swpaul#define SIS_DEVICEID_900 0x0900 34450974Swpaul#define SIS_DEVICEID_7016 0x7016 34550974Swpaul 34662672Swpaul/* 34762672Swpaul * NatSemi vendor ID 34862672Swpaul */ 34962672Swpaul#define NS_VENDORID 0x100B 35062672Swpaul 35162672Swpaul/* 35262672Swpaul * DP83815 device ID 35362672Swpaul */ 35462672Swpaul#define NS_DEVICEID_DP83815 0x0020 35562672Swpaul 35650974Swpaulstruct sis_type { 35750974Swpaul u_int16_t sis_vid; 35850974Swpaul u_int16_t sis_did; 35950974Swpaul char *sis_name; 36050974Swpaul}; 36150974Swpaul 36250974Swpaul#define SIS_TYPE_900 1 36350974Swpaul#define SIS_TYPE_7016 2 36462672Swpaul#define SIS_TYPE_83815 3 36550974Swpaul 36650974Swpaulstruct sis_softc { 36750974Swpaul struct arpcom arpcom; /* interface info */ 36850974Swpaul bus_space_handle_t sis_bhandle; 36950974Swpaul bus_space_tag_t sis_btag; 37050974Swpaul struct resource *sis_res; 37150974Swpaul struct resource *sis_irq; 37250974Swpaul void *sis_intrhand; 37350974Swpaul device_t sis_miibus; 37450974Swpaul u_int8_t sis_unit; 37550974Swpaul u_int8_t sis_type; 37650974Swpaul struct sis_list_data *sis_ldata; 37750974Swpaul struct sis_ring_data sis_cdata; 37850974Swpaul struct callout_handle sis_stat_ch; 37950974Swpaul}; 38050974Swpaul 38150974Swpaul/* 38250974Swpaul * register space access macros 38350974Swpaul */ 38450974Swpaul#define CSR_WRITE_4(sc, reg, val) \ 38550974Swpaul bus_space_write_4(sc->sis_btag, sc->sis_bhandle, reg, val) 38650974Swpaul 38750974Swpaul#define CSR_READ_4(sc, reg) \ 38850974Swpaul bus_space_read_4(sc->sis_btag, sc->sis_bhandle, reg) 38950974Swpaul 39050974Swpaul#define SIS_TIMEOUT 1000 39150974Swpaul#define ETHER_ALIGN 2 39250974Swpaul#define SIS_RXLEN 1536 39350974Swpaul#define SIS_MIN_FRAMELEN 60 39450974Swpaul 39550974Swpaul/* 39650974Swpaul * PCI low memory base and low I/O base register, and 39750974Swpaul * other PCI registers. 39850974Swpaul */ 39950974Swpaul 40050974Swpaul#define SIS_PCI_VENDOR_ID 0x00 40150974Swpaul#define SIS_PCI_DEVICE_ID 0x02 40250974Swpaul#define SIS_PCI_COMMAND 0x04 40350974Swpaul#define SIS_PCI_STATUS 0x06 40450974Swpaul#define SIS_PCI_REVID 0x08 40550974Swpaul#define SIS_PCI_CLASSCODE 0x09 40650974Swpaul#define SIS_PCI_CACHELEN 0x0C 40750974Swpaul#define SIS_PCI_LATENCY_TIMER 0x0D 40850974Swpaul#define SIS_PCI_HEADER_TYPE 0x0E 40950974Swpaul#define SIS_PCI_LOIO 0x10 41050974Swpaul#define SIS_PCI_LOMEM 0x14 41150974Swpaul#define SIS_PCI_BIOSROM 0x30 41250974Swpaul#define SIS_PCI_INTLINE 0x3C 41350974Swpaul#define SIS_PCI_INTPIN 0x3D 41450974Swpaul#define SIS_PCI_MINGNT 0x3E 41550974Swpaul#define SIS_PCI_MINLAT 0x0F 41650974Swpaul#define SIS_PCI_RESETOPT 0x48 41750974Swpaul#define SIS_PCI_EEPROM_DATA 0x4C 41850974Swpaul 41950974Swpaul/* power management registers */ 42050974Swpaul#define SIS_PCI_CAPID 0x50 /* 8 bits */ 42150974Swpaul#define SIS_PCI_NEXTPTR 0x51 /* 8 bits */ 42250974Swpaul#define SIS_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 42350974Swpaul#define SIS_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 42450974Swpaul 42550974Swpaul#define SIS_PSTATE_MASK 0x0003 42650974Swpaul#define SIS_PSTATE_D0 0x0000 42750974Swpaul#define SIS_PSTATE_D1 0x0001 42850974Swpaul#define SIS_PSTATE_D2 0x0002 42950974Swpaul#define SIS_PSTATE_D3 0x0003 43050974Swpaul#define SIS_PME_EN 0x0010 43150974Swpaul#define SIS_PME_STATUS 0x8000 43250974Swpaul 43350974Swpaul#ifdef __alpha__ 43450974Swpaul#undef vtophys 43550974Swpaul#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 43650974Swpaul#endif 437