if_sis.c revision 89296
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_sis.c 89296 2002-01-12 21:12:17Z wpaul $ 33 */ 34 35/* 36 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 37 * available from http://www.sis.com.tw. 38 * 39 * This driver also supports the NatSemi DP83815. Datasheets are 40 * available from http://www.national.com. 41 * 42 * Written by Bill Paul <wpaul@ee.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47/* 48 * The SiS 900 is a fairly simple chip. It uses bus master DMA with 49 * simple TX and RX descriptors of 3 longwords in size. The receiver 50 * has a single perfect filter entry for the station address and a 51 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 52 * transceiver while the 7016 requires an external transceiver chip. 53 * Both chips offer the standard bit-bang MII interface as well as 54 * an enchanced PHY interface which simplifies accessing MII registers. 55 * 56 * The only downside to this chipset is that RX descriptors must be 57 * longword aligned. 58 */ 59 60#include <sys/param.h> 61#include <sys/systm.h> 62#include <sys/sockio.h> 63#include <sys/mbuf.h> 64#include <sys/malloc.h> 65#include <sys/kernel.h> 66#include <sys/socket.h> 67#include <sys/sysctl.h> 68 69#include <net/if.h> 70#include <net/if_arp.h> 71#include <net/ethernet.h> 72#include <net/if_dl.h> 73#include <net/if_media.h> 74#include <net/if_types.h> 75#include <net/if_vlan_var.h> 76 77#include <net/bpf.h> 78 79#include <machine/bus_pio.h> 80#include <machine/bus_memio.h> 81#include <machine/bus.h> 82#include <machine/resource.h> 83#include <sys/bus.h> 84#include <sys/rman.h> 85 86#include <dev/mii/mii.h> 87#include <dev/mii/miivar.h> 88 89#include <pci/pcireg.h> 90#include <pci/pcivar.h> 91 92#define SIS_USEIOSPACE 93 94#include <pci/if_sisreg.h> 95 96MODULE_DEPEND(sis, miibus, 1, 1, 1); 97 98/* "controller miibus0" required. See GENERIC if you get errors here. */ 99#include "miibus_if.h" 100 101#ifndef lint 102static const char rcsid[] = 103 "$FreeBSD: head/sys/pci/if_sis.c 89296 2002-01-12 21:12:17Z wpaul $"; 104#endif 105 106/* 107 * Various supported device vendors/types and their names. 108 */ 109static struct sis_type sis_devs[] = { 110 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 111 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 112 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP83815 10/100BaseTX" }, 113 { 0, 0, NULL } 114}; 115 116static int sis_probe __P((device_t)); 117static int sis_attach __P((device_t)); 118static int sis_detach __P((device_t)); 119 120static int sis_newbuf __P((struct sis_softc *, 121 struct sis_desc *, 122 struct mbuf *)); 123static int sis_encap __P((struct sis_softc *, 124 struct mbuf *, u_int32_t *)); 125static void sis_rxeof __P((struct sis_softc *)); 126static void sis_rxeoc __P((struct sis_softc *)); 127static void sis_txeof __P((struct sis_softc *)); 128static void sis_intr __P((void *)); 129static void sis_tick __P((void *)); 130static void sis_start __P((struct ifnet *)); 131static int sis_ioctl __P((struct ifnet *, u_long, caddr_t)); 132static void sis_init __P((void *)); 133static void sis_stop __P((struct sis_softc *)); 134static void sis_watchdog __P((struct ifnet *)); 135static void sis_shutdown __P((device_t)); 136static int sis_ifmedia_upd __P((struct ifnet *)); 137static void sis_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 138 139static u_int16_t sis_reverse __P((u_int16_t)); 140static void sis_delay __P((struct sis_softc *)); 141static void sis_eeprom_idle __P((struct sis_softc *)); 142static void sis_eeprom_putbyte __P((struct sis_softc *, int)); 143static void sis_eeprom_getword __P((struct sis_softc *, int, u_int16_t *)); 144static void sis_read_eeprom __P((struct sis_softc *, caddr_t, int, 145 int, int)); 146#ifdef __i386__ 147static void sis_read_cmos __P((struct sis_softc *, device_t, caddr_t, 148 int, int)); 149static void sis_read_mac __P((struct sis_softc *, device_t, caddr_t)); 150static device_t sis_find_bridge __P((device_t)); 151#endif 152 153static int sis_miibus_readreg __P((device_t, int, int)); 154static int sis_miibus_writereg __P((device_t, int, int, int)); 155static void sis_miibus_statchg __P((device_t)); 156 157static void sis_setmulti_sis __P((struct sis_softc *)); 158static void sis_setmulti_ns __P((struct sis_softc *)); 159static u_int32_t sis_crc __P((struct sis_softc *, caddr_t)); 160static void sis_reset __P((struct sis_softc *)); 161static int sis_list_rx_init __P((struct sis_softc *)); 162static int sis_list_tx_init __P((struct sis_softc *)); 163 164static void sis_dma_map_desc_ptr __P((void *, bus_dma_segment_t *, 165 int, int)); 166static void sis_dma_map_desc_next __P((void *, bus_dma_segment_t *, 167 int, int)); 168static void sis_dma_map_ring __P((void *, bus_dma_segment_t *, 169 int, int)); 170#ifdef SIS_USEIOSPACE 171#define SIS_RES SYS_RES_IOPORT 172#define SIS_RID SIS_PCI_LOIO 173#else 174#define SIS_RES SYS_RES_MEMORY 175#define SIS_RID SIS_PCI_LOMEM 176#endif 177 178static device_method_t sis_methods[] = { 179 /* Device interface */ 180 DEVMETHOD(device_probe, sis_probe), 181 DEVMETHOD(device_attach, sis_attach), 182 DEVMETHOD(device_detach, sis_detach), 183 DEVMETHOD(device_shutdown, sis_shutdown), 184 185 /* bus interface */ 186 DEVMETHOD(bus_print_child, bus_generic_print_child), 187 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 188 189 /* MII interface */ 190 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 191 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 192 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 193 194 { 0, 0 } 195}; 196 197static driver_t sis_driver = { 198 "sis", 199 sis_methods, 200 sizeof(struct sis_softc) 201}; 202 203static devclass_t sis_devclass; 204 205#ifdef __i386__ 206static int sis_quick=1; 207SYSCTL_INT(_hw, OID_AUTO, sis_quick, CTLFLAG_RW, 208 &sis_quick,0,"do not mdevget in sis driver"); 209#endif 210 211DRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, 0, 0); 212DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 213 214#define SIS_SETBIT(sc, reg, x) \ 215 CSR_WRITE_4(sc, reg, \ 216 CSR_READ_4(sc, reg) | (x)) 217 218#define SIS_CLRBIT(sc, reg, x) \ 219 CSR_WRITE_4(sc, reg, \ 220 CSR_READ_4(sc, reg) & ~(x)) 221 222#define SIO_SET(x) \ 223 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 224 225#define SIO_CLR(x) \ 226 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 227 228static void 229sis_dma_map_desc_next(arg, segs, nseg, error) 230 void *arg; 231 bus_dma_segment_t *segs; 232 int nseg, error; 233{ 234 struct sis_desc *r; 235 236 r = arg; 237 r->sis_next = segs->ds_addr; 238 239 return; 240} 241 242static void 243sis_dma_map_desc_ptr(arg, segs, nseg, error) 244 void *arg; 245 bus_dma_segment_t *segs; 246 int nseg, error; 247{ 248 struct sis_desc *r; 249 250 r = arg; 251 r->sis_ptr = segs->ds_addr; 252 253 return; 254} 255 256static void 257sis_dma_map_ring(arg, segs, nseg, error) 258 void *arg; 259 bus_dma_segment_t *segs; 260 int nseg, error; 261{ 262 u_int32_t *p; 263 264 p = arg; 265 *p = segs->ds_addr; 266 267 return; 268} 269 270/* 271 * Routine to reverse the bits in a word. Stolen almost 272 * verbatim from /usr/games/fortune. 273 */ 274static u_int16_t sis_reverse(n) 275 u_int16_t n; 276{ 277 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 278 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 279 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 280 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 281 282 return(n); 283} 284 285static void sis_delay(sc) 286 struct sis_softc *sc; 287{ 288 int idx; 289 290 for (idx = (300 / 33) + 1; idx > 0; idx--) 291 CSR_READ_4(sc, SIS_CSR); 292 293 return; 294} 295 296static void sis_eeprom_idle(sc) 297 struct sis_softc *sc; 298{ 299 register int i; 300 301 SIO_SET(SIS_EECTL_CSEL); 302 sis_delay(sc); 303 SIO_SET(SIS_EECTL_CLK); 304 sis_delay(sc); 305 306 for (i = 0; i < 25; i++) { 307 SIO_CLR(SIS_EECTL_CLK); 308 sis_delay(sc); 309 SIO_SET(SIS_EECTL_CLK); 310 sis_delay(sc); 311 } 312 313 SIO_CLR(SIS_EECTL_CLK); 314 sis_delay(sc); 315 SIO_CLR(SIS_EECTL_CSEL); 316 sis_delay(sc); 317 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 318 319 return; 320} 321 322/* 323 * Send a read command and address to the EEPROM, check for ACK. 324 */ 325static void sis_eeprom_putbyte(sc, addr) 326 struct sis_softc *sc; 327 int addr; 328{ 329 register int d, i; 330 331 d = addr | SIS_EECMD_READ; 332 333 /* 334 * Feed in each bit and stobe the clock. 335 */ 336 for (i = 0x400; i; i >>= 1) { 337 if (d & i) { 338 SIO_SET(SIS_EECTL_DIN); 339 } else { 340 SIO_CLR(SIS_EECTL_DIN); 341 } 342 sis_delay(sc); 343 SIO_SET(SIS_EECTL_CLK); 344 sis_delay(sc); 345 SIO_CLR(SIS_EECTL_CLK); 346 sis_delay(sc); 347 } 348 349 return; 350} 351 352/* 353 * Read a word of data stored in the EEPROM at address 'addr.' 354 */ 355static void sis_eeprom_getword(sc, addr, dest) 356 struct sis_softc *sc; 357 int addr; 358 u_int16_t *dest; 359{ 360 register int i; 361 u_int16_t word = 0; 362 363 /* Force EEPROM to idle state. */ 364 sis_eeprom_idle(sc); 365 366 /* Enter EEPROM access mode. */ 367 sis_delay(sc); 368 SIO_CLR(SIS_EECTL_CLK); 369 sis_delay(sc); 370 SIO_SET(SIS_EECTL_CSEL); 371 sis_delay(sc); 372 373 /* 374 * Send address of word we want to read. 375 */ 376 sis_eeprom_putbyte(sc, addr); 377 378 /* 379 * Start reading bits from EEPROM. 380 */ 381 for (i = 0x8000; i; i >>= 1) { 382 SIO_SET(SIS_EECTL_CLK); 383 sis_delay(sc); 384 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 385 word |= i; 386 sis_delay(sc); 387 SIO_CLR(SIS_EECTL_CLK); 388 sis_delay(sc); 389 } 390 391 /* Turn off EEPROM access mode. */ 392 sis_eeprom_idle(sc); 393 394 *dest = word; 395 396 return; 397} 398 399/* 400 * Read a sequence of words from the EEPROM. 401 */ 402static void sis_read_eeprom(sc, dest, off, cnt, swap) 403 struct sis_softc *sc; 404 caddr_t dest; 405 int off; 406 int cnt; 407 int swap; 408{ 409 int i; 410 u_int16_t word = 0, *ptr; 411 412 for (i = 0; i < cnt; i++) { 413 sis_eeprom_getword(sc, off + i, &word); 414 ptr = (u_int16_t *)(dest + (i * 2)); 415 if (swap) 416 *ptr = ntohs(word); 417 else 418 *ptr = word; 419 } 420 421 return; 422} 423 424#ifdef __i386__ 425static device_t sis_find_bridge(dev) 426 device_t dev; 427{ 428 devclass_t pci_devclass; 429 device_t *pci_devices; 430 int pci_count = 0; 431 device_t *pci_children; 432 int pci_childcount = 0; 433 device_t *busp, *childp; 434 device_t child = NULL; 435 int i, j; 436 437 if ((pci_devclass = devclass_find("pci")) == NULL) 438 return(NULL); 439 440 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 441 442 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 443 pci_childcount = 0; 444 device_get_children(*busp, &pci_children, &pci_childcount); 445 for (j = 0, childp = pci_children; 446 j < pci_childcount; j++, childp++) { 447 if (pci_get_vendor(*childp) == SIS_VENDORID && 448 pci_get_device(*childp) == 0x0008) { 449 child = *childp; 450 goto done; 451 } 452 } 453 } 454 455done: 456 free(pci_devices, M_TEMP); 457 free(pci_children, M_TEMP); 458 return(child); 459} 460 461static void sis_read_cmos(sc, dev, dest, off, cnt) 462 struct sis_softc *sc; 463 device_t dev; 464 caddr_t dest; 465 int off; 466 int cnt; 467{ 468 device_t bridge; 469 u_int8_t reg; 470 int i; 471 bus_space_tag_t btag; 472 473 bridge = sis_find_bridge(dev); 474 if (bridge == NULL) 475 return; 476 reg = pci_read_config(bridge, 0x48, 1); 477 pci_write_config(bridge, 0x48, reg|0x40, 1); 478 479 /* XXX */ 480 btag = I386_BUS_SPACE_IO; 481 482 for (i = 0; i < cnt; i++) { 483 bus_space_write_1(btag, 0x0, 0x70, i + off); 484 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 485 } 486 487 pci_write_config(bridge, 0x48, reg & ~0x40, 1); 488 return; 489} 490 491static void sis_read_mac(sc, dev, dest) 492 struct sis_softc *sc; 493 device_t dev; 494 caddr_t dest; 495{ 496 u_int32_t filtsave, csrsave; 497 498 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 499 csrsave = CSR_READ_4(sc, SIS_CSR); 500 501 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 502 CSR_WRITE_4(sc, SIS_CSR, 0); 503 504 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 505 506 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 507 ((u_int16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 508 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 509 ((u_int16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 510 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 511 ((u_int16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 512 513 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 514 CSR_WRITE_4(sc, SIS_CSR, csrsave); 515 return; 516} 517#endif 518 519static int sis_miibus_readreg(dev, phy, reg) 520 device_t dev; 521 int phy, reg; 522{ 523 struct sis_softc *sc; 524 int i, val = 0; 525 526 sc = device_get_softc(dev); 527 528 if (sc->sis_type == SIS_TYPE_83815) { 529 if (phy != 0) 530 return(0); 531 /* 532 * The NatSemi chip can take a while after 533 * a reset to come ready, during which the BMSR 534 * returns a value of 0. This is *never* supposed 535 * to happen: some of the BMSR bits are meant to 536 * be hardwired in the on position, and this can 537 * confuse the miibus code a bit during the probe 538 * and attach phase. So we make an effort to check 539 * for this condition and wait for it to clear. 540 */ 541 if (!CSR_READ_4(sc, NS_BMSR)) 542 DELAY(1000); 543 val = CSR_READ_4(sc, NS_BMCR + (reg * 4)); 544 return(val); 545 } 546 547 if (sc->sis_type == SIS_TYPE_900 && 548 sc->sis_rev < SIS_REV_635 && phy != 0) 549 return(0); 550 551 CSR_WRITE_4(sc, SIS_PHYCTL, (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 552 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 553 554 for (i = 0; i < SIS_TIMEOUT; i++) { 555 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 556 break; 557 } 558 559 if (i == SIS_TIMEOUT) { 560 printf("sis%d: PHY failed to come ready\n", sc->sis_unit); 561 return(0); 562 } 563 564 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 565 566 if (val == 0xFFFF) 567 return(0); 568 569 return(val); 570} 571 572static int sis_miibus_writereg(dev, phy, reg, data) 573 device_t dev; 574 int phy, reg, data; 575{ 576 struct sis_softc *sc; 577 int i; 578 579 sc = device_get_softc(dev); 580 581 if (sc->sis_type == SIS_TYPE_83815) { 582 if (phy != 0) 583 return(0); 584 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 585 return(0); 586 } 587 588 if (sc->sis_type == SIS_TYPE_900 && phy != 0) 589 return(0); 590 591 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 592 (reg << 6) | SIS_PHYOP_WRITE); 593 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 594 595 for (i = 0; i < SIS_TIMEOUT; i++) { 596 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 597 break; 598 } 599 600 if (i == SIS_TIMEOUT) 601 printf("sis%d: PHY failed to come ready\n", sc->sis_unit); 602 603 return(0); 604} 605 606static void sis_miibus_statchg(dev) 607 device_t dev; 608{ 609 struct sis_softc *sc; 610 611 sc = device_get_softc(dev); 612 sis_init(sc); 613 614 return; 615} 616 617static u_int32_t sis_crc(sc, addr) 618 struct sis_softc *sc; 619 caddr_t addr; 620{ 621 u_int32_t crc, carry; 622 int i, j; 623 u_int8_t c; 624 625 /* Compute CRC for the address value. */ 626 crc = 0xFFFFFFFF; /* initial value */ 627 628 for (i = 0; i < 6; i++) { 629 c = *(addr + i); 630 for (j = 0; j < 8; j++) { 631 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 632 crc <<= 1; 633 c >>= 1; 634 if (carry) 635 crc = (crc ^ 0x04c11db6) | carry; 636 } 637 } 638 639 /* 640 * return the filter bit position 641 * 642 * The NatSemi chip has a 512-bit filter, which is 643 * different than the SiS, so we special-case it. 644 */ 645 if (sc->sis_type == SIS_TYPE_83815) 646 return((crc >> 23) & 0x1FF); 647 648 return((crc >> 25) & 0x0000007F); 649} 650 651static void sis_setmulti_ns(sc) 652 struct sis_softc *sc; 653{ 654 struct ifnet *ifp; 655 struct ifmultiaddr *ifma; 656 u_int32_t h = 0, i, filtsave; 657 int bit, index; 658 659 ifp = &sc->arpcom.ac_if; 660 661 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 662 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 663 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 664 return; 665 } 666 667 /* 668 * We have to explicitly enable the multicast hash table 669 * on the NatSemi chip if we want to use it, which we do. 670 */ 671 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 672 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 673 674 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 675 676 /* first, zot all the existing hash bits */ 677 for (i = 0; i < 32; i++) { 678 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 679 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 680 } 681 682 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 683 if (ifma->ifma_addr->sa_family != AF_LINK) 684 continue; 685 h = sis_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 686 index = h >> 3; 687 bit = h & 0x1F; 688 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 689 if (bit > 0xF) 690 bit -= 0x10; 691 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 692 } 693 694 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 695 696 return; 697} 698 699static void sis_setmulti_sis(sc) 700 struct sis_softc *sc; 701{ 702 struct ifnet *ifp; 703 struct ifmultiaddr *ifma; 704 u_int32_t h = 0, i, filtsave; 705 706 ifp = &sc->arpcom.ac_if; 707 708 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 709 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 710 return; 711 } 712 713 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 714 715 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 716 717 /* first, zot all the existing hash bits */ 718 for (i = 0; i < 8; i++) { 719 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + ((i * 16) >> 4)) << 16); 720 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 721 } 722 723 /* now program new ones */ 724 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 725 if (ifma->ifma_addr->sa_family != AF_LINK) 726 continue; 727 h = sis_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 728 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + (h >> 4)) << 16); 729 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << (h & 0xF))); 730 } 731 732 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 733 734 return; 735} 736 737static void sis_reset(sc) 738 struct sis_softc *sc; 739{ 740 register int i; 741 742 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 743 744 for (i = 0; i < SIS_TIMEOUT; i++) { 745 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 746 break; 747 } 748 749 if (i == SIS_TIMEOUT) 750 printf("sis%d: reset never completed\n", sc->sis_unit); 751 752 /* Wait a little while for the chip to get its brains in order. */ 753 DELAY(1000); 754 755 /* 756 * If this is a NetSemi chip, make sure to clear 757 * PME mode. 758 */ 759 if (sc->sis_type == SIS_TYPE_83815) { 760 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 761 CSR_WRITE_4(sc, NS_CLKRUN, 0); 762 } 763 764 return; 765} 766 767/* 768 * Probe for an SiS chip. Check the PCI vendor and device 769 * IDs against our list and return a device name if we find a match. 770 */ 771static int sis_probe(dev) 772 device_t dev; 773{ 774 struct sis_type *t; 775 776 t = sis_devs; 777 778 while(t->sis_name != NULL) { 779 if ((pci_get_vendor(dev) == t->sis_vid) && 780 (pci_get_device(dev) == t->sis_did)) { 781 device_set_desc(dev, t->sis_name); 782 return(0); 783 } 784 t++; 785 } 786 787 return(ENXIO); 788} 789 790/* 791 * Attach the interface. Allocate softc structures, do ifmedia 792 * setup and ethernet/BPF attach. 793 */ 794static int sis_attach(dev) 795 device_t dev; 796{ 797 u_char eaddr[ETHER_ADDR_LEN]; 798 u_int32_t command; 799 struct sis_softc *sc; 800 struct ifnet *ifp; 801 int unit, error = 0, rid; 802 803 sc = device_get_softc(dev); 804 unit = device_get_unit(dev); 805 bzero(sc, sizeof(struct sis_softc)); 806 807 mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 808 SIS_LOCK(sc); 809 810 if (pci_get_device(dev) == SIS_DEVICEID_900) 811 sc->sis_type = SIS_TYPE_900; 812 if (pci_get_device(dev) == SIS_DEVICEID_7016) 813 sc->sis_type = SIS_TYPE_7016; 814 if (pci_get_vendor(dev) == NS_VENDORID) 815 sc->sis_type = SIS_TYPE_83815; 816 817 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 818 819 /* 820 * Handle power management nonsense. 821 */ 822 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 823 u_int32_t iobase, membase, irq; 824 825 /* Save important PCI config data. */ 826 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4); 827 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4); 828 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4); 829 830 /* Reset the power state. */ 831 printf("sis%d: chip is in D%d power mode " 832 "-- setting to D0\n", unit, 833 pci_get_powerstate(dev)); 834 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 835 836 /* Restore PCI config data. */ 837 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4); 838 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4); 839 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4); 840 } 841 842 /* 843 * Map control/status registers. 844 */ 845 pci_enable_busmaster(dev); 846 pci_enable_io(dev, SYS_RES_IOPORT); 847 pci_enable_io(dev, SYS_RES_MEMORY); 848 command = pci_read_config(dev, PCIR_COMMAND, 4); 849 850#ifdef SIS_USEIOSPACE 851 if (!(command & PCIM_CMD_PORTEN)) { 852 printf("sis%d: failed to enable I/O ports!\n", unit); 853 error = ENXIO;; 854 goto fail; 855 } 856#else 857 if (!(command & PCIM_CMD_MEMEN)) { 858 printf("sis%d: failed to enable memory mapping!\n", unit); 859 error = ENXIO;; 860 goto fail; 861 } 862#endif 863 864 rid = SIS_RID; 865 sc->sis_res = bus_alloc_resource(dev, SIS_RES, &rid, 866 0, ~0, 1, RF_ACTIVE); 867 868 if (sc->sis_res == NULL) { 869 printf("sis%d: couldn't map ports/memory\n", unit); 870 error = ENXIO; 871 goto fail; 872 } 873 874 sc->sis_btag = rman_get_bustag(sc->sis_res); 875 sc->sis_bhandle = rman_get_bushandle(sc->sis_res); 876 877 /* Allocate interrupt */ 878 rid = 0; 879 sc->sis_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 880 RF_SHAREABLE | RF_ACTIVE); 881 882 if (sc->sis_irq == NULL) { 883 printf("sis%d: couldn't map interrupt\n", unit); 884 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 885 error = ENXIO; 886 goto fail; 887 } 888 889 error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET, 890 sis_intr, sc, &sc->sis_intrhand); 891 892 if (error) { 893 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 894 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 895 printf("sis%d: couldn't set up irq\n", unit); 896 goto fail; 897 } 898 899 /* Reset the adapter. */ 900 sis_reset(sc); 901 902 /* 903 * Get station address from the EEPROM. 904 */ 905 switch (pci_get_vendor(dev)) { 906 case NS_VENDORID: 907 /* 908 * Reading the MAC address out of the EEPROM on 909 * the NatSemi chip takes a bit more work than 910 * you'd expect. The address spans 4 16-bit words, 911 * with the first word containing only a single bit. 912 * You have to shift everything over one bit to 913 * get it aligned properly. Also, the bits are 914 * stored backwards (the LSB is really the MSB, 915 * and so on) so you have to reverse them in order 916 * to get the MAC address into the form we want. 917 * Why? Who the hell knows. 918 */ 919 { 920 u_int16_t tmp[4]; 921 922 sis_read_eeprom(sc, (caddr_t)&tmp, 923 NS_EE_NODEADDR, 4, 0); 924 925 /* Shift everything over one bit. */ 926 tmp[3] = tmp[3] >> 1; 927 tmp[3] |= tmp[2] << 15; 928 tmp[2] = tmp[2] >> 1; 929 tmp[2] |= tmp[1] << 15; 930 tmp[1] = tmp[1] >> 1; 931 tmp[1] |= tmp[0] << 15; 932 933 /* Now reverse all the bits. */ 934 tmp[3] = sis_reverse(tmp[3]); 935 tmp[2] = sis_reverse(tmp[2]); 936 tmp[1] = sis_reverse(tmp[1]); 937 938 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); 939 } 940 break; 941 case SIS_VENDORID: 942 default: 943#ifdef __i386__ 944 /* 945 * If this is a SiS 630E chipset with an embedded 946 * SiS 900 controller, we have to read the MAC address 947 * from the APC CMOS RAM. Our method for doing this 948 * is very ugly since we have to reach out and grab 949 * ahold of hardware for which we cannot properly 950 * allocate resources. This code is only compiled on 951 * the i386 architecture since the SiS 630E chipset 952 * is for x86 motherboards only. Note that there are 953 * a lot of magic numbers in this hack. These are 954 * taken from SiS's Linux driver. I'd like to replace 955 * them with proper symbolic definitions, but that 956 * requires some datasheets that I don't have access 957 * to at the moment. 958 */ 959 if (sc->sis_rev == SIS_REV_630S || 960 sc->sis_rev == SIS_REV_630E || 961 sc->sis_rev == SIS_REV_630EA1 || 962 sc->sis_rev == SIS_REV_630ET) 963 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 964 965 else if (command == SIS_REV_635) 966 sis_read_mac(sc, dev, (caddr_t)&eaddr); 967 else 968#endif 969 sis_read_eeprom(sc, (caddr_t)&eaddr, 970 SIS_EE_NODEADDR, 3, 0); 971 break; 972 } 973 974 /* 975 * A SiS chip was detected. Inform the world. 976 */ 977 printf("sis%d: Ethernet address: %6D\n", unit, eaddr, ":"); 978 979 /* 980 * From the Linux driver: 981 * 630ET : set the mii access mode as software-mode 982 */ 983 if (sc->sis_rev == SIS_REV_630ET) 984 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_ACCESS_MODE); 985 986 sc->sis_unit = unit; 987 callout_handle_init(&sc->sis_stat_ch); 988 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 989 990 /* 991 * Allocate the parent bus DMA tag appropriate for PCI. 992 */ 993#define SIS_NSEG_NEW 32 994 error = bus_dma_tag_create(NULL, /* parent */ 995 1, 0, /* alignment, boundary */ 996 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 997 BUS_SPACE_MAXADDR, /* highaddr */ 998 NULL, NULL, /* filter, filterarg */ 999 MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */ 1000 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1001 BUS_DMA_ALLOCNOW, /* flags */ 1002 &sc->sis_parent_tag); 1003 1004 /* 1005 * Now allocate a tag for the DMA descriptor lists. 1006 * All of our lists are allocated as a contiguous block 1007 * of memory. 1008 */ 1009 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1010 1, 0, /* alignment, boundary */ 1011 BUS_SPACE_MAXADDR, /* lowaddr */ 1012 BUS_SPACE_MAXADDR, /* highaddr */ 1013 NULL, NULL, /* filter, filterarg */ 1014 SIS_RX_LIST_SZ, 1, /* maxsize,nsegments */ 1015 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1016 0, /* flags */ 1017 &sc->sis_ldata.sis_rx_tag); 1018 1019 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1020 1, 0, /* alignment, boundary */ 1021 BUS_SPACE_MAXADDR, /* lowaddr */ 1022 BUS_SPACE_MAXADDR, /* highaddr */ 1023 NULL, NULL, /* filter, filterarg */ 1024 SIS_TX_LIST_SZ, 1, /* maxsize,nsegments */ 1025 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1026 0, /* flags */ 1027 &sc->sis_ldata.sis_tx_tag); 1028 1029 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1030 1, 0, /* alignment, boundary */ 1031 BUS_SPACE_MAXADDR, /* lowaddr */ 1032 BUS_SPACE_MAXADDR, /* highaddr */ 1033 NULL, NULL, /* filter, filterarg */ 1034 SIS_TX_LIST_SZ, 1, /* maxsize,nsegments */ 1035 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1036 0, /* flags */ 1037 &sc->sis_tag); 1038 1039 /* 1040 * Now allocate a chunk of DMA-able memory based on the 1041 * tag we just created. 1042 */ 1043 error = bus_dmamem_alloc(sc->sis_ldata.sis_tx_tag, 1044 (void **)&sc->sis_ldata.sis_tx_list, BUS_DMA_NOWAIT, 1045 &sc->sis_ldata.sis_tx_dmamap); 1046 1047 if (error) { 1048 printf("sis%d: no memory for list buffers!\n", unit); 1049 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1050 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1051 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1052 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1053 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1054 error = ENXIO; 1055 goto fail; 1056 } 1057 1058 error = bus_dmamem_alloc(sc->sis_ldata.sis_rx_tag, 1059 (void **)&sc->sis_ldata.sis_rx_list, BUS_DMA_NOWAIT, 1060 &sc->sis_ldata.sis_rx_dmamap); 1061 1062 if (error) { 1063 printf("sis%d: no memory for list buffers!\n", unit); 1064 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1065 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1066 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1067 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1068 sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 1069 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1070 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1071 error = ENXIO; 1072 goto fail; 1073 } 1074 1075 1076 bzero(sc->sis_ldata.sis_tx_list, SIS_TX_LIST_SZ); 1077 bzero(sc->sis_ldata.sis_rx_list, SIS_RX_LIST_SZ); 1078 1079 /* 1080 * Obtain the physical addresses of the RX and TX 1081 * rings which we'll need later in the init routine. 1082 */ 1083 bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1084 sc->sis_ldata.sis_tx_dmamap, &(sc->sis_ldata.sis_tx_list[0]), 1085 sizeof(struct sis_desc), sis_dma_map_ring, 1086 &sc->sis_cdata.sis_tx_paddr, 0); 1087 bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1088 sc->sis_ldata.sis_rx_dmamap, &(sc->sis_ldata.sis_rx_list[0]), 1089 sizeof(struct sis_desc), sis_dma_map_ring, 1090 &sc->sis_cdata.sis_rx_paddr, 0); 1091 1092 ifp = &sc->arpcom.ac_if; 1093 ifp->if_softc = sc; 1094 ifp->if_unit = unit; 1095 ifp->if_name = "sis"; 1096 ifp->if_mtu = ETHERMTU; 1097 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1098 ifp->if_ioctl = sis_ioctl; 1099 ifp->if_output = ether_output; 1100 ifp->if_start = sis_start; 1101 ifp->if_watchdog = sis_watchdog; 1102 ifp->if_init = sis_init; 1103 ifp->if_baudrate = 10000000; 1104 ifp->if_snd.ifq_maxlen = SIS_TX_LIST_CNT - 1; 1105 1106 /* 1107 * Do MII setup. 1108 */ 1109 if (mii_phy_probe(dev, &sc->sis_miibus, 1110 sis_ifmedia_upd, sis_ifmedia_sts)) { 1111 printf("sis%d: MII without any PHY!\n", sc->sis_unit); 1112 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1113 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1114 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1115 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1116 sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap); 1117 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1118 sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 1119 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1120 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1121 error = ENXIO; 1122 goto fail; 1123 } 1124 1125 /* 1126 * Call MI attach routine. 1127 */ 1128 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1129 1130 /* 1131 * Tell the upper layer(s) we support long frames. 1132 */ 1133 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1134 1135 callout_handle_init(&sc->sis_stat_ch); 1136 SIS_UNLOCK(sc); 1137 return(0); 1138 1139fail: 1140 SIS_UNLOCK(sc); 1141 mtx_destroy(&sc->sis_mtx); 1142 return(error); 1143} 1144 1145static int sis_detach(dev) 1146 device_t dev; 1147{ 1148 struct sis_softc *sc; 1149 struct ifnet *ifp; 1150 1151 1152 sc = device_get_softc(dev); 1153 SIS_LOCK(sc); 1154 ifp = &sc->arpcom.ac_if; 1155 1156 sis_reset(sc); 1157 sis_stop(sc); 1158 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1159 1160 bus_generic_detach(dev); 1161 device_delete_child(dev, sc->sis_miibus); 1162 1163 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1164 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1165 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1166 1167 bus_dmamap_unload(sc->sis_ldata.sis_rx_tag, 1168 sc->sis_ldata.sis_rx_dmamap); 1169 bus_dmamap_unload(sc->sis_ldata.sis_tx_tag, 1170 sc->sis_ldata.sis_tx_dmamap); 1171 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1172 sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap); 1173 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1174 sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 1175 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1176 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1177 bus_dma_tag_destroy(sc->sis_parent_tag); 1178 1179 SIS_UNLOCK(sc); 1180 mtx_destroy(&sc->sis_mtx); 1181 1182 return(0); 1183} 1184 1185/* 1186 * Initialize the transmit descriptors. 1187 */ 1188static int sis_list_tx_init(sc) 1189 struct sis_softc *sc; 1190{ 1191 struct sis_list_data *ld; 1192 struct sis_ring_data *cd; 1193 int i, nexti; 1194 1195 cd = &sc->sis_cdata; 1196 ld = &sc->sis_ldata; 1197 1198 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1199 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1; 1200 ld->sis_tx_list[i].sis_nextdesc = 1201 &ld->sis_tx_list[nexti]; 1202 bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1203 sc->sis_ldata.sis_tx_dmamap, 1204 &ld->sis_tx_list[nexti], sizeof(struct sis_desc), 1205 sis_dma_map_desc_next, &ld->sis_tx_list[i], 0); 1206 ld->sis_tx_list[i].sis_mbuf = NULL; 1207 ld->sis_tx_list[i].sis_ptr = 0; 1208 ld->sis_tx_list[i].sis_ctl = 0; 1209 } 1210 1211 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0; 1212 1213 bus_dmamap_sync(sc->sis_ldata.sis_tx_tag, 1214 sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 1215 1216 return(0); 1217} 1218 1219/* 1220 * Initialize the RX descriptors and allocate mbufs for them. Note that 1221 * we arrange the descriptors in a closed ring, so that the last descriptor 1222 * points back to the first. 1223 */ 1224static int sis_list_rx_init(sc) 1225 struct sis_softc *sc; 1226{ 1227 struct sis_list_data *ld; 1228 struct sis_ring_data *cd; 1229 int i,nexti; 1230 1231 ld = &sc->sis_ldata; 1232 cd = &sc->sis_cdata; 1233 1234 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1235 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS) 1236 return(ENOBUFS); 1237 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1; 1238 ld->sis_rx_list[i].sis_nextdesc = 1239 &ld->sis_rx_list[nexti]; 1240 bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1241 sc->sis_ldata.sis_rx_dmamap, 1242 &ld->sis_rx_list[nexti], 1243 sizeof(struct sis_desc), sis_dma_map_desc_next, 1244 &ld->sis_rx_list[i], 0); 1245 } 1246 1247 bus_dmamap_sync(sc->sis_ldata.sis_rx_tag, 1248 sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 1249 1250 cd->sis_rx_prod = 0; 1251 1252 return(0); 1253} 1254 1255/* 1256 * Initialize an RX descriptor and attach an MBUF cluster. 1257 */ 1258static int sis_newbuf(sc, c, m) 1259 struct sis_softc *sc; 1260 struct sis_desc *c; 1261 struct mbuf *m; 1262{ 1263 struct mbuf *m_new = NULL; 1264 1265 if (c == NULL) 1266 return(EINVAL); 1267 1268 if (m == NULL) { 1269 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1270 if (m_new == NULL) 1271 return(ENOBUFS); 1272 1273 MCLGET(m_new, M_DONTWAIT); 1274 if (!(m_new->m_flags & M_EXT)) { 1275 m_freem(m_new); 1276 return(ENOBUFS); 1277 } 1278 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1279 } else { 1280 m_new = m; 1281 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1282 m_new->m_data = m_new->m_ext.ext_buf; 1283 } 1284 1285 m_adj(m_new, sizeof(u_int64_t)); 1286 1287 c->sis_mbuf = m_new; 1288 c->sis_ctl = SIS_RXLEN; 1289 1290 bus_dmamap_create(sc->sis_tag, 0, &c->sis_map); 1291 bus_dmamap_load(sc->sis_tag, c->sis_map, 1292 mtod(m_new, void *), m_new->m_len, 1293 sis_dma_map_desc_ptr, c, 0); 1294 bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREWRITE); 1295 1296 return(0); 1297} 1298 1299/* 1300 * A frame has been uploaded: pass the resulting mbuf chain up to 1301 * the higher level protocols. 1302 */ 1303static void sis_rxeof(sc) 1304 struct sis_softc *sc; 1305{ 1306 struct ether_header *eh; 1307 struct mbuf *m; 1308 struct ifnet *ifp; 1309 struct sis_desc *cur_rx; 1310 int i, total_len = 0; 1311 u_int32_t rxstat; 1312 1313 ifp = &sc->arpcom.ac_if; 1314 i = sc->sis_cdata.sis_rx_prod; 1315 1316 while(SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) { 1317 1318#ifdef DEVICE_POLLING 1319 if (ifp->if_ipending & IFF_POLLING) { 1320 if (sc->rxcycles <= 0) 1321 break; 1322 sc->rxcycles--; 1323 } 1324#endif /* DEVICE_POLLING */ 1325 cur_rx = &sc->sis_ldata.sis_rx_list[i]; 1326 rxstat = cur_rx->sis_rxstat; 1327 bus_dmamap_sync(sc->sis_tag, 1328 cur_rx->sis_map, BUS_DMASYNC_POSTWRITE); 1329 bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map); 1330 bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map); 1331 m = cur_rx->sis_mbuf; 1332 cur_rx->sis_mbuf = NULL; 1333 total_len = SIS_RXBYTES(cur_rx); 1334 SIS_INC(i, SIS_RX_LIST_CNT); 1335 1336 /* 1337 * If an error occurs, update stats, clear the 1338 * status word and leave the mbuf cluster in place: 1339 * it should simply get re-used next time this descriptor 1340 * comes up in the ring. 1341 */ 1342 if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 1343 ifp->if_ierrors++; 1344 if (rxstat & SIS_RXSTAT_COLL) 1345 ifp->if_collisions++; 1346 sis_newbuf(sc, cur_rx, m); 1347 continue; 1348 } 1349 1350 /* No errors; receive the packet. */ 1351#ifdef __i386__ 1352 /* 1353 * On the x86 we do not have alignment problems, so try to 1354 * allocate a new buffer for the receive ring, and pass up 1355 * the one where the packet is already, saving the expensive 1356 * copy done in m_devget(). 1357 * If we are on an architecture with alignment problems, or 1358 * if the allocation fails, then use m_devget and leave the 1359 * existing buffer in the receive ring. 1360 */ 1361 if (sis_quick && sis_newbuf(sc, cur_rx, NULL) == 0) { 1362 m->m_pkthdr.rcvif = ifp; 1363 m->m_pkthdr.len = m->m_len = total_len; 1364 } else 1365#endif 1366 { 1367 struct mbuf *m0; 1368 m0 = m_devget(mtod(m, char *), total_len, 1369 ETHER_ALIGN, ifp, NULL); 1370 sis_newbuf(sc, cur_rx, m); 1371 if (m0 == NULL) { 1372 ifp->if_ierrors++; 1373 continue; 1374 } 1375 m = m0; 1376 } 1377 1378 ifp->if_ipackets++; 1379 eh = mtod(m, struct ether_header *); 1380 1381 /* Remove header from mbuf and pass it on. */ 1382 m_adj(m, sizeof(struct ether_header)); 1383 ether_input(ifp, eh, m); 1384 } 1385 1386 sc->sis_cdata.sis_rx_prod = i; 1387 1388 return; 1389} 1390 1391void sis_rxeoc(sc) 1392 struct sis_softc *sc; 1393{ 1394 sis_rxeof(sc); 1395 sis_init(sc); 1396 return; 1397} 1398 1399/* 1400 * A frame was downloaded to the chip. It's safe for us to clean up 1401 * the list buffers. 1402 */ 1403 1404static void sis_txeof(sc) 1405 struct sis_softc *sc; 1406{ 1407 struct sis_desc *cur_tx = NULL; 1408 struct ifnet *ifp; 1409 u_int32_t idx; 1410 1411 ifp = &sc->arpcom.ac_if; 1412 1413 /* Clear the timeout timer. */ 1414 ifp->if_timer = 0; 1415 1416 /* 1417 * Go through our tx list and free mbufs for those 1418 * frames that have been transmitted. 1419 */ 1420 idx = sc->sis_cdata.sis_tx_cons; 1421 while (idx != sc->sis_cdata.sis_tx_prod) { 1422 cur_tx = &sc->sis_ldata.sis_tx_list[idx]; 1423 1424 if (SIS_OWNDESC(cur_tx)) 1425 break; 1426 1427 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) { 1428 sc->sis_cdata.sis_tx_cnt--; 1429 SIS_INC(idx, SIS_TX_LIST_CNT); 1430 continue; 1431 } 1432 1433 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 1434 ifp->if_oerrors++; 1435 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 1436 ifp->if_collisions++; 1437 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 1438 ifp->if_collisions++; 1439 } 1440 1441 ifp->if_collisions += 1442 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 1443 1444 ifp->if_opackets++; 1445 if (cur_tx->sis_mbuf != NULL) { 1446 m_freem(cur_tx->sis_mbuf); 1447 cur_tx->sis_mbuf = NULL; 1448 bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map); 1449 bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map); 1450 } 1451 1452 sc->sis_cdata.sis_tx_cnt--; 1453 SIS_INC(idx, SIS_TX_LIST_CNT); 1454 ifp->if_timer = 0; 1455 } 1456 1457 sc->sis_cdata.sis_tx_cons = idx; 1458 1459 if (cur_tx != NULL) 1460 ifp->if_flags &= ~IFF_OACTIVE; 1461 1462 return; 1463} 1464 1465static void sis_tick(xsc) 1466 void *xsc; 1467{ 1468 struct sis_softc *sc; 1469 struct mii_data *mii; 1470 struct ifnet *ifp; 1471 1472 sc = xsc; 1473 SIS_LOCK(sc); 1474 ifp = &sc->arpcom.ac_if; 1475 1476 mii = device_get_softc(sc->sis_miibus); 1477 mii_tick(mii); 1478 1479 if (!sc->sis_link && mii->mii_media_status & IFM_ACTIVE && 1480 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1481 sc->sis_link++; 1482 if (ifp->if_snd.ifq_head != NULL) 1483 sis_start(ifp); 1484 } 1485 1486 sc->sis_stat_ch = timeout(sis_tick, sc, hz); 1487 1488 SIS_UNLOCK(sc); 1489 1490 return; 1491} 1492 1493#ifdef DEVICE_POLLING 1494static poll_handler_t sis_poll; 1495 1496static void 1497sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1498{ 1499 struct sis_softc *sc = ifp->if_softc; 1500 1501 SIS_LOCK(sc); 1502 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1503 CSR_WRITE_4(sc, SIS_IER, 1); 1504 goto done; 1505 } 1506 1507 /* 1508 * On the sis, reading the status register also clears it. 1509 * So before returning to intr mode we must make sure that all 1510 * possible pending sources of interrupts have been served. 1511 * In practice this means run to completion the *eof routines, 1512 * and then call the interrupt routine 1513 */ 1514 sc->rxcycles = count; 1515 sis_rxeof(sc); 1516 sis_txeof(sc); 1517 if (ifp->if_snd.ifq_head != NULL) 1518 sis_start(ifp); 1519 1520 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1521 u_int32_t status; 1522 1523 /* Reading the ISR register clears all interrupts. */ 1524 status = CSR_READ_4(sc, SIS_ISR); 1525 1526 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 1527 sis_rxeoc(sc); 1528 1529 if (status & (SIS_ISR_RX_IDLE)) 1530 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1531 1532 if (status & SIS_ISR_SYSERR) { 1533 sis_reset(sc); 1534 sis_init(sc); 1535 } 1536 } 1537done: 1538 SIS_UNLOCK(sc); 1539 return; 1540} 1541#endif /* DEVICE_POLLING */ 1542 1543static void sis_intr(arg) 1544 void *arg; 1545{ 1546 struct sis_softc *sc; 1547 struct ifnet *ifp; 1548 u_int32_t status; 1549 1550 sc = arg; 1551 ifp = &sc->arpcom.ac_if; 1552 1553 SIS_LOCK(sc); 1554#ifdef DEVICE_POLLING 1555 if (ifp->if_ipending & IFF_POLLING) 1556 goto done; 1557 if (ether_poll_register(sis_poll, ifp)) { /* ok, disable interrupts */ 1558 CSR_WRITE_4(sc, SIS_IER, 0); 1559 goto done; 1560 } 1561#endif /* DEVICE_POLLING */ 1562 1563 /* Supress unwanted interrupts */ 1564 if (!(ifp->if_flags & IFF_UP)) { 1565 sis_stop(sc); 1566 goto done; 1567 } 1568 1569 /* Disable interrupts. */ 1570 CSR_WRITE_4(sc, SIS_IER, 0); 1571 1572 for (;;) { 1573 /* Reading the ISR register clears all interrupts. */ 1574 status = CSR_READ_4(sc, SIS_ISR); 1575 1576 if ((status & SIS_INTRS) == 0) 1577 break; 1578 1579 if (status & 1580 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | 1581 SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) ) 1582 sis_txeof(sc); 1583 1584 if (status & (SIS_ISR_RX_DESC_OK|SIS_ISR_RX_OK|SIS_ISR_RX_IDLE)) 1585 sis_rxeof(sc); 1586 1587 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW)) 1588 sis_rxeoc(sc); 1589 1590 if (status & (SIS_ISR_RX_IDLE)) 1591 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1592 1593 if (status & SIS_ISR_SYSERR) { 1594 sis_reset(sc); 1595 sis_init(sc); 1596 } 1597 } 1598 1599 /* Re-enable interrupts. */ 1600 CSR_WRITE_4(sc, SIS_IER, 1); 1601 1602 if (ifp->if_snd.ifq_head != NULL) 1603 sis_start(ifp); 1604done: 1605 SIS_UNLOCK(sc); 1606 1607 return; 1608} 1609 1610/* 1611 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1612 * pointers to the fragment pointers. 1613 */ 1614static int sis_encap(sc, m_head, txidx) 1615 struct sis_softc *sc; 1616 struct mbuf *m_head; 1617 u_int32_t *txidx; 1618{ 1619 struct sis_desc *f = NULL; 1620 struct mbuf *m; 1621 int frag, cur, cnt = 0; 1622 1623 /* 1624 * Start packing the mbufs in this chain into 1625 * the fragment pointers. Stop when we run out 1626 * of fragments or hit the end of the mbuf chain. 1627 */ 1628 m = m_head; 1629 cur = frag = *txidx; 1630 1631 for (m = m_head; m != NULL; m = m->m_next) { 1632 if (m->m_len != 0) { 1633 if ((SIS_TX_LIST_CNT - 1634 (sc->sis_cdata.sis_tx_cnt + cnt)) < 2) 1635 return(ENOBUFS); 1636 f = &sc->sis_ldata.sis_tx_list[frag]; 1637 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; 1638 bus_dmamap_create(sc->sis_tag, 0, &f->sis_map); 1639 bus_dmamap_load(sc->sis_tag, f->sis_map, 1640 mtod(m, void *), m->m_len, 1641 sis_dma_map_desc_ptr, f, 0); 1642 bus_dmamap_sync(sc->sis_tag, 1643 f->sis_map, BUS_DMASYNC_PREREAD); 1644 if (cnt != 0) 1645 f->sis_ctl |= SIS_CMDSTS_OWN; 1646 cur = frag; 1647 SIS_INC(frag, SIS_TX_LIST_CNT); 1648 cnt++; 1649 } 1650 } 1651 1652 if (m != NULL) 1653 return(ENOBUFS); 1654 1655 sc->sis_ldata.sis_tx_list[cur].sis_mbuf = m_head; 1656 sc->sis_ldata.sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1657 sc->sis_ldata.sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1658 sc->sis_cdata.sis_tx_cnt += cnt; 1659 *txidx = frag; 1660 1661 return(0); 1662} 1663 1664/* 1665 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1666 * to the mbuf data regions directly in the transmit lists. We also save a 1667 * copy of the pointers since the transmit list fragment pointers are 1668 * physical addresses. 1669 */ 1670 1671static void sis_start(ifp) 1672 struct ifnet *ifp; 1673{ 1674 struct sis_softc *sc; 1675 struct mbuf *m_head = NULL; 1676 u_int32_t idx; 1677 1678 sc = ifp->if_softc; 1679 SIS_LOCK(sc); 1680 1681 if (!sc->sis_link) { 1682 SIS_UNLOCK(sc); 1683 return; 1684 } 1685 1686 idx = sc->sis_cdata.sis_tx_prod; 1687 1688 if (ifp->if_flags & IFF_OACTIVE) { 1689 SIS_UNLOCK(sc); 1690 return; 1691 } 1692 1693 while(sc->sis_ldata.sis_tx_list[idx].sis_mbuf == NULL) { 1694 IF_DEQUEUE(&ifp->if_snd, m_head); 1695 if (m_head == NULL) 1696 break; 1697 1698 if (sis_encap(sc, m_head, &idx)) { 1699 IF_PREPEND(&ifp->if_snd, m_head); 1700 ifp->if_flags |= IFF_OACTIVE; 1701 break; 1702 } 1703 1704 /* 1705 * If there's a BPF listener, bounce a copy of this frame 1706 * to him. 1707 */ 1708 if (ifp->if_bpf) 1709 bpf_mtap(ifp, m_head); 1710 1711 } 1712 1713 /* Transmit */ 1714 sc->sis_cdata.sis_tx_prod = idx; 1715 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 1716 1717 /* 1718 * Set a timeout in case the chip goes out to lunch. 1719 */ 1720 ifp->if_timer = 5; 1721 1722 SIS_UNLOCK(sc); 1723 1724 return; 1725} 1726 1727static void sis_init(xsc) 1728 void *xsc; 1729{ 1730 struct sis_softc *sc = xsc; 1731 struct ifnet *ifp = &sc->arpcom.ac_if; 1732 struct mii_data *mii; 1733 1734 SIS_LOCK(sc); 1735 1736 /* 1737 * Cancel pending I/O and free all RX/TX buffers. 1738 */ 1739 sis_stop(sc); 1740 1741 mii = device_get_softc(sc->sis_miibus); 1742 1743 /* Set MAC address */ 1744 if (sc->sis_type == SIS_TYPE_83815) { 1745 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 1746 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1747 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1748 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 1749 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1750 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1751 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 1752 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1753 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1754 } else { 1755 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 1756 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1757 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1758 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 1759 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1760 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1761 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 1762 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1763 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1764 } 1765 1766 /* Init circular RX list. */ 1767 if (sis_list_rx_init(sc) == ENOBUFS) { 1768 printf("sis%d: initialization failed: no " 1769 "memory for rx buffers\n", sc->sis_unit); 1770 sis_stop(sc); 1771 SIS_UNLOCK(sc); 1772 return; 1773 } 1774 1775 /* 1776 * Init tx descriptors. 1777 */ 1778 sis_list_tx_init(sc); 1779 1780 /* 1781 * For the NatSemi chip, we have to explicitly enable the 1782 * reception of ARP frames, as well as turn on the 'perfect 1783 * match' filter where we store the station address, otherwise 1784 * we won't receive unicasts meant for this host. 1785 */ 1786 if (sc->sis_type == SIS_TYPE_83815) { 1787 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 1788 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 1789 } 1790 1791 /* If we want promiscuous mode, set the allframes bit. */ 1792 if (ifp->if_flags & IFF_PROMISC) { 1793 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1794 } else { 1795 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1796 } 1797 1798 /* 1799 * Set the capture broadcast bit to capture broadcast frames. 1800 */ 1801 if (ifp->if_flags & IFF_BROADCAST) { 1802 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1803 } else { 1804 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1805 } 1806 1807 /* 1808 * Load the multicast filter. 1809 */ 1810 if (sc->sis_type == SIS_TYPE_83815) 1811 sis_setmulti_ns(sc); 1812 else 1813 sis_setmulti_sis(sc); 1814 1815 /* Turn the receive filter on */ 1816 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 1817 1818 /* 1819 * Load the address of the RX and TX lists. 1820 */ 1821 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_cdata.sis_rx_paddr); 1822 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_cdata.sis_tx_paddr); 1823 1824 /* Set RX configuration */ 1825 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG); 1826 1827 /* Accept Long Packets for VLAN support */ 1828 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 1829 1830 /* Set TX configuration */ 1831 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 1832 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 1833 } else { 1834 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 1835 } 1836 1837 /* Set full/half duplex mode. */ 1838 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1839 SIS_SETBIT(sc, SIS_TX_CFG, 1840 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 1841 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 1842 } else { 1843 SIS_CLRBIT(sc, SIS_TX_CFG, 1844 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 1845 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 1846 } 1847 1848 /* 1849 * Enable interrupts. 1850 */ 1851 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 1852#ifdef DEVICE_POLLING 1853 /* 1854 * ... only enable interrupts if we are not polling, make sure 1855 * they are off otherwise. 1856 */ 1857 if (ifp->if_ipending & IFF_POLLING) 1858 CSR_WRITE_4(sc, SIS_IER, 0); 1859 else 1860#endif /* DEVICE_POLLING */ 1861 CSR_WRITE_4(sc, SIS_IER, 1); 1862 1863 /* Enable receiver and transmitter. */ 1864 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 1865 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1866 1867#ifdef notdef 1868 mii_mediachg(mii); 1869#endif 1870 1871 /* 1872 * Page 75 of the DP83815 manual recommends the 1873 * following register settings "for optimum 1874 * performance." Note however that at least three 1875 * of the registers are listed as "reserved" in 1876 * the register map, so who knows what they do. 1877 */ 1878 if (sc->sis_type == SIS_TYPE_83815) { 1879 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 1880 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 1881 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 1882 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 1883 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 1884 } 1885 1886 ifp->if_flags |= IFF_RUNNING; 1887 ifp->if_flags &= ~IFF_OACTIVE; 1888 1889 sc->sis_stat_ch = timeout(sis_tick, sc, hz); 1890 1891 SIS_UNLOCK(sc); 1892 1893 return; 1894} 1895 1896/* 1897 * Set media options. 1898 */ 1899static int sis_ifmedia_upd(ifp) 1900 struct ifnet *ifp; 1901{ 1902 struct sis_softc *sc; 1903 struct mii_data *mii; 1904 1905 sc = ifp->if_softc; 1906 1907 mii = device_get_softc(sc->sis_miibus); 1908 sc->sis_link = 0; 1909 if (mii->mii_instance) { 1910 struct mii_softc *miisc; 1911 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1912 mii_phy_reset(miisc); 1913 } 1914 mii_mediachg(mii); 1915 1916 return(0); 1917} 1918 1919/* 1920 * Report current media status. 1921 */ 1922static void sis_ifmedia_sts(ifp, ifmr) 1923 struct ifnet *ifp; 1924 struct ifmediareq *ifmr; 1925{ 1926 struct sis_softc *sc; 1927 struct mii_data *mii; 1928 1929 sc = ifp->if_softc; 1930 1931 mii = device_get_softc(sc->sis_miibus); 1932 mii_pollstat(mii); 1933 ifmr->ifm_active = mii->mii_media_active; 1934 ifmr->ifm_status = mii->mii_media_status; 1935 1936 return; 1937} 1938 1939static int sis_ioctl(ifp, command, data) 1940 struct ifnet *ifp; 1941 u_long command; 1942 caddr_t data; 1943{ 1944 struct sis_softc *sc = ifp->if_softc; 1945 struct ifreq *ifr = (struct ifreq *) data; 1946 struct mii_data *mii; 1947 int error = 0; 1948 1949 switch(command) { 1950 case SIOCSIFADDR: 1951 case SIOCGIFADDR: 1952 case SIOCSIFMTU: 1953 error = ether_ioctl(ifp, command, data); 1954 break; 1955 case SIOCSIFFLAGS: 1956 if (ifp->if_flags & IFF_UP) { 1957 sis_init(sc); 1958 } else { 1959 if (ifp->if_flags & IFF_RUNNING) 1960 sis_stop(sc); 1961 } 1962 error = 0; 1963 break; 1964 case SIOCADDMULTI: 1965 case SIOCDELMULTI: 1966 SIS_LOCK(sc); 1967 if (sc->sis_type == SIS_TYPE_83815) 1968 sis_setmulti_ns(sc); 1969 else 1970 sis_setmulti_sis(sc); 1971 SIS_UNLOCK(sc); 1972 error = 0; 1973 break; 1974 case SIOCGIFMEDIA: 1975 case SIOCSIFMEDIA: 1976 mii = device_get_softc(sc->sis_miibus); 1977 SIS_LOCK(sc); 1978 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1979 SIS_UNLOCK(sc); 1980 break; 1981 default: 1982 error = EINVAL; 1983 break; 1984 } 1985 1986 return(error); 1987} 1988 1989static void sis_watchdog(ifp) 1990 struct ifnet *ifp; 1991{ 1992 struct sis_softc *sc; 1993 1994 sc = ifp->if_softc; 1995 1996 SIS_LOCK(sc); 1997 1998 ifp->if_oerrors++; 1999 printf("sis%d: watchdog timeout\n", sc->sis_unit); 2000 2001 sis_stop(sc); 2002 sis_reset(sc); 2003 sis_init(sc); 2004 2005 if (ifp->if_snd.ifq_head != NULL) 2006 sis_start(ifp); 2007 2008 SIS_UNLOCK(sc); 2009 2010 return; 2011} 2012 2013/* 2014 * Stop the adapter and free any mbufs allocated to the 2015 * RX and TX lists. 2016 */ 2017static void sis_stop(sc) 2018 struct sis_softc *sc; 2019{ 2020 register int i; 2021 struct ifnet *ifp; 2022 2023 SIS_LOCK(sc); 2024 ifp = &sc->arpcom.ac_if; 2025 ifp->if_timer = 0; 2026 2027 untimeout(sis_tick, sc, sc->sis_stat_ch); 2028 2029 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2030#ifdef DEVICE_POLLING 2031 ether_poll_deregister(ifp); 2032#endif 2033 CSR_WRITE_4(sc, SIS_IER, 0); 2034 CSR_WRITE_4(sc, SIS_IMR, 0); 2035 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2036 DELAY(1000); 2037 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 2038 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2039 2040 sc->sis_link = 0; 2041 2042 /* 2043 * Free data in the RX lists. 2044 */ 2045 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 2046 if (sc->sis_ldata.sis_rx_list[i].sis_mbuf != NULL) { 2047 bus_dmamap_unload(sc->sis_tag, 2048 sc->sis_ldata.sis_rx_list[i].sis_map); 2049 bus_dmamap_destroy(sc->sis_tag, 2050 sc->sis_ldata.sis_rx_list[i].sis_map); 2051 m_freem(sc->sis_ldata.sis_rx_list[i].sis_mbuf); 2052 sc->sis_ldata.sis_rx_list[i].sis_mbuf = NULL; 2053 } 2054 } 2055 bzero(sc->sis_ldata.sis_rx_list, 2056 sizeof(sc->sis_ldata.sis_rx_list)); 2057 2058 /* 2059 * Free the TX list buffers. 2060 */ 2061 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 2062 if (sc->sis_ldata.sis_tx_list[i].sis_mbuf != NULL) { 2063 bus_dmamap_unload(sc->sis_tag, 2064 sc->sis_ldata.sis_tx_list[i].sis_map); 2065 bus_dmamap_destroy(sc->sis_tag, 2066 sc->sis_ldata.sis_tx_list[i].sis_map); 2067 m_freem(sc->sis_ldata.sis_tx_list[i].sis_mbuf); 2068 sc->sis_ldata.sis_tx_list[i].sis_mbuf = NULL; 2069 } 2070 } 2071 2072 bzero(sc->sis_ldata.sis_tx_list, 2073 sizeof(sc->sis_ldata.sis_tx_list)); 2074 2075 SIS_UNLOCK(sc); 2076 2077 return; 2078} 2079 2080/* 2081 * Stop all chip I/O so that the kernel's probe routines don't 2082 * get confused by errant DMAs when rebooting. 2083 */ 2084static void sis_shutdown(dev) 2085 device_t dev; 2086{ 2087 struct sis_softc *sc; 2088 2089 sc = device_get_softc(dev); 2090 SIS_LOCK(sc); 2091 sis_reset(sc); 2092 sis_stop(sc); 2093 SIS_UNLOCK(sc); 2094 2095 return; 2096} 2097