if_sis.c revision 87994
1103856Stjr/* 2103856Stjr * Copyright (c) 1997, 1998, 1999 3103856Stjr * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4103856Stjr * 5227753Stheraven * Redistribution and use in source and binary forms, with or without 6227753Stheraven * modification, are permitted provided that the following conditions 7227753Stheraven * are met: 8227753Stheraven * 1. Redistributions of source code must retain the above copyright 9227753Stheraven * notice, this list of conditions and the following disclaimer. 10103856Stjr * 2. Redistributions in binary form must reproduce the above copyright 11103856Stjr * notice, this list of conditions and the following disclaimer in the 12103856Stjr * documentation and/or other materials provided with the distribution. 13103856Stjr * 3. All advertising materials mentioning features or use of this software 14103856Stjr * must display the following acknowledgement: 15103856Stjr * This product includes software developed by Bill Paul. 16103856Stjr * 4. Neither the name of the author nor the names of any co-contributors 17103856Stjr * may be used to endorse or promote products derived from this software 18103856Stjr * without specific prior written permission. 19103856Stjr * 20103856Stjr * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21103856Stjr * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22103856Stjr * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23103856Stjr * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24103856Stjr * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25103856Stjr * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26103856Stjr * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27103856Stjr * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28103856Stjr * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29103856Stjr * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30103856Stjr * THE POSSIBILITY OF SUCH DAMAGE. 31103856Stjr * 32103856Stjr * $FreeBSD: head/sys/pci/if_sis.c 87994 2001-12-15 19:59:28Z archie $ 33103856Stjr */ 34103856Stjr 35103856Stjr/* 36103856Stjr * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 37103856Stjr * available from http://www.sis.com.tw. 38227753Stheraven * 39103856Stjr * This driver also supports the NatSemi DP83815. Datasheets are 40103856Stjr * available from http://www.national.com. 41103856Stjr * 42103856Stjr * Written by Bill Paul <wpaul@ee.columbia.edu> 43103856Stjr * Electrical Engineering Department 44103856Stjr * Columbia University, New York City 45103856Stjr */ 46103856Stjr 47103856Stjr/* 48103856Stjr * The SiS 900 is a fairly simple chip. It uses bus master DMA with 49103856Stjr * simple TX and RX descriptors of 3 longwords in size. The receiver 50103856Stjr * has a single perfect filter entry for the station address and a 51103856Stjr * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 52227753Stheraven * transceiver while the 7016 requires an external transceiver chip. 53227753Stheraven * Both chips offer the standard bit-bang MII interface as well as 54227753Stheraven * an enchanced PHY interface which simplifies accessing MII registers. 55227753Stheraven * 56227753Stheraven * The only downside to this chipset is that RX descriptors must be 57227753Stheraven * longword aligned. 58227753Stheraven */ 59227753Stheraven 60227753Stheraven#include <sys/param.h> 61227753Stheraven#include <sys/systm.h> 62227753Stheraven#include <sys/sockio.h> 63227753Stheraven#include <sys/mbuf.h> 64#include <sys/malloc.h> 65#include <sys/kernel.h> 66#include <sys/socket.h> 67#include <sys/sysctl.h> 68 69#include <net/if.h> 70#include <net/if_arp.h> 71#include <net/ethernet.h> 72#include <net/if_dl.h> 73#include <net/if_media.h> 74#include <net/if_types.h> 75#include <net/if_vlan_var.h> 76 77#include <net/bpf.h> 78 79#include <machine/bus_pio.h> 80#include <machine/bus_memio.h> 81#include <machine/bus.h> 82#include <machine/resource.h> 83#include <sys/bus.h> 84#include <sys/rman.h> 85 86#include <dev/mii/mii.h> 87#include <dev/mii/miivar.h> 88 89#include <pci/pcireg.h> 90#include <pci/pcivar.h> 91 92#define SIS_USEIOSPACE 93 94#include <pci/if_sisreg.h> 95 96MODULE_DEPEND(sis, miibus, 1, 1, 1); 97 98/* "controller miibus0" required. See GENERIC if you get errors here. */ 99#include "miibus_if.h" 100 101#ifndef lint 102static const char rcsid[] = 103 "$FreeBSD: head/sys/pci/if_sis.c 87994 2001-12-15 19:59:28Z archie $"; 104#endif 105 106/* 107 * Various supported device vendors/types and their names. 108 */ 109static struct sis_type sis_devs[] = { 110 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 111 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 112 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP83815 10/100BaseTX" }, 113 { 0, 0, NULL } 114}; 115 116static int sis_probe __P((device_t)); 117static int sis_attach __P((device_t)); 118static int sis_detach __P((device_t)); 119 120static int sis_newbuf __P((struct sis_softc *, 121 struct sis_desc *, 122 struct mbuf *)); 123static int sis_encap __P((struct sis_softc *, 124 struct mbuf *, u_int32_t *)); 125static void sis_rxeof __P((struct sis_softc *)); 126static void sis_rxeoc __P((struct sis_softc *)); 127static void sis_txeof __P((struct sis_softc *)); 128static void sis_intr __P((void *)); 129static void sis_tick __P((void *)); 130static void sis_start __P((struct ifnet *)); 131static int sis_ioctl __P((struct ifnet *, u_long, caddr_t)); 132static void sis_init __P((void *)); 133static void sis_stop __P((struct sis_softc *)); 134static void sis_watchdog __P((struct ifnet *)); 135static void sis_shutdown __P((device_t)); 136static int sis_ifmedia_upd __P((struct ifnet *)); 137static void sis_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 138 139static u_int16_t sis_reverse __P((u_int16_t)); 140static void sis_delay __P((struct sis_softc *)); 141static void sis_eeprom_idle __P((struct sis_softc *)); 142static void sis_eeprom_putbyte __P((struct sis_softc *, int)); 143static void sis_eeprom_getword __P((struct sis_softc *, int, u_int16_t *)); 144static void sis_read_eeprom __P((struct sis_softc *, caddr_t, int, 145 int, int)); 146#ifdef __i386__ 147static void sis_read_cmos __P((struct sis_softc *, device_t, caddr_t, 148 int, int)); 149static device_t sis_find_bridge __P((device_t)); 150#endif 151 152static int sis_miibus_readreg __P((device_t, int, int)); 153static int sis_miibus_writereg __P((device_t, int, int, int)); 154static void sis_miibus_statchg __P((device_t)); 155 156static void sis_setmulti_sis __P((struct sis_softc *)); 157static void sis_setmulti_ns __P((struct sis_softc *)); 158static u_int32_t sis_crc __P((struct sis_softc *, caddr_t)); 159static void sis_reset __P((struct sis_softc *)); 160static int sis_list_rx_init __P((struct sis_softc *)); 161static int sis_list_tx_init __P((struct sis_softc *)); 162 163static void sis_dma_map_desc_ptr __P((void *, bus_dma_segment_t *, 164 int, int)); 165static void sis_dma_map_desc_next __P((void *, bus_dma_segment_t *, 166 int, int)); 167static void sis_dma_map_ring __P((void *, bus_dma_segment_t *, 168 int, int)); 169#ifdef SIS_USEIOSPACE 170#define SIS_RES SYS_RES_IOPORT 171#define SIS_RID SIS_PCI_LOIO 172#else 173#define SIS_RES SYS_RES_MEMORY 174#define SIS_RID SIS_PCI_LOMEM 175#endif 176 177static device_method_t sis_methods[] = { 178 /* Device interface */ 179 DEVMETHOD(device_probe, sis_probe), 180 DEVMETHOD(device_attach, sis_attach), 181 DEVMETHOD(device_detach, sis_detach), 182 DEVMETHOD(device_shutdown, sis_shutdown), 183 184 /* bus interface */ 185 DEVMETHOD(bus_print_child, bus_generic_print_child), 186 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 187 188 /* MII interface */ 189 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 190 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 191 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 192 193 { 0, 0 } 194}; 195 196static driver_t sis_driver = { 197 "sis", 198 sis_methods, 199 sizeof(struct sis_softc) 200}; 201 202static devclass_t sis_devclass; 203 204#ifdef __i386__ 205static int sis_quick=1; 206SYSCTL_INT(_hw, OID_AUTO, sis_quick, CTLFLAG_RW, 207 &sis_quick,0,"do not mdevget in sis driver"); 208#endif 209 210DRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, 0, 0); 211DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 212 213#define SIS_SETBIT(sc, reg, x) \ 214 CSR_WRITE_4(sc, reg, \ 215 CSR_READ_4(sc, reg) | (x)) 216 217#define SIS_CLRBIT(sc, reg, x) \ 218 CSR_WRITE_4(sc, reg, \ 219 CSR_READ_4(sc, reg) & ~(x)) 220 221#define SIO_SET(x) \ 222 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 223 224#define SIO_CLR(x) \ 225 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 226 227static void 228sis_dma_map_desc_next(arg, segs, nseg, error) 229 void *arg; 230 bus_dma_segment_t *segs; 231 int nseg, error; 232{ 233 struct sis_desc *r; 234 235 r = arg; 236 r->sis_next = segs->ds_addr; 237 238 return; 239} 240 241static void 242sis_dma_map_desc_ptr(arg, segs, nseg, error) 243 void *arg; 244 bus_dma_segment_t *segs; 245 int nseg, error; 246{ 247 struct sis_desc *r; 248 249 r = arg; 250 r->sis_ptr = segs->ds_addr; 251 252 return; 253} 254 255static void 256sis_dma_map_ring(arg, segs, nseg, error) 257 void *arg; 258 bus_dma_segment_t *segs; 259 int nseg, error; 260{ 261 u_int32_t *p; 262 263 p = arg; 264 *p = segs->ds_addr; 265 266 return; 267} 268 269/* 270 * Routine to reverse the bits in a word. Stolen almost 271 * verbatim from /usr/games/fortune. 272 */ 273static u_int16_t sis_reverse(n) 274 u_int16_t n; 275{ 276 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 277 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 278 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 279 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 280 281 return(n); 282} 283 284static void sis_delay(sc) 285 struct sis_softc *sc; 286{ 287 int idx; 288 289 for (idx = (300 / 33) + 1; idx > 0; idx--) 290 CSR_READ_4(sc, SIS_CSR); 291 292 return; 293} 294 295static void sis_eeprom_idle(sc) 296 struct sis_softc *sc; 297{ 298 register int i; 299 300 SIO_SET(SIS_EECTL_CSEL); 301 sis_delay(sc); 302 SIO_SET(SIS_EECTL_CLK); 303 sis_delay(sc); 304 305 for (i = 0; i < 25; i++) { 306 SIO_CLR(SIS_EECTL_CLK); 307 sis_delay(sc); 308 SIO_SET(SIS_EECTL_CLK); 309 sis_delay(sc); 310 } 311 312 SIO_CLR(SIS_EECTL_CLK); 313 sis_delay(sc); 314 SIO_CLR(SIS_EECTL_CSEL); 315 sis_delay(sc); 316 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 317 318 return; 319} 320 321/* 322 * Send a read command and address to the EEPROM, check for ACK. 323 */ 324static void sis_eeprom_putbyte(sc, addr) 325 struct sis_softc *sc; 326 int addr; 327{ 328 register int d, i; 329 330 d = addr | SIS_EECMD_READ; 331 332 /* 333 * Feed in each bit and stobe the clock. 334 */ 335 for (i = 0x400; i; i >>= 1) { 336 if (d & i) { 337 SIO_SET(SIS_EECTL_DIN); 338 } else { 339 SIO_CLR(SIS_EECTL_DIN); 340 } 341 sis_delay(sc); 342 SIO_SET(SIS_EECTL_CLK); 343 sis_delay(sc); 344 SIO_CLR(SIS_EECTL_CLK); 345 sis_delay(sc); 346 } 347 348 return; 349} 350 351/* 352 * Read a word of data stored in the EEPROM at address 'addr.' 353 */ 354static void sis_eeprom_getword(sc, addr, dest) 355 struct sis_softc *sc; 356 int addr; 357 u_int16_t *dest; 358{ 359 register int i; 360 u_int16_t word = 0; 361 362 /* Force EEPROM to idle state. */ 363 sis_eeprom_idle(sc); 364 365 /* Enter EEPROM access mode. */ 366 sis_delay(sc); 367 SIO_CLR(SIS_EECTL_CLK); 368 sis_delay(sc); 369 SIO_SET(SIS_EECTL_CSEL); 370 sis_delay(sc); 371 372 /* 373 * Send address of word we want to read. 374 */ 375 sis_eeprom_putbyte(sc, addr); 376 377 /* 378 * Start reading bits from EEPROM. 379 */ 380 for (i = 0x8000; i; i >>= 1) { 381 SIO_SET(SIS_EECTL_CLK); 382 sis_delay(sc); 383 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 384 word |= i; 385 sis_delay(sc); 386 SIO_CLR(SIS_EECTL_CLK); 387 sis_delay(sc); 388 } 389 390 /* Turn off EEPROM access mode. */ 391 sis_eeprom_idle(sc); 392 393 *dest = word; 394 395 return; 396} 397 398/* 399 * Read a sequence of words from the EEPROM. 400 */ 401static void sis_read_eeprom(sc, dest, off, cnt, swap) 402 struct sis_softc *sc; 403 caddr_t dest; 404 int off; 405 int cnt; 406 int swap; 407{ 408 int i; 409 u_int16_t word = 0, *ptr; 410 411 for (i = 0; i < cnt; i++) { 412 sis_eeprom_getword(sc, off + i, &word); 413 ptr = (u_int16_t *)(dest + (i * 2)); 414 if (swap) 415 *ptr = ntohs(word); 416 else 417 *ptr = word; 418 } 419 420 return; 421} 422 423#ifdef __i386__ 424static device_t sis_find_bridge(dev) 425 device_t dev; 426{ 427 devclass_t pci_devclass; 428 device_t *pci_devices; 429 int pci_count = 0; 430 device_t *pci_children; 431 int pci_childcount = 0; 432 device_t *busp, *childp; 433 device_t child = NULL; 434 int i, j; 435 436 if ((pci_devclass = devclass_find("pci")) == NULL) 437 return(NULL); 438 439 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 440 441 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 442 pci_childcount = 0; 443 device_get_children(*busp, &pci_children, &pci_childcount); 444 for (j = 0, childp = pci_children; 445 j < pci_childcount; j++, childp++) { 446 if (pci_get_vendor(*childp) == SIS_VENDORID && 447 pci_get_device(*childp) == 0x0008) { 448 child = *childp; 449 goto done; 450 } 451 } 452 } 453 454done: 455 free(pci_devices, M_TEMP); 456 free(pci_children, M_TEMP); 457 return(child); 458} 459 460static void sis_read_cmos(sc, dev, dest, off, cnt) 461 struct sis_softc *sc; 462 device_t dev; 463 caddr_t dest; 464 int off; 465 int cnt; 466{ 467 device_t bridge; 468 u_int8_t reg; 469 int i; 470 bus_space_tag_t btag; 471 472 bridge = sis_find_bridge(dev); 473 if (bridge == NULL) 474 return; 475 reg = pci_read_config(bridge, 0x48, 1); 476 pci_write_config(bridge, 0x48, reg|0x40, 1); 477 478 /* XXX */ 479 btag = I386_BUS_SPACE_IO; 480 481 for (i = 0; i < cnt; i++) { 482 bus_space_write_1(btag, 0x0, 0x70, i + off); 483 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 484 } 485 486 pci_write_config(bridge, 0x48, reg & ~0x40, 1); 487 return; 488} 489#endif 490 491static int sis_miibus_readreg(dev, phy, reg) 492 device_t dev; 493 int phy, reg; 494{ 495 struct sis_softc *sc; 496 int i, val = 0; 497 498 sc = device_get_softc(dev); 499 500 if (sc->sis_type == SIS_TYPE_83815) { 501 if (phy != 0) 502 return(0); 503 /* 504 * The NatSemi chip can take a while after 505 * a reset to come ready, during which the BMSR 506 * returns a value of 0. This is *never* supposed 507 * to happen: some of the BMSR bits are meant to 508 * be hardwired in the on position, and this can 509 * confuse the miibus code a bit during the probe 510 * and attach phase. So we make an effort to check 511 * for this condition and wait for it to clear. 512 */ 513 if (!CSR_READ_4(sc, NS_BMSR)) 514 DELAY(1000); 515 val = CSR_READ_4(sc, NS_BMCR + (reg * 4)); 516 return(val); 517 } 518 519 if (sc->sis_type == SIS_TYPE_900 && phy != 0) 520 return(0); 521 522 CSR_WRITE_4(sc, SIS_PHYCTL, (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 523 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 524 525 for (i = 0; i < SIS_TIMEOUT; i++) { 526 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 527 break; 528 } 529 530 if (i == SIS_TIMEOUT) { 531 printf("sis%d: PHY failed to come ready\n", sc->sis_unit); 532 return(0); 533 } 534 535 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 536 537 if (val == 0xFFFF) 538 return(0); 539 540 return(val); 541} 542 543static int sis_miibus_writereg(dev, phy, reg, data) 544 device_t dev; 545 int phy, reg, data; 546{ 547 struct sis_softc *sc; 548 int i; 549 550 sc = device_get_softc(dev); 551 552 if (sc->sis_type == SIS_TYPE_83815) { 553 if (phy != 0) 554 return(0); 555 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 556 return(0); 557 } 558 559 if (sc->sis_type == SIS_TYPE_900 && phy != 0) 560 return(0); 561 562 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 563 (reg << 6) | SIS_PHYOP_WRITE); 564 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 565 566 for (i = 0; i < SIS_TIMEOUT; i++) { 567 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 568 break; 569 } 570 571 if (i == SIS_TIMEOUT) 572 printf("sis%d: PHY failed to come ready\n", sc->sis_unit); 573 574 return(0); 575} 576 577static void sis_miibus_statchg(dev) 578 device_t dev; 579{ 580 struct sis_softc *sc; 581 582 sc = device_get_softc(dev); 583 sis_init(sc); 584 585 return; 586} 587 588static u_int32_t sis_crc(sc, addr) 589 struct sis_softc *sc; 590 caddr_t addr; 591{ 592 u_int32_t crc, carry; 593 int i, j; 594 u_int8_t c; 595 596 /* Compute CRC for the address value. */ 597 crc = 0xFFFFFFFF; /* initial value */ 598 599 for (i = 0; i < 6; i++) { 600 c = *(addr + i); 601 for (j = 0; j < 8; j++) { 602 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 603 crc <<= 1; 604 c >>= 1; 605 if (carry) 606 crc = (crc ^ 0x04c11db6) | carry; 607 } 608 } 609 610 /* 611 * return the filter bit position 612 * 613 * The NatSemi chip has a 512-bit filter, which is 614 * different than the SiS, so we special-case it. 615 */ 616 if (sc->sis_type == SIS_TYPE_83815) 617 return((crc >> 23) & 0x1FF); 618 619 return((crc >> 25) & 0x0000007F); 620} 621 622static void sis_setmulti_ns(sc) 623 struct sis_softc *sc; 624{ 625 struct ifnet *ifp; 626 struct ifmultiaddr *ifma; 627 u_int32_t h = 0, i, filtsave; 628 int bit, index; 629 630 ifp = &sc->arpcom.ac_if; 631 632 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 633 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 634 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 635 return; 636 } 637 638 /* 639 * We have to explicitly enable the multicast hash table 640 * on the NatSemi chip if we want to use it, which we do. 641 */ 642 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 643 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 644 645 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 646 647 /* first, zot all the existing hash bits */ 648 for (i = 0; i < 32; i++) { 649 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 650 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 651 } 652 653 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 654 if (ifma->ifma_addr->sa_family != AF_LINK) 655 continue; 656 h = sis_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 657 index = h >> 3; 658 bit = h & 0x1F; 659 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 660 if (bit > 0xF) 661 bit -= 0x10; 662 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 663 } 664 665 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 666 667 return; 668} 669 670static void sis_setmulti_sis(sc) 671 struct sis_softc *sc; 672{ 673 struct ifnet *ifp; 674 struct ifmultiaddr *ifma; 675 u_int32_t h = 0, i, filtsave; 676 677 ifp = &sc->arpcom.ac_if; 678 679 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 680 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 681 return; 682 } 683 684 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 685 686 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 687 688 /* first, zot all the existing hash bits */ 689 for (i = 0; i < 8; i++) { 690 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + ((i * 16) >> 4)) << 16); 691 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 692 } 693 694 /* now program new ones */ 695 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 696 if (ifma->ifma_addr->sa_family != AF_LINK) 697 continue; 698 h = sis_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 699 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + (h >> 4)) << 16); 700 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << (h & 0xF))); 701 } 702 703 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 704 705 return; 706} 707 708static void sis_reset(sc) 709 struct sis_softc *sc; 710{ 711 register int i; 712 713 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 714 715 for (i = 0; i < SIS_TIMEOUT; i++) { 716 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 717 break; 718 } 719 720 if (i == SIS_TIMEOUT) 721 printf("sis%d: reset never completed\n", sc->sis_unit); 722 723 /* Wait a little while for the chip to get its brains in order. */ 724 DELAY(1000); 725 726 /* 727 * If this is a NetSemi chip, make sure to clear 728 * PME mode. 729 */ 730 if (sc->sis_type == SIS_TYPE_83815) { 731 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 732 CSR_WRITE_4(sc, NS_CLKRUN, 0); 733 } 734 735 return; 736} 737 738/* 739 * Probe for an SiS chip. Check the PCI vendor and device 740 * IDs against our list and return a device name if we find a match. 741 */ 742static int sis_probe(dev) 743 device_t dev; 744{ 745 struct sis_type *t; 746 747 t = sis_devs; 748 749 while(t->sis_name != NULL) { 750 if ((pci_get_vendor(dev) == t->sis_vid) && 751 (pci_get_device(dev) == t->sis_did)) { 752 device_set_desc(dev, t->sis_name); 753 return(0); 754 } 755 t++; 756 } 757 758 return(ENXIO); 759} 760 761/* 762 * Attach the interface. Allocate softc structures, do ifmedia 763 * setup and ethernet/BPF attach. 764 */ 765static int sis_attach(dev) 766 device_t dev; 767{ 768 u_char eaddr[ETHER_ADDR_LEN]; 769 u_int32_t command; 770 struct sis_softc *sc; 771 struct ifnet *ifp; 772 int unit, error = 0, rid; 773 774 sc = device_get_softc(dev); 775 unit = device_get_unit(dev); 776 bzero(sc, sizeof(struct sis_softc)); 777 778 mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 779 SIS_LOCK(sc); 780 781 if (pci_get_device(dev) == SIS_DEVICEID_900) 782 sc->sis_type = SIS_TYPE_900; 783 if (pci_get_device(dev) == SIS_DEVICEID_7016) 784 sc->sis_type = SIS_TYPE_7016; 785 if (pci_get_vendor(dev) == NS_VENDORID) 786 sc->sis_type = SIS_TYPE_83815; 787 788 /* 789 * Handle power management nonsense. 790 */ 791 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 792 u_int32_t iobase, membase, irq; 793 794 /* Save important PCI config data. */ 795 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4); 796 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4); 797 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4); 798 799 /* Reset the power state. */ 800 printf("sis%d: chip is in D%d power mode " 801 "-- setting to D0\n", unit, 802 pci_get_powerstate(dev)); 803 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 804 805 /* Restore PCI config data. */ 806 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4); 807 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4); 808 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4); 809 } 810 811 /* 812 * Map control/status registers. 813 */ 814 pci_enable_busmaster(dev); 815 pci_enable_io(dev, SYS_RES_IOPORT); 816 pci_enable_io(dev, SYS_RES_MEMORY); 817 command = pci_read_config(dev, PCIR_COMMAND, 4); 818 819#ifdef SIS_USEIOSPACE 820 if (!(command & PCIM_CMD_PORTEN)) { 821 printf("sis%d: failed to enable I/O ports!\n", unit); 822 error = ENXIO;; 823 goto fail; 824 } 825#else 826 if (!(command & PCIM_CMD_MEMEN)) { 827 printf("sis%d: failed to enable memory mapping!\n", unit); 828 error = ENXIO;; 829 goto fail; 830 } 831#endif 832 833 rid = SIS_RID; 834 sc->sis_res = bus_alloc_resource(dev, SIS_RES, &rid, 835 0, ~0, 1, RF_ACTIVE); 836 837 if (sc->sis_res == NULL) { 838 printf("sis%d: couldn't map ports/memory\n", unit); 839 error = ENXIO; 840 goto fail; 841 } 842 843 sc->sis_btag = rman_get_bustag(sc->sis_res); 844 sc->sis_bhandle = rman_get_bushandle(sc->sis_res); 845 846 /* Allocate interrupt */ 847 rid = 0; 848 sc->sis_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 849 RF_SHAREABLE | RF_ACTIVE); 850 851 if (sc->sis_irq == NULL) { 852 printf("sis%d: couldn't map interrupt\n", unit); 853 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 854 error = ENXIO; 855 goto fail; 856 } 857 858 error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET, 859 sis_intr, sc, &sc->sis_intrhand); 860 861 if (error) { 862 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 863 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 864 printf("sis%d: couldn't set up irq\n", unit); 865 goto fail; 866 } 867 868 /* Reset the adapter. */ 869 sis_reset(sc); 870 871 /* 872 * Get station address from the EEPROM. 873 */ 874 switch (pci_get_vendor(dev)) { 875 case NS_VENDORID: 876 /* 877 * Reading the MAC address out of the EEPROM on 878 * the NatSemi chip takes a bit more work than 879 * you'd expect. The address spans 4 16-bit words, 880 * with the first word containing only a single bit. 881 * You have to shift everything over one bit to 882 * get it aligned properly. Also, the bits are 883 * stored backwards (the LSB is really the MSB, 884 * and so on) so you have to reverse them in order 885 * to get the MAC address into the form we want. 886 * Why? Who the hell knows. 887 */ 888 { 889 u_int16_t tmp[4]; 890 891 sis_read_eeprom(sc, (caddr_t)&tmp, 892 NS_EE_NODEADDR, 4, 0); 893 894 /* Shift everything over one bit. */ 895 tmp[3] = tmp[3] >> 1; 896 tmp[3] |= tmp[2] << 15; 897 tmp[2] = tmp[2] >> 1; 898 tmp[2] |= tmp[1] << 15; 899 tmp[1] = tmp[1] >> 1; 900 tmp[1] |= tmp[0] << 15; 901 902 /* Now reverse all the bits. */ 903 tmp[3] = sis_reverse(tmp[3]); 904 tmp[2] = sis_reverse(tmp[2]); 905 tmp[1] = sis_reverse(tmp[1]); 906 907 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); 908 } 909 break; 910 case SIS_VENDORID: 911 default: 912#ifdef __i386__ 913 /* 914 * If this is a SiS 630E chipset with an embedded 915 * SiS 900 controller, we have to read the MAC address 916 * from the APC CMOS RAM. Our method for doing this 917 * is very ugly since we have to reach out and grab 918 * ahold of hardware for which we cannot properly 919 * allocate resources. This code is only compiled on 920 * the i386 architecture since the SiS 630E chipset 921 * is for x86 motherboards only. Note that there are 922 * a lot of magic numbers in this hack. These are 923 * taken from SiS's Linux driver. I'd like to replace 924 * them with proper symbolic definitions, but that 925 * requires some datasheets that I don't have access 926 * to at the moment. 927 */ 928 command = pci_read_config(dev, PCIR_REVID, 1); 929 if (command == SIS_REV_630S || 930 command == SIS_REV_630E || 931 command == SIS_REV_630EA1) 932 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 933 else 934#endif 935 sis_read_eeprom(sc, (caddr_t)&eaddr, 936 SIS_EE_NODEADDR, 3, 0); 937 break; 938 } 939 940 /* 941 * A SiS chip was detected. Inform the world. 942 */ 943 printf("sis%d: Ethernet address: %6D\n", unit, eaddr, ":"); 944 945 sc->sis_unit = unit; 946 callout_handle_init(&sc->sis_stat_ch); 947 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 948 949 /* 950 * Allocate the parent bus DMA tag appropriate for PCI. 951 */ 952#define SIS_NSEG_NEW 32 953 error = bus_dma_tag_create(NULL, /* parent */ 954 1, 0, /* alignment, boundary */ 955 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 956 BUS_SPACE_MAXADDR, /* highaddr */ 957 NULL, NULL, /* filter, filterarg */ 958 MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */ 959 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 960 BUS_DMA_ALLOCNOW, /* flags */ 961 &sc->sis_parent_tag); 962 963 /* 964 * Now allocate a tag for the DMA descriptor lists. 965 * All of our lists are allocated as a contiguous block 966 * of memory. 967 */ 968 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 969 1, 0, /* alignment, boundary */ 970 BUS_SPACE_MAXADDR, /* lowaddr */ 971 BUS_SPACE_MAXADDR, /* highaddr */ 972 NULL, NULL, /* filter, filterarg */ 973 SIS_RX_LIST_SZ, 1, /* maxsize,nsegments */ 974 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 975 0, /* flags */ 976 &sc->sis_ldata.sis_rx_tag); 977 978 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 979 1, 0, /* alignment, boundary */ 980 BUS_SPACE_MAXADDR, /* lowaddr */ 981 BUS_SPACE_MAXADDR, /* highaddr */ 982 NULL, NULL, /* filter, filterarg */ 983 SIS_TX_LIST_SZ, 1, /* maxsize,nsegments */ 984 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 985 0, /* flags */ 986 &sc->sis_ldata.sis_tx_tag); 987 988 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 989 1, 0, /* alignment, boundary */ 990 BUS_SPACE_MAXADDR, /* lowaddr */ 991 BUS_SPACE_MAXADDR, /* highaddr */ 992 NULL, NULL, /* filter, filterarg */ 993 SIS_TX_LIST_SZ, 1, /* maxsize,nsegments */ 994 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 995 0, /* flags */ 996 &sc->sis_tag); 997 998 /* 999 * Now allocate a chunk of DMA-able memory based on the 1000 * tag we just created. 1001 */ 1002 error = bus_dmamem_alloc(sc->sis_ldata.sis_tx_tag, 1003 (void **)&sc->sis_ldata.sis_tx_list, BUS_DMA_NOWAIT, 1004 &sc->sis_ldata.sis_tx_dmamap); 1005 1006 if (error) { 1007 printf("sis%d: no memory for list buffers!\n", unit); 1008 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1009 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1010 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1011 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1012 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1013 error = ENXIO; 1014 goto fail; 1015 } 1016 1017 error = bus_dmamem_alloc(sc->sis_ldata.sis_rx_tag, 1018 (void **)&sc->sis_ldata.sis_rx_list, BUS_DMA_NOWAIT, 1019 &sc->sis_ldata.sis_rx_dmamap); 1020 1021 if (error) { 1022 printf("sis%d: no memory for list buffers!\n", unit); 1023 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1024 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1025 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1026 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1027 sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 1028 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1029 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1030 error = ENXIO; 1031 goto fail; 1032 } 1033 1034 1035 bzero(sc->sis_ldata.sis_tx_list, SIS_TX_LIST_SZ); 1036 bzero(sc->sis_ldata.sis_rx_list, SIS_RX_LIST_SZ); 1037 1038 /* 1039 * Obtain the physical addresses of the RX and TX 1040 * rings which we'll need later in the init routine. 1041 */ 1042 bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1043 sc->sis_ldata.sis_tx_dmamap, &(sc->sis_ldata.sis_tx_list[0]), 1044 sizeof(struct sis_desc), sis_dma_map_ring, 1045 &sc->sis_cdata.sis_tx_paddr, 0); 1046 bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1047 sc->sis_ldata.sis_rx_dmamap, &(sc->sis_ldata.sis_rx_list[0]), 1048 sizeof(struct sis_desc), sis_dma_map_ring, 1049 &sc->sis_cdata.sis_rx_paddr, 0); 1050 1051 ifp = &sc->arpcom.ac_if; 1052 ifp->if_softc = sc; 1053 ifp->if_unit = unit; 1054 ifp->if_name = "sis"; 1055 ifp->if_mtu = ETHERMTU; 1056 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1057 ifp->if_ioctl = sis_ioctl; 1058 ifp->if_output = ether_output; 1059 ifp->if_start = sis_start; 1060 ifp->if_watchdog = sis_watchdog; 1061 ifp->if_init = sis_init; 1062 ifp->if_baudrate = 10000000; 1063 ifp->if_snd.ifq_maxlen = SIS_TX_LIST_CNT - 1; 1064 1065 /* 1066 * Do MII setup. 1067 */ 1068 if (mii_phy_probe(dev, &sc->sis_miibus, 1069 sis_ifmedia_upd, sis_ifmedia_sts)) { 1070 printf("sis%d: MII without any PHY!\n", sc->sis_unit); 1071 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1072 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1073 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1074 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1075 sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap); 1076 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1077 sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 1078 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1079 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1080 error = ENXIO; 1081 goto fail; 1082 } 1083 1084 /* 1085 * Call MI attach routine. 1086 */ 1087 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1088 1089 /* 1090 * Tell the upper layer(s) we support long frames. 1091 */ 1092 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1093 1094 callout_handle_init(&sc->sis_stat_ch); 1095 SIS_UNLOCK(sc); 1096 return(0); 1097 1098fail: 1099 SIS_UNLOCK(sc); 1100 mtx_destroy(&sc->sis_mtx); 1101 return(error); 1102} 1103 1104static int sis_detach(dev) 1105 device_t dev; 1106{ 1107 struct sis_softc *sc; 1108 struct ifnet *ifp; 1109 1110 1111 sc = device_get_softc(dev); 1112 SIS_LOCK(sc); 1113 ifp = &sc->arpcom.ac_if; 1114 1115 sis_reset(sc); 1116 sis_stop(sc); 1117 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1118 1119 bus_generic_detach(dev); 1120 device_delete_child(dev, sc->sis_miibus); 1121 1122 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1123 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1124 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1125 1126 bus_dmamap_unload(sc->sis_ldata.sis_rx_tag, 1127 sc->sis_ldata.sis_rx_dmamap); 1128 bus_dmamap_unload(sc->sis_ldata.sis_tx_tag, 1129 sc->sis_ldata.sis_tx_dmamap); 1130 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1131 sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap); 1132 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1133 sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 1134 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1135 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1136 bus_dma_tag_destroy(sc->sis_parent_tag); 1137 1138 SIS_UNLOCK(sc); 1139 mtx_destroy(&sc->sis_mtx); 1140 1141 return(0); 1142} 1143 1144/* 1145 * Initialize the transmit descriptors. 1146 */ 1147static int sis_list_tx_init(sc) 1148 struct sis_softc *sc; 1149{ 1150 struct sis_list_data *ld; 1151 struct sis_ring_data *cd; 1152 int i, nexti; 1153 1154 cd = &sc->sis_cdata; 1155 ld = &sc->sis_ldata; 1156 1157 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1158 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1; 1159 ld->sis_tx_list[i].sis_nextdesc = 1160 &ld->sis_tx_list[nexti]; 1161 bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1162 sc->sis_ldata.sis_tx_dmamap, 1163 &ld->sis_tx_list[nexti], sizeof(struct sis_desc), 1164 sis_dma_map_desc_next, &ld->sis_tx_list[i], 0); 1165 ld->sis_tx_list[i].sis_mbuf = NULL; 1166 ld->sis_tx_list[i].sis_ptr = 0; 1167 ld->sis_tx_list[i].sis_ctl = 0; 1168 } 1169 1170 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0; 1171 1172 bus_dmamap_sync(sc->sis_ldata.sis_tx_tag, 1173 sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 1174 1175 return(0); 1176} 1177 1178/* 1179 * Initialize the RX descriptors and allocate mbufs for them. Note that 1180 * we arrange the descriptors in a closed ring, so that the last descriptor 1181 * points back to the first. 1182 */ 1183static int sis_list_rx_init(sc) 1184 struct sis_softc *sc; 1185{ 1186 struct sis_list_data *ld; 1187 struct sis_ring_data *cd; 1188 int i,nexti; 1189 1190 ld = &sc->sis_ldata; 1191 cd = &sc->sis_cdata; 1192 1193 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1194 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS) 1195 return(ENOBUFS); 1196 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1; 1197 ld->sis_rx_list[i].sis_nextdesc = 1198 &ld->sis_rx_list[nexti]; 1199 bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1200 sc->sis_ldata.sis_rx_dmamap, 1201 &ld->sis_rx_list[nexti], 1202 sizeof(struct sis_desc), sis_dma_map_desc_next, 1203 &ld->sis_rx_list[i], 0); 1204 } 1205 1206 bus_dmamap_sync(sc->sis_ldata.sis_rx_tag, 1207 sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 1208 1209 cd->sis_rx_prod = 0; 1210 1211 return(0); 1212} 1213 1214/* 1215 * Initialize an RX descriptor and attach an MBUF cluster. 1216 */ 1217static int sis_newbuf(sc, c, m) 1218 struct sis_softc *sc; 1219 struct sis_desc *c; 1220 struct mbuf *m; 1221{ 1222 struct mbuf *m_new = NULL; 1223 1224 if (c == NULL) 1225 return(EINVAL); 1226 1227 if (m == NULL) { 1228 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1229 if (m_new == NULL) 1230 return(ENOBUFS); 1231 1232 MCLGET(m_new, M_DONTWAIT); 1233 if (!(m_new->m_flags & M_EXT)) { 1234 m_freem(m_new); 1235 return(ENOBUFS); 1236 } 1237 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1238 } else { 1239 m_new = m; 1240 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1241 m_new->m_data = m_new->m_ext.ext_buf; 1242 } 1243 1244 m_adj(m_new, sizeof(u_int64_t)); 1245 1246 c->sis_mbuf = m_new; 1247 c->sis_ctl = SIS_RXLEN; 1248 1249 bus_dmamap_create(sc->sis_tag, 0, &c->sis_map); 1250 bus_dmamap_load(sc->sis_tag, c->sis_map, 1251 mtod(m_new, void *), m_new->m_len, 1252 sis_dma_map_desc_ptr, c, 0); 1253 bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREWRITE); 1254 1255 return(0); 1256} 1257 1258/* 1259 * A frame has been uploaded: pass the resulting mbuf chain up to 1260 * the higher level protocols. 1261 */ 1262static void sis_rxeof(sc) 1263 struct sis_softc *sc; 1264{ 1265 struct ether_header *eh; 1266 struct mbuf *m; 1267 struct ifnet *ifp; 1268 struct sis_desc *cur_rx; 1269 int i, total_len = 0; 1270 u_int32_t rxstat; 1271 1272 ifp = &sc->arpcom.ac_if; 1273 i = sc->sis_cdata.sis_rx_prod; 1274 1275 while(SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) { 1276 1277#ifdef DEVICE_POLLING 1278 if (ifp->if_ipending & IFF_POLLING) { 1279 if (sc->rxcycles <= 0) 1280 break; 1281 sc->rxcycles--; 1282 } 1283#endif /* DEVICE_POLLING */ 1284 cur_rx = &sc->sis_ldata.sis_rx_list[i]; 1285 rxstat = cur_rx->sis_rxstat; 1286 bus_dmamap_sync(sc->sis_tag, 1287 cur_rx->sis_map, BUS_DMASYNC_POSTWRITE); 1288 bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map); 1289 bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map); 1290 m = cur_rx->sis_mbuf; 1291 cur_rx->sis_mbuf = NULL; 1292 total_len = SIS_RXBYTES(cur_rx); 1293 SIS_INC(i, SIS_RX_LIST_CNT); 1294 1295 /* 1296 * If an error occurs, update stats, clear the 1297 * status word and leave the mbuf cluster in place: 1298 * it should simply get re-used next time this descriptor 1299 * comes up in the ring. 1300 */ 1301 if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 1302 ifp->if_ierrors++; 1303 if (rxstat & SIS_RXSTAT_COLL) 1304 ifp->if_collisions++; 1305 sis_newbuf(sc, cur_rx, m); 1306 continue; 1307 } 1308 1309 /* No errors; receive the packet. */ 1310#ifdef __i386__ 1311 /* 1312 * On the x86 we do not have alignment problems, so try to 1313 * allocate a new buffer for the receive ring, and pass up 1314 * the one where the packet is already, saving the expensive 1315 * copy done in m_devget(). 1316 * If we are on an architecture with alignment problems, or 1317 * if the allocation fails, then use m_devget and leave the 1318 * existing buffer in the receive ring. 1319 */ 1320 if (sis_quick && sis_newbuf(sc, cur_rx, NULL) == 0) { 1321 m->m_pkthdr.rcvif = ifp; 1322 m->m_pkthdr.len = m->m_len = total_len; 1323 } else 1324#endif 1325 { 1326 struct mbuf *m0; 1327 m0 = m_devget(mtod(m, char *), total_len, 1328 ETHER_ALIGN, ifp, NULL); 1329 sis_newbuf(sc, cur_rx, m); 1330 if (m0 == NULL) { 1331 ifp->if_ierrors++; 1332 continue; 1333 } 1334 m = m0; 1335 } 1336 1337 ifp->if_ipackets++; 1338 eh = mtod(m, struct ether_header *); 1339 1340 /* Remove header from mbuf and pass it on. */ 1341 m_adj(m, sizeof(struct ether_header)); 1342 ether_input(ifp, eh, m); 1343 } 1344 1345 sc->sis_cdata.sis_rx_prod = i; 1346 1347 return; 1348} 1349 1350void sis_rxeoc(sc) 1351 struct sis_softc *sc; 1352{ 1353 sis_rxeof(sc); 1354 sis_init(sc); 1355 return; 1356} 1357 1358/* 1359 * A frame was downloaded to the chip. It's safe for us to clean up 1360 * the list buffers. 1361 */ 1362 1363static void sis_txeof(sc) 1364 struct sis_softc *sc; 1365{ 1366 struct sis_desc *cur_tx = NULL; 1367 struct ifnet *ifp; 1368 u_int32_t idx; 1369 1370 ifp = &sc->arpcom.ac_if; 1371 1372 /* Clear the timeout timer. */ 1373 ifp->if_timer = 0; 1374 1375 /* 1376 * Go through our tx list and free mbufs for those 1377 * frames that have been transmitted. 1378 */ 1379 idx = sc->sis_cdata.sis_tx_cons; 1380 while (idx != sc->sis_cdata.sis_tx_prod) { 1381 cur_tx = &sc->sis_ldata.sis_tx_list[idx]; 1382 1383 if (SIS_OWNDESC(cur_tx)) 1384 break; 1385 1386 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) { 1387 sc->sis_cdata.sis_tx_cnt--; 1388 SIS_INC(idx, SIS_TX_LIST_CNT); 1389 continue; 1390 } 1391 1392 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 1393 ifp->if_oerrors++; 1394 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 1395 ifp->if_collisions++; 1396 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 1397 ifp->if_collisions++; 1398 } 1399 1400 ifp->if_collisions += 1401 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 1402 1403 ifp->if_opackets++; 1404 if (cur_tx->sis_mbuf != NULL) { 1405 m_freem(cur_tx->sis_mbuf); 1406 cur_tx->sis_mbuf = NULL; 1407 bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map); 1408 bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map); 1409 } 1410 1411 sc->sis_cdata.sis_tx_cnt--; 1412 SIS_INC(idx, SIS_TX_LIST_CNT); 1413 ifp->if_timer = 0; 1414 } 1415 1416 sc->sis_cdata.sis_tx_cons = idx; 1417 1418 if (cur_tx != NULL) 1419 ifp->if_flags &= ~IFF_OACTIVE; 1420 1421 return; 1422} 1423 1424static void sis_tick(xsc) 1425 void *xsc; 1426{ 1427 struct sis_softc *sc; 1428 struct mii_data *mii; 1429 struct ifnet *ifp; 1430 1431 sc = xsc; 1432 SIS_LOCK(sc); 1433 ifp = &sc->arpcom.ac_if; 1434 1435 mii = device_get_softc(sc->sis_miibus); 1436 mii_tick(mii); 1437 1438 if (!sc->sis_link && mii->mii_media_status & IFM_ACTIVE && 1439 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1440 sc->sis_link++; 1441 if (ifp->if_snd.ifq_head != NULL) 1442 sis_start(ifp); 1443 } 1444 1445 sc->sis_stat_ch = timeout(sis_tick, sc, hz); 1446 1447 SIS_UNLOCK(sc); 1448 1449 return; 1450} 1451 1452#ifdef DEVICE_POLLING 1453static poll_handler_t sis_poll; 1454 1455static void 1456sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1457{ 1458 struct sis_softc *sc = ifp->if_softc; 1459 1460 SIS_LOCK(sc); 1461 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1462 CSR_WRITE_4(sc, SIS_IER, 1); 1463 goto done; 1464 } 1465 1466 /* 1467 * On the sis, reading the status register also clears it. 1468 * So before returning to intr mode we must make sure that all 1469 * possible pending sources of interrupts have been served. 1470 * In practice this means run to completion the *eof routines, 1471 * and then call the interrupt routine 1472 */ 1473 sc->rxcycles = count; 1474 sis_rxeof(sc); 1475 sis_txeof(sc); 1476 if (ifp->if_snd.ifq_head != NULL) 1477 sis_start(ifp); 1478 1479 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1480 u_int32_t status; 1481 1482 /* Reading the ISR register clears all interrupts. */ 1483 status = CSR_READ_4(sc, SIS_ISR); 1484 1485 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 1486 sis_rxeoc(sc); 1487 1488 if (status & (SIS_ISR_RX_IDLE)) 1489 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1490 1491 if (status & SIS_ISR_SYSERR) { 1492 sis_reset(sc); 1493 sis_init(sc); 1494 } 1495 } 1496done: 1497 SIS_UNLOCK(sc); 1498 return; 1499} 1500#endif /* DEVICE_POLLING */ 1501 1502static void sis_intr(arg) 1503 void *arg; 1504{ 1505 struct sis_softc *sc; 1506 struct ifnet *ifp; 1507 u_int32_t status; 1508 1509 sc = arg; 1510 ifp = &sc->arpcom.ac_if; 1511 1512 SIS_LOCK(sc); 1513#ifdef DEVICE_POLLING 1514 if (ifp->if_ipending & IFF_POLLING) 1515 goto done; 1516 if (ether_poll_register(sis_poll, ifp)) { /* ok, disable interrupts */ 1517 CSR_WRITE_4(sc, SIS_IER, 0); 1518 goto done; 1519 } 1520#endif /* DEVICE_POLLING */ 1521 1522 /* Supress unwanted interrupts */ 1523 if (!(ifp->if_flags & IFF_UP)) { 1524 sis_stop(sc); 1525 goto done; 1526 } 1527 1528 /* Disable interrupts. */ 1529 CSR_WRITE_4(sc, SIS_IER, 0); 1530 1531 for (;;) { 1532 /* Reading the ISR register clears all interrupts. */ 1533 status = CSR_READ_4(sc, SIS_ISR); 1534 1535 if ((status & SIS_INTRS) == 0) 1536 break; 1537 1538 if (status & 1539 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | 1540 SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) ) 1541 sis_txeof(sc); 1542 1543 if (status & (SIS_ISR_RX_DESC_OK|SIS_ISR_RX_OK|SIS_ISR_RX_IDLE)) 1544 sis_rxeof(sc); 1545 1546 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW)) 1547 sis_rxeoc(sc); 1548 1549 if (status & (SIS_ISR_RX_IDLE)) 1550 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1551 1552 if (status & SIS_ISR_SYSERR) { 1553 sis_reset(sc); 1554 sis_init(sc); 1555 } 1556 } 1557 1558 /* Re-enable interrupts. */ 1559 CSR_WRITE_4(sc, SIS_IER, 1); 1560 1561 if (ifp->if_snd.ifq_head != NULL) 1562 sis_start(ifp); 1563done: 1564 SIS_UNLOCK(sc); 1565 1566 return; 1567} 1568 1569/* 1570 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1571 * pointers to the fragment pointers. 1572 */ 1573static int sis_encap(sc, m_head, txidx) 1574 struct sis_softc *sc; 1575 struct mbuf *m_head; 1576 u_int32_t *txidx; 1577{ 1578 struct sis_desc *f = NULL; 1579 struct mbuf *m; 1580 int frag, cur, cnt = 0; 1581 1582 /* 1583 * Start packing the mbufs in this chain into 1584 * the fragment pointers. Stop when we run out 1585 * of fragments or hit the end of the mbuf chain. 1586 */ 1587 m = m_head; 1588 cur = frag = *txidx; 1589 1590 for (m = m_head; m != NULL; m = m->m_next) { 1591 if (m->m_len != 0) { 1592 if ((SIS_TX_LIST_CNT - 1593 (sc->sis_cdata.sis_tx_cnt + cnt)) < 2) 1594 return(ENOBUFS); 1595 f = &sc->sis_ldata.sis_tx_list[frag]; 1596 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; 1597 bus_dmamap_create(sc->sis_tag, 0, &f->sis_map); 1598 bus_dmamap_load(sc->sis_tag, f->sis_map, 1599 mtod(m, void *), m->m_len, 1600 sis_dma_map_desc_ptr, f, 0); 1601 bus_dmamap_sync(sc->sis_tag, 1602 f->sis_map, BUS_DMASYNC_PREREAD); 1603 if (cnt != 0) 1604 f->sis_ctl |= SIS_CMDSTS_OWN; 1605 cur = frag; 1606 SIS_INC(frag, SIS_TX_LIST_CNT); 1607 cnt++; 1608 } 1609 } 1610 1611 if (m != NULL) 1612 return(ENOBUFS); 1613 1614 sc->sis_ldata.sis_tx_list[cur].sis_mbuf = m_head; 1615 sc->sis_ldata.sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1616 sc->sis_ldata.sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1617 sc->sis_cdata.sis_tx_cnt += cnt; 1618 *txidx = frag; 1619 1620 return(0); 1621} 1622 1623/* 1624 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1625 * to the mbuf data regions directly in the transmit lists. We also save a 1626 * copy of the pointers since the transmit list fragment pointers are 1627 * physical addresses. 1628 */ 1629 1630static void sis_start(ifp) 1631 struct ifnet *ifp; 1632{ 1633 struct sis_softc *sc; 1634 struct mbuf *m_head = NULL; 1635 u_int32_t idx; 1636 1637 sc = ifp->if_softc; 1638 SIS_LOCK(sc); 1639 1640 if (!sc->sis_link) { 1641 SIS_UNLOCK(sc); 1642 return; 1643 } 1644 1645 idx = sc->sis_cdata.sis_tx_prod; 1646 1647 if (ifp->if_flags & IFF_OACTIVE) { 1648 SIS_UNLOCK(sc); 1649 return; 1650 } 1651 1652 while(sc->sis_ldata.sis_tx_list[idx].sis_mbuf == NULL) { 1653 IF_DEQUEUE(&ifp->if_snd, m_head); 1654 if (m_head == NULL) 1655 break; 1656 1657 if (sis_encap(sc, m_head, &idx)) { 1658 IF_PREPEND(&ifp->if_snd, m_head); 1659 ifp->if_flags |= IFF_OACTIVE; 1660 break; 1661 } 1662 1663 /* 1664 * If there's a BPF listener, bounce a copy of this frame 1665 * to him. 1666 */ 1667 if (ifp->if_bpf) 1668 bpf_mtap(ifp, m_head); 1669 1670 } 1671 1672 /* Transmit */ 1673 sc->sis_cdata.sis_tx_prod = idx; 1674 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 1675 1676 /* 1677 * Set a timeout in case the chip goes out to lunch. 1678 */ 1679 ifp->if_timer = 5; 1680 1681 SIS_UNLOCK(sc); 1682 1683 return; 1684} 1685 1686static void sis_init(xsc) 1687 void *xsc; 1688{ 1689 struct sis_softc *sc = xsc; 1690 struct ifnet *ifp = &sc->arpcom.ac_if; 1691 struct mii_data *mii; 1692 1693 SIS_LOCK(sc); 1694 1695 /* 1696 * Cancel pending I/O and free all RX/TX buffers. 1697 */ 1698 sis_stop(sc); 1699 1700 mii = device_get_softc(sc->sis_miibus); 1701 1702 /* Set MAC address */ 1703 if (sc->sis_type == SIS_TYPE_83815) { 1704 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 1705 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1706 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1707 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 1708 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1709 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1710 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 1711 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1712 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1713 } else { 1714 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 1715 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1716 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1717 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 1718 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1719 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1720 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 1721 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1722 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1723 } 1724 1725 /* Init circular RX list. */ 1726 if (sis_list_rx_init(sc) == ENOBUFS) { 1727 printf("sis%d: initialization failed: no " 1728 "memory for rx buffers\n", sc->sis_unit); 1729 sis_stop(sc); 1730 SIS_UNLOCK(sc); 1731 return; 1732 } 1733 1734 /* 1735 * Init tx descriptors. 1736 */ 1737 sis_list_tx_init(sc); 1738 1739 /* 1740 * For the NatSemi chip, we have to explicitly enable the 1741 * reception of ARP frames, as well as turn on the 'perfect 1742 * match' filter where we store the station address, otherwise 1743 * we won't receive unicasts meant for this host. 1744 */ 1745 if (sc->sis_type == SIS_TYPE_83815) { 1746 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 1747 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 1748 } 1749 1750 /* If we want promiscuous mode, set the allframes bit. */ 1751 if (ifp->if_flags & IFF_PROMISC) { 1752 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1753 } else { 1754 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1755 } 1756 1757 /* 1758 * Set the capture broadcast bit to capture broadcast frames. 1759 */ 1760 if (ifp->if_flags & IFF_BROADCAST) { 1761 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1762 } else { 1763 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1764 } 1765 1766 /* 1767 * Load the multicast filter. 1768 */ 1769 if (sc->sis_type == SIS_TYPE_83815) 1770 sis_setmulti_ns(sc); 1771 else 1772 sis_setmulti_sis(sc); 1773 1774 /* Turn the receive filter on */ 1775 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 1776 1777 /* 1778 * Load the address of the RX and TX lists. 1779 */ 1780 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_cdata.sis_rx_paddr); 1781 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_cdata.sis_tx_paddr); 1782 1783 /* Set RX configuration */ 1784 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG); 1785 1786 /* Accept Long Packets for VLAN support */ 1787 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 1788 1789 /* Set TX configuration */ 1790 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 1791 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 1792 } else { 1793 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 1794 } 1795 1796 /* Set full/half duplex mode. */ 1797 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1798 SIS_SETBIT(sc, SIS_TX_CFG, 1799 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 1800 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 1801 } else { 1802 SIS_CLRBIT(sc, SIS_TX_CFG, 1803 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 1804 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 1805 } 1806 1807 /* 1808 * Enable interrupts. 1809 */ 1810 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 1811#ifdef DEVICE_POLLING 1812 /* 1813 * ... only enable interrupts if we are not polling, make sure 1814 * they are off otherwise. 1815 */ 1816 if (ifp->if_ipending & IFF_POLLING) 1817 CSR_WRITE_4(sc, SIS_IER, 0); 1818 else 1819#endif /* DEVICE_POLLING */ 1820 CSR_WRITE_4(sc, SIS_IER, 1); 1821 1822 /* Enable receiver and transmitter. */ 1823 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 1824 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1825 1826#ifdef notdef 1827 mii_mediachg(mii); 1828#endif 1829 1830 /* 1831 * Page 75 of the DP83815 manual recommends the 1832 * following register settings "for optimum 1833 * performance." Note however that at least three 1834 * of the registers are listed as "reserved" in 1835 * the register map, so who knows what they do. 1836 */ 1837 if (sc->sis_type == SIS_TYPE_83815) { 1838 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 1839 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 1840 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 1841 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 1842 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 1843 } 1844 1845 ifp->if_flags |= IFF_RUNNING; 1846 ifp->if_flags &= ~IFF_OACTIVE; 1847 1848 sc->sis_stat_ch = timeout(sis_tick, sc, hz); 1849 1850 SIS_UNLOCK(sc); 1851 1852 return; 1853} 1854 1855/* 1856 * Set media options. 1857 */ 1858static int sis_ifmedia_upd(ifp) 1859 struct ifnet *ifp; 1860{ 1861 struct sis_softc *sc; 1862 struct mii_data *mii; 1863 1864 sc = ifp->if_softc; 1865 1866 mii = device_get_softc(sc->sis_miibus); 1867 sc->sis_link = 0; 1868 if (mii->mii_instance) { 1869 struct mii_softc *miisc; 1870 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1871 mii_phy_reset(miisc); 1872 } 1873 mii_mediachg(mii); 1874 1875 return(0); 1876} 1877 1878/* 1879 * Report current media status. 1880 */ 1881static void sis_ifmedia_sts(ifp, ifmr) 1882 struct ifnet *ifp; 1883 struct ifmediareq *ifmr; 1884{ 1885 struct sis_softc *sc; 1886 struct mii_data *mii; 1887 1888 sc = ifp->if_softc; 1889 1890 mii = device_get_softc(sc->sis_miibus); 1891 mii_pollstat(mii); 1892 ifmr->ifm_active = mii->mii_media_active; 1893 ifmr->ifm_status = mii->mii_media_status; 1894 1895 return; 1896} 1897 1898static int sis_ioctl(ifp, command, data) 1899 struct ifnet *ifp; 1900 u_long command; 1901 caddr_t data; 1902{ 1903 struct sis_softc *sc = ifp->if_softc; 1904 struct ifreq *ifr = (struct ifreq *) data; 1905 struct mii_data *mii; 1906 int error = 0; 1907 1908 switch(command) { 1909 case SIOCSIFADDR: 1910 case SIOCGIFADDR: 1911 case SIOCSIFMTU: 1912 error = ether_ioctl(ifp, command, data); 1913 break; 1914 case SIOCSIFFLAGS: 1915 if (ifp->if_flags & IFF_UP) { 1916 sis_init(sc); 1917 } else { 1918 if (ifp->if_flags & IFF_RUNNING) 1919 sis_stop(sc); 1920 } 1921 error = 0; 1922 break; 1923 case SIOCADDMULTI: 1924 case SIOCDELMULTI: 1925 SIS_LOCK(sc); 1926 if (sc->sis_type == SIS_TYPE_83815) 1927 sis_setmulti_ns(sc); 1928 else 1929 sis_setmulti_sis(sc); 1930 SIS_UNLOCK(sc); 1931 error = 0; 1932 break; 1933 case SIOCGIFMEDIA: 1934 case SIOCSIFMEDIA: 1935 mii = device_get_softc(sc->sis_miibus); 1936 SIS_LOCK(sc); 1937 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1938 SIS_UNLOCK(sc); 1939 break; 1940 default: 1941 error = EINVAL; 1942 break; 1943 } 1944 1945 return(error); 1946} 1947 1948static void sis_watchdog(ifp) 1949 struct ifnet *ifp; 1950{ 1951 struct sis_softc *sc; 1952 1953 sc = ifp->if_softc; 1954 1955 SIS_LOCK(sc); 1956 1957 ifp->if_oerrors++; 1958 printf("sis%d: watchdog timeout\n", sc->sis_unit); 1959 1960 sis_stop(sc); 1961 sis_reset(sc); 1962 sis_init(sc); 1963 1964 if (ifp->if_snd.ifq_head != NULL) 1965 sis_start(ifp); 1966 1967 SIS_UNLOCK(sc); 1968 1969 return; 1970} 1971 1972/* 1973 * Stop the adapter and free any mbufs allocated to the 1974 * RX and TX lists. 1975 */ 1976static void sis_stop(sc) 1977 struct sis_softc *sc; 1978{ 1979 register int i; 1980 struct ifnet *ifp; 1981 1982 SIS_LOCK(sc); 1983 ifp = &sc->arpcom.ac_if; 1984 ifp->if_timer = 0; 1985 1986 untimeout(sis_tick, sc, sc->sis_stat_ch); 1987 1988 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1989#ifdef DEVICE_POLLING 1990 ether_poll_deregister(ifp); 1991#endif 1992 CSR_WRITE_4(sc, SIS_IER, 0); 1993 CSR_WRITE_4(sc, SIS_IMR, 0); 1994 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 1995 DELAY(1000); 1996 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 1997 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 1998 1999 sc->sis_link = 0; 2000 2001 /* 2002 * Free data in the RX lists. 2003 */ 2004 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 2005 if (sc->sis_ldata.sis_rx_list[i].sis_mbuf != NULL) { 2006 bus_dmamap_unload(sc->sis_tag, 2007 sc->sis_ldata.sis_rx_list[i].sis_map); 2008 bus_dmamap_destroy(sc->sis_tag, 2009 sc->sis_ldata.sis_rx_list[i].sis_map); 2010 m_freem(sc->sis_ldata.sis_rx_list[i].sis_mbuf); 2011 sc->sis_ldata.sis_rx_list[i].sis_mbuf = NULL; 2012 } 2013 } 2014 bzero(sc->sis_ldata.sis_rx_list, 2015 sizeof(sc->sis_ldata.sis_rx_list)); 2016 2017 /* 2018 * Free the TX list buffers. 2019 */ 2020 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 2021 if (sc->sis_ldata.sis_tx_list[i].sis_mbuf != NULL) { 2022 bus_dmamap_unload(sc->sis_tag, 2023 sc->sis_ldata.sis_tx_list[i].sis_map); 2024 bus_dmamap_destroy(sc->sis_tag, 2025 sc->sis_ldata.sis_tx_list[i].sis_map); 2026 m_freem(sc->sis_ldata.sis_tx_list[i].sis_mbuf); 2027 sc->sis_ldata.sis_tx_list[i].sis_mbuf = NULL; 2028 } 2029 } 2030 2031 bzero(sc->sis_ldata.sis_tx_list, 2032 sizeof(sc->sis_ldata.sis_tx_list)); 2033 2034 SIS_UNLOCK(sc); 2035 2036 return; 2037} 2038 2039/* 2040 * Stop all chip I/O so that the kernel's probe routines don't 2041 * get confused by errant DMAs when rebooting. 2042 */ 2043static void sis_shutdown(dev) 2044 device_t dev; 2045{ 2046 struct sis_softc *sc; 2047 2048 sc = device_get_softc(dev); 2049 SIS_LOCK(sc); 2050 sis_reset(sc); 2051 sis_stop(sc); 2052 SIS_UNLOCK(sc); 2053 2054 return; 2055} 2056