if_sis.c revision 87390
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_sis.c 87390 2001-12-05 09:34:28Z jhay $ 33 */ 34 35/* 36 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 37 * available from http://www.sis.com.tw. 38 * 39 * This driver also supports the NatSemi DP83815. Datasheets are 40 * available from http://www.national.com. 41 * 42 * Written by Bill Paul <wpaul@ee.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47/* 48 * The SiS 900 is a fairly simple chip. It uses bus master DMA with 49 * simple TX and RX descriptors of 3 longwords in size. The receiver 50 * has a single perfect filter entry for the station address and a 51 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 52 * transceiver while the 7016 requires an external transceiver chip. 53 * Both chips offer the standard bit-bang MII interface as well as 54 * an enchanced PHY interface which simplifies accessing MII registers. 55 * 56 * The only downside to this chipset is that RX descriptors must be 57 * longword aligned. 58 */ 59 60#include <sys/param.h> 61#include <sys/systm.h> 62#include <sys/sockio.h> 63#include <sys/mbuf.h> 64#include <sys/malloc.h> 65#include <sys/kernel.h> 66#include <sys/socket.h> 67#include <sys/sysctl.h> 68 69#include <net/if.h> 70#include <net/if_arp.h> 71#include <net/ethernet.h> 72#include <net/if_dl.h> 73#include <net/if_media.h> 74#include <net/if_types.h> 75#include <net/if_vlan_var.h> 76 77#include <net/bpf.h> 78 79#include <machine/bus_pio.h> 80#include <machine/bus_memio.h> 81#include <machine/bus.h> 82#include <machine/resource.h> 83#include <sys/bus.h> 84#include <sys/rman.h> 85 86#include <dev/mii/mii.h> 87#include <dev/mii/miivar.h> 88 89#include <pci/pcireg.h> 90#include <pci/pcivar.h> 91 92#define SIS_USEIOSPACE 93 94#include <pci/if_sisreg.h> 95 96MODULE_DEPEND(sis, miibus, 1, 1, 1); 97 98/* "controller miibus0" required. See GENERIC if you get errors here. */ 99#include "miibus_if.h" 100 101#ifndef lint 102static const char rcsid[] = 103 "$FreeBSD: head/sys/pci/if_sis.c 87390 2001-12-05 09:34:28Z jhay $"; 104#endif 105 106/* 107 * Various supported device vendors/types and their names. 108 */ 109static struct sis_type sis_devs[] = { 110 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 111 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 112 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP83815 10/100BaseTX" }, 113 { 0, 0, NULL } 114}; 115 116static int sis_probe __P((device_t)); 117static int sis_attach __P((device_t)); 118static int sis_detach __P((device_t)); 119 120static int sis_newbuf __P((struct sis_softc *, 121 struct sis_desc *, 122 struct mbuf *)); 123static int sis_encap __P((struct sis_softc *, 124 struct mbuf *, u_int32_t *)); 125static void sis_rxeof __P((struct sis_softc *)); 126static void sis_rxeoc __P((struct sis_softc *)); 127static void sis_txeof __P((struct sis_softc *)); 128static void sis_intr __P((void *)); 129static void sis_tick __P((void *)); 130static void sis_start __P((struct ifnet *)); 131static int sis_ioctl __P((struct ifnet *, u_long, caddr_t)); 132static void sis_init __P((void *)); 133static void sis_stop __P((struct sis_softc *)); 134static void sis_watchdog __P((struct ifnet *)); 135static void sis_shutdown __P((device_t)); 136static int sis_ifmedia_upd __P((struct ifnet *)); 137static void sis_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 138 139static u_int16_t sis_reverse __P((u_int16_t)); 140static void sis_delay __P((struct sis_softc *)); 141static void sis_eeprom_idle __P((struct sis_softc *)); 142static void sis_eeprom_putbyte __P((struct sis_softc *, int)); 143static void sis_eeprom_getword __P((struct sis_softc *, int, u_int16_t *)); 144static void sis_read_eeprom __P((struct sis_softc *, caddr_t, int, 145 int, int)); 146#ifdef __i386__ 147static void sis_read_cmos __P((struct sis_softc *, device_t, caddr_t, 148 int, int)); 149static device_t sis_find_bridge __P((device_t)); 150#endif 151 152static int sis_miibus_readreg __P((device_t, int, int)); 153static int sis_miibus_writereg __P((device_t, int, int, int)); 154static void sis_miibus_statchg __P((device_t)); 155 156static void sis_setmulti_sis __P((struct sis_softc *)); 157static void sis_setmulti_ns __P((struct sis_softc *)); 158static u_int32_t sis_crc __P((struct sis_softc *, caddr_t)); 159static void sis_reset __P((struct sis_softc *)); 160static int sis_list_rx_init __P((struct sis_softc *)); 161static int sis_list_tx_init __P((struct sis_softc *)); 162 163static void sis_dma_map_desc_ptr __P((void *, bus_dma_segment_t *, 164 int, int)); 165static void sis_dma_map_desc_next __P((void *, bus_dma_segment_t *, 166 int, int)); 167static void sis_dma_map_ring __P((void *, bus_dma_segment_t *, 168 int, int)); 169#ifdef SIS_USEIOSPACE 170#define SIS_RES SYS_RES_IOPORT 171#define SIS_RID SIS_PCI_LOIO 172#else 173#define SIS_RES SYS_RES_MEMORY 174#define SIS_RID SIS_PCI_LOMEM 175#endif 176 177static device_method_t sis_methods[] = { 178 /* Device interface */ 179 DEVMETHOD(device_probe, sis_probe), 180 DEVMETHOD(device_attach, sis_attach), 181 DEVMETHOD(device_detach, sis_detach), 182 DEVMETHOD(device_shutdown, sis_shutdown), 183 184 /* bus interface */ 185 DEVMETHOD(bus_print_child, bus_generic_print_child), 186 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 187 188 /* MII interface */ 189 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 190 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 191 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 192 193 { 0, 0 } 194}; 195 196static driver_t sis_driver = { 197 "sis", 198 sis_methods, 199 sizeof(struct sis_softc) 200}; 201 202static devclass_t sis_devclass; 203 204#ifdef __i386__ 205static int sis_quick=1; 206SYSCTL_INT(_hw, OID_AUTO, sis_quick, CTLFLAG_RW, 207 &sis_quick,0,"do not mdevget in sis driver"); 208#endif 209 210DRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, 0, 0); 211DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 212 213#define SIS_SETBIT(sc, reg, x) \ 214 CSR_WRITE_4(sc, reg, \ 215 CSR_READ_4(sc, reg) | (x)) 216 217#define SIS_CLRBIT(sc, reg, x) \ 218 CSR_WRITE_4(sc, reg, \ 219 CSR_READ_4(sc, reg) & ~(x)) 220 221#define SIO_SET(x) \ 222 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 223 224#define SIO_CLR(x) \ 225 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 226 227static void 228sis_dma_map_desc_next(arg, segs, nseg, error) 229 void *arg; 230 bus_dma_segment_t *segs; 231 int nseg, error; 232{ 233 struct sis_desc *r; 234 235 r = arg; 236 r->sis_next = segs->ds_addr; 237 238 return; 239} 240 241static void 242sis_dma_map_desc_ptr(arg, segs, nseg, error) 243 void *arg; 244 bus_dma_segment_t *segs; 245 int nseg, error; 246{ 247 struct sis_desc *r; 248 249 r = arg; 250 r->sis_ptr = segs->ds_addr; 251 252 return; 253} 254 255static void 256sis_dma_map_ring(arg, segs, nseg, error) 257 void *arg; 258 bus_dma_segment_t *segs; 259 int nseg, error; 260{ 261 u_int32_t *p; 262 263 p = arg; 264 *p = segs->ds_addr; 265 266 return; 267} 268 269/* 270 * Routine to reverse the bits in a word. Stolen almost 271 * verbatim from /usr/games/fortune. 272 */ 273static u_int16_t sis_reverse(n) 274 u_int16_t n; 275{ 276 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 277 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 278 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 279 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 280 281 return(n); 282} 283 284static void sis_delay(sc) 285 struct sis_softc *sc; 286{ 287 int idx; 288 289 for (idx = (300 / 33) + 1; idx > 0; idx--) 290 CSR_READ_4(sc, SIS_CSR); 291 292 return; 293} 294 295static void sis_eeprom_idle(sc) 296 struct sis_softc *sc; 297{ 298 register int i; 299 300 SIO_SET(SIS_EECTL_CSEL); 301 sis_delay(sc); 302 SIO_SET(SIS_EECTL_CLK); 303 sis_delay(sc); 304 305 for (i = 0; i < 25; i++) { 306 SIO_CLR(SIS_EECTL_CLK); 307 sis_delay(sc); 308 SIO_SET(SIS_EECTL_CLK); 309 sis_delay(sc); 310 } 311 312 SIO_CLR(SIS_EECTL_CLK); 313 sis_delay(sc); 314 SIO_CLR(SIS_EECTL_CSEL); 315 sis_delay(sc); 316 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 317 318 return; 319} 320 321/* 322 * Send a read command and address to the EEPROM, check for ACK. 323 */ 324static void sis_eeprom_putbyte(sc, addr) 325 struct sis_softc *sc; 326 int addr; 327{ 328 register int d, i; 329 330 d = addr | SIS_EECMD_READ; 331 332 /* 333 * Feed in each bit and stobe the clock. 334 */ 335 for (i = 0x400; i; i >>= 1) { 336 if (d & i) { 337 SIO_SET(SIS_EECTL_DIN); 338 } else { 339 SIO_CLR(SIS_EECTL_DIN); 340 } 341 sis_delay(sc); 342 SIO_SET(SIS_EECTL_CLK); 343 sis_delay(sc); 344 SIO_CLR(SIS_EECTL_CLK); 345 sis_delay(sc); 346 } 347 348 return; 349} 350 351/* 352 * Read a word of data stored in the EEPROM at address 'addr.' 353 */ 354static void sis_eeprom_getword(sc, addr, dest) 355 struct sis_softc *sc; 356 int addr; 357 u_int16_t *dest; 358{ 359 register int i; 360 u_int16_t word = 0; 361 362 /* Force EEPROM to idle state. */ 363 sis_eeprom_idle(sc); 364 365 /* Enter EEPROM access mode. */ 366 sis_delay(sc); 367 SIO_CLR(SIS_EECTL_CLK); 368 sis_delay(sc); 369 SIO_SET(SIS_EECTL_CSEL); 370 sis_delay(sc); 371 372 /* 373 * Send address of word we want to read. 374 */ 375 sis_eeprom_putbyte(sc, addr); 376 377 /* 378 * Start reading bits from EEPROM. 379 */ 380 for (i = 0x8000; i; i >>= 1) { 381 SIO_SET(SIS_EECTL_CLK); 382 sis_delay(sc); 383 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 384 word |= i; 385 sis_delay(sc); 386 SIO_CLR(SIS_EECTL_CLK); 387 sis_delay(sc); 388 } 389 390 /* Turn off EEPROM access mode. */ 391 sis_eeprom_idle(sc); 392 393 *dest = word; 394 395 return; 396} 397 398/* 399 * Read a sequence of words from the EEPROM. 400 */ 401static void sis_read_eeprom(sc, dest, off, cnt, swap) 402 struct sis_softc *sc; 403 caddr_t dest; 404 int off; 405 int cnt; 406 int swap; 407{ 408 int i; 409 u_int16_t word = 0, *ptr; 410 411 for (i = 0; i < cnt; i++) { 412 sis_eeprom_getword(sc, off + i, &word); 413 ptr = (u_int16_t *)(dest + (i * 2)); 414 if (swap) 415 *ptr = ntohs(word); 416 else 417 *ptr = word; 418 } 419 420 return; 421} 422 423#ifdef __i386__ 424static device_t sis_find_bridge(dev) 425 device_t dev; 426{ 427 devclass_t pci_devclass; 428 device_t *pci_devices; 429 int pci_count = 0; 430 device_t *pci_children; 431 int pci_childcount = 0; 432 device_t *busp, *childp; 433 int i, j; 434 435 if ((pci_devclass = devclass_find("pci")) == NULL) 436 return(NULL); 437 438 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 439 440 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 441 pci_childcount = 0; 442 device_get_children(*busp, &pci_children, &pci_childcount); 443 for (j = 0, childp = pci_children; 444 j < pci_childcount; j++, childp++) { 445 if (pci_get_vendor(*childp) == SIS_VENDORID && 446 pci_get_device(*childp) == 0x0008) { 447 free(pci_devices, M_TEMP); 448 free(pci_children, M_TEMP); 449 return(*childp); 450 } 451 } 452 } 453 454 free(pci_devices, M_TEMP); 455 free(pci_children, M_TEMP); 456 return(NULL); 457} 458 459static void sis_read_cmos(sc, dev, dest, off, cnt) 460 struct sis_softc *sc; 461 device_t dev; 462 caddr_t dest; 463 int off; 464 int cnt; 465{ 466 device_t bridge; 467 u_int8_t reg; 468 int i; 469 bus_space_tag_t btag; 470 471 bridge = sis_find_bridge(dev); 472 if (bridge == NULL) 473 return; 474 reg = pci_read_config(bridge, 0x48, 1); 475 pci_write_config(bridge, 0x48, reg|0x40, 1); 476 477 /* XXX */ 478 btag = I386_BUS_SPACE_IO; 479 480 for (i = 0; i < cnt; i++) { 481 bus_space_write_1(btag, 0x0, 0x70, i + off); 482 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 483 } 484 485 pci_write_config(bridge, 0x48, reg & ~0x40, 1); 486 return; 487} 488#endif 489 490static int sis_miibus_readreg(dev, phy, reg) 491 device_t dev; 492 int phy, reg; 493{ 494 struct sis_softc *sc; 495 int i, val = 0; 496 497 sc = device_get_softc(dev); 498 499 if (sc->sis_type == SIS_TYPE_83815) { 500 if (phy != 0) 501 return(0); 502 /* 503 * The NatSemi chip can take a while after 504 * a reset to come ready, during which the BMSR 505 * returns a value of 0. This is *never* supposed 506 * to happen: some of the BMSR bits are meant to 507 * be hardwired in the on position, and this can 508 * confuse the miibus code a bit during the probe 509 * and attach phase. So we make an effort to check 510 * for this condition and wait for it to clear. 511 */ 512 if (!CSR_READ_4(sc, NS_BMSR)) 513 DELAY(1000); 514 val = CSR_READ_4(sc, NS_BMCR + (reg * 4)); 515 return(val); 516 } 517 518 if (sc->sis_type == SIS_TYPE_900 && phy != 0) 519 return(0); 520 521 CSR_WRITE_4(sc, SIS_PHYCTL, (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 522 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 523 524 for (i = 0; i < SIS_TIMEOUT; i++) { 525 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 526 break; 527 } 528 529 if (i == SIS_TIMEOUT) { 530 printf("sis%d: PHY failed to come ready\n", sc->sis_unit); 531 return(0); 532 } 533 534 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 535 536 if (val == 0xFFFF) 537 return(0); 538 539 return(val); 540} 541 542static int sis_miibus_writereg(dev, phy, reg, data) 543 device_t dev; 544 int phy, reg, data; 545{ 546 struct sis_softc *sc; 547 int i; 548 549 sc = device_get_softc(dev); 550 551 if (sc->sis_type == SIS_TYPE_83815) { 552 if (phy != 0) 553 return(0); 554 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 555 return(0); 556 } 557 558 if (sc->sis_type == SIS_TYPE_900 && phy != 0) 559 return(0); 560 561 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 562 (reg << 6) | SIS_PHYOP_WRITE); 563 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 564 565 for (i = 0; i < SIS_TIMEOUT; i++) { 566 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 567 break; 568 } 569 570 if (i == SIS_TIMEOUT) 571 printf("sis%d: PHY failed to come ready\n", sc->sis_unit); 572 573 return(0); 574} 575 576static void sis_miibus_statchg(dev) 577 device_t dev; 578{ 579 struct sis_softc *sc; 580 581 sc = device_get_softc(dev); 582 sis_init(sc); 583 584 return; 585} 586 587static u_int32_t sis_crc(sc, addr) 588 struct sis_softc *sc; 589 caddr_t addr; 590{ 591 u_int32_t crc, carry; 592 int i, j; 593 u_int8_t c; 594 595 /* Compute CRC for the address value. */ 596 crc = 0xFFFFFFFF; /* initial value */ 597 598 for (i = 0; i < 6; i++) { 599 c = *(addr + i); 600 for (j = 0; j < 8; j++) { 601 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 602 crc <<= 1; 603 c >>= 1; 604 if (carry) 605 crc = (crc ^ 0x04c11db6) | carry; 606 } 607 } 608 609 /* 610 * return the filter bit position 611 * 612 * The NatSemi chip has a 512-bit filter, which is 613 * different than the SiS, so we special-case it. 614 */ 615 if (sc->sis_type == SIS_TYPE_83815) 616 return((crc >> 23) & 0x1FF); 617 618 return((crc >> 25) & 0x0000007F); 619} 620 621static void sis_setmulti_ns(sc) 622 struct sis_softc *sc; 623{ 624 struct ifnet *ifp; 625 struct ifmultiaddr *ifma; 626 u_int32_t h = 0, i, filtsave; 627 int bit, index; 628 629 ifp = &sc->arpcom.ac_if; 630 631 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 632 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 633 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 634 return; 635 } 636 637 /* 638 * We have to explicitly enable the multicast hash table 639 * on the NatSemi chip if we want to use it, which we do. 640 */ 641 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 642 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 643 644 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 645 646 /* first, zot all the existing hash bits */ 647 for (i = 0; i < 32; i++) { 648 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 649 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 650 } 651 652 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 653 if (ifma->ifma_addr->sa_family != AF_LINK) 654 continue; 655 h = sis_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 656 index = h >> 3; 657 bit = h & 0x1F; 658 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 659 if (bit > 0xF) 660 bit -= 0x10; 661 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 662 } 663 664 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 665 666 return; 667} 668 669static void sis_setmulti_sis(sc) 670 struct sis_softc *sc; 671{ 672 struct ifnet *ifp; 673 struct ifmultiaddr *ifma; 674 u_int32_t h = 0, i, filtsave; 675 676 ifp = &sc->arpcom.ac_if; 677 678 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 679 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 680 return; 681 } 682 683 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 684 685 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 686 687 /* first, zot all the existing hash bits */ 688 for (i = 0; i < 8; i++) { 689 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + ((i * 16) >> 4)) << 16); 690 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 691 } 692 693 /* now program new ones */ 694 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 695 if (ifma->ifma_addr->sa_family != AF_LINK) 696 continue; 697 h = sis_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 698 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + (h >> 4)) << 16); 699 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << (h & 0xF))); 700 } 701 702 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 703 704 return; 705} 706 707static void sis_reset(sc) 708 struct sis_softc *sc; 709{ 710 register int i; 711 712 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 713 714 for (i = 0; i < SIS_TIMEOUT; i++) { 715 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 716 break; 717 } 718 719 if (i == SIS_TIMEOUT) 720 printf("sis%d: reset never completed\n", sc->sis_unit); 721 722 /* Wait a little while for the chip to get its brains in order. */ 723 DELAY(1000); 724 725 /* 726 * If this is a NetSemi chip, make sure to clear 727 * PME mode. 728 */ 729 if (sc->sis_type == SIS_TYPE_83815) { 730 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 731 CSR_WRITE_4(sc, NS_CLKRUN, 0); 732 } 733 734 return; 735} 736 737/* 738 * Probe for an SiS chip. Check the PCI vendor and device 739 * IDs against our list and return a device name if we find a match. 740 */ 741static int sis_probe(dev) 742 device_t dev; 743{ 744 struct sis_type *t; 745 746 t = sis_devs; 747 748 while(t->sis_name != NULL) { 749 if ((pci_get_vendor(dev) == t->sis_vid) && 750 (pci_get_device(dev) == t->sis_did)) { 751 device_set_desc(dev, t->sis_name); 752 return(0); 753 } 754 t++; 755 } 756 757 return(ENXIO); 758} 759 760/* 761 * Attach the interface. Allocate softc structures, do ifmedia 762 * setup and ethernet/BPF attach. 763 */ 764static int sis_attach(dev) 765 device_t dev; 766{ 767 u_char eaddr[ETHER_ADDR_LEN]; 768 u_int32_t command; 769 struct sis_softc *sc; 770 struct ifnet *ifp; 771 int unit, error = 0, rid; 772 773 sc = device_get_softc(dev); 774 unit = device_get_unit(dev); 775 bzero(sc, sizeof(struct sis_softc)); 776 777 mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 778 SIS_LOCK(sc); 779 780 if (pci_get_device(dev) == SIS_DEVICEID_900) 781 sc->sis_type = SIS_TYPE_900; 782 if (pci_get_device(dev) == SIS_DEVICEID_7016) 783 sc->sis_type = SIS_TYPE_7016; 784 if (pci_get_vendor(dev) == NS_VENDORID) 785 sc->sis_type = SIS_TYPE_83815; 786 787 /* 788 * Handle power management nonsense. 789 */ 790 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 791 u_int32_t iobase, membase, irq; 792 793 /* Save important PCI config data. */ 794 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4); 795 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4); 796 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4); 797 798 /* Reset the power state. */ 799 printf("sis%d: chip is in D%d power mode " 800 "-- setting to D0\n", unit, 801 pci_get_powerstate(dev)); 802 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 803 804 /* Restore PCI config data. */ 805 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4); 806 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4); 807 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4); 808 } 809 810 /* 811 * Map control/status registers. 812 */ 813 pci_enable_busmaster(dev); 814 pci_enable_io(dev, SYS_RES_IOPORT); 815 pci_enable_io(dev, SYS_RES_MEMORY); 816 command = pci_read_config(dev, PCIR_COMMAND, 4); 817 818#ifdef SIS_USEIOSPACE 819 if (!(command & PCIM_CMD_PORTEN)) { 820 printf("sis%d: failed to enable I/O ports!\n", unit); 821 error = ENXIO;; 822 goto fail; 823 } 824#else 825 if (!(command & PCIM_CMD_MEMEN)) { 826 printf("sis%d: failed to enable memory mapping!\n", unit); 827 error = ENXIO;; 828 goto fail; 829 } 830#endif 831 832 rid = SIS_RID; 833 sc->sis_res = bus_alloc_resource(dev, SIS_RES, &rid, 834 0, ~0, 1, RF_ACTIVE); 835 836 if (sc->sis_res == NULL) { 837 printf("sis%d: couldn't map ports/memory\n", unit); 838 error = ENXIO; 839 goto fail; 840 } 841 842 sc->sis_btag = rman_get_bustag(sc->sis_res); 843 sc->sis_bhandle = rman_get_bushandle(sc->sis_res); 844 845 /* Allocate interrupt */ 846 rid = 0; 847 sc->sis_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 848 RF_SHAREABLE | RF_ACTIVE); 849 850 if (sc->sis_irq == NULL) { 851 printf("sis%d: couldn't map interrupt\n", unit); 852 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 853 error = ENXIO; 854 goto fail; 855 } 856 857 error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET, 858 sis_intr, sc, &sc->sis_intrhand); 859 860 if (error) { 861 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 862 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 863 printf("sis%d: couldn't set up irq\n", unit); 864 goto fail; 865 } 866 867 /* Reset the adapter. */ 868 sis_reset(sc); 869 870 /* 871 * Get station address from the EEPROM. 872 */ 873 switch (pci_get_vendor(dev)) { 874 case NS_VENDORID: 875 /* 876 * Reading the MAC address out of the EEPROM on 877 * the NatSemi chip takes a bit more work than 878 * you'd expect. The address spans 4 16-bit words, 879 * with the first word containing only a single bit. 880 * You have to shift everything over one bit to 881 * get it aligned properly. Also, the bits are 882 * stored backwards (the LSB is really the MSB, 883 * and so on) so you have to reverse them in order 884 * to get the MAC address into the form we want. 885 * Why? Who the hell knows. 886 */ 887 { 888 u_int16_t tmp[4]; 889 890 sis_read_eeprom(sc, (caddr_t)&tmp, 891 NS_EE_NODEADDR, 4, 0); 892 893 /* Shift everything over one bit. */ 894 tmp[3] = tmp[3] >> 1; 895 tmp[3] |= tmp[2] << 15; 896 tmp[2] = tmp[2] >> 1; 897 tmp[2] |= tmp[1] << 15; 898 tmp[1] = tmp[1] >> 1; 899 tmp[1] |= tmp[0] << 15; 900 901 /* Now reverse all the bits. */ 902 tmp[3] = sis_reverse(tmp[3]); 903 tmp[2] = sis_reverse(tmp[2]); 904 tmp[1] = sis_reverse(tmp[1]); 905 906 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); 907 } 908 break; 909 case SIS_VENDORID: 910 default: 911#ifdef __i386__ 912 /* 913 * If this is a SiS 630E chipset with an embedded 914 * SiS 900 controller, we have to read the MAC address 915 * from the APC CMOS RAM. Our method for doing this 916 * is very ugly since we have to reach out and grab 917 * ahold of hardware for which we cannot properly 918 * allocate resources. This code is only compiled on 919 * the i386 architecture since the SiS 630E chipset 920 * is for x86 motherboards only. Note that there are 921 * a lot of magic numbers in this hack. These are 922 * taken from SiS's Linux driver. I'd like to replace 923 * them with proper symbolic definitions, but that 924 * requires some datasheets that I don't have access 925 * to at the moment. 926 */ 927 command = pci_read_config(dev, PCIR_REVID, 1); 928 if (command == SIS_REV_630S || 929 command == SIS_REV_630E || 930 command == SIS_REV_630EA1) 931 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 932 else 933#endif 934 sis_read_eeprom(sc, (caddr_t)&eaddr, 935 SIS_EE_NODEADDR, 3, 0); 936 break; 937 } 938 939 /* 940 * A SiS chip was detected. Inform the world. 941 */ 942 printf("sis%d: Ethernet address: %6D\n", unit, eaddr, ":"); 943 944 sc->sis_unit = unit; 945 callout_handle_init(&sc->sis_stat_ch); 946 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 947 948 /* 949 * Allocate the parent bus DMA tag appropriate for PCI. 950 */ 951#define SIS_NSEG_NEW 32 952 error = bus_dma_tag_create(NULL, /* parent */ 953 1, 0, /* alignment, boundary */ 954 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 955 BUS_SPACE_MAXADDR, /* highaddr */ 956 NULL, NULL, /* filter, filterarg */ 957 MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */ 958 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 959 BUS_DMA_ALLOCNOW, /* flags */ 960 &sc->sis_parent_tag); 961 962 /* 963 * Now allocate a tag for the DMA descriptor lists. 964 * All of our lists are allocated as a contiguous block 965 * of memory. 966 */ 967 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 968 1, 0, /* alignment, boundary */ 969 BUS_SPACE_MAXADDR, /* lowaddr */ 970 BUS_SPACE_MAXADDR, /* highaddr */ 971 NULL, NULL, /* filter, filterarg */ 972 SIS_RX_LIST_SZ, 1, /* maxsize,nsegments */ 973 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 974 0, /* flags */ 975 &sc->sis_ldata.sis_rx_tag); 976 977 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 978 1, 0, /* alignment, boundary */ 979 BUS_SPACE_MAXADDR, /* lowaddr */ 980 BUS_SPACE_MAXADDR, /* highaddr */ 981 NULL, NULL, /* filter, filterarg */ 982 SIS_TX_LIST_SZ, 1, /* maxsize,nsegments */ 983 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 984 0, /* flags */ 985 &sc->sis_ldata.sis_tx_tag); 986 987 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 988 1, 0, /* alignment, boundary */ 989 BUS_SPACE_MAXADDR, /* lowaddr */ 990 BUS_SPACE_MAXADDR, /* highaddr */ 991 NULL, NULL, /* filter, filterarg */ 992 SIS_TX_LIST_SZ, 1, /* maxsize,nsegments */ 993 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 994 0, /* flags */ 995 &sc->sis_tag); 996 997 /* 998 * Now allocate a chunk of DMA-able memory based on the 999 * tag we just created. 1000 */ 1001 error = bus_dmamem_alloc(sc->sis_ldata.sis_tx_tag, 1002 (void **)&sc->sis_ldata.sis_tx_list, BUS_DMA_NOWAIT, 1003 &sc->sis_ldata.sis_tx_dmamap); 1004 1005 if (error) { 1006 printf("sis%d: no memory for list buffers!\n", unit); 1007 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1008 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1009 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1010 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1011 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1012 error = ENXIO; 1013 goto fail; 1014 } 1015 1016 error = bus_dmamem_alloc(sc->sis_ldata.sis_rx_tag, 1017 (void **)&sc->sis_ldata.sis_rx_list, BUS_DMA_NOWAIT, 1018 &sc->sis_ldata.sis_rx_dmamap); 1019 1020 if (error) { 1021 printf("sis%d: no memory for list buffers!\n", unit); 1022 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1023 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1024 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1025 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1026 sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 1027 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1028 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1029 error = ENXIO; 1030 goto fail; 1031 } 1032 1033 1034 bzero(sc->sis_ldata.sis_tx_list, SIS_TX_LIST_SZ); 1035 bzero(sc->sis_ldata.sis_rx_list, SIS_RX_LIST_SZ); 1036 1037 /* 1038 * Obtain the physical addresses of the RX and TX 1039 * rings which we'll need later in the init routine. 1040 */ 1041 bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1042 sc->sis_ldata.sis_tx_dmamap, &(sc->sis_ldata.sis_tx_list[0]), 1043 sizeof(struct sis_desc), sis_dma_map_ring, 1044 &sc->sis_cdata.sis_tx_paddr, 0); 1045 bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1046 sc->sis_ldata.sis_rx_dmamap, &(sc->sis_ldata.sis_rx_list[0]), 1047 sizeof(struct sis_desc), sis_dma_map_ring, 1048 &sc->sis_cdata.sis_rx_paddr, 0); 1049 1050 ifp = &sc->arpcom.ac_if; 1051 ifp->if_softc = sc; 1052 ifp->if_unit = unit; 1053 ifp->if_name = "sis"; 1054 ifp->if_mtu = ETHERMTU; 1055 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1056 ifp->if_ioctl = sis_ioctl; 1057 ifp->if_output = ether_output; 1058 ifp->if_start = sis_start; 1059 ifp->if_watchdog = sis_watchdog; 1060 ifp->if_init = sis_init; 1061 ifp->if_baudrate = 10000000; 1062 ifp->if_snd.ifq_maxlen = SIS_TX_LIST_CNT - 1; 1063 1064 /* 1065 * Do MII setup. 1066 */ 1067 if (mii_phy_probe(dev, &sc->sis_miibus, 1068 sis_ifmedia_upd, sis_ifmedia_sts)) { 1069 printf("sis%d: MII without any PHY!\n", sc->sis_unit); 1070 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1071 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1072 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1073 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1074 sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap); 1075 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1076 sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 1077 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1078 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1079 error = ENXIO; 1080 goto fail; 1081 } 1082 1083 /* 1084 * Call MI attach routine. 1085 */ 1086 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1087 1088 /* 1089 * Tell the upper layer(s) we support long frames. 1090 */ 1091 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1092 1093 callout_handle_init(&sc->sis_stat_ch); 1094 SIS_UNLOCK(sc); 1095 return(0); 1096 1097fail: 1098 SIS_UNLOCK(sc); 1099 mtx_destroy(&sc->sis_mtx); 1100 return(error); 1101} 1102 1103static int sis_detach(dev) 1104 device_t dev; 1105{ 1106 struct sis_softc *sc; 1107 struct ifnet *ifp; 1108 1109 1110 sc = device_get_softc(dev); 1111 SIS_LOCK(sc); 1112 ifp = &sc->arpcom.ac_if; 1113 1114 sis_reset(sc); 1115 sis_stop(sc); 1116 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1117 1118 bus_generic_detach(dev); 1119 device_delete_child(dev, sc->sis_miibus); 1120 1121 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1122 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1123 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1124 1125 bus_dmamap_unload(sc->sis_ldata.sis_rx_tag, 1126 sc->sis_ldata.sis_rx_dmamap); 1127 bus_dmamap_unload(sc->sis_ldata.sis_tx_tag, 1128 sc->sis_ldata.sis_tx_dmamap); 1129 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1130 sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap); 1131 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1132 sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 1133 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1134 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1135 bus_dma_tag_destroy(sc->sis_parent_tag); 1136 1137 SIS_UNLOCK(sc); 1138 mtx_destroy(&sc->sis_mtx); 1139 1140 return(0); 1141} 1142 1143/* 1144 * Initialize the transmit descriptors. 1145 */ 1146static int sis_list_tx_init(sc) 1147 struct sis_softc *sc; 1148{ 1149 struct sis_list_data *ld; 1150 struct sis_ring_data *cd; 1151 int i, nexti; 1152 1153 cd = &sc->sis_cdata; 1154 ld = &sc->sis_ldata; 1155 1156 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1157 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1; 1158 ld->sis_tx_list[i].sis_nextdesc = 1159 &ld->sis_tx_list[nexti]; 1160 bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1161 sc->sis_ldata.sis_tx_dmamap, 1162 &ld->sis_tx_list[nexti], sizeof(struct sis_desc), 1163 sis_dma_map_desc_next, &ld->sis_tx_list[i], 0); 1164 ld->sis_tx_list[i].sis_mbuf = NULL; 1165 ld->sis_tx_list[i].sis_ptr = 0; 1166 ld->sis_tx_list[i].sis_ctl = 0; 1167 } 1168 1169 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0; 1170 1171 bus_dmamap_sync(sc->sis_ldata.sis_tx_tag, 1172 sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 1173 1174 return(0); 1175} 1176 1177/* 1178 * Initialize the RX descriptors and allocate mbufs for them. Note that 1179 * we arrange the descriptors in a closed ring, so that the last descriptor 1180 * points back to the first. 1181 */ 1182static int sis_list_rx_init(sc) 1183 struct sis_softc *sc; 1184{ 1185 struct sis_list_data *ld; 1186 struct sis_ring_data *cd; 1187 int i,nexti; 1188 1189 ld = &sc->sis_ldata; 1190 cd = &sc->sis_cdata; 1191 1192 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1193 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS) 1194 return(ENOBUFS); 1195 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1; 1196 ld->sis_rx_list[i].sis_nextdesc = 1197 &ld->sis_rx_list[nexti]; 1198 bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1199 sc->sis_ldata.sis_rx_dmamap, 1200 &ld->sis_rx_list[nexti], 1201 sizeof(struct sis_desc), sis_dma_map_desc_next, 1202 &ld->sis_rx_list[i], 0); 1203 } 1204 1205 bus_dmamap_sync(sc->sis_ldata.sis_rx_tag, 1206 sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 1207 1208 cd->sis_rx_prod = 0; 1209 1210 return(0); 1211} 1212 1213/* 1214 * Initialize an RX descriptor and attach an MBUF cluster. 1215 */ 1216static int sis_newbuf(sc, c, m) 1217 struct sis_softc *sc; 1218 struct sis_desc *c; 1219 struct mbuf *m; 1220{ 1221 struct mbuf *m_new = NULL; 1222 1223 if (c == NULL) 1224 return(EINVAL); 1225 1226 if (m == NULL) { 1227 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1228 if (m_new == NULL) 1229 return(ENOBUFS); 1230 1231 MCLGET(m_new, M_DONTWAIT); 1232 if (!(m_new->m_flags & M_EXT)) { 1233 m_freem(m_new); 1234 return(ENOBUFS); 1235 } 1236 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1237 } else { 1238 m_new = m; 1239 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1240 m_new->m_data = m_new->m_ext.ext_buf; 1241 } 1242 1243 m_adj(m_new, sizeof(u_int64_t)); 1244 1245 c->sis_mbuf = m_new; 1246 c->sis_ctl = SIS_RXLEN; 1247 1248 bus_dmamap_create(sc->sis_tag, 0, &c->sis_map); 1249 bus_dmamap_load(sc->sis_tag, c->sis_map, 1250 mtod(m_new, void *), m_new->m_len, 1251 sis_dma_map_desc_ptr, c, 0); 1252 bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREWRITE); 1253 1254 return(0); 1255} 1256 1257/* 1258 * A frame has been uploaded: pass the resulting mbuf chain up to 1259 * the higher level protocols. 1260 */ 1261static void sis_rxeof(sc) 1262 struct sis_softc *sc; 1263{ 1264 struct ether_header *eh; 1265 struct mbuf *m; 1266 struct ifnet *ifp; 1267 struct sis_desc *cur_rx; 1268 int i, total_len = 0; 1269 u_int32_t rxstat; 1270 1271 ifp = &sc->arpcom.ac_if; 1272 i = sc->sis_cdata.sis_rx_prod; 1273 1274 while(SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) { 1275 1276 cur_rx = &sc->sis_ldata.sis_rx_list[i]; 1277 rxstat = cur_rx->sis_rxstat; 1278 bus_dmamap_sync(sc->sis_tag, 1279 cur_rx->sis_map, BUS_DMASYNC_POSTWRITE); 1280 bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map); 1281 bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map); 1282 m = cur_rx->sis_mbuf; 1283 cur_rx->sis_mbuf = NULL; 1284 total_len = SIS_RXBYTES(cur_rx); 1285 SIS_INC(i, SIS_RX_LIST_CNT); 1286 1287 /* 1288 * If an error occurs, update stats, clear the 1289 * status word and leave the mbuf cluster in place: 1290 * it should simply get re-used next time this descriptor 1291 * comes up in the ring. 1292 */ 1293 if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 1294 ifp->if_ierrors++; 1295 if (rxstat & SIS_RXSTAT_COLL) 1296 ifp->if_collisions++; 1297 sis_newbuf(sc, cur_rx, m); 1298 continue; 1299 } 1300 1301 /* No errors; receive the packet. */ 1302#ifdef __i386__ 1303 /* 1304 * On the x86 we do not have alignment problems, so try to 1305 * allocate a new buffer for the receive ring, and pass up 1306 * the one where the packet is already, saving the expensive 1307 * copy done in m_devget(). 1308 * If we are on an architecture with alignment problems, or 1309 * if the allocation fails, then use m_devget and leave the 1310 * existing buffer in the receive ring. 1311 */ 1312 if (sis_quick && sis_newbuf(sc, cur_rx, NULL) == 0) { 1313 m->m_pkthdr.rcvif = ifp; 1314 m->m_pkthdr.len = m->m_len = total_len; 1315 } else 1316#endif 1317 { 1318 struct mbuf *m0; 1319 m0 = m_devget(mtod(m, char *), total_len, 1320 ETHER_ALIGN, ifp, NULL); 1321 sis_newbuf(sc, cur_rx, m); 1322 if (m0 == NULL) { 1323 ifp->if_ierrors++; 1324 continue; 1325 } 1326 m = m0; 1327 } 1328 1329 ifp->if_ipackets++; 1330 eh = mtod(m, struct ether_header *); 1331 1332 /* Remove header from mbuf and pass it on. */ 1333 m_adj(m, sizeof(struct ether_header)); 1334 ether_input(ifp, eh, m); 1335 } 1336 1337 sc->sis_cdata.sis_rx_prod = i; 1338 1339 return; 1340} 1341 1342void sis_rxeoc(sc) 1343 struct sis_softc *sc; 1344{ 1345 sis_rxeof(sc); 1346 sis_init(sc); 1347 return; 1348} 1349 1350/* 1351 * A frame was downloaded to the chip. It's safe for us to clean up 1352 * the list buffers. 1353 */ 1354 1355static void sis_txeof(sc) 1356 struct sis_softc *sc; 1357{ 1358 struct sis_desc *cur_tx = NULL; 1359 struct ifnet *ifp; 1360 u_int32_t idx; 1361 1362 ifp = &sc->arpcom.ac_if; 1363 1364 /* Clear the timeout timer. */ 1365 ifp->if_timer = 0; 1366 1367 /* 1368 * Go through our tx list and free mbufs for those 1369 * frames that have been transmitted. 1370 */ 1371 idx = sc->sis_cdata.sis_tx_cons; 1372 while (idx != sc->sis_cdata.sis_tx_prod) { 1373 cur_tx = &sc->sis_ldata.sis_tx_list[idx]; 1374 1375 if (SIS_OWNDESC(cur_tx)) 1376 break; 1377 1378 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) { 1379 sc->sis_cdata.sis_tx_cnt--; 1380 SIS_INC(idx, SIS_TX_LIST_CNT); 1381 continue; 1382 } 1383 1384 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 1385 ifp->if_oerrors++; 1386 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 1387 ifp->if_collisions++; 1388 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 1389 ifp->if_collisions++; 1390 } 1391 1392 ifp->if_collisions += 1393 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 1394 1395 ifp->if_opackets++; 1396 if (cur_tx->sis_mbuf != NULL) { 1397 m_freem(cur_tx->sis_mbuf); 1398 cur_tx->sis_mbuf = NULL; 1399 bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map); 1400 bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map); 1401 } 1402 1403 sc->sis_cdata.sis_tx_cnt--; 1404 SIS_INC(idx, SIS_TX_LIST_CNT); 1405 ifp->if_timer = 0; 1406 } 1407 1408 sc->sis_cdata.sis_tx_cons = idx; 1409 1410 if (cur_tx != NULL) 1411 ifp->if_flags &= ~IFF_OACTIVE; 1412 1413 return; 1414} 1415 1416static void sis_tick(xsc) 1417 void *xsc; 1418{ 1419 struct sis_softc *sc; 1420 struct mii_data *mii; 1421 struct ifnet *ifp; 1422 1423 sc = xsc; 1424 SIS_LOCK(sc); 1425 ifp = &sc->arpcom.ac_if; 1426 1427 mii = device_get_softc(sc->sis_miibus); 1428 mii_tick(mii); 1429 1430 if (!sc->sis_link && mii->mii_media_status & IFM_ACTIVE && 1431 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1432 sc->sis_link++; 1433 if (ifp->if_snd.ifq_head != NULL) 1434 sis_start(ifp); 1435 } 1436 1437 sc->sis_stat_ch = timeout(sis_tick, sc, hz); 1438 1439 SIS_UNLOCK(sc); 1440 1441 return; 1442} 1443 1444static void sis_intr(arg) 1445 void *arg; 1446{ 1447 struct sis_softc *sc; 1448 struct ifnet *ifp; 1449 u_int32_t status; 1450 1451 sc = arg; 1452 ifp = &sc->arpcom.ac_if; 1453 1454 SIS_LOCK(sc); 1455 /* Supress unwanted interrupts */ 1456 if (!(ifp->if_flags & IFF_UP)) { 1457 sis_stop(sc); 1458 goto done; 1459 } 1460 1461 /* Disable interrupts. */ 1462 CSR_WRITE_4(sc, SIS_IER, 0); 1463 1464 for (;;) { 1465 /* Reading the ISR register clears all interrupts. */ 1466 status = CSR_READ_4(sc, SIS_ISR); 1467 1468 if ((status & SIS_INTRS) == 0) 1469 break; 1470 1471 if (status & 1472 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | 1473 SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) ) 1474 sis_txeof(sc); 1475 1476 if (status & (SIS_ISR_RX_DESC_OK|SIS_ISR_RX_OK|SIS_ISR_RX_IDLE)) 1477 sis_rxeof(sc); 1478 1479 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW)) 1480 sis_rxeoc(sc); 1481 1482 if (status & (SIS_ISR_RX_IDLE)) 1483 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1484 1485 if (status & SIS_ISR_SYSERR) { 1486 sis_reset(sc); 1487 sis_init(sc); 1488 } 1489 } 1490 1491 /* Re-enable interrupts. */ 1492 CSR_WRITE_4(sc, SIS_IER, 1); 1493 1494 if (ifp->if_snd.ifq_head != NULL) 1495 sis_start(ifp); 1496done: 1497 SIS_UNLOCK(sc); 1498 1499 return; 1500} 1501 1502/* 1503 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1504 * pointers to the fragment pointers. 1505 */ 1506static int sis_encap(sc, m_head, txidx) 1507 struct sis_softc *sc; 1508 struct mbuf *m_head; 1509 u_int32_t *txidx; 1510{ 1511 struct sis_desc *f = NULL; 1512 struct mbuf *m; 1513 int frag, cur, cnt = 0; 1514 1515 /* 1516 * Start packing the mbufs in this chain into 1517 * the fragment pointers. Stop when we run out 1518 * of fragments or hit the end of the mbuf chain. 1519 */ 1520 m = m_head; 1521 cur = frag = *txidx; 1522 1523 for (m = m_head; m != NULL; m = m->m_next) { 1524 if (m->m_len != 0) { 1525 if ((SIS_TX_LIST_CNT - 1526 (sc->sis_cdata.sis_tx_cnt + cnt)) < 2) 1527 return(ENOBUFS); 1528 f = &sc->sis_ldata.sis_tx_list[frag]; 1529 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; 1530 bus_dmamap_create(sc->sis_tag, 0, &f->sis_map); 1531 bus_dmamap_load(sc->sis_tag, f->sis_map, 1532 mtod(m, void *), m->m_len, 1533 sis_dma_map_desc_ptr, f, 0); 1534 bus_dmamap_sync(sc->sis_tag, 1535 f->sis_map, BUS_DMASYNC_PREREAD); 1536 if (cnt != 0) 1537 f->sis_ctl |= SIS_CMDSTS_OWN; 1538 cur = frag; 1539 SIS_INC(frag, SIS_TX_LIST_CNT); 1540 cnt++; 1541 } 1542 } 1543 1544 if (m != NULL) 1545 return(ENOBUFS); 1546 1547 sc->sis_ldata.sis_tx_list[cur].sis_mbuf = m_head; 1548 sc->sis_ldata.sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1549 sc->sis_ldata.sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1550 sc->sis_cdata.sis_tx_cnt += cnt; 1551 *txidx = frag; 1552 1553 return(0); 1554} 1555 1556/* 1557 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1558 * to the mbuf data regions directly in the transmit lists. We also save a 1559 * copy of the pointers since the transmit list fragment pointers are 1560 * physical addresses. 1561 */ 1562 1563static void sis_start(ifp) 1564 struct ifnet *ifp; 1565{ 1566 struct sis_softc *sc; 1567 struct mbuf *m_head = NULL; 1568 u_int32_t idx; 1569 1570 sc = ifp->if_softc; 1571 SIS_LOCK(sc); 1572 1573 if (!sc->sis_link) { 1574 SIS_UNLOCK(sc); 1575 return; 1576 } 1577 1578 idx = sc->sis_cdata.sis_tx_prod; 1579 1580 if (ifp->if_flags & IFF_OACTIVE) { 1581 SIS_UNLOCK(sc); 1582 return; 1583 } 1584 1585 while(sc->sis_ldata.sis_tx_list[idx].sis_mbuf == NULL) { 1586 IF_DEQUEUE(&ifp->if_snd, m_head); 1587 if (m_head == NULL) 1588 break; 1589 1590 if (sis_encap(sc, m_head, &idx)) { 1591 IF_PREPEND(&ifp->if_snd, m_head); 1592 ifp->if_flags |= IFF_OACTIVE; 1593 break; 1594 } 1595 1596 /* 1597 * If there's a BPF listener, bounce a copy of this frame 1598 * to him. 1599 */ 1600 if (ifp->if_bpf) 1601 bpf_mtap(ifp, m_head); 1602 1603 } 1604 1605 /* Transmit */ 1606 sc->sis_cdata.sis_tx_prod = idx; 1607 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 1608 1609 /* 1610 * Set a timeout in case the chip goes out to lunch. 1611 */ 1612 ifp->if_timer = 5; 1613 1614 SIS_UNLOCK(sc); 1615 1616 return; 1617} 1618 1619static void sis_init(xsc) 1620 void *xsc; 1621{ 1622 struct sis_softc *sc = xsc; 1623 struct ifnet *ifp = &sc->arpcom.ac_if; 1624 struct mii_data *mii; 1625 1626 SIS_LOCK(sc); 1627 1628 /* 1629 * Cancel pending I/O and free all RX/TX buffers. 1630 */ 1631 sis_stop(sc); 1632 1633 mii = device_get_softc(sc->sis_miibus); 1634 1635 /* Set MAC address */ 1636 if (sc->sis_type == SIS_TYPE_83815) { 1637 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 1638 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1639 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1640 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 1641 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1642 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1643 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 1644 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1645 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1646 } else { 1647 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 1648 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1649 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1650 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 1651 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1652 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1653 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 1654 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1655 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1656 } 1657 1658 /* Init circular RX list. */ 1659 if (sis_list_rx_init(sc) == ENOBUFS) { 1660 printf("sis%d: initialization failed: no " 1661 "memory for rx buffers\n", sc->sis_unit); 1662 sis_stop(sc); 1663 SIS_UNLOCK(sc); 1664 return; 1665 } 1666 1667 /* 1668 * Init tx descriptors. 1669 */ 1670 sis_list_tx_init(sc); 1671 1672 /* 1673 * For the NatSemi chip, we have to explicitly enable the 1674 * reception of ARP frames, as well as turn on the 'perfect 1675 * match' filter where we store the station address, otherwise 1676 * we won't receive unicasts meant for this host. 1677 */ 1678 if (sc->sis_type == SIS_TYPE_83815) { 1679 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 1680 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 1681 } 1682 1683 /* If we want promiscuous mode, set the allframes bit. */ 1684 if (ifp->if_flags & IFF_PROMISC) { 1685 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1686 } else { 1687 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1688 } 1689 1690 /* 1691 * Set the capture broadcast bit to capture broadcast frames. 1692 */ 1693 if (ifp->if_flags & IFF_BROADCAST) { 1694 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1695 } else { 1696 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1697 } 1698 1699 /* 1700 * Load the multicast filter. 1701 */ 1702 if (sc->sis_type == SIS_TYPE_83815) 1703 sis_setmulti_ns(sc); 1704 else 1705 sis_setmulti_sis(sc); 1706 1707 /* Turn the receive filter on */ 1708 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 1709 1710 /* 1711 * Load the address of the RX and TX lists. 1712 */ 1713 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_cdata.sis_rx_paddr); 1714 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_cdata.sis_tx_paddr); 1715 1716 /* Set RX configuration */ 1717 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG); 1718 1719 /* Accept Long Packets for VLAN support */ 1720 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 1721 1722 /* Set TX configuration */ 1723 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 1724 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 1725 } else { 1726 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 1727 } 1728 1729 /* Set full/half duplex mode. */ 1730 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1731 SIS_SETBIT(sc, SIS_TX_CFG, 1732 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 1733 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 1734 } else { 1735 SIS_CLRBIT(sc, SIS_TX_CFG, 1736 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 1737 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 1738 } 1739 1740 /* 1741 * Enable interrupts. 1742 */ 1743 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 1744 CSR_WRITE_4(sc, SIS_IER, 1); 1745 1746 /* Enable receiver and transmitter. */ 1747 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 1748 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1749 1750#ifdef notdef 1751 mii_mediachg(mii); 1752#endif 1753 1754 /* 1755 * Page 75 of the DP83815 manual recommends the 1756 * following register settings "for optimum 1757 * performance." Note however that at least three 1758 * of the registers are listed as "reserved" in 1759 * the register map, so who knows what they do. 1760 */ 1761 if (sc->sis_type == SIS_TYPE_83815) { 1762 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 1763 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 1764 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 1765 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 1766 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 1767 } 1768 1769 ifp->if_flags |= IFF_RUNNING; 1770 ifp->if_flags &= ~IFF_OACTIVE; 1771 1772 sc->sis_stat_ch = timeout(sis_tick, sc, hz); 1773 1774 SIS_UNLOCK(sc); 1775 1776 return; 1777} 1778 1779/* 1780 * Set media options. 1781 */ 1782static int sis_ifmedia_upd(ifp) 1783 struct ifnet *ifp; 1784{ 1785 struct sis_softc *sc; 1786 struct mii_data *mii; 1787 1788 sc = ifp->if_softc; 1789 1790 mii = device_get_softc(sc->sis_miibus); 1791 sc->sis_link = 0; 1792 if (mii->mii_instance) { 1793 struct mii_softc *miisc; 1794 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1795 mii_phy_reset(miisc); 1796 } 1797 mii_mediachg(mii); 1798 1799 return(0); 1800} 1801 1802/* 1803 * Report current media status. 1804 */ 1805static void sis_ifmedia_sts(ifp, ifmr) 1806 struct ifnet *ifp; 1807 struct ifmediareq *ifmr; 1808{ 1809 struct sis_softc *sc; 1810 struct mii_data *mii; 1811 1812 sc = ifp->if_softc; 1813 1814 mii = device_get_softc(sc->sis_miibus); 1815 mii_pollstat(mii); 1816 ifmr->ifm_active = mii->mii_media_active; 1817 ifmr->ifm_status = mii->mii_media_status; 1818 1819 return; 1820} 1821 1822static int sis_ioctl(ifp, command, data) 1823 struct ifnet *ifp; 1824 u_long command; 1825 caddr_t data; 1826{ 1827 struct sis_softc *sc = ifp->if_softc; 1828 struct ifreq *ifr = (struct ifreq *) data; 1829 struct mii_data *mii; 1830 int error = 0; 1831 1832 switch(command) { 1833 case SIOCSIFADDR: 1834 case SIOCGIFADDR: 1835 case SIOCSIFMTU: 1836 error = ether_ioctl(ifp, command, data); 1837 break; 1838 case SIOCSIFFLAGS: 1839 if (ifp->if_flags & IFF_UP) { 1840 sis_init(sc); 1841 } else { 1842 if (ifp->if_flags & IFF_RUNNING) 1843 sis_stop(sc); 1844 } 1845 error = 0; 1846 break; 1847 case SIOCADDMULTI: 1848 case SIOCDELMULTI: 1849 SIS_LOCK(sc); 1850 if (sc->sis_type == SIS_TYPE_83815) 1851 sis_setmulti_ns(sc); 1852 else 1853 sis_setmulti_sis(sc); 1854 SIS_UNLOCK(sc); 1855 error = 0; 1856 break; 1857 case SIOCGIFMEDIA: 1858 case SIOCSIFMEDIA: 1859 mii = device_get_softc(sc->sis_miibus); 1860 SIS_LOCK(sc); 1861 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1862 SIS_UNLOCK(sc); 1863 break; 1864 default: 1865 error = EINVAL; 1866 break; 1867 } 1868 1869 return(error); 1870} 1871 1872static void sis_watchdog(ifp) 1873 struct ifnet *ifp; 1874{ 1875 struct sis_softc *sc; 1876 1877 sc = ifp->if_softc; 1878 1879 SIS_LOCK(sc); 1880 1881 ifp->if_oerrors++; 1882 printf("sis%d: watchdog timeout\n", sc->sis_unit); 1883 1884 sis_stop(sc); 1885 sis_reset(sc); 1886 sis_init(sc); 1887 1888 if (ifp->if_snd.ifq_head != NULL) 1889 sis_start(ifp); 1890 1891 SIS_UNLOCK(sc); 1892 1893 return; 1894} 1895 1896/* 1897 * Stop the adapter and free any mbufs allocated to the 1898 * RX and TX lists. 1899 */ 1900static void sis_stop(sc) 1901 struct sis_softc *sc; 1902{ 1903 register int i; 1904 struct ifnet *ifp; 1905 1906 SIS_LOCK(sc); 1907 ifp = &sc->arpcom.ac_if; 1908 ifp->if_timer = 0; 1909 1910 untimeout(sis_tick, sc, sc->sis_stat_ch); 1911 CSR_WRITE_4(sc, SIS_IER, 0); 1912 CSR_WRITE_4(sc, SIS_IMR, 0); 1913 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 1914 DELAY(1000); 1915 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 1916 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 1917 1918 sc->sis_link = 0; 1919 1920 /* 1921 * Free data in the RX lists. 1922 */ 1923 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1924 if (sc->sis_ldata.sis_rx_list[i].sis_mbuf != NULL) { 1925 bus_dmamap_unload(sc->sis_tag, 1926 sc->sis_ldata.sis_rx_list[i].sis_map); 1927 bus_dmamap_destroy(sc->sis_tag, 1928 sc->sis_ldata.sis_rx_list[i].sis_map); 1929 m_freem(sc->sis_ldata.sis_rx_list[i].sis_mbuf); 1930 sc->sis_ldata.sis_rx_list[i].sis_mbuf = NULL; 1931 } 1932 } 1933 bzero(sc->sis_ldata.sis_rx_list, 1934 sizeof(sc->sis_ldata.sis_rx_list)); 1935 1936 /* 1937 * Free the TX list buffers. 1938 */ 1939 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1940 if (sc->sis_ldata.sis_tx_list[i].sis_mbuf != NULL) { 1941 bus_dmamap_unload(sc->sis_tag, 1942 sc->sis_ldata.sis_tx_list[i].sis_map); 1943 bus_dmamap_destroy(sc->sis_tag, 1944 sc->sis_ldata.sis_tx_list[i].sis_map); 1945 m_freem(sc->sis_ldata.sis_tx_list[i].sis_mbuf); 1946 sc->sis_ldata.sis_tx_list[i].sis_mbuf = NULL; 1947 } 1948 } 1949 1950 bzero(sc->sis_ldata.sis_tx_list, 1951 sizeof(sc->sis_ldata.sis_tx_list)); 1952 1953 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1954 1955 SIS_UNLOCK(sc); 1956 1957 return; 1958} 1959 1960/* 1961 * Stop all chip I/O so that the kernel's probe routines don't 1962 * get confused by errant DMAs when rebooting. 1963 */ 1964static void sis_shutdown(dev) 1965 device_t dev; 1966{ 1967 struct sis_softc *sc; 1968 1969 sc = device_get_softc(dev); 1970 SIS_LOCK(sc); 1971 sis_reset(sc); 1972 sis_stop(sc); 1973 SIS_UNLOCK(sc); 1974 1975 return; 1976} 1977