if_sis.c revision 67087
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_sis.c 67087 2000-10-13 17:54:19Z wpaul $ 33 */ 34 35/* 36 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 37 * available from http://www.sis.com.tw. 38 * 39 * This driver also supports the NatSemi DP83815. Datasheets are 40 * available from http://www.national.com. 41 * 42 * Written by Bill Paul <wpaul@ee.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47/* 48 * The SiS 900 is a fairly simple chip. It uses bus master DMA with 49 * simple TX and RX descriptors of 3 longwords in size. The receiver 50 * has a single perfect filter entry for the station address and a 51 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 52 * transceiver while the 7016 requires an external transceiver chip. 53 * Both chips offer the standard bit-bang MII interface as well as 54 * an enchanced PHY interface which simplifies accessing MII registers. 55 * 56 * The only downside to this chipset is that RX descriptors must be 57 * longword aligned. 58 */ 59 60#include <sys/param.h> 61#include <sys/systm.h> 62#include <sys/sockio.h> 63#include <sys/mbuf.h> 64#include <sys/malloc.h> 65#include <sys/kernel.h> 66#include <sys/socket.h> 67 68#include <net/if.h> 69#include <net/if_arp.h> 70#include <net/ethernet.h> 71#include <net/if_dl.h> 72#include <net/if_media.h> 73 74#include <net/bpf.h> 75 76#include <vm/vm.h> /* for vtophys */ 77#include <vm/pmap.h> /* for vtophys */ 78#include <machine/clock.h> /* for DELAY */ 79#include <machine/bus_pio.h> 80#include <machine/bus_memio.h> 81#include <machine/bus.h> 82#include <machine/resource.h> 83#include <sys/bus.h> 84#include <sys/rman.h> 85 86#include <dev/mii/mii.h> 87#include <dev/mii/miivar.h> 88 89#include <pci/pcireg.h> 90#include <pci/pcivar.h> 91 92#define SIS_USEIOSPACE 93 94#include <pci/if_sisreg.h> 95 96MODULE_DEPEND(sis, miibus, 1, 1, 1); 97 98/* "controller miibus0" required. See GENERIC if you get errors here. */ 99#include "miibus_if.h" 100 101#ifndef lint 102static const char rcsid[] = 103 "$FreeBSD: head/sys/pci/if_sis.c 67087 2000-10-13 17:54:19Z wpaul $"; 104#endif 105 106/* 107 * Various supported device vendors/types and their names. 108 */ 109static struct sis_type sis_devs[] = { 110 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 111 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 112 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP83815 10/100BaseTX" }, 113 { 0, 0, NULL } 114}; 115 116static int sis_probe __P((device_t)); 117static int sis_attach __P((device_t)); 118static int sis_detach __P((device_t)); 119 120static int sis_newbuf __P((struct sis_softc *, 121 struct sis_desc *, 122 struct mbuf *)); 123static int sis_encap __P((struct sis_softc *, 124 struct mbuf *, u_int32_t *)); 125static void sis_rxeof __P((struct sis_softc *)); 126static void sis_rxeoc __P((struct sis_softc *)); 127static void sis_txeof __P((struct sis_softc *)); 128static void sis_intr __P((void *)); 129static void sis_tick __P((void *)); 130static void sis_start __P((struct ifnet *)); 131static int sis_ioctl __P((struct ifnet *, u_long, caddr_t)); 132static void sis_init __P((void *)); 133static void sis_stop __P((struct sis_softc *)); 134static void sis_watchdog __P((struct ifnet *)); 135static void sis_shutdown __P((device_t)); 136static int sis_ifmedia_upd __P((struct ifnet *)); 137static void sis_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 138 139static u_int16_t sis_reverse __P((u_int16_t)); 140static void sis_delay __P((struct sis_softc *)); 141static void sis_eeprom_idle __P((struct sis_softc *)); 142static void sis_eeprom_putbyte __P((struct sis_softc *, int)); 143static void sis_eeprom_getword __P((struct sis_softc *, int, u_int16_t *)); 144static void sis_read_eeprom __P((struct sis_softc *, caddr_t, int, 145 int, int)); 146static int sis_miibus_readreg __P((device_t, int, int)); 147static int sis_miibus_writereg __P((device_t, int, int, int)); 148static void sis_miibus_statchg __P((device_t)); 149 150static void sis_setmulti_sis __P((struct sis_softc *)); 151static void sis_setmulti_ns __P((struct sis_softc *)); 152static u_int32_t sis_crc __P((struct sis_softc *, caddr_t)); 153static void sis_reset __P((struct sis_softc *)); 154static int sis_list_rx_init __P((struct sis_softc *)); 155static int sis_list_tx_init __P((struct sis_softc *)); 156 157#ifdef SIS_USEIOSPACE 158#define SIS_RES SYS_RES_IOPORT 159#define SIS_RID SIS_PCI_LOIO 160#else 161#define SIS_RES SYS_RES_MEMORY 162#define SIS_RID SIS_PCI_LOMEM 163#endif 164 165static device_method_t sis_methods[] = { 166 /* Device interface */ 167 DEVMETHOD(device_probe, sis_probe), 168 DEVMETHOD(device_attach, sis_attach), 169 DEVMETHOD(device_detach, sis_detach), 170 DEVMETHOD(device_shutdown, sis_shutdown), 171 172 /* bus interface */ 173 DEVMETHOD(bus_print_child, bus_generic_print_child), 174 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 175 176 /* MII interface */ 177 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 178 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 179 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 180 181 { 0, 0 } 182}; 183 184static driver_t sis_driver = { 185 "sis", 186 sis_methods, 187 sizeof(struct sis_softc) 188}; 189 190static devclass_t sis_devclass; 191 192DRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, 0, 0); 193DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 194 195#define SIS_SETBIT(sc, reg, x) \ 196 CSR_WRITE_4(sc, reg, \ 197 CSR_READ_4(sc, reg) | (x)) 198 199#define SIS_CLRBIT(sc, reg, x) \ 200 CSR_WRITE_4(sc, reg, \ 201 CSR_READ_4(sc, reg) & ~(x)) 202 203#define SIO_SET(x) \ 204 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 205 206#define SIO_CLR(x) \ 207 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 208 209/* 210 * Routine to reverse the bits in a word. Stolen almost 211 * verbatim from /usr/games/fortune. 212 */ 213static u_int16_t sis_reverse(n) 214 u_int16_t n; 215{ 216 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 217 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 218 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 219 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 220 221 return(n); 222} 223 224static void sis_delay(sc) 225 struct sis_softc *sc; 226{ 227 int idx; 228 229 for (idx = (300 / 33) + 1; idx > 0; idx--) 230 CSR_READ_4(sc, SIS_CSR); 231 232 return; 233} 234 235static void sis_eeprom_idle(sc) 236 struct sis_softc *sc; 237{ 238 register int i; 239 240 SIO_SET(SIS_EECTL_CSEL); 241 sis_delay(sc); 242 SIO_SET(SIS_EECTL_CLK); 243 sis_delay(sc); 244 245 for (i = 0; i < 25; i++) { 246 SIO_CLR(SIS_EECTL_CLK); 247 sis_delay(sc); 248 SIO_SET(SIS_EECTL_CLK); 249 sis_delay(sc); 250 } 251 252 SIO_CLR(SIS_EECTL_CLK); 253 sis_delay(sc); 254 SIO_CLR(SIS_EECTL_CSEL); 255 sis_delay(sc); 256 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 257 258 return; 259} 260 261/* 262 * Send a read command and address to the EEPROM, check for ACK. 263 */ 264static void sis_eeprom_putbyte(sc, addr) 265 struct sis_softc *sc; 266 int addr; 267{ 268 register int d, i; 269 270 d = addr | SIS_EECMD_READ; 271 272 /* 273 * Feed in each bit and stobe the clock. 274 */ 275 for (i = 0x400; i; i >>= 1) { 276 if (d & i) { 277 SIO_SET(SIS_EECTL_DIN); 278 } else { 279 SIO_CLR(SIS_EECTL_DIN); 280 } 281 sis_delay(sc); 282 SIO_SET(SIS_EECTL_CLK); 283 sis_delay(sc); 284 SIO_CLR(SIS_EECTL_CLK); 285 sis_delay(sc); 286 } 287 288 return; 289} 290 291/* 292 * Read a word of data stored in the EEPROM at address 'addr.' 293 */ 294static void sis_eeprom_getword(sc, addr, dest) 295 struct sis_softc *sc; 296 int addr; 297 u_int16_t *dest; 298{ 299 register int i; 300 u_int16_t word = 0; 301 302 /* Force EEPROM to idle state. */ 303 sis_eeprom_idle(sc); 304 305 /* Enter EEPROM access mode. */ 306 sis_delay(sc); 307 SIO_CLR(SIS_EECTL_CLK); 308 sis_delay(sc); 309 SIO_SET(SIS_EECTL_CSEL); 310 sis_delay(sc); 311 312 /* 313 * Send address of word we want to read. 314 */ 315 sis_eeprom_putbyte(sc, addr); 316 317 /* 318 * Start reading bits from EEPROM. 319 */ 320 for (i = 0x8000; i; i >>= 1) { 321 SIO_SET(SIS_EECTL_CLK); 322 sis_delay(sc); 323 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 324 word |= i; 325 sis_delay(sc); 326 SIO_CLR(SIS_EECTL_CLK); 327 sis_delay(sc); 328 } 329 330 /* Turn off EEPROM access mode. */ 331 sis_eeprom_idle(sc); 332 333 *dest = word; 334 335 return; 336} 337 338/* 339 * Read a sequence of words from the EEPROM. 340 */ 341static void sis_read_eeprom(sc, dest, off, cnt, swap) 342 struct sis_softc *sc; 343 caddr_t dest; 344 int off; 345 int cnt; 346 int swap; 347{ 348 int i; 349 u_int16_t word = 0, *ptr; 350 351 for (i = 0; i < cnt; i++) { 352 sis_eeprom_getword(sc, off + i, &word); 353 ptr = (u_int16_t *)(dest + (i * 2)); 354 if (swap) 355 *ptr = ntohs(word); 356 else 357 *ptr = word; 358 } 359 360 return; 361} 362 363static int sis_miibus_readreg(dev, phy, reg) 364 device_t dev; 365 int phy, reg; 366{ 367 struct sis_softc *sc; 368 int i, val = 0; 369 370 sc = device_get_softc(dev); 371 372 if (sc->sis_type == SIS_TYPE_83815) { 373 if (phy != 0) 374 return(0); 375 /* 376 * The NatSemi chip can take a while after 377 * a reset to come ready, during which the BMSR 378 * returns a value of 0. This is *never* supposed 379 * to happen: some of the BMSR bits are meant to 380 * be hardwired in the on position, and this can 381 * confuse the miibus code a bit during the probe 382 * and attach phase. So we make an effort to check 383 * for this condition and wait for it to clear. 384 */ 385 if (!CSR_READ_4(sc, NS_BMSR)) 386 DELAY(1000); 387 val = CSR_READ_4(sc, NS_BMCR + (reg * 4)); 388 return(val); 389 } 390 391 if (sc->sis_type == SIS_TYPE_900 && phy != 0) 392 return(0); 393 394 CSR_WRITE_4(sc, SIS_PHYCTL, (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 395 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 396 397 for (i = 0; i < SIS_TIMEOUT; i++) { 398 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 399 break; 400 } 401 402 if (i == SIS_TIMEOUT) { 403 printf("sis%d: PHY failed to come ready\n", sc->sis_unit); 404 return(0); 405 } 406 407 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 408 409 if (val == 0xFFFF) 410 return(0); 411 412 return(val); 413} 414 415static int sis_miibus_writereg(dev, phy, reg, data) 416 device_t dev; 417 int phy, reg, data; 418{ 419 struct sis_softc *sc; 420 int i; 421 422 sc = device_get_softc(dev); 423 424 if (sc->sis_type == SIS_TYPE_83815) { 425 if (phy != 0) 426 return(0); 427 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 428 return(0); 429 } 430 431 if (sc->sis_type == SIS_TYPE_900 && phy != 0) 432 return(0); 433 434 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 435 (reg << 6) | SIS_PHYOP_WRITE); 436 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 437 438 for (i = 0; i < SIS_TIMEOUT; i++) { 439 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 440 break; 441 } 442 443 if (i == SIS_TIMEOUT) 444 printf("sis%d: PHY failed to come ready\n", sc->sis_unit); 445 446 return(0); 447} 448 449static void sis_miibus_statchg(dev) 450 device_t dev; 451{ 452 struct sis_softc *sc; 453 454 sc = device_get_softc(dev); 455 sis_init(sc); 456 457 return; 458} 459 460static u_int32_t sis_crc(sc, addr) 461 struct sis_softc *sc; 462 caddr_t addr; 463{ 464 u_int32_t crc, carry; 465 int i, j; 466 u_int8_t c; 467 468 /* Compute CRC for the address value. */ 469 crc = 0xFFFFFFFF; /* initial value */ 470 471 for (i = 0; i < 6; i++) { 472 c = *(addr + i); 473 for (j = 0; j < 8; j++) { 474 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 475 crc <<= 1; 476 c >>= 1; 477 if (carry) 478 crc = (crc ^ 0x04c11db6) | carry; 479 } 480 } 481 482 /* 483 * return the filter bit position 484 * 485 * The NatSemi chip has a 512-bit filter, which is 486 * different than the SiS, so we special-case it. 487 */ 488 if (sc->sis_type == SIS_TYPE_83815) 489 return((crc >> 23) & 0x1FF); 490 491 return((crc >> 25) & 0x0000007F); 492} 493 494static void sis_setmulti_ns(sc) 495 struct sis_softc *sc; 496{ 497 struct ifnet *ifp; 498 struct ifmultiaddr *ifma; 499 u_int32_t h = 0, i, filtsave; 500 int bit, index; 501 502 ifp = &sc->arpcom.ac_if; 503 504 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 505 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 506 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 507 return; 508 } 509 510 /* 511 * We have to explicitly enable the multicast hash table 512 * on the NatSemi chip if we want to use it, which we do. 513 */ 514 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 515 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 516 517 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 518 519 /* first, zot all the existing hash bits */ 520 for (i = 0; i < 32; i++) { 521 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 522 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 523 } 524 525 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 526 ifma = ifma->ifma_link.le_next) { 527 if (ifma->ifma_addr->sa_family != AF_LINK) 528 continue; 529 h = sis_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 530 index = h >> 3; 531 bit = h & 0x1F; 532 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 533 if (bit > 0xF) 534 bit -= 0x10; 535 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 536 } 537 538 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 539 540 return; 541} 542 543static void sis_setmulti_sis(sc) 544 struct sis_softc *sc; 545{ 546 struct ifnet *ifp; 547 struct ifmultiaddr *ifma; 548 u_int32_t h = 0, i, filtsave; 549 550 ifp = &sc->arpcom.ac_if; 551 552 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 553 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 554 return; 555 } 556 557 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 558 559 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 560 561 /* first, zot all the existing hash bits */ 562 for (i = 0; i < 8; i++) { 563 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + ((i * 16) >> 4)) << 16); 564 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 565 } 566 567 /* now program new ones */ 568 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 569 ifma = ifma->ifma_link.le_next) { 570 if (ifma->ifma_addr->sa_family != AF_LINK) 571 continue; 572 h = sis_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 573 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + (h >> 4)) << 16); 574 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << (h & 0xF))); 575 } 576 577 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 578 579 return; 580} 581 582static void sis_reset(sc) 583 struct sis_softc *sc; 584{ 585 register int i; 586 587 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 588 589 for (i = 0; i < SIS_TIMEOUT; i++) { 590 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 591 break; 592 } 593 594 if (i == SIS_TIMEOUT) 595 printf("sis%d: reset never completed\n", sc->sis_unit); 596 597 /* Wait a little while for the chip to get its brains in order. */ 598 DELAY(1000); 599 return; 600} 601 602/* 603 * Probe for an SiS chip. Check the PCI vendor and device 604 * IDs against our list and return a device name if we find a match. 605 */ 606static int sis_probe(dev) 607 device_t dev; 608{ 609 struct sis_type *t; 610 611 t = sis_devs; 612 613 while(t->sis_name != NULL) { 614 if ((pci_get_vendor(dev) == t->sis_vid) && 615 (pci_get_device(dev) == t->sis_did)) { 616 device_set_desc(dev, t->sis_name); 617 return(0); 618 } 619 t++; 620 } 621 622 return(ENXIO); 623} 624 625/* 626 * Attach the interface. Allocate softc structures, do ifmedia 627 * setup and ethernet/BPF attach. 628 */ 629static int sis_attach(dev) 630 device_t dev; 631{ 632 u_char eaddr[ETHER_ADDR_LEN]; 633 u_int32_t command; 634 struct sis_softc *sc; 635 struct ifnet *ifp; 636 int unit, error = 0, rid; 637 638 sc = device_get_softc(dev); 639 unit = device_get_unit(dev); 640 bzero(sc, sizeof(struct sis_softc)); 641 642 if (pci_get_device(dev) == SIS_DEVICEID_900) 643 sc->sis_type = SIS_TYPE_900; 644 if (pci_get_device(dev) == SIS_DEVICEID_7016) 645 sc->sis_type = SIS_TYPE_7016; 646 if (pci_get_vendor(dev) == NS_VENDORID) 647 sc->sis_type = SIS_TYPE_83815; 648 649 /* 650 * Handle power management nonsense. 651 */ 652 653 command = pci_read_config(dev, SIS_PCI_CAPID, 4) & 0x000000FF; 654 if (command == 0x01) { 655 656 command = pci_read_config(dev, SIS_PCI_PWRMGMTCTRL, 4); 657 if (command & SIS_PSTATE_MASK) { 658 u_int32_t iobase, membase, irq; 659 660 /* Save important PCI config data. */ 661 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4); 662 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4); 663 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4); 664 665 /* Reset the power state. */ 666 printf("sis%d: chip is in D%d power mode " 667 "-- setting to D0\n", unit, command & SIS_PSTATE_MASK); 668 command &= 0xFFFFFFFC; 669 pci_write_config(dev, SIS_PCI_PWRMGMTCTRL, command, 4); 670 671 /* Restore PCI config data. */ 672 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4); 673 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4); 674 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4); 675 } 676 } 677 678 /* 679 * Map control/status registers. 680 */ 681 command = pci_read_config(dev, PCIR_COMMAND, 4); 682 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 683 pci_write_config(dev, PCIR_COMMAND, command, 4); 684 command = pci_read_config(dev, PCIR_COMMAND, 4); 685 686#ifdef SIS_USEIOSPACE 687 if (!(command & PCIM_CMD_PORTEN)) { 688 printf("sis%d: failed to enable I/O ports!\n", unit); 689 error = ENXIO;; 690 goto fail; 691 } 692#else 693 if (!(command & PCIM_CMD_MEMEN)) { 694 printf("sis%d: failed to enable memory mapping!\n", unit); 695 error = ENXIO;; 696 goto fail; 697 } 698#endif 699 700 rid = SIS_RID; 701 sc->sis_res = bus_alloc_resource(dev, SIS_RES, &rid, 702 0, ~0, 1, RF_ACTIVE); 703 704 if (sc->sis_res == NULL) { 705 printf("sis%d: couldn't map ports/memory\n", unit); 706 error = ENXIO; 707 goto fail; 708 } 709 710 sc->sis_btag = rman_get_bustag(sc->sis_res); 711 sc->sis_bhandle = rman_get_bushandle(sc->sis_res); 712 713 /* Allocate interrupt */ 714 rid = 0; 715 sc->sis_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 716 RF_SHAREABLE | RF_ACTIVE); 717 718 if (sc->sis_irq == NULL) { 719 printf("sis%d: couldn't map interrupt\n", unit); 720 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 721 error = ENXIO; 722 goto fail; 723 } 724 725 error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET, 726 sis_intr, sc, &sc->sis_intrhand); 727 728 if (error) { 729 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_res); 730 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 731 printf("sis%d: couldn't set up irq\n", unit); 732 goto fail; 733 } 734 735 mtx_init(&sc->sis_mtx, "sis", MTX_DEF); 736 SIS_LOCK(sc); 737 738 /* Reset the adapter. */ 739 sis_reset(sc); 740 741 /* 742 * Get station address from the EEPROM. 743 */ 744 switch (pci_get_vendor(dev)) { 745 case NS_VENDORID: 746 /* 747 * Reading the MAC address out of the EEPROM on 748 * the NatSemi chip takes a bit more work than 749 * you'd expect. The address spans 4 16-bit words, 750 * with the first word containing only a single bit. 751 * You have to shift everything over one bit to 752 * get it aligned properly. Also, the bits are 753 * stored backwards (the LSB is really the MSB, 754 * and so on) so you have to reverse them in order 755 * to get the MAC address into the form we want. 756 * Why? Who the hell knows. 757 */ 758 { 759 u_int16_t tmp[4]; 760 761 sis_read_eeprom(sc, (caddr_t)&tmp, 762 NS_EE_NODEADDR, 4, 0); 763 764 /* Shift everything over one bit. */ 765 tmp[3] = tmp[3] >> 1; 766 tmp[3] |= tmp[2] << 15; 767 tmp[2] = tmp[2] >> 1; 768 tmp[2] |= tmp[1] << 15; 769 tmp[1] = tmp[1] >> 1; 770 tmp[1] |= tmp[0] << 15; 771 772 /* Now reverse all the bits. */ 773 tmp[3] = sis_reverse(tmp[3]); 774 tmp[2] = sis_reverse(tmp[2]); 775 tmp[1] = sis_reverse(tmp[1]); 776 777 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); 778 } 779 break; 780 case SIS_VENDORID: 781 default: 782 sis_read_eeprom(sc, (caddr_t)&eaddr, SIS_EE_NODEADDR, 3, 0); 783 break; 784 } 785 786 /* 787 * A SiS chip was detected. Inform the world. 788 */ 789 printf("sis%d: Ethernet address: %6D\n", unit, eaddr, ":"); 790 791 sc->sis_unit = unit; 792 callout_handle_init(&sc->sis_stat_ch); 793 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 794 795 sc->sis_ldata = contigmalloc(sizeof(struct sis_list_data), M_DEVBUF, 796 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 797 798 if (sc->sis_ldata == NULL) { 799 printf("sis%d: no memory for list buffers!\n", unit); 800 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 801 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 802 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 803 error = ENXIO; 804 goto fail; 805 } 806 bzero(sc->sis_ldata, sizeof(struct sis_list_data)); 807 808 ifp = &sc->arpcom.ac_if; 809 ifp->if_softc = sc; 810 ifp->if_unit = unit; 811 ifp->if_name = "sis"; 812 ifp->if_mtu = ETHERMTU; 813 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 814 ifp->if_ioctl = sis_ioctl; 815 ifp->if_output = ether_output; 816 ifp->if_start = sis_start; 817 ifp->if_watchdog = sis_watchdog; 818 ifp->if_init = sis_init; 819 ifp->if_baudrate = 10000000; 820 ifp->if_snd.ifq_maxlen = SIS_TX_LIST_CNT - 1; 821 822 /* 823 * Do MII setup. 824 */ 825 if (mii_phy_probe(dev, &sc->sis_miibus, 826 sis_ifmedia_upd, sis_ifmedia_sts)) { 827 printf("sis%d: MII without any PHY!\n", sc->sis_unit); 828 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 829 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 830 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 831 error = ENXIO; 832 goto fail; 833 } 834 835 /* 836 * Call MI attach routine. 837 */ 838 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 839 callout_handle_init(&sc->sis_stat_ch); 840 SIS_UNLOCK(sc); 841 return(0); 842 843fail: 844 SIS_UNLOCK(sc); 845 mtx_destroy(&sc->sis_mtx); 846 return(error); 847} 848 849static int sis_detach(dev) 850 device_t dev; 851{ 852 struct sis_softc *sc; 853 struct ifnet *ifp; 854 855 856 sc = device_get_softc(dev); 857 SIS_LOCK(sc); 858 ifp = &sc->arpcom.ac_if; 859 860 sis_reset(sc); 861 sis_stop(sc); 862 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 863 864 bus_generic_detach(dev); 865 device_delete_child(dev, sc->sis_miibus); 866 867 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 868 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 869 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 870 871 contigfree(sc->sis_ldata, sizeof(struct sis_list_data), M_DEVBUF); 872 873 SIS_UNLOCK(sc); 874 mtx_destroy(&sc->sis_mtx); 875 876 return(0); 877} 878 879/* 880 * Initialize the transmit descriptors. 881 */ 882static int sis_list_tx_init(sc) 883 struct sis_softc *sc; 884{ 885 struct sis_list_data *ld; 886 struct sis_ring_data *cd; 887 int i; 888 889 cd = &sc->sis_cdata; 890 ld = sc->sis_ldata; 891 892 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 893 if (i == (SIS_TX_LIST_CNT - 1)) { 894 ld->sis_tx_list[i].sis_nextdesc = 895 &ld->sis_tx_list[0]; 896 ld->sis_tx_list[i].sis_next = 897 vtophys(&ld->sis_tx_list[0]); 898 } else { 899 ld->sis_tx_list[i].sis_nextdesc = 900 &ld->sis_tx_list[i + 1]; 901 ld->sis_tx_list[i].sis_next = 902 vtophys(&ld->sis_tx_list[i + 1]); 903 } 904 ld->sis_tx_list[i].sis_mbuf = NULL; 905 ld->sis_tx_list[i].sis_ptr = 0; 906 ld->sis_tx_list[i].sis_ctl = 0; 907 } 908 909 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0; 910 911 return(0); 912} 913 914 915/* 916 * Initialize the RX descriptors and allocate mbufs for them. Note that 917 * we arrange the descriptors in a closed ring, so that the last descriptor 918 * points back to the first. 919 */ 920static int sis_list_rx_init(sc) 921 struct sis_softc *sc; 922{ 923 struct sis_list_data *ld; 924 struct sis_ring_data *cd; 925 int i; 926 927 ld = sc->sis_ldata; 928 cd = &sc->sis_cdata; 929 930 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 931 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS) 932 return(ENOBUFS); 933 if (i == (SIS_RX_LIST_CNT - 1)) { 934 ld->sis_rx_list[i].sis_nextdesc = 935 &ld->sis_rx_list[0]; 936 ld->sis_rx_list[i].sis_next = 937 vtophys(&ld->sis_rx_list[0]); 938 } else { 939 ld->sis_rx_list[i].sis_nextdesc = 940 &ld->sis_rx_list[i + 1]; 941 ld->sis_rx_list[i].sis_next = 942 vtophys(&ld->sis_rx_list[i + 1]); 943 } 944 } 945 946 cd->sis_rx_prod = 0; 947 948 return(0); 949} 950 951/* 952 * Initialize an RX descriptor and attach an MBUF cluster. 953 */ 954static int sis_newbuf(sc, c, m) 955 struct sis_softc *sc; 956 struct sis_desc *c; 957 struct mbuf *m; 958{ 959 struct mbuf *m_new = NULL; 960 961 if (m == NULL) { 962 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 963 if (m_new == NULL) { 964 printf("sis%d: no memory for rx list " 965 "-- packet dropped!\n", sc->sis_unit); 966 return(ENOBUFS); 967 } 968 969 MCLGET(m_new, M_DONTWAIT); 970 if (!(m_new->m_flags & M_EXT)) { 971 printf("sis%d: no memory for rx list " 972 "-- packet dropped!\n", sc->sis_unit); 973 m_freem(m_new); 974 return(ENOBUFS); 975 } 976 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 977 } else { 978 m_new = m; 979 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 980 m_new->m_data = m_new->m_ext.ext_buf; 981 } 982 983 m_adj(m_new, sizeof(u_int64_t)); 984 985 c->sis_mbuf = m_new; 986 c->sis_ptr = vtophys(mtod(m_new, caddr_t)); 987 c->sis_ctl = SIS_RXLEN; 988 989 return(0); 990} 991 992/* 993 * A frame has been uploaded: pass the resulting mbuf chain up to 994 * the higher level protocols. 995 */ 996static void sis_rxeof(sc) 997 struct sis_softc *sc; 998{ 999 struct ether_header *eh; 1000 struct mbuf *m; 1001 struct ifnet *ifp; 1002 struct sis_desc *cur_rx; 1003 int i, total_len = 0; 1004 u_int32_t rxstat; 1005 1006 ifp = &sc->arpcom.ac_if; 1007 i = sc->sis_cdata.sis_rx_prod; 1008 1009 while(SIS_OWNDESC(&sc->sis_ldata->sis_rx_list[i])) { 1010 struct mbuf *m0 = NULL; 1011 1012 cur_rx = &sc->sis_ldata->sis_rx_list[i]; 1013 rxstat = cur_rx->sis_rxstat; 1014 m = cur_rx->sis_mbuf; 1015 cur_rx->sis_mbuf = NULL; 1016 total_len = SIS_RXBYTES(cur_rx); 1017 SIS_INC(i, SIS_RX_LIST_CNT); 1018 1019 /* 1020 * If an error occurs, update stats, clear the 1021 * status word and leave the mbuf cluster in place: 1022 * it should simply get re-used next time this descriptor 1023 * comes up in the ring. 1024 */ 1025 if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 1026 ifp->if_ierrors++; 1027 if (rxstat & SIS_RXSTAT_COLL) 1028 ifp->if_collisions++; 1029 sis_newbuf(sc, cur_rx, m); 1030 continue; 1031 } 1032 1033 /* No errors; receive the packet. */ 1034 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1035 total_len + ETHER_ALIGN, 0, ifp, NULL); 1036 sis_newbuf(sc, cur_rx, m); 1037 if (m0 == NULL) { 1038 ifp->if_ierrors++; 1039 continue; 1040 } 1041 m_adj(m0, ETHER_ALIGN); 1042 m = m0; 1043 1044 ifp->if_ipackets++; 1045 eh = mtod(m, struct ether_header *); 1046 1047 /* Remove header from mbuf and pass it on. */ 1048 m_adj(m, sizeof(struct ether_header)); 1049 ether_input(ifp, eh, m); 1050 } 1051 1052 sc->sis_cdata.sis_rx_prod = i; 1053 1054 return; 1055} 1056 1057void sis_rxeoc(sc) 1058 struct sis_softc *sc; 1059{ 1060 sis_rxeof(sc); 1061 sis_init(sc); 1062 return; 1063} 1064 1065/* 1066 * A frame was downloaded to the chip. It's safe for us to clean up 1067 * the list buffers. 1068 */ 1069 1070static void sis_txeof(sc) 1071 struct sis_softc *sc; 1072{ 1073 struct sis_desc *cur_tx = NULL; 1074 struct ifnet *ifp; 1075 u_int32_t idx; 1076 1077 ifp = &sc->arpcom.ac_if; 1078 1079 /* Clear the timeout timer. */ 1080 ifp->if_timer = 0; 1081 1082 /* 1083 * Go through our tx list and free mbufs for those 1084 * frames that have been transmitted. 1085 */ 1086 idx = sc->sis_cdata.sis_tx_cons; 1087 while (idx != sc->sis_cdata.sis_tx_prod) { 1088 cur_tx = &sc->sis_ldata->sis_tx_list[idx]; 1089 1090 if (SIS_OWNDESC(cur_tx)) 1091 break; 1092 1093 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) { 1094 sc->sis_cdata.sis_tx_cnt--; 1095 SIS_INC(idx, SIS_TX_LIST_CNT); 1096 continue; 1097 } 1098 1099 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 1100 ifp->if_oerrors++; 1101 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 1102 ifp->if_collisions++; 1103 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 1104 ifp->if_collisions++; 1105 } 1106 1107 ifp->if_collisions += 1108 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 1109 1110 ifp->if_opackets++; 1111 if (cur_tx->sis_mbuf != NULL) { 1112 m_freem(cur_tx->sis_mbuf); 1113 cur_tx->sis_mbuf = NULL; 1114 } 1115 1116 sc->sis_cdata.sis_tx_cnt--; 1117 SIS_INC(idx, SIS_TX_LIST_CNT); 1118 ifp->if_timer = 0; 1119 } 1120 1121 sc->sis_cdata.sis_tx_cons = idx; 1122 1123 if (cur_tx != NULL) 1124 ifp->if_flags &= ~IFF_OACTIVE; 1125 1126 return; 1127} 1128 1129static void sis_tick(xsc) 1130 void *xsc; 1131{ 1132 struct sis_softc *sc; 1133 struct mii_data *mii; 1134 struct ifnet *ifp; 1135 1136 sc = xsc; 1137 SIS_LOCK(sc); 1138 ifp = &sc->arpcom.ac_if; 1139 1140 mii = device_get_softc(sc->sis_miibus); 1141 mii_tick(mii); 1142 1143 if (!sc->sis_link) { 1144 mii_pollstat(mii); 1145 if (mii->mii_media_status & IFM_ACTIVE && 1146 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1147 sc->sis_link++; 1148 if (ifp->if_snd.ifq_head != NULL) 1149 sis_start(ifp); 1150 } 1151 1152 sc->sis_stat_ch = timeout(sis_tick, sc, hz); 1153 1154 SIS_UNLOCK(sc); 1155 1156 return; 1157} 1158 1159static void sis_intr(arg) 1160 void *arg; 1161{ 1162 struct sis_softc *sc; 1163 struct ifnet *ifp; 1164 u_int32_t status; 1165 1166 sc = arg; 1167 SIS_LOCK(sc); 1168 ifp = &sc->arpcom.ac_if; 1169 1170 /* Supress unwanted interrupts */ 1171 if (!(ifp->if_flags & IFF_UP)) { 1172 sis_stop(sc); 1173 SIS_UNLOCK(sc); 1174 return; 1175 } 1176 1177 /* Disable interrupts. */ 1178 CSR_WRITE_4(sc, SIS_IER, 0); 1179 1180 for (;;) { 1181 /* Reading the ISR register clears all interrupts. */ 1182 status = CSR_READ_4(sc, SIS_ISR); 1183 1184 if ((status & SIS_INTRS) == 0) 1185 break; 1186 1187 if ((status & SIS_ISR_TX_DESC_OK) || 1188 (status & SIS_ISR_TX_ERR) || 1189 (status & SIS_ISR_TX_OK) || 1190 (status & SIS_ISR_TX_IDLE)) 1191 sis_txeof(sc); 1192 1193 if ((status & SIS_ISR_RX_DESC_OK) || 1194 (status & SIS_ISR_RX_OK)) 1195 sis_rxeof(sc); 1196 1197 if ((status & SIS_ISR_RX_ERR) || 1198 (status & SIS_ISR_RX_OFLOW)) { 1199 sis_rxeoc(sc); 1200 } 1201 1202 if (status & SIS_ISR_SYSERR) { 1203 sis_reset(sc); 1204 sis_init(sc); 1205 } 1206 } 1207 1208 /* Re-enable interrupts. */ 1209 CSR_WRITE_4(sc, SIS_IER, 1); 1210 1211 if (ifp->if_snd.ifq_head != NULL) 1212 sis_start(ifp); 1213 1214 SIS_UNLOCK(sc); 1215 1216 return; 1217} 1218 1219/* 1220 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1221 * pointers to the fragment pointers. 1222 */ 1223static int sis_encap(sc, m_head, txidx) 1224 struct sis_softc *sc; 1225 struct mbuf *m_head; 1226 u_int32_t *txidx; 1227{ 1228 struct sis_desc *f = NULL; 1229 struct mbuf *m; 1230 int frag, cur, cnt = 0; 1231 1232 /* 1233 * Start packing the mbufs in this chain into 1234 * the fragment pointers. Stop when we run out 1235 * of fragments or hit the end of the mbuf chain. 1236 */ 1237 m = m_head; 1238 cur = frag = *txidx; 1239 1240 for (m = m_head; m != NULL; m = m->m_next) { 1241 if (m->m_len != 0) { 1242 if ((SIS_TX_LIST_CNT - 1243 (sc->sis_cdata.sis_tx_cnt + cnt)) < 2) 1244 return(ENOBUFS); 1245 f = &sc->sis_ldata->sis_tx_list[frag]; 1246 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; 1247 f->sis_ptr = vtophys(mtod(m, vm_offset_t)); 1248 if (cnt != 0) 1249 f->sis_ctl |= SIS_CMDSTS_OWN; 1250 cur = frag; 1251 SIS_INC(frag, SIS_TX_LIST_CNT); 1252 cnt++; 1253 } 1254 } 1255 1256 if (m != NULL) 1257 return(ENOBUFS); 1258 1259 sc->sis_ldata->sis_tx_list[cur].sis_mbuf = m_head; 1260 sc->sis_ldata->sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1261 sc->sis_ldata->sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1262 sc->sis_cdata.sis_tx_cnt += cnt; 1263 *txidx = frag; 1264 1265 return(0); 1266} 1267 1268/* 1269 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1270 * to the mbuf data regions directly in the transmit lists. We also save a 1271 * copy of the pointers since the transmit list fragment pointers are 1272 * physical addresses. 1273 */ 1274 1275static void sis_start(ifp) 1276 struct ifnet *ifp; 1277{ 1278 struct sis_softc *sc; 1279 struct mbuf *m_head = NULL; 1280 u_int32_t idx; 1281 1282 sc = ifp->if_softc; 1283 SIS_LOCK(sc); 1284 1285 if (!sc->sis_link) { 1286 SIS_UNLOCK(sc); 1287 return; 1288 } 1289 1290 idx = sc->sis_cdata.sis_tx_prod; 1291 1292 if (ifp->if_flags & IFF_OACTIVE) { 1293 SIS_UNLOCK(sc); 1294 return; 1295 } 1296 1297 while(sc->sis_ldata->sis_tx_list[idx].sis_mbuf == NULL) { 1298 IF_DEQUEUE(&ifp->if_snd, m_head); 1299 if (m_head == NULL) 1300 break; 1301 1302 if (sis_encap(sc, m_head, &idx)) { 1303 IF_PREPEND(&ifp->if_snd, m_head); 1304 ifp->if_flags |= IFF_OACTIVE; 1305 break; 1306 } 1307 1308 /* 1309 * If there's a BPF listener, bounce a copy of this frame 1310 * to him. 1311 */ 1312 if (ifp->if_bpf) 1313 bpf_mtap(ifp, m_head); 1314 1315 } 1316 1317 /* Transmit */ 1318 sc->sis_cdata.sis_tx_prod = idx; 1319 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 1320 1321 /* 1322 * Set a timeout in case the chip goes out to lunch. 1323 */ 1324 ifp->if_timer = 5; 1325 1326 SIS_UNLOCK(sc); 1327 1328 return; 1329} 1330 1331static void sis_init(xsc) 1332 void *xsc; 1333{ 1334 struct sis_softc *sc = xsc; 1335 struct ifnet *ifp = &sc->arpcom.ac_if; 1336 struct mii_data *mii; 1337 1338 SIS_LOCK(sc); 1339 1340 /* 1341 * Cancel pending I/O and free all RX/TX buffers. 1342 */ 1343 sis_stop(sc); 1344 1345 mii = device_get_softc(sc->sis_miibus); 1346 1347 /* Set MAC address */ 1348 if (sc->sis_type == SIS_TYPE_83815) { 1349 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 1350 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1351 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1352 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 1353 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1354 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1355 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 1356 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1357 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1358 } else { 1359 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 1360 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1361 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1362 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 1363 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1364 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1365 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 1366 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1367 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1368 } 1369 1370 /* Init circular RX list. */ 1371 if (sis_list_rx_init(sc) == ENOBUFS) { 1372 printf("sis%d: initialization failed: no " 1373 "memory for rx buffers\n", sc->sis_unit); 1374 sis_stop(sc); 1375 SIS_UNLOCK(sc); 1376 return; 1377 } 1378 1379 /* 1380 * Init tx descriptors. 1381 */ 1382 sis_list_tx_init(sc); 1383 1384 /* 1385 * For the NatSemi chip, we have to explicitly enable the 1386 * reception of ARP frames, as well as turn on the 'perfect 1387 * match' filter where we store the station address, otherwise 1388 * we won't receive unicasts meant for this host. 1389 */ 1390 if (sc->sis_type == SIS_TYPE_83815) { 1391 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 1392 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 1393 } 1394 1395 /* If we want promiscuous mode, set the allframes bit. */ 1396 if (ifp->if_flags & IFF_PROMISC) { 1397 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1398 } else { 1399 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1400 } 1401 1402 /* 1403 * Set the capture broadcast bit to capture broadcast frames. 1404 */ 1405 if (ifp->if_flags & IFF_BROADCAST) { 1406 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1407 } else { 1408 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1409 } 1410 1411 /* 1412 * Load the multicast filter. 1413 */ 1414 if (sc->sis_type == SIS_TYPE_83815) 1415 sis_setmulti_ns(sc); 1416 else 1417 sis_setmulti_sis(sc); 1418 1419 /* Turn the receive filter on */ 1420 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 1421 1422 /* 1423 * Load the address of the RX and TX lists. 1424 */ 1425 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 1426 vtophys(&sc->sis_ldata->sis_rx_list[0])); 1427 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 1428 vtophys(&sc->sis_ldata->sis_tx_list[0])); 1429 1430 /* Set RX configuration */ 1431 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG); 1432 1433 /* Set TX configuration */ 1434 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 1435 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 1436 } else { 1437 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 1438 } 1439 1440 /* Set full/half duplex mode. */ 1441 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1442 SIS_SETBIT(sc, SIS_TX_CFG, 1443 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 1444 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 1445 } else { 1446 SIS_CLRBIT(sc, SIS_TX_CFG, 1447 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 1448 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 1449 } 1450 1451 /* 1452 * Enable interrupts. 1453 */ 1454 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 1455 CSR_WRITE_4(sc, SIS_IER, 1); 1456 1457 /* Enable receiver and transmitter. */ 1458 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 1459 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1460 1461#ifdef notdef 1462 mii_mediachg(mii); 1463#endif 1464 1465 /* 1466 * Page 75 of the DP83815 manual recommends the 1467 * following register settings "for optimum 1468 * performance." Note however that at least three 1469 * of the registers are listed as "reserved" in 1470 * the register map, so who knows what they do. 1471 */ 1472 if (sc->sis_type == SIS_TYPE_83815) { 1473 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 1474 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 1475 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 1476 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 1477 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 1478 } 1479 1480 ifp->if_flags |= IFF_RUNNING; 1481 ifp->if_flags &= ~IFF_OACTIVE; 1482 1483 sc->sis_stat_ch = timeout(sis_tick, sc, hz); 1484 1485 SIS_UNLOCK(sc); 1486 1487 return; 1488} 1489 1490/* 1491 * Set media options. 1492 */ 1493static int sis_ifmedia_upd(ifp) 1494 struct ifnet *ifp; 1495{ 1496 struct sis_softc *sc; 1497 struct mii_data *mii; 1498 1499 sc = ifp->if_softc; 1500 1501 mii = device_get_softc(sc->sis_miibus); 1502 sc->sis_link = 0; 1503 if (mii->mii_instance) { 1504 struct mii_softc *miisc; 1505 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1506 miisc = LIST_NEXT(miisc, mii_list)) 1507 mii_phy_reset(miisc); 1508 } 1509 mii_mediachg(mii); 1510 1511 return(0); 1512} 1513 1514/* 1515 * Report current media status. 1516 */ 1517static void sis_ifmedia_sts(ifp, ifmr) 1518 struct ifnet *ifp; 1519 struct ifmediareq *ifmr; 1520{ 1521 struct sis_softc *sc; 1522 struct mii_data *mii; 1523 1524 sc = ifp->if_softc; 1525 1526 mii = device_get_softc(sc->sis_miibus); 1527 mii_pollstat(mii); 1528 ifmr->ifm_active = mii->mii_media_active; 1529 ifmr->ifm_status = mii->mii_media_status; 1530 1531 return; 1532} 1533 1534static int sis_ioctl(ifp, command, data) 1535 struct ifnet *ifp; 1536 u_long command; 1537 caddr_t data; 1538{ 1539 struct sis_softc *sc = ifp->if_softc; 1540 struct ifreq *ifr = (struct ifreq *) data; 1541 struct mii_data *mii; 1542 int error = 0; 1543 1544 SIS_LOCK(sc); 1545 1546 switch(command) { 1547 case SIOCSIFADDR: 1548 case SIOCGIFADDR: 1549 case SIOCSIFMTU: 1550 error = ether_ioctl(ifp, command, data); 1551 break; 1552 case SIOCSIFFLAGS: 1553 if (ifp->if_flags & IFF_UP) { 1554 sis_init(sc); 1555 } else { 1556 if (ifp->if_flags & IFF_RUNNING) 1557 sis_stop(sc); 1558 } 1559 error = 0; 1560 break; 1561 case SIOCADDMULTI: 1562 case SIOCDELMULTI: 1563 if (sc->sis_type == SIS_TYPE_83815) 1564 sis_setmulti_ns(sc); 1565 else 1566 sis_setmulti_sis(sc); 1567 error = 0; 1568 break; 1569 case SIOCGIFMEDIA: 1570 case SIOCSIFMEDIA: 1571 mii = device_get_softc(sc->sis_miibus); 1572 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1573 break; 1574 default: 1575 error = EINVAL; 1576 break; 1577 } 1578 1579 SIS_UNLOCK(sc); 1580 1581 return(error); 1582} 1583 1584static void sis_watchdog(ifp) 1585 struct ifnet *ifp; 1586{ 1587 struct sis_softc *sc; 1588 1589 sc = ifp->if_softc; 1590 1591 SIS_LOCK(sc); 1592 1593 ifp->if_oerrors++; 1594 printf("sis%d: watchdog timeout\n", sc->sis_unit); 1595 1596 sis_stop(sc); 1597 sis_reset(sc); 1598 sis_init(sc); 1599 1600 if (ifp->if_snd.ifq_head != NULL) 1601 sis_start(ifp); 1602 1603 SIS_UNLOCK(sc); 1604 1605 return; 1606} 1607 1608/* 1609 * Stop the adapter and free any mbufs allocated to the 1610 * RX and TX lists. 1611 */ 1612static void sis_stop(sc) 1613 struct sis_softc *sc; 1614{ 1615 register int i; 1616 struct ifnet *ifp; 1617 1618 SIS_LOCK(sc); 1619 ifp = &sc->arpcom.ac_if; 1620 ifp->if_timer = 0; 1621 1622 untimeout(sis_tick, sc, sc->sis_stat_ch); 1623 CSR_WRITE_4(sc, SIS_IER, 0); 1624 CSR_WRITE_4(sc, SIS_IMR, 0); 1625 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 1626 DELAY(1000); 1627 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 1628 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 1629 1630 sc->sis_link = 0; 1631 1632 /* 1633 * Free data in the RX lists. 1634 */ 1635 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1636 if (sc->sis_ldata->sis_rx_list[i].sis_mbuf != NULL) { 1637 m_freem(sc->sis_ldata->sis_rx_list[i].sis_mbuf); 1638 sc->sis_ldata->sis_rx_list[i].sis_mbuf = NULL; 1639 } 1640 } 1641 bzero((char *)&sc->sis_ldata->sis_rx_list, 1642 sizeof(sc->sis_ldata->sis_rx_list)); 1643 1644 /* 1645 * Free the TX list buffers. 1646 */ 1647 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1648 if (sc->sis_ldata->sis_tx_list[i].sis_mbuf != NULL) { 1649 m_freem(sc->sis_ldata->sis_tx_list[i].sis_mbuf); 1650 sc->sis_ldata->sis_tx_list[i].sis_mbuf = NULL; 1651 } 1652 } 1653 1654 bzero((char *)&sc->sis_ldata->sis_tx_list, 1655 sizeof(sc->sis_ldata->sis_tx_list)); 1656 1657 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1658 1659 SIS_UNLOCK(sc); 1660 1661 return; 1662} 1663 1664/* 1665 * Stop all chip I/O so that the kernel's probe routines don't 1666 * get confused by errant DMAs when rebooting. 1667 */ 1668static void sis_shutdown(dev) 1669 device_t dev; 1670{ 1671 struct sis_softc *sc; 1672 1673 sc = device_get_softc(dev); 1674 SIS_LOCK(sc); 1675 sis_reset(sc); 1676 sis_stop(sc); 1677 SIS_UNLOCK(sc); 1678 1679 return; 1680} 1681