if_sis.c revision 64963
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_sis.c 64963 2000-08-22 23:26:51Z wpaul $ 33 */ 34 35/* 36 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 37 * available from http://www.sis.com.tw. 38 * 39 * This driver also supports the NatSemi DP83815. Datasheets are 40 * available from http://www.national.com. 41 * 42 * Written by Bill Paul <wpaul@ee.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47/* 48 * The SiS 900 is a fairly simple chip. It uses bus master DMA with 49 * simple TX and RX descriptors of 3 longwords in size. The receiver 50 * has a single perfect filter entry for the station address and a 51 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 52 * transceiver while the 7016 requires an external transceiver chip. 53 * Both chips offer the standard bit-bang MII interface as well as 54 * an enchanced PHY interface which simplifies accessing MII registers. 55 * 56 * The only downside to this chipset is that RX descriptors must be 57 * longword aligned. 58 */ 59 60#include <sys/param.h> 61#include <sys/systm.h> 62#include <sys/sockio.h> 63#include <sys/mbuf.h> 64#include <sys/malloc.h> 65#include <sys/kernel.h> 66#include <sys/socket.h> 67 68#include <net/if.h> 69#include <net/if_arp.h> 70#include <net/ethernet.h> 71#include <net/if_dl.h> 72#include <net/if_media.h> 73 74#include <net/bpf.h> 75 76#include <vm/vm.h> /* for vtophys */ 77#include <vm/pmap.h> /* for vtophys */ 78#include <machine/clock.h> /* for DELAY */ 79#include <machine/bus_pio.h> 80#include <machine/bus_memio.h> 81#include <machine/bus.h> 82#include <machine/resource.h> 83#include <sys/bus.h> 84#include <sys/rman.h> 85 86#include <dev/mii/mii.h> 87#include <dev/mii/miivar.h> 88 89#include <pci/pcireg.h> 90#include <pci/pcivar.h> 91 92#define SIS_USEIOSPACE 93 94#include <pci/if_sisreg.h> 95 96MODULE_DEPEND(sis, miibus, 1, 1, 1); 97 98/* "controller miibus0" required. See GENERIC if you get errors here. */ 99#include "miibus_if.h" 100 101#ifndef lint 102static const char rcsid[] = 103 "$FreeBSD: head/sys/pci/if_sis.c 64963 2000-08-22 23:26:51Z wpaul $"; 104#endif 105 106/* 107 * Various supported device vendors/types and their names. 108 */ 109static struct sis_type sis_devs[] = { 110 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 111 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 112 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP83815 10/100BaseTX" }, 113 { 0, 0, NULL } 114}; 115 116static int sis_probe __P((device_t)); 117static int sis_attach __P((device_t)); 118static int sis_detach __P((device_t)); 119 120static int sis_newbuf __P((struct sis_softc *, 121 struct sis_desc *, 122 struct mbuf *)); 123static int sis_encap __P((struct sis_softc *, 124 struct mbuf *, u_int32_t *)); 125static void sis_rxeof __P((struct sis_softc *)); 126static void sis_rxeoc __P((struct sis_softc *)); 127static void sis_txeof __P((struct sis_softc *)); 128static void sis_intr __P((void *)); 129static void sis_tick __P((void *)); 130static void sis_start __P((struct ifnet *)); 131static int sis_ioctl __P((struct ifnet *, u_long, caddr_t)); 132static void sis_init __P((void *)); 133static void sis_stop __P((struct sis_softc *)); 134static void sis_watchdog __P((struct ifnet *)); 135static void sis_shutdown __P((device_t)); 136static int sis_ifmedia_upd __P((struct ifnet *)); 137static void sis_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 138 139static u_int16_t sis_reverse __P((u_int16_t)); 140static void sis_delay __P((struct sis_softc *)); 141static void sis_eeprom_idle __P((struct sis_softc *)); 142static void sis_eeprom_putbyte __P((struct sis_softc *, int)); 143static void sis_eeprom_getword __P((struct sis_softc *, int, u_int16_t *)); 144static void sis_read_eeprom __P((struct sis_softc *, caddr_t, int, 145 int, int)); 146static int sis_miibus_readreg __P((device_t, int, int)); 147static int sis_miibus_writereg __P((device_t, int, int, int)); 148static void sis_miibus_statchg __P((device_t)); 149 150static void sis_setmulti_sis __P((struct sis_softc *)); 151static void sis_setmulti_ns __P((struct sis_softc *)); 152static u_int32_t sis_crc __P((struct sis_softc *, caddr_t)); 153static void sis_reset __P((struct sis_softc *)); 154static int sis_list_rx_init __P((struct sis_softc *)); 155static int sis_list_tx_init __P((struct sis_softc *)); 156 157#ifdef SIS_USEIOSPACE 158#define SIS_RES SYS_RES_IOPORT 159#define SIS_RID SIS_PCI_LOIO 160#else 161#define SIS_RES SYS_RES_MEMORY 162#define SIS_RID SIS_PCI_LOMEM 163#endif 164 165static device_method_t sis_methods[] = { 166 /* Device interface */ 167 DEVMETHOD(device_probe, sis_probe), 168 DEVMETHOD(device_attach, sis_attach), 169 DEVMETHOD(device_detach, sis_detach), 170 DEVMETHOD(device_shutdown, sis_shutdown), 171 172 /* bus interface */ 173 DEVMETHOD(bus_print_child, bus_generic_print_child), 174 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 175 176 /* MII interface */ 177 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 178 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 179 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 180 181 { 0, 0 } 182}; 183 184static driver_t sis_driver = { 185 "sis", 186 sis_methods, 187 sizeof(struct sis_softc) 188}; 189 190static devclass_t sis_devclass; 191 192DRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, 0, 0); 193DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 194 195#define SIS_SETBIT(sc, reg, x) \ 196 CSR_WRITE_4(sc, reg, \ 197 CSR_READ_4(sc, reg) | (x)) 198 199#define SIS_CLRBIT(sc, reg, x) \ 200 CSR_WRITE_4(sc, reg, \ 201 CSR_READ_4(sc, reg) & ~(x)) 202 203#define SIO_SET(x) \ 204 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 205 206#define SIO_CLR(x) \ 207 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 208 209/* 210 * Routine to reverse the bits in a word. Stolen almost 211 * verbatim from /usr/games/fortune. 212 */ 213static u_int16_t sis_reverse(n) 214 u_int16_t n; 215{ 216 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 217 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 218 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 219 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 220 221 return(n); 222} 223 224static void sis_delay(sc) 225 struct sis_softc *sc; 226{ 227 int idx; 228 229 for (idx = (300 / 33) + 1; idx > 0; idx--) 230 CSR_READ_4(sc, SIS_CSR); 231 232 return; 233} 234 235static void sis_eeprom_idle(sc) 236 struct sis_softc *sc; 237{ 238 register int i; 239 240 SIO_SET(SIS_EECTL_CSEL); 241 sis_delay(sc); 242 SIO_SET(SIS_EECTL_CLK); 243 sis_delay(sc); 244 245 for (i = 0; i < 25; i++) { 246 SIO_CLR(SIS_EECTL_CLK); 247 sis_delay(sc); 248 SIO_SET(SIS_EECTL_CLK); 249 sis_delay(sc); 250 } 251 252 SIO_CLR(SIS_EECTL_CLK); 253 sis_delay(sc); 254 SIO_CLR(SIS_EECTL_CSEL); 255 sis_delay(sc); 256 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 257 258 return; 259} 260 261/* 262 * Send a read command and address to the EEPROM, check for ACK. 263 */ 264static void sis_eeprom_putbyte(sc, addr) 265 struct sis_softc *sc; 266 int addr; 267{ 268 register int d, i; 269 270 d = addr | SIS_EECMD_READ; 271 272 /* 273 * Feed in each bit and stobe the clock. 274 */ 275 for (i = 0x400; i; i >>= 1) { 276 if (d & i) { 277 SIO_SET(SIS_EECTL_DIN); 278 } else { 279 SIO_CLR(SIS_EECTL_DIN); 280 } 281 sis_delay(sc); 282 SIO_SET(SIS_EECTL_CLK); 283 sis_delay(sc); 284 SIO_CLR(SIS_EECTL_CLK); 285 sis_delay(sc); 286 } 287 288 return; 289} 290 291/* 292 * Read a word of data stored in the EEPROM at address 'addr.' 293 */ 294static void sis_eeprom_getword(sc, addr, dest) 295 struct sis_softc *sc; 296 int addr; 297 u_int16_t *dest; 298{ 299 register int i; 300 u_int16_t word = 0; 301 302 /* Force EEPROM to idle state. */ 303 sis_eeprom_idle(sc); 304 305 /* Enter EEPROM access mode. */ 306 sis_delay(sc); 307 SIO_CLR(SIS_EECTL_CLK); 308 sis_delay(sc); 309 SIO_SET(SIS_EECTL_CSEL); 310 sis_delay(sc); 311 312 /* 313 * Send address of word we want to read. 314 */ 315 sis_eeprom_putbyte(sc, addr); 316 317 /* 318 * Start reading bits from EEPROM. 319 */ 320 for (i = 0x8000; i; i >>= 1) { 321 SIO_SET(SIS_EECTL_CLK); 322 sis_delay(sc); 323 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 324 word |= i; 325 sis_delay(sc); 326 SIO_CLR(SIS_EECTL_CLK); 327 sis_delay(sc); 328 } 329 330 /* Turn off EEPROM access mode. */ 331 sis_eeprom_idle(sc); 332 333 *dest = word; 334 335 return; 336} 337 338/* 339 * Read a sequence of words from the EEPROM. 340 */ 341static void sis_read_eeprom(sc, dest, off, cnt, swap) 342 struct sis_softc *sc; 343 caddr_t dest; 344 int off; 345 int cnt; 346 int swap; 347{ 348 int i; 349 u_int16_t word = 0, *ptr; 350 351 for (i = 0; i < cnt; i++) { 352 sis_eeprom_getword(sc, off + i, &word); 353 ptr = (u_int16_t *)(dest + (i * 2)); 354 if (swap) 355 *ptr = ntohs(word); 356 else 357 *ptr = word; 358 } 359 360 return; 361} 362 363static int sis_miibus_readreg(dev, phy, reg) 364 device_t dev; 365 int phy, reg; 366{ 367 struct sis_softc *sc; 368 int i, val = 0; 369 370 sc = device_get_softc(dev); 371 372 if (sc->sis_type == SIS_TYPE_83815) { 373 if (phy != 0) 374 return(0); 375 /* 376 * The NatSemi chip can take a while after 377 * a reset to come ready, during which the BMSR 378 * returns a value of 0. This is *never* supposed 379 * to happen: some of the BMSR bits are meant to 380 * be hardwired in the on position, and this can 381 * confuse the miibus code a bit during the probe 382 * and attach phase. So we make an effort to check 383 * for this condition and wait for it to clear. 384 */ 385 if (!CSR_READ_4(sc, NS_BMSR)) 386 DELAY(1000); 387 val = CSR_READ_4(sc, NS_BMCR + (reg * 4)); 388 return(val); 389 } 390 391 if (sc->sis_type == SIS_TYPE_900 && phy != 0) 392 return(0); 393 394 CSR_WRITE_4(sc, SIS_PHYCTL, (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 395 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 396 397 for (i = 0; i < SIS_TIMEOUT; i++) { 398 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 399 break; 400 } 401 402 if (i == SIS_TIMEOUT) { 403 printf("sis%d: PHY failed to come ready\n", sc->sis_unit); 404 return(0); 405 } 406 407 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 408 409 if (val == 0xFFFF) 410 return(0); 411 412 return(val); 413} 414 415static int sis_miibus_writereg(dev, phy, reg, data) 416 device_t dev; 417 int phy, reg, data; 418{ 419 struct sis_softc *sc; 420 int i; 421 422 sc = device_get_softc(dev); 423 424 if (sc->sis_type == SIS_TYPE_83815) { 425 if (phy != 0) 426 return(0); 427 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 428 return(0); 429 } 430 431 if (sc->sis_type == SIS_TYPE_900 && phy != 0) 432 return(0); 433 434 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 435 (reg << 6) | SIS_PHYOP_WRITE); 436 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 437 438 for (i = 0; i < SIS_TIMEOUT; i++) { 439 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 440 break; 441 } 442 443 if (i == SIS_TIMEOUT) 444 printf("sis%d: PHY failed to come ready\n", sc->sis_unit); 445 446 return(0); 447} 448 449static void sis_miibus_statchg(dev) 450 device_t dev; 451{ 452 struct sis_softc *sc; 453 454 sc = device_get_softc(dev); 455 sis_init(sc); 456 457 return; 458} 459 460static u_int32_t sis_crc(sc, addr) 461 struct sis_softc *sc; 462 caddr_t addr; 463{ 464 u_int32_t crc, carry; 465 int i, j; 466 u_int8_t c; 467 468 /* Compute CRC for the address value. */ 469 crc = 0xFFFFFFFF; /* initial value */ 470 471 for (i = 0; i < 6; i++) { 472 c = *(addr + i); 473 for (j = 0; j < 8; j++) { 474 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 475 crc <<= 1; 476 c >>= 1; 477 if (carry) 478 crc = (crc ^ 0x04c11db6) | carry; 479 } 480 } 481 482 /* 483 * return the filter bit position 484 * 485 * The NatSemi chip has a 512-bit filter, which is 486 * different than the SiS, so we special-case it. 487 */ 488 if (sc->sis_type == SIS_TYPE_83815) 489 return((crc >> 23) & 0x1FF); 490 491 return((crc >> 25) & 0x0000007F); 492} 493 494static void sis_setmulti_ns(sc) 495 struct sis_softc *sc; 496{ 497 struct ifnet *ifp; 498 struct ifmultiaddr *ifma; 499 u_int32_t h = 0, i, filtsave; 500 int bit, index; 501 502 ifp = &sc->arpcom.ac_if; 503 504 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 505 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 506 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 507 return; 508 } 509 510 /* 511 * We have to explicitly enable the multicast hash table 512 * on the NatSemi chip if we want to use it, which we do. 513 */ 514 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 515 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 516 517 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 518 519 /* first, zot all the existing hash bits */ 520 for (i = 0; i < 32; i++) { 521 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 522 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 523 } 524 525 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 526 ifma = ifma->ifma_link.le_next) { 527 if (ifma->ifma_addr->sa_family != AF_LINK) 528 continue; 529 h = sis_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 530 index = h >> 3; 531 bit = h & 0x1F; 532 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 533 if (bit > 0xF) 534 bit -= 0x10; 535 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 536 } 537 538 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 539 540 return; 541} 542 543static void sis_setmulti_sis(sc) 544 struct sis_softc *sc; 545{ 546 struct ifnet *ifp; 547 struct ifmultiaddr *ifma; 548 u_int32_t h = 0, i, filtsave; 549 550 ifp = &sc->arpcom.ac_if; 551 552 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 553 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 554 return; 555 } 556 557 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 558 559 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 560 561 /* first, zot all the existing hash bits */ 562 for (i = 0; i < 8; i++) { 563 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + ((i * 16) >> 4)) << 16); 564 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 565 } 566 567 /* now program new ones */ 568 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 569 ifma = ifma->ifma_link.le_next) { 570 if (ifma->ifma_addr->sa_family != AF_LINK) 571 continue; 572 h = sis_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 573 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + (h >> 4)) << 16); 574 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << (h & 0xF))); 575 } 576 577 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 578 579 return; 580} 581 582static void sis_reset(sc) 583 struct sis_softc *sc; 584{ 585 register int i; 586 587 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 588 589 for (i = 0; i < SIS_TIMEOUT; i++) { 590 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 591 break; 592 } 593 594 if (i == SIS_TIMEOUT) 595 printf("sis%d: reset never completed\n", sc->sis_unit); 596 597 /* Wait a little while for the chip to get its brains in order. */ 598 DELAY(1000); 599 return; 600} 601 602/* 603 * Probe for an SiS chip. Check the PCI vendor and device 604 * IDs against our list and return a device name if we find a match. 605 */ 606static int sis_probe(dev) 607 device_t dev; 608{ 609 struct sis_type *t; 610 611 t = sis_devs; 612 613 while(t->sis_name != NULL) { 614 if ((pci_get_vendor(dev) == t->sis_vid) && 615 (pci_get_device(dev) == t->sis_did)) { 616 device_set_desc(dev, t->sis_name); 617 return(0); 618 } 619 t++; 620 } 621 622 return(ENXIO); 623} 624 625/* 626 * Attach the interface. Allocate softc structures, do ifmedia 627 * setup and ethernet/BPF attach. 628 */ 629static int sis_attach(dev) 630 device_t dev; 631{ 632 int s; 633 u_char eaddr[ETHER_ADDR_LEN]; 634 u_int32_t command; 635 struct sis_softc *sc; 636 struct ifnet *ifp; 637 int unit, error = 0, rid; 638 639 s = splimp(); 640 641 sc = device_get_softc(dev); 642 unit = device_get_unit(dev); 643 bzero(sc, sizeof(struct sis_softc)); 644 645 if (pci_get_device(dev) == SIS_DEVICEID_900) 646 sc->sis_type = SIS_TYPE_900; 647 if (pci_get_device(dev) == SIS_DEVICEID_7016) 648 sc->sis_type = SIS_TYPE_7016; 649 if (pci_get_vendor(dev) == NS_VENDORID) 650 sc->sis_type = SIS_TYPE_83815; 651 652 /* 653 * Handle power management nonsense. 654 */ 655 656 command = pci_read_config(dev, SIS_PCI_CAPID, 4) & 0x000000FF; 657 if (command == 0x01) { 658 659 command = pci_read_config(dev, SIS_PCI_PWRMGMTCTRL, 4); 660 if (command & SIS_PSTATE_MASK) { 661 u_int32_t iobase, membase, irq; 662 663 /* Save important PCI config data. */ 664 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4); 665 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4); 666 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4); 667 668 /* Reset the power state. */ 669 printf("sis%d: chip is in D%d power mode " 670 "-- setting to D0\n", unit, command & SIS_PSTATE_MASK); 671 command &= 0xFFFFFFFC; 672 pci_write_config(dev, SIS_PCI_PWRMGMTCTRL, command, 4); 673 674 /* Restore PCI config data. */ 675 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4); 676 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4); 677 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4); 678 } 679 } 680 681 /* 682 * Map control/status registers. 683 */ 684 command = pci_read_config(dev, PCIR_COMMAND, 4); 685 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 686 pci_write_config(dev, PCIR_COMMAND, command, 4); 687 command = pci_read_config(dev, PCIR_COMMAND, 4); 688 689#ifdef SIS_USEIOSPACE 690 if (!(command & PCIM_CMD_PORTEN)) { 691 printf("sis%d: failed to enable I/O ports!\n", unit); 692 error = ENXIO;; 693 goto fail; 694 } 695#else 696 if (!(command & PCIM_CMD_MEMEN)) { 697 printf("sis%d: failed to enable memory mapping!\n", unit); 698 error = ENXIO;; 699 goto fail; 700 } 701#endif 702 703 rid = SIS_RID; 704 sc->sis_res = bus_alloc_resource(dev, SIS_RES, &rid, 705 0, ~0, 1, RF_ACTIVE); 706 707 if (sc->sis_res == NULL) { 708 printf("sis%d: couldn't map ports/memory\n", unit); 709 error = ENXIO; 710 goto fail; 711 } 712 713 sc->sis_btag = rman_get_bustag(sc->sis_res); 714 sc->sis_bhandle = rman_get_bushandle(sc->sis_res); 715 716 /* Allocate interrupt */ 717 rid = 0; 718 sc->sis_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 719 RF_SHAREABLE | RF_ACTIVE); 720 721 if (sc->sis_irq == NULL) { 722 printf("sis%d: couldn't map interrupt\n", unit); 723 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 724 error = ENXIO; 725 goto fail; 726 } 727 728 error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET, 729 sis_intr, sc, &sc->sis_intrhand); 730 731 if (error) { 732 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_res); 733 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 734 printf("sis%d: couldn't set up irq\n", unit); 735 goto fail; 736 } 737 738 /* Reset the adapter. */ 739 sis_reset(sc); 740 741 /* 742 * Get station address from the EEPROM. 743 */ 744 switch (pci_get_vendor(dev)) { 745 case NS_VENDORID: 746 /* 747 * Reading the MAC address out of the EEPROM on 748 * the NatSemi chip takes a bit more work than 749 * you'd expect. The address spans 4 16-bit words, 750 * with the first word containing only a single bit. 751 * You have to shift everything over one bit to 752 * get it aligned properly. Also, the bits are 753 * stored backwards (the LSB is really the MSB, 754 * and so on) so you have to reverse them in order 755 * to get the MAC address into the form we want. 756 * Why? Who the hell knows. 757 */ 758 { 759 u_int16_t tmp[4]; 760 761 sis_read_eeprom(sc, (caddr_t)&tmp, 762 NS_EE_NODEADDR, 4, 0); 763 764 /* Shift everything over one bit. */ 765 tmp[3] = tmp[3] >> 1; 766 tmp[3] |= tmp[2] << 15; 767 tmp[2] = tmp[2] >> 1; 768 tmp[2] |= tmp[1] << 15; 769 tmp[1] = tmp[1] >> 1; 770 tmp[1] |= tmp[0] << 15; 771 772 /* Now reverse all the bits. */ 773 tmp[3] = sis_reverse(tmp[3]); 774 tmp[2] = sis_reverse(tmp[2]); 775 tmp[1] = sis_reverse(tmp[1]); 776 777 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); 778 } 779 break; 780 case SIS_VENDORID: 781 default: 782 sis_read_eeprom(sc, (caddr_t)&eaddr, SIS_EE_NODEADDR, 3, 0); 783 break; 784 } 785 786 /* 787 * A SiS chip was detected. Inform the world. 788 */ 789 printf("sis%d: Ethernet address: %6D\n", unit, eaddr, ":"); 790 791 sc->sis_unit = unit; 792 callout_handle_init(&sc->sis_stat_ch); 793 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 794 795 sc->sis_ldata = contigmalloc(sizeof(struct sis_list_data), M_DEVBUF, 796 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 797 798 if (sc->sis_ldata == NULL) { 799 printf("sis%d: no memory for list buffers!\n", unit); 800 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 801 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 802 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 803 error = ENXIO; 804 goto fail; 805 } 806 bzero(sc->sis_ldata, sizeof(struct sis_list_data)); 807 808 ifp = &sc->arpcom.ac_if; 809 ifp->if_softc = sc; 810 ifp->if_unit = unit; 811 ifp->if_name = "sis"; 812 ifp->if_mtu = ETHERMTU; 813 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 814 ifp->if_ioctl = sis_ioctl; 815 ifp->if_output = ether_output; 816 ifp->if_start = sis_start; 817 ifp->if_watchdog = sis_watchdog; 818 ifp->if_init = sis_init; 819 ifp->if_baudrate = 10000000; 820 ifp->if_snd.ifq_maxlen = SIS_TX_LIST_CNT - 1; 821 822 /* 823 * Do MII setup. 824 */ 825 if (mii_phy_probe(dev, &sc->sis_miibus, 826 sis_ifmedia_upd, sis_ifmedia_sts)) { 827 printf("sis%d: MII without any PHY!\n", sc->sis_unit); 828 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 829 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 830 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 831 error = ENXIO; 832 goto fail; 833 } 834 835 /* 836 * Call MI attach routine. 837 */ 838 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 839 callout_handle_init(&sc->sis_stat_ch); 840 841fail: 842 splx(s); 843 return(error); 844} 845 846static int sis_detach(dev) 847 device_t dev; 848{ 849 struct sis_softc *sc; 850 struct ifnet *ifp; 851 int s; 852 853 s = splimp(); 854 855 sc = device_get_softc(dev); 856 ifp = &sc->arpcom.ac_if; 857 858 sis_reset(sc); 859 sis_stop(sc); 860 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 861 862 bus_generic_detach(dev); 863 device_delete_child(dev, sc->sis_miibus); 864 865 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 866 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 867 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 868 869 contigfree(sc->sis_ldata, sizeof(struct sis_list_data), M_DEVBUF); 870 871 splx(s); 872 873 return(0); 874} 875 876/* 877 * Initialize the transmit descriptors. 878 */ 879static int sis_list_tx_init(sc) 880 struct sis_softc *sc; 881{ 882 struct sis_list_data *ld; 883 struct sis_ring_data *cd; 884 int i; 885 886 cd = &sc->sis_cdata; 887 ld = sc->sis_ldata; 888 889 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 890 if (i == (SIS_TX_LIST_CNT - 1)) { 891 ld->sis_tx_list[i].sis_nextdesc = 892 &ld->sis_tx_list[0]; 893 ld->sis_tx_list[i].sis_next = 894 vtophys(&ld->sis_tx_list[0]); 895 } else { 896 ld->sis_tx_list[i].sis_nextdesc = 897 &ld->sis_tx_list[i + 1]; 898 ld->sis_tx_list[i].sis_next = 899 vtophys(&ld->sis_tx_list[i + 1]); 900 } 901 ld->sis_tx_list[i].sis_mbuf = NULL; 902 ld->sis_tx_list[i].sis_ptr = 0; 903 ld->sis_tx_list[i].sis_ctl = 0; 904 } 905 906 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0; 907 908 return(0); 909} 910 911 912/* 913 * Initialize the RX descriptors and allocate mbufs for them. Note that 914 * we arrange the descriptors in a closed ring, so that the last descriptor 915 * points back to the first. 916 */ 917static int sis_list_rx_init(sc) 918 struct sis_softc *sc; 919{ 920 struct sis_list_data *ld; 921 struct sis_ring_data *cd; 922 int i; 923 924 ld = sc->sis_ldata; 925 cd = &sc->sis_cdata; 926 927 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 928 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS) 929 return(ENOBUFS); 930 if (i == (SIS_RX_LIST_CNT - 1)) { 931 ld->sis_rx_list[i].sis_nextdesc = 932 &ld->sis_rx_list[0]; 933 ld->sis_rx_list[i].sis_next = 934 vtophys(&ld->sis_rx_list[0]); 935 } else { 936 ld->sis_rx_list[i].sis_nextdesc = 937 &ld->sis_rx_list[i + 1]; 938 ld->sis_rx_list[i].sis_next = 939 vtophys(&ld->sis_rx_list[i + 1]); 940 } 941 } 942 943 cd->sis_rx_prod = 0; 944 945 return(0); 946} 947 948/* 949 * Initialize an RX descriptor and attach an MBUF cluster. 950 */ 951static int sis_newbuf(sc, c, m) 952 struct sis_softc *sc; 953 struct sis_desc *c; 954 struct mbuf *m; 955{ 956 struct mbuf *m_new = NULL; 957 958 if (m == NULL) { 959 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 960 if (m_new == NULL) { 961 printf("sis%d: no memory for rx list " 962 "-- packet dropped!\n", sc->sis_unit); 963 return(ENOBUFS); 964 } 965 966 MCLGET(m_new, M_DONTWAIT); 967 if (!(m_new->m_flags & M_EXT)) { 968 printf("sis%d: no memory for rx list " 969 "-- packet dropped!\n", sc->sis_unit); 970 m_freem(m_new); 971 return(ENOBUFS); 972 } 973 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 974 } else { 975 m_new = m; 976 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 977 m_new->m_data = m_new->m_ext.ext_buf; 978 } 979 980 m_adj(m_new, sizeof(u_int64_t)); 981 982 c->sis_mbuf = m_new; 983 c->sis_ptr = vtophys(mtod(m_new, caddr_t)); 984 c->sis_ctl = SIS_RXLEN; 985 986 return(0); 987} 988 989/* 990 * A frame has been uploaded: pass the resulting mbuf chain up to 991 * the higher level protocols. 992 */ 993static void sis_rxeof(sc) 994 struct sis_softc *sc; 995{ 996 struct ether_header *eh; 997 struct mbuf *m; 998 struct ifnet *ifp; 999 struct sis_desc *cur_rx; 1000 int i, total_len = 0; 1001 u_int32_t rxstat; 1002 1003 ifp = &sc->arpcom.ac_if; 1004 i = sc->sis_cdata.sis_rx_prod; 1005 1006 while(SIS_OWNDESC(&sc->sis_ldata->sis_rx_list[i])) { 1007 struct mbuf *m0 = NULL; 1008 1009 cur_rx = &sc->sis_ldata->sis_rx_list[i]; 1010 rxstat = cur_rx->sis_rxstat; 1011 m = cur_rx->sis_mbuf; 1012 cur_rx->sis_mbuf = NULL; 1013 total_len = SIS_RXBYTES(cur_rx); 1014 SIS_INC(i, SIS_RX_LIST_CNT); 1015 1016 /* 1017 * If an error occurs, update stats, clear the 1018 * status word and leave the mbuf cluster in place: 1019 * it should simply get re-used next time this descriptor 1020 * comes up in the ring. 1021 */ 1022 if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 1023 ifp->if_ierrors++; 1024 if (rxstat & SIS_RXSTAT_COLL) 1025 ifp->if_collisions++; 1026 sis_newbuf(sc, cur_rx, m); 1027 continue; 1028 } 1029 1030 /* No errors; receive the packet. */ 1031 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1032 total_len + ETHER_ALIGN, 0, ifp, NULL); 1033 sis_newbuf(sc, cur_rx, m); 1034 if (m0 == NULL) { 1035 ifp->if_ierrors++; 1036 continue; 1037 } 1038 m_adj(m0, ETHER_ALIGN); 1039 m = m0; 1040 1041 ifp->if_ipackets++; 1042 eh = mtod(m, struct ether_header *); 1043 1044 /* Remove header from mbuf and pass it on. */ 1045 m_adj(m, sizeof(struct ether_header)); 1046 ether_input(ifp, eh, m); 1047 } 1048 1049 sc->sis_cdata.sis_rx_prod = i; 1050 1051 return; 1052} 1053 1054void sis_rxeoc(sc) 1055 struct sis_softc *sc; 1056{ 1057 sis_rxeof(sc); 1058 sis_init(sc); 1059 return; 1060} 1061 1062/* 1063 * A frame was downloaded to the chip. It's safe for us to clean up 1064 * the list buffers. 1065 */ 1066 1067static void sis_txeof(sc) 1068 struct sis_softc *sc; 1069{ 1070 struct sis_desc *cur_tx = NULL; 1071 struct ifnet *ifp; 1072 u_int32_t idx; 1073 1074 ifp = &sc->arpcom.ac_if; 1075 1076 /* Clear the timeout timer. */ 1077 ifp->if_timer = 0; 1078 1079 /* 1080 * Go through our tx list and free mbufs for those 1081 * frames that have been transmitted. 1082 */ 1083 idx = sc->sis_cdata.sis_tx_cons; 1084 while (idx != sc->sis_cdata.sis_tx_prod) { 1085 cur_tx = &sc->sis_ldata->sis_tx_list[idx]; 1086 1087 if (SIS_OWNDESC(cur_tx)) 1088 break; 1089 1090 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) { 1091 sc->sis_cdata.sis_tx_cnt--; 1092 SIS_INC(idx, SIS_TX_LIST_CNT); 1093 continue; 1094 } 1095 1096 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 1097 ifp->if_oerrors++; 1098 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 1099 ifp->if_collisions++; 1100 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 1101 ifp->if_collisions++; 1102 } 1103 1104 ifp->if_collisions += 1105 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 1106 1107 ifp->if_opackets++; 1108 if (cur_tx->sis_mbuf != NULL) { 1109 m_freem(cur_tx->sis_mbuf); 1110 cur_tx->sis_mbuf = NULL; 1111 } 1112 1113 sc->sis_cdata.sis_tx_cnt--; 1114 SIS_INC(idx, SIS_TX_LIST_CNT); 1115 ifp->if_timer = 0; 1116 } 1117 1118 sc->sis_cdata.sis_tx_cons = idx; 1119 1120 if (cur_tx != NULL) 1121 ifp->if_flags &= ~IFF_OACTIVE; 1122 1123 return; 1124} 1125 1126static void sis_tick(xsc) 1127 void *xsc; 1128{ 1129 struct sis_softc *sc; 1130 struct mii_data *mii; 1131 struct ifnet *ifp; 1132 int s; 1133 1134 s = splimp(); 1135 1136 sc = xsc; 1137 ifp = &sc->arpcom.ac_if; 1138 1139 mii = device_get_softc(sc->sis_miibus); 1140 mii_tick(mii); 1141 1142 if (!sc->sis_link) { 1143 mii_pollstat(mii); 1144 if (mii->mii_media_status & IFM_ACTIVE && 1145 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1146 sc->sis_link++; 1147 if (ifp->if_snd.ifq_head != NULL) 1148 sis_start(ifp); 1149 } 1150 1151 sc->sis_stat_ch = timeout(sis_tick, sc, hz); 1152 1153 splx(s); 1154 1155 return; 1156} 1157 1158static void sis_intr(arg) 1159 void *arg; 1160{ 1161 struct sis_softc *sc; 1162 struct ifnet *ifp; 1163 u_int32_t status; 1164 1165 sc = arg; 1166 ifp = &sc->arpcom.ac_if; 1167 1168 /* Supress unwanted interrupts */ 1169 if (!(ifp->if_flags & IFF_UP)) { 1170 sis_stop(sc); 1171 return; 1172 } 1173 1174 /* Disable interrupts. */ 1175 CSR_WRITE_4(sc, SIS_IER, 0); 1176 1177 for (;;) { 1178 /* Reading the ISR register clears all interrupts. */ 1179 status = CSR_READ_4(sc, SIS_ISR); 1180 1181 if ((status & SIS_INTRS) == 0) 1182 break; 1183 1184 if ((status & SIS_ISR_TX_DESC_OK) || 1185 (status & SIS_ISR_TX_ERR) || 1186 (status & SIS_ISR_TX_OK) || 1187 (status & SIS_ISR_TX_IDLE)) 1188 sis_txeof(sc); 1189 1190 if ((status & SIS_ISR_RX_DESC_OK) || 1191 (status & SIS_ISR_RX_OK)) 1192 sis_rxeof(sc); 1193 1194 if ((status & SIS_ISR_RX_ERR) || 1195 (status & SIS_ISR_RX_OFLOW)) { 1196 sis_rxeoc(sc); 1197 } 1198 1199 if (status & SIS_ISR_SYSERR) { 1200 sis_reset(sc); 1201 sis_init(sc); 1202 } 1203 } 1204 1205 /* Re-enable interrupts. */ 1206 CSR_WRITE_4(sc, SIS_IER, 1); 1207 1208 if (ifp->if_snd.ifq_head != NULL) 1209 sis_start(ifp); 1210 1211 return; 1212} 1213 1214/* 1215 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1216 * pointers to the fragment pointers. 1217 */ 1218static int sis_encap(sc, m_head, txidx) 1219 struct sis_softc *sc; 1220 struct mbuf *m_head; 1221 u_int32_t *txidx; 1222{ 1223 struct sis_desc *f = NULL; 1224 struct mbuf *m; 1225 int frag, cur, cnt = 0; 1226 1227 /* 1228 * Start packing the mbufs in this chain into 1229 * the fragment pointers. Stop when we run out 1230 * of fragments or hit the end of the mbuf chain. 1231 */ 1232 m = m_head; 1233 cur = frag = *txidx; 1234 1235 for (m = m_head; m != NULL; m = m->m_next) { 1236 if (m->m_len != 0) { 1237 if ((SIS_TX_LIST_CNT - 1238 (sc->sis_cdata.sis_tx_cnt + cnt)) < 2) 1239 return(ENOBUFS); 1240 f = &sc->sis_ldata->sis_tx_list[frag]; 1241 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; 1242 f->sis_ptr = vtophys(mtod(m, vm_offset_t)); 1243 if (cnt != 0) 1244 f->sis_ctl |= SIS_CMDSTS_OWN; 1245 cur = frag; 1246 SIS_INC(frag, SIS_TX_LIST_CNT); 1247 cnt++; 1248 } 1249 } 1250 1251 if (m != NULL) 1252 return(ENOBUFS); 1253 1254 sc->sis_ldata->sis_tx_list[cur].sis_mbuf = m_head; 1255 sc->sis_ldata->sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1256 sc->sis_ldata->sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1257 sc->sis_cdata.sis_tx_cnt += cnt; 1258 *txidx = frag; 1259 1260 return(0); 1261} 1262 1263/* 1264 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1265 * to the mbuf data regions directly in the transmit lists. We also save a 1266 * copy of the pointers since the transmit list fragment pointers are 1267 * physical addresses. 1268 */ 1269 1270static void sis_start(ifp) 1271 struct ifnet *ifp; 1272{ 1273 struct sis_softc *sc; 1274 struct mbuf *m_head = NULL; 1275 u_int32_t idx; 1276 1277 sc = ifp->if_softc; 1278 1279 if (!sc->sis_link) 1280 return; 1281 1282 idx = sc->sis_cdata.sis_tx_prod; 1283 1284 if (ifp->if_flags & IFF_OACTIVE) 1285 return; 1286 1287 while(sc->sis_ldata->sis_tx_list[idx].sis_mbuf == NULL) { 1288 IF_DEQUEUE(&ifp->if_snd, m_head); 1289 if (m_head == NULL) 1290 break; 1291 1292 if (sis_encap(sc, m_head, &idx)) { 1293 IF_PREPEND(&ifp->if_snd, m_head); 1294 ifp->if_flags |= IFF_OACTIVE; 1295 break; 1296 } 1297 1298 /* 1299 * If there's a BPF listener, bounce a copy of this frame 1300 * to him. 1301 */ 1302 if (ifp->if_bpf) 1303 bpf_mtap(ifp, m_head); 1304 1305 } 1306 1307 /* Transmit */ 1308 sc->sis_cdata.sis_tx_prod = idx; 1309 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 1310 1311 /* 1312 * Set a timeout in case the chip goes out to lunch. 1313 */ 1314 ifp->if_timer = 5; 1315 1316 return; 1317} 1318 1319static void sis_init(xsc) 1320 void *xsc; 1321{ 1322 struct sis_softc *sc = xsc; 1323 struct ifnet *ifp = &sc->arpcom.ac_if; 1324 struct mii_data *mii; 1325 int s; 1326 1327 s = splimp(); 1328 1329 /* 1330 * Cancel pending I/O and free all RX/TX buffers. 1331 */ 1332 sis_stop(sc); 1333 1334 mii = device_get_softc(sc->sis_miibus); 1335 1336 /* Set MAC address */ 1337 if (sc->sis_type == SIS_TYPE_83815) { 1338 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 1339 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1340 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1341 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 1342 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1343 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1344 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 1345 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1346 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1347 } else { 1348 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 1349 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1350 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1351 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 1352 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1353 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1354 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 1355 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1356 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1357 } 1358 1359 /* Init circular RX list. */ 1360 if (sis_list_rx_init(sc) == ENOBUFS) { 1361 printf("sis%d: initialization failed: no " 1362 "memory for rx buffers\n", sc->sis_unit); 1363 sis_stop(sc); 1364 (void)splx(s); 1365 return; 1366 } 1367 1368 /* 1369 * Init tx descriptors. 1370 */ 1371 sis_list_tx_init(sc); 1372 1373 /* 1374 * For the NatSemi chip, we have to explicitly enable the 1375 * reception of ARP frames, as well as turn on the 'perfect 1376 * match' filter where we store the station address, otherwise 1377 * we won't receive unicasts meant for this host. 1378 */ 1379 if (sc->sis_type == SIS_TYPE_83815) { 1380 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 1381 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 1382 } 1383 1384 /* If we want promiscuous mode, set the allframes bit. */ 1385 if (ifp->if_flags & IFF_PROMISC) { 1386 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1387 } else { 1388 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1389 } 1390 1391 /* 1392 * Set the capture broadcast bit to capture broadcast frames. 1393 */ 1394 if (ifp->if_flags & IFF_BROADCAST) { 1395 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1396 } else { 1397 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1398 } 1399 1400 /* 1401 * Load the multicast filter. 1402 */ 1403 if (sc->sis_type == SIS_TYPE_83815) 1404 sis_setmulti_ns(sc); 1405 else 1406 sis_setmulti_sis(sc); 1407 1408 /* Turn the receive filter on */ 1409 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 1410 1411 /* 1412 * Load the address of the RX and TX lists. 1413 */ 1414 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 1415 vtophys(&sc->sis_ldata->sis_rx_list[0])); 1416 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 1417 vtophys(&sc->sis_ldata->sis_tx_list[0])); 1418 1419 /* Set RX configuration */ 1420 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG); 1421 1422 /* Set TX configuration */ 1423 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 1424 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 1425 } else { 1426 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 1427 } 1428 1429 /* Set full/half duplex mode. */ 1430 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1431 SIS_SETBIT(sc, SIS_TX_CFG, 1432 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 1433 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 1434 } else { 1435 SIS_CLRBIT(sc, SIS_TX_CFG, 1436 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 1437 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 1438 } 1439 1440 /* 1441 * Enable interrupts. 1442 */ 1443 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 1444 CSR_WRITE_4(sc, SIS_IER, 1); 1445 1446 /* Enable receiver and transmitter. */ 1447 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 1448 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1449 1450#ifdef notdef 1451 mii_mediachg(mii); 1452#endif 1453 1454 /* 1455 * Page 75 of the DP83815 manual recommends the 1456 * following register settings "for optimum 1457 * performance." Note however that at least three 1458 * of the registers are listed as "reserved" in 1459 * the register map, so who knows what they do. 1460 */ 1461 if (sc->sis_type == SIS_TYPE_83815) { 1462 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 1463 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 1464 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 1465 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 1466 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 1467 } 1468 1469 ifp->if_flags |= IFF_RUNNING; 1470 ifp->if_flags &= ~IFF_OACTIVE; 1471 1472 (void)splx(s); 1473 1474 sc->sis_stat_ch = timeout(sis_tick, sc, hz); 1475 1476 return; 1477} 1478 1479/* 1480 * Set media options. 1481 */ 1482static int sis_ifmedia_upd(ifp) 1483 struct ifnet *ifp; 1484{ 1485 struct sis_softc *sc; 1486 struct mii_data *mii; 1487 1488 sc = ifp->if_softc; 1489 1490 mii = device_get_softc(sc->sis_miibus); 1491 sc->sis_link = 0; 1492 if (mii->mii_instance) { 1493 struct mii_softc *miisc; 1494 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1495 miisc = LIST_NEXT(miisc, mii_list)) 1496 mii_phy_reset(miisc); 1497 } 1498 mii_mediachg(mii); 1499 1500 return(0); 1501} 1502 1503/* 1504 * Report current media status. 1505 */ 1506static void sis_ifmedia_sts(ifp, ifmr) 1507 struct ifnet *ifp; 1508 struct ifmediareq *ifmr; 1509{ 1510 struct sis_softc *sc; 1511 struct mii_data *mii; 1512 1513 sc = ifp->if_softc; 1514 1515 mii = device_get_softc(sc->sis_miibus); 1516 mii_pollstat(mii); 1517 ifmr->ifm_active = mii->mii_media_active; 1518 ifmr->ifm_status = mii->mii_media_status; 1519 1520 return; 1521} 1522 1523static int sis_ioctl(ifp, command, data) 1524 struct ifnet *ifp; 1525 u_long command; 1526 caddr_t data; 1527{ 1528 struct sis_softc *sc = ifp->if_softc; 1529 struct ifreq *ifr = (struct ifreq *) data; 1530 struct mii_data *mii; 1531 int s, error = 0; 1532 1533 s = splimp(); 1534 1535 switch(command) { 1536 case SIOCSIFADDR: 1537 case SIOCGIFADDR: 1538 case SIOCSIFMTU: 1539 error = ether_ioctl(ifp, command, data); 1540 break; 1541 case SIOCSIFFLAGS: 1542 if (ifp->if_flags & IFF_UP) { 1543 sis_init(sc); 1544 } else { 1545 if (ifp->if_flags & IFF_RUNNING) 1546 sis_stop(sc); 1547 } 1548 error = 0; 1549 break; 1550 case SIOCADDMULTI: 1551 case SIOCDELMULTI: 1552 if (sc->sis_type == SIS_TYPE_83815) 1553 sis_setmulti_ns(sc); 1554 else 1555 sis_setmulti_sis(sc); 1556 error = 0; 1557 break; 1558 case SIOCGIFMEDIA: 1559 case SIOCSIFMEDIA: 1560 mii = device_get_softc(sc->sis_miibus); 1561 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1562 break; 1563 default: 1564 error = EINVAL; 1565 break; 1566 } 1567 1568 (void)splx(s); 1569 1570 return(error); 1571} 1572 1573static void sis_watchdog(ifp) 1574 struct ifnet *ifp; 1575{ 1576 struct sis_softc *sc; 1577 1578 sc = ifp->if_softc; 1579 1580 ifp->if_oerrors++; 1581 printf("sis%d: watchdog timeout\n", sc->sis_unit); 1582 1583 sis_stop(sc); 1584 sis_reset(sc); 1585 sis_init(sc); 1586 1587 if (ifp->if_snd.ifq_head != NULL) 1588 sis_start(ifp); 1589 1590 return; 1591} 1592 1593/* 1594 * Stop the adapter and free any mbufs allocated to the 1595 * RX and TX lists. 1596 */ 1597static void sis_stop(sc) 1598 struct sis_softc *sc; 1599{ 1600 register int i; 1601 struct ifnet *ifp; 1602 1603 ifp = &sc->arpcom.ac_if; 1604 ifp->if_timer = 0; 1605 1606 untimeout(sis_tick, sc, sc->sis_stat_ch); 1607 CSR_WRITE_4(sc, SIS_IER, 0); 1608 CSR_WRITE_4(sc, SIS_IMR, 0); 1609 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 1610 DELAY(1000); 1611 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 1612 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 1613 1614 sc->sis_link = 0; 1615 1616 /* 1617 * Free data in the RX lists. 1618 */ 1619 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1620 if (sc->sis_ldata->sis_rx_list[i].sis_mbuf != NULL) { 1621 m_freem(sc->sis_ldata->sis_rx_list[i].sis_mbuf); 1622 sc->sis_ldata->sis_rx_list[i].sis_mbuf = NULL; 1623 } 1624 } 1625 bzero((char *)&sc->sis_ldata->sis_rx_list, 1626 sizeof(sc->sis_ldata->sis_rx_list)); 1627 1628 /* 1629 * Free the TX list buffers. 1630 */ 1631 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1632 if (sc->sis_ldata->sis_tx_list[i].sis_mbuf != NULL) { 1633 m_freem(sc->sis_ldata->sis_tx_list[i].sis_mbuf); 1634 sc->sis_ldata->sis_tx_list[i].sis_mbuf = NULL; 1635 } 1636 } 1637 1638 bzero((char *)&sc->sis_ldata->sis_tx_list, 1639 sizeof(sc->sis_ldata->sis_tx_list)); 1640 1641 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1642 1643 return; 1644} 1645 1646/* 1647 * Stop all chip I/O so that the kernel's probe routines don't 1648 * get confused by errant DMAs when rebooting. 1649 */ 1650static void sis_shutdown(dev) 1651 device_t dev; 1652{ 1653 struct sis_softc *sc; 1654 1655 sc = device_get_softc(dev); 1656 1657 sis_reset(sc); 1658 sis_stop(sc); 1659 1660 return; 1661} 1662