if_sis.c revision 62672
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_sis.c 62672 2000-07-06 06:02:04Z wpaul $ 33 */ 34 35/* 36 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 37 * available from http://www.sis.com.tw. 38 * 39 * Written by Bill Paul <wpaul@ee.columbia.edu> 40 * Electrical Engineering Department 41 * Columbia University, New York City 42 */ 43 44/* 45 * The SiS 900 is a fairly simple chip. It uses bus master DMA with 46 * simple TX and RX descriptors of 3 longwords in size. The receiver 47 * has a single perfect filter entry for the station address and a 48 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 49 * transceiver while the 7016 requires an external transceiver chip. 50 * Both chips offer the standard bit-bang MII interface as well as 51 * an enchanced PHY interface which simplifies accessing MII registers. 52 * 53 * The only downside to this chipset is that RX descriptors must be 54 * longword aligned. 55 */ 56 57#include <sys/param.h> 58#include <sys/systm.h> 59#include <sys/sockio.h> 60#include <sys/mbuf.h> 61#include <sys/malloc.h> 62#include <sys/kernel.h> 63#include <sys/socket.h> 64 65#include <net/if.h> 66#include <net/if_arp.h> 67#include <net/ethernet.h> 68#include <net/if_dl.h> 69#include <net/if_media.h> 70 71#include <net/bpf.h> 72 73#include <vm/vm.h> /* for vtophys */ 74#include <vm/pmap.h> /* for vtophys */ 75#include <machine/clock.h> /* for DELAY */ 76#include <machine/bus_pio.h> 77#include <machine/bus_memio.h> 78#include <machine/bus.h> 79#include <machine/resource.h> 80#include <sys/bus.h> 81#include <sys/rman.h> 82 83#include <dev/mii/mii.h> 84#include <dev/mii/miivar.h> 85 86#include <pci/pcireg.h> 87#include <pci/pcivar.h> 88 89#define SIS_USEIOSPACE 90 91#include <pci/if_sisreg.h> 92 93MODULE_DEPEND(sis, miibus, 1, 1, 1); 94 95/* "controller miibus0" required. See GENERIC if you get errors here. */ 96#include "miibus_if.h" 97 98#ifndef lint 99static const char rcsid[] = 100 "$FreeBSD: head/sys/pci/if_sis.c 62672 2000-07-06 06:02:04Z wpaul $"; 101#endif 102 103/* 104 * Various supported device vendors/types and their names. 105 */ 106static struct sis_type sis_devs[] = { 107 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 108 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 109 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP83815 10/100BaseTX" }, 110 { 0, 0, NULL } 111}; 112 113static int sis_probe __P((device_t)); 114static int sis_attach __P((device_t)); 115static int sis_detach __P((device_t)); 116 117static int sis_newbuf __P((struct sis_softc *, 118 struct sis_desc *, 119 struct mbuf *)); 120static int sis_encap __P((struct sis_softc *, 121 struct mbuf *, u_int32_t *)); 122static void sis_rxeof __P((struct sis_softc *)); 123static void sis_rxeoc __P((struct sis_softc *)); 124static void sis_txeof __P((struct sis_softc *)); 125static void sis_intr __P((void *)); 126static void sis_tick __P((void *)); 127static void sis_start __P((struct ifnet *)); 128static int sis_ioctl __P((struct ifnet *, u_long, caddr_t)); 129static void sis_init __P((void *)); 130static void sis_stop __P((struct sis_softc *)); 131static void sis_watchdog __P((struct ifnet *)); 132static void sis_shutdown __P((device_t)); 133static int sis_ifmedia_upd __P((struct ifnet *)); 134static void sis_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 135 136static u_int16_t sis_reverse __P((u_int16_t)); 137static void sis_delay __P((struct sis_softc *)); 138static void sis_eeprom_idle __P((struct sis_softc *)); 139static void sis_eeprom_putbyte __P((struct sis_softc *, int)); 140static void sis_eeprom_getword __P((struct sis_softc *, int, u_int16_t *)); 141static void sis_read_eeprom __P((struct sis_softc *, caddr_t, int, 142 int, int)); 143static int sis_miibus_readreg __P((device_t, int, int)); 144static int sis_miibus_writereg __P((device_t, int, int, int)); 145static void sis_miibus_statchg __P((device_t)); 146 147static void sis_setmulti_sis __P((struct sis_softc *)); 148static void sis_setmulti_ns __P((struct sis_softc *)); 149static u_int32_t sis_crc __P((struct sis_softc *, caddr_t)); 150static void sis_reset __P((struct sis_softc *)); 151static int sis_list_rx_init __P((struct sis_softc *)); 152static int sis_list_tx_init __P((struct sis_softc *)); 153 154#ifdef SIS_USEIOSPACE 155#define SIS_RES SYS_RES_IOPORT 156#define SIS_RID SIS_PCI_LOIO 157#else 158#define SIS_RES SYS_RES_MEMORY 159#define SIS_RID SIS_PCI_LOMEM 160#endif 161 162static device_method_t sis_methods[] = { 163 /* Device interface */ 164 DEVMETHOD(device_probe, sis_probe), 165 DEVMETHOD(device_attach, sis_attach), 166 DEVMETHOD(device_detach, sis_detach), 167 DEVMETHOD(device_shutdown, sis_shutdown), 168 169 /* bus interface */ 170 DEVMETHOD(bus_print_child, bus_generic_print_child), 171 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 172 173 /* MII interface */ 174 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 175 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 176 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 177 178 { 0, 0 } 179}; 180 181static driver_t sis_driver = { 182 "sis", 183 sis_methods, 184 sizeof(struct sis_softc) 185}; 186 187static devclass_t sis_devclass; 188 189DRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, 0, 0); 190DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 191 192#define SIS_SETBIT(sc, reg, x) \ 193 CSR_WRITE_4(sc, reg, \ 194 CSR_READ_4(sc, reg) | (x)) 195 196#define SIS_CLRBIT(sc, reg, x) \ 197 CSR_WRITE_4(sc, reg, \ 198 CSR_READ_4(sc, reg) & ~(x)) 199 200#define SIO_SET(x) \ 201 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 202 203#define SIO_CLR(x) \ 204 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 205 206/* 207 * Routine to reverse the bits in a word. Stolen almost 208 * verbatim from /usr/games/fortune. 209 */ 210static u_int16_t sis_reverse(n) 211 u_int16_t n; 212{ 213 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 214 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 215 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 216 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 217 218 return(n); 219} 220 221static void sis_delay(sc) 222 struct sis_softc *sc; 223{ 224 int idx; 225 226 for (idx = (300 / 33) + 1; idx > 0; idx--) 227 CSR_READ_4(sc, SIS_CSR); 228 229 return; 230} 231 232static void sis_eeprom_idle(sc) 233 struct sis_softc *sc; 234{ 235 register int i; 236 237 SIO_SET(SIS_EECTL_CSEL); 238 sis_delay(sc); 239 SIO_SET(SIS_EECTL_CLK); 240 sis_delay(sc); 241 242 for (i = 0; i < 25; i++) { 243 SIO_CLR(SIS_EECTL_CLK); 244 sis_delay(sc); 245 SIO_SET(SIS_EECTL_CLK); 246 sis_delay(sc); 247 } 248 249 SIO_CLR(SIS_EECTL_CLK); 250 sis_delay(sc); 251 SIO_CLR(SIS_EECTL_CSEL); 252 sis_delay(sc); 253 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 254 255 return; 256} 257 258/* 259 * Send a read command and address to the EEPROM, check for ACK. 260 */ 261static void sis_eeprom_putbyte(sc, addr) 262 struct sis_softc *sc; 263 int addr; 264{ 265 register int d, i; 266 267 d = addr | SIS_EECMD_READ; 268 269 /* 270 * Feed in each bit and stobe the clock. 271 */ 272 for (i = 0x400; i; i >>= 1) { 273 if (d & i) { 274 SIO_SET(SIS_EECTL_DIN); 275 } else { 276 SIO_CLR(SIS_EECTL_DIN); 277 } 278 sis_delay(sc); 279 SIO_SET(SIS_EECTL_CLK); 280 sis_delay(sc); 281 SIO_CLR(SIS_EECTL_CLK); 282 sis_delay(sc); 283 } 284 285 return; 286} 287 288/* 289 * Read a word of data stored in the EEPROM at address 'addr.' 290 */ 291static void sis_eeprom_getword(sc, addr, dest) 292 struct sis_softc *sc; 293 int addr; 294 u_int16_t *dest; 295{ 296 register int i; 297 u_int16_t word = 0; 298 299 /* Force EEPROM to idle state. */ 300 sis_eeprom_idle(sc); 301 302 /* Enter EEPROM access mode. */ 303 sis_delay(sc); 304 SIO_CLR(SIS_EECTL_CLK); 305 sis_delay(sc); 306 SIO_SET(SIS_EECTL_CSEL); 307 sis_delay(sc); 308 309 /* 310 * Send address of word we want to read. 311 */ 312 sis_eeprom_putbyte(sc, addr); 313 314 /* 315 * Start reading bits from EEPROM. 316 */ 317 for (i = 0x8000; i; i >>= 1) { 318 SIO_SET(SIS_EECTL_CLK); 319 sis_delay(sc); 320 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 321 word |= i; 322 sis_delay(sc); 323 SIO_CLR(SIS_EECTL_CLK); 324 sis_delay(sc); 325 } 326 327 /* Turn off EEPROM access mode. */ 328 sis_eeprom_idle(sc); 329 330 *dest = word; 331 332 return; 333} 334 335/* 336 * Read a sequence of words from the EEPROM. 337 */ 338static void sis_read_eeprom(sc, dest, off, cnt, swap) 339 struct sis_softc *sc; 340 caddr_t dest; 341 int off; 342 int cnt; 343 int swap; 344{ 345 int i; 346 u_int16_t word = 0, *ptr; 347 348 for (i = 0; i < cnt; i++) { 349 sis_eeprom_getword(sc, off + i, &word); 350 ptr = (u_int16_t *)(dest + (i * 2)); 351 if (swap) 352 *ptr = ntohs(word); 353 else 354 *ptr = word; 355 } 356 357 return; 358} 359 360static int sis_miibus_readreg(dev, phy, reg) 361 device_t dev; 362 int phy, reg; 363{ 364 struct sis_softc *sc; 365 int i, val = 0; 366 367 sc = device_get_softc(dev); 368 369 if (sc->sis_type == SIS_TYPE_83815) { 370 if (phy != 0) 371 return(0); 372 /* 373 * The NatSemi chip can take a while after 374 * a reset to come ready, during which the BMSR 375 * returns a value of 0. This is *never* supposed 376 * to happen: some of the BMSR bits are meant to 377 * be hardwired in the on position, and this can 378 * confuse the miibus code a bit during the probe 379 * and attach phase. So we make an effort to check 380 * for this condition and wait for it to clear. 381 */ 382 if (!CSR_READ_4(sc, NS_BMSR)) 383 DELAY(1000); 384 val = CSR_READ_4(sc, NS_BMCR + (reg * 4)); 385 return(val); 386 } 387 388 if (sc->sis_type == SIS_TYPE_900 && phy != 0) 389 return(0); 390 391 CSR_WRITE_4(sc, SIS_PHYCTL, (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 392 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 393 394 for (i = 0; i < SIS_TIMEOUT; i++) { 395 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 396 break; 397 } 398 399 if (i == SIS_TIMEOUT) { 400 printf("sis%d: PHY failed to come ready\n", sc->sis_unit); 401 return(0); 402 } 403 404 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 405 406 if (val == 0xFFFF) 407 return(0); 408 409 return(val); 410} 411 412static int sis_miibus_writereg(dev, phy, reg, data) 413 device_t dev; 414 int phy, reg, data; 415{ 416 struct sis_softc *sc; 417 int i; 418 419 sc = device_get_softc(dev); 420 421 if (sc->sis_type == SIS_TYPE_83815) { 422 if (phy != 0) 423 return(0); 424 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 425 return(0); 426 } 427 428 if (sc->sis_type == SIS_TYPE_900 && phy != 0) 429 return(0); 430 431 if (sc->sis_type == SIS_TYPE_900 && phy != 0) 432 return(0); 433 434 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 435 (reg << 6) | SIS_PHYOP_WRITE); 436 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 437 438 for (i = 0; i < SIS_TIMEOUT; i++) { 439 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 440 break; 441 } 442 443 if (i == SIS_TIMEOUT) 444 printf("sis%d: PHY failed to come ready\n", sc->sis_unit); 445 446 return(0); 447} 448 449static void sis_miibus_statchg(dev) 450 device_t dev; 451{ 452 struct sis_softc *sc; 453 struct mii_data *mii; 454 455 sc = device_get_softc(dev); 456 mii = device_get_softc(sc->sis_miibus); 457 458 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 459 SIS_SETBIT(sc, SIS_TX_CFG, 460 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 461 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 462 } else { 463 SIS_CLRBIT(sc, SIS_TX_CFG, 464 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 465 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 466 } 467 468 return; 469} 470 471static u_int32_t sis_crc(sc, addr) 472 struct sis_softc *sc; 473 caddr_t addr; 474{ 475 u_int32_t crc, carry; 476 int i, j; 477 u_int8_t c; 478 479 /* Compute CRC for the address value. */ 480 crc = 0xFFFFFFFF; /* initial value */ 481 482 for (i = 0; i < 6; i++) { 483 c = *(addr + i); 484 for (j = 0; j < 8; j++) { 485 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 486 crc <<= 1; 487 c >>= 1; 488 if (carry) 489 crc = (crc ^ 0x04c11db6) | carry; 490 } 491 } 492 493 /* 494 * return the filter bit position 495 * 496 * The NatSemi chip has a 512-bit filter, which is 497 * different than the SiS, so we special-case it. 498 */ 499 if (sc->sis_type == SIS_TYPE_83815) 500 return((crc >> 23) & 0x1FF); 501 502 return((crc >> 25) & 0x0000007F); 503} 504 505static void sis_setmulti_ns(sc) 506 struct sis_softc *sc; 507{ 508 struct ifnet *ifp; 509 struct ifmultiaddr *ifma; 510 u_int32_t h = 0, i, filtsave; 511 int bit, index; 512 513 ifp = &sc->arpcom.ac_if; 514 515 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 516 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 517 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 518 return; 519 } 520 521 /* 522 * We have to explicitly enable the multicast hash table 523 * on the NatSemi chip if we want to use it, which we do. 524 */ 525 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 526 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 527 528 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 529 530 /* first, zot all the existing hash bits */ 531 for (i = 0; i < 32; i++) { 532 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 533 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 534 } 535 536 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 537 ifma = ifma->ifma_link.le_next) { 538 if (ifma->ifma_addr->sa_family != AF_LINK) 539 continue; 540 h = sis_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 541 index = h >> 3; 542 bit = h & 0x1F; 543 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 544 if (bit > 0xF) 545 bit -= 0x10; 546 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 547 } 548 549 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 550 551 return; 552} 553 554static void sis_setmulti_sis(sc) 555 struct sis_softc *sc; 556{ 557 struct ifnet *ifp; 558 struct ifmultiaddr *ifma; 559 u_int32_t h = 0, i, filtsave; 560 561 ifp = &sc->arpcom.ac_if; 562 563 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 564 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 565 return; 566 } 567 568 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 569 570 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 571 572 /* first, zot all the existing hash bits */ 573 for (i = 0; i < 8; i++) { 574 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + ((i * 16) >> 4)) << 16); 575 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 576 } 577 578 /* now program new ones */ 579 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 580 ifma = ifma->ifma_link.le_next) { 581 if (ifma->ifma_addr->sa_family != AF_LINK) 582 continue; 583 h = sis_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 584 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + (h >> 4)) << 16); 585 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << (h & 0xF))); 586 } 587 588 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 589 590 return; 591} 592 593static void sis_reset(sc) 594 struct sis_softc *sc; 595{ 596 register int i; 597 598 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 599 600 for (i = 0; i < SIS_TIMEOUT; i++) { 601 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 602 break; 603 } 604 605 if (i == SIS_TIMEOUT) 606 printf("sis%d: reset never completed\n", sc->sis_unit); 607 608 /* Wait a little while for the chip to get its brains in order. */ 609 DELAY(1000); 610 return; 611} 612 613/* 614 * Probe for an SiS chip. Check the PCI vendor and device 615 * IDs against our list and return a device name if we find a match. 616 */ 617static int sis_probe(dev) 618 device_t dev; 619{ 620 struct sis_type *t; 621 622 t = sis_devs; 623 624 while(t->sis_name != NULL) { 625 if ((pci_get_vendor(dev) == t->sis_vid) && 626 (pci_get_device(dev) == t->sis_did)) { 627 device_set_desc(dev, t->sis_name); 628 return(0); 629 } 630 t++; 631 } 632 633 return(ENXIO); 634} 635 636/* 637 * Attach the interface. Allocate softc structures, do ifmedia 638 * setup and ethernet/BPF attach. 639 */ 640static int sis_attach(dev) 641 device_t dev; 642{ 643 int s; 644 u_char eaddr[ETHER_ADDR_LEN]; 645 u_int32_t command; 646 struct sis_softc *sc; 647 struct ifnet *ifp; 648 int unit, error = 0, rid; 649 650 s = splimp(); 651 652 sc = device_get_softc(dev); 653 unit = device_get_unit(dev); 654 bzero(sc, sizeof(struct sis_softc)); 655 656 if (pci_get_device(dev) == SIS_DEVICEID_900) 657 sc->sis_type = SIS_TYPE_900; 658 if (pci_get_device(dev) == SIS_DEVICEID_7016) 659 sc->sis_type = SIS_TYPE_7016; 660 if (pci_get_vendor(dev) == NS_VENDORID) 661 sc->sis_type = SIS_TYPE_83815; 662 663 /* 664 * Handle power management nonsense. 665 */ 666 667 command = pci_read_config(dev, SIS_PCI_CAPID, 4) & 0x000000FF; 668 if (command == 0x01) { 669 670 command = pci_read_config(dev, SIS_PCI_PWRMGMTCTRL, 4); 671 if (command & SIS_PSTATE_MASK) { 672 u_int32_t iobase, membase, irq; 673 674 /* Save important PCI config data. */ 675 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4); 676 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4); 677 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4); 678 679 /* Reset the power state. */ 680 printf("sis%d: chip is in D%d power mode " 681 "-- setting to D0\n", unit, command & SIS_PSTATE_MASK); 682 command &= 0xFFFFFFFC; 683 pci_write_config(dev, SIS_PCI_PWRMGMTCTRL, command, 4); 684 685 /* Restore PCI config data. */ 686 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4); 687 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4); 688 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4); 689 } 690 } 691 692 /* 693 * Map control/status registers. 694 */ 695 command = pci_read_config(dev, PCIR_COMMAND, 4); 696 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 697 pci_write_config(dev, PCIR_COMMAND, command, 4); 698 command = pci_read_config(dev, PCIR_COMMAND, 4); 699 700#ifdef SIS_USEIOSPACE 701 if (!(command & PCIM_CMD_PORTEN)) { 702 printf("sis%d: failed to enable I/O ports!\n", unit); 703 error = ENXIO;; 704 goto fail; 705 } 706#else 707 if (!(command & PCIM_CMD_MEMEN)) { 708 printf("sis%d: failed to enable memory mapping!\n", unit); 709 error = ENXIO;; 710 goto fail; 711 } 712#endif 713 714 rid = SIS_RID; 715 sc->sis_res = bus_alloc_resource(dev, SIS_RES, &rid, 716 0, ~0, 1, RF_ACTIVE); 717 718 if (sc->sis_res == NULL) { 719 printf("sis%d: couldn't map ports/memory\n", unit); 720 error = ENXIO; 721 goto fail; 722 } 723 724 sc->sis_btag = rman_get_bustag(sc->sis_res); 725 sc->sis_bhandle = rman_get_bushandle(sc->sis_res); 726 727 /* Allocate interrupt */ 728 rid = 0; 729 sc->sis_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 730 RF_SHAREABLE | RF_ACTIVE); 731 732 if (sc->sis_irq == NULL) { 733 printf("sis%d: couldn't map interrupt\n", unit); 734 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 735 error = ENXIO; 736 goto fail; 737 } 738 739 error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET, 740 sis_intr, sc, &sc->sis_intrhand); 741 742 if (error) { 743 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_res); 744 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 745 printf("sis%d: couldn't set up irq\n", unit); 746 goto fail; 747 } 748 749 /* Reset the adapter. */ 750 sis_reset(sc); 751 752 /* 753 * Get station address from the EEPROM. 754 */ 755 switch (pci_get_vendor(dev)) { 756 case NS_VENDORID: 757 /* 758 * Reading the MAC address out of the EEPROM on 759 * the NatSemi chip takes a bit more work than 760 * you'd expect. The address spans 4 16-bit words, 761 * with the first word containing only a single bit. 762 * You have to shift everything over one bit to 763 * get it aligned properly. Also, the bits are 764 * stored backwards (the LSB is really the MSB, 765 * and so on) so you have to reverse them in order 766 * to get the MAC address into the form we want. 767 * Why? Who the hell knows. 768 */ 769 { 770 u_int16_t tmp[4]; 771 772 sis_read_eeprom(sc, (caddr_t)&tmp, 773 NS_EE_NODEADDR, 4, 0); 774 775 /* Shift everything over one bit. */ 776 tmp[3] = tmp[3] >> 1; 777 tmp[3] |= tmp[2] >> 15; 778 tmp[2] = tmp[2] >> 1; 779 tmp[2] |= tmp[1] >> 15; 780 tmp[1] = tmp[1] >> 1; 781 tmp[1] |= tmp[0] >> 15; 782 783 /* Now reverse all the bits. */ 784 tmp[3] = sis_reverse(tmp[3]); 785 tmp[2] = sis_reverse(tmp[2]); 786 tmp[1] = sis_reverse(tmp[1]); 787 788 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); 789 } 790 break; 791 case SIS_VENDORID: 792 default: 793 sis_read_eeprom(sc, (caddr_t)&eaddr, SIS_EE_NODEADDR, 3, 0); 794 break; 795 } 796 797 /* 798 * A SiS chip was detected. Inform the world. 799 */ 800 printf("sis%d: Ethernet address: %6D\n", unit, eaddr, ":"); 801 802 sc->sis_unit = unit; 803 callout_handle_init(&sc->sis_stat_ch); 804 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 805 806 sc->sis_ldata = contigmalloc(sizeof(struct sis_list_data), M_DEVBUF, 807 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 808 809 if (sc->sis_ldata == NULL) { 810 printf("sis%d: no memory for list buffers!\n", unit); 811 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 812 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 813 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 814 error = ENXIO; 815 goto fail; 816 } 817 bzero(sc->sis_ldata, sizeof(struct sis_list_data)); 818 819 ifp = &sc->arpcom.ac_if; 820 ifp->if_softc = sc; 821 ifp->if_unit = unit; 822 ifp->if_name = "sis"; 823 ifp->if_mtu = ETHERMTU; 824 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 825 ifp->if_ioctl = sis_ioctl; 826 ifp->if_output = ether_output; 827 ifp->if_start = sis_start; 828 ifp->if_watchdog = sis_watchdog; 829 ifp->if_init = sis_init; 830 ifp->if_baudrate = 10000000; 831 ifp->if_snd.ifq_maxlen = SIS_TX_LIST_CNT - 1; 832 833 /* 834 * Do MII setup. 835 */ 836 if (mii_phy_probe(dev, &sc->sis_miibus, 837 sis_ifmedia_upd, sis_ifmedia_sts)) { 838 printf("sis%d: MII without any PHY!\n", sc->sis_unit); 839 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 840 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 841 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 842 error = ENXIO; 843 goto fail; 844 } 845 846 /* 847 * Call MI attach routines. 848 */ 849 if_attach(ifp); 850 ether_ifattach(ifp); 851 callout_handle_init(&sc->sis_stat_ch); 852 853 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 854 855fail: 856 splx(s); 857 return(error); 858} 859 860static int sis_detach(dev) 861 device_t dev; 862{ 863 struct sis_softc *sc; 864 struct ifnet *ifp; 865 int s; 866 867 s = splimp(); 868 869 sc = device_get_softc(dev); 870 ifp = &sc->arpcom.ac_if; 871 872 sis_reset(sc); 873 sis_stop(sc); 874 if_detach(ifp); 875 876 bus_generic_detach(dev); 877 device_delete_child(dev, sc->sis_miibus); 878 879 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 880 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 881 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 882 883 contigfree(sc->sis_ldata, sizeof(struct sis_list_data), M_DEVBUF); 884 885 splx(s); 886 887 return(0); 888} 889 890/* 891 * Initialize the transmit descriptors. 892 */ 893static int sis_list_tx_init(sc) 894 struct sis_softc *sc; 895{ 896 struct sis_list_data *ld; 897 struct sis_ring_data *cd; 898 int i; 899 900 cd = &sc->sis_cdata; 901 ld = sc->sis_ldata; 902 903 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 904 if (i == (SIS_TX_LIST_CNT - 1)) { 905 ld->sis_tx_list[i].sis_nextdesc = 906 &ld->sis_tx_list[0]; 907 ld->sis_tx_list[i].sis_next = 908 vtophys(&ld->sis_tx_list[0]); 909 } else { 910 ld->sis_tx_list[i].sis_nextdesc = 911 &ld->sis_tx_list[i + 1]; 912 ld->sis_tx_list[i].sis_next = 913 vtophys(&ld->sis_tx_list[i + 1]); 914 } 915 ld->sis_tx_list[i].sis_mbuf = NULL; 916 ld->sis_tx_list[i].sis_ptr = 0; 917 ld->sis_tx_list[i].sis_ctl = 0; 918 } 919 920 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0; 921 922 return(0); 923} 924 925 926/* 927 * Initialize the RX descriptors and allocate mbufs for them. Note that 928 * we arrange the descriptors in a closed ring, so that the last descriptor 929 * points back to the first. 930 */ 931static int sis_list_rx_init(sc) 932 struct sis_softc *sc; 933{ 934 struct sis_list_data *ld; 935 struct sis_ring_data *cd; 936 int i; 937 938 ld = sc->sis_ldata; 939 cd = &sc->sis_cdata; 940 941 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 942 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS) 943 return(ENOBUFS); 944 if (i == (SIS_RX_LIST_CNT - 1)) { 945 ld->sis_rx_list[i].sis_nextdesc = 946 &ld->sis_rx_list[0]; 947 ld->sis_rx_list[i].sis_next = 948 vtophys(&ld->sis_rx_list[0]); 949 } else { 950 ld->sis_rx_list[i].sis_nextdesc = 951 &ld->sis_rx_list[i + 1]; 952 ld->sis_rx_list[i].sis_next = 953 vtophys(&ld->sis_rx_list[i + 1]); 954 } 955 } 956 957 cd->sis_rx_prod = 0; 958 959 return(0); 960} 961 962/* 963 * Initialize an RX descriptor and attach an MBUF cluster. 964 */ 965static int sis_newbuf(sc, c, m) 966 struct sis_softc *sc; 967 struct sis_desc *c; 968 struct mbuf *m; 969{ 970 struct mbuf *m_new = NULL; 971 972 if (m == NULL) { 973 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 974 if (m_new == NULL) { 975 printf("sis%d: no memory for rx list " 976 "-- packet dropped!\n", sc->sis_unit); 977 return(ENOBUFS); 978 } 979 980 MCLGET(m_new, M_DONTWAIT); 981 if (!(m_new->m_flags & M_EXT)) { 982 printf("sis%d: no memory for rx list " 983 "-- packet dropped!\n", sc->sis_unit); 984 m_freem(m_new); 985 return(ENOBUFS); 986 } 987 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 988 } else { 989 m_new = m; 990 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 991 m_new->m_data = m_new->m_ext.ext_buf; 992 } 993 994 m_adj(m_new, sizeof(u_int64_t)); 995 996 c->sis_mbuf = m_new; 997 c->sis_ptr = vtophys(mtod(m_new, caddr_t)); 998 c->sis_ctl = SIS_RXLEN; 999 1000 return(0); 1001} 1002 1003/* 1004 * A frame has been uploaded: pass the resulting mbuf chain up to 1005 * the higher level protocols. 1006 */ 1007static void sis_rxeof(sc) 1008 struct sis_softc *sc; 1009{ 1010 struct ether_header *eh; 1011 struct mbuf *m; 1012 struct ifnet *ifp; 1013 struct sis_desc *cur_rx; 1014 int i, total_len = 0; 1015 u_int32_t rxstat; 1016 1017 ifp = &sc->arpcom.ac_if; 1018 i = sc->sis_cdata.sis_rx_prod; 1019 1020 while(SIS_OWNDESC(&sc->sis_ldata->sis_rx_list[i])) { 1021 struct mbuf *m0 = NULL; 1022 1023 cur_rx = &sc->sis_ldata->sis_rx_list[i]; 1024 rxstat = cur_rx->sis_rxstat; 1025 m = cur_rx->sis_mbuf; 1026 cur_rx->sis_mbuf = NULL; 1027 total_len = SIS_RXBYTES(cur_rx); 1028 SIS_INC(i, SIS_RX_LIST_CNT); 1029 1030 /* 1031 * If an error occurs, update stats, clear the 1032 * status word and leave the mbuf cluster in place: 1033 * it should simply get re-used next time this descriptor 1034 * comes up in the ring. 1035 */ 1036 if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 1037 ifp->if_ierrors++; 1038 if (rxstat & SIS_RXSTAT_COLL) 1039 ifp->if_collisions++; 1040 sis_newbuf(sc, cur_rx, m); 1041 continue; 1042 } 1043 1044 /* No errors; receive the packet. */ 1045 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1046 total_len + ETHER_ALIGN, 0, ifp, NULL); 1047 sis_newbuf(sc, cur_rx, m); 1048 if (m0 == NULL) { 1049 ifp->if_ierrors++; 1050 continue; 1051 } 1052 m_adj(m0, ETHER_ALIGN); 1053 m = m0; 1054 1055 ifp->if_ipackets++; 1056 eh = mtod(m, struct ether_header *); 1057 1058 /* Remove header from mbuf and pass it on. */ 1059 m_adj(m, sizeof(struct ether_header)); 1060 ether_input(ifp, eh, m); 1061 } 1062 1063 sc->sis_cdata.sis_rx_prod = i; 1064 1065 return; 1066} 1067 1068void sis_rxeoc(sc) 1069 struct sis_softc *sc; 1070{ 1071 sis_rxeof(sc); 1072 sis_init(sc); 1073 return; 1074} 1075 1076/* 1077 * A frame was downloaded to the chip. It's safe for us to clean up 1078 * the list buffers. 1079 */ 1080 1081static void sis_txeof(sc) 1082 struct sis_softc *sc; 1083{ 1084 struct sis_desc *cur_tx = NULL; 1085 struct ifnet *ifp; 1086 u_int32_t idx; 1087 1088 ifp = &sc->arpcom.ac_if; 1089 1090 /* Clear the timeout timer. */ 1091 ifp->if_timer = 0; 1092 1093 /* 1094 * Go through our tx list and free mbufs for those 1095 * frames that have been transmitted. 1096 */ 1097 idx = sc->sis_cdata.sis_tx_cons; 1098 while (idx != sc->sis_cdata.sis_tx_prod) { 1099 cur_tx = &sc->sis_ldata->sis_tx_list[idx]; 1100 1101 if (SIS_OWNDESC(cur_tx)) 1102 break; 1103 1104 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) { 1105 sc->sis_cdata.sis_tx_cnt--; 1106 SIS_INC(idx, SIS_TX_LIST_CNT); 1107 continue; 1108 } 1109 1110 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 1111 ifp->if_oerrors++; 1112 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 1113 ifp->if_collisions++; 1114 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 1115 ifp->if_collisions++; 1116 } 1117 1118 ifp->if_collisions += 1119 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 1120 1121 ifp->if_opackets++; 1122 if (cur_tx->sis_mbuf != NULL) { 1123 m_freem(cur_tx->sis_mbuf); 1124 cur_tx->sis_mbuf = NULL; 1125 } 1126 1127 sc->sis_cdata.sis_tx_cnt--; 1128 SIS_INC(idx, SIS_TX_LIST_CNT); 1129 ifp->if_timer = 0; 1130 } 1131 1132 sc->sis_cdata.sis_tx_cons = idx; 1133 1134 if (cur_tx != NULL) 1135 ifp->if_flags &= ~IFF_OACTIVE; 1136 1137 return; 1138} 1139 1140static void sis_tick(xsc) 1141 void *xsc; 1142{ 1143 struct sis_softc *sc; 1144 struct mii_data *mii; 1145 int s; 1146 1147 s = splimp(); 1148 1149 sc = xsc; 1150 mii = device_get_softc(sc->sis_miibus); 1151 mii_tick(mii); 1152 sc->sis_stat_ch = timeout(sis_tick, sc, hz); 1153 1154 splx(s); 1155 1156 return; 1157} 1158 1159static void sis_intr(arg) 1160 void *arg; 1161{ 1162 struct sis_softc *sc; 1163 struct ifnet *ifp; 1164 u_int32_t status; 1165 1166 sc = arg; 1167 ifp = &sc->arpcom.ac_if; 1168 1169 /* Supress unwanted interrupts */ 1170 if (!(ifp->if_flags & IFF_UP)) { 1171 sis_stop(sc); 1172 return; 1173 } 1174 1175 /* Disable interrupts. */ 1176 CSR_WRITE_4(sc, SIS_IER, 0); 1177 1178 for (;;) { 1179 /* Reading the ISR register clears all interrupts. */ 1180 status = CSR_READ_4(sc, SIS_ISR); 1181 1182 if ((status & SIS_INTRS) == 0) 1183 break; 1184 1185 if ((status & SIS_ISR_TX_OK) || 1186 (status & SIS_ISR_TX_ERR) || 1187 (status & SIS_ISR_TX_IDLE)) 1188 sis_txeof(sc); 1189 1190 if (status & SIS_ISR_RX_OK) 1191 sis_rxeof(sc); 1192 1193 if ((status & SIS_ISR_RX_ERR) || 1194 (status & SIS_ISR_RX_OFLOW)) { 1195 sis_rxeoc(sc); 1196 } 1197 1198 if (status & SIS_ISR_SYSERR) { 1199 sis_reset(sc); 1200 sis_init(sc); 1201 } 1202 } 1203 1204 /* Re-enable interrupts. */ 1205 CSR_WRITE_4(sc, SIS_IER, 1); 1206 1207 if (ifp->if_snd.ifq_head != NULL) 1208 sis_start(ifp); 1209 1210 return; 1211} 1212 1213/* 1214 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1215 * pointers to the fragment pointers. 1216 */ 1217static int sis_encap(sc, m_head, txidx) 1218 struct sis_softc *sc; 1219 struct mbuf *m_head; 1220 u_int32_t *txidx; 1221{ 1222 struct sis_desc *f = NULL; 1223 struct mbuf *m; 1224 int frag, cur, cnt = 0; 1225 1226 /* 1227 * Start packing the mbufs in this chain into 1228 * the fragment pointers. Stop when we run out 1229 * of fragments or hit the end of the mbuf chain. 1230 */ 1231 m = m_head; 1232 cur = frag = *txidx; 1233 1234 for (m = m_head; m != NULL; m = m->m_next) { 1235 if (m->m_len != 0) { 1236 if ((SIS_TX_LIST_CNT - 1237 (sc->sis_cdata.sis_tx_cnt + cnt)) < 2) 1238 return(ENOBUFS); 1239 f = &sc->sis_ldata->sis_tx_list[frag]; 1240 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; 1241 f->sis_ptr = vtophys(mtod(m, vm_offset_t)); 1242 if (cnt != 0) 1243 f->sis_ctl |= SIS_CMDSTS_OWN; 1244 cur = frag; 1245 SIS_INC(frag, SIS_TX_LIST_CNT); 1246 cnt++; 1247 } 1248 } 1249 1250 if (m != NULL) 1251 return(ENOBUFS); 1252 1253 sc->sis_ldata->sis_tx_list[cur].sis_mbuf = m_head; 1254 sc->sis_ldata->sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1255 sc->sis_ldata->sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1256 sc->sis_cdata.sis_tx_cnt += cnt; 1257 *txidx = frag; 1258 1259 return(0); 1260} 1261 1262/* 1263 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1264 * to the mbuf data regions directly in the transmit lists. We also save a 1265 * copy of the pointers since the transmit list fragment pointers are 1266 * physical addresses. 1267 */ 1268 1269static void sis_start(ifp) 1270 struct ifnet *ifp; 1271{ 1272 struct sis_softc *sc; 1273 struct mbuf *m_head = NULL; 1274 u_int32_t idx; 1275 1276 sc = ifp->if_softc; 1277 1278 idx = sc->sis_cdata.sis_tx_prod; 1279 1280 if (ifp->if_flags & IFF_OACTIVE) 1281 return; 1282 1283 while(sc->sis_ldata->sis_tx_list[idx].sis_mbuf == NULL) { 1284 IF_DEQUEUE(&ifp->if_snd, m_head); 1285 if (m_head == NULL) 1286 break; 1287 1288 if (sis_encap(sc, m_head, &idx)) { 1289 IF_PREPEND(&ifp->if_snd, m_head); 1290 ifp->if_flags |= IFF_OACTIVE; 1291 break; 1292 } 1293 1294 /* 1295 * If there's a BPF listener, bounce a copy of this frame 1296 * to him. 1297 */ 1298 if (ifp->if_bpf) 1299 bpf_mtap(ifp, m_head); 1300 1301 } 1302 1303 /* Transmit */ 1304 sc->sis_cdata.sis_tx_prod = idx; 1305 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 1306 1307 /* 1308 * Set a timeout in case the chip goes out to lunch. 1309 */ 1310 ifp->if_timer = 5; 1311 1312 return; 1313} 1314 1315static void sis_init(xsc) 1316 void *xsc; 1317{ 1318 struct sis_softc *sc = xsc; 1319 struct ifnet *ifp = &sc->arpcom.ac_if; 1320 struct mii_data *mii; 1321 int s; 1322 1323 s = splimp(); 1324 1325 /* 1326 * Cancel pending I/O and free all RX/TX buffers. 1327 */ 1328 sis_stop(sc); 1329 1330 mii = device_get_softc(sc->sis_miibus); 1331 1332 /* Set MAC address */ 1333 if (sc->sis_type == SIS_TYPE_83815) { 1334 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 1335 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1336 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1337 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 1338 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1339 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1340 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 1341 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1342 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1343 } else { 1344 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 1345 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1346 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1347 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 1348 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1349 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1350 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 1351 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1352 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1353 } 1354 1355 /* Init circular RX list. */ 1356 if (sis_list_rx_init(sc) == ENOBUFS) { 1357 printf("sis%d: initialization failed: no " 1358 "memory for rx buffers\n", sc->sis_unit); 1359 sis_stop(sc); 1360 (void)splx(s); 1361 return; 1362 } 1363 1364 /* 1365 * Init tx descriptors. 1366 */ 1367 sis_list_tx_init(sc); 1368 1369 /* 1370 * For the NatSemi chip, we have to explicitly enable the 1371 * reception of ARP frames, as well as turn on the 'perfect 1372 * match' filter where we store the station address, otherwise 1373 * we won't receive unicasts meant for this host. 1374 */ 1375 if (sc->sis_type == SIS_TYPE_83815) { 1376 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 1377 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 1378 } 1379 1380 /* If we want promiscuous mode, set the allframes bit. */ 1381 if (ifp->if_flags & IFF_PROMISC) { 1382 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1383 } else { 1384 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1385 } 1386 1387 /* 1388 * Set the capture broadcast bit to capture broadcast frames. 1389 */ 1390 if (ifp->if_flags & IFF_BROADCAST) { 1391 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1392 } else { 1393 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1394 } 1395 1396 /* 1397 * Load the multicast filter. 1398 */ 1399 if (sc->sis_type == SIS_TYPE_83815) 1400 sis_setmulti_ns(sc); 1401 else 1402 sis_setmulti_sis(sc); 1403 1404 /* Turn the receive filter on */ 1405 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 1406 1407 /* 1408 * Load the address of the RX and TX lists. 1409 */ 1410 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 1411 vtophys(&sc->sis_ldata->sis_rx_list[0])); 1412 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 1413 vtophys(&sc->sis_ldata->sis_tx_list[0])); 1414 1415 /* Set RX configuration */ 1416 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG); 1417 /* Set TX configuration */ 1418 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG); 1419 1420 /* 1421 * Enable interrupts. 1422 */ 1423 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 1424 CSR_WRITE_4(sc, SIS_IER, 1); 1425 1426 /* Enable receiver and transmitter. */ 1427 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 1428 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1429 1430 mii_mediachg(mii); 1431 1432 ifp->if_flags |= IFF_RUNNING; 1433 ifp->if_flags &= ~IFF_OACTIVE; 1434 1435 (void)splx(s); 1436 1437 sc->sis_stat_ch = timeout(sis_tick, sc, hz); 1438 1439 return; 1440} 1441 1442/* 1443 * Set media options. 1444 */ 1445static int sis_ifmedia_upd(ifp) 1446 struct ifnet *ifp; 1447{ 1448 struct sis_softc *sc; 1449 1450 sc = ifp->if_softc; 1451 1452 if (ifp->if_flags & IFF_UP) 1453 sis_init(sc); 1454 1455 return(0); 1456} 1457 1458/* 1459 * Report current media status. 1460 */ 1461static void sis_ifmedia_sts(ifp, ifmr) 1462 struct ifnet *ifp; 1463 struct ifmediareq *ifmr; 1464{ 1465 struct sis_softc *sc; 1466 struct mii_data *mii; 1467 1468 sc = ifp->if_softc; 1469 1470 mii = device_get_softc(sc->sis_miibus); 1471 mii_pollstat(mii); 1472 ifmr->ifm_active = mii->mii_media_active; 1473 ifmr->ifm_status = mii->mii_media_status; 1474 1475 return; 1476} 1477 1478static int sis_ioctl(ifp, command, data) 1479 struct ifnet *ifp; 1480 u_long command; 1481 caddr_t data; 1482{ 1483 struct sis_softc *sc = ifp->if_softc; 1484 struct ifreq *ifr = (struct ifreq *) data; 1485 struct mii_data *mii; 1486 int s, error = 0; 1487 1488 s = splimp(); 1489 1490 switch(command) { 1491 case SIOCSIFADDR: 1492 case SIOCGIFADDR: 1493 case SIOCSIFMTU: 1494 error = ether_ioctl(ifp, command, data); 1495 break; 1496 case SIOCSIFFLAGS: 1497 if (ifp->if_flags & IFF_UP) { 1498 sis_init(sc); 1499 } else { 1500 if (ifp->if_flags & IFF_RUNNING) 1501 sis_stop(sc); 1502 } 1503 error = 0; 1504 break; 1505 case SIOCADDMULTI: 1506 case SIOCDELMULTI: 1507 if (sc->sis_type == SIS_TYPE_83815) 1508 sis_setmulti_ns(sc); 1509 else 1510 sis_setmulti_sis(sc); 1511 error = 0; 1512 break; 1513 case SIOCGIFMEDIA: 1514 case SIOCSIFMEDIA: 1515 mii = device_get_softc(sc->sis_miibus); 1516 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1517 break; 1518 default: 1519 error = EINVAL; 1520 break; 1521 } 1522 1523 (void)splx(s); 1524 1525 return(error); 1526} 1527 1528static void sis_watchdog(ifp) 1529 struct ifnet *ifp; 1530{ 1531 struct sis_softc *sc; 1532 1533 sc = ifp->if_softc; 1534 1535 ifp->if_oerrors++; 1536 printf("sis%d: watchdog timeout\n", sc->sis_unit); 1537 1538 sis_stop(sc); 1539 sis_reset(sc); 1540 sis_init(sc); 1541 1542 if (ifp->if_snd.ifq_head != NULL) 1543 sis_start(ifp); 1544 1545 return; 1546} 1547 1548/* 1549 * Stop the adapter and free any mbufs allocated to the 1550 * RX and TX lists. 1551 */ 1552static void sis_stop(sc) 1553 struct sis_softc *sc; 1554{ 1555 register int i; 1556 struct ifnet *ifp; 1557 1558 ifp = &sc->arpcom.ac_if; 1559 ifp->if_timer = 0; 1560 1561 untimeout(sis_tick, sc, sc->sis_stat_ch); 1562 CSR_WRITE_4(sc, SIS_IER, 0); 1563 CSR_WRITE_4(sc, SIS_IMR, 0); 1564 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 1565 DELAY(1000); 1566 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 1567 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 1568 1569 /* 1570 * Free data in the RX lists. 1571 */ 1572 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1573 if (sc->sis_ldata->sis_rx_list[i].sis_mbuf != NULL) { 1574 m_freem(sc->sis_ldata->sis_rx_list[i].sis_mbuf); 1575 sc->sis_ldata->sis_rx_list[i].sis_mbuf = NULL; 1576 } 1577 } 1578 bzero((char *)&sc->sis_ldata->sis_rx_list, 1579 sizeof(sc->sis_ldata->sis_rx_list)); 1580 1581 /* 1582 * Free the TX list buffers. 1583 */ 1584 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1585 if (sc->sis_ldata->sis_tx_list[i].sis_mbuf != NULL) { 1586 m_freem(sc->sis_ldata->sis_tx_list[i].sis_mbuf); 1587 sc->sis_ldata->sis_tx_list[i].sis_mbuf = NULL; 1588 } 1589 } 1590 1591 bzero((char *)&sc->sis_ldata->sis_tx_list, 1592 sizeof(sc->sis_ldata->sis_tx_list)); 1593 1594 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1595 1596 return; 1597} 1598 1599/* 1600 * Stop all chip I/O so that the kernel's probe routines don't 1601 * get confused by errant DMAs when rebooting. 1602 */ 1603static void sis_shutdown(dev) 1604 device_t dev; 1605{ 1606 struct sis_softc *sc; 1607 1608 sc = device_get_softc(dev); 1609 1610 sis_reset(sc); 1611 sis_stop(sc); 1612 1613 return; 1614} 1615