if_sis.c revision 59758
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_sis.c 59758 2000-04-29 13:41:57Z peter $ 33 */ 34 35/* 36 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 37 * available from http://www.sis.com.tw. 38 * 39 * Written by Bill Paul <wpaul@ee.columbia.edu> 40 * Electrical Engineering Department 41 * Columbia University, New York City 42 */ 43 44/* 45 * The SiS 900 is a fairly simple chip. It uses bus master DMA with 46 * simple TX and RX descriptors of 3 longwords in size. The receiver 47 * has a single perfect filter entry for the station address and a 48 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 49 * transceiver while the 7016 requires an external transceiver chip. 50 * Both chips offer the standard bit-bang MII interface as well as 51 * an enchanced PHY interface which simplifies accessing MII registers. 52 * 53 * The only downside to this chipset is that RX descriptors must be 54 * longword aligned. 55 */ 56 57#include <sys/param.h> 58#include <sys/systm.h> 59#include <sys/sockio.h> 60#include <sys/mbuf.h> 61#include <sys/malloc.h> 62#include <sys/kernel.h> 63#include <sys/socket.h> 64 65#include <net/if.h> 66#include <net/if_arp.h> 67#include <net/ethernet.h> 68#include <net/if_dl.h> 69#include <net/if_media.h> 70 71#include <net/bpf.h> 72 73#include <vm/vm.h> /* for vtophys */ 74#include <vm/pmap.h> /* for vtophys */ 75#include <machine/clock.h> /* for DELAY */ 76#include <machine/bus_pio.h> 77#include <machine/bus_memio.h> 78#include <machine/bus.h> 79#include <machine/resource.h> 80#include <sys/bus.h> 81#include <sys/rman.h> 82 83#include <dev/mii/mii.h> 84#include <dev/mii/miivar.h> 85 86#include <pci/pcireg.h> 87#include <pci/pcivar.h> 88 89#define SIS_USEIOSPACE 90 91#include <pci/if_sisreg.h> 92 93MODULE_DEPEND(sis, miibus, 1, 1, 1); 94 95/* "controller miibus0" required. See GENERIC if you get errors here. */ 96#include "miibus_if.h" 97 98#ifndef lint 99static const char rcsid[] = 100 "$FreeBSD: head/sys/pci/if_sis.c 59758 2000-04-29 13:41:57Z peter $"; 101#endif 102 103/* 104 * Various supported device vendors/types and their names. 105 */ 106static struct sis_type sis_devs[] = { 107 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 108 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 109 { 0, 0, NULL } 110}; 111 112static int sis_probe __P((device_t)); 113static int sis_attach __P((device_t)); 114static int sis_detach __P((device_t)); 115 116static int sis_newbuf __P((struct sis_softc *, 117 struct sis_desc *, 118 struct mbuf *)); 119static int sis_encap __P((struct sis_softc *, 120 struct mbuf *, u_int32_t *)); 121static void sis_rxeof __P((struct sis_softc *)); 122static void sis_rxeoc __P((struct sis_softc *)); 123static void sis_txeof __P((struct sis_softc *)); 124static void sis_intr __P((void *)); 125static void sis_tick __P((void *)); 126static void sis_start __P((struct ifnet *)); 127static int sis_ioctl __P((struct ifnet *, u_long, caddr_t)); 128static void sis_init __P((void *)); 129static void sis_stop __P((struct sis_softc *)); 130static void sis_watchdog __P((struct ifnet *)); 131static void sis_shutdown __P((device_t)); 132static int sis_ifmedia_upd __P((struct ifnet *)); 133static void sis_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 134 135static void sis_delay __P((struct sis_softc *)); 136static void sis_eeprom_idle __P((struct sis_softc *)); 137static void sis_eeprom_putbyte __P((struct sis_softc *, int)); 138static void sis_eeprom_getword __P((struct sis_softc *, int, u_int16_t *)); 139static void sis_read_eeprom __P((struct sis_softc *, caddr_t, int, 140 int, int)); 141static int sis_miibus_readreg __P((device_t, int, int)); 142static int sis_miibus_writereg __P((device_t, int, int, int)); 143static void sis_miibus_statchg __P((device_t)); 144 145static void sis_setmulti __P((struct sis_softc *)); 146static u_int32_t sis_calchash __P((caddr_t)); 147static void sis_reset __P((struct sis_softc *)); 148static int sis_list_rx_init __P((struct sis_softc *)); 149static int sis_list_tx_init __P((struct sis_softc *)); 150 151#ifdef SIS_USEIOSPACE 152#define SIS_RES SYS_RES_IOPORT 153#define SIS_RID SIS_PCI_LOIO 154#else 155#define SIS_RES SYS_RES_MEMORY 156#define SIS_RID SIS_PCI_LOMEM 157#endif 158 159static device_method_t sis_methods[] = { 160 /* Device interface */ 161 DEVMETHOD(device_probe, sis_probe), 162 DEVMETHOD(device_attach, sis_attach), 163 DEVMETHOD(device_detach, sis_detach), 164 DEVMETHOD(device_shutdown, sis_shutdown), 165 166 /* bus interface */ 167 DEVMETHOD(bus_print_child, bus_generic_print_child), 168 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 169 170 /* MII interface */ 171 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 172 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 173 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 174 175 { 0, 0 } 176}; 177 178static driver_t sis_driver = { 179 "sis", 180 sis_methods, 181 sizeof(struct sis_softc) 182}; 183 184static devclass_t sis_devclass; 185 186DRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, 0, 0); 187DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 188 189#define SIS_SETBIT(sc, reg, x) \ 190 CSR_WRITE_4(sc, reg, \ 191 CSR_READ_4(sc, reg) | (x)) 192 193#define SIS_CLRBIT(sc, reg, x) \ 194 CSR_WRITE_4(sc, reg, \ 195 CSR_READ_4(sc, reg) & ~(x)) 196 197#define SIO_SET(x) \ 198 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 199 200#define SIO_CLR(x) \ 201 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 202 203static void sis_delay(sc) 204 struct sis_softc *sc; 205{ 206 int idx; 207 208 for (idx = (300 / 33) + 1; idx > 0; idx--) 209 CSR_READ_4(sc, SIS_CSR); 210 211 return; 212} 213 214static void sis_eeprom_idle(sc) 215 struct sis_softc *sc; 216{ 217 register int i; 218 219 SIO_SET(SIS_EECTL_CSEL); 220 sis_delay(sc); 221 SIO_SET(SIS_EECTL_CLK); 222 sis_delay(sc); 223 224 for (i = 0; i < 25; i++) { 225 SIO_CLR(SIS_EECTL_CLK); 226 sis_delay(sc); 227 SIO_SET(SIS_EECTL_CLK); 228 sis_delay(sc); 229 } 230 231 SIO_CLR(SIS_EECTL_CLK); 232 sis_delay(sc); 233 SIO_CLR(SIS_EECTL_CSEL); 234 sis_delay(sc); 235 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 236 237 return; 238} 239 240/* 241 * Send a read command and address to the EEPROM, check for ACK. 242 */ 243static void sis_eeprom_putbyte(sc, addr) 244 struct sis_softc *sc; 245 int addr; 246{ 247 register int d, i; 248 249 d = addr | SIS_EECMD_READ; 250 251 /* 252 * Feed in each bit and stobe the clock. 253 */ 254 for (i = 0x400; i; i >>= 1) { 255 if (d & i) { 256 SIO_SET(SIS_EECTL_DIN); 257 } else { 258 SIO_CLR(SIS_EECTL_DIN); 259 } 260 sis_delay(sc); 261 SIO_SET(SIS_EECTL_CLK); 262 sis_delay(sc); 263 SIO_CLR(SIS_EECTL_CLK); 264 sis_delay(sc); 265 } 266 267 return; 268} 269 270/* 271 * Read a word of data stored in the EEPROM at address 'addr.' 272 */ 273static void sis_eeprom_getword(sc, addr, dest) 274 struct sis_softc *sc; 275 int addr; 276 u_int16_t *dest; 277{ 278 register int i; 279 u_int16_t word = 0; 280 281 /* Force EEPROM to idle state. */ 282 sis_eeprom_idle(sc); 283 284 /* Enter EEPROM access mode. */ 285 sis_delay(sc); 286 SIO_SET(SIS_EECTL_CSEL); 287 sis_delay(sc); 288 SIO_SET(SIS_EECTL_CLK); 289 sis_delay(sc); 290 291 /* 292 * Send address of word we want to read. 293 */ 294 sis_eeprom_putbyte(sc, addr); 295 296 /* 297 * Start reading bits from EEPROM. 298 */ 299 for (i = 0x8000; i; i >>= 1) { 300 SIO_SET(SIS_EECTL_CLK); 301 sis_delay(sc); 302 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 303 word |= i; 304 sis_delay(sc); 305 SIO_CLR(SIS_EECTL_CLK); 306 sis_delay(sc); 307 } 308 309 /* Turn off EEPROM access mode. */ 310 sis_eeprom_idle(sc); 311 312 *dest = word; 313 314 return; 315} 316 317/* 318 * Read a sequence of words from the EEPROM. 319 */ 320static void sis_read_eeprom(sc, dest, off, cnt, swap) 321 struct sis_softc *sc; 322 caddr_t dest; 323 int off; 324 int cnt; 325 int swap; 326{ 327 int i; 328 u_int16_t word = 0, *ptr; 329 330 for (i = 0; i < cnt; i++) { 331 sis_eeprom_getword(sc, off + i, &word); 332 ptr = (u_int16_t *)(dest + (i * 2)); 333 if (swap) 334 *ptr = ntohs(word); 335 else 336 *ptr = word; 337 } 338 339 return; 340} 341 342static int sis_miibus_readreg(dev, phy, reg) 343 device_t dev; 344 int phy, reg; 345{ 346 struct sis_softc *sc; 347 int i, val; 348 349 sc = device_get_softc(dev); 350 351 if (sc->sis_type == SIS_TYPE_900 && phy != 0) 352 return(0); 353 354 CSR_WRITE_4(sc, SIS_PHYCTL, (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 355 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 356 357 for (i = 0; i < SIS_TIMEOUT; i++) { 358 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 359 break; 360 } 361 362 if (i == SIS_TIMEOUT) { 363 printf("sis%d: PHY failed to come ready\n", sc->sis_unit); 364 return(0); 365 } 366 367 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 368 369 if (val == 0xFFFF) 370 return(0); 371 372 return(val); 373} 374 375static int sis_miibus_writereg(dev, phy, reg, data) 376 device_t dev; 377 int phy, reg, data; 378{ 379 struct sis_softc *sc; 380 int i; 381 382 sc = device_get_softc(dev); 383 384 if (sc->sis_type == SIS_TYPE_900 && phy != 0) 385 return(0); 386 387 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 388 (reg << 6) | SIS_PHYOP_WRITE); 389 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 390 391 for (i = 0; i < SIS_TIMEOUT; i++) { 392 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 393 break; 394 } 395 396 if (i == SIS_TIMEOUT) 397 printf("sis%d: PHY failed to come ready\n", sc->sis_unit); 398 399 return(0); 400} 401 402static void sis_miibus_statchg(dev) 403 device_t dev; 404{ 405 struct sis_softc *sc; 406 struct mii_data *mii; 407 408 sc = device_get_softc(dev); 409 mii = device_get_softc(sc->sis_miibus); 410 411 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 412 SIS_SETBIT(sc, SIS_TX_CFG, 413 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 414 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 415 } else { 416 SIS_CLRBIT(sc, SIS_TX_CFG, 417 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 418 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 419 } 420 421 return; 422} 423 424static u_int32_t sis_calchash(addr) 425 caddr_t addr; 426{ 427 u_int32_t crc, carry; 428 int i, j; 429 u_int8_t c; 430 431 /* Compute CRC for the address value. */ 432 crc = 0xFFFFFFFF; /* initial value */ 433 434 for (i = 0; i < 6; i++) { 435 c = *(addr + i); 436 for (j = 0; j < 8; j++) { 437 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 438 crc <<= 1; 439 c >>= 1; 440 if (carry) 441 crc = (crc ^ 0x04c11db6) | carry; 442 } 443 } 444 445 /* return the filter bit position */ 446 return((crc >> 25) & 0x0000007F); 447} 448 449static void sis_setmulti(sc) 450 struct sis_softc *sc; 451{ 452 struct ifnet *ifp; 453 struct ifmultiaddr *ifma; 454 u_int32_t h = 0, i, filtsave; 455 456 ifp = &sc->arpcom.ac_if; 457 458 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 459 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 460 return; 461 } 462 463 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 464 465 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 466 467 /* first, zot all the existing hash bits */ 468 for (i = 0; i < 8; i++) { 469 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + ((i * 16) >> 4)) << 16); 470 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 471 } 472 473 /* now program new ones */ 474 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 475 ifma = ifma->ifma_link.le_next) { 476 if (ifma->ifma_addr->sa_family != AF_LINK) 477 continue; 478 h = sis_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 479 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + (h >> 4)) << 16); 480 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << (h & 0xF))); 481 } 482 483 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 484 485 return; 486} 487 488static void sis_reset(sc) 489 struct sis_softc *sc; 490{ 491 register int i; 492 493 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 494 495 for (i = 0; i < SIS_TIMEOUT; i++) { 496 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 497 break; 498 } 499 500 if (i == SIS_TIMEOUT) 501 printf("sis%d: reset never completed\n", sc->sis_unit); 502 503 /* Wait a little while for the chip to get its brains in order. */ 504 DELAY(1000); 505 return; 506} 507 508/* 509 * Probe for an SiS chip. Check the PCI vendor and device 510 * IDs against our list and return a device name if we find a match. 511 */ 512static int sis_probe(dev) 513 device_t dev; 514{ 515 struct sis_type *t; 516 517 t = sis_devs; 518 519 while(t->sis_name != NULL) { 520 if ((pci_get_vendor(dev) == t->sis_vid) && 521 (pci_get_device(dev) == t->sis_did)) { 522 device_set_desc(dev, t->sis_name); 523 return(0); 524 } 525 t++; 526 } 527 528 return(ENXIO); 529} 530 531/* 532 * Attach the interface. Allocate softc structures, do ifmedia 533 * setup and ethernet/BPF attach. 534 */ 535static int sis_attach(dev) 536 device_t dev; 537{ 538 int s; 539 u_char eaddr[ETHER_ADDR_LEN]; 540 u_int32_t command; 541 struct sis_softc *sc; 542 struct ifnet *ifp; 543 int unit, error = 0, rid; 544 545 s = splimp(); 546 547 sc = device_get_softc(dev); 548 unit = device_get_unit(dev); 549 bzero(sc, sizeof(struct sis_softc)); 550 551 if (pci_get_device(dev) == SIS_DEVICEID_900) 552 sc->sis_type = SIS_TYPE_900; 553 if (pci_get_device(dev) == SIS_DEVICEID_7016) 554 sc->sis_type = SIS_TYPE_7016; 555 556 /* 557 * Handle power management nonsense. 558 */ 559 560 command = pci_read_config(dev, SIS_PCI_CAPID, 4) & 0x000000FF; 561 if (command == 0x01) { 562 563 command = pci_read_config(dev, SIS_PCI_PWRMGMTCTRL, 4); 564 if (command & SIS_PSTATE_MASK) { 565 u_int32_t iobase, membase, irq; 566 567 /* Save important PCI config data. */ 568 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4); 569 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4); 570 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4); 571 572 /* Reset the power state. */ 573 printf("sis%d: chip is in D%d power mode " 574 "-- setting to D0\n", unit, command & SIS_PSTATE_MASK); 575 command &= 0xFFFFFFFC; 576 pci_write_config(dev, SIS_PCI_PWRMGMTCTRL, command, 4); 577 578 /* Restore PCI config data. */ 579 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4); 580 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4); 581 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4); 582 } 583 } 584 585 /* 586 * Map control/status registers. 587 */ 588 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 589 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 590 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4); 591 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 592 593#ifdef SIS_USEIOSPACE 594 if (!(command & PCIM_CMD_PORTEN)) { 595 printf("sis%d: failed to enable I/O ports!\n", unit); 596 error = ENXIO;; 597 goto fail; 598 } 599#else 600 if (!(command & PCIM_CMD_MEMEN)) { 601 printf("sis%d: failed to enable memory mapping!\n", unit); 602 error = ENXIO;; 603 goto fail; 604 } 605#endif 606 607 rid = SIS_RID; 608 sc->sis_res = bus_alloc_resource(dev, SIS_RES, &rid, 609 0, ~0, 1, RF_ACTIVE); 610 611 if (sc->sis_res == NULL) { 612 printf("sis%d: couldn't map ports/memory\n", unit); 613 error = ENXIO; 614 goto fail; 615 } 616 617 sc->sis_btag = rman_get_bustag(sc->sis_res); 618 sc->sis_bhandle = rman_get_bushandle(sc->sis_res); 619 620 /* Allocate interrupt */ 621 rid = 0; 622 sc->sis_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 623 RF_SHAREABLE | RF_ACTIVE); 624 625 if (sc->sis_irq == NULL) { 626 printf("sis%d: couldn't map interrupt\n", unit); 627 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 628 error = ENXIO; 629 goto fail; 630 } 631 632 error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET, 633 sis_intr, sc, &sc->sis_intrhand); 634 635 if (error) { 636 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_res); 637 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 638 printf("sis%d: couldn't set up irq\n", unit); 639 goto fail; 640 } 641 642 /* Reset the adapter. */ 643 sis_reset(sc); 644 645 /* 646 * Get station address from the EEPROM. 647 */ 648 sis_read_eeprom(sc, (caddr_t)&eaddr, SIS_EE_NODEADDR, 3, 0); 649 650 /* 651 * A SiS chip was detected. Inform the world. 652 */ 653 printf("sis%d: Ethernet address: %6D\n", unit, eaddr, ":"); 654 655 sc->sis_unit = unit; 656 callout_handle_init(&sc->sis_stat_ch); 657 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 658 659 sc->sis_ldata = contigmalloc(sizeof(struct sis_list_data), M_DEVBUF, 660 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 661 662 if (sc->sis_ldata == NULL) { 663 printf("sis%d: no memory for list buffers!\n", unit); 664 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 665 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 666 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 667 error = ENXIO; 668 goto fail; 669 } 670 bzero(sc->sis_ldata, sizeof(struct sis_list_data)); 671 672 ifp = &sc->arpcom.ac_if; 673 ifp->if_softc = sc; 674 ifp->if_unit = unit; 675 ifp->if_name = "sis"; 676 ifp->if_mtu = ETHERMTU; 677 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 678 ifp->if_ioctl = sis_ioctl; 679 ifp->if_output = ether_output; 680 ifp->if_start = sis_start; 681 ifp->if_watchdog = sis_watchdog; 682 ifp->if_init = sis_init; 683 ifp->if_baudrate = 10000000; 684 ifp->if_snd.ifq_maxlen = SIS_TX_LIST_CNT - 1; 685 686 /* 687 * Do MII setup. 688 */ 689 if (mii_phy_probe(dev, &sc->sis_miibus, 690 sis_ifmedia_upd, sis_ifmedia_sts)) { 691 printf("sis%d: MII without any PHY!\n", sc->sis_unit); 692 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 693 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 694 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 695 error = ENXIO; 696 goto fail; 697 } 698 699 /* 700 * Call MI attach routines. 701 */ 702 if_attach(ifp); 703 ether_ifattach(ifp); 704 callout_handle_init(&sc->sis_stat_ch); 705 706 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 707 708fail: 709 splx(s); 710 return(error); 711} 712 713static int sis_detach(dev) 714 device_t dev; 715{ 716 struct sis_softc *sc; 717 struct ifnet *ifp; 718 int s; 719 720 s = splimp(); 721 722 sc = device_get_softc(dev); 723 ifp = &sc->arpcom.ac_if; 724 725 sis_reset(sc); 726 sis_stop(sc); 727 if_detach(ifp); 728 729 bus_generic_detach(dev); 730 device_delete_child(dev, sc->sis_miibus); 731 732 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 733 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 734 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 735 736 contigfree(sc->sis_ldata, sizeof(struct sis_list_data), M_DEVBUF); 737 738 splx(s); 739 740 return(0); 741} 742 743/* 744 * Initialize the transmit descriptors. 745 */ 746static int sis_list_tx_init(sc) 747 struct sis_softc *sc; 748{ 749 struct sis_list_data *ld; 750 struct sis_ring_data *cd; 751 int i; 752 753 cd = &sc->sis_cdata; 754 ld = sc->sis_ldata; 755 756 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 757 if (i == (SIS_TX_LIST_CNT - 1)) { 758 ld->sis_tx_list[i].sis_nextdesc = 759 &ld->sis_tx_list[0]; 760 ld->sis_tx_list[i].sis_next = 761 vtophys(&ld->sis_tx_list[0]); 762 } else { 763 ld->sis_tx_list[i].sis_nextdesc = 764 &ld->sis_tx_list[i + 1]; 765 ld->sis_tx_list[i].sis_next = 766 vtophys(&ld->sis_tx_list[i + 1]); 767 } 768 ld->sis_tx_list[i].sis_mbuf = NULL; 769 ld->sis_tx_list[i].sis_ptr = 0; 770 ld->sis_tx_list[i].sis_ctl = 0; 771 } 772 773 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0; 774 775 return(0); 776} 777 778 779/* 780 * Initialize the RX descriptors and allocate mbufs for them. Note that 781 * we arrange the descriptors in a closed ring, so that the last descriptor 782 * points back to the first. 783 */ 784static int sis_list_rx_init(sc) 785 struct sis_softc *sc; 786{ 787 struct sis_list_data *ld; 788 struct sis_ring_data *cd; 789 int i; 790 791 ld = sc->sis_ldata; 792 cd = &sc->sis_cdata; 793 794 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 795 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS) 796 return(ENOBUFS); 797 if (i == (SIS_RX_LIST_CNT - 1)) { 798 ld->sis_rx_list[i].sis_nextdesc = 799 &ld->sis_rx_list[0]; 800 ld->sis_rx_list[i].sis_next = 801 vtophys(&ld->sis_rx_list[0]); 802 } else { 803 ld->sis_rx_list[i].sis_nextdesc = 804 &ld->sis_rx_list[i + 1]; 805 ld->sis_rx_list[i].sis_next = 806 vtophys(&ld->sis_rx_list[i + 1]); 807 } 808 } 809 810 cd->sis_rx_prod = 0; 811 812 return(0); 813} 814 815/* 816 * Initialize an RX descriptor and attach an MBUF cluster. 817 */ 818static int sis_newbuf(sc, c, m) 819 struct sis_softc *sc; 820 struct sis_desc *c; 821 struct mbuf *m; 822{ 823 struct mbuf *m_new = NULL; 824 825 if (m == NULL) { 826 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 827 if (m_new == NULL) { 828 printf("sis%d: no memory for rx list " 829 "-- packet dropped!\n", sc->sis_unit); 830 return(ENOBUFS); 831 } 832 833 MCLGET(m_new, M_DONTWAIT); 834 if (!(m_new->m_flags & M_EXT)) { 835 printf("sis%d: no memory for rx list " 836 "-- packet dropped!\n", sc->sis_unit); 837 m_freem(m_new); 838 return(ENOBUFS); 839 } 840 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 841 } else { 842 m_new = m; 843 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 844 m_new->m_data = m_new->m_ext.ext_buf; 845 } 846 847 m_adj(m_new, sizeof(u_int64_t)); 848 849 c->sis_mbuf = m_new; 850 c->sis_ptr = vtophys(mtod(m_new, caddr_t)); 851 c->sis_ctl = SIS_RXLEN; 852 853 return(0); 854} 855 856/* 857 * A frame has been uploaded: pass the resulting mbuf chain up to 858 * the higher level protocols. 859 */ 860static void sis_rxeof(sc) 861 struct sis_softc *sc; 862{ 863 struct ether_header *eh; 864 struct mbuf *m; 865 struct ifnet *ifp; 866 struct sis_desc *cur_rx; 867 int i, total_len = 0; 868 u_int32_t rxstat; 869 870 ifp = &sc->arpcom.ac_if; 871 i = sc->sis_cdata.sis_rx_prod; 872 873 while(SIS_OWNDESC(&sc->sis_ldata->sis_rx_list[i])) { 874 struct mbuf *m0 = NULL; 875 876 cur_rx = &sc->sis_ldata->sis_rx_list[i]; 877 rxstat = cur_rx->sis_rxstat; 878 m = cur_rx->sis_mbuf; 879 cur_rx->sis_mbuf = NULL; 880 total_len = SIS_RXBYTES(cur_rx); 881 SIS_INC(i, SIS_RX_LIST_CNT); 882 883 /* 884 * If an error occurs, update stats, clear the 885 * status word and leave the mbuf cluster in place: 886 * it should simply get re-used next time this descriptor 887 * comes up in the ring. 888 */ 889 if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 890 ifp->if_ierrors++; 891 if (rxstat & SIS_RXSTAT_COLL) 892 ifp->if_collisions++; 893 sis_newbuf(sc, cur_rx, m); 894 continue; 895 } 896 897 /* No errors; receive the packet. */ 898 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 899 total_len + ETHER_ALIGN, 0, ifp, NULL); 900 sis_newbuf(sc, cur_rx, m); 901 if (m0 == NULL) { 902 ifp->if_ierrors++; 903 continue; 904 } 905 m_adj(m0, ETHER_ALIGN); 906 m = m0; 907 908 ifp->if_ipackets++; 909 eh = mtod(m, struct ether_header *); 910 911 /* 912 * Handle BPF listeners. Let the BPF user see the packet, but 913 * don't pass it up to the ether_input() layer unless it's 914 * a broadcast packet, multicast packet, matches our ethernet 915 * address or the interface is in promiscuous mode. 916 */ 917 if (ifp->if_bpf) { 918 bpf_mtap(ifp, m); 919 if (ifp->if_flags & IFF_PROMISC && 920 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 921 ETHER_ADDR_LEN) && !(eh->ether_dhost[0] & 1))) { 922 m_freem(m); 923 continue; 924 } 925 } 926 927 /* Remove header from mbuf and pass it on. */ 928 m_adj(m, sizeof(struct ether_header)); 929 ether_input(ifp, eh, m); 930 } 931 932 sc->sis_cdata.sis_rx_prod = i; 933 934 return; 935} 936 937void sis_rxeoc(sc) 938 struct sis_softc *sc; 939{ 940 sis_rxeof(sc); 941 sis_init(sc); 942 return; 943} 944 945/* 946 * A frame was downloaded to the chip. It's safe for us to clean up 947 * the list buffers. 948 */ 949 950static void sis_txeof(sc) 951 struct sis_softc *sc; 952{ 953 struct sis_desc *cur_tx = NULL; 954 struct ifnet *ifp; 955 u_int32_t idx; 956 957 ifp = &sc->arpcom.ac_if; 958 959 /* Clear the timeout timer. */ 960 ifp->if_timer = 0; 961 962 /* 963 * Go through our tx list and free mbufs for those 964 * frames that have been transmitted. 965 */ 966 idx = sc->sis_cdata.sis_tx_cons; 967 while (idx != sc->sis_cdata.sis_tx_prod) { 968 cur_tx = &sc->sis_ldata->sis_tx_list[idx]; 969 970 if (SIS_OWNDESC(cur_tx)) 971 break; 972 973 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) { 974 sc->sis_cdata.sis_tx_cnt--; 975 SIS_INC(idx, SIS_TX_LIST_CNT); 976 continue; 977 } 978 979 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 980 ifp->if_oerrors++; 981 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 982 ifp->if_collisions++; 983 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 984 ifp->if_collisions++; 985 } 986 987 ifp->if_collisions += 988 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 989 990 ifp->if_opackets++; 991 if (cur_tx->sis_mbuf != NULL) { 992 m_freem(cur_tx->sis_mbuf); 993 cur_tx->sis_mbuf = NULL; 994 } 995 996 sc->sis_cdata.sis_tx_cnt--; 997 SIS_INC(idx, SIS_TX_LIST_CNT); 998 ifp->if_timer = 0; 999 } 1000 1001 sc->sis_cdata.sis_tx_cons = idx; 1002 1003 if (cur_tx != NULL) 1004 ifp->if_flags &= ~IFF_OACTIVE; 1005 1006 return; 1007} 1008 1009static void sis_tick(xsc) 1010 void *xsc; 1011{ 1012 struct sis_softc *sc; 1013 struct mii_data *mii; 1014 int s; 1015 1016 s = splimp(); 1017 1018 sc = xsc; 1019 mii = device_get_softc(sc->sis_miibus); 1020 mii_tick(mii); 1021 sc->sis_stat_ch = timeout(sis_tick, sc, hz); 1022 1023 splx(s); 1024 1025 return; 1026} 1027 1028static void sis_intr(arg) 1029 void *arg; 1030{ 1031 struct sis_softc *sc; 1032 struct ifnet *ifp; 1033 u_int32_t status; 1034 1035 sc = arg; 1036 ifp = &sc->arpcom.ac_if; 1037 1038 /* Supress unwanted interrupts */ 1039 if (!(ifp->if_flags & IFF_UP)) { 1040 sis_stop(sc); 1041 return; 1042 } 1043 1044 /* Disable interrupts. */ 1045 CSR_WRITE_4(sc, SIS_IER, 0); 1046 1047 for (;;) { 1048 /* Reading the ISR register clears all interrupts. */ 1049 status = CSR_READ_4(sc, SIS_ISR); 1050 1051 if ((status & SIS_INTRS) == 0) 1052 break; 1053 1054 if ((status & SIS_ISR_TX_OK) || 1055 (status & SIS_ISR_TX_ERR) || 1056 (status & SIS_ISR_TX_IDLE)) 1057 sis_txeof(sc); 1058 1059 if (status & SIS_ISR_RX_OK) 1060 sis_rxeof(sc); 1061 1062 if ((status & SIS_ISR_RX_ERR) || 1063 (status & SIS_ISR_RX_OFLOW)) { 1064 sis_rxeoc(sc); 1065 } 1066 1067 if (status & SIS_ISR_SYSERR) { 1068 sis_reset(sc); 1069 sis_init(sc); 1070 } 1071 } 1072 1073 /* Re-enable interrupts. */ 1074 CSR_WRITE_4(sc, SIS_IER, 1); 1075 1076 if (ifp->if_snd.ifq_head != NULL) 1077 sis_start(ifp); 1078 1079 return; 1080} 1081 1082/* 1083 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1084 * pointers to the fragment pointers. 1085 */ 1086static int sis_encap(sc, m_head, txidx) 1087 struct sis_softc *sc; 1088 struct mbuf *m_head; 1089 u_int32_t *txidx; 1090{ 1091 struct sis_desc *f = NULL; 1092 struct mbuf *m; 1093 int frag, cur, cnt = 0; 1094 1095 /* 1096 * Start packing the mbufs in this chain into 1097 * the fragment pointers. Stop when we run out 1098 * of fragments or hit the end of the mbuf chain. 1099 */ 1100 m = m_head; 1101 cur = frag = *txidx; 1102 1103 for (m = m_head; m != NULL; m = m->m_next) { 1104 if (m->m_len != 0) { 1105 if ((SIS_TX_LIST_CNT - 1106 (sc->sis_cdata.sis_tx_cnt + cnt)) < 2) 1107 return(ENOBUFS); 1108 f = &sc->sis_ldata->sis_tx_list[frag]; 1109 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; 1110 f->sis_ptr = vtophys(mtod(m, vm_offset_t)); 1111 if (cnt != 0) 1112 f->sis_ctl |= SIS_CMDSTS_OWN; 1113 cur = frag; 1114 SIS_INC(frag, SIS_TX_LIST_CNT); 1115 cnt++; 1116 } 1117 } 1118 1119 if (m != NULL) 1120 return(ENOBUFS); 1121 1122 sc->sis_ldata->sis_tx_list[cur].sis_mbuf = m_head; 1123 sc->sis_ldata->sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1124 sc->sis_ldata->sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1125 sc->sis_cdata.sis_tx_cnt += cnt; 1126 *txidx = frag; 1127 1128 return(0); 1129} 1130 1131/* 1132 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1133 * to the mbuf data regions directly in the transmit lists. We also save a 1134 * copy of the pointers since the transmit list fragment pointers are 1135 * physical addresses. 1136 */ 1137 1138static void sis_start(ifp) 1139 struct ifnet *ifp; 1140{ 1141 struct sis_softc *sc; 1142 struct mbuf *m_head = NULL; 1143 u_int32_t idx; 1144 1145 sc = ifp->if_softc; 1146 1147 idx = sc->sis_cdata.sis_tx_prod; 1148 1149 if (ifp->if_flags & IFF_OACTIVE) 1150 return; 1151 1152 while(sc->sis_ldata->sis_tx_list[idx].sis_mbuf == NULL) { 1153 IF_DEQUEUE(&ifp->if_snd, m_head); 1154 if (m_head == NULL) 1155 break; 1156 1157 if (sis_encap(sc, m_head, &idx)) { 1158 IF_PREPEND(&ifp->if_snd, m_head); 1159 ifp->if_flags |= IFF_OACTIVE; 1160 break; 1161 } 1162 1163 /* 1164 * If there's a BPF listener, bounce a copy of this frame 1165 * to him. 1166 */ 1167 if (ifp->if_bpf) 1168 bpf_mtap(ifp, m_head); 1169 1170 } 1171 1172 /* Transmit */ 1173 sc->sis_cdata.sis_tx_prod = idx; 1174 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 1175 1176 /* 1177 * Set a timeout in case the chip goes out to lunch. 1178 */ 1179 ifp->if_timer = 5; 1180 1181 return; 1182} 1183 1184static void sis_init(xsc) 1185 void *xsc; 1186{ 1187 struct sis_softc *sc = xsc; 1188 struct ifnet *ifp = &sc->arpcom.ac_if; 1189 struct mii_data *mii; 1190 int s; 1191 1192 s = splimp(); 1193 1194 /* 1195 * Cancel pending I/O and free all RX/TX buffers. 1196 */ 1197 sis_stop(sc); 1198 1199 mii = device_get_softc(sc->sis_miibus); 1200 1201 /* Set MAC address */ 1202 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 1203 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1204 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1205 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 1206 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1207 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1208 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 1209 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1210 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1211 1212 /* Init circular RX list. */ 1213 if (sis_list_rx_init(sc) == ENOBUFS) { 1214 printf("sis%d: initialization failed: no " 1215 "memory for rx buffers\n", sc->sis_unit); 1216 sis_stop(sc); 1217 (void)splx(s); 1218 return; 1219 } 1220 1221 /* 1222 * Init tx descriptors. 1223 */ 1224 sis_list_tx_init(sc); 1225 1226 /* If we want promiscuous mode, set the allframes bit. */ 1227 if (ifp->if_flags & IFF_PROMISC) { 1228 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1229 } else { 1230 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1231 } 1232 1233 /* 1234 * Set the capture broadcast bit to capture broadcast frames. 1235 */ 1236 if (ifp->if_flags & IFF_BROADCAST) { 1237 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1238 } else { 1239 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1240 } 1241 1242 /* 1243 * Load the multicast filter. 1244 */ 1245 sis_setmulti(sc); 1246 1247 /* Turn the receive filter on */ 1248 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 1249 1250 /* 1251 * Load the address of the RX and TX lists. 1252 */ 1253 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 1254 vtophys(&sc->sis_ldata->sis_rx_list[0])); 1255 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 1256 vtophys(&sc->sis_ldata->sis_tx_list[0])); 1257 1258 /* Set RX configuration */ 1259 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG); 1260 /* Set TX configuration */ 1261 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG); 1262 1263 /* 1264 * Enable interrupts. 1265 */ 1266 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 1267 CSR_WRITE_4(sc, SIS_IER, 1); 1268 1269 /* Enable receiver and transmitter. */ 1270 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 1271 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1272 1273 mii_mediachg(mii); 1274 1275 ifp->if_flags |= IFF_RUNNING; 1276 ifp->if_flags &= ~IFF_OACTIVE; 1277 1278 (void)splx(s); 1279 1280 sc->sis_stat_ch = timeout(sis_tick, sc, hz); 1281 1282 return; 1283} 1284 1285/* 1286 * Set media options. 1287 */ 1288static int sis_ifmedia_upd(ifp) 1289 struct ifnet *ifp; 1290{ 1291 struct sis_softc *sc; 1292 1293 sc = ifp->if_softc; 1294 1295 if (ifp->if_flags & IFF_UP) 1296 sis_init(sc); 1297 1298 return(0); 1299} 1300 1301/* 1302 * Report current media status. 1303 */ 1304static void sis_ifmedia_sts(ifp, ifmr) 1305 struct ifnet *ifp; 1306 struct ifmediareq *ifmr; 1307{ 1308 struct sis_softc *sc; 1309 struct mii_data *mii; 1310 1311 sc = ifp->if_softc; 1312 1313 mii = device_get_softc(sc->sis_miibus); 1314 mii_pollstat(mii); 1315 ifmr->ifm_active = mii->mii_media_active; 1316 ifmr->ifm_status = mii->mii_media_status; 1317 1318 return; 1319} 1320 1321static int sis_ioctl(ifp, command, data) 1322 struct ifnet *ifp; 1323 u_long command; 1324 caddr_t data; 1325{ 1326 struct sis_softc *sc = ifp->if_softc; 1327 struct ifreq *ifr = (struct ifreq *) data; 1328 struct mii_data *mii; 1329 int s, error = 0; 1330 1331 s = splimp(); 1332 1333 switch(command) { 1334 case SIOCSIFADDR: 1335 case SIOCGIFADDR: 1336 case SIOCSIFMTU: 1337 error = ether_ioctl(ifp, command, data); 1338 break; 1339 case SIOCSIFFLAGS: 1340 if (ifp->if_flags & IFF_UP) { 1341 sis_init(sc); 1342 } else { 1343 if (ifp->if_flags & IFF_RUNNING) 1344 sis_stop(sc); 1345 } 1346 error = 0; 1347 break; 1348 case SIOCADDMULTI: 1349 case SIOCDELMULTI: 1350 sis_setmulti(sc); 1351 error = 0; 1352 break; 1353 case SIOCGIFMEDIA: 1354 case SIOCSIFMEDIA: 1355 mii = device_get_softc(sc->sis_miibus); 1356 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1357 break; 1358 default: 1359 error = EINVAL; 1360 break; 1361 } 1362 1363 (void)splx(s); 1364 1365 return(error); 1366} 1367 1368static void sis_watchdog(ifp) 1369 struct ifnet *ifp; 1370{ 1371 struct sis_softc *sc; 1372 1373 sc = ifp->if_softc; 1374 1375 ifp->if_oerrors++; 1376 printf("sis%d: watchdog timeout\n", sc->sis_unit); 1377 1378 sis_stop(sc); 1379 sis_reset(sc); 1380 sis_init(sc); 1381 1382 if (ifp->if_snd.ifq_head != NULL) 1383 sis_start(ifp); 1384 1385 return; 1386} 1387 1388/* 1389 * Stop the adapter and free any mbufs allocated to the 1390 * RX and TX lists. 1391 */ 1392static void sis_stop(sc) 1393 struct sis_softc *sc; 1394{ 1395 register int i; 1396 struct ifnet *ifp; 1397 1398 ifp = &sc->arpcom.ac_if; 1399 ifp->if_timer = 0; 1400 1401 untimeout(sis_tick, sc, sc->sis_stat_ch); 1402 CSR_WRITE_4(sc, SIS_IER, 0); 1403 CSR_WRITE_4(sc, SIS_IMR, 0); 1404 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 1405 DELAY(1000); 1406 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 1407 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 1408 1409 /* 1410 * Free data in the RX lists. 1411 */ 1412 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1413 if (sc->sis_ldata->sis_rx_list[i].sis_mbuf != NULL) { 1414 m_freem(sc->sis_ldata->sis_rx_list[i].sis_mbuf); 1415 sc->sis_ldata->sis_rx_list[i].sis_mbuf = NULL; 1416 } 1417 } 1418 bzero((char *)&sc->sis_ldata->sis_rx_list, 1419 sizeof(sc->sis_ldata->sis_rx_list)); 1420 1421 /* 1422 * Free the TX list buffers. 1423 */ 1424 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1425 if (sc->sis_ldata->sis_tx_list[i].sis_mbuf != NULL) { 1426 m_freem(sc->sis_ldata->sis_tx_list[i].sis_mbuf); 1427 sc->sis_ldata->sis_tx_list[i].sis_mbuf = NULL; 1428 } 1429 } 1430 1431 bzero((char *)&sc->sis_ldata->sis_tx_list, 1432 sizeof(sc->sis_ldata->sis_tx_list)); 1433 1434 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1435 1436 return; 1437} 1438 1439/* 1440 * Stop all chip I/O so that the kernel's probe routines don't 1441 * get confused by errant DMAs when rebooting. 1442 */ 1443static void sis_shutdown(dev) 1444 device_t dev; 1445{ 1446 struct sis_softc *sc; 1447 1448 sc = device_get_softc(dev); 1449 1450 sis_reset(sc); 1451 sis_stop(sc); 1452 1453 return; 1454} 1455