if_sis.c revision 206909
1139825Simp/*- 2139740Sphk * Copyright (c) 2005 Poul-Henning Kamp <phk@FreeBSD.org> 350974Swpaul * Copyright (c) 1997, 1998, 1999 450974Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 550974Swpaul * 650974Swpaul * Redistribution and use in source and binary forms, with or without 750974Swpaul * modification, are permitted provided that the following conditions 850974Swpaul * are met: 950974Swpaul * 1. Redistributions of source code must retain the above copyright 1050974Swpaul * notice, this list of conditions and the following disclaimer. 1150974Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1250974Swpaul * notice, this list of conditions and the following disclaimer in the 1350974Swpaul * documentation and/or other materials provided with the distribution. 1450974Swpaul * 3. All advertising materials mentioning features or use of this software 1550974Swpaul * must display the following acknowledgement: 1650974Swpaul * This product includes software developed by Bill Paul. 1750974Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1850974Swpaul * may be used to endorse or promote products derived from this software 1950974Swpaul * without specific prior written permission. 2050974Swpaul * 2150974Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2250974Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2350974Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2450974Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2550974Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2650974Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2750974Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2850974Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2950974Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3050974Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3150974Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3250974Swpaul */ 3350974Swpaul 34122678Sobrien#include <sys/cdefs.h> 35122678Sobrien__FBSDID("$FreeBSD: head/sys/dev/sis/if_sis.c 206909 2010-04-20 19:30:12Z brucec $"); 36122678Sobrien 3750974Swpaul/* 3850974Swpaul * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 3950974Swpaul * available from http://www.sis.com.tw. 4050974Swpaul * 4164963Swpaul * This driver also supports the NatSemi DP83815. Datasheets are 4264963Swpaul * available from http://www.national.com. 4364963Swpaul * 4450974Swpaul * Written by Bill Paul <wpaul@ee.columbia.edu> 4550974Swpaul * Electrical Engineering Department 4650974Swpaul * Columbia University, New York City 4750974Swpaul */ 4850974Swpaul/* 4950974Swpaul * The SiS 900 is a fairly simple chip. It uses bus master DMA with 5050974Swpaul * simple TX and RX descriptors of 3 longwords in size. The receiver 5150974Swpaul * has a single perfect filter entry for the station address and a 5250974Swpaul * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 5350974Swpaul * transceiver while the 7016 requires an external transceiver chip. 5450974Swpaul * Both chips offer the standard bit-bang MII interface as well as 5550974Swpaul * an enchanced PHY interface which simplifies accessing MII registers. 5650974Swpaul * 5750974Swpaul * The only downside to this chipset is that RX descriptors must be 5850974Swpaul * longword aligned. 5950974Swpaul */ 6050974Swpaul 61150968Sglebius#ifdef HAVE_KERNEL_OPTION_HEADERS 62150968Sglebius#include "opt_device_polling.h" 63150968Sglebius#endif 64150968Sglebius 6550974Swpaul#include <sys/param.h> 6650974Swpaul#include <sys/systm.h> 6750974Swpaul#include <sys/sockio.h> 6850974Swpaul#include <sys/mbuf.h> 6950974Swpaul#include <sys/malloc.h> 7050974Swpaul#include <sys/kernel.h> 71129876Sphk#include <sys/module.h> 7250974Swpaul#include <sys/socket.h> 7350974Swpaul 7450974Swpaul#include <net/if.h> 7550974Swpaul#include <net/if_arp.h> 7650974Swpaul#include <net/ethernet.h> 7750974Swpaul#include <net/if_dl.h> 7850974Swpaul#include <net/if_media.h> 7987390Sjhay#include <net/if_types.h> 8087390Sjhay#include <net/if_vlan_var.h> 8150974Swpaul 8250974Swpaul#include <net/bpf.h> 8350974Swpaul 8450974Swpaul#include <machine/bus.h> 8550974Swpaul#include <machine/resource.h> 8650974Swpaul#include <sys/bus.h> 8750974Swpaul#include <sys/rman.h> 8850974Swpaul 8950974Swpaul#include <dev/mii/mii.h> 9050974Swpaul#include <dev/mii/miivar.h> 9150974Swpaul 92119288Simp#include <dev/pci/pcireg.h> 93119288Simp#include <dev/pci/pcivar.h> 9450974Swpaul 9550974Swpaul#define SIS_USEIOSPACE 9650974Swpaul 97181524Simp#include <dev/sis/if_sisreg.h> 9850974Swpaul 99113506SmdoddMODULE_DEPEND(sis, pci, 1, 1, 1); 100113506SmdoddMODULE_DEPEND(sis, ether, 1, 1, 1); 10159758SpeterMODULE_DEPEND(sis, miibus, 1, 1, 1); 10259758Speter 103151545Simp/* "device miibus" required. See GENERIC if you get errors here. */ 10450974Swpaul#include "miibus_if.h" 10550974Swpaul 106150369Sphk#define SIS_LOCK(_sc) mtx_lock(&(_sc)->sis_mtx) 107150369Sphk#define SIS_UNLOCK(_sc) mtx_unlock(&(_sc)->sis_mtx) 108150369Sphk#define SIS_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sis_mtx, MA_OWNED) 109150369Sphk 11050974Swpaul/* 111150369Sphk * register space access macros 112150369Sphk */ 113150526Sphk#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sis_res[0], reg, val) 114150369Sphk 115150526Sphk#define CSR_READ_4(sc, reg) bus_read_4(sc->sis_res[0], reg) 116150369Sphk 117150526Sphk#define CSR_READ_2(sc, reg) bus_read_2(sc->sis_res[0], reg) 118150369Sphk 119150369Sphk/* 12050974Swpaul * Various supported device vendors/types and their names. 12150974Swpaul */ 12250974Swpaulstatic struct sis_type sis_devs[] = { 12350974Swpaul { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 12450974Swpaul { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 125119712Sphk { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" }, 12650974Swpaul { 0, 0, NULL } 12750974Swpaul}; 12850974Swpaul 129139801Sphkstatic int sis_detach(device_t); 130139801Sphkstatic void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *); 131139801Sphkstatic int sis_ifmedia_upd(struct ifnet *); 132139801Sphkstatic void sis_init(void *); 133139801Sphkstatic void sis_initl(struct sis_softc *); 134139801Sphkstatic void sis_intr(void *); 135139801Sphkstatic int sis_ioctl(struct ifnet *, u_long, caddr_t); 136139801Sphkstatic int sis_newbuf(struct sis_softc *, struct sis_desc *, struct mbuf *); 137139801Sphkstatic void sis_start(struct ifnet *); 138139801Sphkstatic void sis_startl(struct ifnet *); 139139801Sphkstatic void sis_stop(struct sis_softc *); 140166940Sdelphijstatic void sis_watchdog(struct sis_softc *); 14150974Swpaul 142150526Sphk 143150526Sphkstatic struct resource_spec sis_res_spec[] = { 14450974Swpaul#ifdef SIS_USEIOSPACE 145150526Sphk { SYS_RES_IOPORT, SIS_PCI_LOIO, RF_ACTIVE}, 14650974Swpaul#else 147150526Sphk { SYS_RES_MEMORY, SIS_PCI_LOMEM, RF_ACTIVE}, 14850974Swpaul#endif 149150526Sphk { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE}, 150150526Sphk { -1, 0 } 151150526Sphk}; 15250974Swpaul 15350974Swpaul#define SIS_SETBIT(sc, reg, x) \ 15450974Swpaul CSR_WRITE_4(sc, reg, \ 15550974Swpaul CSR_READ_4(sc, reg) | (x)) 15650974Swpaul 15750974Swpaul#define SIS_CLRBIT(sc, reg, x) \ 15850974Swpaul CSR_WRITE_4(sc, reg, \ 15950974Swpaul CSR_READ_4(sc, reg) & ~(x)) 16050974Swpaul 16150974Swpaul#define SIO_SET(x) \ 16250974Swpaul CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 16350974Swpaul 16450974Swpaul#define SIO_CLR(x) \ 16550974Swpaul CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 16650974Swpaul 16781713Swpaulstatic void 168139740Sphksis_dma_map_desc_next(void *arg, bus_dma_segment_t *segs, int nseg, int error) 16981713Swpaul{ 17081713Swpaul struct sis_desc *r; 17181713Swpaul 17281713Swpaul r = arg; 17381713Swpaul r->sis_next = segs->ds_addr; 17481713Swpaul} 17581713Swpaul 17681713Swpaulstatic void 177139740Sphksis_dma_map_desc_ptr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 17881713Swpaul{ 17981713Swpaul struct sis_desc *r; 18081713Swpaul 18181713Swpaul r = arg; 18281713Swpaul r->sis_ptr = segs->ds_addr; 18381713Swpaul} 18481713Swpaul 18581713Swpaulstatic void 186139740Sphksis_dma_map_ring(void *arg, bus_dma_segment_t *segs, int nseg, int error) 18781713Swpaul{ 18881713Swpaul u_int32_t *p; 18981713Swpaul 19081713Swpaul p = arg; 19181713Swpaul *p = segs->ds_addr; 19281713Swpaul} 19381713Swpaul 19462672Swpaul/* 19562672Swpaul * Routine to reverse the bits in a word. Stolen almost 19662672Swpaul * verbatim from /usr/games/fortune. 19762672Swpaul */ 198139740Sphkstatic uint16_t 199139740Sphksis_reverse(uint16_t n) 20062672Swpaul{ 20162672Swpaul n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 20262672Swpaul n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 20362672Swpaul n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 20462672Swpaul n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 20562672Swpaul 20662672Swpaul return(n); 20762672Swpaul} 20862672Swpaul 209102334Salfredstatic void 210139740Sphksis_delay(struct sis_softc *sc) 21150974Swpaul{ 21250974Swpaul int idx; 21350974Swpaul 21450974Swpaul for (idx = (300 / 33) + 1; idx > 0; idx--) 21550974Swpaul CSR_READ_4(sc, SIS_CSR); 21650974Swpaul} 21750974Swpaul 218102334Salfredstatic void 219139740Sphksis_eeprom_idle(struct sis_softc *sc) 22050974Swpaul{ 221139708Sphk int i; 22250974Swpaul 22350974Swpaul SIO_SET(SIS_EECTL_CSEL); 22450974Swpaul sis_delay(sc); 22550974Swpaul SIO_SET(SIS_EECTL_CLK); 22650974Swpaul sis_delay(sc); 22750974Swpaul 22850974Swpaul for (i = 0; i < 25; i++) { 22950974Swpaul SIO_CLR(SIS_EECTL_CLK); 23050974Swpaul sis_delay(sc); 23150974Swpaul SIO_SET(SIS_EECTL_CLK); 23250974Swpaul sis_delay(sc); 23350974Swpaul } 23450974Swpaul 23550974Swpaul SIO_CLR(SIS_EECTL_CLK); 23650974Swpaul sis_delay(sc); 23750974Swpaul SIO_CLR(SIS_EECTL_CSEL); 23850974Swpaul sis_delay(sc); 23950974Swpaul CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 24050974Swpaul} 24150974Swpaul 24250974Swpaul/* 24350974Swpaul * Send a read command and address to the EEPROM, check for ACK. 24450974Swpaul */ 245102334Salfredstatic void 246139740Sphksis_eeprom_putbyte(struct sis_softc *sc, int addr) 24750974Swpaul{ 248139708Sphk int d, i; 24950974Swpaul 25050974Swpaul d = addr | SIS_EECMD_READ; 25150974Swpaul 25250974Swpaul /* 25350974Swpaul * Feed in each bit and stobe the clock. 25450974Swpaul */ 25550974Swpaul for (i = 0x400; i; i >>= 1) { 25650974Swpaul if (d & i) { 25750974Swpaul SIO_SET(SIS_EECTL_DIN); 25850974Swpaul } else { 25950974Swpaul SIO_CLR(SIS_EECTL_DIN); 26050974Swpaul } 26150974Swpaul sis_delay(sc); 26250974Swpaul SIO_SET(SIS_EECTL_CLK); 26350974Swpaul sis_delay(sc); 26450974Swpaul SIO_CLR(SIS_EECTL_CLK); 26550974Swpaul sis_delay(sc); 26650974Swpaul } 26750974Swpaul} 26850974Swpaul 26950974Swpaul/* 27050974Swpaul * Read a word of data stored in the EEPROM at address 'addr.' 27150974Swpaul */ 272102334Salfredstatic void 273139740Sphksis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest) 27450974Swpaul{ 275139708Sphk int i; 27650974Swpaul u_int16_t word = 0; 27750974Swpaul 27850974Swpaul /* Force EEPROM to idle state. */ 27950974Swpaul sis_eeprom_idle(sc); 28050974Swpaul 28150974Swpaul /* Enter EEPROM access mode. */ 28250974Swpaul sis_delay(sc); 28362672Swpaul SIO_CLR(SIS_EECTL_CLK); 28462672Swpaul sis_delay(sc); 28550974Swpaul SIO_SET(SIS_EECTL_CSEL); 28650974Swpaul sis_delay(sc); 28750974Swpaul 28850974Swpaul /* 28950974Swpaul * Send address of word we want to read. 29050974Swpaul */ 29150974Swpaul sis_eeprom_putbyte(sc, addr); 29250974Swpaul 29350974Swpaul /* 29450974Swpaul * Start reading bits from EEPROM. 29550974Swpaul */ 29650974Swpaul for (i = 0x8000; i; i >>= 1) { 29750974Swpaul SIO_SET(SIS_EECTL_CLK); 29850974Swpaul sis_delay(sc); 29950974Swpaul if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 30050974Swpaul word |= i; 30150974Swpaul sis_delay(sc); 30250974Swpaul SIO_CLR(SIS_EECTL_CLK); 30350974Swpaul sis_delay(sc); 30450974Swpaul } 30550974Swpaul 30650974Swpaul /* Turn off EEPROM access mode. */ 30750974Swpaul sis_eeprom_idle(sc); 30850974Swpaul 30950974Swpaul *dest = word; 31050974Swpaul} 31150974Swpaul 31250974Swpaul/* 31350974Swpaul * Read a sequence of words from the EEPROM. 31450974Swpaul */ 315102334Salfredstatic void 316139740Sphksis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap) 31750974Swpaul{ 31850974Swpaul int i; 31950974Swpaul u_int16_t word = 0, *ptr; 32050974Swpaul 32150974Swpaul for (i = 0; i < cnt; i++) { 32250974Swpaul sis_eeprom_getword(sc, off + i, &word); 32350974Swpaul ptr = (u_int16_t *)(dest + (i * 2)); 32450974Swpaul if (swap) 32550974Swpaul *ptr = ntohs(word); 32650974Swpaul else 32750974Swpaul *ptr = word; 32850974Swpaul } 32950974Swpaul} 33050974Swpaul 331144243Sobrien#if defined(__i386__) || defined(__amd64__) 332102334Salfredstatic device_t 333139740Sphksis_find_bridge(device_t dev) 33472197Swpaul{ 33572197Swpaul devclass_t pci_devclass; 33672197Swpaul device_t *pci_devices; 33772197Swpaul int pci_count = 0; 33872197Swpaul device_t *pci_children; 33972197Swpaul int pci_childcount = 0; 34072197Swpaul device_t *busp, *childp; 34187994Sarchie device_t child = NULL; 34272197Swpaul int i, j; 34372197Swpaul 34472197Swpaul if ((pci_devclass = devclass_find("pci")) == NULL) 34572197Swpaul return(NULL); 34672197Swpaul 34772197Swpaul devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 34872197Swpaul 34972197Swpaul for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 350182065Simp if (device_get_children(*busp, &pci_children, &pci_childcount)) 351182065Simp continue; 35272197Swpaul for (j = 0, childp = pci_children; 35372197Swpaul j < pci_childcount; j++, childp++) { 35472197Swpaul if (pci_get_vendor(*childp) == SIS_VENDORID && 35572197Swpaul pci_get_device(*childp) == 0x0008) { 35687994Sarchie child = *childp; 357182065Simp free(pci_children, M_TEMP); 35887994Sarchie goto done; 35972197Swpaul } 36072197Swpaul } 361182065Simp free(pci_children, M_TEMP); 36272197Swpaul } 36372197Swpaul 36487994Sarchiedone: 36572197Swpaul free(pci_devices, M_TEMP); 36687994Sarchie return(child); 36772197Swpaul} 36872197Swpaul 369102334Salfredstatic void 370139740Sphksis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off, int cnt) 37172197Swpaul{ 37272197Swpaul device_t bridge; 37372197Swpaul u_int8_t reg; 37472197Swpaul int i; 37572197Swpaul bus_space_tag_t btag; 37672197Swpaul 37772197Swpaul bridge = sis_find_bridge(dev); 37872197Swpaul if (bridge == NULL) 37972197Swpaul return; 38072197Swpaul reg = pci_read_config(bridge, 0x48, 1); 38172197Swpaul pci_write_config(bridge, 0x48, reg|0x40, 1); 38272197Swpaul 38372197Swpaul /* XXX */ 384144243Sobrien#if defined(__i386__) 38572197Swpaul btag = I386_BUS_SPACE_IO; 386144243Sobrien#elif defined(__amd64__) 387144243Sobrien btag = AMD64_BUS_SPACE_IO; 388144243Sobrien#endif 38972197Swpaul 39072197Swpaul for (i = 0; i < cnt; i++) { 39172197Swpaul bus_space_write_1(btag, 0x0, 0x70, i + off); 39272197Swpaul *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 39372197Swpaul } 39472197Swpaul 39572197Swpaul pci_write_config(bridge, 0x48, reg & ~0x40, 1); 39672197Swpaul return; 39772197Swpaul} 39889296Swpaul 399102334Salfredstatic void 400139740Sphksis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest) 40189296Swpaul{ 40289296Swpaul u_int32_t filtsave, csrsave; 40389296Swpaul 40489296Swpaul filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 40589296Swpaul csrsave = CSR_READ_4(sc, SIS_CSR); 40689296Swpaul 40789296Swpaul CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 40889296Swpaul CSR_WRITE_4(sc, SIS_CSR, 0); 40989296Swpaul 41089296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 41189296Swpaul 41289296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 41389296Swpaul ((u_int16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 41489296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 41589296Swpaul ((u_int16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 41689296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 41789296Swpaul ((u_int16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 41889296Swpaul 41989296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 42089296Swpaul CSR_WRITE_4(sc, SIS_CSR, csrsave); 42189296Swpaul return; 42289296Swpaul} 42372197Swpaul#endif 42472197Swpaul 425109060Smbr/* 426109060Smbr * Sync the PHYs by setting data bit and strobing the clock 32 times. 427109060Smbr */ 428139740Sphkstatic void 429139740Sphksis_mii_sync(struct sis_softc *sc) 430109060Smbr{ 431139708Sphk int i; 432109060Smbr 433109060Smbr SIO_SET(SIS_MII_DIR|SIS_MII_DATA); 434109060Smbr 435109060Smbr for (i = 0; i < 32; i++) { 436109060Smbr SIO_SET(SIS_MII_CLK); 437109060Smbr DELAY(1); 438109060Smbr SIO_CLR(SIS_MII_CLK); 439109060Smbr DELAY(1); 440109060Smbr } 441109060Smbr} 442109060Smbr 443109060Smbr/* 444109060Smbr * Clock a series of bits through the MII. 445109060Smbr */ 446139740Sphkstatic void 447139740Sphksis_mii_send(struct sis_softc *sc, uint32_t bits, int cnt) 448109060Smbr{ 449109060Smbr int i; 450109060Smbr 451109060Smbr SIO_CLR(SIS_MII_CLK); 452109060Smbr 453109060Smbr for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 454109060Smbr if (bits & i) { 455109060Smbr SIO_SET(SIS_MII_DATA); 456109060Smbr } else { 457109060Smbr SIO_CLR(SIS_MII_DATA); 458109060Smbr } 459109060Smbr DELAY(1); 460109060Smbr SIO_CLR(SIS_MII_CLK); 461109060Smbr DELAY(1); 462109060Smbr SIO_SET(SIS_MII_CLK); 463109060Smbr } 464109060Smbr} 465109060Smbr 466109060Smbr/* 467109060Smbr * Read an PHY register through the MII. 468109060Smbr */ 469139740Sphkstatic int 470139740Sphksis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame) 471109060Smbr{ 472150583Sjhb int i, ack; 473109060Smbr 474109060Smbr /* 475109060Smbr * Set up frame for RX. 476109060Smbr */ 477109060Smbr frame->mii_stdelim = SIS_MII_STARTDELIM; 478109060Smbr frame->mii_opcode = SIS_MII_READOP; 479109060Smbr frame->mii_turnaround = 0; 480109060Smbr frame->mii_data = 0; 481109060Smbr 482109060Smbr /* 483109060Smbr * Turn on data xmit. 484109060Smbr */ 485109060Smbr SIO_SET(SIS_MII_DIR); 486109060Smbr 487109060Smbr sis_mii_sync(sc); 488109060Smbr 489109060Smbr /* 490109060Smbr * Send command/address info. 491109060Smbr */ 492109060Smbr sis_mii_send(sc, frame->mii_stdelim, 2); 493109060Smbr sis_mii_send(sc, frame->mii_opcode, 2); 494109060Smbr sis_mii_send(sc, frame->mii_phyaddr, 5); 495109060Smbr sis_mii_send(sc, frame->mii_regaddr, 5); 496109060Smbr 497109060Smbr /* Idle bit */ 498109060Smbr SIO_CLR((SIS_MII_CLK|SIS_MII_DATA)); 499109060Smbr DELAY(1); 500109060Smbr SIO_SET(SIS_MII_CLK); 501109060Smbr DELAY(1); 502109060Smbr 503109060Smbr /* Turn off xmit. */ 504109060Smbr SIO_CLR(SIS_MII_DIR); 505109060Smbr 506109060Smbr /* Check for ack */ 507109060Smbr SIO_CLR(SIS_MII_CLK); 508109060Smbr DELAY(1); 509109060Smbr ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA; 510109060Smbr SIO_SET(SIS_MII_CLK); 511109060Smbr DELAY(1); 512109060Smbr 513109060Smbr /* 514109060Smbr * Now try reading data bits. If the ack failed, we still 515109060Smbr * need to clock through 16 cycles to keep the PHY(s) in sync. 516109060Smbr */ 517109060Smbr if (ack) { 518109060Smbr for(i = 0; i < 16; i++) { 519109060Smbr SIO_CLR(SIS_MII_CLK); 520109060Smbr DELAY(1); 521109060Smbr SIO_SET(SIS_MII_CLK); 522109060Smbr DELAY(1); 523109060Smbr } 524109060Smbr goto fail; 525109060Smbr } 526109060Smbr 527109060Smbr for (i = 0x8000; i; i >>= 1) { 528109060Smbr SIO_CLR(SIS_MII_CLK); 529109060Smbr DELAY(1); 530109060Smbr if (!ack) { 531109060Smbr if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA) 532109060Smbr frame->mii_data |= i; 533109060Smbr DELAY(1); 534109060Smbr } 535109060Smbr SIO_SET(SIS_MII_CLK); 536109060Smbr DELAY(1); 537109060Smbr } 538109060Smbr 539109060Smbrfail: 540109060Smbr 541109060Smbr SIO_CLR(SIS_MII_CLK); 542109060Smbr DELAY(1); 543109060Smbr SIO_SET(SIS_MII_CLK); 544109060Smbr DELAY(1); 545109060Smbr 546109060Smbr if (ack) 547109060Smbr return(1); 548109060Smbr return(0); 549109060Smbr} 550109060Smbr 551109060Smbr/* 552109060Smbr * Write to a PHY register through the MII. 553109060Smbr */ 554139740Sphkstatic int 555139740Sphksis_mii_writereg(struct sis_softc *sc, struct sis_mii_frame *frame) 556109060Smbr{ 557109060Smbr 558109060Smbr /* 559109060Smbr * Set up frame for TX. 560109060Smbr */ 561109060Smbr 562109060Smbr frame->mii_stdelim = SIS_MII_STARTDELIM; 563109060Smbr frame->mii_opcode = SIS_MII_WRITEOP; 564109060Smbr frame->mii_turnaround = SIS_MII_TURNAROUND; 565109060Smbr 566109060Smbr /* 567109060Smbr * Turn on data output. 568109060Smbr */ 569109060Smbr SIO_SET(SIS_MII_DIR); 570109060Smbr 571109060Smbr sis_mii_sync(sc); 572109060Smbr 573109060Smbr sis_mii_send(sc, frame->mii_stdelim, 2); 574109060Smbr sis_mii_send(sc, frame->mii_opcode, 2); 575109060Smbr sis_mii_send(sc, frame->mii_phyaddr, 5); 576109060Smbr sis_mii_send(sc, frame->mii_regaddr, 5); 577109060Smbr sis_mii_send(sc, frame->mii_turnaround, 2); 578109060Smbr sis_mii_send(sc, frame->mii_data, 16); 579109060Smbr 580109060Smbr /* Idle bit. */ 581109060Smbr SIO_SET(SIS_MII_CLK); 582109060Smbr DELAY(1); 583109060Smbr SIO_CLR(SIS_MII_CLK); 584109060Smbr DELAY(1); 585109060Smbr 586109060Smbr /* 587109060Smbr * Turn off xmit. 588109060Smbr */ 589109060Smbr SIO_CLR(SIS_MII_DIR); 590109060Smbr 591109060Smbr return(0); 592109060Smbr} 593109060Smbr 594102334Salfredstatic int 595139740Sphksis_miibus_readreg(device_t dev, int phy, int reg) 59650974Swpaul{ 59750974Swpaul struct sis_softc *sc; 598109060Smbr struct sis_mii_frame frame; 59950974Swpaul 60050974Swpaul sc = device_get_softc(dev); 60150974Swpaul 60262672Swpaul if (sc->sis_type == SIS_TYPE_83815) { 60362672Swpaul if (phy != 0) 60462672Swpaul return(0); 60562672Swpaul /* 60662672Swpaul * The NatSemi chip can take a while after 60762672Swpaul * a reset to come ready, during which the BMSR 60862672Swpaul * returns a value of 0. This is *never* supposed 60962672Swpaul * to happen: some of the BMSR bits are meant to 61062672Swpaul * be hardwired in the on position, and this can 61162672Swpaul * confuse the miibus code a bit during the probe 61262672Swpaul * and attach phase. So we make an effort to check 61362672Swpaul * for this condition and wait for it to clear. 61462672Swpaul */ 61562672Swpaul if (!CSR_READ_4(sc, NS_BMSR)) 61662672Swpaul DELAY(1000); 617109060Smbr return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 61862672Swpaul } 61962672Swpaul 620109976Smbr /* 621109976Smbr * Chipsets < SIS_635 seem not to be able to read/write 622109976Smbr * through mdio. Use the enhanced PHY access register 623109976Smbr * again for them. 624109976Smbr */ 62589296Swpaul if (sc->sis_type == SIS_TYPE_900 && 626109976Smbr sc->sis_rev < SIS_REV_635) { 627109976Smbr int i, val = 0; 62850974Swpaul 629109976Smbr if (phy != 0) 630109976Smbr return(0); 63150974Swpaul 632109976Smbr CSR_WRITE_4(sc, SIS_PHYCTL, 633109976Smbr (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 634109976Smbr SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 63550974Swpaul 636109976Smbr for (i = 0; i < SIS_TIMEOUT; i++) { 637109976Smbr if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 638109976Smbr break; 639109976Smbr } 640109976Smbr 641109976Smbr if (i == SIS_TIMEOUT) { 642162315Sglebius device_printf(sc->sis_dev, "PHY failed to come ready\n"); 643109976Smbr return(0); 644109976Smbr } 645109976Smbr 646109976Smbr val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 647109976Smbr 648109976Smbr if (val == 0xFFFF) 649109976Smbr return(0); 650109976Smbr 651109976Smbr return(val); 652109976Smbr } else { 653109976Smbr bzero((char *)&frame, sizeof(frame)); 654109976Smbr 655109976Smbr frame.mii_phyaddr = phy; 656109976Smbr frame.mii_regaddr = reg; 657109976Smbr sis_mii_readreg(sc, &frame); 658109976Smbr 659109976Smbr return(frame.mii_data); 660109976Smbr } 66150974Swpaul} 66250974Swpaul 663102334Salfredstatic int 664139740Sphksis_miibus_writereg(device_t dev, int phy, int reg, int data) 66550974Swpaul{ 66650974Swpaul struct sis_softc *sc; 667109060Smbr struct sis_mii_frame frame; 66850974Swpaul 66950974Swpaul sc = device_get_softc(dev); 67050974Swpaul 67162672Swpaul if (sc->sis_type == SIS_TYPE_83815) { 67262672Swpaul if (phy != 0) 67362672Swpaul return(0); 67462672Swpaul CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 67562672Swpaul return(0); 67662672Swpaul } 67762672Swpaul 678109976Smbr /* 679109976Smbr * Chipsets < SIS_635 seem not to be able to read/write 680109976Smbr * through mdio. Use the enhanced PHY access register 681109976Smbr * again for them. 682109976Smbr */ 683109976Smbr if (sc->sis_type == SIS_TYPE_900 && 684109976Smbr sc->sis_rev < SIS_REV_635) { 685109976Smbr int i; 68650974Swpaul 687109976Smbr if (phy != 0) 688109976Smbr return(0); 68950974Swpaul 690109976Smbr CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 691109976Smbr (reg << 6) | SIS_PHYOP_WRITE); 692109976Smbr SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 69350974Swpaul 694109976Smbr for (i = 0; i < SIS_TIMEOUT; i++) { 695109976Smbr if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 696109976Smbr break; 697109976Smbr } 69850974Swpaul 699109976Smbr if (i == SIS_TIMEOUT) 700162315Sglebius device_printf(sc->sis_dev, "PHY failed to come ready\n"); 701109976Smbr } else { 702109976Smbr bzero((char *)&frame, sizeof(frame)); 703109976Smbr 704109976Smbr frame.mii_phyaddr = phy; 705109976Smbr frame.mii_regaddr = reg; 706109976Smbr frame.mii_data = data; 707109976Smbr sis_mii_writereg(sc, &frame); 708109976Smbr } 70950974Swpaul return(0); 71050974Swpaul} 71150974Swpaul 712102334Salfredstatic void 713139717Sphksis_miibus_statchg(device_t dev) 71450974Swpaul{ 71550974Swpaul struct sis_softc *sc; 71650974Swpaul 71750974Swpaul sc = device_get_softc(dev); 718139717Sphk SIS_LOCK_ASSERT(sc); 719139717Sphk sis_initl(sc); 72050974Swpaul} 72150974Swpaul 722139740Sphkstatic uint32_t 723139740Sphksis_mchash(struct sis_softc *sc, const uint8_t *addr) 72450974Swpaul{ 725130270Snaddy uint32_t crc; 72650974Swpaul 72750974Swpaul /* Compute CRC for the address value. */ 728130270Snaddy crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 72950974Swpaul 73062672Swpaul /* 73162672Swpaul * return the filter bit position 73262672Swpaul * 73362672Swpaul * The NatSemi chip has a 512-bit filter, which is 73462672Swpaul * different than the SiS, so we special-case it. 73562672Swpaul */ 73662672Swpaul if (sc->sis_type == SIS_TYPE_83815) 737109060Smbr return (crc >> 23); 738109976Smbr else if (sc->sis_rev >= SIS_REV_635 || 739109976Smbr sc->sis_rev == SIS_REV_900B) 740109060Smbr return (crc >> 24); 741109976Smbr else 742109976Smbr return (crc >> 25); 74350974Swpaul} 74450974Swpaul 745102334Salfredstatic void 746139740Sphksis_setmulti_ns(struct sis_softc *sc) 74750974Swpaul{ 74850974Swpaul struct ifnet *ifp; 74950974Swpaul struct ifmultiaddr *ifma; 75050974Swpaul u_int32_t h = 0, i, filtsave; 75162672Swpaul int bit, index; 75250974Swpaul 753147256Sbrooks ifp = sc->sis_ifp; 75450974Swpaul 75550974Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 75662672Swpaul SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 75750974Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 75850974Swpaul return; 75950974Swpaul } 76050974Swpaul 76162672Swpaul /* 76262672Swpaul * We have to explicitly enable the multicast hash table 76362672Swpaul * on the NatSemi chip if we want to use it, which we do. 76462672Swpaul */ 76562672Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 76650974Swpaul SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 76750974Swpaul 76850974Swpaul filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 76950974Swpaul 77050974Swpaul /* first, zot all the existing hash bits */ 77162672Swpaul for (i = 0; i < 32; i++) { 77262672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 77362672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 77462672Swpaul } 77562672Swpaul 776195049Srwatson if_maddr_rlock(ifp); 77772084Sphk TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 77862672Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 77962672Swpaul continue; 780122625Sobrien h = sis_mchash(sc, 781122625Sobrien LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 78262672Swpaul index = h >> 3; 78362672Swpaul bit = h & 0x1F; 78462672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 78562672Swpaul if (bit > 0xF) 78662672Swpaul bit -= 0x10; 78762672Swpaul SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 78862672Swpaul } 789195049Srwatson if_maddr_runlock(ifp); 79062672Swpaul 79162672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 79262672Swpaul 79362672Swpaul return; 79462672Swpaul} 79562672Swpaul 796102334Salfredstatic void 797139740Sphksis_setmulti_sis(struct sis_softc *sc) 79862672Swpaul{ 79962672Swpaul struct ifnet *ifp; 80062672Swpaul struct ifmultiaddr *ifma; 801109060Smbr u_int32_t h, i, n, ctl; 802109060Smbr u_int16_t hashes[16]; 80362672Swpaul 804147256Sbrooks ifp = sc->sis_ifp; 80562672Swpaul 806109060Smbr /* hash table size */ 807109976Smbr if (sc->sis_rev >= SIS_REV_635 || 808109976Smbr sc->sis_rev == SIS_REV_900B) 809109976Smbr n = 16; 810109976Smbr else 811109976Smbr n = 8; 81262672Swpaul 813109060Smbr ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE; 81462672Swpaul 815109060Smbr if (ifp->if_flags & IFF_BROADCAST) 816109060Smbr ctl |= SIS_RXFILTCTL_BROAD; 81762672Swpaul 818109060Smbr if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 819109060Smbr ctl |= SIS_RXFILTCTL_ALLMULTI; 820109060Smbr if (ifp->if_flags & IFF_PROMISC) 821109060Smbr ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS; 822109060Smbr for (i = 0; i < n; i++) 823109060Smbr hashes[i] = ~0; 824109060Smbr } else { 825109060Smbr for (i = 0; i < n; i++) 826109060Smbr hashes[i] = 0; 827109060Smbr i = 0; 828195049Srwatson if_maddr_rlock(ifp); 829109060Smbr TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 830109060Smbr if (ifma->ifma_addr->sa_family != AF_LINK) 831109060Smbr continue; 832122625Sobrien h = sis_mchash(sc, 833109060Smbr LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 834109060Smbr hashes[h >> 4] |= 1 << (h & 0xf); 835109060Smbr i++; 836109060Smbr } 837195049Srwatson if_maddr_runlock(ifp); 838109060Smbr if (i > n) { 839109060Smbr ctl |= SIS_RXFILTCTL_ALLMULTI; 840109060Smbr for (i = 0; i < n; i++) 841109060Smbr hashes[i] = ~0; 842109060Smbr } 84350974Swpaul } 84450974Swpaul 845109060Smbr for (i = 0; i < n; i++) { 846109060Smbr CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); 847109060Smbr CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); 84850974Swpaul } 84950974Swpaul 850109060Smbr CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl); 85150974Swpaul} 85250974Swpaul 853102334Salfredstatic void 854139717Sphksis_reset(struct sis_softc *sc) 85550974Swpaul{ 856139708Sphk int i; 85750974Swpaul 85850974Swpaul SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 85950974Swpaul 86050974Swpaul for (i = 0; i < SIS_TIMEOUT; i++) { 86150974Swpaul if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 86250974Swpaul break; 86350974Swpaul } 86450974Swpaul 86550974Swpaul if (i == SIS_TIMEOUT) 866162315Sglebius device_printf(sc->sis_dev, "reset never completed\n"); 86750974Swpaul 86850974Swpaul /* Wait a little while for the chip to get its brains in order. */ 86950974Swpaul DELAY(1000); 87072813Swpaul 87172813Swpaul /* 87272813Swpaul * If this is a NetSemi chip, make sure to clear 87372813Swpaul * PME mode. 87472813Swpaul */ 87572813Swpaul if (sc->sis_type == SIS_TYPE_83815) { 87672813Swpaul CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 87772813Swpaul CSR_WRITE_4(sc, NS_CLKRUN, 0); 87872813Swpaul } 87972813Swpaul 88050974Swpaul return; 88150974Swpaul} 88250974Swpaul 88350974Swpaul/* 88450974Swpaul * Probe for an SiS chip. Check the PCI vendor and device 88550974Swpaul * IDs against our list and return a device name if we find a match. 88650974Swpaul */ 887102334Salfredstatic int 888139740Sphksis_probe(device_t dev) 88950974Swpaul{ 89050974Swpaul struct sis_type *t; 89150974Swpaul 89250974Swpaul t = sis_devs; 89350974Swpaul 89450974Swpaul while(t->sis_name != NULL) { 89550974Swpaul if ((pci_get_vendor(dev) == t->sis_vid) && 89650974Swpaul (pci_get_device(dev) == t->sis_did)) { 89750974Swpaul device_set_desc(dev, t->sis_name); 898142398Simp return (BUS_PROBE_DEFAULT); 89950974Swpaul } 90050974Swpaul t++; 90150974Swpaul } 90250974Swpaul 90350974Swpaul return(ENXIO); 90450974Swpaul} 90550974Swpaul 90650974Swpaul/* 90750974Swpaul * Attach the interface. Allocate softc structures, do ifmedia 90850974Swpaul * setup and ethernet/BPF attach. 90950974Swpaul */ 910102334Salfredstatic int 911139740Sphksis_attach(device_t dev) 91250974Swpaul{ 91350974Swpaul u_char eaddr[ETHER_ADDR_LEN]; 91450974Swpaul struct sis_softc *sc; 91550974Swpaul struct ifnet *ifp; 916150583Sjhb int error = 0, waittime = 0; 91750974Swpaul 918109061Smbr waittime = 0; 91950974Swpaul sc = device_get_softc(dev); 92050974Swpaul 921162315Sglebius sc->sis_dev = dev; 922119712Sphk 92393818Sjhb mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 924139810Sphk MTX_DEF); 925150583Sjhb callout_init_mtx(&sc->sis_stat_ch, &sc->sis_mtx, 0); 92669583Swpaul 92750974Swpaul if (pci_get_device(dev) == SIS_DEVICEID_900) 92850974Swpaul sc->sis_type = SIS_TYPE_900; 92950974Swpaul if (pci_get_device(dev) == SIS_DEVICEID_7016) 93050974Swpaul sc->sis_type = SIS_TYPE_7016; 93162672Swpaul if (pci_get_vendor(dev) == NS_VENDORID) 93262672Swpaul sc->sis_type = SIS_TYPE_83815; 93350974Swpaul 93489296Swpaul sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 93550974Swpaul /* 93650974Swpaul * Map control/status registers. 93750974Swpaul */ 93872813Swpaul pci_enable_busmaster(dev); 93950974Swpaul 940150526Sphk error = bus_alloc_resources(dev, sis_res_spec, sc->sis_res); 941150583Sjhb if (error) { 942150583Sjhb device_printf(dev, "couldn't allocate resources\n"); 943150583Sjhb goto fail; 944150583Sjhb } 94550974Swpaul 94650974Swpaul /* Reset the adapter. */ 94750974Swpaul sis_reset(sc); 94850974Swpaul 949109976Smbr if (sc->sis_type == SIS_TYPE_900 && 950109976Smbr (sc->sis_rev == SIS_REV_635 || 951109976Smbr sc->sis_rev == SIS_REV_900B)) { 952109976Smbr SIO_SET(SIS_CFG_RND_CNT); 953109976Smbr SIO_SET(SIS_CFG_PERR_DETECT); 954109976Smbr } 955109976Smbr 95650974Swpaul /* 95750974Swpaul * Get station address from the EEPROM. 95850974Swpaul */ 95962672Swpaul switch (pci_get_vendor(dev)) { 96062672Swpaul case NS_VENDORID: 961119712Sphk sc->sis_srr = CSR_READ_4(sc, NS_SRR); 962119712Sphk 963119712Sphk /* We can't update the device description, so spew */ 964119712Sphk if (sc->sis_srr == NS_SRR_15C) 965119712Sphk device_printf(dev, "Silicon Revision: DP83815C\n"); 966119712Sphk else if (sc->sis_srr == NS_SRR_15D) 967119712Sphk device_printf(dev, "Silicon Revision: DP83815D\n"); 968119712Sphk else if (sc->sis_srr == NS_SRR_16A) 969119712Sphk device_printf(dev, "Silicon Revision: DP83816A\n"); 970119712Sphk else 971119712Sphk device_printf(dev, "Silicon Revision %x\n", sc->sis_srr); 972119712Sphk 97362672Swpaul /* 97462672Swpaul * Reading the MAC address out of the EEPROM on 97562672Swpaul * the NatSemi chip takes a bit more work than 97662672Swpaul * you'd expect. The address spans 4 16-bit words, 97762672Swpaul * with the first word containing only a single bit. 97862672Swpaul * You have to shift everything over one bit to 97962672Swpaul * get it aligned properly. Also, the bits are 98062672Swpaul * stored backwards (the LSB is really the MSB, 98162672Swpaul * and so on) so you have to reverse them in order 98262672Swpaul * to get the MAC address into the form we want. 98362672Swpaul * Why? Who the hell knows. 98462672Swpaul */ 98562672Swpaul { 98662672Swpaul u_int16_t tmp[4]; 98750974Swpaul 98862672Swpaul sis_read_eeprom(sc, (caddr_t)&tmp, 98962672Swpaul NS_EE_NODEADDR, 4, 0); 99062672Swpaul 99162672Swpaul /* Shift everything over one bit. */ 99262672Swpaul tmp[3] = tmp[3] >> 1; 99362681Swpaul tmp[3] |= tmp[2] << 15; 99462672Swpaul tmp[2] = tmp[2] >> 1; 99562681Swpaul tmp[2] |= tmp[1] << 15; 99662672Swpaul tmp[1] = tmp[1] >> 1; 99762681Swpaul tmp[1] |= tmp[0] << 15; 99862672Swpaul 99962672Swpaul /* Now reverse all the bits. */ 100062672Swpaul tmp[3] = sis_reverse(tmp[3]); 100162672Swpaul tmp[2] = sis_reverse(tmp[2]); 100262672Swpaul tmp[1] = sis_reverse(tmp[1]); 100362672Swpaul 100462672Swpaul bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); 100562672Swpaul } 100662672Swpaul break; 100762672Swpaul case SIS_VENDORID: 100862672Swpaul default: 1009144243Sobrien#if defined(__i386__) || defined(__amd64__) 101072197Swpaul /* 101172197Swpaul * If this is a SiS 630E chipset with an embedded 101272197Swpaul * SiS 900 controller, we have to read the MAC address 101372197Swpaul * from the APC CMOS RAM. Our method for doing this 101472197Swpaul * is very ugly since we have to reach out and grab 101572197Swpaul * ahold of hardware for which we cannot properly 101672197Swpaul * allocate resources. This code is only compiled on 101772197Swpaul * the i386 architecture since the SiS 630E chipset 101872197Swpaul * is for x86 motherboards only. Note that there are 101972197Swpaul * a lot of magic numbers in this hack. These are 102072197Swpaul * taken from SiS's Linux driver. I'd like to replace 102172197Swpaul * them with proper symbolic definitions, but that 102272197Swpaul * requires some datasheets that I don't have access 102372197Swpaul * to at the moment. 102472197Swpaul */ 102589296Swpaul if (sc->sis_rev == SIS_REV_630S || 102689296Swpaul sc->sis_rev == SIS_REV_630E || 102790328Sambrisko sc->sis_rev == SIS_REV_630EA1) 102872197Swpaul sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 102989296Swpaul 103090328Sambrisko else if (sc->sis_rev == SIS_REV_635 || 103190328Sambrisko sc->sis_rev == SIS_REV_630ET) 103289296Swpaul sis_read_mac(sc, dev, (caddr_t)&eaddr); 1033109061Smbr else if (sc->sis_rev == SIS_REV_96x) { 1034109061Smbr /* Allow to read EEPROM from LAN. It is shared 1035109061Smbr * between a 1394 controller and the NIC and each 1036109061Smbr * time we access it, we need to set SIS_EECMD_REQ. 1037109061Smbr */ 1038109061Smbr SIO_SET(SIS_EECMD_REQ); 1039109061Smbr for (waittime = 0; waittime < SIS_TIMEOUT; 1040109061Smbr waittime++) { 1041109061Smbr /* Force EEPROM to idle state. */ 1042109061Smbr sis_eeprom_idle(sc); 1043109061Smbr if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { 1044109061Smbr sis_read_eeprom(sc, (caddr_t)&eaddr, 1045109061Smbr SIS_EE_NODEADDR, 3, 0); 1046109061Smbr break; 1047109061Smbr } 1048109061Smbr DELAY(1); 1049109061Smbr } 1050109061Smbr /* 1051109061Smbr * Set SIS_EECTL_CLK to high, so a other master 1052109061Smbr * can operate on the i2c bus. 1053109061Smbr */ 1054109061Smbr SIO_SET(SIS_EECTL_CLK); 1055109061Smbr /* Refuse EEPROM access by LAN */ 1056109061Smbr SIO_SET(SIS_EECMD_DONE); 1057109061Smbr } else 105872197Swpaul#endif 105972197Swpaul sis_read_eeprom(sc, (caddr_t)&eaddr, 106072197Swpaul SIS_EE_NODEADDR, 3, 0); 106162672Swpaul break; 106262672Swpaul } 106362672Swpaul 106481713Swpaul /* 106581713Swpaul * Allocate the parent bus DMA tag appropriate for PCI. 106681713Swpaul */ 106781713Swpaul#define SIS_NSEG_NEW 32 106881713Swpaul error = bus_dma_tag_create(NULL, /* parent */ 106981713Swpaul 1, 0, /* alignment, boundary */ 107081713Swpaul BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 107181713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 107281713Swpaul NULL, NULL, /* filter, filterarg */ 107381713Swpaul MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */ 107481713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 107581713Swpaul BUS_DMA_ALLOCNOW, /* flags */ 1076117126Sscottl NULL, NULL, /* lockfunc, lockarg */ 107781713Swpaul &sc->sis_parent_tag); 1078112872Snjl if (error) 1079112872Snjl goto fail; 108050974Swpaul 108181713Swpaul /* 1082112872Snjl * Now allocate a tag for the DMA descriptor lists and a chunk 1083112872Snjl * of DMA-able memory based on the tag. Also obtain the physical 1084112872Snjl * addresses of the RX and TX ring, which we'll need later. 108581713Swpaul * All of our lists are allocated as a contiguous block 108681713Swpaul * of memory. 108781713Swpaul */ 108881713Swpaul error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 108981713Swpaul 1, 0, /* alignment, boundary */ 109081713Swpaul BUS_SPACE_MAXADDR, /* lowaddr */ 109181713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 109281713Swpaul NULL, NULL, /* filter, filterarg */ 109381713Swpaul SIS_RX_LIST_SZ, 1, /* maxsize,nsegments */ 109481713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 109581713Swpaul 0, /* flags */ 1096117126Sscottl busdma_lock_mutex, /* lockfunc */ 1097117126Sscottl &Giant, /* lockarg */ 1098139690Sphk &sc->sis_rx_tag); 1099112872Snjl if (error) 1100112872Snjl goto fail; 110181713Swpaul 1102139690Sphk error = bus_dmamem_alloc(sc->sis_rx_tag, 1103139690Sphk (void **)&sc->sis_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1104139690Sphk &sc->sis_rx_dmamap); 1105112872Snjl 1106112872Snjl if (error) { 1107150583Sjhb device_printf(dev, "no memory for rx list buffers!\n"); 1108139690Sphk bus_dma_tag_destroy(sc->sis_rx_tag); 1109139690Sphk sc->sis_rx_tag = NULL; 1110112872Snjl goto fail; 1111112872Snjl } 1112112872Snjl 1113139690Sphk error = bus_dmamap_load(sc->sis_rx_tag, 1114139690Sphk sc->sis_rx_dmamap, &(sc->sis_rx_list[0]), 1115112872Snjl sizeof(struct sis_desc), sis_dma_map_ring, 1116139690Sphk &sc->sis_rx_paddr, 0); 1117112872Snjl 1118112872Snjl if (error) { 1119150583Sjhb device_printf(dev, "cannot get address of the rx ring!\n"); 1120139690Sphk bus_dmamem_free(sc->sis_rx_tag, 1121139690Sphk sc->sis_rx_list, sc->sis_rx_dmamap); 1122139690Sphk bus_dma_tag_destroy(sc->sis_rx_tag); 1123139690Sphk sc->sis_rx_tag = NULL; 1124112872Snjl goto fail; 1125112872Snjl } 1126112872Snjl 112781713Swpaul error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 112881713Swpaul 1, 0, /* alignment, boundary */ 112981713Swpaul BUS_SPACE_MAXADDR, /* lowaddr */ 113081713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 113181713Swpaul NULL, NULL, /* filter, filterarg */ 113281713Swpaul SIS_TX_LIST_SZ, 1, /* maxsize,nsegments */ 113381713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 113481713Swpaul 0, /* flags */ 1135117126Sscottl busdma_lock_mutex, /* lockfunc */ 1136117126Sscottl &Giant, /* lockarg */ 1137139690Sphk &sc->sis_tx_tag); 1138112872Snjl if (error) 1139112872Snjl goto fail; 114081713Swpaul 1141139690Sphk error = bus_dmamem_alloc(sc->sis_tx_tag, 1142139690Sphk (void **)&sc->sis_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1143139690Sphk &sc->sis_tx_dmamap); 114481713Swpaul 114581713Swpaul if (error) { 1146150583Sjhb device_printf(dev, "no memory for tx list buffers!\n"); 1147139690Sphk bus_dma_tag_destroy(sc->sis_tx_tag); 1148139690Sphk sc->sis_tx_tag = NULL; 114950974Swpaul goto fail; 115050974Swpaul } 115150974Swpaul 1152139690Sphk error = bus_dmamap_load(sc->sis_tx_tag, 1153139690Sphk sc->sis_tx_dmamap, &(sc->sis_tx_list[0]), 1154112872Snjl sizeof(struct sis_desc), sis_dma_map_ring, 1155139690Sphk &sc->sis_tx_paddr, 0); 115681713Swpaul 115781713Swpaul if (error) { 1158150583Sjhb device_printf(dev, "cannot get address of the tx ring!\n"); 1159139690Sphk bus_dmamem_free(sc->sis_tx_tag, 1160139690Sphk sc->sis_tx_list, sc->sis_tx_dmamap); 1161139690Sphk bus_dma_tag_destroy(sc->sis_tx_tag); 1162139690Sphk sc->sis_tx_tag = NULL; 116381713Swpaul goto fail; 116481713Swpaul } 116581713Swpaul 1166112872Snjl error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1167112872Snjl 1, 0, /* alignment, boundary */ 1168112872Snjl BUS_SPACE_MAXADDR, /* lowaddr */ 1169112872Snjl BUS_SPACE_MAXADDR, /* highaddr */ 1170112872Snjl NULL, NULL, /* filter, filterarg */ 1171112872Snjl MCLBYTES, 1, /* maxsize,nsegments */ 1172112872Snjl BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1173112872Snjl 0, /* flags */ 1174117126Sscottl busdma_lock_mutex, /* lockfunc */ 1175117126Sscottl &Giant, /* lockarg */ 1176112872Snjl &sc->sis_tag); 1177112872Snjl if (error) 1178112872Snjl goto fail; 117981713Swpaul 118081713Swpaul /* 118181713Swpaul * Obtain the physical addresses of the RX and TX 118281713Swpaul * rings which we'll need later in the init routine. 118381713Swpaul */ 118481713Swpaul 1185147256Sbrooks ifp = sc->sis_ifp = if_alloc(IFT_ETHER); 1186147256Sbrooks if (ifp == NULL) { 1187150583Sjhb device_printf(dev, "can not if_alloc()\n"); 1188147256Sbrooks error = ENOSPC; 1189147256Sbrooks goto fail; 1190147256Sbrooks } 119150974Swpaul ifp->if_softc = sc; 1192121816Sbrooks if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 119350974Swpaul ifp->if_mtu = ETHERMTU; 119450974Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 119550974Swpaul ifp->if_ioctl = sis_ioctl; 119650974Swpaul ifp->if_start = sis_start; 119750974Swpaul ifp->if_init = sis_init; 1198131455Smlaier IFQ_SET_MAXLEN(&ifp->if_snd, SIS_TX_LIST_CNT - 1); 1199131455Smlaier ifp->if_snd.ifq_drv_maxlen = SIS_TX_LIST_CNT - 1; 1200131455Smlaier IFQ_SET_READY(&ifp->if_snd); 120150974Swpaul 120250974Swpaul /* 120350974Swpaul * Do MII setup. 120450974Swpaul */ 120550974Swpaul if (mii_phy_probe(dev, &sc->sis_miibus, 120650974Swpaul sis_ifmedia_upd, sis_ifmedia_sts)) { 1207150583Sjhb device_printf(dev, "MII without any PHY!\n"); 120850974Swpaul error = ENXIO; 120950974Swpaul goto fail; 121050974Swpaul } 121150974Swpaul 121250974Swpaul /* 121363090Sarchie * Call MI attach routine. 121450974Swpaul */ 1215106936Ssam ether_ifattach(ifp, eaddr); 121687390Sjhay 121787390Sjhay /* 121887390Sjhay * Tell the upper layer(s) we support long frames. 121987390Sjhay */ 122087390Sjhay ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1221106936Ssam ifp->if_capabilities |= IFCAP_VLAN_MTU; 1222150789Sglebius ifp->if_capenable = ifp->if_capabilities; 1223128138Sru#ifdef DEVICE_POLLING 1224128138Sru ifp->if_capabilities |= IFCAP_POLLING; 1225128138Sru#endif 1226128138Sru 1227113609Snjl /* Hook interrupt last to avoid having to lock softc */ 1228150526Sphk error = bus_setup_intr(dev, sc->sis_res[1], INTR_TYPE_NET | INTR_MPSAFE, 1229166901Spiso NULL, sis_intr, sc, &sc->sis_intrhand); 123050974Swpaul 1231112872Snjl if (error) { 1232150583Sjhb device_printf(dev, "couldn't set up irq\n"); 1233113609Snjl ether_ifdetach(ifp); 1234112872Snjl goto fail; 1235112872Snjl } 1236112872Snjl 123750974Swpaulfail: 1238112872Snjl if (error) 1239112872Snjl sis_detach(dev); 1240112872Snjl 124150974Swpaul return(error); 124250974Swpaul} 124350974Swpaul 1244113609Snjl/* 1245113609Snjl * Shutdown hardware and free up resources. This can be called any 1246113609Snjl * time after the mutex has been initialized. It is called in both 1247113609Snjl * the error case in attach and the normal detach case so it needs 1248113609Snjl * to be careful about only freeing resources that have actually been 1249113609Snjl * allocated. 1250113609Snjl */ 1251102334Salfredstatic int 1252139740Sphksis_detach(device_t dev) 125350974Swpaul{ 125450974Swpaul struct sis_softc *sc; 125550974Swpaul struct ifnet *ifp; 125650974Swpaul 125750974Swpaul sc = device_get_softc(dev); 1258112880Sjhb KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized")); 1259147256Sbrooks ifp = sc->sis_ifp; 126050974Swpaul 1261150789Sglebius#ifdef DEVICE_POLLING 1262150789Sglebius if (ifp->if_capenable & IFCAP_POLLING) 1263150789Sglebius ether_poll_deregister(ifp); 1264150789Sglebius#endif 1265150789Sglebius 1266118089Smux /* These should only be active if attach succeeded. */ 1267113812Simp if (device_is_attached(dev)) { 1268150583Sjhb SIS_LOCK(sc); 1269113609Snjl sis_reset(sc); 1270113609Snjl sis_stop(sc); 1271150583Sjhb SIS_UNLOCK(sc); 1272150583Sjhb callout_drain(&sc->sis_stat_ch); 1273112872Snjl ether_ifdetach(ifp); 1274150213Sru } 1275113609Snjl if (sc->sis_miibus) 1276112872Snjl device_delete_child(dev, sc->sis_miibus); 1277113609Snjl bus_generic_detach(dev); 127850974Swpaul 1279112872Snjl if (sc->sis_intrhand) 1280150526Sphk bus_teardown_intr(dev, sc->sis_res[1], sc->sis_intrhand); 1281150526Sphk bus_release_resources(dev, sis_res_spec, sc->sis_res); 128250974Swpaul 1283151297Sru if (ifp) 1284151297Sru if_free(ifp); 1285151297Sru 1286139690Sphk if (sc->sis_rx_tag) { 1287139690Sphk bus_dmamap_unload(sc->sis_rx_tag, 1288139690Sphk sc->sis_rx_dmamap); 1289139690Sphk bus_dmamem_free(sc->sis_rx_tag, 1290139690Sphk sc->sis_rx_list, sc->sis_rx_dmamap); 1291139690Sphk bus_dma_tag_destroy(sc->sis_rx_tag); 1292112872Snjl } 1293139690Sphk if (sc->sis_tx_tag) { 1294139690Sphk bus_dmamap_unload(sc->sis_tx_tag, 1295139690Sphk sc->sis_tx_dmamap); 1296139690Sphk bus_dmamem_free(sc->sis_tx_tag, 1297139690Sphk sc->sis_tx_list, sc->sis_tx_dmamap); 1298139690Sphk bus_dma_tag_destroy(sc->sis_tx_tag); 1299112872Snjl } 1300112872Snjl if (sc->sis_parent_tag) 1301112872Snjl bus_dma_tag_destroy(sc->sis_parent_tag); 1302112872Snjl if (sc->sis_tag) 1303112872Snjl bus_dma_tag_destroy(sc->sis_tag); 130450974Swpaul 130567087Swpaul mtx_destroy(&sc->sis_mtx); 130650974Swpaul 130750974Swpaul return(0); 130850974Swpaul} 130950974Swpaul 131050974Swpaul/* 1311139802Sphk * Initialize the TX and RX descriptors and allocate mbufs for them. Note that 1312139802Sphk * we arrange the descriptors in a closed ring, so that the last descriptor 1313139802Sphk * points back to the first. 131450974Swpaul */ 1315102334Salfredstatic int 1316139802Sphksis_ring_init(struct sis_softc *sc) 131750974Swpaul{ 1318139802Sphk int i, error; 1319139802Sphk struct sis_desc *dp; 132050974Swpaul 1321139802Sphk dp = &sc->sis_tx_list[0]; 1322139802Sphk for (i = 0; i < SIS_TX_LIST_CNT; i++, dp++) { 1323139802Sphk if (i == (SIS_TX_LIST_CNT - 1)) 1324139802Sphk dp->sis_nextdesc = &sc->sis_tx_list[0]; 1325139802Sphk else 1326139802Sphk dp->sis_nextdesc = dp + 1; 1327139802Sphk bus_dmamap_load(sc->sis_tx_tag, 1328139802Sphk sc->sis_tx_dmamap, 1329139802Sphk dp->sis_nextdesc, sizeof(struct sis_desc), 1330139802Sphk sis_dma_map_desc_next, dp, 0); 1331139802Sphk dp->sis_mbuf = NULL; 1332139802Sphk dp->sis_ptr = 0; 1333139802Sphk dp->sis_ctl = 0; 133450974Swpaul } 133550974Swpaul 1336139690Sphk sc->sis_tx_prod = sc->sis_tx_cons = sc->sis_tx_cnt = 0; 133750974Swpaul 1338139690Sphk bus_dmamap_sync(sc->sis_tx_tag, 1339148444Sjhb sc->sis_tx_dmamap, BUS_DMASYNC_PREWRITE); 134081713Swpaul 1341139802Sphk dp = &sc->sis_rx_list[0]; 1342139802Sphk for (i = 0; i < SIS_RX_LIST_CNT; i++, dp++) { 1343139802Sphk error = sis_newbuf(sc, dp, NULL); 1344139802Sphk if (error) 1345139802Sphk return(error); 1346139802Sphk if (i == (SIS_RX_LIST_CNT - 1)) 1347139802Sphk dp->sis_nextdesc = &sc->sis_rx_list[0]; 1348139802Sphk else 1349139802Sphk dp->sis_nextdesc = dp + 1; 1350139802Sphk bus_dmamap_load(sc->sis_rx_tag, 1351139802Sphk sc->sis_rx_dmamap, 1352139802Sphk dp->sis_nextdesc, sizeof(struct sis_desc), 1353139802Sphk sis_dma_map_desc_next, dp, 0); 135450974Swpaul } 135550974Swpaul 1356139690Sphk bus_dmamap_sync(sc->sis_rx_tag, 1357139690Sphk sc->sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 135881713Swpaul 1359139691Sphk sc->sis_rx_pdsc = &sc->sis_rx_list[0]; 136050974Swpaul 136150974Swpaul return(0); 136250974Swpaul} 136350974Swpaul 136450974Swpaul/* 136550974Swpaul * Initialize an RX descriptor and attach an MBUF cluster. 136650974Swpaul */ 1367102334Salfredstatic int 1368139740Sphksis_newbuf(struct sis_softc *sc, struct sis_desc *c, struct mbuf *m) 136950974Swpaul{ 137050974Swpaul 137181713Swpaul if (c == NULL) 137281713Swpaul return(EINVAL); 137381713Swpaul 137450974Swpaul if (m == NULL) { 1375111119Simp m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1376101340Sluigi if (m == NULL) 137750974Swpaul return(ENOBUFS); 1378101340Sluigi } else 1379101340Sluigi m->m_data = m->m_ext.ext_buf; 138050974Swpaul 1381101340Sluigi c->sis_mbuf = m; 138250974Swpaul c->sis_ctl = SIS_RXLEN; 138350974Swpaul 138481713Swpaul bus_dmamap_create(sc->sis_tag, 0, &c->sis_map); 138581713Swpaul bus_dmamap_load(sc->sis_tag, c->sis_map, 1386101464Sluigi mtod(m, void *), MCLBYTES, 138781713Swpaul sis_dma_map_desc_ptr, c, 0); 1388139944Ssam bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREREAD); 138981713Swpaul 139050974Swpaul return(0); 139150974Swpaul} 139250974Swpaul 139350974Swpaul/* 139450974Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 139550974Swpaul * the higher level protocols. 139650974Swpaul */ 1397193096Sattiliostatic int 1398139740Sphksis_rxeof(struct sis_softc *sc) 139950974Swpaul{ 1400163773Smarius struct mbuf *m, *m0; 1401163773Smarius struct ifnet *ifp; 140250974Swpaul struct sis_desc *cur_rx; 1403193096Sattilio int total_len = 0, rx_npkts = 0; 140450974Swpaul u_int32_t rxstat; 140550974Swpaul 1406122689Ssam SIS_LOCK_ASSERT(sc); 1407122689Ssam 1408147256Sbrooks ifp = sc->sis_ifp; 140950974Swpaul 1410139691Sphk for(cur_rx = sc->sis_rx_pdsc; SIS_OWNDESC(cur_rx); 1411139691Sphk cur_rx = cur_rx->sis_nextdesc) { 141250974Swpaul 141387902Sluigi#ifdef DEVICE_POLLING 1414150789Sglebius if (ifp->if_capenable & IFCAP_POLLING) { 141587902Sluigi if (sc->rxcycles <= 0) 141687902Sluigi break; 141787902Sluigi sc->rxcycles--; 141887902Sluigi } 1419150789Sglebius#endif 142050974Swpaul rxstat = cur_rx->sis_rxstat; 142181713Swpaul bus_dmamap_sync(sc->sis_tag, 142281713Swpaul cur_rx->sis_map, BUS_DMASYNC_POSTWRITE); 142381713Swpaul bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map); 142481713Swpaul bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map); 142550974Swpaul m = cur_rx->sis_mbuf; 142650974Swpaul cur_rx->sis_mbuf = NULL; 142750974Swpaul total_len = SIS_RXBYTES(cur_rx); 142850974Swpaul 142950974Swpaul /* 143050974Swpaul * If an error occurs, update stats, clear the 143150974Swpaul * status word and leave the mbuf cluster in place: 143250974Swpaul * it should simply get re-used next time this descriptor 143350974Swpaul * comes up in the ring. 143450974Swpaul */ 1435185784Syongari if ((ifp->if_capenable & IFCAP_VLAN_MTU) != 0 && 1436185784Syongari total_len <= (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - 1437185784Syongari ETHER_CRC_LEN)) 1438185784Syongari rxstat &= ~SIS_RXSTAT_GIANT; 1439185784Syongari if (SIS_RXSTAT_ERROR(rxstat) != 0) { 144050974Swpaul ifp->if_ierrors++; 144150974Swpaul if (rxstat & SIS_RXSTAT_COLL) 144250974Swpaul ifp->if_collisions++; 144350974Swpaul sis_newbuf(sc, cur_rx, m); 144450974Swpaul continue; 144550974Swpaul } 144650974Swpaul 144750974Swpaul /* No errors; receive the packet. */ 1448163773Smarius#ifdef __NO_STRICT_ALIGNMENT 144987059Sluigi /* 1450163773Smarius * On architectures without alignment problems we try to 145187059Sluigi * allocate a new buffer for the receive ring, and pass up 145287059Sluigi * the one where the packet is already, saving the expensive 145387059Sluigi * copy done in m_devget(). 145487059Sluigi * If we are on an architecture with alignment problems, or 145587059Sluigi * if the allocation fails, then use m_devget and leave the 145687059Sluigi * existing buffer in the receive ring. 145787059Sluigi */ 1458101464Sluigi if (sis_newbuf(sc, cur_rx, NULL) == 0) 145987059Sluigi m->m_pkthdr.len = m->m_len = total_len; 1460101464Sluigi else 146187059Sluigi#endif 146287059Sluigi { 146387059Sluigi m0 = m_devget(mtod(m, char *), total_len, 146487059Sluigi ETHER_ALIGN, ifp, NULL); 146587059Sluigi sis_newbuf(sc, cur_rx, m); 146687059Sluigi if (m0 == NULL) { 146787059Sluigi ifp->if_ierrors++; 146887059Sluigi continue; 146987059Sluigi } 147087059Sluigi m = m0; 147150974Swpaul } 147250974Swpaul 147350974Swpaul ifp->if_ipackets++; 1474106936Ssam m->m_pkthdr.rcvif = ifp; 1475106936Ssam 1476122689Ssam SIS_UNLOCK(sc); 1477106936Ssam (*ifp->if_input)(ifp, m); 1478122689Ssam SIS_LOCK(sc); 1479193096Sattilio rx_npkts++; 148050974Swpaul } 148150974Swpaul 1482139691Sphk sc->sis_rx_pdsc = cur_rx; 1483193096Sattilio return (rx_npkts); 148450974Swpaul} 148550974Swpaul 148650974Swpaul/* 148750974Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 148850974Swpaul * the list buffers. 148950974Swpaul */ 149050974Swpaul 1491102334Salfredstatic void 1492139740Sphksis_txeof(struct sis_softc *sc) 149350974Swpaul{ 149450974Swpaul struct ifnet *ifp; 149550974Swpaul u_int32_t idx; 149650974Swpaul 1497139715Sphk SIS_LOCK_ASSERT(sc); 1498147256Sbrooks ifp = sc->sis_ifp; 149950974Swpaul 150050974Swpaul /* 150150974Swpaul * Go through our tx list and free mbufs for those 150250974Swpaul * frames that have been transmitted. 150350974Swpaul */ 1504139690Sphk for (idx = sc->sis_tx_cons; sc->sis_tx_cnt > 0; 1505139690Sphk sc->sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) { 1506139690Sphk struct sis_desc *cur_tx = &sc->sis_tx_list[idx]; 150750974Swpaul 150850974Swpaul if (SIS_OWNDESC(cur_tx)) 150950974Swpaul break; 151050974Swpaul 151199163Sluigi if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) 151250974Swpaul continue; 151350974Swpaul 151450974Swpaul if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 151550974Swpaul ifp->if_oerrors++; 151650974Swpaul if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 151750974Swpaul ifp->if_collisions++; 151850974Swpaul if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 151950974Swpaul ifp->if_collisions++; 152050974Swpaul } 152150974Swpaul 152250974Swpaul ifp->if_collisions += 152350974Swpaul (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 152450974Swpaul 152550974Swpaul ifp->if_opackets++; 152650974Swpaul if (cur_tx->sis_mbuf != NULL) { 152750974Swpaul m_freem(cur_tx->sis_mbuf); 152850974Swpaul cur_tx->sis_mbuf = NULL; 152981713Swpaul bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map); 153081713Swpaul bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map); 153150974Swpaul } 153299163Sluigi } 153350974Swpaul 1534139690Sphk if (idx != sc->sis_tx_cons) { 153599163Sluigi /* we freed up some buffers */ 1536139690Sphk sc->sis_tx_cons = idx; 1537148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 153850974Swpaul } 153950974Swpaul 1540166940Sdelphij sc->sis_watchdog_timer = (sc->sis_tx_cnt == 0) ? 0 : 5; 154150974Swpaul 154250974Swpaul return; 154350974Swpaul} 154450974Swpaul 1545102334Salfredstatic void 1546139740Sphksis_tick(void *xsc) 154750974Swpaul{ 154850974Swpaul struct sis_softc *sc; 154950974Swpaul struct mii_data *mii; 155064963Swpaul struct ifnet *ifp; 155150974Swpaul 155250974Swpaul sc = xsc; 1553150583Sjhb SIS_LOCK_ASSERT(sc); 1554117858Scognet sc->in_tick = 1; 1555147256Sbrooks ifp = sc->sis_ifp; 155664963Swpaul 155750974Swpaul mii = device_get_softc(sc->sis_miibus); 155850974Swpaul mii_tick(mii); 155964963Swpaul 1560166940Sdelphij sis_watchdog(sc); 1561166940Sdelphij 156284147Sjlemon if (!sc->sis_link && mii->mii_media_status & IFM_ACTIVE && 156384147Sjlemon IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 156484147Sjlemon sc->sis_link++; 1565131455Smlaier if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1566139714Sphk sis_startl(ifp); 156764963Swpaul } 156864963Swpaul 1569119785Ssam callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 1570117858Scognet sc->in_tick = 0; 157150974Swpaul} 157250974Swpaul 157387902Sluigi#ifdef DEVICE_POLLING 157487902Sluigistatic poll_handler_t sis_poll; 157587902Sluigi 1576193096Sattiliostatic int 157787902Sluigisis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 157887902Sluigi{ 157987973Speter struct sis_softc *sc = ifp->if_softc; 1580193096Sattilio int rx_npkts = 0; 158187973Speter 158287902Sluigi SIS_LOCK(sc); 1583150789Sglebius if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1584150789Sglebius SIS_UNLOCK(sc); 1585193096Sattilio return (rx_npkts); 1586128138Sru } 158787902Sluigi 158887902Sluigi /* 158987902Sluigi * On the sis, reading the status register also clears it. 159087902Sluigi * So before returning to intr mode we must make sure that all 159187902Sluigi * possible pending sources of interrupts have been served. 159287902Sluigi * In practice this means run to completion the *eof routines, 159387902Sluigi * and then call the interrupt routine 159487902Sluigi */ 159587902Sluigi sc->rxcycles = count; 1596193096Sattilio rx_npkts = sis_rxeof(sc); 159787902Sluigi sis_txeof(sc); 1598131455Smlaier if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1599139714Sphk sis_startl(ifp); 160087902Sluigi 160187902Sluigi if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 160287902Sluigi u_int32_t status; 160387902Sluigi 160487902Sluigi /* Reading the ISR register clears all interrupts. */ 160587902Sluigi status = CSR_READ_4(sc, SIS_ISR); 160687902Sluigi 160787902Sluigi if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 1608206909Sbrucec ifp->if_ierrors++; 160987902Sluigi 161087902Sluigi if (status & (SIS_ISR_RX_IDLE)) 161187902Sluigi SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 161287902Sluigi 161387902Sluigi if (status & SIS_ISR_SYSERR) { 161487902Sluigi sis_reset(sc); 1615139715Sphk sis_initl(sc); 161687902Sluigi } 161787902Sluigi } 1618150789Sglebius 161987902Sluigi SIS_UNLOCK(sc); 1620193096Sattilio return (rx_npkts); 162187902Sluigi} 162287902Sluigi#endif /* DEVICE_POLLING */ 162387902Sluigi 1624102334Salfredstatic void 1625139740Sphksis_intr(void *arg) 162650974Swpaul{ 162750974Swpaul struct sis_softc *sc; 162850974Swpaul struct ifnet *ifp; 162950974Swpaul u_int32_t status; 163050974Swpaul 163150974Swpaul sc = arg; 1632147256Sbrooks ifp = sc->sis_ifp; 163350974Swpaul 1634139809Sphk if (sc->sis_stopped) /* Most likely shared interrupt */ 1635139809Sphk return; 1636139809Sphk 163786984Sluigi SIS_LOCK(sc); 163887902Sluigi#ifdef DEVICE_POLLING 1639150789Sglebius if (ifp->if_capenable & IFCAP_POLLING) { 1640150789Sglebius SIS_UNLOCK(sc); 1641150789Sglebius return; 164287902Sluigi } 1643150789Sglebius#endif 164487902Sluigi 164550974Swpaul /* Disable interrupts. */ 164650974Swpaul CSR_WRITE_4(sc, SIS_IER, 0); 164750974Swpaul 164850974Swpaul for (;;) { 1649139717Sphk SIS_LOCK_ASSERT(sc); 165050974Swpaul /* Reading the ISR register clears all interrupts. */ 165150974Swpaul status = CSR_READ_4(sc, SIS_ISR); 165250974Swpaul 165350974Swpaul if ((status & SIS_INTRS) == 0) 165450974Swpaul break; 165550974Swpaul 165686984Sluigi if (status & 165786984Sluigi (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | 165886984Sluigi SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) ) 165950974Swpaul sis_txeof(sc); 166050974Swpaul 1661188550Syongari if (status & (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK | 1662188550Syongari SIS_ISR_RX_ERR | SIS_ISR_RX_IDLE)) 166350974Swpaul sis_rxeof(sc); 166450974Swpaul 1665188550Syongari if (status & SIS_ISR_RX_OFLOW) 1666206909Sbrucec ifp->if_ierrors++; 166750974Swpaul 166886984Sluigi if (status & (SIS_ISR_RX_IDLE)) 166986984Sluigi SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 167086984Sluigi 167150974Swpaul if (status & SIS_ISR_SYSERR) { 167250974Swpaul sis_reset(sc); 1673139715Sphk sis_initl(sc); 167450974Swpaul } 167550974Swpaul } 167650974Swpaul 167750974Swpaul /* Re-enable interrupts. */ 167850974Swpaul CSR_WRITE_4(sc, SIS_IER, 1); 167950974Swpaul 1680131455Smlaier if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1681139714Sphk sis_startl(ifp); 1682139809Sphk 168367087Swpaul SIS_UNLOCK(sc); 168450974Swpaul} 168550974Swpaul 168650974Swpaul/* 168750974Swpaul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 168850974Swpaul * pointers to the fragment pointers. 168950974Swpaul */ 1690102334Salfredstatic int 1691139740Sphksis_encap(struct sis_softc *sc, struct mbuf **m_head, uint32_t *txidx) 169250974Swpaul{ 169350974Swpaul struct sis_desc *f = NULL; 169450974Swpaul struct mbuf *m; 1695112808Ssilby int frag, cur, cnt = 0, chainlen = 0; 169650974Swpaul 169750974Swpaul /* 1698112808Ssilby * If there's no way we can send any packets, return now. 1699112808Ssilby */ 1700139690Sphk if (SIS_TX_LIST_CNT - sc->sis_tx_cnt < 2) 1701112808Ssilby return (ENOBUFS); 1702112808Ssilby 1703112808Ssilby /* 1704112808Ssilby * Count the number of frags in this chain to see if 1705112808Ssilby * we need to m_defrag. Since the descriptor list is shared 1706112808Ssilby * by all packets, we'll m_defrag long chains so that they 1707112808Ssilby * do not use up the entire list, even if they would fit. 1708112808Ssilby */ 1709112808Ssilby 1710121262Ssilby for (m = *m_head; m != NULL; m = m->m_next) 1711112808Ssilby chainlen++; 1712112808Ssilby 1713112808Ssilby if ((chainlen > SIS_TX_LIST_CNT / 4) || 1714139690Sphk ((SIS_TX_LIST_CNT - (chainlen + sc->sis_tx_cnt)) < 2)) { 1715121262Ssilby m = m_defrag(*m_head, M_DONTWAIT); 1716112808Ssilby if (m == NULL) 1717112808Ssilby return (ENOBUFS); 1718121262Ssilby *m_head = m; 1719112808Ssilby } 1720112808Ssilby 1721112808Ssilby /* 172250974Swpaul * Start packing the mbufs in this chain into 172350974Swpaul * the fragment pointers. Stop when we run out 172450974Swpaul * of fragments or hit the end of the mbuf chain. 172550974Swpaul */ 172650974Swpaul cur = frag = *txidx; 172750974Swpaul 1728121262Ssilby for (m = *m_head; m != NULL; m = m->m_next) { 172950974Swpaul if (m->m_len != 0) { 173051042Swpaul if ((SIS_TX_LIST_CNT - 1731139690Sphk (sc->sis_tx_cnt + cnt)) < 2) 173250974Swpaul return(ENOBUFS); 1733139690Sphk f = &sc->sis_tx_list[frag]; 173450974Swpaul f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; 173581713Swpaul bus_dmamap_create(sc->sis_tag, 0, &f->sis_map); 173681713Swpaul bus_dmamap_load(sc->sis_tag, f->sis_map, 173781713Swpaul mtod(m, void *), m->m_len, 173881713Swpaul sis_dma_map_desc_ptr, f, 0); 173981713Swpaul bus_dmamap_sync(sc->sis_tag, 174081713Swpaul f->sis_map, BUS_DMASYNC_PREREAD); 174150974Swpaul if (cnt != 0) 174250974Swpaul f->sis_ctl |= SIS_CMDSTS_OWN; 174350974Swpaul cur = frag; 174450974Swpaul SIS_INC(frag, SIS_TX_LIST_CNT); 174550974Swpaul cnt++; 174650974Swpaul } 174750974Swpaul } 174850974Swpaul 174950974Swpaul if (m != NULL) 175050974Swpaul return(ENOBUFS); 175150974Swpaul 1752139690Sphk sc->sis_tx_list[cur].sis_mbuf = *m_head; 1753139690Sphk sc->sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1754139690Sphk sc->sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1755139690Sphk sc->sis_tx_cnt += cnt; 175650974Swpaul *txidx = frag; 175750974Swpaul 175850974Swpaul return(0); 175950974Swpaul} 176050974Swpaul 176150974Swpaul/* 176250974Swpaul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 176350974Swpaul * to the mbuf data regions directly in the transmit lists. We also save a 176450974Swpaul * copy of the pointers since the transmit list fragment pointers are 176550974Swpaul * physical addresses. 176650974Swpaul */ 176750974Swpaul 1768102334Salfredstatic void 1769139717Sphksis_start(struct ifnet *ifp) 177050974Swpaul{ 177150974Swpaul struct sis_softc *sc; 1772139714Sphk 1773139714Sphk sc = ifp->if_softc; 1774139714Sphk SIS_LOCK(sc); 1775139714Sphk sis_startl(ifp); 1776139714Sphk SIS_UNLOCK(sc); 1777139714Sphk} 1778139714Sphk 1779139714Sphkstatic void 1780139714Sphksis_startl(struct ifnet *ifp) 1781139714Sphk{ 1782139714Sphk struct sis_softc *sc; 178350974Swpaul struct mbuf *m_head = NULL; 1784136269Smlaier u_int32_t idx, queued = 0; 178550974Swpaul 178650974Swpaul sc = ifp->if_softc; 178750974Swpaul 1788139714Sphk SIS_LOCK_ASSERT(sc); 1789139714Sphk 1790139714Sphk if (!sc->sis_link) 179164963Swpaul return; 179264963Swpaul 1793139690Sphk idx = sc->sis_tx_prod; 179450974Swpaul 1795148887Srwatson if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 179650974Swpaul return; 179750974Swpaul 1798139690Sphk while(sc->sis_tx_list[idx].sis_mbuf == NULL) { 1799131455Smlaier IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 180050974Swpaul if (m_head == NULL) 180150974Swpaul break; 180250974Swpaul 1803121262Ssilby if (sis_encap(sc, &m_head, &idx)) { 1804131455Smlaier IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1805148887Srwatson ifp->if_drv_flags |= IFF_DRV_OACTIVE; 180650974Swpaul break; 180750974Swpaul } 180850974Swpaul 1809136269Smlaier queued++; 1810136269Smlaier 181150974Swpaul /* 181250974Swpaul * If there's a BPF listener, bounce a copy of this frame 181350974Swpaul * to him. 181450974Swpaul */ 1815106936Ssam BPF_MTAP(ifp, m_head); 181651583Swpaul 181750974Swpaul } 181850974Swpaul 1819136269Smlaier if (queued) { 1820136269Smlaier /* Transmit */ 1821139690Sphk sc->sis_tx_prod = idx; 1822136269Smlaier SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 182350974Swpaul 1824136269Smlaier /* 1825136269Smlaier * Set a timeout in case the chip goes out to lunch. 1826136269Smlaier */ 1827166940Sdelphij sc->sis_watchdog_timer = 5; 1828136269Smlaier } 182950974Swpaul} 183050974Swpaul 1831102334Salfredstatic void 1832139715Sphksis_init(void *xsc) 183350974Swpaul{ 183450974Swpaul struct sis_softc *sc = xsc; 1835139715Sphk 1836139715Sphk SIS_LOCK(sc); 1837139717Sphk sis_initl(sc); 1838139715Sphk SIS_UNLOCK(sc); 1839139715Sphk} 1840139715Sphk 1841139715Sphkstatic void 1842139717Sphksis_initl(struct sis_softc *sc) 1843139715Sphk{ 1844147256Sbrooks struct ifnet *ifp = sc->sis_ifp; 184550974Swpaul struct mii_data *mii; 184650974Swpaul 1847139715Sphk SIS_LOCK_ASSERT(sc); 184850974Swpaul 184950974Swpaul /* 185050974Swpaul * Cancel pending I/O and free all RX/TX buffers. 185150974Swpaul */ 185250974Swpaul sis_stop(sc); 1853123833Sphk sc->sis_stopped = 0; 185450974Swpaul 1855119712Sphk#ifdef notyet 1856119712Sphk if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) { 1857119712Sphk /* 1858119712Sphk * Configure 400usec of interrupt holdoff. This is based 1859119712Sphk * on emperical tests on a Soekris 4801. 1860119712Sphk */ 1861119712Sphk CSR_WRITE_4(sc, NS_IHR, 0x100 | 4); 1862119712Sphk } 1863119712Sphk#endif 1864119712Sphk 186550974Swpaul mii = device_get_softc(sc->sis_miibus); 186650974Swpaul 186750974Swpaul /* Set MAC address */ 186862672Swpaul if (sc->sis_type == SIS_TYPE_83815) { 186962672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 187062672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1871152315Sru ((u_int16_t *)IF_LLADDR(sc->sis_ifp))[0]); 187262672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 187362672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1874152315Sru ((u_int16_t *)IF_LLADDR(sc->sis_ifp))[1]); 187562672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 187662672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1877152315Sru ((u_int16_t *)IF_LLADDR(sc->sis_ifp))[2]); 187862672Swpaul } else { 187962672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 188062672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1881152315Sru ((u_int16_t *)IF_LLADDR(sc->sis_ifp))[0]); 188262672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 188362672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1884152315Sru ((u_int16_t *)IF_LLADDR(sc->sis_ifp))[1]); 188562672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 188662672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1887152315Sru ((u_int16_t *)IF_LLADDR(sc->sis_ifp))[2]); 188862672Swpaul } 188950974Swpaul 1890139802Sphk /* Init circular TX/RX lists. */ 1891139802Sphk if (sis_ring_init(sc) != 0) { 1892162315Sglebius device_printf(sc->sis_dev, 1893150583Sjhb "initialization failed: no memory for rx buffers\n"); 189450974Swpaul sis_stop(sc); 189550974Swpaul return; 189650974Swpaul } 189750974Swpaul 189850974Swpaul /* 1899139806Sphk * Short Cable Receive Errors (MP21.E) 1900139806Sphk * also: Page 78 of the DP83815 data sheet (september 2002 version) 1901123491Sphk * recommends the following register settings "for optimum 1902181002Sjhb * performance." for rev 15C. Set this also for 15D parts as 1903181002Sjhb * they require it in practice. 1904123491Sphk */ 1905139806Sphk if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr <= NS_SRR_15D) { 1906123491Sphk CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 1907123491Sphk CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 1908181002Sjhb /* set val for c2 */ 1909181002Sjhb CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 1910181002Sjhb /* load/kill c2 */ 1911181002Sjhb CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 1912181002Sjhb /* rais SD off, from 4 to c */ 1913181002Sjhb CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 1914123491Sphk CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 1915123491Sphk } 1916123491Sphk 1917123491Sphk 1918123491Sphk /* 191962672Swpaul * For the NatSemi chip, we have to explicitly enable the 192062672Swpaul * reception of ARP frames, as well as turn on the 'perfect 192162672Swpaul * match' filter where we store the station address, otherwise 192262672Swpaul * we won't receive unicasts meant for this host. 192362672Swpaul */ 192462672Swpaul if (sc->sis_type == SIS_TYPE_83815) { 192562672Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 192662672Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 192762672Swpaul } 192862672Swpaul 192950974Swpaul /* If we want promiscuous mode, set the allframes bit. */ 193050974Swpaul if (ifp->if_flags & IFF_PROMISC) { 193150974Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 193250974Swpaul } else { 193350974Swpaul SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 193450974Swpaul } 193550974Swpaul 193650974Swpaul /* 193750974Swpaul * Set the capture broadcast bit to capture broadcast frames. 193850974Swpaul */ 193950974Swpaul if (ifp->if_flags & IFF_BROADCAST) { 194050974Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 194150974Swpaul } else { 194250974Swpaul SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 194350974Swpaul } 194450974Swpaul 194550974Swpaul /* 194650974Swpaul * Load the multicast filter. 194750974Swpaul */ 194862672Swpaul if (sc->sis_type == SIS_TYPE_83815) 194962672Swpaul sis_setmulti_ns(sc); 195062672Swpaul else 195162672Swpaul sis_setmulti_sis(sc); 195250974Swpaul 195350974Swpaul /* Turn the receive filter on */ 195450974Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 195550974Swpaul 195650974Swpaul /* 195750974Swpaul * Load the address of the RX and TX lists. 195850974Swpaul */ 1959139690Sphk CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_rx_paddr); 1960139690Sphk CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_tx_paddr); 196150974Swpaul 1962109059Smbr /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of 1963109059Smbr * the PCI bus. When this bit is set, the Max DMA Burst Size 1964109059Smbr * for TX/RX DMA should be no larger than 16 double words. 1965109059Smbr */ 1966109059Smbr if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) { 1967109059Smbr CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); 1968109059Smbr } else { 1969109059Smbr CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); 1970109059Smbr } 197164963Swpaul 197287390Sjhay /* Accept Long Packets for VLAN support */ 197387390Sjhay SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 197487390Sjhay 197550974Swpaul /* Set TX configuration */ 197664963Swpaul if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 197764963Swpaul CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 197864963Swpaul } else { 197964963Swpaul CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 198064963Swpaul } 198150974Swpaul 198264963Swpaul /* Set full/half duplex mode. */ 198364963Swpaul if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 198464963Swpaul SIS_SETBIT(sc, SIS_TX_CFG, 198564963Swpaul (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 198664963Swpaul SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 198764963Swpaul } else { 198864963Swpaul SIS_CLRBIT(sc, SIS_TX_CFG, 198964963Swpaul (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 199064963Swpaul SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 199164963Swpaul } 199264963Swpaul 1993139807Sphk if (sc->sis_type == SIS_TYPE_83816) { 1994139807Sphk /* 1995139807Sphk * MPII03.D: Half Duplex Excessive Collisions. 1996139807Sphk * Also page 49 in 83816 manual 1997139807Sphk */ 1998139807Sphk SIS_SETBIT(sc, SIS_TX_CFG, SIS_TXCFG_MPII03D); 1999139807Sphk } 2000139807Sphk 2001139808Sphk if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr < NS_SRR_16A && 2002119130Ssam IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 2003119130Ssam uint32_t reg; 2004119130Ssam 2005119130Ssam /* 2006139806Sphk * Short Cable Receive Errors (MP21.E) 2007119130Ssam */ 2008119130Ssam CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 2009139806Sphk reg = CSR_READ_4(sc, NS_PHY_DSPCFG) & 0xfff; 2010139806Sphk CSR_WRITE_4(sc, NS_PHY_DSPCFG, reg | 0x1000); 2011206909Sbrucec DELAY(100); 2012139806Sphk reg = CSR_READ_4(sc, NS_PHY_TDATA) & 0xff; 2013139806Sphk if ((reg & 0x0080) == 0 || (reg > 0xd8 && reg <= 0xff)) { 2014162315Sglebius device_printf(sc->sis_dev, 2015139806Sphk "Applying short cable fix (reg=%x)\n", reg); 2016119130Ssam CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8); 2017181000Sjhb SIS_SETBIT(sc, NS_PHY_DSPCFG, 0x20); 2018119130Ssam } 2019119130Ssam CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 2020119130Ssam } 2021119130Ssam 202250974Swpaul /* 202350974Swpaul * Enable interrupts. 202450974Swpaul */ 202550974Swpaul CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 202687902Sluigi#ifdef DEVICE_POLLING 202787902Sluigi /* 202887902Sluigi * ... only enable interrupts if we are not polling, make sure 202987902Sluigi * they are off otherwise. 203087902Sluigi */ 2031150789Sglebius if (ifp->if_capenable & IFCAP_POLLING) 203287902Sluigi CSR_WRITE_4(sc, SIS_IER, 0); 203387902Sluigi else 2034150789Sglebius#endif 203550974Swpaul CSR_WRITE_4(sc, SIS_IER, 1); 203650974Swpaul 203750974Swpaul /* Enable receiver and transmitter. */ 203850974Swpaul SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 203950974Swpaul SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 204050974Swpaul 204164963Swpaul#ifdef notdef 204250974Swpaul mii_mediachg(mii); 204364963Swpaul#endif 204450974Swpaul 2045148887Srwatson ifp->if_drv_flags |= IFF_DRV_RUNNING; 2046148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 204750974Swpaul 2048117858Scognet if (!sc->in_tick) 2049119785Ssam callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 205050974Swpaul} 205150974Swpaul 205250974Swpaul/* 205350974Swpaul * Set media options. 205450974Swpaul */ 2055102334Salfredstatic int 2056139740Sphksis_ifmedia_upd(struct ifnet *ifp) 205750974Swpaul{ 205850974Swpaul struct sis_softc *sc; 205964963Swpaul struct mii_data *mii; 206050974Swpaul 206150974Swpaul sc = ifp->if_softc; 206250974Swpaul 2063150583Sjhb SIS_LOCK(sc); 206464963Swpaul mii = device_get_softc(sc->sis_miibus); 206564963Swpaul sc->sis_link = 0; 206664963Swpaul if (mii->mii_instance) { 206764963Swpaul struct mii_softc *miisc; 206872012Sphk LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 206964963Swpaul mii_phy_reset(miisc); 207064963Swpaul } 207164963Swpaul mii_mediachg(mii); 2072150583Sjhb SIS_UNLOCK(sc); 207350974Swpaul 207450974Swpaul return(0); 207550974Swpaul} 207650974Swpaul 207750974Swpaul/* 207850974Swpaul * Report current media status. 207950974Swpaul */ 2080102334Salfredstatic void 2081139740Sphksis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 208250974Swpaul{ 208350974Swpaul struct sis_softc *sc; 208450974Swpaul struct mii_data *mii; 208550974Swpaul 208650974Swpaul sc = ifp->if_softc; 208750974Swpaul 2088150583Sjhb SIS_LOCK(sc); 208950974Swpaul mii = device_get_softc(sc->sis_miibus); 209050974Swpaul mii_pollstat(mii); 2091150583Sjhb SIS_UNLOCK(sc); 209250974Swpaul ifmr->ifm_active = mii->mii_media_active; 209350974Swpaul ifmr->ifm_status = mii->mii_media_status; 209450974Swpaul} 209550974Swpaul 2096102334Salfredstatic int 2097139740Sphksis_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 209850974Swpaul{ 209950974Swpaul struct sis_softc *sc = ifp->if_softc; 210050974Swpaul struct ifreq *ifr = (struct ifreq *) data; 210150974Swpaul struct mii_data *mii; 210267087Swpaul int error = 0; 210350974Swpaul 210450974Swpaul switch(command) { 210550974Swpaul case SIOCSIFFLAGS: 2106150583Sjhb SIS_LOCK(sc); 210750974Swpaul if (ifp->if_flags & IFF_UP) { 2108150583Sjhb sis_initl(sc); 2109148887Srwatson } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2110139741Sphk sis_stop(sc); 211150974Swpaul } 2112150583Sjhb SIS_UNLOCK(sc); 211350974Swpaul error = 0; 211450974Swpaul break; 211550974Swpaul case SIOCADDMULTI: 211650974Swpaul case SIOCDELMULTI: 211781713Swpaul SIS_LOCK(sc); 211862672Swpaul if (sc->sis_type == SIS_TYPE_83815) 211962672Swpaul sis_setmulti_ns(sc); 212062672Swpaul else 212162672Swpaul sis_setmulti_sis(sc); 212281713Swpaul SIS_UNLOCK(sc); 212350974Swpaul error = 0; 212450974Swpaul break; 212550974Swpaul case SIOCGIFMEDIA: 212650974Swpaul case SIOCSIFMEDIA: 212750974Swpaul mii = device_get_softc(sc->sis_miibus); 212850974Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 212950974Swpaul break; 2130128138Sru case SIOCSIFCAP: 2131150789Sglebius /* ok, disable interrupts */ 2132150789Sglebius#ifdef DEVICE_POLLING 2133150789Sglebius if (ifr->ifr_reqcap & IFCAP_POLLING && 2134150789Sglebius !(ifp->if_capenable & IFCAP_POLLING)) { 2135150789Sglebius error = ether_poll_register(sis_poll, ifp); 2136150789Sglebius if (error) 2137150789Sglebius return(error); 2138150789Sglebius SIS_LOCK(sc); 2139150789Sglebius /* Disable interrupts */ 2140150789Sglebius CSR_WRITE_4(sc, SIS_IER, 0); 2141150789Sglebius ifp->if_capenable |= IFCAP_POLLING; 2142150789Sglebius SIS_UNLOCK(sc); 2143150789Sglebius return (error); 2144150789Sglebius 2145150789Sglebius } 2146150789Sglebius if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 2147150789Sglebius ifp->if_capenable & IFCAP_POLLING) { 2148150789Sglebius error = ether_poll_deregister(ifp); 2149150789Sglebius /* Enable interrupts. */ 2150150789Sglebius SIS_LOCK(sc); 2151150789Sglebius CSR_WRITE_4(sc, SIS_IER, 1); 2152150789Sglebius ifp->if_capenable &= ~IFCAP_POLLING; 2153150789Sglebius SIS_UNLOCK(sc); 2154150789Sglebius return (error); 2155150789Sglebius } 2156150789Sglebius#endif /* DEVICE_POLLING */ 2157128138Sru break; 215850974Swpaul default: 2159106936Ssam error = ether_ioctl(ifp, command, data); 216050974Swpaul break; 216150974Swpaul } 216250974Swpaul 216350974Swpaul return(error); 216450974Swpaul} 216550974Swpaul 2166102334Salfredstatic void 2167166940Sdelphijsis_watchdog(struct sis_softc *sc) 216850974Swpaul{ 216950974Swpaul 2170166940Sdelphij SIS_LOCK_ASSERT(sc); 2171139797Sphk if (sc->sis_stopped) { 2172139797Sphk SIS_UNLOCK(sc); 2173139797Sphk return; 2174139797Sphk } 217567087Swpaul 2176166940Sdelphij if (sc->sis_watchdog_timer == 0 || --sc->sis_watchdog_timer >0) 2177166940Sdelphij return; 217850974Swpaul 2179166940Sdelphij device_printf(sc->sis_dev, "watchdog timeout\n"); 2180166940Sdelphij sc->sis_ifp->if_oerrors++; 2181166940Sdelphij 218250974Swpaul sis_stop(sc); 218350974Swpaul sis_reset(sc); 2184139715Sphk sis_initl(sc); 218550974Swpaul 2186166940Sdelphij if (!IFQ_DRV_IS_EMPTY(&sc->sis_ifp->if_snd)) 2187166940Sdelphij sis_startl(sc->sis_ifp); 218850974Swpaul} 218950974Swpaul 219050974Swpaul/* 219150974Swpaul * Stop the adapter and free any mbufs allocated to the 219250974Swpaul * RX and TX lists. 219350974Swpaul */ 2194102334Salfredstatic void 2195139740Sphksis_stop(struct sis_softc *sc) 219650974Swpaul{ 2197139805Sphk int i; 2198139805Sphk struct ifnet *ifp; 2199139805Sphk struct sis_desc *dp; 220050974Swpaul 2201123833Sphk if (sc->sis_stopped) 2202123833Sphk return; 2203139717Sphk SIS_LOCK_ASSERT(sc); 2204147256Sbrooks ifp = sc->sis_ifp; 2205166940Sdelphij sc->sis_watchdog_timer = 0; 220650974Swpaul 2207119785Ssam callout_stop(&sc->sis_stat_ch); 220887472Speter 2209148887Srwatson ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 221050974Swpaul CSR_WRITE_4(sc, SIS_IER, 0); 221150974Swpaul CSR_WRITE_4(sc, SIS_IMR, 0); 2212139798Sphk CSR_READ_4(sc, SIS_ISR); /* clear any interrupts already pending */ 221350974Swpaul SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 221450974Swpaul DELAY(1000); 221550974Swpaul CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 221650974Swpaul CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 221750974Swpaul 221864963Swpaul sc->sis_link = 0; 221964963Swpaul 222050974Swpaul /* 222150974Swpaul * Free data in the RX lists. 222250974Swpaul */ 2223139805Sphk dp = &sc->sis_rx_list[0]; 2224139805Sphk for (i = 0; i < SIS_RX_LIST_CNT; i++, dp++) { 2225139805Sphk if (dp->sis_mbuf == NULL) 2226139805Sphk continue; 2227139805Sphk bus_dmamap_unload(sc->sis_tag, dp->sis_map); 2228139805Sphk bus_dmamap_destroy(sc->sis_tag, dp->sis_map); 2229139805Sphk m_freem(dp->sis_mbuf); 2230139805Sphk dp->sis_mbuf = NULL; 223150974Swpaul } 2232139805Sphk bzero(sc->sis_rx_list, SIS_RX_LIST_SZ); 223350974Swpaul 223450974Swpaul /* 223550974Swpaul * Free the TX list buffers. 223650974Swpaul */ 2237139805Sphk dp = &sc->sis_tx_list[0]; 2238139805Sphk for (i = 0; i < SIS_TX_LIST_CNT; i++, dp++) { 2239139805Sphk if (dp->sis_mbuf == NULL) 2240139805Sphk continue; 2241139805Sphk bus_dmamap_unload(sc->sis_tag, dp->sis_map); 2242139805Sphk bus_dmamap_destroy(sc->sis_tag, dp->sis_map); 2243139805Sphk m_freem(dp->sis_mbuf); 2244139805Sphk dp->sis_mbuf = NULL; 224550974Swpaul } 224650974Swpaul 2247139805Sphk bzero(sc->sis_tx_list, SIS_TX_LIST_SZ); 224850974Swpaul 2249123833Sphk sc->sis_stopped = 1; 225050974Swpaul} 225150974Swpaul 225250974Swpaul/* 225350974Swpaul * Stop all chip I/O so that the kernel's probe routines don't 225450974Swpaul * get confused by errant DMAs when rebooting. 225550974Swpaul */ 2256188463Simpstatic int 2257139717Sphksis_shutdown(device_t dev) 225850974Swpaul{ 225950974Swpaul struct sis_softc *sc; 226050974Swpaul 226150974Swpaul sc = device_get_softc(dev); 226267087Swpaul SIS_LOCK(sc); 226350974Swpaul sis_reset(sc); 226450974Swpaul sis_stop(sc); 226567087Swpaul SIS_UNLOCK(sc); 2266188463Simp return (0); 226750974Swpaul} 2268139800Sphk 2269139800Sphkstatic device_method_t sis_methods[] = { 2270139800Sphk /* Device interface */ 2271139800Sphk DEVMETHOD(device_probe, sis_probe), 2272139800Sphk DEVMETHOD(device_attach, sis_attach), 2273139800Sphk DEVMETHOD(device_detach, sis_detach), 2274139800Sphk DEVMETHOD(device_shutdown, sis_shutdown), 2275139800Sphk 2276139800Sphk /* bus interface */ 2277139800Sphk DEVMETHOD(bus_print_child, bus_generic_print_child), 2278139800Sphk DEVMETHOD(bus_driver_added, bus_generic_driver_added), 2279139800Sphk 2280139800Sphk /* MII interface */ 2281139800Sphk DEVMETHOD(miibus_readreg, sis_miibus_readreg), 2282139800Sphk DEVMETHOD(miibus_writereg, sis_miibus_writereg), 2283139800Sphk DEVMETHOD(miibus_statchg, sis_miibus_statchg), 2284139800Sphk 2285139800Sphk { 0, 0 } 2286139800Sphk}; 2287139800Sphk 2288139800Sphkstatic driver_t sis_driver = { 2289139800Sphk "sis", 2290139800Sphk sis_methods, 2291139800Sphk sizeof(struct sis_softc) 2292139800Sphk}; 2293139800Sphk 2294139800Sphkstatic devclass_t sis_devclass; 2295139800Sphk 2296139800SphkDRIVER_MODULE(sis, pci, sis_driver, sis_devclass, 0, 0); 2297139800SphkDRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 2298