if_sis.c revision 166901
1139825Simp/*- 2139740Sphk * Copyright (c) 2005 Poul-Henning Kamp <phk@FreeBSD.org> 350974Swpaul * Copyright (c) 1997, 1998, 1999 450974Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 550974Swpaul * 650974Swpaul * Redistribution and use in source and binary forms, with or without 750974Swpaul * modification, are permitted provided that the following conditions 850974Swpaul * are met: 950974Swpaul * 1. Redistributions of source code must retain the above copyright 1050974Swpaul * notice, this list of conditions and the following disclaimer. 1150974Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1250974Swpaul * notice, this list of conditions and the following disclaimer in the 1350974Swpaul * documentation and/or other materials provided with the distribution. 1450974Swpaul * 3. All advertising materials mentioning features or use of this software 1550974Swpaul * must display the following acknowledgement: 1650974Swpaul * This product includes software developed by Bill Paul. 1750974Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1850974Swpaul * may be used to endorse or promote products derived from this software 1950974Swpaul * without specific prior written permission. 2050974Swpaul * 2150974Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2250974Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2350974Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2450974Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2550974Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2650974Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2750974Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2850974Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2950974Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3050974Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3150974Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3250974Swpaul */ 3350974Swpaul 34122678Sobrien#include <sys/cdefs.h> 35122678Sobrien__FBSDID("$FreeBSD: head/sys/pci/if_sis.c 166901 2007-02-23 12:19:07Z piso $"); 36122678Sobrien 3750974Swpaul/* 3850974Swpaul * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 3950974Swpaul * available from http://www.sis.com.tw. 4050974Swpaul * 4164963Swpaul * This driver also supports the NatSemi DP83815. Datasheets are 4264963Swpaul * available from http://www.national.com. 4364963Swpaul * 4450974Swpaul * Written by Bill Paul <wpaul@ee.columbia.edu> 4550974Swpaul * Electrical Engineering Department 4650974Swpaul * Columbia University, New York City 4750974Swpaul */ 4850974Swpaul/* 4950974Swpaul * The SiS 900 is a fairly simple chip. It uses bus master DMA with 5050974Swpaul * simple TX and RX descriptors of 3 longwords in size. The receiver 5150974Swpaul * has a single perfect filter entry for the station address and a 5250974Swpaul * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 5350974Swpaul * transceiver while the 7016 requires an external transceiver chip. 5450974Swpaul * Both chips offer the standard bit-bang MII interface as well as 5550974Swpaul * an enchanced PHY interface which simplifies accessing MII registers. 5650974Swpaul * 5750974Swpaul * The only downside to this chipset is that RX descriptors must be 5850974Swpaul * longword aligned. 5950974Swpaul */ 6050974Swpaul 61150968Sglebius#ifdef HAVE_KERNEL_OPTION_HEADERS 62150968Sglebius#include "opt_device_polling.h" 63150968Sglebius#endif 64150968Sglebius 6550974Swpaul#include <sys/param.h> 6650974Swpaul#include <sys/systm.h> 6750974Swpaul#include <sys/sockio.h> 6850974Swpaul#include <sys/mbuf.h> 6950974Swpaul#include <sys/malloc.h> 7050974Swpaul#include <sys/kernel.h> 71129876Sphk#include <sys/module.h> 7250974Swpaul#include <sys/socket.h> 7350974Swpaul 7450974Swpaul#include <net/if.h> 7550974Swpaul#include <net/if_arp.h> 7650974Swpaul#include <net/ethernet.h> 7750974Swpaul#include <net/if_dl.h> 7850974Swpaul#include <net/if_media.h> 7987390Sjhay#include <net/if_types.h> 8087390Sjhay#include <net/if_vlan_var.h> 8150974Swpaul 8250974Swpaul#include <net/bpf.h> 8350974Swpaul 8450974Swpaul#include <machine/bus.h> 8550974Swpaul#include <machine/resource.h> 8650974Swpaul#include <sys/bus.h> 8750974Swpaul#include <sys/rman.h> 8850974Swpaul 8950974Swpaul#include <dev/mii/mii.h> 9050974Swpaul#include <dev/mii/miivar.h> 9150974Swpaul 92119288Simp#include <dev/pci/pcireg.h> 93119288Simp#include <dev/pci/pcivar.h> 9450974Swpaul 9550974Swpaul#define SIS_USEIOSPACE 9650974Swpaul 9750974Swpaul#include <pci/if_sisreg.h> 9850974Swpaul 99113506SmdoddMODULE_DEPEND(sis, pci, 1, 1, 1); 100113506SmdoddMODULE_DEPEND(sis, ether, 1, 1, 1); 10159758SpeterMODULE_DEPEND(sis, miibus, 1, 1, 1); 10259758Speter 103151545Simp/* "device miibus" required. See GENERIC if you get errors here. */ 10450974Swpaul#include "miibus_if.h" 10550974Swpaul 106150369Sphk#define SIS_LOCK(_sc) mtx_lock(&(_sc)->sis_mtx) 107150369Sphk#define SIS_UNLOCK(_sc) mtx_unlock(&(_sc)->sis_mtx) 108150369Sphk#define SIS_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sis_mtx, MA_OWNED) 109150369Sphk 11050974Swpaul/* 111150369Sphk * register space access macros 112150369Sphk */ 113150526Sphk#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sis_res[0], reg, val) 114150369Sphk 115150526Sphk#define CSR_READ_4(sc, reg) bus_read_4(sc->sis_res[0], reg) 116150369Sphk 117150526Sphk#define CSR_READ_2(sc, reg) bus_read_2(sc->sis_res[0], reg) 118150369Sphk 119150369Sphk/* 12050974Swpaul * Various supported device vendors/types and their names. 12150974Swpaul */ 12250974Swpaulstatic struct sis_type sis_devs[] = { 12350974Swpaul { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 12450974Swpaul { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 125119712Sphk { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" }, 12650974Swpaul { 0, 0, NULL } 12750974Swpaul}; 12850974Swpaul 129139801Sphkstatic int sis_detach(device_t); 130139801Sphkstatic void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *); 131139801Sphkstatic int sis_ifmedia_upd(struct ifnet *); 132139801Sphkstatic void sis_init(void *); 133139801Sphkstatic void sis_initl(struct sis_softc *); 134139801Sphkstatic void sis_intr(void *); 135139801Sphkstatic int sis_ioctl(struct ifnet *, u_long, caddr_t); 136139801Sphkstatic int sis_newbuf(struct sis_softc *, struct sis_desc *, struct mbuf *); 137139801Sphkstatic void sis_start(struct ifnet *); 138139801Sphkstatic void sis_startl(struct ifnet *); 139139801Sphkstatic void sis_stop(struct sis_softc *); 140139801Sphkstatic void sis_watchdog(struct ifnet *); 14150974Swpaul 142150526Sphk 143150526Sphkstatic struct resource_spec sis_res_spec[] = { 14450974Swpaul#ifdef SIS_USEIOSPACE 145150526Sphk { SYS_RES_IOPORT, SIS_PCI_LOIO, RF_ACTIVE}, 14650974Swpaul#else 147150526Sphk { SYS_RES_MEMORY, SIS_PCI_LOMEM, RF_ACTIVE}, 14850974Swpaul#endif 149150526Sphk { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE}, 150150526Sphk { -1, 0 } 151150526Sphk}; 15250974Swpaul 15350974Swpaul#define SIS_SETBIT(sc, reg, x) \ 15450974Swpaul CSR_WRITE_4(sc, reg, \ 15550974Swpaul CSR_READ_4(sc, reg) | (x)) 15650974Swpaul 15750974Swpaul#define SIS_CLRBIT(sc, reg, x) \ 15850974Swpaul CSR_WRITE_4(sc, reg, \ 15950974Swpaul CSR_READ_4(sc, reg) & ~(x)) 16050974Swpaul 16150974Swpaul#define SIO_SET(x) \ 16250974Swpaul CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 16350974Swpaul 16450974Swpaul#define SIO_CLR(x) \ 16550974Swpaul CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 16650974Swpaul 16781713Swpaulstatic void 168139740Sphksis_dma_map_desc_next(void *arg, bus_dma_segment_t *segs, int nseg, int error) 16981713Swpaul{ 17081713Swpaul struct sis_desc *r; 17181713Swpaul 17281713Swpaul r = arg; 17381713Swpaul r->sis_next = segs->ds_addr; 17481713Swpaul} 17581713Swpaul 17681713Swpaulstatic void 177139740Sphksis_dma_map_desc_ptr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 17881713Swpaul{ 17981713Swpaul struct sis_desc *r; 18081713Swpaul 18181713Swpaul r = arg; 18281713Swpaul r->sis_ptr = segs->ds_addr; 18381713Swpaul} 18481713Swpaul 18581713Swpaulstatic void 186139740Sphksis_dma_map_ring(void *arg, bus_dma_segment_t *segs, int nseg, int error) 18781713Swpaul{ 18881713Swpaul u_int32_t *p; 18981713Swpaul 19081713Swpaul p = arg; 19181713Swpaul *p = segs->ds_addr; 19281713Swpaul} 19381713Swpaul 19462672Swpaul/* 19562672Swpaul * Routine to reverse the bits in a word. Stolen almost 19662672Swpaul * verbatim from /usr/games/fortune. 19762672Swpaul */ 198139740Sphkstatic uint16_t 199139740Sphksis_reverse(uint16_t n) 20062672Swpaul{ 20162672Swpaul n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 20262672Swpaul n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 20362672Swpaul n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 20462672Swpaul n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 20562672Swpaul 20662672Swpaul return(n); 20762672Swpaul} 20862672Swpaul 209102334Salfredstatic void 210139740Sphksis_delay(struct sis_softc *sc) 21150974Swpaul{ 21250974Swpaul int idx; 21350974Swpaul 21450974Swpaul for (idx = (300 / 33) + 1; idx > 0; idx--) 21550974Swpaul CSR_READ_4(sc, SIS_CSR); 21650974Swpaul} 21750974Swpaul 218102334Salfredstatic void 219139740Sphksis_eeprom_idle(struct sis_softc *sc) 22050974Swpaul{ 221139708Sphk int i; 22250974Swpaul 22350974Swpaul SIO_SET(SIS_EECTL_CSEL); 22450974Swpaul sis_delay(sc); 22550974Swpaul SIO_SET(SIS_EECTL_CLK); 22650974Swpaul sis_delay(sc); 22750974Swpaul 22850974Swpaul for (i = 0; i < 25; i++) { 22950974Swpaul SIO_CLR(SIS_EECTL_CLK); 23050974Swpaul sis_delay(sc); 23150974Swpaul SIO_SET(SIS_EECTL_CLK); 23250974Swpaul sis_delay(sc); 23350974Swpaul } 23450974Swpaul 23550974Swpaul SIO_CLR(SIS_EECTL_CLK); 23650974Swpaul sis_delay(sc); 23750974Swpaul SIO_CLR(SIS_EECTL_CSEL); 23850974Swpaul sis_delay(sc); 23950974Swpaul CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 24050974Swpaul} 24150974Swpaul 24250974Swpaul/* 24350974Swpaul * Send a read command and address to the EEPROM, check for ACK. 24450974Swpaul */ 245102334Salfredstatic void 246139740Sphksis_eeprom_putbyte(struct sis_softc *sc, int addr) 24750974Swpaul{ 248139708Sphk int d, i; 24950974Swpaul 25050974Swpaul d = addr | SIS_EECMD_READ; 25150974Swpaul 25250974Swpaul /* 25350974Swpaul * Feed in each bit and stobe the clock. 25450974Swpaul */ 25550974Swpaul for (i = 0x400; i; i >>= 1) { 25650974Swpaul if (d & i) { 25750974Swpaul SIO_SET(SIS_EECTL_DIN); 25850974Swpaul } else { 25950974Swpaul SIO_CLR(SIS_EECTL_DIN); 26050974Swpaul } 26150974Swpaul sis_delay(sc); 26250974Swpaul SIO_SET(SIS_EECTL_CLK); 26350974Swpaul sis_delay(sc); 26450974Swpaul SIO_CLR(SIS_EECTL_CLK); 26550974Swpaul sis_delay(sc); 26650974Swpaul } 26750974Swpaul} 26850974Swpaul 26950974Swpaul/* 27050974Swpaul * Read a word of data stored in the EEPROM at address 'addr.' 27150974Swpaul */ 272102334Salfredstatic void 273139740Sphksis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest) 27450974Swpaul{ 275139708Sphk int i; 27650974Swpaul u_int16_t word = 0; 27750974Swpaul 27850974Swpaul /* Force EEPROM to idle state. */ 27950974Swpaul sis_eeprom_idle(sc); 28050974Swpaul 28150974Swpaul /* Enter EEPROM access mode. */ 28250974Swpaul sis_delay(sc); 28362672Swpaul SIO_CLR(SIS_EECTL_CLK); 28462672Swpaul sis_delay(sc); 28550974Swpaul SIO_SET(SIS_EECTL_CSEL); 28650974Swpaul sis_delay(sc); 28750974Swpaul 28850974Swpaul /* 28950974Swpaul * Send address of word we want to read. 29050974Swpaul */ 29150974Swpaul sis_eeprom_putbyte(sc, addr); 29250974Swpaul 29350974Swpaul /* 29450974Swpaul * Start reading bits from EEPROM. 29550974Swpaul */ 29650974Swpaul for (i = 0x8000; i; i >>= 1) { 29750974Swpaul SIO_SET(SIS_EECTL_CLK); 29850974Swpaul sis_delay(sc); 29950974Swpaul if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 30050974Swpaul word |= i; 30150974Swpaul sis_delay(sc); 30250974Swpaul SIO_CLR(SIS_EECTL_CLK); 30350974Swpaul sis_delay(sc); 30450974Swpaul } 30550974Swpaul 30650974Swpaul /* Turn off EEPROM access mode. */ 30750974Swpaul sis_eeprom_idle(sc); 30850974Swpaul 30950974Swpaul *dest = word; 31050974Swpaul} 31150974Swpaul 31250974Swpaul/* 31350974Swpaul * Read a sequence of words from the EEPROM. 31450974Swpaul */ 315102334Salfredstatic void 316139740Sphksis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap) 31750974Swpaul{ 31850974Swpaul int i; 31950974Swpaul u_int16_t word = 0, *ptr; 32050974Swpaul 32150974Swpaul for (i = 0; i < cnt; i++) { 32250974Swpaul sis_eeprom_getword(sc, off + i, &word); 32350974Swpaul ptr = (u_int16_t *)(dest + (i * 2)); 32450974Swpaul if (swap) 32550974Swpaul *ptr = ntohs(word); 32650974Swpaul else 32750974Swpaul *ptr = word; 32850974Swpaul } 32950974Swpaul} 33050974Swpaul 331144243Sobrien#if defined(__i386__) || defined(__amd64__) 332102334Salfredstatic device_t 333139740Sphksis_find_bridge(device_t dev) 33472197Swpaul{ 33572197Swpaul devclass_t pci_devclass; 33672197Swpaul device_t *pci_devices; 33772197Swpaul int pci_count = 0; 33872197Swpaul device_t *pci_children; 33972197Swpaul int pci_childcount = 0; 34072197Swpaul device_t *busp, *childp; 34187994Sarchie device_t child = NULL; 34272197Swpaul int i, j; 34372197Swpaul 34472197Swpaul if ((pci_devclass = devclass_find("pci")) == NULL) 34572197Swpaul return(NULL); 34672197Swpaul 34772197Swpaul devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 34872197Swpaul 34972197Swpaul for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 35072197Swpaul pci_childcount = 0; 35172197Swpaul device_get_children(*busp, &pci_children, &pci_childcount); 35272197Swpaul for (j = 0, childp = pci_children; 35372197Swpaul j < pci_childcount; j++, childp++) { 35472197Swpaul if (pci_get_vendor(*childp) == SIS_VENDORID && 35572197Swpaul pci_get_device(*childp) == 0x0008) { 35687994Sarchie child = *childp; 35787994Sarchie goto done; 35872197Swpaul } 35972197Swpaul } 36072197Swpaul } 36172197Swpaul 36287994Sarchiedone: 36372197Swpaul free(pci_devices, M_TEMP); 36472197Swpaul free(pci_children, M_TEMP); 36587994Sarchie return(child); 36672197Swpaul} 36772197Swpaul 368102334Salfredstatic void 369139740Sphksis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off, int cnt) 37072197Swpaul{ 37172197Swpaul device_t bridge; 37272197Swpaul u_int8_t reg; 37372197Swpaul int i; 37472197Swpaul bus_space_tag_t btag; 37572197Swpaul 37672197Swpaul bridge = sis_find_bridge(dev); 37772197Swpaul if (bridge == NULL) 37872197Swpaul return; 37972197Swpaul reg = pci_read_config(bridge, 0x48, 1); 38072197Swpaul pci_write_config(bridge, 0x48, reg|0x40, 1); 38172197Swpaul 38272197Swpaul /* XXX */ 383144243Sobrien#if defined(__i386__) 38472197Swpaul btag = I386_BUS_SPACE_IO; 385144243Sobrien#elif defined(__amd64__) 386144243Sobrien btag = AMD64_BUS_SPACE_IO; 387144243Sobrien#endif 38872197Swpaul 38972197Swpaul for (i = 0; i < cnt; i++) { 39072197Swpaul bus_space_write_1(btag, 0x0, 0x70, i + off); 39172197Swpaul *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 39272197Swpaul } 39372197Swpaul 39472197Swpaul pci_write_config(bridge, 0x48, reg & ~0x40, 1); 39572197Swpaul return; 39672197Swpaul} 39789296Swpaul 398102334Salfredstatic void 399139740Sphksis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest) 40089296Swpaul{ 40189296Swpaul u_int32_t filtsave, csrsave; 40289296Swpaul 40389296Swpaul filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 40489296Swpaul csrsave = CSR_READ_4(sc, SIS_CSR); 40589296Swpaul 40689296Swpaul CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 40789296Swpaul CSR_WRITE_4(sc, SIS_CSR, 0); 40889296Swpaul 40989296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 41089296Swpaul 41189296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 41289296Swpaul ((u_int16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 41389296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 41489296Swpaul ((u_int16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 41589296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 41689296Swpaul ((u_int16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 41789296Swpaul 41889296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 41989296Swpaul CSR_WRITE_4(sc, SIS_CSR, csrsave); 42089296Swpaul return; 42189296Swpaul} 42272197Swpaul#endif 42372197Swpaul 424109060Smbr/* 425109060Smbr * Sync the PHYs by setting data bit and strobing the clock 32 times. 426109060Smbr */ 427139740Sphkstatic void 428139740Sphksis_mii_sync(struct sis_softc *sc) 429109060Smbr{ 430139708Sphk int i; 431109060Smbr 432109060Smbr SIO_SET(SIS_MII_DIR|SIS_MII_DATA); 433109060Smbr 434109060Smbr for (i = 0; i < 32; i++) { 435109060Smbr SIO_SET(SIS_MII_CLK); 436109060Smbr DELAY(1); 437109060Smbr SIO_CLR(SIS_MII_CLK); 438109060Smbr DELAY(1); 439109060Smbr } 440109060Smbr} 441109060Smbr 442109060Smbr/* 443109060Smbr * Clock a series of bits through the MII. 444109060Smbr */ 445139740Sphkstatic void 446139740Sphksis_mii_send(struct sis_softc *sc, uint32_t bits, int cnt) 447109060Smbr{ 448109060Smbr int i; 449109060Smbr 450109060Smbr SIO_CLR(SIS_MII_CLK); 451109060Smbr 452109060Smbr for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 453109060Smbr if (bits & i) { 454109060Smbr SIO_SET(SIS_MII_DATA); 455109060Smbr } else { 456109060Smbr SIO_CLR(SIS_MII_DATA); 457109060Smbr } 458109060Smbr DELAY(1); 459109060Smbr SIO_CLR(SIS_MII_CLK); 460109060Smbr DELAY(1); 461109060Smbr SIO_SET(SIS_MII_CLK); 462109060Smbr } 463109060Smbr} 464109060Smbr 465109060Smbr/* 466109060Smbr * Read an PHY register through the MII. 467109060Smbr */ 468139740Sphkstatic int 469139740Sphksis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame) 470109060Smbr{ 471150583Sjhb int i, ack; 472109060Smbr 473109060Smbr /* 474109060Smbr * Set up frame for RX. 475109060Smbr */ 476109060Smbr frame->mii_stdelim = SIS_MII_STARTDELIM; 477109060Smbr frame->mii_opcode = SIS_MII_READOP; 478109060Smbr frame->mii_turnaround = 0; 479109060Smbr frame->mii_data = 0; 480109060Smbr 481109060Smbr /* 482109060Smbr * Turn on data xmit. 483109060Smbr */ 484109060Smbr SIO_SET(SIS_MII_DIR); 485109060Smbr 486109060Smbr sis_mii_sync(sc); 487109060Smbr 488109060Smbr /* 489109060Smbr * Send command/address info. 490109060Smbr */ 491109060Smbr sis_mii_send(sc, frame->mii_stdelim, 2); 492109060Smbr sis_mii_send(sc, frame->mii_opcode, 2); 493109060Smbr sis_mii_send(sc, frame->mii_phyaddr, 5); 494109060Smbr sis_mii_send(sc, frame->mii_regaddr, 5); 495109060Smbr 496109060Smbr /* Idle bit */ 497109060Smbr SIO_CLR((SIS_MII_CLK|SIS_MII_DATA)); 498109060Smbr DELAY(1); 499109060Smbr SIO_SET(SIS_MII_CLK); 500109060Smbr DELAY(1); 501109060Smbr 502109060Smbr /* Turn off xmit. */ 503109060Smbr SIO_CLR(SIS_MII_DIR); 504109060Smbr 505109060Smbr /* Check for ack */ 506109060Smbr SIO_CLR(SIS_MII_CLK); 507109060Smbr DELAY(1); 508109060Smbr ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA; 509109060Smbr SIO_SET(SIS_MII_CLK); 510109060Smbr DELAY(1); 511109060Smbr 512109060Smbr /* 513109060Smbr * Now try reading data bits. If the ack failed, we still 514109060Smbr * need to clock through 16 cycles to keep the PHY(s) in sync. 515109060Smbr */ 516109060Smbr if (ack) { 517109060Smbr for(i = 0; i < 16; i++) { 518109060Smbr SIO_CLR(SIS_MII_CLK); 519109060Smbr DELAY(1); 520109060Smbr SIO_SET(SIS_MII_CLK); 521109060Smbr DELAY(1); 522109060Smbr } 523109060Smbr goto fail; 524109060Smbr } 525109060Smbr 526109060Smbr for (i = 0x8000; i; i >>= 1) { 527109060Smbr SIO_CLR(SIS_MII_CLK); 528109060Smbr DELAY(1); 529109060Smbr if (!ack) { 530109060Smbr if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA) 531109060Smbr frame->mii_data |= i; 532109060Smbr DELAY(1); 533109060Smbr } 534109060Smbr SIO_SET(SIS_MII_CLK); 535109060Smbr DELAY(1); 536109060Smbr } 537109060Smbr 538109060Smbrfail: 539109060Smbr 540109060Smbr SIO_CLR(SIS_MII_CLK); 541109060Smbr DELAY(1); 542109060Smbr SIO_SET(SIS_MII_CLK); 543109060Smbr DELAY(1); 544109060Smbr 545109060Smbr if (ack) 546109060Smbr return(1); 547109060Smbr return(0); 548109060Smbr} 549109060Smbr 550109060Smbr/* 551109060Smbr * Write to a PHY register through the MII. 552109060Smbr */ 553139740Sphkstatic int 554139740Sphksis_mii_writereg(struct sis_softc *sc, struct sis_mii_frame *frame) 555109060Smbr{ 556109060Smbr 557109060Smbr /* 558109060Smbr * Set up frame for TX. 559109060Smbr */ 560109060Smbr 561109060Smbr frame->mii_stdelim = SIS_MII_STARTDELIM; 562109060Smbr frame->mii_opcode = SIS_MII_WRITEOP; 563109060Smbr frame->mii_turnaround = SIS_MII_TURNAROUND; 564109060Smbr 565109060Smbr /* 566109060Smbr * Turn on data output. 567109060Smbr */ 568109060Smbr SIO_SET(SIS_MII_DIR); 569109060Smbr 570109060Smbr sis_mii_sync(sc); 571109060Smbr 572109060Smbr sis_mii_send(sc, frame->mii_stdelim, 2); 573109060Smbr sis_mii_send(sc, frame->mii_opcode, 2); 574109060Smbr sis_mii_send(sc, frame->mii_phyaddr, 5); 575109060Smbr sis_mii_send(sc, frame->mii_regaddr, 5); 576109060Smbr sis_mii_send(sc, frame->mii_turnaround, 2); 577109060Smbr sis_mii_send(sc, frame->mii_data, 16); 578109060Smbr 579109060Smbr /* Idle bit. */ 580109060Smbr SIO_SET(SIS_MII_CLK); 581109060Smbr DELAY(1); 582109060Smbr SIO_CLR(SIS_MII_CLK); 583109060Smbr DELAY(1); 584109060Smbr 585109060Smbr /* 586109060Smbr * Turn off xmit. 587109060Smbr */ 588109060Smbr SIO_CLR(SIS_MII_DIR); 589109060Smbr 590109060Smbr return(0); 591109060Smbr} 592109060Smbr 593102334Salfredstatic int 594139740Sphksis_miibus_readreg(device_t dev, int phy, int reg) 59550974Swpaul{ 59650974Swpaul struct sis_softc *sc; 597109060Smbr struct sis_mii_frame frame; 59850974Swpaul 59950974Swpaul sc = device_get_softc(dev); 60050974Swpaul 60162672Swpaul if (sc->sis_type == SIS_TYPE_83815) { 60262672Swpaul if (phy != 0) 60362672Swpaul return(0); 60462672Swpaul /* 60562672Swpaul * The NatSemi chip can take a while after 60662672Swpaul * a reset to come ready, during which the BMSR 60762672Swpaul * returns a value of 0. This is *never* supposed 60862672Swpaul * to happen: some of the BMSR bits are meant to 60962672Swpaul * be hardwired in the on position, and this can 61062672Swpaul * confuse the miibus code a bit during the probe 61162672Swpaul * and attach phase. So we make an effort to check 61262672Swpaul * for this condition and wait for it to clear. 61362672Swpaul */ 61462672Swpaul if (!CSR_READ_4(sc, NS_BMSR)) 61562672Swpaul DELAY(1000); 616109060Smbr return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 61762672Swpaul } 61862672Swpaul 619109976Smbr /* 620109976Smbr * Chipsets < SIS_635 seem not to be able to read/write 621109976Smbr * through mdio. Use the enhanced PHY access register 622109976Smbr * again for them. 623109976Smbr */ 62489296Swpaul if (sc->sis_type == SIS_TYPE_900 && 625109976Smbr sc->sis_rev < SIS_REV_635) { 626109976Smbr int i, val = 0; 62750974Swpaul 628109976Smbr if (phy != 0) 629109976Smbr return(0); 63050974Swpaul 631109976Smbr CSR_WRITE_4(sc, SIS_PHYCTL, 632109976Smbr (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 633109976Smbr SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 63450974Swpaul 635109976Smbr for (i = 0; i < SIS_TIMEOUT; i++) { 636109976Smbr if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 637109976Smbr break; 638109976Smbr } 639109976Smbr 640109976Smbr if (i == SIS_TIMEOUT) { 641162315Sglebius device_printf(sc->sis_dev, "PHY failed to come ready\n"); 642109976Smbr return(0); 643109976Smbr } 644109976Smbr 645109976Smbr val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 646109976Smbr 647109976Smbr if (val == 0xFFFF) 648109976Smbr return(0); 649109976Smbr 650109976Smbr return(val); 651109976Smbr } else { 652109976Smbr bzero((char *)&frame, sizeof(frame)); 653109976Smbr 654109976Smbr frame.mii_phyaddr = phy; 655109976Smbr frame.mii_regaddr = reg; 656109976Smbr sis_mii_readreg(sc, &frame); 657109976Smbr 658109976Smbr return(frame.mii_data); 659109976Smbr } 66050974Swpaul} 66150974Swpaul 662102334Salfredstatic int 663139740Sphksis_miibus_writereg(device_t dev, int phy, int reg, int data) 66450974Swpaul{ 66550974Swpaul struct sis_softc *sc; 666109060Smbr struct sis_mii_frame frame; 66750974Swpaul 66850974Swpaul sc = device_get_softc(dev); 66950974Swpaul 67062672Swpaul if (sc->sis_type == SIS_TYPE_83815) { 67162672Swpaul if (phy != 0) 67262672Swpaul return(0); 67362672Swpaul CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 67462672Swpaul return(0); 67562672Swpaul } 67662672Swpaul 677109976Smbr /* 678109976Smbr * Chipsets < SIS_635 seem not to be able to read/write 679109976Smbr * through mdio. Use the enhanced PHY access register 680109976Smbr * again for them. 681109976Smbr */ 682109976Smbr if (sc->sis_type == SIS_TYPE_900 && 683109976Smbr sc->sis_rev < SIS_REV_635) { 684109976Smbr int i; 68550974Swpaul 686109976Smbr if (phy != 0) 687109976Smbr return(0); 68850974Swpaul 689109976Smbr CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 690109976Smbr (reg << 6) | SIS_PHYOP_WRITE); 691109976Smbr SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 69250974Swpaul 693109976Smbr for (i = 0; i < SIS_TIMEOUT; i++) { 694109976Smbr if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 695109976Smbr break; 696109976Smbr } 69750974Swpaul 698109976Smbr if (i == SIS_TIMEOUT) 699162315Sglebius device_printf(sc->sis_dev, "PHY failed to come ready\n"); 700109976Smbr } else { 701109976Smbr bzero((char *)&frame, sizeof(frame)); 702109976Smbr 703109976Smbr frame.mii_phyaddr = phy; 704109976Smbr frame.mii_regaddr = reg; 705109976Smbr frame.mii_data = data; 706109976Smbr sis_mii_writereg(sc, &frame); 707109976Smbr } 70850974Swpaul return(0); 70950974Swpaul} 71050974Swpaul 711102334Salfredstatic void 712139717Sphksis_miibus_statchg(device_t dev) 71350974Swpaul{ 71450974Swpaul struct sis_softc *sc; 71550974Swpaul 71650974Swpaul sc = device_get_softc(dev); 717139717Sphk SIS_LOCK_ASSERT(sc); 718139717Sphk sis_initl(sc); 71950974Swpaul} 72050974Swpaul 721139740Sphkstatic uint32_t 722139740Sphksis_mchash(struct sis_softc *sc, const uint8_t *addr) 72350974Swpaul{ 724130270Snaddy uint32_t crc; 72550974Swpaul 72650974Swpaul /* Compute CRC for the address value. */ 727130270Snaddy crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 72850974Swpaul 72962672Swpaul /* 73062672Swpaul * return the filter bit position 73162672Swpaul * 73262672Swpaul * The NatSemi chip has a 512-bit filter, which is 73362672Swpaul * different than the SiS, so we special-case it. 73462672Swpaul */ 73562672Swpaul if (sc->sis_type == SIS_TYPE_83815) 736109060Smbr return (crc >> 23); 737109976Smbr else if (sc->sis_rev >= SIS_REV_635 || 738109976Smbr sc->sis_rev == SIS_REV_900B) 739109060Smbr return (crc >> 24); 740109976Smbr else 741109976Smbr return (crc >> 25); 74250974Swpaul} 74350974Swpaul 744102334Salfredstatic void 745139740Sphksis_setmulti_ns(struct sis_softc *sc) 74650974Swpaul{ 74750974Swpaul struct ifnet *ifp; 74850974Swpaul struct ifmultiaddr *ifma; 74950974Swpaul u_int32_t h = 0, i, filtsave; 75062672Swpaul int bit, index; 75150974Swpaul 752147256Sbrooks ifp = sc->sis_ifp; 75350974Swpaul 75450974Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 75562672Swpaul SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 75650974Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 75750974Swpaul return; 75850974Swpaul } 75950974Swpaul 76062672Swpaul /* 76162672Swpaul * We have to explicitly enable the multicast hash table 76262672Swpaul * on the NatSemi chip if we want to use it, which we do. 76362672Swpaul */ 76462672Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 76550974Swpaul SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 76650974Swpaul 76750974Swpaul filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 76850974Swpaul 76950974Swpaul /* first, zot all the existing hash bits */ 77062672Swpaul for (i = 0; i < 32; i++) { 77162672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 77262672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 77362672Swpaul } 77462672Swpaul 775148654Srwatson IF_ADDR_LOCK(ifp); 77672084Sphk TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 77762672Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 77862672Swpaul continue; 779122625Sobrien h = sis_mchash(sc, 780122625Sobrien LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 78162672Swpaul index = h >> 3; 78262672Swpaul bit = h & 0x1F; 78362672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 78462672Swpaul if (bit > 0xF) 78562672Swpaul bit -= 0x10; 78662672Swpaul SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 78762672Swpaul } 788148654Srwatson IF_ADDR_UNLOCK(ifp); 78962672Swpaul 79062672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 79162672Swpaul 79262672Swpaul return; 79362672Swpaul} 79462672Swpaul 795102334Salfredstatic void 796139740Sphksis_setmulti_sis(struct sis_softc *sc) 79762672Swpaul{ 79862672Swpaul struct ifnet *ifp; 79962672Swpaul struct ifmultiaddr *ifma; 800109060Smbr u_int32_t h, i, n, ctl; 801109060Smbr u_int16_t hashes[16]; 80262672Swpaul 803147256Sbrooks ifp = sc->sis_ifp; 80462672Swpaul 805109060Smbr /* hash table size */ 806109976Smbr if (sc->sis_rev >= SIS_REV_635 || 807109976Smbr sc->sis_rev == SIS_REV_900B) 808109976Smbr n = 16; 809109976Smbr else 810109976Smbr n = 8; 81162672Swpaul 812109060Smbr ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE; 81362672Swpaul 814109060Smbr if (ifp->if_flags & IFF_BROADCAST) 815109060Smbr ctl |= SIS_RXFILTCTL_BROAD; 81662672Swpaul 817109060Smbr if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 818109060Smbr ctl |= SIS_RXFILTCTL_ALLMULTI; 819109060Smbr if (ifp->if_flags & IFF_PROMISC) 820109060Smbr ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS; 821109060Smbr for (i = 0; i < n; i++) 822109060Smbr hashes[i] = ~0; 823109060Smbr } else { 824109060Smbr for (i = 0; i < n; i++) 825109060Smbr hashes[i] = 0; 826109060Smbr i = 0; 827148654Srwatson IF_ADDR_LOCK(ifp); 828109060Smbr TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 829109060Smbr if (ifma->ifma_addr->sa_family != AF_LINK) 830109060Smbr continue; 831122625Sobrien h = sis_mchash(sc, 832109060Smbr LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 833109060Smbr hashes[h >> 4] |= 1 << (h & 0xf); 834109060Smbr i++; 835109060Smbr } 836148654Srwatson IF_ADDR_UNLOCK(ifp); 837109060Smbr if (i > n) { 838109060Smbr ctl |= SIS_RXFILTCTL_ALLMULTI; 839109060Smbr for (i = 0; i < n; i++) 840109060Smbr hashes[i] = ~0; 841109060Smbr } 84250974Swpaul } 84350974Swpaul 844109060Smbr for (i = 0; i < n; i++) { 845109060Smbr CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); 846109060Smbr CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); 84750974Swpaul } 84850974Swpaul 849109060Smbr CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl); 85050974Swpaul} 85150974Swpaul 852102334Salfredstatic void 853139717Sphksis_reset(struct sis_softc *sc) 85450974Swpaul{ 855139708Sphk int i; 85650974Swpaul 85750974Swpaul SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 85850974Swpaul 85950974Swpaul for (i = 0; i < SIS_TIMEOUT; i++) { 86050974Swpaul if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 86150974Swpaul break; 86250974Swpaul } 86350974Swpaul 86450974Swpaul if (i == SIS_TIMEOUT) 865162315Sglebius device_printf(sc->sis_dev, "reset never completed\n"); 86650974Swpaul 86750974Swpaul /* Wait a little while for the chip to get its brains in order. */ 86850974Swpaul DELAY(1000); 86972813Swpaul 87072813Swpaul /* 87172813Swpaul * If this is a NetSemi chip, make sure to clear 87272813Swpaul * PME mode. 87372813Swpaul */ 87472813Swpaul if (sc->sis_type == SIS_TYPE_83815) { 87572813Swpaul CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 87672813Swpaul CSR_WRITE_4(sc, NS_CLKRUN, 0); 87772813Swpaul } 87872813Swpaul 87950974Swpaul return; 88050974Swpaul} 88150974Swpaul 88250974Swpaul/* 88350974Swpaul * Probe for an SiS chip. Check the PCI vendor and device 88450974Swpaul * IDs against our list and return a device name if we find a match. 88550974Swpaul */ 886102334Salfredstatic int 887139740Sphksis_probe(device_t dev) 88850974Swpaul{ 88950974Swpaul struct sis_type *t; 89050974Swpaul 89150974Swpaul t = sis_devs; 89250974Swpaul 89350974Swpaul while(t->sis_name != NULL) { 89450974Swpaul if ((pci_get_vendor(dev) == t->sis_vid) && 89550974Swpaul (pci_get_device(dev) == t->sis_did)) { 89650974Swpaul device_set_desc(dev, t->sis_name); 897142398Simp return (BUS_PROBE_DEFAULT); 89850974Swpaul } 89950974Swpaul t++; 90050974Swpaul } 90150974Swpaul 90250974Swpaul return(ENXIO); 90350974Swpaul} 90450974Swpaul 90550974Swpaul/* 90650974Swpaul * Attach the interface. Allocate softc structures, do ifmedia 90750974Swpaul * setup and ethernet/BPF attach. 90850974Swpaul */ 909102334Salfredstatic int 910139740Sphksis_attach(device_t dev) 91150974Swpaul{ 91250974Swpaul u_char eaddr[ETHER_ADDR_LEN]; 91350974Swpaul struct sis_softc *sc; 91450974Swpaul struct ifnet *ifp; 915150583Sjhb int error = 0, waittime = 0; 91650974Swpaul 917109061Smbr waittime = 0; 91850974Swpaul sc = device_get_softc(dev); 91950974Swpaul 920162315Sglebius sc->sis_dev = dev; 921119712Sphk 92293818Sjhb mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 923139810Sphk MTX_DEF); 924150583Sjhb callout_init_mtx(&sc->sis_stat_ch, &sc->sis_mtx, 0); 92569583Swpaul 92650974Swpaul if (pci_get_device(dev) == SIS_DEVICEID_900) 92750974Swpaul sc->sis_type = SIS_TYPE_900; 92850974Swpaul if (pci_get_device(dev) == SIS_DEVICEID_7016) 92950974Swpaul sc->sis_type = SIS_TYPE_7016; 93062672Swpaul if (pci_get_vendor(dev) == NS_VENDORID) 93162672Swpaul sc->sis_type = SIS_TYPE_83815; 93250974Swpaul 93389296Swpaul sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 93450974Swpaul /* 93550974Swpaul * Map control/status registers. 93650974Swpaul */ 93772813Swpaul pci_enable_busmaster(dev); 93850974Swpaul 939150526Sphk error = bus_alloc_resources(dev, sis_res_spec, sc->sis_res); 940150583Sjhb if (error) { 941150583Sjhb device_printf(dev, "couldn't allocate resources\n"); 942150583Sjhb goto fail; 943150583Sjhb } 94450974Swpaul 94550974Swpaul /* Reset the adapter. */ 94650974Swpaul sis_reset(sc); 94750974Swpaul 948109976Smbr if (sc->sis_type == SIS_TYPE_900 && 949109976Smbr (sc->sis_rev == SIS_REV_635 || 950109976Smbr sc->sis_rev == SIS_REV_900B)) { 951109976Smbr SIO_SET(SIS_CFG_RND_CNT); 952109976Smbr SIO_SET(SIS_CFG_PERR_DETECT); 953109976Smbr } 954109976Smbr 95550974Swpaul /* 95650974Swpaul * Get station address from the EEPROM. 95750974Swpaul */ 95862672Swpaul switch (pci_get_vendor(dev)) { 95962672Swpaul case NS_VENDORID: 960119712Sphk sc->sis_srr = CSR_READ_4(sc, NS_SRR); 961119712Sphk 962119712Sphk /* We can't update the device description, so spew */ 963119712Sphk if (sc->sis_srr == NS_SRR_15C) 964119712Sphk device_printf(dev, "Silicon Revision: DP83815C\n"); 965119712Sphk else if (sc->sis_srr == NS_SRR_15D) 966119712Sphk device_printf(dev, "Silicon Revision: DP83815D\n"); 967119712Sphk else if (sc->sis_srr == NS_SRR_16A) 968119712Sphk device_printf(dev, "Silicon Revision: DP83816A\n"); 969119712Sphk else 970119712Sphk device_printf(dev, "Silicon Revision %x\n", sc->sis_srr); 971119712Sphk 97262672Swpaul /* 97362672Swpaul * Reading the MAC address out of the EEPROM on 97462672Swpaul * the NatSemi chip takes a bit more work than 97562672Swpaul * you'd expect. The address spans 4 16-bit words, 97662672Swpaul * with the first word containing only a single bit. 97762672Swpaul * You have to shift everything over one bit to 97862672Swpaul * get it aligned properly. Also, the bits are 97962672Swpaul * stored backwards (the LSB is really the MSB, 98062672Swpaul * and so on) so you have to reverse them in order 98162672Swpaul * to get the MAC address into the form we want. 98262672Swpaul * Why? Who the hell knows. 98362672Swpaul */ 98462672Swpaul { 98562672Swpaul u_int16_t tmp[4]; 98650974Swpaul 98762672Swpaul sis_read_eeprom(sc, (caddr_t)&tmp, 98862672Swpaul NS_EE_NODEADDR, 4, 0); 98962672Swpaul 99062672Swpaul /* Shift everything over one bit. */ 99162672Swpaul tmp[3] = tmp[3] >> 1; 99262681Swpaul tmp[3] |= tmp[2] << 15; 99362672Swpaul tmp[2] = tmp[2] >> 1; 99462681Swpaul tmp[2] |= tmp[1] << 15; 99562672Swpaul tmp[1] = tmp[1] >> 1; 99662681Swpaul tmp[1] |= tmp[0] << 15; 99762672Swpaul 99862672Swpaul /* Now reverse all the bits. */ 99962672Swpaul tmp[3] = sis_reverse(tmp[3]); 100062672Swpaul tmp[2] = sis_reverse(tmp[2]); 100162672Swpaul tmp[1] = sis_reverse(tmp[1]); 100262672Swpaul 100362672Swpaul bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); 100462672Swpaul } 100562672Swpaul break; 100662672Swpaul case SIS_VENDORID: 100762672Swpaul default: 1008144243Sobrien#if defined(__i386__) || defined(__amd64__) 100972197Swpaul /* 101072197Swpaul * If this is a SiS 630E chipset with an embedded 101172197Swpaul * SiS 900 controller, we have to read the MAC address 101272197Swpaul * from the APC CMOS RAM. Our method for doing this 101372197Swpaul * is very ugly since we have to reach out and grab 101472197Swpaul * ahold of hardware for which we cannot properly 101572197Swpaul * allocate resources. This code is only compiled on 101672197Swpaul * the i386 architecture since the SiS 630E chipset 101772197Swpaul * is for x86 motherboards only. Note that there are 101872197Swpaul * a lot of magic numbers in this hack. These are 101972197Swpaul * taken from SiS's Linux driver. I'd like to replace 102072197Swpaul * them with proper symbolic definitions, but that 102172197Swpaul * requires some datasheets that I don't have access 102272197Swpaul * to at the moment. 102372197Swpaul */ 102489296Swpaul if (sc->sis_rev == SIS_REV_630S || 102589296Swpaul sc->sis_rev == SIS_REV_630E || 102690328Sambrisko sc->sis_rev == SIS_REV_630EA1) 102772197Swpaul sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 102889296Swpaul 102990328Sambrisko else if (sc->sis_rev == SIS_REV_635 || 103090328Sambrisko sc->sis_rev == SIS_REV_630ET) 103189296Swpaul sis_read_mac(sc, dev, (caddr_t)&eaddr); 1032109061Smbr else if (sc->sis_rev == SIS_REV_96x) { 1033109061Smbr /* Allow to read EEPROM from LAN. It is shared 1034109061Smbr * between a 1394 controller and the NIC and each 1035109061Smbr * time we access it, we need to set SIS_EECMD_REQ. 1036109061Smbr */ 1037109061Smbr SIO_SET(SIS_EECMD_REQ); 1038109061Smbr for (waittime = 0; waittime < SIS_TIMEOUT; 1039109061Smbr waittime++) { 1040109061Smbr /* Force EEPROM to idle state. */ 1041109061Smbr sis_eeprom_idle(sc); 1042109061Smbr if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { 1043109061Smbr sis_read_eeprom(sc, (caddr_t)&eaddr, 1044109061Smbr SIS_EE_NODEADDR, 3, 0); 1045109061Smbr break; 1046109061Smbr } 1047109061Smbr DELAY(1); 1048109061Smbr } 1049109061Smbr /* 1050109061Smbr * Set SIS_EECTL_CLK to high, so a other master 1051109061Smbr * can operate on the i2c bus. 1052109061Smbr */ 1053109061Smbr SIO_SET(SIS_EECTL_CLK); 1054109061Smbr /* Refuse EEPROM access by LAN */ 1055109061Smbr SIO_SET(SIS_EECMD_DONE); 1056109061Smbr } else 105772197Swpaul#endif 105872197Swpaul sis_read_eeprom(sc, (caddr_t)&eaddr, 105972197Swpaul SIS_EE_NODEADDR, 3, 0); 106062672Swpaul break; 106162672Swpaul } 106262672Swpaul 106381713Swpaul /* 106481713Swpaul * Allocate the parent bus DMA tag appropriate for PCI. 106581713Swpaul */ 106681713Swpaul#define SIS_NSEG_NEW 32 106781713Swpaul error = bus_dma_tag_create(NULL, /* parent */ 106881713Swpaul 1, 0, /* alignment, boundary */ 106981713Swpaul BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 107081713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 107181713Swpaul NULL, NULL, /* filter, filterarg */ 107281713Swpaul MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */ 107381713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 107481713Swpaul BUS_DMA_ALLOCNOW, /* flags */ 1075117126Sscottl NULL, NULL, /* lockfunc, lockarg */ 107681713Swpaul &sc->sis_parent_tag); 1077112872Snjl if (error) 1078112872Snjl goto fail; 107950974Swpaul 108081713Swpaul /* 1081112872Snjl * Now allocate a tag for the DMA descriptor lists and a chunk 1082112872Snjl * of DMA-able memory based on the tag. Also obtain the physical 1083112872Snjl * addresses of the RX and TX ring, which we'll need later. 108481713Swpaul * All of our lists are allocated as a contiguous block 108581713Swpaul * of memory. 108681713Swpaul */ 108781713Swpaul error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 108881713Swpaul 1, 0, /* alignment, boundary */ 108981713Swpaul BUS_SPACE_MAXADDR, /* lowaddr */ 109081713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 109181713Swpaul NULL, NULL, /* filter, filterarg */ 109281713Swpaul SIS_RX_LIST_SZ, 1, /* maxsize,nsegments */ 109381713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 109481713Swpaul 0, /* flags */ 1095117126Sscottl busdma_lock_mutex, /* lockfunc */ 1096117126Sscottl &Giant, /* lockarg */ 1097139690Sphk &sc->sis_rx_tag); 1098112872Snjl if (error) 1099112872Snjl goto fail; 110081713Swpaul 1101139690Sphk error = bus_dmamem_alloc(sc->sis_rx_tag, 1102139690Sphk (void **)&sc->sis_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1103139690Sphk &sc->sis_rx_dmamap); 1104112872Snjl 1105112872Snjl if (error) { 1106150583Sjhb device_printf(dev, "no memory for rx list buffers!\n"); 1107139690Sphk bus_dma_tag_destroy(sc->sis_rx_tag); 1108139690Sphk sc->sis_rx_tag = NULL; 1109112872Snjl goto fail; 1110112872Snjl } 1111112872Snjl 1112139690Sphk error = bus_dmamap_load(sc->sis_rx_tag, 1113139690Sphk sc->sis_rx_dmamap, &(sc->sis_rx_list[0]), 1114112872Snjl sizeof(struct sis_desc), sis_dma_map_ring, 1115139690Sphk &sc->sis_rx_paddr, 0); 1116112872Snjl 1117112872Snjl if (error) { 1118150583Sjhb device_printf(dev, "cannot get address of the rx ring!\n"); 1119139690Sphk bus_dmamem_free(sc->sis_rx_tag, 1120139690Sphk sc->sis_rx_list, sc->sis_rx_dmamap); 1121139690Sphk bus_dma_tag_destroy(sc->sis_rx_tag); 1122139690Sphk sc->sis_rx_tag = NULL; 1123112872Snjl goto fail; 1124112872Snjl } 1125112872Snjl 112681713Swpaul error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 112781713Swpaul 1, 0, /* alignment, boundary */ 112881713Swpaul BUS_SPACE_MAXADDR, /* lowaddr */ 112981713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 113081713Swpaul NULL, NULL, /* filter, filterarg */ 113181713Swpaul SIS_TX_LIST_SZ, 1, /* maxsize,nsegments */ 113281713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 113381713Swpaul 0, /* flags */ 1134117126Sscottl busdma_lock_mutex, /* lockfunc */ 1135117126Sscottl &Giant, /* lockarg */ 1136139690Sphk &sc->sis_tx_tag); 1137112872Snjl if (error) 1138112872Snjl goto fail; 113981713Swpaul 1140139690Sphk error = bus_dmamem_alloc(sc->sis_tx_tag, 1141139690Sphk (void **)&sc->sis_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1142139690Sphk &sc->sis_tx_dmamap); 114381713Swpaul 114481713Swpaul if (error) { 1145150583Sjhb device_printf(dev, "no memory for tx list buffers!\n"); 1146139690Sphk bus_dma_tag_destroy(sc->sis_tx_tag); 1147139690Sphk sc->sis_tx_tag = NULL; 114850974Swpaul goto fail; 114950974Swpaul } 115050974Swpaul 1151139690Sphk error = bus_dmamap_load(sc->sis_tx_tag, 1152139690Sphk sc->sis_tx_dmamap, &(sc->sis_tx_list[0]), 1153112872Snjl sizeof(struct sis_desc), sis_dma_map_ring, 1154139690Sphk &sc->sis_tx_paddr, 0); 115581713Swpaul 115681713Swpaul if (error) { 1157150583Sjhb device_printf(dev, "cannot get address of the tx ring!\n"); 1158139690Sphk bus_dmamem_free(sc->sis_tx_tag, 1159139690Sphk sc->sis_tx_list, sc->sis_tx_dmamap); 1160139690Sphk bus_dma_tag_destroy(sc->sis_tx_tag); 1161139690Sphk sc->sis_tx_tag = NULL; 116281713Swpaul goto fail; 116381713Swpaul } 116481713Swpaul 1165112872Snjl error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1166112872Snjl 1, 0, /* alignment, boundary */ 1167112872Snjl BUS_SPACE_MAXADDR, /* lowaddr */ 1168112872Snjl BUS_SPACE_MAXADDR, /* highaddr */ 1169112872Snjl NULL, NULL, /* filter, filterarg */ 1170112872Snjl MCLBYTES, 1, /* maxsize,nsegments */ 1171112872Snjl BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1172112872Snjl 0, /* flags */ 1173117126Sscottl busdma_lock_mutex, /* lockfunc */ 1174117126Sscottl &Giant, /* lockarg */ 1175112872Snjl &sc->sis_tag); 1176112872Snjl if (error) 1177112872Snjl goto fail; 117881713Swpaul 117981713Swpaul /* 118081713Swpaul * Obtain the physical addresses of the RX and TX 118181713Swpaul * rings which we'll need later in the init routine. 118281713Swpaul */ 118381713Swpaul 1184147256Sbrooks ifp = sc->sis_ifp = if_alloc(IFT_ETHER); 1185147256Sbrooks if (ifp == NULL) { 1186150583Sjhb device_printf(dev, "can not if_alloc()\n"); 1187147256Sbrooks error = ENOSPC; 1188147256Sbrooks goto fail; 1189147256Sbrooks } 119050974Swpaul ifp->if_softc = sc; 1191121816Sbrooks if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 119250974Swpaul ifp->if_mtu = ETHERMTU; 119350974Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 119450974Swpaul ifp->if_ioctl = sis_ioctl; 119550974Swpaul ifp->if_start = sis_start; 119650974Swpaul ifp->if_watchdog = sis_watchdog; 119750974Swpaul ifp->if_init = sis_init; 1198131455Smlaier IFQ_SET_MAXLEN(&ifp->if_snd, SIS_TX_LIST_CNT - 1); 1199131455Smlaier ifp->if_snd.ifq_drv_maxlen = SIS_TX_LIST_CNT - 1; 1200131455Smlaier IFQ_SET_READY(&ifp->if_snd); 120150974Swpaul 120250974Swpaul /* 120350974Swpaul * Do MII setup. 120450974Swpaul */ 120550974Swpaul if (mii_phy_probe(dev, &sc->sis_miibus, 120650974Swpaul sis_ifmedia_upd, sis_ifmedia_sts)) { 1207150583Sjhb device_printf(dev, "MII without any PHY!\n"); 120850974Swpaul error = ENXIO; 120950974Swpaul goto fail; 121050974Swpaul } 121150974Swpaul 121250974Swpaul /* 121363090Sarchie * Call MI attach routine. 121450974Swpaul */ 1215106936Ssam ether_ifattach(ifp, eaddr); 121687390Sjhay 121787390Sjhay /* 121887390Sjhay * Tell the upper layer(s) we support long frames. 121987390Sjhay */ 122087390Sjhay ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1221106936Ssam ifp->if_capabilities |= IFCAP_VLAN_MTU; 1222150789Sglebius ifp->if_capenable = ifp->if_capabilities; 1223128138Sru#ifdef DEVICE_POLLING 1224128138Sru ifp->if_capabilities |= IFCAP_POLLING; 1225128138Sru#endif 1226128138Sru 1227113609Snjl /* Hook interrupt last to avoid having to lock softc */ 1228150526Sphk error = bus_setup_intr(dev, sc->sis_res[1], INTR_TYPE_NET | INTR_MPSAFE, 1229166901Spiso NULL, sis_intr, sc, &sc->sis_intrhand); 123050974Swpaul 1231112872Snjl if (error) { 1232150583Sjhb device_printf(dev, "couldn't set up irq\n"); 1233113609Snjl ether_ifdetach(ifp); 1234112872Snjl goto fail; 1235112872Snjl } 1236112872Snjl 123750974Swpaulfail: 1238112872Snjl if (error) 1239112872Snjl sis_detach(dev); 1240112872Snjl 124150974Swpaul return(error); 124250974Swpaul} 124350974Swpaul 1244113609Snjl/* 1245113609Snjl * Shutdown hardware and free up resources. This can be called any 1246113609Snjl * time after the mutex has been initialized. It is called in both 1247113609Snjl * the error case in attach and the normal detach case so it needs 1248113609Snjl * to be careful about only freeing resources that have actually been 1249113609Snjl * allocated. 1250113609Snjl */ 1251102334Salfredstatic int 1252139740Sphksis_detach(device_t dev) 125350974Swpaul{ 125450974Swpaul struct sis_softc *sc; 125550974Swpaul struct ifnet *ifp; 125650974Swpaul 125750974Swpaul sc = device_get_softc(dev); 1258112880Sjhb KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized")); 1259147256Sbrooks ifp = sc->sis_ifp; 126050974Swpaul 1261150789Sglebius#ifdef DEVICE_POLLING 1262150789Sglebius if (ifp->if_capenable & IFCAP_POLLING) 1263150789Sglebius ether_poll_deregister(ifp); 1264150789Sglebius#endif 1265150789Sglebius 1266118089Smux /* These should only be active if attach succeeded. */ 1267113812Simp if (device_is_attached(dev)) { 1268150583Sjhb SIS_LOCK(sc); 1269113609Snjl sis_reset(sc); 1270113609Snjl sis_stop(sc); 1271150583Sjhb SIS_UNLOCK(sc); 1272150583Sjhb callout_drain(&sc->sis_stat_ch); 1273112872Snjl ether_ifdetach(ifp); 1274150213Sru } 1275113609Snjl if (sc->sis_miibus) 1276112872Snjl device_delete_child(dev, sc->sis_miibus); 1277113609Snjl bus_generic_detach(dev); 127850974Swpaul 1279112872Snjl if (sc->sis_intrhand) 1280150526Sphk bus_teardown_intr(dev, sc->sis_res[1], sc->sis_intrhand); 1281150526Sphk bus_release_resources(dev, sis_res_spec, sc->sis_res); 128250974Swpaul 1283151297Sru if (ifp) 1284151297Sru if_free(ifp); 1285151297Sru 1286139690Sphk if (sc->sis_rx_tag) { 1287139690Sphk bus_dmamap_unload(sc->sis_rx_tag, 1288139690Sphk sc->sis_rx_dmamap); 1289139690Sphk bus_dmamem_free(sc->sis_rx_tag, 1290139690Sphk sc->sis_rx_list, sc->sis_rx_dmamap); 1291139690Sphk bus_dma_tag_destroy(sc->sis_rx_tag); 1292112872Snjl } 1293139690Sphk if (sc->sis_tx_tag) { 1294139690Sphk bus_dmamap_unload(sc->sis_tx_tag, 1295139690Sphk sc->sis_tx_dmamap); 1296139690Sphk bus_dmamem_free(sc->sis_tx_tag, 1297139690Sphk sc->sis_tx_list, sc->sis_tx_dmamap); 1298139690Sphk bus_dma_tag_destroy(sc->sis_tx_tag); 1299112872Snjl } 1300112872Snjl if (sc->sis_parent_tag) 1301112872Snjl bus_dma_tag_destroy(sc->sis_parent_tag); 1302112872Snjl if (sc->sis_tag) 1303112872Snjl bus_dma_tag_destroy(sc->sis_tag); 130450974Swpaul 130567087Swpaul mtx_destroy(&sc->sis_mtx); 130650974Swpaul 130750974Swpaul return(0); 130850974Swpaul} 130950974Swpaul 131050974Swpaul/* 1311139802Sphk * Initialize the TX and RX descriptors and allocate mbufs for them. Note that 1312139802Sphk * we arrange the descriptors in a closed ring, so that the last descriptor 1313139802Sphk * points back to the first. 131450974Swpaul */ 1315102334Salfredstatic int 1316139802Sphksis_ring_init(struct sis_softc *sc) 131750974Swpaul{ 1318139802Sphk int i, error; 1319139802Sphk struct sis_desc *dp; 132050974Swpaul 1321139802Sphk dp = &sc->sis_tx_list[0]; 1322139802Sphk for (i = 0; i < SIS_TX_LIST_CNT; i++, dp++) { 1323139802Sphk if (i == (SIS_TX_LIST_CNT - 1)) 1324139802Sphk dp->sis_nextdesc = &sc->sis_tx_list[0]; 1325139802Sphk else 1326139802Sphk dp->sis_nextdesc = dp + 1; 1327139802Sphk bus_dmamap_load(sc->sis_tx_tag, 1328139802Sphk sc->sis_tx_dmamap, 1329139802Sphk dp->sis_nextdesc, sizeof(struct sis_desc), 1330139802Sphk sis_dma_map_desc_next, dp, 0); 1331139802Sphk dp->sis_mbuf = NULL; 1332139802Sphk dp->sis_ptr = 0; 1333139802Sphk dp->sis_ctl = 0; 133450974Swpaul } 133550974Swpaul 1336139690Sphk sc->sis_tx_prod = sc->sis_tx_cons = sc->sis_tx_cnt = 0; 133750974Swpaul 1338139690Sphk bus_dmamap_sync(sc->sis_tx_tag, 1339148444Sjhb sc->sis_tx_dmamap, BUS_DMASYNC_PREWRITE); 134081713Swpaul 1341139802Sphk dp = &sc->sis_rx_list[0]; 1342139802Sphk for (i = 0; i < SIS_RX_LIST_CNT; i++, dp++) { 1343139802Sphk error = sis_newbuf(sc, dp, NULL); 1344139802Sphk if (error) 1345139802Sphk return(error); 1346139802Sphk if (i == (SIS_RX_LIST_CNT - 1)) 1347139802Sphk dp->sis_nextdesc = &sc->sis_rx_list[0]; 1348139802Sphk else 1349139802Sphk dp->sis_nextdesc = dp + 1; 1350139802Sphk bus_dmamap_load(sc->sis_rx_tag, 1351139802Sphk sc->sis_rx_dmamap, 1352139802Sphk dp->sis_nextdesc, sizeof(struct sis_desc), 1353139802Sphk sis_dma_map_desc_next, dp, 0); 135450974Swpaul } 135550974Swpaul 1356139690Sphk bus_dmamap_sync(sc->sis_rx_tag, 1357139690Sphk sc->sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 135881713Swpaul 1359139691Sphk sc->sis_rx_pdsc = &sc->sis_rx_list[0]; 136050974Swpaul 136150974Swpaul return(0); 136250974Swpaul} 136350974Swpaul 136450974Swpaul/* 136550974Swpaul * Initialize an RX descriptor and attach an MBUF cluster. 136650974Swpaul */ 1367102334Salfredstatic int 1368139740Sphksis_newbuf(struct sis_softc *sc, struct sis_desc *c, struct mbuf *m) 136950974Swpaul{ 137050974Swpaul 137181713Swpaul if (c == NULL) 137281713Swpaul return(EINVAL); 137381713Swpaul 137450974Swpaul if (m == NULL) { 1375111119Simp m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1376101340Sluigi if (m == NULL) 137750974Swpaul return(ENOBUFS); 1378101340Sluigi } else 1379101340Sluigi m->m_data = m->m_ext.ext_buf; 138050974Swpaul 1381101340Sluigi c->sis_mbuf = m; 138250974Swpaul c->sis_ctl = SIS_RXLEN; 138350974Swpaul 138481713Swpaul bus_dmamap_create(sc->sis_tag, 0, &c->sis_map); 138581713Swpaul bus_dmamap_load(sc->sis_tag, c->sis_map, 1386101464Sluigi mtod(m, void *), MCLBYTES, 138781713Swpaul sis_dma_map_desc_ptr, c, 0); 1388139944Ssam bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREREAD); 138981713Swpaul 139050974Swpaul return(0); 139150974Swpaul} 139250974Swpaul 139350974Swpaul/* 139450974Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 139550974Swpaul * the higher level protocols. 139650974Swpaul */ 1397102334Salfredstatic void 1398139740Sphksis_rxeof(struct sis_softc *sc) 139950974Swpaul{ 1400163773Smarius struct mbuf *m, *m0; 1401163773Smarius struct ifnet *ifp; 140250974Swpaul struct sis_desc *cur_rx; 1403139691Sphk int total_len = 0; 140450974Swpaul u_int32_t rxstat; 140550974Swpaul 1406122689Ssam SIS_LOCK_ASSERT(sc); 1407122689Ssam 1408147256Sbrooks ifp = sc->sis_ifp; 140950974Swpaul 1410139691Sphk for(cur_rx = sc->sis_rx_pdsc; SIS_OWNDESC(cur_rx); 1411139691Sphk cur_rx = cur_rx->sis_nextdesc) { 141250974Swpaul 141387902Sluigi#ifdef DEVICE_POLLING 1414150789Sglebius if (ifp->if_capenable & IFCAP_POLLING) { 141587902Sluigi if (sc->rxcycles <= 0) 141687902Sluigi break; 141787902Sluigi sc->rxcycles--; 141887902Sluigi } 1419150789Sglebius#endif 142050974Swpaul rxstat = cur_rx->sis_rxstat; 142181713Swpaul bus_dmamap_sync(sc->sis_tag, 142281713Swpaul cur_rx->sis_map, BUS_DMASYNC_POSTWRITE); 142381713Swpaul bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map); 142481713Swpaul bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map); 142550974Swpaul m = cur_rx->sis_mbuf; 142650974Swpaul cur_rx->sis_mbuf = NULL; 142750974Swpaul total_len = SIS_RXBYTES(cur_rx); 142850974Swpaul 142950974Swpaul /* 143050974Swpaul * If an error occurs, update stats, clear the 143150974Swpaul * status word and leave the mbuf cluster in place: 143250974Swpaul * it should simply get re-used next time this descriptor 143350974Swpaul * comes up in the ring. 143450974Swpaul */ 143550974Swpaul if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 143650974Swpaul ifp->if_ierrors++; 143750974Swpaul if (rxstat & SIS_RXSTAT_COLL) 143850974Swpaul ifp->if_collisions++; 143950974Swpaul sis_newbuf(sc, cur_rx, m); 144050974Swpaul continue; 144150974Swpaul } 144250974Swpaul 144350974Swpaul /* No errors; receive the packet. */ 1444163773Smarius#ifdef __NO_STRICT_ALIGNMENT 144587059Sluigi /* 1446163773Smarius * On architectures without alignment problems we try to 144787059Sluigi * allocate a new buffer for the receive ring, and pass up 144887059Sluigi * the one where the packet is already, saving the expensive 144987059Sluigi * copy done in m_devget(). 145087059Sluigi * If we are on an architecture with alignment problems, or 145187059Sluigi * if the allocation fails, then use m_devget and leave the 145287059Sluigi * existing buffer in the receive ring. 145387059Sluigi */ 1454101464Sluigi if (sis_newbuf(sc, cur_rx, NULL) == 0) 145587059Sluigi m->m_pkthdr.len = m->m_len = total_len; 1456101464Sluigi else 145787059Sluigi#endif 145887059Sluigi { 145987059Sluigi m0 = m_devget(mtod(m, char *), total_len, 146087059Sluigi ETHER_ALIGN, ifp, NULL); 146187059Sluigi sis_newbuf(sc, cur_rx, m); 146287059Sluigi if (m0 == NULL) { 146387059Sluigi ifp->if_ierrors++; 146487059Sluigi continue; 146587059Sluigi } 146687059Sluigi m = m0; 146750974Swpaul } 146850974Swpaul 146950974Swpaul ifp->if_ipackets++; 1470106936Ssam m->m_pkthdr.rcvif = ifp; 1471106936Ssam 1472122689Ssam SIS_UNLOCK(sc); 1473106936Ssam (*ifp->if_input)(ifp, m); 1474122689Ssam SIS_LOCK(sc); 147550974Swpaul } 147650974Swpaul 1477139691Sphk sc->sis_rx_pdsc = cur_rx; 147850974Swpaul} 147950974Swpaul 1480105219Sphkstatic void 1481139715Sphksis_rxeoc(struct sis_softc *sc) 148250974Swpaul{ 1483139715Sphk 1484139715Sphk SIS_LOCK_ASSERT(sc); 148550974Swpaul sis_rxeof(sc); 1486139715Sphk sis_initl(sc); 148750974Swpaul} 148850974Swpaul 148950974Swpaul/* 149050974Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 149150974Swpaul * the list buffers. 149250974Swpaul */ 149350974Swpaul 1494102334Salfredstatic void 1495139740Sphksis_txeof(struct sis_softc *sc) 149650974Swpaul{ 149750974Swpaul struct ifnet *ifp; 149850974Swpaul u_int32_t idx; 149950974Swpaul 1500139715Sphk SIS_LOCK_ASSERT(sc); 1501147256Sbrooks ifp = sc->sis_ifp; 150250974Swpaul 150350974Swpaul /* 150450974Swpaul * Go through our tx list and free mbufs for those 150550974Swpaul * frames that have been transmitted. 150650974Swpaul */ 1507139690Sphk for (idx = sc->sis_tx_cons; sc->sis_tx_cnt > 0; 1508139690Sphk sc->sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) { 1509139690Sphk struct sis_desc *cur_tx = &sc->sis_tx_list[idx]; 151050974Swpaul 151150974Swpaul if (SIS_OWNDESC(cur_tx)) 151250974Swpaul break; 151350974Swpaul 151499163Sluigi if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) 151550974Swpaul continue; 151650974Swpaul 151750974Swpaul if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 151850974Swpaul ifp->if_oerrors++; 151950974Swpaul if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 152050974Swpaul ifp->if_collisions++; 152150974Swpaul if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 152250974Swpaul ifp->if_collisions++; 152350974Swpaul } 152450974Swpaul 152550974Swpaul ifp->if_collisions += 152650974Swpaul (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 152750974Swpaul 152850974Swpaul ifp->if_opackets++; 152950974Swpaul if (cur_tx->sis_mbuf != NULL) { 153050974Swpaul m_freem(cur_tx->sis_mbuf); 153150974Swpaul cur_tx->sis_mbuf = NULL; 153281713Swpaul bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map); 153381713Swpaul bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map); 153450974Swpaul } 153599163Sluigi } 153650974Swpaul 1537139690Sphk if (idx != sc->sis_tx_cons) { 153899163Sluigi /* we freed up some buffers */ 1539139690Sphk sc->sis_tx_cons = idx; 1540148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 154150974Swpaul } 154250974Swpaul 1543139690Sphk ifp->if_timer = (sc->sis_tx_cnt == 0) ? 0 : 5; 154450974Swpaul 154550974Swpaul return; 154650974Swpaul} 154750974Swpaul 1548102334Salfredstatic void 1549139740Sphksis_tick(void *xsc) 155050974Swpaul{ 155150974Swpaul struct sis_softc *sc; 155250974Swpaul struct mii_data *mii; 155364963Swpaul struct ifnet *ifp; 155450974Swpaul 155550974Swpaul sc = xsc; 1556150583Sjhb SIS_LOCK_ASSERT(sc); 1557117858Scognet sc->in_tick = 1; 1558147256Sbrooks ifp = sc->sis_ifp; 155964963Swpaul 156050974Swpaul mii = device_get_softc(sc->sis_miibus); 156150974Swpaul mii_tick(mii); 156264963Swpaul 156384147Sjlemon if (!sc->sis_link && mii->mii_media_status & IFM_ACTIVE && 156484147Sjlemon IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 156584147Sjlemon sc->sis_link++; 1566131455Smlaier if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1567139714Sphk sis_startl(ifp); 156864963Swpaul } 156964963Swpaul 1570119785Ssam callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 1571117858Scognet sc->in_tick = 0; 157250974Swpaul} 157350974Swpaul 157487902Sluigi#ifdef DEVICE_POLLING 157587902Sluigistatic poll_handler_t sis_poll; 157687902Sluigi 157787902Sluigistatic void 157887902Sluigisis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 157987902Sluigi{ 158087973Speter struct sis_softc *sc = ifp->if_softc; 158187973Speter 158287902Sluigi SIS_LOCK(sc); 1583150789Sglebius if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1584150789Sglebius SIS_UNLOCK(sc); 1585150789Sglebius return; 1586128138Sru } 158787902Sluigi 158887902Sluigi /* 158987902Sluigi * On the sis, reading the status register also clears it. 159087902Sluigi * So before returning to intr mode we must make sure that all 159187902Sluigi * possible pending sources of interrupts have been served. 159287902Sluigi * In practice this means run to completion the *eof routines, 159387902Sluigi * and then call the interrupt routine 159487902Sluigi */ 159587902Sluigi sc->rxcycles = count; 159687902Sluigi sis_rxeof(sc); 159787902Sluigi sis_txeof(sc); 1598131455Smlaier if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1599139714Sphk sis_startl(ifp); 160087902Sluigi 160187902Sluigi if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 160287902Sluigi u_int32_t status; 160387902Sluigi 160487902Sluigi /* Reading the ISR register clears all interrupts. */ 160587902Sluigi status = CSR_READ_4(sc, SIS_ISR); 160687902Sluigi 160787902Sluigi if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 160887902Sluigi sis_rxeoc(sc); 160987902Sluigi 161087902Sluigi if (status & (SIS_ISR_RX_IDLE)) 161187902Sluigi SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 161287902Sluigi 161387902Sluigi if (status & SIS_ISR_SYSERR) { 161487902Sluigi sis_reset(sc); 1615139715Sphk sis_initl(sc); 161687902Sluigi } 161787902Sluigi } 1618150789Sglebius 161987902Sluigi SIS_UNLOCK(sc); 162087902Sluigi} 162187902Sluigi#endif /* DEVICE_POLLING */ 162287902Sluigi 1623102334Salfredstatic void 1624139740Sphksis_intr(void *arg) 162550974Swpaul{ 162650974Swpaul struct sis_softc *sc; 162750974Swpaul struct ifnet *ifp; 162850974Swpaul u_int32_t status; 162950974Swpaul 163050974Swpaul sc = arg; 1631147256Sbrooks ifp = sc->sis_ifp; 163250974Swpaul 1633139809Sphk if (sc->sis_stopped) /* Most likely shared interrupt */ 1634139809Sphk return; 1635139809Sphk 163686984Sluigi SIS_LOCK(sc); 163787902Sluigi#ifdef DEVICE_POLLING 1638150789Sglebius if (ifp->if_capenable & IFCAP_POLLING) { 1639150789Sglebius SIS_UNLOCK(sc); 1640150789Sglebius return; 164187902Sluigi } 1642150789Sglebius#endif 164387902Sluigi 164450974Swpaul /* Disable interrupts. */ 164550974Swpaul CSR_WRITE_4(sc, SIS_IER, 0); 164650974Swpaul 164750974Swpaul for (;;) { 1648139717Sphk SIS_LOCK_ASSERT(sc); 164950974Swpaul /* Reading the ISR register clears all interrupts. */ 165050974Swpaul status = CSR_READ_4(sc, SIS_ISR); 165150974Swpaul 165250974Swpaul if ((status & SIS_INTRS) == 0) 165350974Swpaul break; 165450974Swpaul 165586984Sluigi if (status & 165686984Sluigi (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | 165786984Sluigi SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) ) 165850974Swpaul sis_txeof(sc); 165950974Swpaul 166086984Sluigi if (status & (SIS_ISR_RX_DESC_OK|SIS_ISR_RX_OK|SIS_ISR_RX_IDLE)) 166150974Swpaul sis_rxeof(sc); 166250974Swpaul 166386984Sluigi if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW)) 166450974Swpaul sis_rxeoc(sc); 166550974Swpaul 166686984Sluigi if (status & (SIS_ISR_RX_IDLE)) 166786984Sluigi SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 166886984Sluigi 166950974Swpaul if (status & SIS_ISR_SYSERR) { 167050974Swpaul sis_reset(sc); 1671139715Sphk sis_initl(sc); 167250974Swpaul } 167350974Swpaul } 167450974Swpaul 167550974Swpaul /* Re-enable interrupts. */ 167650974Swpaul CSR_WRITE_4(sc, SIS_IER, 1); 167750974Swpaul 1678131455Smlaier if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1679139714Sphk sis_startl(ifp); 1680139809Sphk 168167087Swpaul SIS_UNLOCK(sc); 168250974Swpaul} 168350974Swpaul 168450974Swpaul/* 168550974Swpaul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 168650974Swpaul * pointers to the fragment pointers. 168750974Swpaul */ 1688102334Salfredstatic int 1689139740Sphksis_encap(struct sis_softc *sc, struct mbuf **m_head, uint32_t *txidx) 169050974Swpaul{ 169150974Swpaul struct sis_desc *f = NULL; 169250974Swpaul struct mbuf *m; 1693112808Ssilby int frag, cur, cnt = 0, chainlen = 0; 169450974Swpaul 169550974Swpaul /* 1696112808Ssilby * If there's no way we can send any packets, return now. 1697112808Ssilby */ 1698139690Sphk if (SIS_TX_LIST_CNT - sc->sis_tx_cnt < 2) 1699112808Ssilby return (ENOBUFS); 1700112808Ssilby 1701112808Ssilby /* 1702112808Ssilby * Count the number of frags in this chain to see if 1703112808Ssilby * we need to m_defrag. Since the descriptor list is shared 1704112808Ssilby * by all packets, we'll m_defrag long chains so that they 1705112808Ssilby * do not use up the entire list, even if they would fit. 1706112808Ssilby */ 1707112808Ssilby 1708121262Ssilby for (m = *m_head; m != NULL; m = m->m_next) 1709112808Ssilby chainlen++; 1710112808Ssilby 1711112808Ssilby if ((chainlen > SIS_TX_LIST_CNT / 4) || 1712139690Sphk ((SIS_TX_LIST_CNT - (chainlen + sc->sis_tx_cnt)) < 2)) { 1713121262Ssilby m = m_defrag(*m_head, M_DONTWAIT); 1714112808Ssilby if (m == NULL) 1715112808Ssilby return (ENOBUFS); 1716121262Ssilby *m_head = m; 1717112808Ssilby } 1718112808Ssilby 1719112808Ssilby /* 172050974Swpaul * Start packing the mbufs in this chain into 172150974Swpaul * the fragment pointers. Stop when we run out 172250974Swpaul * of fragments or hit the end of the mbuf chain. 172350974Swpaul */ 172450974Swpaul cur = frag = *txidx; 172550974Swpaul 1726121262Ssilby for (m = *m_head; m != NULL; m = m->m_next) { 172750974Swpaul if (m->m_len != 0) { 172851042Swpaul if ((SIS_TX_LIST_CNT - 1729139690Sphk (sc->sis_tx_cnt + cnt)) < 2) 173050974Swpaul return(ENOBUFS); 1731139690Sphk f = &sc->sis_tx_list[frag]; 173250974Swpaul f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; 173381713Swpaul bus_dmamap_create(sc->sis_tag, 0, &f->sis_map); 173481713Swpaul bus_dmamap_load(sc->sis_tag, f->sis_map, 173581713Swpaul mtod(m, void *), m->m_len, 173681713Swpaul sis_dma_map_desc_ptr, f, 0); 173781713Swpaul bus_dmamap_sync(sc->sis_tag, 173881713Swpaul f->sis_map, BUS_DMASYNC_PREREAD); 173950974Swpaul if (cnt != 0) 174050974Swpaul f->sis_ctl |= SIS_CMDSTS_OWN; 174150974Swpaul cur = frag; 174250974Swpaul SIS_INC(frag, SIS_TX_LIST_CNT); 174350974Swpaul cnt++; 174450974Swpaul } 174550974Swpaul } 174650974Swpaul 174750974Swpaul if (m != NULL) 174850974Swpaul return(ENOBUFS); 174950974Swpaul 1750139690Sphk sc->sis_tx_list[cur].sis_mbuf = *m_head; 1751139690Sphk sc->sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1752139690Sphk sc->sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1753139690Sphk sc->sis_tx_cnt += cnt; 175450974Swpaul *txidx = frag; 175550974Swpaul 175650974Swpaul return(0); 175750974Swpaul} 175850974Swpaul 175950974Swpaul/* 176050974Swpaul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 176150974Swpaul * to the mbuf data regions directly in the transmit lists. We also save a 176250974Swpaul * copy of the pointers since the transmit list fragment pointers are 176350974Swpaul * physical addresses. 176450974Swpaul */ 176550974Swpaul 1766102334Salfredstatic void 1767139717Sphksis_start(struct ifnet *ifp) 176850974Swpaul{ 176950974Swpaul struct sis_softc *sc; 1770139714Sphk 1771139714Sphk sc = ifp->if_softc; 1772139714Sphk SIS_LOCK(sc); 1773139714Sphk sis_startl(ifp); 1774139714Sphk SIS_UNLOCK(sc); 1775139714Sphk} 1776139714Sphk 1777139714Sphkstatic void 1778139714Sphksis_startl(struct ifnet *ifp) 1779139714Sphk{ 1780139714Sphk struct sis_softc *sc; 178150974Swpaul struct mbuf *m_head = NULL; 1782136269Smlaier u_int32_t idx, queued = 0; 178350974Swpaul 178450974Swpaul sc = ifp->if_softc; 178550974Swpaul 1786139714Sphk SIS_LOCK_ASSERT(sc); 1787139714Sphk 1788139714Sphk if (!sc->sis_link) 178964963Swpaul return; 179064963Swpaul 1791139690Sphk idx = sc->sis_tx_prod; 179250974Swpaul 1793148887Srwatson if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 179450974Swpaul return; 179550974Swpaul 1796139690Sphk while(sc->sis_tx_list[idx].sis_mbuf == NULL) { 1797131455Smlaier IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 179850974Swpaul if (m_head == NULL) 179950974Swpaul break; 180050974Swpaul 1801121262Ssilby if (sis_encap(sc, &m_head, &idx)) { 1802131455Smlaier IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1803148887Srwatson ifp->if_drv_flags |= IFF_DRV_OACTIVE; 180450974Swpaul break; 180550974Swpaul } 180650974Swpaul 1807136269Smlaier queued++; 1808136269Smlaier 180950974Swpaul /* 181050974Swpaul * If there's a BPF listener, bounce a copy of this frame 181150974Swpaul * to him. 181250974Swpaul */ 1813106936Ssam BPF_MTAP(ifp, m_head); 181451583Swpaul 181550974Swpaul } 181650974Swpaul 1817136269Smlaier if (queued) { 1818136269Smlaier /* Transmit */ 1819139690Sphk sc->sis_tx_prod = idx; 1820136269Smlaier SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 182150974Swpaul 1822136269Smlaier /* 1823136269Smlaier * Set a timeout in case the chip goes out to lunch. 1824136269Smlaier */ 1825136269Smlaier ifp->if_timer = 5; 1826136269Smlaier } 182750974Swpaul} 182850974Swpaul 1829102334Salfredstatic void 1830139715Sphksis_init(void *xsc) 183150974Swpaul{ 183250974Swpaul struct sis_softc *sc = xsc; 1833139715Sphk 1834139715Sphk SIS_LOCK(sc); 1835139717Sphk sis_initl(sc); 1836139715Sphk SIS_UNLOCK(sc); 1837139715Sphk} 1838139715Sphk 1839139715Sphkstatic void 1840139717Sphksis_initl(struct sis_softc *sc) 1841139715Sphk{ 1842147256Sbrooks struct ifnet *ifp = sc->sis_ifp; 184350974Swpaul struct mii_data *mii; 184450974Swpaul 1845139715Sphk SIS_LOCK_ASSERT(sc); 184650974Swpaul 184750974Swpaul /* 184850974Swpaul * Cancel pending I/O and free all RX/TX buffers. 184950974Swpaul */ 185050974Swpaul sis_stop(sc); 1851123833Sphk sc->sis_stopped = 0; 185250974Swpaul 1853119712Sphk#ifdef notyet 1854119712Sphk if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) { 1855119712Sphk /* 1856119712Sphk * Configure 400usec of interrupt holdoff. This is based 1857119712Sphk * on emperical tests on a Soekris 4801. 1858119712Sphk */ 1859119712Sphk CSR_WRITE_4(sc, NS_IHR, 0x100 | 4); 1860119712Sphk } 1861119712Sphk#endif 1862119712Sphk 186350974Swpaul mii = device_get_softc(sc->sis_miibus); 186450974Swpaul 186550974Swpaul /* Set MAC address */ 186662672Swpaul if (sc->sis_type == SIS_TYPE_83815) { 186762672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 186862672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1869152315Sru ((u_int16_t *)IF_LLADDR(sc->sis_ifp))[0]); 187062672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 187162672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1872152315Sru ((u_int16_t *)IF_LLADDR(sc->sis_ifp))[1]); 187362672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 187462672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1875152315Sru ((u_int16_t *)IF_LLADDR(sc->sis_ifp))[2]); 187662672Swpaul } else { 187762672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 187862672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1879152315Sru ((u_int16_t *)IF_LLADDR(sc->sis_ifp))[0]); 188062672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 188162672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1882152315Sru ((u_int16_t *)IF_LLADDR(sc->sis_ifp))[1]); 188362672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 188462672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1885152315Sru ((u_int16_t *)IF_LLADDR(sc->sis_ifp))[2]); 188662672Swpaul } 188750974Swpaul 1888139802Sphk /* Init circular TX/RX lists. */ 1889139802Sphk if (sis_ring_init(sc) != 0) { 1890162315Sglebius device_printf(sc->sis_dev, 1891150583Sjhb "initialization failed: no memory for rx buffers\n"); 189250974Swpaul sis_stop(sc); 189350974Swpaul return; 189450974Swpaul } 189550974Swpaul 189650974Swpaul /* 1897139806Sphk * Short Cable Receive Errors (MP21.E) 1898139806Sphk * also: Page 78 of the DP83815 data sheet (september 2002 version) 1899123491Sphk * recommends the following register settings "for optimum 1900123491Sphk * performance." for rev 15C. The driver from NS also sets 1901123491Sphk * the PHY_CR register for later versions. 1902123491Sphk */ 1903139806Sphk if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr <= NS_SRR_15D) { 1904123491Sphk CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 1905123491Sphk CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 1906123491Sphk if (sc->sis_srr == NS_SRR_15C) { 1907123491Sphk /* set val for c2 */ 1908123491Sphk CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 1909123491Sphk /* load/kill c2 */ 1910123491Sphk CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 1911123491Sphk /* rais SD off, from 4 to c */ 1912123491Sphk CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 1913123491Sphk } 1914123491Sphk CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 1915123491Sphk } 1916123491Sphk 1917123491Sphk 1918123491Sphk /* 191962672Swpaul * For the NatSemi chip, we have to explicitly enable the 192062672Swpaul * reception of ARP frames, as well as turn on the 'perfect 192162672Swpaul * match' filter where we store the station address, otherwise 192262672Swpaul * we won't receive unicasts meant for this host. 192362672Swpaul */ 192462672Swpaul if (sc->sis_type == SIS_TYPE_83815) { 192562672Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 192662672Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 192762672Swpaul } 192862672Swpaul 192950974Swpaul /* If we want promiscuous mode, set the allframes bit. */ 193050974Swpaul if (ifp->if_flags & IFF_PROMISC) { 193150974Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 193250974Swpaul } else { 193350974Swpaul SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 193450974Swpaul } 193550974Swpaul 193650974Swpaul /* 193750974Swpaul * Set the capture broadcast bit to capture broadcast frames. 193850974Swpaul */ 193950974Swpaul if (ifp->if_flags & IFF_BROADCAST) { 194050974Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 194150974Swpaul } else { 194250974Swpaul SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 194350974Swpaul } 194450974Swpaul 194550974Swpaul /* 194650974Swpaul * Load the multicast filter. 194750974Swpaul */ 194862672Swpaul if (sc->sis_type == SIS_TYPE_83815) 194962672Swpaul sis_setmulti_ns(sc); 195062672Swpaul else 195162672Swpaul sis_setmulti_sis(sc); 195250974Swpaul 195350974Swpaul /* Turn the receive filter on */ 195450974Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 195550974Swpaul 195650974Swpaul /* 195750974Swpaul * Load the address of the RX and TX lists. 195850974Swpaul */ 1959139690Sphk CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_rx_paddr); 1960139690Sphk CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_tx_paddr); 196150974Swpaul 1962109059Smbr /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of 1963109059Smbr * the PCI bus. When this bit is set, the Max DMA Burst Size 1964109059Smbr * for TX/RX DMA should be no larger than 16 double words. 1965109059Smbr */ 1966109059Smbr if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) { 1967109059Smbr CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); 1968109059Smbr } else { 1969109059Smbr CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); 1970109059Smbr } 197164963Swpaul 197287390Sjhay /* Accept Long Packets for VLAN support */ 197387390Sjhay SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 197487390Sjhay 197550974Swpaul /* Set TX configuration */ 197664963Swpaul if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 197764963Swpaul CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 197864963Swpaul } else { 197964963Swpaul CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 198064963Swpaul } 198150974Swpaul 198264963Swpaul /* Set full/half duplex mode. */ 198364963Swpaul if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 198464963Swpaul SIS_SETBIT(sc, SIS_TX_CFG, 198564963Swpaul (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 198664963Swpaul SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 198764963Swpaul } else { 198864963Swpaul SIS_CLRBIT(sc, SIS_TX_CFG, 198964963Swpaul (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 199064963Swpaul SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 199164963Swpaul } 199264963Swpaul 1993139807Sphk if (sc->sis_type == SIS_TYPE_83816) { 1994139807Sphk /* 1995139807Sphk * MPII03.D: Half Duplex Excessive Collisions. 1996139807Sphk * Also page 49 in 83816 manual 1997139807Sphk */ 1998139807Sphk SIS_SETBIT(sc, SIS_TX_CFG, SIS_TXCFG_MPII03D); 1999139807Sphk } 2000139807Sphk 2001139808Sphk if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr < NS_SRR_16A && 2002119130Ssam IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 2003119130Ssam uint32_t reg; 2004119130Ssam 2005119130Ssam /* 2006139806Sphk * Short Cable Receive Errors (MP21.E) 2007119130Ssam */ 2008119130Ssam CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 2009139806Sphk reg = CSR_READ_4(sc, NS_PHY_DSPCFG) & 0xfff; 2010139806Sphk CSR_WRITE_4(sc, NS_PHY_DSPCFG, reg | 0x1000); 2011139806Sphk DELAY(100000); 2012139806Sphk reg = CSR_READ_4(sc, NS_PHY_TDATA) & 0xff; 2013139806Sphk if ((reg & 0x0080) == 0 || (reg > 0xd8 && reg <= 0xff)) { 2014162315Sglebius device_printf(sc->sis_dev, 2015139806Sphk "Applying short cable fix (reg=%x)\n", reg); 2016119130Ssam CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8); 2017139806Sphk reg = CSR_READ_4(sc, NS_PHY_DSPCFG); 2018139806Sphk SIS_SETBIT(sc, NS_PHY_DSPCFG, reg | 0x20); 2019119130Ssam } 2020119130Ssam CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 2021119130Ssam } 2022119130Ssam 202350974Swpaul /* 202450974Swpaul * Enable interrupts. 202550974Swpaul */ 202650974Swpaul CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 202787902Sluigi#ifdef DEVICE_POLLING 202887902Sluigi /* 202987902Sluigi * ... only enable interrupts if we are not polling, make sure 203087902Sluigi * they are off otherwise. 203187902Sluigi */ 2032150789Sglebius if (ifp->if_capenable & IFCAP_POLLING) 203387902Sluigi CSR_WRITE_4(sc, SIS_IER, 0); 203487902Sluigi else 2035150789Sglebius#endif 203650974Swpaul CSR_WRITE_4(sc, SIS_IER, 1); 203750974Swpaul 203850974Swpaul /* Enable receiver and transmitter. */ 203950974Swpaul SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 204050974Swpaul SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 204150974Swpaul 204264963Swpaul#ifdef notdef 204350974Swpaul mii_mediachg(mii); 204464963Swpaul#endif 204550974Swpaul 2046148887Srwatson ifp->if_drv_flags |= IFF_DRV_RUNNING; 2047148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 204850974Swpaul 2049117858Scognet if (!sc->in_tick) 2050119785Ssam callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 205150974Swpaul} 205250974Swpaul 205350974Swpaul/* 205450974Swpaul * Set media options. 205550974Swpaul */ 2056102334Salfredstatic int 2057139740Sphksis_ifmedia_upd(struct ifnet *ifp) 205850974Swpaul{ 205950974Swpaul struct sis_softc *sc; 206064963Swpaul struct mii_data *mii; 206150974Swpaul 206250974Swpaul sc = ifp->if_softc; 206350974Swpaul 2064150583Sjhb SIS_LOCK(sc); 206564963Swpaul mii = device_get_softc(sc->sis_miibus); 206664963Swpaul sc->sis_link = 0; 206764963Swpaul if (mii->mii_instance) { 206864963Swpaul struct mii_softc *miisc; 206972012Sphk LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 207064963Swpaul mii_phy_reset(miisc); 207164963Swpaul } 207264963Swpaul mii_mediachg(mii); 2073150583Sjhb SIS_UNLOCK(sc); 207450974Swpaul 207550974Swpaul return(0); 207650974Swpaul} 207750974Swpaul 207850974Swpaul/* 207950974Swpaul * Report current media status. 208050974Swpaul */ 2081102334Salfredstatic void 2082139740Sphksis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 208350974Swpaul{ 208450974Swpaul struct sis_softc *sc; 208550974Swpaul struct mii_data *mii; 208650974Swpaul 208750974Swpaul sc = ifp->if_softc; 208850974Swpaul 2089150583Sjhb SIS_LOCK(sc); 209050974Swpaul mii = device_get_softc(sc->sis_miibus); 209150974Swpaul mii_pollstat(mii); 2092150583Sjhb SIS_UNLOCK(sc); 209350974Swpaul ifmr->ifm_active = mii->mii_media_active; 209450974Swpaul ifmr->ifm_status = mii->mii_media_status; 209550974Swpaul} 209650974Swpaul 2097102334Salfredstatic int 2098139740Sphksis_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 209950974Swpaul{ 210050974Swpaul struct sis_softc *sc = ifp->if_softc; 210150974Swpaul struct ifreq *ifr = (struct ifreq *) data; 210250974Swpaul struct mii_data *mii; 210367087Swpaul int error = 0; 210450974Swpaul 210550974Swpaul switch(command) { 210650974Swpaul case SIOCSIFFLAGS: 2107150583Sjhb SIS_LOCK(sc); 210850974Swpaul if (ifp->if_flags & IFF_UP) { 2109150583Sjhb sis_initl(sc); 2110148887Srwatson } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2111139741Sphk sis_stop(sc); 211250974Swpaul } 2113150583Sjhb SIS_UNLOCK(sc); 211450974Swpaul error = 0; 211550974Swpaul break; 211650974Swpaul case SIOCADDMULTI: 211750974Swpaul case SIOCDELMULTI: 211881713Swpaul SIS_LOCK(sc); 211962672Swpaul if (sc->sis_type == SIS_TYPE_83815) 212062672Swpaul sis_setmulti_ns(sc); 212162672Swpaul else 212262672Swpaul sis_setmulti_sis(sc); 212381713Swpaul SIS_UNLOCK(sc); 212450974Swpaul error = 0; 212550974Swpaul break; 212650974Swpaul case SIOCGIFMEDIA: 212750974Swpaul case SIOCSIFMEDIA: 212850974Swpaul mii = device_get_softc(sc->sis_miibus); 212950974Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 213050974Swpaul break; 2131128138Sru case SIOCSIFCAP: 2132150789Sglebius /* ok, disable interrupts */ 2133150789Sglebius#ifdef DEVICE_POLLING 2134150789Sglebius if (ifr->ifr_reqcap & IFCAP_POLLING && 2135150789Sglebius !(ifp->if_capenable & IFCAP_POLLING)) { 2136150789Sglebius error = ether_poll_register(sis_poll, ifp); 2137150789Sglebius if (error) 2138150789Sglebius return(error); 2139150789Sglebius SIS_LOCK(sc); 2140150789Sglebius /* Disable interrupts */ 2141150789Sglebius CSR_WRITE_4(sc, SIS_IER, 0); 2142150789Sglebius ifp->if_capenable |= IFCAP_POLLING; 2143150789Sglebius SIS_UNLOCK(sc); 2144150789Sglebius return (error); 2145150789Sglebius 2146150789Sglebius } 2147150789Sglebius if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 2148150789Sglebius ifp->if_capenable & IFCAP_POLLING) { 2149150789Sglebius error = ether_poll_deregister(ifp); 2150150789Sglebius /* Enable interrupts. */ 2151150789Sglebius SIS_LOCK(sc); 2152150789Sglebius CSR_WRITE_4(sc, SIS_IER, 1); 2153150789Sglebius ifp->if_capenable &= ~IFCAP_POLLING; 2154150789Sglebius SIS_UNLOCK(sc); 2155150789Sglebius return (error); 2156150789Sglebius } 2157150789Sglebius#endif /* DEVICE_POLLING */ 2158128138Sru break; 215950974Swpaul default: 2160106936Ssam error = ether_ioctl(ifp, command, data); 216150974Swpaul break; 216250974Swpaul } 216350974Swpaul 216450974Swpaul return(error); 216550974Swpaul} 216650974Swpaul 2167102334Salfredstatic void 2168139740Sphksis_watchdog(struct ifnet *ifp) 216950974Swpaul{ 2170139797Sphk struct sis_softc *sc; 217150974Swpaul 217250974Swpaul sc = ifp->if_softc; 217350974Swpaul 217467087Swpaul SIS_LOCK(sc); 2175139797Sphk if (sc->sis_stopped) { 2176139797Sphk SIS_UNLOCK(sc); 2177139797Sphk return; 2178139797Sphk } 217967087Swpaul 218050974Swpaul ifp->if_oerrors++; 2181150583Sjhb if_printf(ifp, "watchdog timeout\n"); 218250974Swpaul 218350974Swpaul sis_stop(sc); 218450974Swpaul sis_reset(sc); 2185139715Sphk sis_initl(sc); 218650974Swpaul 2187131455Smlaier if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2188139714Sphk sis_startl(ifp); 218950974Swpaul 219067087Swpaul SIS_UNLOCK(sc); 219150974Swpaul} 219250974Swpaul 219350974Swpaul/* 219450974Swpaul * Stop the adapter and free any mbufs allocated to the 219550974Swpaul * RX and TX lists. 219650974Swpaul */ 2197102334Salfredstatic void 2198139740Sphksis_stop(struct sis_softc *sc) 219950974Swpaul{ 2200139805Sphk int i; 2201139805Sphk struct ifnet *ifp; 2202139805Sphk struct sis_desc *dp; 220350974Swpaul 2204123833Sphk if (sc->sis_stopped) 2205123833Sphk return; 2206139717Sphk SIS_LOCK_ASSERT(sc); 2207147256Sbrooks ifp = sc->sis_ifp; 220850974Swpaul ifp->if_timer = 0; 220950974Swpaul 2210119785Ssam callout_stop(&sc->sis_stat_ch); 221187472Speter 2212148887Srwatson ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 221350974Swpaul CSR_WRITE_4(sc, SIS_IER, 0); 221450974Swpaul CSR_WRITE_4(sc, SIS_IMR, 0); 2215139798Sphk CSR_READ_4(sc, SIS_ISR); /* clear any interrupts already pending */ 221650974Swpaul SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 221750974Swpaul DELAY(1000); 221850974Swpaul CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 221950974Swpaul CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 222050974Swpaul 222164963Swpaul sc->sis_link = 0; 222264963Swpaul 222350974Swpaul /* 222450974Swpaul * Free data in the RX lists. 222550974Swpaul */ 2226139805Sphk dp = &sc->sis_rx_list[0]; 2227139805Sphk for (i = 0; i < SIS_RX_LIST_CNT; i++, dp++) { 2228139805Sphk if (dp->sis_mbuf == NULL) 2229139805Sphk continue; 2230139805Sphk bus_dmamap_unload(sc->sis_tag, dp->sis_map); 2231139805Sphk bus_dmamap_destroy(sc->sis_tag, dp->sis_map); 2232139805Sphk m_freem(dp->sis_mbuf); 2233139805Sphk dp->sis_mbuf = NULL; 223450974Swpaul } 2235139805Sphk bzero(sc->sis_rx_list, SIS_RX_LIST_SZ); 223650974Swpaul 223750974Swpaul /* 223850974Swpaul * Free the TX list buffers. 223950974Swpaul */ 2240139805Sphk dp = &sc->sis_tx_list[0]; 2241139805Sphk for (i = 0; i < SIS_TX_LIST_CNT; i++, dp++) { 2242139805Sphk if (dp->sis_mbuf == NULL) 2243139805Sphk continue; 2244139805Sphk bus_dmamap_unload(sc->sis_tag, dp->sis_map); 2245139805Sphk bus_dmamap_destroy(sc->sis_tag, dp->sis_map); 2246139805Sphk m_freem(dp->sis_mbuf); 2247139805Sphk dp->sis_mbuf = NULL; 224850974Swpaul } 224950974Swpaul 2250139805Sphk bzero(sc->sis_tx_list, SIS_TX_LIST_SZ); 225150974Swpaul 2252123833Sphk sc->sis_stopped = 1; 225350974Swpaul} 225450974Swpaul 225550974Swpaul/* 225650974Swpaul * Stop all chip I/O so that the kernel's probe routines don't 225750974Swpaul * get confused by errant DMAs when rebooting. 225850974Swpaul */ 2259102334Salfredstatic void 2260139717Sphksis_shutdown(device_t dev) 226150974Swpaul{ 226250974Swpaul struct sis_softc *sc; 226350974Swpaul 226450974Swpaul sc = device_get_softc(dev); 226567087Swpaul SIS_LOCK(sc); 226650974Swpaul sis_reset(sc); 226750974Swpaul sis_stop(sc); 226867087Swpaul SIS_UNLOCK(sc); 226950974Swpaul} 2270139800Sphk 2271139800Sphkstatic device_method_t sis_methods[] = { 2272139800Sphk /* Device interface */ 2273139800Sphk DEVMETHOD(device_probe, sis_probe), 2274139800Sphk DEVMETHOD(device_attach, sis_attach), 2275139800Sphk DEVMETHOD(device_detach, sis_detach), 2276139800Sphk DEVMETHOD(device_shutdown, sis_shutdown), 2277139800Sphk 2278139800Sphk /* bus interface */ 2279139800Sphk DEVMETHOD(bus_print_child, bus_generic_print_child), 2280139800Sphk DEVMETHOD(bus_driver_added, bus_generic_driver_added), 2281139800Sphk 2282139800Sphk /* MII interface */ 2283139800Sphk DEVMETHOD(miibus_readreg, sis_miibus_readreg), 2284139800Sphk DEVMETHOD(miibus_writereg, sis_miibus_writereg), 2285139800Sphk DEVMETHOD(miibus_statchg, sis_miibus_statchg), 2286139800Sphk 2287139800Sphk { 0, 0 } 2288139800Sphk}; 2289139800Sphk 2290139800Sphkstatic driver_t sis_driver = { 2291139800Sphk "sis", 2292139800Sphk sis_methods, 2293139800Sphk sizeof(struct sis_softc) 2294139800Sphk}; 2295139800Sphk 2296139800Sphkstatic devclass_t sis_devclass; 2297139800Sphk 2298139800SphkDRIVER_MODULE(sis, pci, sis_driver, sis_devclass, 0, 0); 2299139800SphkDRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 2300