if_sis.c revision 150526
1139825Simp/*- 2139740Sphk * Copyright (c) 2005 Poul-Henning Kamp <phk@FreeBSD.org> 350974Swpaul * Copyright (c) 1997, 1998, 1999 450974Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 550974Swpaul * 650974Swpaul * Redistribution and use in source and binary forms, with or without 750974Swpaul * modification, are permitted provided that the following conditions 850974Swpaul * are met: 950974Swpaul * 1. Redistributions of source code must retain the above copyright 1050974Swpaul * notice, this list of conditions and the following disclaimer. 1150974Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1250974Swpaul * notice, this list of conditions and the following disclaimer in the 1350974Swpaul * documentation and/or other materials provided with the distribution. 1450974Swpaul * 3. All advertising materials mentioning features or use of this software 1550974Swpaul * must display the following acknowledgement: 1650974Swpaul * This product includes software developed by Bill Paul. 1750974Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1850974Swpaul * may be used to endorse or promote products derived from this software 1950974Swpaul * without specific prior written permission. 2050974Swpaul * 2150974Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2250974Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2350974Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2450974Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2550974Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2650974Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2750974Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2850974Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2950974Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3050974Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3150974Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3250974Swpaul */ 3350974Swpaul 34122678Sobrien#include <sys/cdefs.h> 35122678Sobrien__FBSDID("$FreeBSD: head/sys/pci/if_sis.c 150526 2005-09-24 20:46:02Z phk $"); 36122678Sobrien 3750974Swpaul/* 3850974Swpaul * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 3950974Swpaul * available from http://www.sis.com.tw. 4050974Swpaul * 4164963Swpaul * This driver also supports the NatSemi DP83815. Datasheets are 4264963Swpaul * available from http://www.national.com. 4364963Swpaul * 4450974Swpaul * Written by Bill Paul <wpaul@ee.columbia.edu> 4550974Swpaul * Electrical Engineering Department 4650974Swpaul * Columbia University, New York City 4750974Swpaul */ 4850974Swpaul/* 4950974Swpaul * The SiS 900 is a fairly simple chip. It uses bus master DMA with 5050974Swpaul * simple TX and RX descriptors of 3 longwords in size. The receiver 5150974Swpaul * has a single perfect filter entry for the station address and a 5250974Swpaul * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 5350974Swpaul * transceiver while the 7016 requires an external transceiver chip. 5450974Swpaul * Both chips offer the standard bit-bang MII interface as well as 5550974Swpaul * an enchanced PHY interface which simplifies accessing MII registers. 5650974Swpaul * 5750974Swpaul * The only downside to this chipset is that RX descriptors must be 5850974Swpaul * longword aligned. 5950974Swpaul */ 6050974Swpaul 6150974Swpaul#include <sys/param.h> 6250974Swpaul#include <sys/systm.h> 6350974Swpaul#include <sys/sockio.h> 6450974Swpaul#include <sys/mbuf.h> 6550974Swpaul#include <sys/malloc.h> 6650974Swpaul#include <sys/kernel.h> 67129876Sphk#include <sys/module.h> 6850974Swpaul#include <sys/socket.h> 6987059Sluigi#include <sys/sysctl.h> 7050974Swpaul 7150974Swpaul#include <net/if.h> 7250974Swpaul#include <net/if_arp.h> 7350974Swpaul#include <net/ethernet.h> 7450974Swpaul#include <net/if_dl.h> 7550974Swpaul#include <net/if_media.h> 7687390Sjhay#include <net/if_types.h> 7787390Sjhay#include <net/if_vlan_var.h> 7850974Swpaul 7950974Swpaul#include <net/bpf.h> 8050974Swpaul 8150974Swpaul#include <machine/bus.h> 8250974Swpaul#include <machine/resource.h> 8350974Swpaul#include <sys/bus.h> 8450974Swpaul#include <sys/rman.h> 8550974Swpaul 8650974Swpaul#include <dev/mii/mii.h> 8750974Swpaul#include <dev/mii/miivar.h> 8850974Swpaul 89119288Simp#include <dev/pci/pcireg.h> 90119288Simp#include <dev/pci/pcivar.h> 9150974Swpaul 9250974Swpaul#define SIS_USEIOSPACE 9350974Swpaul 9450974Swpaul#include <pci/if_sisreg.h> 9550974Swpaul 96113506SmdoddMODULE_DEPEND(sis, pci, 1, 1, 1); 97113506SmdoddMODULE_DEPEND(sis, ether, 1, 1, 1); 9859758SpeterMODULE_DEPEND(sis, miibus, 1, 1, 1); 9959758Speter 10051089Speter/* "controller miibus0" required. See GENERIC if you get errors here. */ 10150974Swpaul#include "miibus_if.h" 10250974Swpaul 103150369Sphk#define SIS_LOCK(_sc) mtx_lock(&(_sc)->sis_mtx) 104150369Sphk#define SIS_UNLOCK(_sc) mtx_unlock(&(_sc)->sis_mtx) 105150369Sphk#define SIS_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sis_mtx, MA_OWNED) 106150369Sphk 10750974Swpaul/* 108150369Sphk * register space access macros 109150369Sphk */ 110150526Sphk#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sis_res[0], reg, val) 111150369Sphk 112150526Sphk#define CSR_READ_4(sc, reg) bus_read_4(sc->sis_res[0], reg) 113150369Sphk 114150526Sphk#define CSR_READ_2(sc, reg) bus_read_2(sc->sis_res[0], reg) 115150369Sphk 116150369Sphk/* 11750974Swpaul * Various supported device vendors/types and their names. 11850974Swpaul */ 11950974Swpaulstatic struct sis_type sis_devs[] = { 12050974Swpaul { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 12150974Swpaul { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 122119712Sphk { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" }, 12350974Swpaul { 0, 0, NULL } 12450974Swpaul}; 12550974Swpaul 126139801Sphkstatic int sis_detach(device_t); 127139801Sphkstatic void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *); 128139801Sphkstatic int sis_ifmedia_upd(struct ifnet *); 129139801Sphkstatic void sis_init(void *); 130139801Sphkstatic void sis_initl(struct sis_softc *); 131139801Sphkstatic void sis_intr(void *); 132139801Sphkstatic int sis_ioctl(struct ifnet *, u_long, caddr_t); 133139801Sphkstatic int sis_newbuf(struct sis_softc *, struct sis_desc *, struct mbuf *); 134139801Sphkstatic void sis_start(struct ifnet *); 135139801Sphkstatic void sis_startl(struct ifnet *); 136139801Sphkstatic void sis_stop(struct sis_softc *); 137139801Sphkstatic void sis_watchdog(struct ifnet *); 13850974Swpaul 139150526Sphk 140150526Sphkstatic struct resource_spec sis_res_spec[] = { 14150974Swpaul#ifdef SIS_USEIOSPACE 142150526Sphk { SYS_RES_IOPORT, SIS_PCI_LOIO, RF_ACTIVE}, 14350974Swpaul#else 144150526Sphk { SYS_RES_MEMORY, SIS_PCI_LOMEM, RF_ACTIVE}, 14550974Swpaul#endif 146150526Sphk { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE}, 147150526Sphk { -1, 0 } 148150526Sphk}; 14950974Swpaul 15050974Swpaul#define SIS_SETBIT(sc, reg, x) \ 15150974Swpaul CSR_WRITE_4(sc, reg, \ 15250974Swpaul CSR_READ_4(sc, reg) | (x)) 15350974Swpaul 15450974Swpaul#define SIS_CLRBIT(sc, reg, x) \ 15550974Swpaul CSR_WRITE_4(sc, reg, \ 15650974Swpaul CSR_READ_4(sc, reg) & ~(x)) 15750974Swpaul 15850974Swpaul#define SIO_SET(x) \ 15950974Swpaul CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 16050974Swpaul 16150974Swpaul#define SIO_CLR(x) \ 16250974Swpaul CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 16350974Swpaul 16481713Swpaulstatic void 165139740Sphksis_dma_map_desc_next(void *arg, bus_dma_segment_t *segs, int nseg, int error) 16681713Swpaul{ 16781713Swpaul struct sis_desc *r; 16881713Swpaul 16981713Swpaul r = arg; 17081713Swpaul r->sis_next = segs->ds_addr; 17181713Swpaul} 17281713Swpaul 17381713Swpaulstatic void 174139740Sphksis_dma_map_desc_ptr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 17581713Swpaul{ 17681713Swpaul struct sis_desc *r; 17781713Swpaul 17881713Swpaul r = arg; 17981713Swpaul r->sis_ptr = segs->ds_addr; 18081713Swpaul} 18181713Swpaul 18281713Swpaulstatic void 183139740Sphksis_dma_map_ring(void *arg, bus_dma_segment_t *segs, int nseg, int error) 18481713Swpaul{ 18581713Swpaul u_int32_t *p; 18681713Swpaul 18781713Swpaul p = arg; 18881713Swpaul *p = segs->ds_addr; 18981713Swpaul} 19081713Swpaul 19162672Swpaul/* 19262672Swpaul * Routine to reverse the bits in a word. Stolen almost 19362672Swpaul * verbatim from /usr/games/fortune. 19462672Swpaul */ 195139740Sphkstatic uint16_t 196139740Sphksis_reverse(uint16_t n) 19762672Swpaul{ 19862672Swpaul n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 19962672Swpaul n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 20062672Swpaul n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 20162672Swpaul n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 20262672Swpaul 20362672Swpaul return(n); 20462672Swpaul} 20562672Swpaul 206102334Salfredstatic void 207139740Sphksis_delay(struct sis_softc *sc) 20850974Swpaul{ 20950974Swpaul int idx; 21050974Swpaul 21150974Swpaul for (idx = (300 / 33) + 1; idx > 0; idx--) 21250974Swpaul CSR_READ_4(sc, SIS_CSR); 21350974Swpaul} 21450974Swpaul 215102334Salfredstatic void 216139740Sphksis_eeprom_idle(struct sis_softc *sc) 21750974Swpaul{ 218139708Sphk int i; 21950974Swpaul 22050974Swpaul SIO_SET(SIS_EECTL_CSEL); 22150974Swpaul sis_delay(sc); 22250974Swpaul SIO_SET(SIS_EECTL_CLK); 22350974Swpaul sis_delay(sc); 22450974Swpaul 22550974Swpaul for (i = 0; i < 25; i++) { 22650974Swpaul SIO_CLR(SIS_EECTL_CLK); 22750974Swpaul sis_delay(sc); 22850974Swpaul SIO_SET(SIS_EECTL_CLK); 22950974Swpaul sis_delay(sc); 23050974Swpaul } 23150974Swpaul 23250974Swpaul SIO_CLR(SIS_EECTL_CLK); 23350974Swpaul sis_delay(sc); 23450974Swpaul SIO_CLR(SIS_EECTL_CSEL); 23550974Swpaul sis_delay(sc); 23650974Swpaul CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 23750974Swpaul} 23850974Swpaul 23950974Swpaul/* 24050974Swpaul * Send a read command and address to the EEPROM, check for ACK. 24150974Swpaul */ 242102334Salfredstatic void 243139740Sphksis_eeprom_putbyte(struct sis_softc *sc, int addr) 24450974Swpaul{ 245139708Sphk int d, i; 24650974Swpaul 24750974Swpaul d = addr | SIS_EECMD_READ; 24850974Swpaul 24950974Swpaul /* 25050974Swpaul * Feed in each bit and stobe the clock. 25150974Swpaul */ 25250974Swpaul for (i = 0x400; i; i >>= 1) { 25350974Swpaul if (d & i) { 25450974Swpaul SIO_SET(SIS_EECTL_DIN); 25550974Swpaul } else { 25650974Swpaul SIO_CLR(SIS_EECTL_DIN); 25750974Swpaul } 25850974Swpaul sis_delay(sc); 25950974Swpaul SIO_SET(SIS_EECTL_CLK); 26050974Swpaul sis_delay(sc); 26150974Swpaul SIO_CLR(SIS_EECTL_CLK); 26250974Swpaul sis_delay(sc); 26350974Swpaul } 26450974Swpaul} 26550974Swpaul 26650974Swpaul/* 26750974Swpaul * Read a word of data stored in the EEPROM at address 'addr.' 26850974Swpaul */ 269102334Salfredstatic void 270139740Sphksis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest) 27150974Swpaul{ 272139708Sphk int i; 27350974Swpaul u_int16_t word = 0; 27450974Swpaul 27550974Swpaul /* Force EEPROM to idle state. */ 27650974Swpaul sis_eeprom_idle(sc); 27750974Swpaul 27850974Swpaul /* Enter EEPROM access mode. */ 27950974Swpaul sis_delay(sc); 28062672Swpaul SIO_CLR(SIS_EECTL_CLK); 28162672Swpaul sis_delay(sc); 28250974Swpaul SIO_SET(SIS_EECTL_CSEL); 28350974Swpaul sis_delay(sc); 28450974Swpaul 28550974Swpaul /* 28650974Swpaul * Send address of word we want to read. 28750974Swpaul */ 28850974Swpaul sis_eeprom_putbyte(sc, addr); 28950974Swpaul 29050974Swpaul /* 29150974Swpaul * Start reading bits from EEPROM. 29250974Swpaul */ 29350974Swpaul for (i = 0x8000; i; i >>= 1) { 29450974Swpaul SIO_SET(SIS_EECTL_CLK); 29550974Swpaul sis_delay(sc); 29650974Swpaul if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 29750974Swpaul word |= i; 29850974Swpaul sis_delay(sc); 29950974Swpaul SIO_CLR(SIS_EECTL_CLK); 30050974Swpaul sis_delay(sc); 30150974Swpaul } 30250974Swpaul 30350974Swpaul /* Turn off EEPROM access mode. */ 30450974Swpaul sis_eeprom_idle(sc); 30550974Swpaul 30650974Swpaul *dest = word; 30750974Swpaul} 30850974Swpaul 30950974Swpaul/* 31050974Swpaul * Read a sequence of words from the EEPROM. 31150974Swpaul */ 312102334Salfredstatic void 313139740Sphksis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap) 31450974Swpaul{ 31550974Swpaul int i; 31650974Swpaul u_int16_t word = 0, *ptr; 31750974Swpaul 31850974Swpaul for (i = 0; i < cnt; i++) { 31950974Swpaul sis_eeprom_getword(sc, off + i, &word); 32050974Swpaul ptr = (u_int16_t *)(dest + (i * 2)); 32150974Swpaul if (swap) 32250974Swpaul *ptr = ntohs(word); 32350974Swpaul else 32450974Swpaul *ptr = word; 32550974Swpaul } 32650974Swpaul} 32750974Swpaul 328144243Sobrien#if defined(__i386__) || defined(__amd64__) 329102334Salfredstatic device_t 330139740Sphksis_find_bridge(device_t dev) 33172197Swpaul{ 33272197Swpaul devclass_t pci_devclass; 33372197Swpaul device_t *pci_devices; 33472197Swpaul int pci_count = 0; 33572197Swpaul device_t *pci_children; 33672197Swpaul int pci_childcount = 0; 33772197Swpaul device_t *busp, *childp; 33887994Sarchie device_t child = NULL; 33972197Swpaul int i, j; 34072197Swpaul 34172197Swpaul if ((pci_devclass = devclass_find("pci")) == NULL) 34272197Swpaul return(NULL); 34372197Swpaul 34472197Swpaul devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 34572197Swpaul 34672197Swpaul for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 34772197Swpaul pci_childcount = 0; 34872197Swpaul device_get_children(*busp, &pci_children, &pci_childcount); 34972197Swpaul for (j = 0, childp = pci_children; 35072197Swpaul j < pci_childcount; j++, childp++) { 35172197Swpaul if (pci_get_vendor(*childp) == SIS_VENDORID && 35272197Swpaul pci_get_device(*childp) == 0x0008) { 35387994Sarchie child = *childp; 35487994Sarchie goto done; 35572197Swpaul } 35672197Swpaul } 35772197Swpaul } 35872197Swpaul 35987994Sarchiedone: 36072197Swpaul free(pci_devices, M_TEMP); 36172197Swpaul free(pci_children, M_TEMP); 36287994Sarchie return(child); 36372197Swpaul} 36472197Swpaul 365102334Salfredstatic void 366139740Sphksis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off, int cnt) 36772197Swpaul{ 36872197Swpaul device_t bridge; 36972197Swpaul u_int8_t reg; 37072197Swpaul int i; 37172197Swpaul bus_space_tag_t btag; 37272197Swpaul 37372197Swpaul bridge = sis_find_bridge(dev); 37472197Swpaul if (bridge == NULL) 37572197Swpaul return; 37672197Swpaul reg = pci_read_config(bridge, 0x48, 1); 37772197Swpaul pci_write_config(bridge, 0x48, reg|0x40, 1); 37872197Swpaul 37972197Swpaul /* XXX */ 380144243Sobrien#if defined(__i386__) 38172197Swpaul btag = I386_BUS_SPACE_IO; 382144243Sobrien#elif defined(__amd64__) 383144243Sobrien btag = AMD64_BUS_SPACE_IO; 384144243Sobrien#endif 38572197Swpaul 38672197Swpaul for (i = 0; i < cnt; i++) { 38772197Swpaul bus_space_write_1(btag, 0x0, 0x70, i + off); 38872197Swpaul *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 38972197Swpaul } 39072197Swpaul 39172197Swpaul pci_write_config(bridge, 0x48, reg & ~0x40, 1); 39272197Swpaul return; 39372197Swpaul} 39489296Swpaul 395102334Salfredstatic void 396139740Sphksis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest) 39789296Swpaul{ 39889296Swpaul u_int32_t filtsave, csrsave; 39989296Swpaul 40089296Swpaul filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 40189296Swpaul csrsave = CSR_READ_4(sc, SIS_CSR); 40289296Swpaul 40389296Swpaul CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 40489296Swpaul CSR_WRITE_4(sc, SIS_CSR, 0); 40589296Swpaul 40689296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 40789296Swpaul 40889296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 40989296Swpaul ((u_int16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 41089296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 41189296Swpaul ((u_int16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 41289296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 41389296Swpaul ((u_int16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 41489296Swpaul 41589296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 41689296Swpaul CSR_WRITE_4(sc, SIS_CSR, csrsave); 41789296Swpaul return; 41889296Swpaul} 41972197Swpaul#endif 42072197Swpaul 421109060Smbr/* 422109060Smbr * Sync the PHYs by setting data bit and strobing the clock 32 times. 423109060Smbr */ 424139740Sphkstatic void 425139740Sphksis_mii_sync(struct sis_softc *sc) 426109060Smbr{ 427139708Sphk int i; 428109060Smbr 429109060Smbr SIO_SET(SIS_MII_DIR|SIS_MII_DATA); 430109060Smbr 431109060Smbr for (i = 0; i < 32; i++) { 432109060Smbr SIO_SET(SIS_MII_CLK); 433109060Smbr DELAY(1); 434109060Smbr SIO_CLR(SIS_MII_CLK); 435109060Smbr DELAY(1); 436109060Smbr } 437109060Smbr} 438109060Smbr 439109060Smbr/* 440109060Smbr * Clock a series of bits through the MII. 441109060Smbr */ 442139740Sphkstatic void 443139740Sphksis_mii_send(struct sis_softc *sc, uint32_t bits, int cnt) 444109060Smbr{ 445109060Smbr int i; 446109060Smbr 447109060Smbr SIO_CLR(SIS_MII_CLK); 448109060Smbr 449109060Smbr for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 450109060Smbr if (bits & i) { 451109060Smbr SIO_SET(SIS_MII_DATA); 452109060Smbr } else { 453109060Smbr SIO_CLR(SIS_MII_DATA); 454109060Smbr } 455109060Smbr DELAY(1); 456109060Smbr SIO_CLR(SIS_MII_CLK); 457109060Smbr DELAY(1); 458109060Smbr SIO_SET(SIS_MII_CLK); 459109060Smbr } 460109060Smbr} 461109060Smbr 462109060Smbr/* 463109060Smbr * Read an PHY register through the MII. 464109060Smbr */ 465139740Sphkstatic int 466139740Sphksis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame) 467109060Smbr{ 468109060Smbr int i, ack, s; 469109060Smbr 470109060Smbr s = splimp(); 471109060Smbr 472109060Smbr /* 473109060Smbr * Set up frame for RX. 474109060Smbr */ 475109060Smbr frame->mii_stdelim = SIS_MII_STARTDELIM; 476109060Smbr frame->mii_opcode = SIS_MII_READOP; 477109060Smbr frame->mii_turnaround = 0; 478109060Smbr frame->mii_data = 0; 479109060Smbr 480109060Smbr /* 481109060Smbr * Turn on data xmit. 482109060Smbr */ 483109060Smbr SIO_SET(SIS_MII_DIR); 484109060Smbr 485109060Smbr sis_mii_sync(sc); 486109060Smbr 487109060Smbr /* 488109060Smbr * Send command/address info. 489109060Smbr */ 490109060Smbr sis_mii_send(sc, frame->mii_stdelim, 2); 491109060Smbr sis_mii_send(sc, frame->mii_opcode, 2); 492109060Smbr sis_mii_send(sc, frame->mii_phyaddr, 5); 493109060Smbr sis_mii_send(sc, frame->mii_regaddr, 5); 494109060Smbr 495109060Smbr /* Idle bit */ 496109060Smbr SIO_CLR((SIS_MII_CLK|SIS_MII_DATA)); 497109060Smbr DELAY(1); 498109060Smbr SIO_SET(SIS_MII_CLK); 499109060Smbr DELAY(1); 500109060Smbr 501109060Smbr /* Turn off xmit. */ 502109060Smbr SIO_CLR(SIS_MII_DIR); 503109060Smbr 504109060Smbr /* Check for ack */ 505109060Smbr SIO_CLR(SIS_MII_CLK); 506109060Smbr DELAY(1); 507109060Smbr ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA; 508109060Smbr SIO_SET(SIS_MII_CLK); 509109060Smbr DELAY(1); 510109060Smbr 511109060Smbr /* 512109060Smbr * Now try reading data bits. If the ack failed, we still 513109060Smbr * need to clock through 16 cycles to keep the PHY(s) in sync. 514109060Smbr */ 515109060Smbr if (ack) { 516109060Smbr for(i = 0; i < 16; i++) { 517109060Smbr SIO_CLR(SIS_MII_CLK); 518109060Smbr DELAY(1); 519109060Smbr SIO_SET(SIS_MII_CLK); 520109060Smbr DELAY(1); 521109060Smbr } 522109060Smbr goto fail; 523109060Smbr } 524109060Smbr 525109060Smbr for (i = 0x8000; i; i >>= 1) { 526109060Smbr SIO_CLR(SIS_MII_CLK); 527109060Smbr DELAY(1); 528109060Smbr if (!ack) { 529109060Smbr if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA) 530109060Smbr frame->mii_data |= i; 531109060Smbr DELAY(1); 532109060Smbr } 533109060Smbr SIO_SET(SIS_MII_CLK); 534109060Smbr DELAY(1); 535109060Smbr } 536109060Smbr 537109060Smbrfail: 538109060Smbr 539109060Smbr SIO_CLR(SIS_MII_CLK); 540109060Smbr DELAY(1); 541109060Smbr SIO_SET(SIS_MII_CLK); 542109060Smbr DELAY(1); 543109060Smbr 544109060Smbr splx(s); 545109060Smbr 546109060Smbr if (ack) 547109060Smbr return(1); 548109060Smbr return(0); 549109060Smbr} 550109060Smbr 551109060Smbr/* 552109060Smbr * Write to a PHY register through the MII. 553109060Smbr */ 554139740Sphkstatic int 555139740Sphksis_mii_writereg(struct sis_softc *sc, struct sis_mii_frame *frame) 556109060Smbr{ 557109060Smbr int s; 558109060Smbr 559109060Smbr s = splimp(); 560109060Smbr /* 561109060Smbr * Set up frame for TX. 562109060Smbr */ 563109060Smbr 564109060Smbr frame->mii_stdelim = SIS_MII_STARTDELIM; 565109060Smbr frame->mii_opcode = SIS_MII_WRITEOP; 566109060Smbr frame->mii_turnaround = SIS_MII_TURNAROUND; 567109060Smbr 568109060Smbr /* 569109060Smbr * Turn on data output. 570109060Smbr */ 571109060Smbr SIO_SET(SIS_MII_DIR); 572109060Smbr 573109060Smbr sis_mii_sync(sc); 574109060Smbr 575109060Smbr sis_mii_send(sc, frame->mii_stdelim, 2); 576109060Smbr sis_mii_send(sc, frame->mii_opcode, 2); 577109060Smbr sis_mii_send(sc, frame->mii_phyaddr, 5); 578109060Smbr sis_mii_send(sc, frame->mii_regaddr, 5); 579109060Smbr sis_mii_send(sc, frame->mii_turnaround, 2); 580109060Smbr sis_mii_send(sc, frame->mii_data, 16); 581109060Smbr 582109060Smbr /* Idle bit. */ 583109060Smbr SIO_SET(SIS_MII_CLK); 584109060Smbr DELAY(1); 585109060Smbr SIO_CLR(SIS_MII_CLK); 586109060Smbr DELAY(1); 587109060Smbr 588109060Smbr /* 589109060Smbr * Turn off xmit. 590109060Smbr */ 591109060Smbr SIO_CLR(SIS_MII_DIR); 592109060Smbr 593109060Smbr splx(s); 594109060Smbr 595109060Smbr return(0); 596109060Smbr} 597109060Smbr 598102334Salfredstatic int 599139740Sphksis_miibus_readreg(device_t dev, int phy, int reg) 60050974Swpaul{ 60150974Swpaul struct sis_softc *sc; 602109060Smbr struct sis_mii_frame frame; 60350974Swpaul 60450974Swpaul sc = device_get_softc(dev); 60550974Swpaul 60662672Swpaul if (sc->sis_type == SIS_TYPE_83815) { 60762672Swpaul if (phy != 0) 60862672Swpaul return(0); 60962672Swpaul /* 61062672Swpaul * The NatSemi chip can take a while after 61162672Swpaul * a reset to come ready, during which the BMSR 61262672Swpaul * returns a value of 0. This is *never* supposed 61362672Swpaul * to happen: some of the BMSR bits are meant to 61462672Swpaul * be hardwired in the on position, and this can 61562672Swpaul * confuse the miibus code a bit during the probe 61662672Swpaul * and attach phase. So we make an effort to check 61762672Swpaul * for this condition and wait for it to clear. 61862672Swpaul */ 61962672Swpaul if (!CSR_READ_4(sc, NS_BMSR)) 62062672Swpaul DELAY(1000); 621109060Smbr return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 62262672Swpaul } 62362672Swpaul 624109976Smbr /* 625109976Smbr * Chipsets < SIS_635 seem not to be able to read/write 626109976Smbr * through mdio. Use the enhanced PHY access register 627109976Smbr * again for them. 628109976Smbr */ 62989296Swpaul if (sc->sis_type == SIS_TYPE_900 && 630109976Smbr sc->sis_rev < SIS_REV_635) { 631109976Smbr int i, val = 0; 63250974Swpaul 633109976Smbr if (phy != 0) 634109976Smbr return(0); 63550974Swpaul 636109976Smbr CSR_WRITE_4(sc, SIS_PHYCTL, 637109976Smbr (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 638109976Smbr SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 63950974Swpaul 640109976Smbr for (i = 0; i < SIS_TIMEOUT; i++) { 641109976Smbr if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 642109976Smbr break; 643109976Smbr } 644109976Smbr 645109976Smbr if (i == SIS_TIMEOUT) { 646109976Smbr printf("sis%d: PHY failed to come ready\n", 647109976Smbr sc->sis_unit); 648109976Smbr return(0); 649109976Smbr } 650109976Smbr 651109976Smbr val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 652109976Smbr 653109976Smbr if (val == 0xFFFF) 654109976Smbr return(0); 655109976Smbr 656109976Smbr return(val); 657109976Smbr } else { 658109976Smbr bzero((char *)&frame, sizeof(frame)); 659109976Smbr 660109976Smbr frame.mii_phyaddr = phy; 661109976Smbr frame.mii_regaddr = reg; 662109976Smbr sis_mii_readreg(sc, &frame); 663109976Smbr 664109976Smbr return(frame.mii_data); 665109976Smbr } 66650974Swpaul} 66750974Swpaul 668102334Salfredstatic int 669139740Sphksis_miibus_writereg(device_t dev, int phy, int reg, int data) 67050974Swpaul{ 67150974Swpaul struct sis_softc *sc; 672109060Smbr struct sis_mii_frame frame; 67350974Swpaul 67450974Swpaul sc = device_get_softc(dev); 67550974Swpaul 67662672Swpaul if (sc->sis_type == SIS_TYPE_83815) { 67762672Swpaul if (phy != 0) 67862672Swpaul return(0); 67962672Swpaul CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 68062672Swpaul return(0); 68162672Swpaul } 68262672Swpaul 683109976Smbr /* 684109976Smbr * Chipsets < SIS_635 seem not to be able to read/write 685109976Smbr * through mdio. Use the enhanced PHY access register 686109976Smbr * again for them. 687109976Smbr */ 688109976Smbr if (sc->sis_type == SIS_TYPE_900 && 689109976Smbr sc->sis_rev < SIS_REV_635) { 690109976Smbr int i; 69150974Swpaul 692109976Smbr if (phy != 0) 693109976Smbr return(0); 69450974Swpaul 695109976Smbr CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 696109976Smbr (reg << 6) | SIS_PHYOP_WRITE); 697109976Smbr SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 69850974Swpaul 699109976Smbr for (i = 0; i < SIS_TIMEOUT; i++) { 700109976Smbr if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 701109976Smbr break; 702109976Smbr } 70350974Swpaul 704109976Smbr if (i == SIS_TIMEOUT) 705109976Smbr printf("sis%d: PHY failed to come ready\n", 706109976Smbr sc->sis_unit); 707109976Smbr } else { 708109976Smbr bzero((char *)&frame, sizeof(frame)); 709109976Smbr 710109976Smbr frame.mii_phyaddr = phy; 711109976Smbr frame.mii_regaddr = reg; 712109976Smbr frame.mii_data = data; 713109976Smbr sis_mii_writereg(sc, &frame); 714109976Smbr } 71550974Swpaul return(0); 71650974Swpaul} 71750974Swpaul 718102334Salfredstatic void 719139717Sphksis_miibus_statchg(device_t dev) 72050974Swpaul{ 72150974Swpaul struct sis_softc *sc; 72250974Swpaul 72350974Swpaul sc = device_get_softc(dev); 724139717Sphk SIS_LOCK_ASSERT(sc); 725139717Sphk sis_initl(sc); 72650974Swpaul} 72750974Swpaul 728139740Sphkstatic uint32_t 729139740Sphksis_mchash(struct sis_softc *sc, const uint8_t *addr) 73050974Swpaul{ 731130270Snaddy uint32_t crc; 73250974Swpaul 73350974Swpaul /* Compute CRC for the address value. */ 734130270Snaddy crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 73550974Swpaul 73662672Swpaul /* 73762672Swpaul * return the filter bit position 73862672Swpaul * 73962672Swpaul * The NatSemi chip has a 512-bit filter, which is 74062672Swpaul * different than the SiS, so we special-case it. 74162672Swpaul */ 74262672Swpaul if (sc->sis_type == SIS_TYPE_83815) 743109060Smbr return (crc >> 23); 744109976Smbr else if (sc->sis_rev >= SIS_REV_635 || 745109976Smbr sc->sis_rev == SIS_REV_900B) 746109060Smbr return (crc >> 24); 747109976Smbr else 748109976Smbr return (crc >> 25); 74950974Swpaul} 75050974Swpaul 751102334Salfredstatic void 752139740Sphksis_setmulti_ns(struct sis_softc *sc) 75350974Swpaul{ 75450974Swpaul struct ifnet *ifp; 75550974Swpaul struct ifmultiaddr *ifma; 75650974Swpaul u_int32_t h = 0, i, filtsave; 75762672Swpaul int bit, index; 75850974Swpaul 759147256Sbrooks ifp = sc->sis_ifp; 76050974Swpaul 76150974Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 76262672Swpaul SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 76350974Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 76450974Swpaul return; 76550974Swpaul } 76650974Swpaul 76762672Swpaul /* 76862672Swpaul * We have to explicitly enable the multicast hash table 76962672Swpaul * on the NatSemi chip if we want to use it, which we do. 77062672Swpaul */ 77162672Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 77250974Swpaul SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 77350974Swpaul 77450974Swpaul filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 77550974Swpaul 77650974Swpaul /* first, zot all the existing hash bits */ 77762672Swpaul for (i = 0; i < 32; i++) { 77862672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 77962672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 78062672Swpaul } 78162672Swpaul 782148654Srwatson IF_ADDR_LOCK(ifp); 78372084Sphk TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 78462672Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 78562672Swpaul continue; 786122625Sobrien h = sis_mchash(sc, 787122625Sobrien LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 78862672Swpaul index = h >> 3; 78962672Swpaul bit = h & 0x1F; 79062672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 79162672Swpaul if (bit > 0xF) 79262672Swpaul bit -= 0x10; 79362672Swpaul SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 79462672Swpaul } 795148654Srwatson IF_ADDR_UNLOCK(ifp); 79662672Swpaul 79762672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 79862672Swpaul 79962672Swpaul return; 80062672Swpaul} 80162672Swpaul 802102334Salfredstatic void 803139740Sphksis_setmulti_sis(struct sis_softc *sc) 80462672Swpaul{ 80562672Swpaul struct ifnet *ifp; 80662672Swpaul struct ifmultiaddr *ifma; 807109060Smbr u_int32_t h, i, n, ctl; 808109060Smbr u_int16_t hashes[16]; 80962672Swpaul 810147256Sbrooks ifp = sc->sis_ifp; 81162672Swpaul 812109060Smbr /* hash table size */ 813109976Smbr if (sc->sis_rev >= SIS_REV_635 || 814109976Smbr sc->sis_rev == SIS_REV_900B) 815109976Smbr n = 16; 816109976Smbr else 817109976Smbr n = 8; 81862672Swpaul 819109060Smbr ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE; 82062672Swpaul 821109060Smbr if (ifp->if_flags & IFF_BROADCAST) 822109060Smbr ctl |= SIS_RXFILTCTL_BROAD; 82362672Swpaul 824109060Smbr if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 825109060Smbr ctl |= SIS_RXFILTCTL_ALLMULTI; 826109060Smbr if (ifp->if_flags & IFF_PROMISC) 827109060Smbr ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS; 828109060Smbr for (i = 0; i < n; i++) 829109060Smbr hashes[i] = ~0; 830109060Smbr } else { 831109060Smbr for (i = 0; i < n; i++) 832109060Smbr hashes[i] = 0; 833109060Smbr i = 0; 834148654Srwatson IF_ADDR_LOCK(ifp); 835109060Smbr TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 836109060Smbr if (ifma->ifma_addr->sa_family != AF_LINK) 837109060Smbr continue; 838122625Sobrien h = sis_mchash(sc, 839109060Smbr LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 840109060Smbr hashes[h >> 4] |= 1 << (h & 0xf); 841109060Smbr i++; 842109060Smbr } 843148654Srwatson IF_ADDR_UNLOCK(ifp); 844109060Smbr if (i > n) { 845109060Smbr ctl |= SIS_RXFILTCTL_ALLMULTI; 846109060Smbr for (i = 0; i < n; i++) 847109060Smbr hashes[i] = ~0; 848109060Smbr } 84950974Swpaul } 85050974Swpaul 851109060Smbr for (i = 0; i < n; i++) { 852109060Smbr CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); 853109060Smbr CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); 85450974Swpaul } 85550974Swpaul 856109060Smbr CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl); 85750974Swpaul} 85850974Swpaul 859102334Salfredstatic void 860139717Sphksis_reset(struct sis_softc *sc) 86150974Swpaul{ 862139708Sphk int i; 86350974Swpaul 86450974Swpaul SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 86550974Swpaul 86650974Swpaul for (i = 0; i < SIS_TIMEOUT; i++) { 86750974Swpaul if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 86850974Swpaul break; 86950974Swpaul } 87050974Swpaul 87150974Swpaul if (i == SIS_TIMEOUT) 87250974Swpaul printf("sis%d: reset never completed\n", sc->sis_unit); 87350974Swpaul 87450974Swpaul /* Wait a little while for the chip to get its brains in order. */ 87550974Swpaul DELAY(1000); 87672813Swpaul 87772813Swpaul /* 87872813Swpaul * If this is a NetSemi chip, make sure to clear 87972813Swpaul * PME mode. 88072813Swpaul */ 88172813Swpaul if (sc->sis_type == SIS_TYPE_83815) { 88272813Swpaul CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 88372813Swpaul CSR_WRITE_4(sc, NS_CLKRUN, 0); 88472813Swpaul } 88572813Swpaul 88650974Swpaul return; 88750974Swpaul} 88850974Swpaul 88950974Swpaul/* 89050974Swpaul * Probe for an SiS chip. Check the PCI vendor and device 89150974Swpaul * IDs against our list and return a device name if we find a match. 89250974Swpaul */ 893102334Salfredstatic int 894139740Sphksis_probe(device_t dev) 89550974Swpaul{ 89650974Swpaul struct sis_type *t; 89750974Swpaul 89850974Swpaul t = sis_devs; 89950974Swpaul 90050974Swpaul while(t->sis_name != NULL) { 90150974Swpaul if ((pci_get_vendor(dev) == t->sis_vid) && 90250974Swpaul (pci_get_device(dev) == t->sis_did)) { 90350974Swpaul device_set_desc(dev, t->sis_name); 904142398Simp return (BUS_PROBE_DEFAULT); 90550974Swpaul } 90650974Swpaul t++; 90750974Swpaul } 90850974Swpaul 90950974Swpaul return(ENXIO); 91050974Swpaul} 91150974Swpaul 91250974Swpaul/* 91350974Swpaul * Attach the interface. Allocate softc structures, do ifmedia 91450974Swpaul * setup and ethernet/BPF attach. 91550974Swpaul */ 916102334Salfredstatic int 917139740Sphksis_attach(device_t dev) 91850974Swpaul{ 91950974Swpaul u_char eaddr[ETHER_ADDR_LEN]; 92050974Swpaul struct sis_softc *sc; 92150974Swpaul struct ifnet *ifp; 922150526Sphk int unit, error = 0, waittime = 0; 92350974Swpaul 924109061Smbr waittime = 0; 92550974Swpaul sc = device_get_softc(dev); 92650974Swpaul unit = device_get_unit(dev); 92750974Swpaul 928119712Sphk sc->sis_self = dev; 929119712Sphk 93093818Sjhb mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 931139810Sphk MTX_DEF); 93269583Swpaul 93350974Swpaul if (pci_get_device(dev) == SIS_DEVICEID_900) 93450974Swpaul sc->sis_type = SIS_TYPE_900; 93550974Swpaul if (pci_get_device(dev) == SIS_DEVICEID_7016) 93650974Swpaul sc->sis_type = SIS_TYPE_7016; 93762672Swpaul if (pci_get_vendor(dev) == NS_VENDORID) 93862672Swpaul sc->sis_type = SIS_TYPE_83815; 93950974Swpaul 94089296Swpaul sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 94150974Swpaul /* 94250974Swpaul * Map control/status registers. 94350974Swpaul */ 94472813Swpaul pci_enable_busmaster(dev); 94550974Swpaul 946150526Sphk error = bus_alloc_resources(dev, sis_res_spec, sc->sis_res); 947150526Sphk if (error) 948150526Sphk return (error); 94950974Swpaul 95050974Swpaul /* Reset the adapter. */ 95150974Swpaul sis_reset(sc); 95250974Swpaul 953109976Smbr if (sc->sis_type == SIS_TYPE_900 && 954109976Smbr (sc->sis_rev == SIS_REV_635 || 955109976Smbr sc->sis_rev == SIS_REV_900B)) { 956109976Smbr SIO_SET(SIS_CFG_RND_CNT); 957109976Smbr SIO_SET(SIS_CFG_PERR_DETECT); 958109976Smbr } 959109976Smbr 96050974Swpaul /* 96150974Swpaul * Get station address from the EEPROM. 96250974Swpaul */ 96362672Swpaul switch (pci_get_vendor(dev)) { 96462672Swpaul case NS_VENDORID: 965119712Sphk sc->sis_srr = CSR_READ_4(sc, NS_SRR); 966119712Sphk 967119712Sphk /* We can't update the device description, so spew */ 968119712Sphk if (sc->sis_srr == NS_SRR_15C) 969119712Sphk device_printf(dev, "Silicon Revision: DP83815C\n"); 970119712Sphk else if (sc->sis_srr == NS_SRR_15D) 971119712Sphk device_printf(dev, "Silicon Revision: DP83815D\n"); 972119712Sphk else if (sc->sis_srr == NS_SRR_16A) 973119712Sphk device_printf(dev, "Silicon Revision: DP83816A\n"); 974119712Sphk else 975119712Sphk device_printf(dev, "Silicon Revision %x\n", sc->sis_srr); 976119712Sphk 97762672Swpaul /* 97862672Swpaul * Reading the MAC address out of the EEPROM on 97962672Swpaul * the NatSemi chip takes a bit more work than 98062672Swpaul * you'd expect. The address spans 4 16-bit words, 98162672Swpaul * with the first word containing only a single bit. 98262672Swpaul * You have to shift everything over one bit to 98362672Swpaul * get it aligned properly. Also, the bits are 98462672Swpaul * stored backwards (the LSB is really the MSB, 98562672Swpaul * and so on) so you have to reverse them in order 98662672Swpaul * to get the MAC address into the form we want. 98762672Swpaul * Why? Who the hell knows. 98862672Swpaul */ 98962672Swpaul { 99062672Swpaul u_int16_t tmp[4]; 99150974Swpaul 99262672Swpaul sis_read_eeprom(sc, (caddr_t)&tmp, 99362672Swpaul NS_EE_NODEADDR, 4, 0); 99462672Swpaul 99562672Swpaul /* Shift everything over one bit. */ 99662672Swpaul tmp[3] = tmp[3] >> 1; 99762681Swpaul tmp[3] |= tmp[2] << 15; 99862672Swpaul tmp[2] = tmp[2] >> 1; 99962681Swpaul tmp[2] |= tmp[1] << 15; 100062672Swpaul tmp[1] = tmp[1] >> 1; 100162681Swpaul tmp[1] |= tmp[0] << 15; 100262672Swpaul 100362672Swpaul /* Now reverse all the bits. */ 100462672Swpaul tmp[3] = sis_reverse(tmp[3]); 100562672Swpaul tmp[2] = sis_reverse(tmp[2]); 100662672Swpaul tmp[1] = sis_reverse(tmp[1]); 100762672Swpaul 100862672Swpaul bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); 100962672Swpaul } 101062672Swpaul break; 101162672Swpaul case SIS_VENDORID: 101262672Swpaul default: 1013144243Sobrien#if defined(__i386__) || defined(__amd64__) 101472197Swpaul /* 101572197Swpaul * If this is a SiS 630E chipset with an embedded 101672197Swpaul * SiS 900 controller, we have to read the MAC address 101772197Swpaul * from the APC CMOS RAM. Our method for doing this 101872197Swpaul * is very ugly since we have to reach out and grab 101972197Swpaul * ahold of hardware for which we cannot properly 102072197Swpaul * allocate resources. This code is only compiled on 102172197Swpaul * the i386 architecture since the SiS 630E chipset 102272197Swpaul * is for x86 motherboards only. Note that there are 102372197Swpaul * a lot of magic numbers in this hack. These are 102472197Swpaul * taken from SiS's Linux driver. I'd like to replace 102572197Swpaul * them with proper symbolic definitions, but that 102672197Swpaul * requires some datasheets that I don't have access 102772197Swpaul * to at the moment. 102872197Swpaul */ 102989296Swpaul if (sc->sis_rev == SIS_REV_630S || 103089296Swpaul sc->sis_rev == SIS_REV_630E || 103190328Sambrisko sc->sis_rev == SIS_REV_630EA1) 103272197Swpaul sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 103389296Swpaul 103490328Sambrisko else if (sc->sis_rev == SIS_REV_635 || 103590328Sambrisko sc->sis_rev == SIS_REV_630ET) 103689296Swpaul sis_read_mac(sc, dev, (caddr_t)&eaddr); 1037109061Smbr else if (sc->sis_rev == SIS_REV_96x) { 1038109061Smbr /* Allow to read EEPROM from LAN. It is shared 1039109061Smbr * between a 1394 controller and the NIC and each 1040109061Smbr * time we access it, we need to set SIS_EECMD_REQ. 1041109061Smbr */ 1042109061Smbr SIO_SET(SIS_EECMD_REQ); 1043109061Smbr for (waittime = 0; waittime < SIS_TIMEOUT; 1044109061Smbr waittime++) { 1045109061Smbr /* Force EEPROM to idle state. */ 1046109061Smbr sis_eeprom_idle(sc); 1047109061Smbr if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { 1048109061Smbr sis_read_eeprom(sc, (caddr_t)&eaddr, 1049109061Smbr SIS_EE_NODEADDR, 3, 0); 1050109061Smbr break; 1051109061Smbr } 1052109061Smbr DELAY(1); 1053109061Smbr } 1054109061Smbr /* 1055109061Smbr * Set SIS_EECTL_CLK to high, so a other master 1056109061Smbr * can operate on the i2c bus. 1057109061Smbr */ 1058109061Smbr SIO_SET(SIS_EECTL_CLK); 1059109061Smbr /* Refuse EEPROM access by LAN */ 1060109061Smbr SIO_SET(SIS_EECMD_DONE); 1061109061Smbr } else 106272197Swpaul#endif 106372197Swpaul sis_read_eeprom(sc, (caddr_t)&eaddr, 106472197Swpaul SIS_EE_NODEADDR, 3, 0); 106562672Swpaul break; 106662672Swpaul } 106762672Swpaul 106850974Swpaul sc->sis_unit = unit; 1069129636Srwatson if (debug_mpsafenet) 1070129636Srwatson callout_init(&sc->sis_stat_ch, CALLOUT_MPSAFE); 1071129636Srwatson else 1072129636Srwatson callout_init(&sc->sis_stat_ch, 0); 107350974Swpaul 107481713Swpaul /* 107581713Swpaul * Allocate the parent bus DMA tag appropriate for PCI. 107681713Swpaul */ 107781713Swpaul#define SIS_NSEG_NEW 32 107881713Swpaul error = bus_dma_tag_create(NULL, /* parent */ 107981713Swpaul 1, 0, /* alignment, boundary */ 108081713Swpaul BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 108181713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 108281713Swpaul NULL, NULL, /* filter, filterarg */ 108381713Swpaul MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */ 108481713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 108581713Swpaul BUS_DMA_ALLOCNOW, /* flags */ 1086117126Sscottl NULL, NULL, /* lockfunc, lockarg */ 108781713Swpaul &sc->sis_parent_tag); 1088112872Snjl if (error) 1089112872Snjl goto fail; 109050974Swpaul 109181713Swpaul /* 1092112872Snjl * Now allocate a tag for the DMA descriptor lists and a chunk 1093112872Snjl * of DMA-able memory based on the tag. Also obtain the physical 1094112872Snjl * addresses of the RX and TX ring, which we'll need later. 109581713Swpaul * All of our lists are allocated as a contiguous block 109681713Swpaul * of memory. 109781713Swpaul */ 109881713Swpaul error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 109981713Swpaul 1, 0, /* alignment, boundary */ 110081713Swpaul BUS_SPACE_MAXADDR, /* lowaddr */ 110181713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 110281713Swpaul NULL, NULL, /* filter, filterarg */ 110381713Swpaul SIS_RX_LIST_SZ, 1, /* maxsize,nsegments */ 110481713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 110581713Swpaul 0, /* flags */ 1106117126Sscottl busdma_lock_mutex, /* lockfunc */ 1107117126Sscottl &Giant, /* lockarg */ 1108139690Sphk &sc->sis_rx_tag); 1109112872Snjl if (error) 1110112872Snjl goto fail; 111181713Swpaul 1112139690Sphk error = bus_dmamem_alloc(sc->sis_rx_tag, 1113139690Sphk (void **)&sc->sis_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1114139690Sphk &sc->sis_rx_dmamap); 1115112872Snjl 1116112872Snjl if (error) { 1117112872Snjl printf("sis%d: no memory for rx list buffers!\n", unit); 1118139690Sphk bus_dma_tag_destroy(sc->sis_rx_tag); 1119139690Sphk sc->sis_rx_tag = NULL; 1120112872Snjl goto fail; 1121112872Snjl } 1122112872Snjl 1123139690Sphk error = bus_dmamap_load(sc->sis_rx_tag, 1124139690Sphk sc->sis_rx_dmamap, &(sc->sis_rx_list[0]), 1125112872Snjl sizeof(struct sis_desc), sis_dma_map_ring, 1126139690Sphk &sc->sis_rx_paddr, 0); 1127112872Snjl 1128112872Snjl if (error) { 1129112872Snjl printf("sis%d: cannot get address of the rx ring!\n", unit); 1130139690Sphk bus_dmamem_free(sc->sis_rx_tag, 1131139690Sphk sc->sis_rx_list, sc->sis_rx_dmamap); 1132139690Sphk bus_dma_tag_destroy(sc->sis_rx_tag); 1133139690Sphk sc->sis_rx_tag = NULL; 1134112872Snjl goto fail; 1135112872Snjl } 1136112872Snjl 113781713Swpaul error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 113881713Swpaul 1, 0, /* alignment, boundary */ 113981713Swpaul BUS_SPACE_MAXADDR, /* lowaddr */ 114081713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 114181713Swpaul NULL, NULL, /* filter, filterarg */ 114281713Swpaul SIS_TX_LIST_SZ, 1, /* maxsize,nsegments */ 114381713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 114481713Swpaul 0, /* flags */ 1145117126Sscottl busdma_lock_mutex, /* lockfunc */ 1146117126Sscottl &Giant, /* lockarg */ 1147139690Sphk &sc->sis_tx_tag); 1148112872Snjl if (error) 1149112872Snjl goto fail; 115081713Swpaul 1151139690Sphk error = bus_dmamem_alloc(sc->sis_tx_tag, 1152139690Sphk (void **)&sc->sis_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1153139690Sphk &sc->sis_tx_dmamap); 115481713Swpaul 115581713Swpaul if (error) { 1156112872Snjl printf("sis%d: no memory for tx list buffers!\n", unit); 1157139690Sphk bus_dma_tag_destroy(sc->sis_tx_tag); 1158139690Sphk sc->sis_tx_tag = NULL; 115950974Swpaul goto fail; 116050974Swpaul } 116150974Swpaul 1162139690Sphk error = bus_dmamap_load(sc->sis_tx_tag, 1163139690Sphk sc->sis_tx_dmamap, &(sc->sis_tx_list[0]), 1164112872Snjl sizeof(struct sis_desc), sis_dma_map_ring, 1165139690Sphk &sc->sis_tx_paddr, 0); 116681713Swpaul 116781713Swpaul if (error) { 1168112872Snjl printf("sis%d: cannot get address of the tx ring!\n", unit); 1169139690Sphk bus_dmamem_free(sc->sis_tx_tag, 1170139690Sphk sc->sis_tx_list, sc->sis_tx_dmamap); 1171139690Sphk bus_dma_tag_destroy(sc->sis_tx_tag); 1172139690Sphk sc->sis_tx_tag = NULL; 117381713Swpaul goto fail; 117481713Swpaul } 117581713Swpaul 1176112872Snjl error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1177112872Snjl 1, 0, /* alignment, boundary */ 1178112872Snjl BUS_SPACE_MAXADDR, /* lowaddr */ 1179112872Snjl BUS_SPACE_MAXADDR, /* highaddr */ 1180112872Snjl NULL, NULL, /* filter, filterarg */ 1181112872Snjl MCLBYTES, 1, /* maxsize,nsegments */ 1182112872Snjl BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1183112872Snjl 0, /* flags */ 1184117126Sscottl busdma_lock_mutex, /* lockfunc */ 1185117126Sscottl &Giant, /* lockarg */ 1186112872Snjl &sc->sis_tag); 1187112872Snjl if (error) 1188112872Snjl goto fail; 118981713Swpaul 119081713Swpaul /* 119181713Swpaul * Obtain the physical addresses of the RX and TX 119281713Swpaul * rings which we'll need later in the init routine. 119381713Swpaul */ 119481713Swpaul 1195147256Sbrooks ifp = sc->sis_ifp = if_alloc(IFT_ETHER); 1196147256Sbrooks if (ifp == NULL) { 1197147256Sbrooks printf("sis%d: can not if_alloc()\n", sc->sis_unit); 1198147256Sbrooks error = ENOSPC; 1199147256Sbrooks goto fail; 1200147256Sbrooks } 120150974Swpaul ifp->if_softc = sc; 1202121816Sbrooks if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 120350974Swpaul ifp->if_mtu = ETHERMTU; 120450974Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 120550974Swpaul ifp->if_ioctl = sis_ioctl; 120650974Swpaul ifp->if_start = sis_start; 120750974Swpaul ifp->if_watchdog = sis_watchdog; 120850974Swpaul ifp->if_init = sis_init; 120950974Swpaul ifp->if_baudrate = 10000000; 1210131455Smlaier IFQ_SET_MAXLEN(&ifp->if_snd, SIS_TX_LIST_CNT - 1); 1211131455Smlaier ifp->if_snd.ifq_drv_maxlen = SIS_TX_LIST_CNT - 1; 1212131455Smlaier IFQ_SET_READY(&ifp->if_snd); 121350974Swpaul 121450974Swpaul /* 121550974Swpaul * Do MII setup. 121650974Swpaul */ 121750974Swpaul if (mii_phy_probe(dev, &sc->sis_miibus, 121850974Swpaul sis_ifmedia_upd, sis_ifmedia_sts)) { 121950974Swpaul printf("sis%d: MII without any PHY!\n", sc->sis_unit); 122050974Swpaul error = ENXIO; 122150974Swpaul goto fail; 122250974Swpaul } 122350974Swpaul 122450974Swpaul /* 122563090Sarchie * Call MI attach routine. 122650974Swpaul */ 1227106936Ssam ether_ifattach(ifp, eaddr); 122887390Sjhay 122987390Sjhay /* 123087390Sjhay * Tell the upper layer(s) we support long frames. 123187390Sjhay */ 123287390Sjhay ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1233106936Ssam ifp->if_capabilities |= IFCAP_VLAN_MTU; 123487390Sjhay 1235128138Sru#ifdef DEVICE_POLLING 1236128138Sru ifp->if_capabilities |= IFCAP_POLLING; 1237128138Sru#endif 1238128138Sru ifp->if_capenable = ifp->if_capabilities; 1239128138Sru 1240113609Snjl /* Hook interrupt last to avoid having to lock softc */ 1241150526Sphk error = bus_setup_intr(dev, sc->sis_res[1], INTR_TYPE_NET | INTR_MPSAFE, 1242112872Snjl sis_intr, sc, &sc->sis_intrhand); 124350974Swpaul 1244112872Snjl if (error) { 1245112872Snjl printf("sis%d: couldn't set up irq\n", unit); 1246113609Snjl ether_ifdetach(ifp); 1247112872Snjl goto fail; 1248112872Snjl } 1249112872Snjl 125050974Swpaulfail: 1251112872Snjl if (error) 1252112872Snjl sis_detach(dev); 1253112872Snjl 125450974Swpaul return(error); 125550974Swpaul} 125650974Swpaul 1257113609Snjl/* 1258113609Snjl * Shutdown hardware and free up resources. This can be called any 1259113609Snjl * time after the mutex has been initialized. It is called in both 1260113609Snjl * the error case in attach and the normal detach case so it needs 1261113609Snjl * to be careful about only freeing resources that have actually been 1262113609Snjl * allocated. 1263113609Snjl */ 1264102334Salfredstatic int 1265139740Sphksis_detach(device_t dev) 126650974Swpaul{ 126750974Swpaul struct sis_softc *sc; 126850974Swpaul struct ifnet *ifp; 126950974Swpaul 127050974Swpaul sc = device_get_softc(dev); 1271112880Sjhb KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized")); 127267087Swpaul SIS_LOCK(sc); 1273147256Sbrooks ifp = sc->sis_ifp; 127450974Swpaul 1275118089Smux /* These should only be active if attach succeeded. */ 1276113812Simp if (device_is_attached(dev)) { 1277113609Snjl sis_reset(sc); 1278113609Snjl sis_stop(sc); 1279112872Snjl ether_ifdetach(ifp); 1280150213Sru } 1281150213Sru if (ifp) 1282147256Sbrooks if_free(ifp); 1283113609Snjl if (sc->sis_miibus) 1284112872Snjl device_delete_child(dev, sc->sis_miibus); 1285113609Snjl bus_generic_detach(dev); 128650974Swpaul 1287112872Snjl if (sc->sis_intrhand) 1288150526Sphk bus_teardown_intr(dev, sc->sis_res[1], sc->sis_intrhand); 1289150526Sphk bus_release_resources(dev, sis_res_spec, sc->sis_res); 129050974Swpaul 1291139690Sphk if (sc->sis_rx_tag) { 1292139690Sphk bus_dmamap_unload(sc->sis_rx_tag, 1293139690Sphk sc->sis_rx_dmamap); 1294139690Sphk bus_dmamem_free(sc->sis_rx_tag, 1295139690Sphk sc->sis_rx_list, sc->sis_rx_dmamap); 1296139690Sphk bus_dma_tag_destroy(sc->sis_rx_tag); 1297112872Snjl } 1298139690Sphk if (sc->sis_tx_tag) { 1299139690Sphk bus_dmamap_unload(sc->sis_tx_tag, 1300139690Sphk sc->sis_tx_dmamap); 1301139690Sphk bus_dmamem_free(sc->sis_tx_tag, 1302139690Sphk sc->sis_tx_list, sc->sis_tx_dmamap); 1303139690Sphk bus_dma_tag_destroy(sc->sis_tx_tag); 1304112872Snjl } 1305112872Snjl if (sc->sis_parent_tag) 1306112872Snjl bus_dma_tag_destroy(sc->sis_parent_tag); 1307112872Snjl if (sc->sis_tag) 1308112872Snjl bus_dma_tag_destroy(sc->sis_tag); 130950974Swpaul 131067087Swpaul SIS_UNLOCK(sc); 131167087Swpaul mtx_destroy(&sc->sis_mtx); 131250974Swpaul 131350974Swpaul return(0); 131450974Swpaul} 131550974Swpaul 131650974Swpaul/* 1317139802Sphk * Initialize the TX and RX descriptors and allocate mbufs for them. Note that 1318139802Sphk * we arrange the descriptors in a closed ring, so that the last descriptor 1319139802Sphk * points back to the first. 132050974Swpaul */ 1321102334Salfredstatic int 1322139802Sphksis_ring_init(struct sis_softc *sc) 132350974Swpaul{ 1324139802Sphk int i, error; 1325139802Sphk struct sis_desc *dp; 132650974Swpaul 1327139802Sphk dp = &sc->sis_tx_list[0]; 1328139802Sphk for (i = 0; i < SIS_TX_LIST_CNT; i++, dp++) { 1329139802Sphk if (i == (SIS_TX_LIST_CNT - 1)) 1330139802Sphk dp->sis_nextdesc = &sc->sis_tx_list[0]; 1331139802Sphk else 1332139802Sphk dp->sis_nextdesc = dp + 1; 1333139802Sphk bus_dmamap_load(sc->sis_tx_tag, 1334139802Sphk sc->sis_tx_dmamap, 1335139802Sphk dp->sis_nextdesc, sizeof(struct sis_desc), 1336139802Sphk sis_dma_map_desc_next, dp, 0); 1337139802Sphk dp->sis_mbuf = NULL; 1338139802Sphk dp->sis_ptr = 0; 1339139802Sphk dp->sis_ctl = 0; 134050974Swpaul } 134150974Swpaul 1342139690Sphk sc->sis_tx_prod = sc->sis_tx_cons = sc->sis_tx_cnt = 0; 134350974Swpaul 1344139690Sphk bus_dmamap_sync(sc->sis_tx_tag, 1345148444Sjhb sc->sis_tx_dmamap, BUS_DMASYNC_PREWRITE); 134681713Swpaul 1347139802Sphk dp = &sc->sis_rx_list[0]; 1348139802Sphk for (i = 0; i < SIS_RX_LIST_CNT; i++, dp++) { 1349139802Sphk error = sis_newbuf(sc, dp, NULL); 1350139802Sphk if (error) 1351139802Sphk return(error); 1352139802Sphk if (i == (SIS_RX_LIST_CNT - 1)) 1353139802Sphk dp->sis_nextdesc = &sc->sis_rx_list[0]; 1354139802Sphk else 1355139802Sphk dp->sis_nextdesc = dp + 1; 1356139802Sphk bus_dmamap_load(sc->sis_rx_tag, 1357139802Sphk sc->sis_rx_dmamap, 1358139802Sphk dp->sis_nextdesc, sizeof(struct sis_desc), 1359139802Sphk sis_dma_map_desc_next, dp, 0); 136050974Swpaul } 136150974Swpaul 1362139690Sphk bus_dmamap_sync(sc->sis_rx_tag, 1363139690Sphk sc->sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 136481713Swpaul 1365139691Sphk sc->sis_rx_pdsc = &sc->sis_rx_list[0]; 136650974Swpaul 136750974Swpaul return(0); 136850974Swpaul} 136950974Swpaul 137050974Swpaul/* 137150974Swpaul * Initialize an RX descriptor and attach an MBUF cluster. 137250974Swpaul */ 1373102334Salfredstatic int 1374139740Sphksis_newbuf(struct sis_softc *sc, struct sis_desc *c, struct mbuf *m) 137550974Swpaul{ 137650974Swpaul 137781713Swpaul if (c == NULL) 137881713Swpaul return(EINVAL); 137981713Swpaul 138050974Swpaul if (m == NULL) { 1381111119Simp m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1382101340Sluigi if (m == NULL) 138350974Swpaul return(ENOBUFS); 1384101340Sluigi } else 1385101340Sluigi m->m_data = m->m_ext.ext_buf; 138650974Swpaul 1387101340Sluigi c->sis_mbuf = m; 138850974Swpaul c->sis_ctl = SIS_RXLEN; 138950974Swpaul 139081713Swpaul bus_dmamap_create(sc->sis_tag, 0, &c->sis_map); 139181713Swpaul bus_dmamap_load(sc->sis_tag, c->sis_map, 1392101464Sluigi mtod(m, void *), MCLBYTES, 139381713Swpaul sis_dma_map_desc_ptr, c, 0); 1394139944Ssam bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREREAD); 139581713Swpaul 139650974Swpaul return(0); 139750974Swpaul} 139850974Swpaul 139950974Swpaul/* 140050974Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 140150974Swpaul * the higher level protocols. 140250974Swpaul */ 1403102334Salfredstatic void 1404139740Sphksis_rxeof(struct sis_softc *sc) 140550974Swpaul{ 140650974Swpaul struct mbuf *m; 140750974Swpaul struct ifnet *ifp; 140850974Swpaul struct sis_desc *cur_rx; 1409139691Sphk int total_len = 0; 141050974Swpaul u_int32_t rxstat; 141150974Swpaul 1412122689Ssam SIS_LOCK_ASSERT(sc); 1413122689Ssam 1414147256Sbrooks ifp = sc->sis_ifp; 141550974Swpaul 1416139691Sphk for(cur_rx = sc->sis_rx_pdsc; SIS_OWNDESC(cur_rx); 1417139691Sphk cur_rx = cur_rx->sis_nextdesc) { 141850974Swpaul 141987902Sluigi#ifdef DEVICE_POLLING 1420102052Ssobomax if (ifp->if_flags & IFF_POLLING) { 142187902Sluigi if (sc->rxcycles <= 0) 142287902Sluigi break; 142387902Sluigi sc->rxcycles--; 142487902Sluigi } 142587902Sluigi#endif /* DEVICE_POLLING */ 142650974Swpaul rxstat = cur_rx->sis_rxstat; 142781713Swpaul bus_dmamap_sync(sc->sis_tag, 142881713Swpaul cur_rx->sis_map, BUS_DMASYNC_POSTWRITE); 142981713Swpaul bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map); 143081713Swpaul bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map); 143150974Swpaul m = cur_rx->sis_mbuf; 143250974Swpaul cur_rx->sis_mbuf = NULL; 143350974Swpaul total_len = SIS_RXBYTES(cur_rx); 143450974Swpaul 143550974Swpaul /* 143650974Swpaul * If an error occurs, update stats, clear the 143750974Swpaul * status word and leave the mbuf cluster in place: 143850974Swpaul * it should simply get re-used next time this descriptor 143950974Swpaul * comes up in the ring. 144050974Swpaul */ 144150974Swpaul if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 144250974Swpaul ifp->if_ierrors++; 144350974Swpaul if (rxstat & SIS_RXSTAT_COLL) 144450974Swpaul ifp->if_collisions++; 144550974Swpaul sis_newbuf(sc, cur_rx, m); 144650974Swpaul continue; 144750974Swpaul } 144850974Swpaul 144950974Swpaul /* No errors; receive the packet. */ 1450144243Sobrien#if defined(__i386__) || defined(__amd64__) 145187059Sluigi /* 145287059Sluigi * On the x86 we do not have alignment problems, so try to 145387059Sluigi * allocate a new buffer for the receive ring, and pass up 145487059Sluigi * the one where the packet is already, saving the expensive 145587059Sluigi * copy done in m_devget(). 145687059Sluigi * If we are on an architecture with alignment problems, or 145787059Sluigi * if the allocation fails, then use m_devget and leave the 145887059Sluigi * existing buffer in the receive ring. 145987059Sluigi */ 1460101464Sluigi if (sis_newbuf(sc, cur_rx, NULL) == 0) 146187059Sluigi m->m_pkthdr.len = m->m_len = total_len; 1462101464Sluigi else 146387059Sluigi#endif 146487059Sluigi { 146587059Sluigi struct mbuf *m0; 146687059Sluigi m0 = m_devget(mtod(m, char *), total_len, 146787059Sluigi ETHER_ALIGN, ifp, NULL); 146887059Sluigi sis_newbuf(sc, cur_rx, m); 146987059Sluigi if (m0 == NULL) { 147087059Sluigi ifp->if_ierrors++; 147187059Sluigi continue; 147287059Sluigi } 147387059Sluigi m = m0; 147450974Swpaul } 147550974Swpaul 147650974Swpaul ifp->if_ipackets++; 1477106936Ssam m->m_pkthdr.rcvif = ifp; 1478106936Ssam 1479122689Ssam SIS_UNLOCK(sc); 1480106936Ssam (*ifp->if_input)(ifp, m); 1481122689Ssam SIS_LOCK(sc); 148250974Swpaul } 148350974Swpaul 1484139691Sphk sc->sis_rx_pdsc = cur_rx; 148550974Swpaul} 148650974Swpaul 1487105219Sphkstatic void 1488139715Sphksis_rxeoc(struct sis_softc *sc) 148950974Swpaul{ 1490139715Sphk 1491139715Sphk SIS_LOCK_ASSERT(sc); 149250974Swpaul sis_rxeof(sc); 1493139715Sphk sis_initl(sc); 149450974Swpaul} 149550974Swpaul 149650974Swpaul/* 149750974Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 149850974Swpaul * the list buffers. 149950974Swpaul */ 150050974Swpaul 1501102334Salfredstatic void 1502139740Sphksis_txeof(struct sis_softc *sc) 150350974Swpaul{ 150450974Swpaul struct ifnet *ifp; 150550974Swpaul u_int32_t idx; 150650974Swpaul 1507139715Sphk SIS_LOCK_ASSERT(sc); 1508147256Sbrooks ifp = sc->sis_ifp; 150950974Swpaul 151050974Swpaul /* 151150974Swpaul * Go through our tx list and free mbufs for those 151250974Swpaul * frames that have been transmitted. 151350974Swpaul */ 1514139690Sphk for (idx = sc->sis_tx_cons; sc->sis_tx_cnt > 0; 1515139690Sphk sc->sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) { 1516139690Sphk struct sis_desc *cur_tx = &sc->sis_tx_list[idx]; 151750974Swpaul 151850974Swpaul if (SIS_OWNDESC(cur_tx)) 151950974Swpaul break; 152050974Swpaul 152199163Sluigi if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) 152250974Swpaul continue; 152350974Swpaul 152450974Swpaul if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 152550974Swpaul ifp->if_oerrors++; 152650974Swpaul if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 152750974Swpaul ifp->if_collisions++; 152850974Swpaul if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 152950974Swpaul ifp->if_collisions++; 153050974Swpaul } 153150974Swpaul 153250974Swpaul ifp->if_collisions += 153350974Swpaul (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 153450974Swpaul 153550974Swpaul ifp->if_opackets++; 153650974Swpaul if (cur_tx->sis_mbuf != NULL) { 153750974Swpaul m_freem(cur_tx->sis_mbuf); 153850974Swpaul cur_tx->sis_mbuf = NULL; 153981713Swpaul bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map); 154081713Swpaul bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map); 154150974Swpaul } 154299163Sluigi } 154350974Swpaul 1544139690Sphk if (idx != sc->sis_tx_cons) { 154599163Sluigi /* we freed up some buffers */ 1546139690Sphk sc->sis_tx_cons = idx; 1547148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 154850974Swpaul } 154950974Swpaul 1550139690Sphk ifp->if_timer = (sc->sis_tx_cnt == 0) ? 0 : 5; 155150974Swpaul 155250974Swpaul return; 155350974Swpaul} 155450974Swpaul 1555102334Salfredstatic void 1556139740Sphksis_tick(void *xsc) 155750974Swpaul{ 155850974Swpaul struct sis_softc *sc; 155950974Swpaul struct mii_data *mii; 156064963Swpaul struct ifnet *ifp; 156150974Swpaul 156250974Swpaul sc = xsc; 156367087Swpaul SIS_LOCK(sc); 1564117858Scognet sc->in_tick = 1; 1565147256Sbrooks ifp = sc->sis_ifp; 156664963Swpaul 156750974Swpaul mii = device_get_softc(sc->sis_miibus); 156850974Swpaul mii_tick(mii); 156964963Swpaul 157084147Sjlemon if (!sc->sis_link && mii->mii_media_status & IFM_ACTIVE && 157184147Sjlemon IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 157284147Sjlemon sc->sis_link++; 1573131455Smlaier if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1574139714Sphk sis_startl(ifp); 157564963Swpaul } 157664963Swpaul 1577119785Ssam callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 1578117858Scognet sc->in_tick = 0; 157967087Swpaul SIS_UNLOCK(sc); 158050974Swpaul} 158150974Swpaul 158287902Sluigi#ifdef DEVICE_POLLING 158387902Sluigistatic poll_handler_t sis_poll; 158487902Sluigi 158587902Sluigistatic void 158687902Sluigisis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 158787902Sluigi{ 158887973Speter struct sis_softc *sc = ifp->if_softc; 158987973Speter 159087902Sluigi SIS_LOCK(sc); 1591128138Sru if (!(ifp->if_capenable & IFCAP_POLLING)) { 1592128138Sru ether_poll_deregister(ifp); 1593128138Sru cmd = POLL_DEREGISTER; 1594128138Sru } 159587902Sluigi if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 159687902Sluigi CSR_WRITE_4(sc, SIS_IER, 1); 159787902Sluigi goto done; 159887902Sluigi } 159987902Sluigi 160087902Sluigi /* 160187902Sluigi * On the sis, reading the status register also clears it. 160287902Sluigi * So before returning to intr mode we must make sure that all 160387902Sluigi * possible pending sources of interrupts have been served. 160487902Sluigi * In practice this means run to completion the *eof routines, 160587902Sluigi * and then call the interrupt routine 160687902Sluigi */ 160787902Sluigi sc->rxcycles = count; 160887902Sluigi sis_rxeof(sc); 160987902Sluigi sis_txeof(sc); 1610131455Smlaier if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1611139714Sphk sis_startl(ifp); 161287902Sluigi 161387902Sluigi if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 161487902Sluigi u_int32_t status; 161587902Sluigi 161687902Sluigi /* Reading the ISR register clears all interrupts. */ 161787902Sluigi status = CSR_READ_4(sc, SIS_ISR); 161887902Sluigi 161987902Sluigi if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 162087902Sluigi sis_rxeoc(sc); 162187902Sluigi 162287902Sluigi if (status & (SIS_ISR_RX_IDLE)) 162387902Sluigi SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 162487902Sluigi 162587902Sluigi if (status & SIS_ISR_SYSERR) { 162687902Sluigi sis_reset(sc); 1627139715Sphk sis_initl(sc); 162887902Sluigi } 162987902Sluigi } 163087902Sluigidone: 163187902Sluigi SIS_UNLOCK(sc); 163287902Sluigi} 163387902Sluigi#endif /* DEVICE_POLLING */ 163487902Sluigi 1635102334Salfredstatic void 1636139740Sphksis_intr(void *arg) 163750974Swpaul{ 163850974Swpaul struct sis_softc *sc; 163950974Swpaul struct ifnet *ifp; 164050974Swpaul u_int32_t status; 164150974Swpaul 164250974Swpaul sc = arg; 1643147256Sbrooks ifp = sc->sis_ifp; 164450974Swpaul 1645139809Sphk if (sc->sis_stopped) /* Most likely shared interrupt */ 1646139809Sphk return; 1647139809Sphk 164886984Sluigi SIS_LOCK(sc); 164987902Sluigi#ifdef DEVICE_POLLING 1650139974Sru if (ifp->if_flags & IFF_POLLING) 1651139974Sru goto done; 1652139974Sru if ((ifp->if_capenable & IFCAP_POLLING) && 1653139974Sru ether_poll_register(sis_poll, ifp)) { /* ok, disable interrupts */ 165487902Sluigi CSR_WRITE_4(sc, SIS_IER, 0); 1655139974Sru goto done; 165687902Sluigi } 165787902Sluigi#endif /* DEVICE_POLLING */ 165887902Sluigi 165950974Swpaul /* Disable interrupts. */ 166050974Swpaul CSR_WRITE_4(sc, SIS_IER, 0); 166150974Swpaul 166250974Swpaul for (;;) { 1663139717Sphk SIS_LOCK_ASSERT(sc); 166450974Swpaul /* Reading the ISR register clears all interrupts. */ 166550974Swpaul status = CSR_READ_4(sc, SIS_ISR); 166650974Swpaul 166750974Swpaul if ((status & SIS_INTRS) == 0) 166850974Swpaul break; 166950974Swpaul 167086984Sluigi if (status & 167186984Sluigi (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | 167286984Sluigi SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) ) 167350974Swpaul sis_txeof(sc); 167450974Swpaul 167586984Sluigi if (status & (SIS_ISR_RX_DESC_OK|SIS_ISR_RX_OK|SIS_ISR_RX_IDLE)) 167650974Swpaul sis_rxeof(sc); 167750974Swpaul 167886984Sluigi if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW)) 167950974Swpaul sis_rxeoc(sc); 168050974Swpaul 168186984Sluigi if (status & (SIS_ISR_RX_IDLE)) 168286984Sluigi SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 168386984Sluigi 168450974Swpaul if (status & SIS_ISR_SYSERR) { 168550974Swpaul sis_reset(sc); 1686139715Sphk sis_initl(sc); 168750974Swpaul } 168850974Swpaul } 168950974Swpaul 169050974Swpaul /* Re-enable interrupts. */ 169150974Swpaul CSR_WRITE_4(sc, SIS_IER, 1); 169250974Swpaul 1693131455Smlaier if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1694139714Sphk sis_startl(ifp); 1695139809Sphk 1696139974Sru#ifdef DEVICE_POLLING 1697139974Srudone: 1698139974Sru#endif /* DEVICE_POLLING */ 169967087Swpaul SIS_UNLOCK(sc); 170050974Swpaul} 170150974Swpaul 170250974Swpaul/* 170350974Swpaul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 170450974Swpaul * pointers to the fragment pointers. 170550974Swpaul */ 1706102334Salfredstatic int 1707139740Sphksis_encap(struct sis_softc *sc, struct mbuf **m_head, uint32_t *txidx) 170850974Swpaul{ 170950974Swpaul struct sis_desc *f = NULL; 171050974Swpaul struct mbuf *m; 1711112808Ssilby int frag, cur, cnt = 0, chainlen = 0; 171250974Swpaul 171350974Swpaul /* 1714112808Ssilby * If there's no way we can send any packets, return now. 1715112808Ssilby */ 1716139690Sphk if (SIS_TX_LIST_CNT - sc->sis_tx_cnt < 2) 1717112808Ssilby return (ENOBUFS); 1718112808Ssilby 1719112808Ssilby /* 1720112808Ssilby * Count the number of frags in this chain to see if 1721112808Ssilby * we need to m_defrag. Since the descriptor list is shared 1722112808Ssilby * by all packets, we'll m_defrag long chains so that they 1723112808Ssilby * do not use up the entire list, even if they would fit. 1724112808Ssilby */ 1725112808Ssilby 1726121262Ssilby for (m = *m_head; m != NULL; m = m->m_next) 1727112808Ssilby chainlen++; 1728112808Ssilby 1729112808Ssilby if ((chainlen > SIS_TX_LIST_CNT / 4) || 1730139690Sphk ((SIS_TX_LIST_CNT - (chainlen + sc->sis_tx_cnt)) < 2)) { 1731121262Ssilby m = m_defrag(*m_head, M_DONTWAIT); 1732112808Ssilby if (m == NULL) 1733112808Ssilby return (ENOBUFS); 1734121262Ssilby *m_head = m; 1735112808Ssilby } 1736112808Ssilby 1737112808Ssilby /* 173850974Swpaul * Start packing the mbufs in this chain into 173950974Swpaul * the fragment pointers. Stop when we run out 174050974Swpaul * of fragments or hit the end of the mbuf chain. 174150974Swpaul */ 174250974Swpaul cur = frag = *txidx; 174350974Swpaul 1744121262Ssilby for (m = *m_head; m != NULL; m = m->m_next) { 174550974Swpaul if (m->m_len != 0) { 174651042Swpaul if ((SIS_TX_LIST_CNT - 1747139690Sphk (sc->sis_tx_cnt + cnt)) < 2) 174850974Swpaul return(ENOBUFS); 1749139690Sphk f = &sc->sis_tx_list[frag]; 175050974Swpaul f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; 175181713Swpaul bus_dmamap_create(sc->sis_tag, 0, &f->sis_map); 175281713Swpaul bus_dmamap_load(sc->sis_tag, f->sis_map, 175381713Swpaul mtod(m, void *), m->m_len, 175481713Swpaul sis_dma_map_desc_ptr, f, 0); 175581713Swpaul bus_dmamap_sync(sc->sis_tag, 175681713Swpaul f->sis_map, BUS_DMASYNC_PREREAD); 175750974Swpaul if (cnt != 0) 175850974Swpaul f->sis_ctl |= SIS_CMDSTS_OWN; 175950974Swpaul cur = frag; 176050974Swpaul SIS_INC(frag, SIS_TX_LIST_CNT); 176150974Swpaul cnt++; 176250974Swpaul } 176350974Swpaul } 176450974Swpaul 176550974Swpaul if (m != NULL) 176650974Swpaul return(ENOBUFS); 176750974Swpaul 1768139690Sphk sc->sis_tx_list[cur].sis_mbuf = *m_head; 1769139690Sphk sc->sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1770139690Sphk sc->sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1771139690Sphk sc->sis_tx_cnt += cnt; 177250974Swpaul *txidx = frag; 177350974Swpaul 177450974Swpaul return(0); 177550974Swpaul} 177650974Swpaul 177750974Swpaul/* 177850974Swpaul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 177950974Swpaul * to the mbuf data regions directly in the transmit lists. We also save a 178050974Swpaul * copy of the pointers since the transmit list fragment pointers are 178150974Swpaul * physical addresses. 178250974Swpaul */ 178350974Swpaul 1784102334Salfredstatic void 1785139717Sphksis_start(struct ifnet *ifp) 178650974Swpaul{ 178750974Swpaul struct sis_softc *sc; 1788139714Sphk 1789139714Sphk sc = ifp->if_softc; 1790139714Sphk SIS_LOCK(sc); 1791139714Sphk sis_startl(ifp); 1792139714Sphk SIS_UNLOCK(sc); 1793139714Sphk} 1794139714Sphk 1795139714Sphkstatic void 1796139714Sphksis_startl(struct ifnet *ifp) 1797139714Sphk{ 1798139714Sphk struct sis_softc *sc; 179950974Swpaul struct mbuf *m_head = NULL; 1800136269Smlaier u_int32_t idx, queued = 0; 180150974Swpaul 180250974Swpaul sc = ifp->if_softc; 180350974Swpaul 1804139714Sphk SIS_LOCK_ASSERT(sc); 1805139714Sphk 1806139714Sphk if (!sc->sis_link) 180764963Swpaul return; 180864963Swpaul 1809139690Sphk idx = sc->sis_tx_prod; 181050974Swpaul 1811148887Srwatson if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 181250974Swpaul return; 181350974Swpaul 1814139690Sphk while(sc->sis_tx_list[idx].sis_mbuf == NULL) { 1815131455Smlaier IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 181650974Swpaul if (m_head == NULL) 181750974Swpaul break; 181850974Swpaul 1819121262Ssilby if (sis_encap(sc, &m_head, &idx)) { 1820131455Smlaier IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1821148887Srwatson ifp->if_drv_flags |= IFF_DRV_OACTIVE; 182250974Swpaul break; 182350974Swpaul } 182450974Swpaul 1825136269Smlaier queued++; 1826136269Smlaier 182750974Swpaul /* 182850974Swpaul * If there's a BPF listener, bounce a copy of this frame 182950974Swpaul * to him. 183050974Swpaul */ 1831106936Ssam BPF_MTAP(ifp, m_head); 183251583Swpaul 183350974Swpaul } 183450974Swpaul 1835136269Smlaier if (queued) { 1836136269Smlaier /* Transmit */ 1837139690Sphk sc->sis_tx_prod = idx; 1838136269Smlaier SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 183950974Swpaul 1840136269Smlaier /* 1841136269Smlaier * Set a timeout in case the chip goes out to lunch. 1842136269Smlaier */ 1843136269Smlaier ifp->if_timer = 5; 1844136269Smlaier } 184550974Swpaul} 184650974Swpaul 1847102334Salfredstatic void 1848139715Sphksis_init(void *xsc) 184950974Swpaul{ 185050974Swpaul struct sis_softc *sc = xsc; 1851139715Sphk 1852139715Sphk SIS_LOCK(sc); 1853139717Sphk sis_initl(sc); 1854139715Sphk SIS_UNLOCK(sc); 1855139715Sphk} 1856139715Sphk 1857139715Sphkstatic void 1858139717Sphksis_initl(struct sis_softc *sc) 1859139715Sphk{ 1860147256Sbrooks struct ifnet *ifp = sc->sis_ifp; 186150974Swpaul struct mii_data *mii; 186250974Swpaul 1863139715Sphk SIS_LOCK_ASSERT(sc); 186450974Swpaul 186550974Swpaul /* 186650974Swpaul * Cancel pending I/O and free all RX/TX buffers. 186750974Swpaul */ 186850974Swpaul sis_stop(sc); 1869123833Sphk sc->sis_stopped = 0; 187050974Swpaul 1871119712Sphk#ifdef notyet 1872119712Sphk if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) { 1873119712Sphk /* 1874119712Sphk * Configure 400usec of interrupt holdoff. This is based 1875119712Sphk * on emperical tests on a Soekris 4801. 1876119712Sphk */ 1877119712Sphk CSR_WRITE_4(sc, NS_IHR, 0x100 | 4); 1878119712Sphk } 1879119712Sphk#endif 1880119712Sphk 188150974Swpaul mii = device_get_softc(sc->sis_miibus); 188250974Swpaul 188350974Swpaul /* Set MAC address */ 188462672Swpaul if (sc->sis_type == SIS_TYPE_83815) { 188562672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 188662672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1887147256Sbrooks ((u_int16_t *)IFP2ENADDR(sc->sis_ifp))[0]); 188862672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 188962672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1890147256Sbrooks ((u_int16_t *)IFP2ENADDR(sc->sis_ifp))[1]); 189162672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 189262672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1893147256Sbrooks ((u_int16_t *)IFP2ENADDR(sc->sis_ifp))[2]); 189462672Swpaul } else { 189562672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 189662672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1897147256Sbrooks ((u_int16_t *)IFP2ENADDR(sc->sis_ifp))[0]); 189862672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 189962672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1900147256Sbrooks ((u_int16_t *)IFP2ENADDR(sc->sis_ifp))[1]); 190162672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 190262672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1903147256Sbrooks ((u_int16_t *)IFP2ENADDR(sc->sis_ifp))[2]); 190462672Swpaul } 190550974Swpaul 1906139802Sphk /* Init circular TX/RX lists. */ 1907139802Sphk if (sis_ring_init(sc) != 0) { 190850974Swpaul printf("sis%d: initialization failed: no " 190950974Swpaul "memory for rx buffers\n", sc->sis_unit); 191050974Swpaul sis_stop(sc); 191150974Swpaul return; 191250974Swpaul } 191350974Swpaul 191450974Swpaul /* 1915139806Sphk * Short Cable Receive Errors (MP21.E) 1916139806Sphk * also: Page 78 of the DP83815 data sheet (september 2002 version) 1917123491Sphk * recommends the following register settings "for optimum 1918123491Sphk * performance." for rev 15C. The driver from NS also sets 1919123491Sphk * the PHY_CR register for later versions. 1920123491Sphk */ 1921139806Sphk if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr <= NS_SRR_15D) { 1922123491Sphk CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 1923123491Sphk CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 1924123491Sphk if (sc->sis_srr == NS_SRR_15C) { 1925123491Sphk /* set val for c2 */ 1926123491Sphk CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 1927123491Sphk /* load/kill c2 */ 1928123491Sphk CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 1929123491Sphk /* rais SD off, from 4 to c */ 1930123491Sphk CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 1931123491Sphk } 1932123491Sphk CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 1933123491Sphk } 1934123491Sphk 1935123491Sphk 1936123491Sphk /* 193762672Swpaul * For the NatSemi chip, we have to explicitly enable the 193862672Swpaul * reception of ARP frames, as well as turn on the 'perfect 193962672Swpaul * match' filter where we store the station address, otherwise 194062672Swpaul * we won't receive unicasts meant for this host. 194162672Swpaul */ 194262672Swpaul if (sc->sis_type == SIS_TYPE_83815) { 194362672Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 194462672Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 194562672Swpaul } 194662672Swpaul 194750974Swpaul /* If we want promiscuous mode, set the allframes bit. */ 194850974Swpaul if (ifp->if_flags & IFF_PROMISC) { 194950974Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 195050974Swpaul } else { 195150974Swpaul SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 195250974Swpaul } 195350974Swpaul 195450974Swpaul /* 195550974Swpaul * Set the capture broadcast bit to capture broadcast frames. 195650974Swpaul */ 195750974Swpaul if (ifp->if_flags & IFF_BROADCAST) { 195850974Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 195950974Swpaul } else { 196050974Swpaul SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 196150974Swpaul } 196250974Swpaul 196350974Swpaul /* 196450974Swpaul * Load the multicast filter. 196550974Swpaul */ 196662672Swpaul if (sc->sis_type == SIS_TYPE_83815) 196762672Swpaul sis_setmulti_ns(sc); 196862672Swpaul else 196962672Swpaul sis_setmulti_sis(sc); 197050974Swpaul 197150974Swpaul /* Turn the receive filter on */ 197250974Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 197350974Swpaul 197450974Swpaul /* 197550974Swpaul * Load the address of the RX and TX lists. 197650974Swpaul */ 1977139690Sphk CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_rx_paddr); 1978139690Sphk CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_tx_paddr); 197950974Swpaul 1980109059Smbr /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of 1981109059Smbr * the PCI bus. When this bit is set, the Max DMA Burst Size 1982109059Smbr * for TX/RX DMA should be no larger than 16 double words. 1983109059Smbr */ 1984109059Smbr if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) { 1985109059Smbr CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); 1986109059Smbr } else { 1987109059Smbr CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); 1988109059Smbr } 198964963Swpaul 199087390Sjhay /* Accept Long Packets for VLAN support */ 199187390Sjhay SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 199287390Sjhay 199350974Swpaul /* Set TX configuration */ 199464963Swpaul if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 199564963Swpaul CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 199664963Swpaul } else { 199764963Swpaul CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 199864963Swpaul } 199950974Swpaul 200064963Swpaul /* Set full/half duplex mode. */ 200164963Swpaul if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 200264963Swpaul SIS_SETBIT(sc, SIS_TX_CFG, 200364963Swpaul (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 200464963Swpaul SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 200564963Swpaul } else { 200664963Swpaul SIS_CLRBIT(sc, SIS_TX_CFG, 200764963Swpaul (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 200864963Swpaul SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 200964963Swpaul } 201064963Swpaul 2011139807Sphk if (sc->sis_type == SIS_TYPE_83816) { 2012139807Sphk /* 2013139807Sphk * MPII03.D: Half Duplex Excessive Collisions. 2014139807Sphk * Also page 49 in 83816 manual 2015139807Sphk */ 2016139807Sphk SIS_SETBIT(sc, SIS_TX_CFG, SIS_TXCFG_MPII03D); 2017139807Sphk } 2018139807Sphk 2019139808Sphk if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr < NS_SRR_16A && 2020119130Ssam IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 2021119130Ssam uint32_t reg; 2022119130Ssam 2023119130Ssam /* 2024139806Sphk * Short Cable Receive Errors (MP21.E) 2025119130Ssam */ 2026119130Ssam CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 2027139806Sphk reg = CSR_READ_4(sc, NS_PHY_DSPCFG) & 0xfff; 2028139806Sphk CSR_WRITE_4(sc, NS_PHY_DSPCFG, reg | 0x1000); 2029139806Sphk DELAY(100000); 2030139806Sphk reg = CSR_READ_4(sc, NS_PHY_TDATA) & 0xff; 2031139806Sphk if ((reg & 0x0080) == 0 || (reg > 0xd8 && reg <= 0xff)) { 2032139806Sphk device_printf(sc->sis_self, 2033139806Sphk "Applying short cable fix (reg=%x)\n", reg); 2034119130Ssam CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8); 2035139806Sphk reg = CSR_READ_4(sc, NS_PHY_DSPCFG); 2036139806Sphk SIS_SETBIT(sc, NS_PHY_DSPCFG, reg | 0x20); 2037119130Ssam } 2038119130Ssam CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 2039119130Ssam } 2040119130Ssam 204150974Swpaul /* 204250974Swpaul * Enable interrupts. 204350974Swpaul */ 204450974Swpaul CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 204587902Sluigi#ifdef DEVICE_POLLING 204687902Sluigi /* 204787902Sluigi * ... only enable interrupts if we are not polling, make sure 204887902Sluigi * they are off otherwise. 204987902Sluigi */ 2050102052Ssobomax if (ifp->if_flags & IFF_POLLING) 205187902Sluigi CSR_WRITE_4(sc, SIS_IER, 0); 205287902Sluigi else 205387902Sluigi#endif /* DEVICE_POLLING */ 205450974Swpaul CSR_WRITE_4(sc, SIS_IER, 1); 205550974Swpaul 205650974Swpaul /* Enable receiver and transmitter. */ 205750974Swpaul SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 205850974Swpaul SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 205950974Swpaul 206064963Swpaul#ifdef notdef 206150974Swpaul mii_mediachg(mii); 206264963Swpaul#endif 206350974Swpaul 2064148887Srwatson ifp->if_drv_flags |= IFF_DRV_RUNNING; 2065148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 206650974Swpaul 2067117858Scognet if (!sc->in_tick) 2068119785Ssam callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 206950974Swpaul} 207050974Swpaul 207150974Swpaul/* 207250974Swpaul * Set media options. 207350974Swpaul */ 2074102334Salfredstatic int 2075139740Sphksis_ifmedia_upd(struct ifnet *ifp) 207650974Swpaul{ 207750974Swpaul struct sis_softc *sc; 207864963Swpaul struct mii_data *mii; 207950974Swpaul 208050974Swpaul sc = ifp->if_softc; 208150974Swpaul 208264963Swpaul mii = device_get_softc(sc->sis_miibus); 208364963Swpaul sc->sis_link = 0; 208464963Swpaul if (mii->mii_instance) { 208564963Swpaul struct mii_softc *miisc; 208672012Sphk LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 208764963Swpaul mii_phy_reset(miisc); 208864963Swpaul } 208964963Swpaul mii_mediachg(mii); 209050974Swpaul 209150974Swpaul return(0); 209250974Swpaul} 209350974Swpaul 209450974Swpaul/* 209550974Swpaul * Report current media status. 209650974Swpaul */ 2097102334Salfredstatic void 2098139740Sphksis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 209950974Swpaul{ 210050974Swpaul struct sis_softc *sc; 210150974Swpaul struct mii_data *mii; 210250974Swpaul 210350974Swpaul sc = ifp->if_softc; 210450974Swpaul 210550974Swpaul mii = device_get_softc(sc->sis_miibus); 210650974Swpaul mii_pollstat(mii); 210750974Swpaul ifmr->ifm_active = mii->mii_media_active; 210850974Swpaul ifmr->ifm_status = mii->mii_media_status; 210950974Swpaul} 211050974Swpaul 2111102334Salfredstatic int 2112139740Sphksis_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 211350974Swpaul{ 211450974Swpaul struct sis_softc *sc = ifp->if_softc; 211550974Swpaul struct ifreq *ifr = (struct ifreq *) data; 211650974Swpaul struct mii_data *mii; 211767087Swpaul int error = 0; 211850974Swpaul 211950974Swpaul switch(command) { 212050974Swpaul case SIOCSIFFLAGS: 212150974Swpaul if (ifp->if_flags & IFF_UP) { 212250974Swpaul sis_init(sc); 2123148887Srwatson } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2124139741Sphk SIS_LOCK(sc); 2125139741Sphk sis_stop(sc); 2126139741Sphk SIS_UNLOCK(sc); 212750974Swpaul } 212850974Swpaul error = 0; 212950974Swpaul break; 213050974Swpaul case SIOCADDMULTI: 213150974Swpaul case SIOCDELMULTI: 213281713Swpaul SIS_LOCK(sc); 213362672Swpaul if (sc->sis_type == SIS_TYPE_83815) 213462672Swpaul sis_setmulti_ns(sc); 213562672Swpaul else 213662672Swpaul sis_setmulti_sis(sc); 213781713Swpaul SIS_UNLOCK(sc); 213850974Swpaul error = 0; 213950974Swpaul break; 214050974Swpaul case SIOCGIFMEDIA: 214150974Swpaul case SIOCSIFMEDIA: 214250974Swpaul mii = device_get_softc(sc->sis_miibus); 214381713Swpaul SIS_LOCK(sc); 214450974Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 214581713Swpaul SIS_UNLOCK(sc); 214650974Swpaul break; 2147128138Sru case SIOCSIFCAP: 2148129633Syar ifp->if_capenable &= ~IFCAP_POLLING; 2149129633Syar ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_POLLING; 2150128138Sru break; 215150974Swpaul default: 2152106936Ssam error = ether_ioctl(ifp, command, data); 215350974Swpaul break; 215450974Swpaul } 215550974Swpaul 215650974Swpaul return(error); 215750974Swpaul} 215850974Swpaul 2159102334Salfredstatic void 2160139740Sphksis_watchdog(struct ifnet *ifp) 216150974Swpaul{ 2162139797Sphk struct sis_softc *sc; 216350974Swpaul 216450974Swpaul sc = ifp->if_softc; 216550974Swpaul 216667087Swpaul SIS_LOCK(sc); 2167139797Sphk if (sc->sis_stopped) { 2168139797Sphk SIS_UNLOCK(sc); 2169139797Sphk return; 2170139797Sphk } 217167087Swpaul 217250974Swpaul ifp->if_oerrors++; 217350974Swpaul printf("sis%d: watchdog timeout\n", sc->sis_unit); 217450974Swpaul 217550974Swpaul sis_stop(sc); 217650974Swpaul sis_reset(sc); 2177139715Sphk sis_initl(sc); 217850974Swpaul 2179131455Smlaier if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2180139714Sphk sis_startl(ifp); 218150974Swpaul 218267087Swpaul SIS_UNLOCK(sc); 218350974Swpaul} 218450974Swpaul 218550974Swpaul/* 218650974Swpaul * Stop the adapter and free any mbufs allocated to the 218750974Swpaul * RX and TX lists. 218850974Swpaul */ 2189102334Salfredstatic void 2190139740Sphksis_stop(struct sis_softc *sc) 219150974Swpaul{ 2192139805Sphk int i; 2193139805Sphk struct ifnet *ifp; 2194139805Sphk struct sis_desc *dp; 219550974Swpaul 2196123833Sphk if (sc->sis_stopped) 2197123833Sphk return; 2198139717Sphk SIS_LOCK_ASSERT(sc); 2199147256Sbrooks ifp = sc->sis_ifp; 220050974Swpaul ifp->if_timer = 0; 220150974Swpaul 2202119785Ssam callout_stop(&sc->sis_stat_ch); 220387472Speter 2204148887Srwatson ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 220587902Sluigi#ifdef DEVICE_POLLING 220687902Sluigi ether_poll_deregister(ifp); 220787902Sluigi#endif 220850974Swpaul CSR_WRITE_4(sc, SIS_IER, 0); 220950974Swpaul CSR_WRITE_4(sc, SIS_IMR, 0); 2210139798Sphk CSR_READ_4(sc, SIS_ISR); /* clear any interrupts already pending */ 221150974Swpaul SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 221250974Swpaul DELAY(1000); 221350974Swpaul CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 221450974Swpaul CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 221550974Swpaul 221664963Swpaul sc->sis_link = 0; 221764963Swpaul 221850974Swpaul /* 221950974Swpaul * Free data in the RX lists. 222050974Swpaul */ 2221139805Sphk dp = &sc->sis_rx_list[0]; 2222139805Sphk for (i = 0; i < SIS_RX_LIST_CNT; i++, dp++) { 2223139805Sphk if (dp->sis_mbuf == NULL) 2224139805Sphk continue; 2225139805Sphk bus_dmamap_unload(sc->sis_tag, dp->sis_map); 2226139805Sphk bus_dmamap_destroy(sc->sis_tag, dp->sis_map); 2227139805Sphk m_freem(dp->sis_mbuf); 2228139805Sphk dp->sis_mbuf = NULL; 222950974Swpaul } 2230139805Sphk bzero(sc->sis_rx_list, SIS_RX_LIST_SZ); 223150974Swpaul 223250974Swpaul /* 223350974Swpaul * Free the TX list buffers. 223450974Swpaul */ 2235139805Sphk dp = &sc->sis_tx_list[0]; 2236139805Sphk for (i = 0; i < SIS_TX_LIST_CNT; i++, dp++) { 2237139805Sphk if (dp->sis_mbuf == NULL) 2238139805Sphk continue; 2239139805Sphk bus_dmamap_unload(sc->sis_tag, dp->sis_map); 2240139805Sphk bus_dmamap_destroy(sc->sis_tag, dp->sis_map); 2241139805Sphk m_freem(dp->sis_mbuf); 2242139805Sphk dp->sis_mbuf = NULL; 224350974Swpaul } 224450974Swpaul 2245139805Sphk bzero(sc->sis_tx_list, SIS_TX_LIST_SZ); 224650974Swpaul 2247123833Sphk sc->sis_stopped = 1; 224850974Swpaul} 224950974Swpaul 225050974Swpaul/* 225150974Swpaul * Stop all chip I/O so that the kernel's probe routines don't 225250974Swpaul * get confused by errant DMAs when rebooting. 225350974Swpaul */ 2254102334Salfredstatic void 2255139717Sphksis_shutdown(device_t dev) 225650974Swpaul{ 225750974Swpaul struct sis_softc *sc; 225850974Swpaul 225950974Swpaul sc = device_get_softc(dev); 226067087Swpaul SIS_LOCK(sc); 226150974Swpaul sis_reset(sc); 226250974Swpaul sis_stop(sc); 226367087Swpaul SIS_UNLOCK(sc); 226450974Swpaul} 2265139800Sphk 2266139800Sphkstatic device_method_t sis_methods[] = { 2267139800Sphk /* Device interface */ 2268139800Sphk DEVMETHOD(device_probe, sis_probe), 2269139800Sphk DEVMETHOD(device_attach, sis_attach), 2270139800Sphk DEVMETHOD(device_detach, sis_detach), 2271139800Sphk DEVMETHOD(device_shutdown, sis_shutdown), 2272139800Sphk 2273139800Sphk /* bus interface */ 2274139800Sphk DEVMETHOD(bus_print_child, bus_generic_print_child), 2275139800Sphk DEVMETHOD(bus_driver_added, bus_generic_driver_added), 2276139800Sphk 2277139800Sphk /* MII interface */ 2278139800Sphk DEVMETHOD(miibus_readreg, sis_miibus_readreg), 2279139800Sphk DEVMETHOD(miibus_writereg, sis_miibus_writereg), 2280139800Sphk DEVMETHOD(miibus_statchg, sis_miibus_statchg), 2281139800Sphk 2282139800Sphk { 0, 0 } 2283139800Sphk}; 2284139800Sphk 2285139800Sphkstatic driver_t sis_driver = { 2286139800Sphk "sis", 2287139800Sphk sis_methods, 2288139800Sphk sizeof(struct sis_softc) 2289139800Sphk}; 2290139800Sphk 2291139800Sphkstatic devclass_t sis_devclass; 2292139800Sphk 2293139800SphkDRIVER_MODULE(sis, pci, sis_driver, sis_devclass, 0, 0); 2294139800SphkDRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 2295