if_sis.c revision 139809
1303980Sngie/* 2303980Sngie * Copyright (c) 2005 Poul-Henning Kamp <phk@FreeBSD.org> 3303980Sngie * Copyright (c) 1997, 1998, 1999 4303980Sngie * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 5303980Sngie * 6303980Sngie * Redistribution and use in source and binary forms, with or without 7303980Sngie * modification, are permitted provided that the following conditions 8303980Sngie * are met: 9303980Sngie * 1. Redistributions of source code must retain the above copyright 10303980Sngie * notice, this list of conditions and the following disclaimer. 11303980Sngie * 2. Redistributions in binary form must reproduce the above copyright 12303980Sngie * notice, this list of conditions and the following disclaimer in the 13303980Sngie * documentation and/or other materials provided with the distribution. 14303980Sngie * 3. All advertising materials mentioning features or use of this software 15303980Sngie * must display the following acknowledgement: 16303980Sngie * This product includes software developed by Bill Paul. 17303980Sngie * 4. Neither the name of the author nor the names of any co-contributors 18303980Sngie * may be used to endorse or promote products derived from this software 19303980Sngie * without specific prior written permission. 20303980Sngie * 21303980Sngie * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22303980Sngie * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23303980Sngie * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24303980Sngie * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25303980Sngie * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26303980Sngie * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27303980Sngie * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28303980Sngie * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29303980Sngie * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30303980Sngie * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31303980Sngie * THE POSSIBILITY OF SUCH DAMAGE. 32303980Sngie */ 33303980Sngie 34303980Sngie#include <sys/cdefs.h> 35303980Sngie__FBSDID("$FreeBSD: head/sys/pci/if_sis.c 139809 2005-01-07 00:01:43Z phk $"); 36303980Sngie 37303980Sngie/* 38303980Sngie * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 39303980Sngie * available from http://www.sis.com.tw. 40303980Sngie * 41303980Sngie * This driver also supports the NatSemi DP83815. Datasheets are 42303980Sngie * available from http://www.national.com. 43303980Sngie * 44303980Sngie * Written by Bill Paul <wpaul@ee.columbia.edu> 45303980Sngie * Electrical Engineering Department 46303980Sngie * Columbia University, New York City 47303980Sngie */ 48303980Sngie/* 49303980Sngie * The SiS 900 is a fairly simple chip. It uses bus master DMA with 50303980Sngie * simple TX and RX descriptors of 3 longwords in size. The receiver 51303980Sngie * has a single perfect filter entry for the station address and a 52303980Sngie * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 53303980Sngie * transceiver while the 7016 requires an external transceiver chip. 54303980Sngie * Both chips offer the standard bit-bang MII interface as well as 55303980Sngie * an enchanced PHY interface which simplifies accessing MII registers. 56303980Sngie * 57303980Sngie * The only downside to this chipset is that RX descriptors must be 58303980Sngie * longword aligned. 59303980Sngie */ 60303980Sngie 61303980Sngie#include <sys/param.h> 62303980Sngie#include <sys/systm.h> 63303980Sngie#include <sys/sockio.h> 64303980Sngie#include <sys/mbuf.h> 65303980Sngie#include <sys/malloc.h> 66303980Sngie#include <sys/kernel.h> 67303980Sngie#include <sys/module.h> 68303980Sngie#include <sys/socket.h> 69303980Sngie#include <sys/sysctl.h> 70303980Sngie 71303980Sngie#include <net/if.h> 72303980Sngie#include <net/if_arp.h> 73303980Sngie#include <net/ethernet.h> 74303980Sngie#include <net/if_dl.h> 75303980Sngie#include <net/if_media.h> 76303980Sngie#include <net/if_types.h> 77303980Sngie#include <net/if_vlan_var.h> 78303980Sngie 79303980Sngie#include <net/bpf.h> 80303980Sngie 81303980Sngie#include <machine/bus_pio.h> 82303980Sngie#include <machine/bus_memio.h> 83303980Sngie#include <machine/bus.h> 84303980Sngie#include <machine/resource.h> 85303980Sngie#include <sys/bus.h> 86303980Sngie#include <sys/rman.h> 87303980Sngie 88303980Sngie#include <dev/mii/mii.h> 89303980Sngie#include <dev/mii/miivar.h> 90303980Sngie 91303980Sngie#include <dev/pci/pcireg.h> 92303980Sngie#include <dev/pci/pcivar.h> 93303980Sngie 94303980Sngie#define SIS_USEIOSPACE 95303980Sngie 96303980Sngie#include <pci/if_sisreg.h> 97303980Sngie 98303980SngieMODULE_DEPEND(sis, pci, 1, 1, 1); 99303980SngieMODULE_DEPEND(sis, ether, 1, 1, 1); 100303980SngieMODULE_DEPEND(sis, miibus, 1, 1, 1); 101303980Sngie 102303980Sngie/* "controller miibus0" required. See GENERIC if you get errors here. */ 103303980Sngie#include "miibus_if.h" 104303980Sngie 105303980Sngie/* 106303980Sngie * Various supported device vendors/types and their names. 107303980Sngie */ 108303980Sngiestatic struct sis_type sis_devs[] = { 109303980Sngie { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 110303980Sngie { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 111303980Sngie { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" }, 112303980Sngie { 0, 0, NULL } 113303980Sngie}; 114303980Sngie 115303980Sngiestatic int sis_detach(device_t); 116303980Sngiestatic void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *); 117303980Sngiestatic int sis_ifmedia_upd(struct ifnet *); 118303980Sngiestatic void sis_init(void *); 119303980Sngiestatic void sis_initl(struct sis_softc *); 120303980Sngiestatic void sis_intr(void *); 121303980Sngiestatic int sis_ioctl(struct ifnet *, u_long, caddr_t); 122303980Sngiestatic int sis_newbuf(struct sis_softc *, struct sis_desc *, struct mbuf *); 123303980Sngiestatic void sis_start(struct ifnet *); 124303980Sngiestatic void sis_startl(struct ifnet *); 125303980Sngiestatic void sis_stop(struct sis_softc *); 126303980Sngiestatic void sis_watchdog(struct ifnet *); 127303980Sngie 128303980Sngie#ifdef SIS_USEIOSPACE 129303980Sngie#define SIS_RES SYS_RES_IOPORT 130303980Sngie#define SIS_RID SIS_PCI_LOIO 131303980Sngie#else 132303980Sngie#define SIS_RES SYS_RES_MEMORY 133303980Sngie#define SIS_RID SIS_PCI_LOMEM 134303980Sngie#endif 135303980Sngie 136303980Sngie#define SIS_SETBIT(sc, reg, x) \ 137303980Sngie CSR_WRITE_4(sc, reg, \ 138303980Sngie CSR_READ_4(sc, reg) | (x)) 139303980Sngie 140303980Sngie#define SIS_CLRBIT(sc, reg, x) \ 141303980Sngie CSR_WRITE_4(sc, reg, \ 142303980Sngie CSR_READ_4(sc, reg) & ~(x)) 143303980Sngie 144303980Sngie#define SIO_SET(x) \ 145303980Sngie CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 146303980Sngie 147303980Sngie#define SIO_CLR(x) \ 148303980Sngie CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 149303980Sngie 150303980Sngiestatic void 151303980Sngiesis_dma_map_desc_next(void *arg, bus_dma_segment_t *segs, int nseg, int error) 152303980Sngie{ 153303980Sngie struct sis_desc *r; 154303980Sngie 155303980Sngie r = arg; 156303980Sngie r->sis_next = segs->ds_addr; 157303980Sngie} 158303980Sngie 159303980Sngiestatic void 160303980Sngiesis_dma_map_desc_ptr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 161303980Sngie{ 162303980Sngie struct sis_desc *r; 163303980Sngie 164303980Sngie r = arg; 165303980Sngie r->sis_ptr = segs->ds_addr; 166303980Sngie} 167303980Sngie 168303980Sngiestatic void 169303980Sngiesis_dma_map_ring(void *arg, bus_dma_segment_t *segs, int nseg, int error) 170303980Sngie{ 171303980Sngie u_int32_t *p; 172303980Sngie 173303980Sngie p = arg; 174303980Sngie *p = segs->ds_addr; 175303980Sngie} 176303980Sngie 177303980Sngie/* 178303980Sngie * Routine to reverse the bits in a word. Stolen almost 179303980Sngie * verbatim from /usr/games/fortune. 180303980Sngie */ 181303980Sngiestatic uint16_t 182303980Sngiesis_reverse(uint16_t n) 183303980Sngie{ 184303980Sngie n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 185303980Sngie n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 186303980Sngie n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 187303980Sngie n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 188303980Sngie 189303980Sngie return(n); 190303980Sngie} 191303980Sngie 192303980Sngiestatic void 193303980Sngiesis_delay(struct sis_softc *sc) 194303980Sngie{ 195303980Sngie int idx; 196303980Sngie 197303980Sngie for (idx = (300 / 33) + 1; idx > 0; idx--) 198303980Sngie CSR_READ_4(sc, SIS_CSR); 199303980Sngie} 200303980Sngie 201303980Sngiestatic void 202303980Sngiesis_eeprom_idle(struct sis_softc *sc) 203303980Sngie{ 204303980Sngie int i; 205303980Sngie 206303980Sngie SIO_SET(SIS_EECTL_CSEL); 207303980Sngie sis_delay(sc); 208303980Sngie SIO_SET(SIS_EECTL_CLK); 209303980Sngie sis_delay(sc); 210303980Sngie 211303980Sngie for (i = 0; i < 25; i++) { 212303980Sngie SIO_CLR(SIS_EECTL_CLK); 213303980Sngie sis_delay(sc); 214303980Sngie SIO_SET(SIS_EECTL_CLK); 215303980Sngie sis_delay(sc); 216303980Sngie } 217303980Sngie 218303980Sngie SIO_CLR(SIS_EECTL_CLK); 219303980Sngie sis_delay(sc); 220303980Sngie SIO_CLR(SIS_EECTL_CSEL); 221303980Sngie sis_delay(sc); 222303980Sngie CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 223303980Sngie} 224303980Sngie 225303980Sngie/* 226303980Sngie * Send a read command and address to the EEPROM, check for ACK. 227303980Sngie */ 228303980Sngiestatic void 229303980Sngiesis_eeprom_putbyte(struct sis_softc *sc, int addr) 230303980Sngie{ 231303980Sngie int d, i; 232303980Sngie 233303980Sngie d = addr | SIS_EECMD_READ; 234303980Sngie 235303980Sngie /* 236303980Sngie * Feed in each bit and stobe the clock. 237303980Sngie */ 238303980Sngie for (i = 0x400; i; i >>= 1) { 239303980Sngie if (d & i) { 240303980Sngie SIO_SET(SIS_EECTL_DIN); 241303980Sngie } else { 242303980Sngie SIO_CLR(SIS_EECTL_DIN); 243303980Sngie } 244303980Sngie sis_delay(sc); 245303980Sngie SIO_SET(SIS_EECTL_CLK); 246303980Sngie sis_delay(sc); 247303980Sngie SIO_CLR(SIS_EECTL_CLK); 248303980Sngie sis_delay(sc); 249303980Sngie } 250303980Sngie} 251303980Sngie 252/* 253 * Read a word of data stored in the EEPROM at address 'addr.' 254 */ 255static void 256sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest) 257{ 258 int i; 259 u_int16_t word = 0; 260 261 /* Force EEPROM to idle state. */ 262 sis_eeprom_idle(sc); 263 264 /* Enter EEPROM access mode. */ 265 sis_delay(sc); 266 SIO_CLR(SIS_EECTL_CLK); 267 sis_delay(sc); 268 SIO_SET(SIS_EECTL_CSEL); 269 sis_delay(sc); 270 271 /* 272 * Send address of word we want to read. 273 */ 274 sis_eeprom_putbyte(sc, addr); 275 276 /* 277 * Start reading bits from EEPROM. 278 */ 279 for (i = 0x8000; i; i >>= 1) { 280 SIO_SET(SIS_EECTL_CLK); 281 sis_delay(sc); 282 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 283 word |= i; 284 sis_delay(sc); 285 SIO_CLR(SIS_EECTL_CLK); 286 sis_delay(sc); 287 } 288 289 /* Turn off EEPROM access mode. */ 290 sis_eeprom_idle(sc); 291 292 *dest = word; 293} 294 295/* 296 * Read a sequence of words from the EEPROM. 297 */ 298static void 299sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap) 300{ 301 int i; 302 u_int16_t word = 0, *ptr; 303 304 for (i = 0; i < cnt; i++) { 305 sis_eeprom_getword(sc, off + i, &word); 306 ptr = (u_int16_t *)(dest + (i * 2)); 307 if (swap) 308 *ptr = ntohs(word); 309 else 310 *ptr = word; 311 } 312} 313 314#ifdef __i386__ 315static device_t 316sis_find_bridge(device_t dev) 317{ 318 devclass_t pci_devclass; 319 device_t *pci_devices; 320 int pci_count = 0; 321 device_t *pci_children; 322 int pci_childcount = 0; 323 device_t *busp, *childp; 324 device_t child = NULL; 325 int i, j; 326 327 if ((pci_devclass = devclass_find("pci")) == NULL) 328 return(NULL); 329 330 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 331 332 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 333 pci_childcount = 0; 334 device_get_children(*busp, &pci_children, &pci_childcount); 335 for (j = 0, childp = pci_children; 336 j < pci_childcount; j++, childp++) { 337 if (pci_get_vendor(*childp) == SIS_VENDORID && 338 pci_get_device(*childp) == 0x0008) { 339 child = *childp; 340 goto done; 341 } 342 } 343 } 344 345done: 346 free(pci_devices, M_TEMP); 347 free(pci_children, M_TEMP); 348 return(child); 349} 350 351static void 352sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off, int cnt) 353{ 354 device_t bridge; 355 u_int8_t reg; 356 int i; 357 bus_space_tag_t btag; 358 359 bridge = sis_find_bridge(dev); 360 if (bridge == NULL) 361 return; 362 reg = pci_read_config(bridge, 0x48, 1); 363 pci_write_config(bridge, 0x48, reg|0x40, 1); 364 365 /* XXX */ 366 btag = I386_BUS_SPACE_IO; 367 368 for (i = 0; i < cnt; i++) { 369 bus_space_write_1(btag, 0x0, 0x70, i + off); 370 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 371 } 372 373 pci_write_config(bridge, 0x48, reg & ~0x40, 1); 374 return; 375} 376 377static void 378sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest) 379{ 380 u_int32_t filtsave, csrsave; 381 382 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 383 csrsave = CSR_READ_4(sc, SIS_CSR); 384 385 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 386 CSR_WRITE_4(sc, SIS_CSR, 0); 387 388 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 389 390 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 391 ((u_int16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 392 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 393 ((u_int16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 394 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 395 ((u_int16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 396 397 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 398 CSR_WRITE_4(sc, SIS_CSR, csrsave); 399 return; 400} 401#endif 402 403/* 404 * Sync the PHYs by setting data bit and strobing the clock 32 times. 405 */ 406static void 407sis_mii_sync(struct sis_softc *sc) 408{ 409 int i; 410 411 SIO_SET(SIS_MII_DIR|SIS_MII_DATA); 412 413 for (i = 0; i < 32; i++) { 414 SIO_SET(SIS_MII_CLK); 415 DELAY(1); 416 SIO_CLR(SIS_MII_CLK); 417 DELAY(1); 418 } 419} 420 421/* 422 * Clock a series of bits through the MII. 423 */ 424static void 425sis_mii_send(struct sis_softc *sc, uint32_t bits, int cnt) 426{ 427 int i; 428 429 SIO_CLR(SIS_MII_CLK); 430 431 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 432 if (bits & i) { 433 SIO_SET(SIS_MII_DATA); 434 } else { 435 SIO_CLR(SIS_MII_DATA); 436 } 437 DELAY(1); 438 SIO_CLR(SIS_MII_CLK); 439 DELAY(1); 440 SIO_SET(SIS_MII_CLK); 441 } 442} 443 444/* 445 * Read an PHY register through the MII. 446 */ 447static int 448sis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame) 449{ 450 int i, ack, s; 451 452 s = splimp(); 453 454 /* 455 * Set up frame for RX. 456 */ 457 frame->mii_stdelim = SIS_MII_STARTDELIM; 458 frame->mii_opcode = SIS_MII_READOP; 459 frame->mii_turnaround = 0; 460 frame->mii_data = 0; 461 462 /* 463 * Turn on data xmit. 464 */ 465 SIO_SET(SIS_MII_DIR); 466 467 sis_mii_sync(sc); 468 469 /* 470 * Send command/address info. 471 */ 472 sis_mii_send(sc, frame->mii_stdelim, 2); 473 sis_mii_send(sc, frame->mii_opcode, 2); 474 sis_mii_send(sc, frame->mii_phyaddr, 5); 475 sis_mii_send(sc, frame->mii_regaddr, 5); 476 477 /* Idle bit */ 478 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA)); 479 DELAY(1); 480 SIO_SET(SIS_MII_CLK); 481 DELAY(1); 482 483 /* Turn off xmit. */ 484 SIO_CLR(SIS_MII_DIR); 485 486 /* Check for ack */ 487 SIO_CLR(SIS_MII_CLK); 488 DELAY(1); 489 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA; 490 SIO_SET(SIS_MII_CLK); 491 DELAY(1); 492 493 /* 494 * Now try reading data bits. If the ack failed, we still 495 * need to clock through 16 cycles to keep the PHY(s) in sync. 496 */ 497 if (ack) { 498 for(i = 0; i < 16; i++) { 499 SIO_CLR(SIS_MII_CLK); 500 DELAY(1); 501 SIO_SET(SIS_MII_CLK); 502 DELAY(1); 503 } 504 goto fail; 505 } 506 507 for (i = 0x8000; i; i >>= 1) { 508 SIO_CLR(SIS_MII_CLK); 509 DELAY(1); 510 if (!ack) { 511 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA) 512 frame->mii_data |= i; 513 DELAY(1); 514 } 515 SIO_SET(SIS_MII_CLK); 516 DELAY(1); 517 } 518 519fail: 520 521 SIO_CLR(SIS_MII_CLK); 522 DELAY(1); 523 SIO_SET(SIS_MII_CLK); 524 DELAY(1); 525 526 splx(s); 527 528 if (ack) 529 return(1); 530 return(0); 531} 532 533/* 534 * Write to a PHY register through the MII. 535 */ 536static int 537sis_mii_writereg(struct sis_softc *sc, struct sis_mii_frame *frame) 538{ 539 int s; 540 541 s = splimp(); 542 /* 543 * Set up frame for TX. 544 */ 545 546 frame->mii_stdelim = SIS_MII_STARTDELIM; 547 frame->mii_opcode = SIS_MII_WRITEOP; 548 frame->mii_turnaround = SIS_MII_TURNAROUND; 549 550 /* 551 * Turn on data output. 552 */ 553 SIO_SET(SIS_MII_DIR); 554 555 sis_mii_sync(sc); 556 557 sis_mii_send(sc, frame->mii_stdelim, 2); 558 sis_mii_send(sc, frame->mii_opcode, 2); 559 sis_mii_send(sc, frame->mii_phyaddr, 5); 560 sis_mii_send(sc, frame->mii_regaddr, 5); 561 sis_mii_send(sc, frame->mii_turnaround, 2); 562 sis_mii_send(sc, frame->mii_data, 16); 563 564 /* Idle bit. */ 565 SIO_SET(SIS_MII_CLK); 566 DELAY(1); 567 SIO_CLR(SIS_MII_CLK); 568 DELAY(1); 569 570 /* 571 * Turn off xmit. 572 */ 573 SIO_CLR(SIS_MII_DIR); 574 575 splx(s); 576 577 return(0); 578} 579 580static int 581sis_miibus_readreg(device_t dev, int phy, int reg) 582{ 583 struct sis_softc *sc; 584 struct sis_mii_frame frame; 585 586 sc = device_get_softc(dev); 587 588 if (sc->sis_type == SIS_TYPE_83815) { 589 if (phy != 0) 590 return(0); 591 /* 592 * The NatSemi chip can take a while after 593 * a reset to come ready, during which the BMSR 594 * returns a value of 0. This is *never* supposed 595 * to happen: some of the BMSR bits are meant to 596 * be hardwired in the on position, and this can 597 * confuse the miibus code a bit during the probe 598 * and attach phase. So we make an effort to check 599 * for this condition and wait for it to clear. 600 */ 601 if (!CSR_READ_4(sc, NS_BMSR)) 602 DELAY(1000); 603 return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 604 } 605 606 /* 607 * Chipsets < SIS_635 seem not to be able to read/write 608 * through mdio. Use the enhanced PHY access register 609 * again for them. 610 */ 611 if (sc->sis_type == SIS_TYPE_900 && 612 sc->sis_rev < SIS_REV_635) { 613 int i, val = 0; 614 615 if (phy != 0) 616 return(0); 617 618 CSR_WRITE_4(sc, SIS_PHYCTL, 619 (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 620 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 621 622 for (i = 0; i < SIS_TIMEOUT; i++) { 623 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 624 break; 625 } 626 627 if (i == SIS_TIMEOUT) { 628 printf("sis%d: PHY failed to come ready\n", 629 sc->sis_unit); 630 return(0); 631 } 632 633 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 634 635 if (val == 0xFFFF) 636 return(0); 637 638 return(val); 639 } else { 640 bzero((char *)&frame, sizeof(frame)); 641 642 frame.mii_phyaddr = phy; 643 frame.mii_regaddr = reg; 644 sis_mii_readreg(sc, &frame); 645 646 return(frame.mii_data); 647 } 648} 649 650static int 651sis_miibus_writereg(device_t dev, int phy, int reg, int data) 652{ 653 struct sis_softc *sc; 654 struct sis_mii_frame frame; 655 656 sc = device_get_softc(dev); 657 658 if (sc->sis_type == SIS_TYPE_83815) { 659 if (phy != 0) 660 return(0); 661 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 662 return(0); 663 } 664 665 /* 666 * Chipsets < SIS_635 seem not to be able to read/write 667 * through mdio. Use the enhanced PHY access register 668 * again for them. 669 */ 670 if (sc->sis_type == SIS_TYPE_900 && 671 sc->sis_rev < SIS_REV_635) { 672 int i; 673 674 if (phy != 0) 675 return(0); 676 677 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 678 (reg << 6) | SIS_PHYOP_WRITE); 679 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 680 681 for (i = 0; i < SIS_TIMEOUT; i++) { 682 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 683 break; 684 } 685 686 if (i == SIS_TIMEOUT) 687 printf("sis%d: PHY failed to come ready\n", 688 sc->sis_unit); 689 } else { 690 bzero((char *)&frame, sizeof(frame)); 691 692 frame.mii_phyaddr = phy; 693 frame.mii_regaddr = reg; 694 frame.mii_data = data; 695 sis_mii_writereg(sc, &frame); 696 } 697 return(0); 698} 699 700static void 701sis_miibus_statchg(device_t dev) 702{ 703 struct sis_softc *sc; 704 705 sc = device_get_softc(dev); 706 SIS_LOCK_ASSERT(sc); 707 sis_initl(sc); 708} 709 710static uint32_t 711sis_mchash(struct sis_softc *sc, const uint8_t *addr) 712{ 713 uint32_t crc; 714 715 /* Compute CRC for the address value. */ 716 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 717 718 /* 719 * return the filter bit position 720 * 721 * The NatSemi chip has a 512-bit filter, which is 722 * different than the SiS, so we special-case it. 723 */ 724 if (sc->sis_type == SIS_TYPE_83815) 725 return (crc >> 23); 726 else if (sc->sis_rev >= SIS_REV_635 || 727 sc->sis_rev == SIS_REV_900B) 728 return (crc >> 24); 729 else 730 return (crc >> 25); 731} 732 733static void 734sis_setmulti_ns(struct sis_softc *sc) 735{ 736 struct ifnet *ifp; 737 struct ifmultiaddr *ifma; 738 u_int32_t h = 0, i, filtsave; 739 int bit, index; 740 741 ifp = &sc->arpcom.ac_if; 742 743 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 744 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 745 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 746 return; 747 } 748 749 /* 750 * We have to explicitly enable the multicast hash table 751 * on the NatSemi chip if we want to use it, which we do. 752 */ 753 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 754 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 755 756 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 757 758 /* first, zot all the existing hash bits */ 759 for (i = 0; i < 32; i++) { 760 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 761 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 762 } 763 764 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 765 if (ifma->ifma_addr->sa_family != AF_LINK) 766 continue; 767 h = sis_mchash(sc, 768 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 769 index = h >> 3; 770 bit = h & 0x1F; 771 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 772 if (bit > 0xF) 773 bit -= 0x10; 774 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 775 } 776 777 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 778 779 return; 780} 781 782static void 783sis_setmulti_sis(struct sis_softc *sc) 784{ 785 struct ifnet *ifp; 786 struct ifmultiaddr *ifma; 787 u_int32_t h, i, n, ctl; 788 u_int16_t hashes[16]; 789 790 ifp = &sc->arpcom.ac_if; 791 792 /* hash table size */ 793 if (sc->sis_rev >= SIS_REV_635 || 794 sc->sis_rev == SIS_REV_900B) 795 n = 16; 796 else 797 n = 8; 798 799 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE; 800 801 if (ifp->if_flags & IFF_BROADCAST) 802 ctl |= SIS_RXFILTCTL_BROAD; 803 804 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 805 ctl |= SIS_RXFILTCTL_ALLMULTI; 806 if (ifp->if_flags & IFF_PROMISC) 807 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS; 808 for (i = 0; i < n; i++) 809 hashes[i] = ~0; 810 } else { 811 for (i = 0; i < n; i++) 812 hashes[i] = 0; 813 i = 0; 814 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 815 if (ifma->ifma_addr->sa_family != AF_LINK) 816 continue; 817 h = sis_mchash(sc, 818 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 819 hashes[h >> 4] |= 1 << (h & 0xf); 820 i++; 821 } 822 if (i > n) { 823 ctl |= SIS_RXFILTCTL_ALLMULTI; 824 for (i = 0; i < n; i++) 825 hashes[i] = ~0; 826 } 827 } 828 829 for (i = 0; i < n; i++) { 830 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); 831 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); 832 } 833 834 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl); 835} 836 837static void 838sis_reset(struct sis_softc *sc) 839{ 840 int i; 841 842 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 843 844 for (i = 0; i < SIS_TIMEOUT; i++) { 845 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 846 break; 847 } 848 849 if (i == SIS_TIMEOUT) 850 printf("sis%d: reset never completed\n", sc->sis_unit); 851 852 /* Wait a little while for the chip to get its brains in order. */ 853 DELAY(1000); 854 855 /* 856 * If this is a NetSemi chip, make sure to clear 857 * PME mode. 858 */ 859 if (sc->sis_type == SIS_TYPE_83815) { 860 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 861 CSR_WRITE_4(sc, NS_CLKRUN, 0); 862 } 863 864 return; 865} 866 867/* 868 * Probe for an SiS chip. Check the PCI vendor and device 869 * IDs against our list and return a device name if we find a match. 870 */ 871static int 872sis_probe(device_t dev) 873{ 874 struct sis_type *t; 875 876 t = sis_devs; 877 878 while(t->sis_name != NULL) { 879 if ((pci_get_vendor(dev) == t->sis_vid) && 880 (pci_get_device(dev) == t->sis_did)) { 881 device_set_desc(dev, t->sis_name); 882 return(0); 883 } 884 t++; 885 } 886 887 return(ENXIO); 888} 889 890/* 891 * Attach the interface. Allocate softc structures, do ifmedia 892 * setup and ethernet/BPF attach. 893 */ 894static int 895sis_attach(device_t dev) 896{ 897 u_char eaddr[ETHER_ADDR_LEN]; 898 struct sis_softc *sc; 899 struct ifnet *ifp; 900 int unit, error = 0, rid, waittime = 0; 901 902 waittime = 0; 903 sc = device_get_softc(dev); 904 unit = device_get_unit(dev); 905 906 sc->sis_self = dev; 907 908 mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 909 MTX_DEF | MTX_RECURSE); 910 911 if (pci_get_device(dev) == SIS_DEVICEID_900) 912 sc->sis_type = SIS_TYPE_900; 913 if (pci_get_device(dev) == SIS_DEVICEID_7016) 914 sc->sis_type = SIS_TYPE_7016; 915 if (pci_get_vendor(dev) == NS_VENDORID) 916 sc->sis_type = SIS_TYPE_83815; 917 918 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 919 /* 920 * Map control/status registers. 921 */ 922 pci_enable_busmaster(dev); 923 924 rid = SIS_RID; 925 sc->sis_res = bus_alloc_resource_any(dev, SIS_RES, &rid, RF_ACTIVE); 926 927 if (sc->sis_res == NULL) { 928 printf("sis%d: couldn't map ports/memory\n", unit); 929 error = ENXIO; 930 goto fail; 931 } 932 933 sc->sis_btag = rman_get_bustag(sc->sis_res); 934 sc->sis_bhandle = rman_get_bushandle(sc->sis_res); 935 936 /* Allocate interrupt */ 937 rid = 0; 938 sc->sis_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 939 RF_SHAREABLE | RF_ACTIVE); 940 941 if (sc->sis_irq == NULL) { 942 printf("sis%d: couldn't map interrupt\n", unit); 943 error = ENXIO; 944 goto fail; 945 } 946 947 /* Reset the adapter. */ 948 sis_reset(sc); 949 950 if (sc->sis_type == SIS_TYPE_900 && 951 (sc->sis_rev == SIS_REV_635 || 952 sc->sis_rev == SIS_REV_900B)) { 953 SIO_SET(SIS_CFG_RND_CNT); 954 SIO_SET(SIS_CFG_PERR_DETECT); 955 } 956 957 /* 958 * Get station address from the EEPROM. 959 */ 960 switch (pci_get_vendor(dev)) { 961 case NS_VENDORID: 962 sc->sis_srr = CSR_READ_4(sc, NS_SRR); 963 964 /* We can't update the device description, so spew */ 965 if (sc->sis_srr == NS_SRR_15C) 966 device_printf(dev, "Silicon Revision: DP83815C\n"); 967 else if (sc->sis_srr == NS_SRR_15D) 968 device_printf(dev, "Silicon Revision: DP83815D\n"); 969 else if (sc->sis_srr == NS_SRR_16A) 970 device_printf(dev, "Silicon Revision: DP83816A\n"); 971 else 972 device_printf(dev, "Silicon Revision %x\n", sc->sis_srr); 973 974 /* 975 * Reading the MAC address out of the EEPROM on 976 * the NatSemi chip takes a bit more work than 977 * you'd expect. The address spans 4 16-bit words, 978 * with the first word containing only a single bit. 979 * You have to shift everything over one bit to 980 * get it aligned properly. Also, the bits are 981 * stored backwards (the LSB is really the MSB, 982 * and so on) so you have to reverse them in order 983 * to get the MAC address into the form we want. 984 * Why? Who the hell knows. 985 */ 986 { 987 u_int16_t tmp[4]; 988 989 sis_read_eeprom(sc, (caddr_t)&tmp, 990 NS_EE_NODEADDR, 4, 0); 991 992 /* Shift everything over one bit. */ 993 tmp[3] = tmp[3] >> 1; 994 tmp[3] |= tmp[2] << 15; 995 tmp[2] = tmp[2] >> 1; 996 tmp[2] |= tmp[1] << 15; 997 tmp[1] = tmp[1] >> 1; 998 tmp[1] |= tmp[0] << 15; 999 1000 /* Now reverse all the bits. */ 1001 tmp[3] = sis_reverse(tmp[3]); 1002 tmp[2] = sis_reverse(tmp[2]); 1003 tmp[1] = sis_reverse(tmp[1]); 1004 1005 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); 1006 } 1007 break; 1008 case SIS_VENDORID: 1009 default: 1010#ifdef __i386__ 1011 /* 1012 * If this is a SiS 630E chipset with an embedded 1013 * SiS 900 controller, we have to read the MAC address 1014 * from the APC CMOS RAM. Our method for doing this 1015 * is very ugly since we have to reach out and grab 1016 * ahold of hardware for which we cannot properly 1017 * allocate resources. This code is only compiled on 1018 * the i386 architecture since the SiS 630E chipset 1019 * is for x86 motherboards only. Note that there are 1020 * a lot of magic numbers in this hack. These are 1021 * taken from SiS's Linux driver. I'd like to replace 1022 * them with proper symbolic definitions, but that 1023 * requires some datasheets that I don't have access 1024 * to at the moment. 1025 */ 1026 if (sc->sis_rev == SIS_REV_630S || 1027 sc->sis_rev == SIS_REV_630E || 1028 sc->sis_rev == SIS_REV_630EA1) 1029 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 1030 1031 else if (sc->sis_rev == SIS_REV_635 || 1032 sc->sis_rev == SIS_REV_630ET) 1033 sis_read_mac(sc, dev, (caddr_t)&eaddr); 1034 else if (sc->sis_rev == SIS_REV_96x) { 1035 /* Allow to read EEPROM from LAN. It is shared 1036 * between a 1394 controller and the NIC and each 1037 * time we access it, we need to set SIS_EECMD_REQ. 1038 */ 1039 SIO_SET(SIS_EECMD_REQ); 1040 for (waittime = 0; waittime < SIS_TIMEOUT; 1041 waittime++) { 1042 /* Force EEPROM to idle state. */ 1043 sis_eeprom_idle(sc); 1044 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { 1045 sis_read_eeprom(sc, (caddr_t)&eaddr, 1046 SIS_EE_NODEADDR, 3, 0); 1047 break; 1048 } 1049 DELAY(1); 1050 } 1051 /* 1052 * Set SIS_EECTL_CLK to high, so a other master 1053 * can operate on the i2c bus. 1054 */ 1055 SIO_SET(SIS_EECTL_CLK); 1056 /* Refuse EEPROM access by LAN */ 1057 SIO_SET(SIS_EECMD_DONE); 1058 } else 1059#endif 1060 sis_read_eeprom(sc, (caddr_t)&eaddr, 1061 SIS_EE_NODEADDR, 3, 0); 1062 break; 1063 } 1064 1065 sc->sis_unit = unit; 1066 if (debug_mpsafenet) 1067 callout_init(&sc->sis_stat_ch, CALLOUT_MPSAFE); 1068 else 1069 callout_init(&sc->sis_stat_ch, 0); 1070 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1071 1072 /* 1073 * Allocate the parent bus DMA tag appropriate for PCI. 1074 */ 1075#define SIS_NSEG_NEW 32 1076 error = bus_dma_tag_create(NULL, /* parent */ 1077 1, 0, /* alignment, boundary */ 1078 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1079 BUS_SPACE_MAXADDR, /* highaddr */ 1080 NULL, NULL, /* filter, filterarg */ 1081 MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */ 1082 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1083 BUS_DMA_ALLOCNOW, /* flags */ 1084 NULL, NULL, /* lockfunc, lockarg */ 1085 &sc->sis_parent_tag); 1086 if (error) 1087 goto fail; 1088 1089 /* 1090 * Now allocate a tag for the DMA descriptor lists and a chunk 1091 * of DMA-able memory based on the tag. Also obtain the physical 1092 * addresses of the RX and TX ring, which we'll need later. 1093 * All of our lists are allocated as a contiguous block 1094 * of memory. 1095 */ 1096 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1097 1, 0, /* alignment, boundary */ 1098 BUS_SPACE_MAXADDR, /* lowaddr */ 1099 BUS_SPACE_MAXADDR, /* highaddr */ 1100 NULL, NULL, /* filter, filterarg */ 1101 SIS_RX_LIST_SZ, 1, /* maxsize,nsegments */ 1102 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1103 0, /* flags */ 1104 busdma_lock_mutex, /* lockfunc */ 1105 &Giant, /* lockarg */ 1106 &sc->sis_rx_tag); 1107 if (error) 1108 goto fail; 1109 1110 error = bus_dmamem_alloc(sc->sis_rx_tag, 1111 (void **)&sc->sis_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1112 &sc->sis_rx_dmamap); 1113 1114 if (error) { 1115 printf("sis%d: no memory for rx list buffers!\n", unit); 1116 bus_dma_tag_destroy(sc->sis_rx_tag); 1117 sc->sis_rx_tag = NULL; 1118 goto fail; 1119 } 1120 1121 error = bus_dmamap_load(sc->sis_rx_tag, 1122 sc->sis_rx_dmamap, &(sc->sis_rx_list[0]), 1123 sizeof(struct sis_desc), sis_dma_map_ring, 1124 &sc->sis_rx_paddr, 0); 1125 1126 if (error) { 1127 printf("sis%d: cannot get address of the rx ring!\n", unit); 1128 bus_dmamem_free(sc->sis_rx_tag, 1129 sc->sis_rx_list, sc->sis_rx_dmamap); 1130 bus_dma_tag_destroy(sc->sis_rx_tag); 1131 sc->sis_rx_tag = NULL; 1132 goto fail; 1133 } 1134 1135 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1136 1, 0, /* alignment, boundary */ 1137 BUS_SPACE_MAXADDR, /* lowaddr */ 1138 BUS_SPACE_MAXADDR, /* highaddr */ 1139 NULL, NULL, /* filter, filterarg */ 1140 SIS_TX_LIST_SZ, 1, /* maxsize,nsegments */ 1141 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1142 0, /* flags */ 1143 busdma_lock_mutex, /* lockfunc */ 1144 &Giant, /* lockarg */ 1145 &sc->sis_tx_tag); 1146 if (error) 1147 goto fail; 1148 1149 error = bus_dmamem_alloc(sc->sis_tx_tag, 1150 (void **)&sc->sis_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1151 &sc->sis_tx_dmamap); 1152 1153 if (error) { 1154 printf("sis%d: no memory for tx list buffers!\n", unit); 1155 bus_dma_tag_destroy(sc->sis_tx_tag); 1156 sc->sis_tx_tag = NULL; 1157 goto fail; 1158 } 1159 1160 error = bus_dmamap_load(sc->sis_tx_tag, 1161 sc->sis_tx_dmamap, &(sc->sis_tx_list[0]), 1162 sizeof(struct sis_desc), sis_dma_map_ring, 1163 &sc->sis_tx_paddr, 0); 1164 1165 if (error) { 1166 printf("sis%d: cannot get address of the tx ring!\n", unit); 1167 bus_dmamem_free(sc->sis_tx_tag, 1168 sc->sis_tx_list, sc->sis_tx_dmamap); 1169 bus_dma_tag_destroy(sc->sis_tx_tag); 1170 sc->sis_tx_tag = NULL; 1171 goto fail; 1172 } 1173 1174 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1175 1, 0, /* alignment, boundary */ 1176 BUS_SPACE_MAXADDR, /* lowaddr */ 1177 BUS_SPACE_MAXADDR, /* highaddr */ 1178 NULL, NULL, /* filter, filterarg */ 1179 MCLBYTES, 1, /* maxsize,nsegments */ 1180 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1181 0, /* flags */ 1182 busdma_lock_mutex, /* lockfunc */ 1183 &Giant, /* lockarg */ 1184 &sc->sis_tag); 1185 if (error) 1186 goto fail; 1187 1188 /* 1189 * Obtain the physical addresses of the RX and TX 1190 * rings which we'll need later in the init routine. 1191 */ 1192 1193 ifp = &sc->arpcom.ac_if; 1194 ifp->if_softc = sc; 1195 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1196 ifp->if_mtu = ETHERMTU; 1197 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1198 ifp->if_ioctl = sis_ioctl; 1199 ifp->if_start = sis_start; 1200 ifp->if_watchdog = sis_watchdog; 1201 ifp->if_init = sis_init; 1202 ifp->if_baudrate = 10000000; 1203 IFQ_SET_MAXLEN(&ifp->if_snd, SIS_TX_LIST_CNT - 1); 1204 ifp->if_snd.ifq_drv_maxlen = SIS_TX_LIST_CNT - 1; 1205 IFQ_SET_READY(&ifp->if_snd); 1206 1207 /* 1208 * Do MII setup. 1209 */ 1210 if (mii_phy_probe(dev, &sc->sis_miibus, 1211 sis_ifmedia_upd, sis_ifmedia_sts)) { 1212 printf("sis%d: MII without any PHY!\n", sc->sis_unit); 1213 error = ENXIO; 1214 goto fail; 1215 } 1216 1217 /* 1218 * Call MI attach routine. 1219 */ 1220 ether_ifattach(ifp, eaddr); 1221 1222 /* 1223 * Tell the upper layer(s) we support long frames. 1224 */ 1225 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1226 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1227 1228#ifdef DEVICE_POLLING 1229 ifp->if_capabilities |= IFCAP_POLLING; 1230#endif 1231 ifp->if_capenable = ifp->if_capabilities; 1232 1233 /* Hook interrupt last to avoid having to lock softc */ 1234 error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET | INTR_MPSAFE, 1235 sis_intr, sc, &sc->sis_intrhand); 1236 1237 if (error) { 1238 printf("sis%d: couldn't set up irq\n", unit); 1239 ether_ifdetach(ifp); 1240 goto fail; 1241 } 1242 1243fail: 1244 if (error) 1245 sis_detach(dev); 1246 1247 return(error); 1248} 1249 1250/* 1251 * Shutdown hardware and free up resources. This can be called any 1252 * time after the mutex has been initialized. It is called in both 1253 * the error case in attach and the normal detach case so it needs 1254 * to be careful about only freeing resources that have actually been 1255 * allocated. 1256 */ 1257static int 1258sis_detach(device_t dev) 1259{ 1260 struct sis_softc *sc; 1261 struct ifnet *ifp; 1262 1263 sc = device_get_softc(dev); 1264 KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized")); 1265 SIS_LOCK(sc); 1266 ifp = &sc->arpcom.ac_if; 1267 1268 /* These should only be active if attach succeeded. */ 1269 if (device_is_attached(dev)) { 1270 sis_reset(sc); 1271 sis_stop(sc); 1272 ether_ifdetach(ifp); 1273 } 1274 if (sc->sis_miibus) 1275 device_delete_child(dev, sc->sis_miibus); 1276 bus_generic_detach(dev); 1277 1278 if (sc->sis_intrhand) 1279 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1280 if (sc->sis_irq) 1281 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1282 if (sc->sis_res) 1283 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1284 1285 if (sc->sis_rx_tag) { 1286 bus_dmamap_unload(sc->sis_rx_tag, 1287 sc->sis_rx_dmamap); 1288 bus_dmamem_free(sc->sis_rx_tag, 1289 sc->sis_rx_list, sc->sis_rx_dmamap); 1290 bus_dma_tag_destroy(sc->sis_rx_tag); 1291 } 1292 if (sc->sis_tx_tag) { 1293 bus_dmamap_unload(sc->sis_tx_tag, 1294 sc->sis_tx_dmamap); 1295 bus_dmamem_free(sc->sis_tx_tag, 1296 sc->sis_tx_list, sc->sis_tx_dmamap); 1297 bus_dma_tag_destroy(sc->sis_tx_tag); 1298 } 1299 if (sc->sis_parent_tag) 1300 bus_dma_tag_destroy(sc->sis_parent_tag); 1301 if (sc->sis_tag) 1302 bus_dma_tag_destroy(sc->sis_tag); 1303 1304 SIS_UNLOCK(sc); 1305 mtx_destroy(&sc->sis_mtx); 1306 1307 return(0); 1308} 1309 1310/* 1311 * Initialize the TX and RX descriptors and allocate mbufs for them. Note that 1312 * we arrange the descriptors in a closed ring, so that the last descriptor 1313 * points back to the first. 1314 */ 1315static int 1316sis_ring_init(struct sis_softc *sc) 1317{ 1318 int i, error; 1319 struct sis_desc *dp; 1320 1321 dp = &sc->sis_tx_list[0]; 1322 for (i = 0; i < SIS_TX_LIST_CNT; i++, dp++) { 1323 if (i == (SIS_TX_LIST_CNT - 1)) 1324 dp->sis_nextdesc = &sc->sis_tx_list[0]; 1325 else 1326 dp->sis_nextdesc = dp + 1; 1327 bus_dmamap_load(sc->sis_tx_tag, 1328 sc->sis_tx_dmamap, 1329 dp->sis_nextdesc, sizeof(struct sis_desc), 1330 sis_dma_map_desc_next, dp, 0); 1331 dp->sis_mbuf = NULL; 1332 dp->sis_ptr = 0; 1333 dp->sis_ctl = 0; 1334 } 1335 1336 sc->sis_tx_prod = sc->sis_tx_cons = sc->sis_tx_cnt = 0; 1337 1338 bus_dmamap_sync(sc->sis_tx_tag, 1339 sc->sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 1340 1341 dp = &sc->sis_rx_list[0]; 1342 for (i = 0; i < SIS_RX_LIST_CNT; i++, dp++) { 1343 error = sis_newbuf(sc, dp, NULL); 1344 if (error) 1345 return(error); 1346 if (i == (SIS_RX_LIST_CNT - 1)) 1347 dp->sis_nextdesc = &sc->sis_rx_list[0]; 1348 else 1349 dp->sis_nextdesc = dp + 1; 1350 bus_dmamap_load(sc->sis_rx_tag, 1351 sc->sis_rx_dmamap, 1352 dp->sis_nextdesc, sizeof(struct sis_desc), 1353 sis_dma_map_desc_next, dp, 0); 1354 } 1355 1356 bus_dmamap_sync(sc->sis_rx_tag, 1357 sc->sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 1358 1359 sc->sis_rx_pdsc = &sc->sis_rx_list[0]; 1360 1361 return(0); 1362} 1363 1364/* 1365 * Initialize an RX descriptor and attach an MBUF cluster. 1366 */ 1367static int 1368sis_newbuf(struct sis_softc *sc, struct sis_desc *c, struct mbuf *m) 1369{ 1370 1371 if (c == NULL) 1372 return(EINVAL); 1373 1374 if (m == NULL) { 1375 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1376 if (m == NULL) 1377 return(ENOBUFS); 1378 } else 1379 m->m_data = m->m_ext.ext_buf; 1380 1381 c->sis_mbuf = m; 1382 c->sis_ctl = SIS_RXLEN; 1383 1384 bus_dmamap_create(sc->sis_tag, 0, &c->sis_map); 1385 bus_dmamap_load(sc->sis_tag, c->sis_map, 1386 mtod(m, void *), MCLBYTES, 1387 sis_dma_map_desc_ptr, c, 0); 1388 bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREWRITE); 1389 1390 return(0); 1391} 1392 1393/* 1394 * A frame has been uploaded: pass the resulting mbuf chain up to 1395 * the higher level protocols. 1396 */ 1397static void 1398sis_rxeof(struct sis_softc *sc) 1399{ 1400 struct mbuf *m; 1401 struct ifnet *ifp; 1402 struct sis_desc *cur_rx; 1403 int total_len = 0; 1404 u_int32_t rxstat; 1405 1406 SIS_LOCK_ASSERT(sc); 1407 1408 ifp = &sc->arpcom.ac_if; 1409 1410 for(cur_rx = sc->sis_rx_pdsc; SIS_OWNDESC(cur_rx); 1411 cur_rx = cur_rx->sis_nextdesc) { 1412 1413#ifdef DEVICE_POLLING 1414 if (ifp->if_flags & IFF_POLLING) { 1415 if (sc->rxcycles <= 0) 1416 break; 1417 sc->rxcycles--; 1418 } 1419#endif /* DEVICE_POLLING */ 1420 rxstat = cur_rx->sis_rxstat; 1421 bus_dmamap_sync(sc->sis_tag, 1422 cur_rx->sis_map, BUS_DMASYNC_POSTWRITE); 1423 bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map); 1424 bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map); 1425 m = cur_rx->sis_mbuf; 1426 cur_rx->sis_mbuf = NULL; 1427 total_len = SIS_RXBYTES(cur_rx); 1428 1429 /* 1430 * If an error occurs, update stats, clear the 1431 * status word and leave the mbuf cluster in place: 1432 * it should simply get re-used next time this descriptor 1433 * comes up in the ring. 1434 */ 1435 if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 1436 ifp->if_ierrors++; 1437 if (rxstat & SIS_RXSTAT_COLL) 1438 ifp->if_collisions++; 1439 sis_newbuf(sc, cur_rx, m); 1440 continue; 1441 } 1442 1443 /* No errors; receive the packet. */ 1444#ifdef __i386__ 1445 /* 1446 * On the x86 we do not have alignment problems, so try to 1447 * allocate a new buffer for the receive ring, and pass up 1448 * the one where the packet is already, saving the expensive 1449 * copy done in m_devget(). 1450 * If we are on an architecture with alignment problems, or 1451 * if the allocation fails, then use m_devget and leave the 1452 * existing buffer in the receive ring. 1453 */ 1454 if (sis_newbuf(sc, cur_rx, NULL) == 0) 1455 m->m_pkthdr.len = m->m_len = total_len; 1456 else 1457#endif 1458 { 1459 struct mbuf *m0; 1460 m0 = m_devget(mtod(m, char *), total_len, 1461 ETHER_ALIGN, ifp, NULL); 1462 sis_newbuf(sc, cur_rx, m); 1463 if (m0 == NULL) { 1464 ifp->if_ierrors++; 1465 continue; 1466 } 1467 m = m0; 1468 } 1469 1470 ifp->if_ipackets++; 1471 m->m_pkthdr.rcvif = ifp; 1472 1473 SIS_UNLOCK(sc); 1474 (*ifp->if_input)(ifp, m); 1475 SIS_LOCK(sc); 1476 } 1477 1478 sc->sis_rx_pdsc = cur_rx; 1479} 1480 1481static void 1482sis_rxeoc(struct sis_softc *sc) 1483{ 1484 1485 SIS_LOCK_ASSERT(sc); 1486 sis_rxeof(sc); 1487 sis_initl(sc); 1488} 1489 1490/* 1491 * A frame was downloaded to the chip. It's safe for us to clean up 1492 * the list buffers. 1493 */ 1494 1495static void 1496sis_txeof(struct sis_softc *sc) 1497{ 1498 struct ifnet *ifp; 1499 u_int32_t idx; 1500 1501 SIS_LOCK_ASSERT(sc); 1502 ifp = &sc->arpcom.ac_if; 1503 1504 /* 1505 * Go through our tx list and free mbufs for those 1506 * frames that have been transmitted. 1507 */ 1508 for (idx = sc->sis_tx_cons; sc->sis_tx_cnt > 0; 1509 sc->sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) { 1510 struct sis_desc *cur_tx = &sc->sis_tx_list[idx]; 1511 1512 if (SIS_OWNDESC(cur_tx)) 1513 break; 1514 1515 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) 1516 continue; 1517 1518 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 1519 ifp->if_oerrors++; 1520 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 1521 ifp->if_collisions++; 1522 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 1523 ifp->if_collisions++; 1524 } 1525 1526 ifp->if_collisions += 1527 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 1528 1529 ifp->if_opackets++; 1530 if (cur_tx->sis_mbuf != NULL) { 1531 m_freem(cur_tx->sis_mbuf); 1532 cur_tx->sis_mbuf = NULL; 1533 bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map); 1534 bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map); 1535 } 1536 } 1537 1538 if (idx != sc->sis_tx_cons) { 1539 /* we freed up some buffers */ 1540 sc->sis_tx_cons = idx; 1541 ifp->if_flags &= ~IFF_OACTIVE; 1542 } 1543 1544 ifp->if_timer = (sc->sis_tx_cnt == 0) ? 0 : 5; 1545 1546 return; 1547} 1548 1549static void 1550sis_tick(void *xsc) 1551{ 1552 struct sis_softc *sc; 1553 struct mii_data *mii; 1554 struct ifnet *ifp; 1555 1556 sc = xsc; 1557 SIS_LOCK(sc); 1558 sc->in_tick = 1; 1559 ifp = &sc->arpcom.ac_if; 1560 1561 mii = device_get_softc(sc->sis_miibus); 1562 mii_tick(mii); 1563 1564 if (!sc->sis_link && mii->mii_media_status & IFM_ACTIVE && 1565 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1566 sc->sis_link++; 1567 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1568 sis_startl(ifp); 1569 } 1570 1571 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 1572 sc->in_tick = 0; 1573 SIS_UNLOCK(sc); 1574} 1575 1576#ifdef DEVICE_POLLING 1577static poll_handler_t sis_poll; 1578 1579static void 1580sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1581{ 1582 struct sis_softc *sc = ifp->if_softc; 1583 1584 SIS_LOCK(sc); 1585 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1586 ether_poll_deregister(ifp); 1587 cmd = POLL_DEREGISTER; 1588 } 1589 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1590 CSR_WRITE_4(sc, SIS_IER, 1); 1591 goto done; 1592 } 1593 1594 /* 1595 * On the sis, reading the status register also clears it. 1596 * So before returning to intr mode we must make sure that all 1597 * possible pending sources of interrupts have been served. 1598 * In practice this means run to completion the *eof routines, 1599 * and then call the interrupt routine 1600 */ 1601 sc->rxcycles = count; 1602 sis_rxeof(sc); 1603 sis_txeof(sc); 1604 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1605 sis_startl(ifp); 1606 1607 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1608 u_int32_t status; 1609 1610 /* Reading the ISR register clears all interrupts. */ 1611 status = CSR_READ_4(sc, SIS_ISR); 1612 1613 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 1614 sis_rxeoc(sc); 1615 1616 if (status & (SIS_ISR_RX_IDLE)) 1617 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1618 1619 if (status & SIS_ISR_SYSERR) { 1620 sis_reset(sc); 1621 sis_initl(sc); 1622 } 1623 } 1624done: 1625 SIS_UNLOCK(sc); 1626} 1627#endif /* DEVICE_POLLING */ 1628 1629static void 1630sis_intr(void *arg) 1631{ 1632 struct sis_softc *sc; 1633 struct ifnet *ifp; 1634 u_int32_t status; 1635 1636 sc = arg; 1637 ifp = &sc->arpcom.ac_if; 1638 1639 if (sc->sis_stopped) /* Most likely shared interrupt */ 1640 return; 1641 1642 SIS_LOCK(sc); 1643#ifdef DEVICE_POLLING 1644 if (ifp->if_flags & IFF_POLLING) 1645 goto done; 1646 if ((ifp->if_capenable & IFCAP_POLLING) && 1647 ether_poll_register(sis_poll, ifp)) { /* ok, disable interrupts */ 1648 CSR_WRITE_4(sc, SIS_IER, 0); 1649 goto done; 1650 } 1651#endif /* DEVICE_POLLING */ 1652 1653 /* Disable interrupts. */ 1654 CSR_WRITE_4(sc, SIS_IER, 0); 1655 1656 for (;;) { 1657 SIS_LOCK_ASSERT(sc); 1658 /* Reading the ISR register clears all interrupts. */ 1659 status = CSR_READ_4(sc, SIS_ISR); 1660 1661 if ((status & SIS_INTRS) == 0) 1662 break; 1663 1664 if (status & 1665 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | 1666 SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) ) 1667 sis_txeof(sc); 1668 1669 if (status & (SIS_ISR_RX_DESC_OK|SIS_ISR_RX_OK|SIS_ISR_RX_IDLE)) 1670 sis_rxeof(sc); 1671 1672 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW)) 1673 sis_rxeoc(sc); 1674 1675 if (status & (SIS_ISR_RX_IDLE)) 1676 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1677 1678 if (status & SIS_ISR_SYSERR) { 1679 sis_reset(sc); 1680 sis_initl(sc); 1681 } 1682 } 1683 1684 /* Re-enable interrupts. */ 1685 CSR_WRITE_4(sc, SIS_IER, 1); 1686 1687 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1688 sis_startl(ifp); 1689 1690 SIS_UNLOCK(sc); 1691} 1692 1693/* 1694 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1695 * pointers to the fragment pointers. 1696 */ 1697static int 1698sis_encap(struct sis_softc *sc, struct mbuf **m_head, uint32_t *txidx) 1699{ 1700 struct sis_desc *f = NULL; 1701 struct mbuf *m; 1702 int frag, cur, cnt = 0, chainlen = 0; 1703 1704 /* 1705 * If there's no way we can send any packets, return now. 1706 */ 1707 if (SIS_TX_LIST_CNT - sc->sis_tx_cnt < 2) 1708 return (ENOBUFS); 1709 1710 /* 1711 * Count the number of frags in this chain to see if 1712 * we need to m_defrag. Since the descriptor list is shared 1713 * by all packets, we'll m_defrag long chains so that they 1714 * do not use up the entire list, even if they would fit. 1715 */ 1716 1717 for (m = *m_head; m != NULL; m = m->m_next) 1718 chainlen++; 1719 1720 if ((chainlen > SIS_TX_LIST_CNT / 4) || 1721 ((SIS_TX_LIST_CNT - (chainlen + sc->sis_tx_cnt)) < 2)) { 1722 m = m_defrag(*m_head, M_DONTWAIT); 1723 if (m == NULL) 1724 return (ENOBUFS); 1725 *m_head = m; 1726 } 1727 1728 /* 1729 * Start packing the mbufs in this chain into 1730 * the fragment pointers. Stop when we run out 1731 * of fragments or hit the end of the mbuf chain. 1732 */ 1733 cur = frag = *txidx; 1734 1735 for (m = *m_head; m != NULL; m = m->m_next) { 1736 if (m->m_len != 0) { 1737 if ((SIS_TX_LIST_CNT - 1738 (sc->sis_tx_cnt + cnt)) < 2) 1739 return(ENOBUFS); 1740 f = &sc->sis_tx_list[frag]; 1741 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; 1742 bus_dmamap_create(sc->sis_tag, 0, &f->sis_map); 1743 bus_dmamap_load(sc->sis_tag, f->sis_map, 1744 mtod(m, void *), m->m_len, 1745 sis_dma_map_desc_ptr, f, 0); 1746 bus_dmamap_sync(sc->sis_tag, 1747 f->sis_map, BUS_DMASYNC_PREREAD); 1748 if (cnt != 0) 1749 f->sis_ctl |= SIS_CMDSTS_OWN; 1750 cur = frag; 1751 SIS_INC(frag, SIS_TX_LIST_CNT); 1752 cnt++; 1753 } 1754 } 1755 1756 if (m != NULL) 1757 return(ENOBUFS); 1758 1759 sc->sis_tx_list[cur].sis_mbuf = *m_head; 1760 sc->sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1761 sc->sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1762 sc->sis_tx_cnt += cnt; 1763 *txidx = frag; 1764 1765 return(0); 1766} 1767 1768/* 1769 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1770 * to the mbuf data regions directly in the transmit lists. We also save a 1771 * copy of the pointers since the transmit list fragment pointers are 1772 * physical addresses. 1773 */ 1774 1775static void 1776sis_start(struct ifnet *ifp) 1777{ 1778 struct sis_softc *sc; 1779 1780 sc = ifp->if_softc; 1781 SIS_LOCK(sc); 1782 sis_startl(ifp); 1783 SIS_UNLOCK(sc); 1784} 1785 1786static void 1787sis_startl(struct ifnet *ifp) 1788{ 1789 struct sis_softc *sc; 1790 struct mbuf *m_head = NULL; 1791 u_int32_t idx, queued = 0; 1792 1793 sc = ifp->if_softc; 1794 1795 SIS_LOCK_ASSERT(sc); 1796 1797 if (!sc->sis_link) 1798 return; 1799 1800 idx = sc->sis_tx_prod; 1801 1802 if (ifp->if_flags & IFF_OACTIVE) 1803 return; 1804 1805 while(sc->sis_tx_list[idx].sis_mbuf == NULL) { 1806 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1807 if (m_head == NULL) 1808 break; 1809 1810 if (sis_encap(sc, &m_head, &idx)) { 1811 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1812 ifp->if_flags |= IFF_OACTIVE; 1813 break; 1814 } 1815 1816 queued++; 1817 1818 /* 1819 * If there's a BPF listener, bounce a copy of this frame 1820 * to him. 1821 */ 1822 BPF_MTAP(ifp, m_head); 1823 1824 } 1825 1826 if (queued) { 1827 /* Transmit */ 1828 sc->sis_tx_prod = idx; 1829 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 1830 1831 /* 1832 * Set a timeout in case the chip goes out to lunch. 1833 */ 1834 ifp->if_timer = 5; 1835 } 1836} 1837 1838static void 1839sis_init(void *xsc) 1840{ 1841 struct sis_softc *sc = xsc; 1842 1843 SIS_LOCK(sc); 1844 sis_initl(sc); 1845 SIS_UNLOCK(sc); 1846} 1847 1848static void 1849sis_initl(struct sis_softc *sc) 1850{ 1851 struct ifnet *ifp = &sc->arpcom.ac_if; 1852 struct mii_data *mii; 1853 1854 SIS_LOCK_ASSERT(sc); 1855 1856 /* 1857 * Cancel pending I/O and free all RX/TX buffers. 1858 */ 1859 sis_stop(sc); 1860 sc->sis_stopped = 0; 1861 1862#ifdef notyet 1863 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) { 1864 /* 1865 * Configure 400usec of interrupt holdoff. This is based 1866 * on emperical tests on a Soekris 4801. 1867 */ 1868 CSR_WRITE_4(sc, NS_IHR, 0x100 | 4); 1869 } 1870#endif 1871 1872 mii = device_get_softc(sc->sis_miibus); 1873 1874 /* Set MAC address */ 1875 if (sc->sis_type == SIS_TYPE_83815) { 1876 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 1877 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1878 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1879 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 1880 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1881 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1882 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 1883 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1884 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1885 } else { 1886 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 1887 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1888 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1889 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 1890 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1891 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1892 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 1893 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1894 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1895 } 1896 1897 /* Init circular TX/RX lists. */ 1898 if (sis_ring_init(sc) != 0) { 1899 printf("sis%d: initialization failed: no " 1900 "memory for rx buffers\n", sc->sis_unit); 1901 sis_stop(sc); 1902 return; 1903 } 1904 1905 /* 1906 * Short Cable Receive Errors (MP21.E) 1907 * also: Page 78 of the DP83815 data sheet (september 2002 version) 1908 * recommends the following register settings "for optimum 1909 * performance." for rev 15C. The driver from NS also sets 1910 * the PHY_CR register for later versions. 1911 */ 1912 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr <= NS_SRR_15D) { 1913 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 1914 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 1915 if (sc->sis_srr == NS_SRR_15C) { 1916 /* set val for c2 */ 1917 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 1918 /* load/kill c2 */ 1919 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 1920 /* rais SD off, from 4 to c */ 1921 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 1922 } 1923 CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 1924 } 1925 1926 1927 /* 1928 * For the NatSemi chip, we have to explicitly enable the 1929 * reception of ARP frames, as well as turn on the 'perfect 1930 * match' filter where we store the station address, otherwise 1931 * we won't receive unicasts meant for this host. 1932 */ 1933 if (sc->sis_type == SIS_TYPE_83815) { 1934 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 1935 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 1936 } 1937 1938 /* If we want promiscuous mode, set the allframes bit. */ 1939 if (ifp->if_flags & IFF_PROMISC) { 1940 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1941 } else { 1942 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1943 } 1944 1945 /* 1946 * Set the capture broadcast bit to capture broadcast frames. 1947 */ 1948 if (ifp->if_flags & IFF_BROADCAST) { 1949 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1950 } else { 1951 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1952 } 1953 1954 /* 1955 * Load the multicast filter. 1956 */ 1957 if (sc->sis_type == SIS_TYPE_83815) 1958 sis_setmulti_ns(sc); 1959 else 1960 sis_setmulti_sis(sc); 1961 1962 /* Turn the receive filter on */ 1963 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 1964 1965 /* 1966 * Load the address of the RX and TX lists. 1967 */ 1968 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_rx_paddr); 1969 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_tx_paddr); 1970 1971 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of 1972 * the PCI bus. When this bit is set, the Max DMA Burst Size 1973 * for TX/RX DMA should be no larger than 16 double words. 1974 */ 1975 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) { 1976 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); 1977 } else { 1978 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); 1979 } 1980 1981 /* Accept Long Packets for VLAN support */ 1982 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 1983 1984 /* Set TX configuration */ 1985 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 1986 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 1987 } else { 1988 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 1989 } 1990 1991 /* Set full/half duplex mode. */ 1992 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1993 SIS_SETBIT(sc, SIS_TX_CFG, 1994 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 1995 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 1996 } else { 1997 SIS_CLRBIT(sc, SIS_TX_CFG, 1998 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 1999 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 2000 } 2001 2002 if (sc->sis_type == SIS_TYPE_83816) { 2003 /* 2004 * MPII03.D: Half Duplex Excessive Collisions. 2005 * Also page 49 in 83816 manual 2006 */ 2007 SIS_SETBIT(sc, SIS_TX_CFG, SIS_TXCFG_MPII03D); 2008 } 2009 2010 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr < NS_SRR_16A && 2011 IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 2012 uint32_t reg; 2013 2014 /* 2015 * Short Cable Receive Errors (MP21.E) 2016 */ 2017 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 2018 reg = CSR_READ_4(sc, NS_PHY_DSPCFG) & 0xfff; 2019 CSR_WRITE_4(sc, NS_PHY_DSPCFG, reg | 0x1000); 2020 DELAY(100000); 2021 reg = CSR_READ_4(sc, NS_PHY_TDATA) & 0xff; 2022 if ((reg & 0x0080) == 0 || (reg > 0xd8 && reg <= 0xff)) { 2023 device_printf(sc->sis_self, 2024 "Applying short cable fix (reg=%x)\n", reg); 2025 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8); 2026 reg = CSR_READ_4(sc, NS_PHY_DSPCFG); 2027 SIS_SETBIT(sc, NS_PHY_DSPCFG, reg | 0x20); 2028 } 2029 CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 2030 } 2031 2032 /* 2033 * Enable interrupts. 2034 */ 2035 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 2036#ifdef DEVICE_POLLING 2037 /* 2038 * ... only enable interrupts if we are not polling, make sure 2039 * they are off otherwise. 2040 */ 2041 if (ifp->if_flags & IFF_POLLING) 2042 CSR_WRITE_4(sc, SIS_IER, 0); 2043 else 2044#endif /* DEVICE_POLLING */ 2045 CSR_WRITE_4(sc, SIS_IER, 1); 2046 2047 /* Enable receiver and transmitter. */ 2048 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2049 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 2050 2051#ifdef notdef 2052 mii_mediachg(mii); 2053#endif 2054 2055 ifp->if_flags |= IFF_RUNNING; 2056 ifp->if_flags &= ~IFF_OACTIVE; 2057 2058 if (!sc->in_tick) 2059 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 2060} 2061 2062/* 2063 * Set media options. 2064 */ 2065static int 2066sis_ifmedia_upd(struct ifnet *ifp) 2067{ 2068 struct sis_softc *sc; 2069 struct mii_data *mii; 2070 2071 sc = ifp->if_softc; 2072 2073 mii = device_get_softc(sc->sis_miibus); 2074 sc->sis_link = 0; 2075 if (mii->mii_instance) { 2076 struct mii_softc *miisc; 2077 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2078 mii_phy_reset(miisc); 2079 } 2080 mii_mediachg(mii); 2081 2082 return(0); 2083} 2084 2085/* 2086 * Report current media status. 2087 */ 2088static void 2089sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2090{ 2091 struct sis_softc *sc; 2092 struct mii_data *mii; 2093 2094 sc = ifp->if_softc; 2095 2096 mii = device_get_softc(sc->sis_miibus); 2097 mii_pollstat(mii); 2098 ifmr->ifm_active = mii->mii_media_active; 2099 ifmr->ifm_status = mii->mii_media_status; 2100} 2101 2102static int 2103sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2104{ 2105 struct sis_softc *sc = ifp->if_softc; 2106 struct ifreq *ifr = (struct ifreq *) data; 2107 struct mii_data *mii; 2108 int error = 0; 2109 2110 switch(command) { 2111 case SIOCSIFFLAGS: 2112 if (ifp->if_flags & IFF_UP) { 2113 sis_init(sc); 2114 } else if (ifp->if_flags & IFF_RUNNING) { 2115 SIS_LOCK(sc); 2116 sis_stop(sc); 2117 SIS_UNLOCK(sc); 2118 } 2119 error = 0; 2120 break; 2121 case SIOCADDMULTI: 2122 case SIOCDELMULTI: 2123 SIS_LOCK(sc); 2124 if (sc->sis_type == SIS_TYPE_83815) 2125 sis_setmulti_ns(sc); 2126 else 2127 sis_setmulti_sis(sc); 2128 SIS_UNLOCK(sc); 2129 error = 0; 2130 break; 2131 case SIOCGIFMEDIA: 2132 case SIOCSIFMEDIA: 2133 mii = device_get_softc(sc->sis_miibus); 2134 SIS_LOCK(sc); 2135 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2136 SIS_UNLOCK(sc); 2137 break; 2138 case SIOCSIFCAP: 2139 ifp->if_capenable &= ~IFCAP_POLLING; 2140 ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_POLLING; 2141 break; 2142 default: 2143 error = ether_ioctl(ifp, command, data); 2144 break; 2145 } 2146 2147 return(error); 2148} 2149 2150static void 2151sis_watchdog(struct ifnet *ifp) 2152{ 2153 struct sis_softc *sc; 2154 2155 sc = ifp->if_softc; 2156 2157 SIS_LOCK(sc); 2158 if (sc->sis_stopped) { 2159 SIS_UNLOCK(sc); 2160 return; 2161 } 2162 2163 ifp->if_oerrors++; 2164 printf("sis%d: watchdog timeout\n", sc->sis_unit); 2165 2166 sis_stop(sc); 2167 sis_reset(sc); 2168 sis_initl(sc); 2169 2170 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2171 sis_startl(ifp); 2172 2173 SIS_UNLOCK(sc); 2174} 2175 2176/* 2177 * Stop the adapter and free any mbufs allocated to the 2178 * RX and TX lists. 2179 */ 2180static void 2181sis_stop(struct sis_softc *sc) 2182{ 2183 int i; 2184 struct ifnet *ifp; 2185 struct sis_desc *dp; 2186 2187 if (sc->sis_stopped) 2188 return; 2189 SIS_LOCK_ASSERT(sc); 2190 ifp = &sc->arpcom.ac_if; 2191 ifp->if_timer = 0; 2192 2193 callout_stop(&sc->sis_stat_ch); 2194 2195 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2196#ifdef DEVICE_POLLING 2197 ether_poll_deregister(ifp); 2198#endif 2199 CSR_WRITE_4(sc, SIS_IER, 0); 2200 CSR_WRITE_4(sc, SIS_IMR, 0); 2201 CSR_READ_4(sc, SIS_ISR); /* clear any interrupts already pending */ 2202 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2203 DELAY(1000); 2204 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 2205 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2206 2207 sc->sis_link = 0; 2208 2209 /* 2210 * Free data in the RX lists. 2211 */ 2212 dp = &sc->sis_rx_list[0]; 2213 for (i = 0; i < SIS_RX_LIST_CNT; i++, dp++) { 2214 if (dp->sis_mbuf == NULL) 2215 continue; 2216 bus_dmamap_unload(sc->sis_tag, dp->sis_map); 2217 bus_dmamap_destroy(sc->sis_tag, dp->sis_map); 2218 m_freem(dp->sis_mbuf); 2219 dp->sis_mbuf = NULL; 2220 } 2221 bzero(sc->sis_rx_list, SIS_RX_LIST_SZ); 2222 2223 /* 2224 * Free the TX list buffers. 2225 */ 2226 dp = &sc->sis_tx_list[0]; 2227 for (i = 0; i < SIS_TX_LIST_CNT; i++, dp++) { 2228 if (dp->sis_mbuf == NULL) 2229 continue; 2230 bus_dmamap_unload(sc->sis_tag, dp->sis_map); 2231 bus_dmamap_destroy(sc->sis_tag, dp->sis_map); 2232 m_freem(dp->sis_mbuf); 2233 dp->sis_mbuf = NULL; 2234 } 2235 2236 bzero(sc->sis_tx_list, SIS_TX_LIST_SZ); 2237 2238 sc->sis_stopped = 1; 2239} 2240 2241/* 2242 * Stop all chip I/O so that the kernel's probe routines don't 2243 * get confused by errant DMAs when rebooting. 2244 */ 2245static void 2246sis_shutdown(device_t dev) 2247{ 2248 struct sis_softc *sc; 2249 2250 sc = device_get_softc(dev); 2251 SIS_LOCK(sc); 2252 sis_reset(sc); 2253 sis_stop(sc); 2254 SIS_UNLOCK(sc); 2255} 2256 2257static device_method_t sis_methods[] = { 2258 /* Device interface */ 2259 DEVMETHOD(device_probe, sis_probe), 2260 DEVMETHOD(device_attach, sis_attach), 2261 DEVMETHOD(device_detach, sis_detach), 2262 DEVMETHOD(device_shutdown, sis_shutdown), 2263 2264 /* bus interface */ 2265 DEVMETHOD(bus_print_child, bus_generic_print_child), 2266 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 2267 2268 /* MII interface */ 2269 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 2270 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 2271 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 2272 2273 { 0, 0 } 2274}; 2275 2276static driver_t sis_driver = { 2277 "sis", 2278 sis_methods, 2279 sizeof(struct sis_softc) 2280}; 2281 2282static devclass_t sis_devclass; 2283 2284DRIVER_MODULE(sis, pci, sis_driver, sis_devclass, 0, 0); 2285DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 2286