if_sis.c revision 139801
150974Swpaul/* 2139740Sphk * Copyright (c) 2005 Poul-Henning Kamp <phk@FreeBSD.org> 350974Swpaul * Copyright (c) 1997, 1998, 1999 450974Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 550974Swpaul * 650974Swpaul * Redistribution and use in source and binary forms, with or without 750974Swpaul * modification, are permitted provided that the following conditions 850974Swpaul * are met: 950974Swpaul * 1. Redistributions of source code must retain the above copyright 1050974Swpaul * notice, this list of conditions and the following disclaimer. 1150974Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1250974Swpaul * notice, this list of conditions and the following disclaimer in the 1350974Swpaul * documentation and/or other materials provided with the distribution. 1450974Swpaul * 3. All advertising materials mentioning features or use of this software 1550974Swpaul * must display the following acknowledgement: 1650974Swpaul * This product includes software developed by Bill Paul. 1750974Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1850974Swpaul * may be used to endorse or promote products derived from this software 1950974Swpaul * without specific prior written permission. 2050974Swpaul * 2150974Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2250974Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2350974Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2450974Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2550974Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2650974Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2750974Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2850974Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2950974Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3050974Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3150974Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3250974Swpaul */ 3350974Swpaul 34122678Sobrien#include <sys/cdefs.h> 35122678Sobrien__FBSDID("$FreeBSD: head/sys/pci/if_sis.c 139801 2005-01-06 23:26:13Z phk $"); 36122678Sobrien 3750974Swpaul/* 3850974Swpaul * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 3950974Swpaul * available from http://www.sis.com.tw. 4050974Swpaul * 4164963Swpaul * This driver also supports the NatSemi DP83815. Datasheets are 4264963Swpaul * available from http://www.national.com. 4364963Swpaul * 4450974Swpaul * Written by Bill Paul <wpaul@ee.columbia.edu> 4550974Swpaul * Electrical Engineering Department 4650974Swpaul * Columbia University, New York City 4750974Swpaul */ 4850974Swpaul/* 4950974Swpaul * The SiS 900 is a fairly simple chip. It uses bus master DMA with 5050974Swpaul * simple TX and RX descriptors of 3 longwords in size. The receiver 5150974Swpaul * has a single perfect filter entry for the station address and a 5250974Swpaul * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 5350974Swpaul * transceiver while the 7016 requires an external transceiver chip. 5450974Swpaul * Both chips offer the standard bit-bang MII interface as well as 5550974Swpaul * an enchanced PHY interface which simplifies accessing MII registers. 5650974Swpaul * 5750974Swpaul * The only downside to this chipset is that RX descriptors must be 5850974Swpaul * longword aligned. 5950974Swpaul */ 6050974Swpaul 6150974Swpaul#include <sys/param.h> 6250974Swpaul#include <sys/systm.h> 6350974Swpaul#include <sys/sockio.h> 6450974Swpaul#include <sys/mbuf.h> 6550974Swpaul#include <sys/malloc.h> 6650974Swpaul#include <sys/kernel.h> 67129876Sphk#include <sys/module.h> 6850974Swpaul#include <sys/socket.h> 6987059Sluigi#include <sys/sysctl.h> 7050974Swpaul 7150974Swpaul#include <net/if.h> 7250974Swpaul#include <net/if_arp.h> 7350974Swpaul#include <net/ethernet.h> 7450974Swpaul#include <net/if_dl.h> 7550974Swpaul#include <net/if_media.h> 7687390Sjhay#include <net/if_types.h> 7787390Sjhay#include <net/if_vlan_var.h> 7850974Swpaul 7950974Swpaul#include <net/bpf.h> 8050974Swpaul 8150974Swpaul#include <machine/bus_pio.h> 8250974Swpaul#include <machine/bus_memio.h> 8350974Swpaul#include <machine/bus.h> 8450974Swpaul#include <machine/resource.h> 8550974Swpaul#include <sys/bus.h> 8650974Swpaul#include <sys/rman.h> 8750974Swpaul 8850974Swpaul#include <dev/mii/mii.h> 8950974Swpaul#include <dev/mii/miivar.h> 9050974Swpaul 91119288Simp#include <dev/pci/pcireg.h> 92119288Simp#include <dev/pci/pcivar.h> 9350974Swpaul 9450974Swpaul#define SIS_USEIOSPACE 9550974Swpaul 9650974Swpaul#include <pci/if_sisreg.h> 9750974Swpaul 98113506SmdoddMODULE_DEPEND(sis, pci, 1, 1, 1); 99113506SmdoddMODULE_DEPEND(sis, ether, 1, 1, 1); 10059758SpeterMODULE_DEPEND(sis, miibus, 1, 1, 1); 10159758Speter 10251089Speter/* "controller miibus0" required. See GENERIC if you get errors here. */ 10350974Swpaul#include "miibus_if.h" 10450974Swpaul 10550974Swpaul/* 10650974Swpaul * Various supported device vendors/types and their names. 10750974Swpaul */ 10850974Swpaulstatic struct sis_type sis_devs[] = { 10950974Swpaul { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 11050974Swpaul { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 111119712Sphk { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" }, 11250974Swpaul { 0, 0, NULL } 11350974Swpaul}; 11450974Swpaul 115139801Sphkstatic int sis_detach(device_t); 116139801Sphkstatic void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *); 117139801Sphkstatic int sis_ifmedia_upd(struct ifnet *); 118139801Sphkstatic void sis_init(void *); 119139801Sphkstatic void sis_initl(struct sis_softc *); 120139801Sphkstatic void sis_intr(void *); 121139801Sphkstatic int sis_ioctl(struct ifnet *, u_long, caddr_t); 122139801Sphkstatic int sis_newbuf(struct sis_softc *, struct sis_desc *, struct mbuf *); 123139801Sphkstatic void sis_start(struct ifnet *); 124139801Sphkstatic void sis_startl(struct ifnet *); 125139801Sphkstatic void sis_stop(struct sis_softc *); 126139801Sphkstatic void sis_watchdog(struct ifnet *); 12750974Swpaul 12850974Swpaul#ifdef SIS_USEIOSPACE 12950974Swpaul#define SIS_RES SYS_RES_IOPORT 13050974Swpaul#define SIS_RID SIS_PCI_LOIO 13150974Swpaul#else 13251030Swpaul#define SIS_RES SYS_RES_MEMORY 13351030Swpaul#define SIS_RID SIS_PCI_LOMEM 13450974Swpaul#endif 13550974Swpaul 13650974Swpaul#define SIS_SETBIT(sc, reg, x) \ 13750974Swpaul CSR_WRITE_4(sc, reg, \ 13850974Swpaul CSR_READ_4(sc, reg) | (x)) 13950974Swpaul 14050974Swpaul#define SIS_CLRBIT(sc, reg, x) \ 14150974Swpaul CSR_WRITE_4(sc, reg, \ 14250974Swpaul CSR_READ_4(sc, reg) & ~(x)) 14350974Swpaul 14450974Swpaul#define SIO_SET(x) \ 14550974Swpaul CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 14650974Swpaul 14750974Swpaul#define SIO_CLR(x) \ 14850974Swpaul CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 14950974Swpaul 15081713Swpaulstatic void 151139740Sphksis_dma_map_desc_next(void *arg, bus_dma_segment_t *segs, int nseg, int error) 15281713Swpaul{ 15381713Swpaul struct sis_desc *r; 15481713Swpaul 15581713Swpaul r = arg; 15681713Swpaul r->sis_next = segs->ds_addr; 15781713Swpaul} 15881713Swpaul 15981713Swpaulstatic void 160139740Sphksis_dma_map_desc_ptr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 16181713Swpaul{ 16281713Swpaul struct sis_desc *r; 16381713Swpaul 16481713Swpaul r = arg; 16581713Swpaul r->sis_ptr = segs->ds_addr; 16681713Swpaul} 16781713Swpaul 16881713Swpaulstatic void 169139740Sphksis_dma_map_ring(void *arg, bus_dma_segment_t *segs, int nseg, int error) 17081713Swpaul{ 17181713Swpaul u_int32_t *p; 17281713Swpaul 17381713Swpaul p = arg; 17481713Swpaul *p = segs->ds_addr; 17581713Swpaul} 17681713Swpaul 17762672Swpaul/* 17862672Swpaul * Routine to reverse the bits in a word. Stolen almost 17962672Swpaul * verbatim from /usr/games/fortune. 18062672Swpaul */ 181139740Sphkstatic uint16_t 182139740Sphksis_reverse(uint16_t n) 18362672Swpaul{ 18462672Swpaul n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 18562672Swpaul n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 18662672Swpaul n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 18762672Swpaul n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 18862672Swpaul 18962672Swpaul return(n); 19062672Swpaul} 19162672Swpaul 192102334Salfredstatic void 193139740Sphksis_delay(struct sis_softc *sc) 19450974Swpaul{ 19550974Swpaul int idx; 19650974Swpaul 19750974Swpaul for (idx = (300 / 33) + 1; idx > 0; idx--) 19850974Swpaul CSR_READ_4(sc, SIS_CSR); 19950974Swpaul} 20050974Swpaul 201102334Salfredstatic void 202139740Sphksis_eeprom_idle(struct sis_softc *sc) 20350974Swpaul{ 204139708Sphk int i; 20550974Swpaul 20650974Swpaul SIO_SET(SIS_EECTL_CSEL); 20750974Swpaul sis_delay(sc); 20850974Swpaul SIO_SET(SIS_EECTL_CLK); 20950974Swpaul sis_delay(sc); 21050974Swpaul 21150974Swpaul for (i = 0; i < 25; i++) { 21250974Swpaul SIO_CLR(SIS_EECTL_CLK); 21350974Swpaul sis_delay(sc); 21450974Swpaul SIO_SET(SIS_EECTL_CLK); 21550974Swpaul sis_delay(sc); 21650974Swpaul } 21750974Swpaul 21850974Swpaul SIO_CLR(SIS_EECTL_CLK); 21950974Swpaul sis_delay(sc); 22050974Swpaul SIO_CLR(SIS_EECTL_CSEL); 22150974Swpaul sis_delay(sc); 22250974Swpaul CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 22350974Swpaul} 22450974Swpaul 22550974Swpaul/* 22650974Swpaul * Send a read command and address to the EEPROM, check for ACK. 22750974Swpaul */ 228102334Salfredstatic void 229139740Sphksis_eeprom_putbyte(struct sis_softc *sc, int addr) 23050974Swpaul{ 231139708Sphk int d, i; 23250974Swpaul 23350974Swpaul d = addr | SIS_EECMD_READ; 23450974Swpaul 23550974Swpaul /* 23650974Swpaul * Feed in each bit and stobe the clock. 23750974Swpaul */ 23850974Swpaul for (i = 0x400; i; i >>= 1) { 23950974Swpaul if (d & i) { 24050974Swpaul SIO_SET(SIS_EECTL_DIN); 24150974Swpaul } else { 24250974Swpaul SIO_CLR(SIS_EECTL_DIN); 24350974Swpaul } 24450974Swpaul sis_delay(sc); 24550974Swpaul SIO_SET(SIS_EECTL_CLK); 24650974Swpaul sis_delay(sc); 24750974Swpaul SIO_CLR(SIS_EECTL_CLK); 24850974Swpaul sis_delay(sc); 24950974Swpaul } 25050974Swpaul} 25150974Swpaul 25250974Swpaul/* 25350974Swpaul * Read a word of data stored in the EEPROM at address 'addr.' 25450974Swpaul */ 255102334Salfredstatic void 256139740Sphksis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest) 25750974Swpaul{ 258139708Sphk int i; 25950974Swpaul u_int16_t word = 0; 26050974Swpaul 26150974Swpaul /* Force EEPROM to idle state. */ 26250974Swpaul sis_eeprom_idle(sc); 26350974Swpaul 26450974Swpaul /* Enter EEPROM access mode. */ 26550974Swpaul sis_delay(sc); 26662672Swpaul SIO_CLR(SIS_EECTL_CLK); 26762672Swpaul sis_delay(sc); 26850974Swpaul SIO_SET(SIS_EECTL_CSEL); 26950974Swpaul sis_delay(sc); 27050974Swpaul 27150974Swpaul /* 27250974Swpaul * Send address of word we want to read. 27350974Swpaul */ 27450974Swpaul sis_eeprom_putbyte(sc, addr); 27550974Swpaul 27650974Swpaul /* 27750974Swpaul * Start reading bits from EEPROM. 27850974Swpaul */ 27950974Swpaul for (i = 0x8000; i; i >>= 1) { 28050974Swpaul SIO_SET(SIS_EECTL_CLK); 28150974Swpaul sis_delay(sc); 28250974Swpaul if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 28350974Swpaul word |= i; 28450974Swpaul sis_delay(sc); 28550974Swpaul SIO_CLR(SIS_EECTL_CLK); 28650974Swpaul sis_delay(sc); 28750974Swpaul } 28850974Swpaul 28950974Swpaul /* Turn off EEPROM access mode. */ 29050974Swpaul sis_eeprom_idle(sc); 29150974Swpaul 29250974Swpaul *dest = word; 29350974Swpaul} 29450974Swpaul 29550974Swpaul/* 29650974Swpaul * Read a sequence of words from the EEPROM. 29750974Swpaul */ 298102334Salfredstatic void 299139740Sphksis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap) 30050974Swpaul{ 30150974Swpaul int i; 30250974Swpaul u_int16_t word = 0, *ptr; 30350974Swpaul 30450974Swpaul for (i = 0; i < cnt; i++) { 30550974Swpaul sis_eeprom_getword(sc, off + i, &word); 30650974Swpaul ptr = (u_int16_t *)(dest + (i * 2)); 30750974Swpaul if (swap) 30850974Swpaul *ptr = ntohs(word); 30950974Swpaul else 31050974Swpaul *ptr = word; 31150974Swpaul } 31250974Swpaul} 31350974Swpaul 31472197Swpaul#ifdef __i386__ 315102334Salfredstatic device_t 316139740Sphksis_find_bridge(device_t dev) 31772197Swpaul{ 31872197Swpaul devclass_t pci_devclass; 31972197Swpaul device_t *pci_devices; 32072197Swpaul int pci_count = 0; 32172197Swpaul device_t *pci_children; 32272197Swpaul int pci_childcount = 0; 32372197Swpaul device_t *busp, *childp; 32487994Sarchie device_t child = NULL; 32572197Swpaul int i, j; 32672197Swpaul 32772197Swpaul if ((pci_devclass = devclass_find("pci")) == NULL) 32872197Swpaul return(NULL); 32972197Swpaul 33072197Swpaul devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 33172197Swpaul 33272197Swpaul for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 33372197Swpaul pci_childcount = 0; 33472197Swpaul device_get_children(*busp, &pci_children, &pci_childcount); 33572197Swpaul for (j = 0, childp = pci_children; 33672197Swpaul j < pci_childcount; j++, childp++) { 33772197Swpaul if (pci_get_vendor(*childp) == SIS_VENDORID && 33872197Swpaul pci_get_device(*childp) == 0x0008) { 33987994Sarchie child = *childp; 34087994Sarchie goto done; 34172197Swpaul } 34272197Swpaul } 34372197Swpaul } 34472197Swpaul 34587994Sarchiedone: 34672197Swpaul free(pci_devices, M_TEMP); 34772197Swpaul free(pci_children, M_TEMP); 34887994Sarchie return(child); 34972197Swpaul} 35072197Swpaul 351102334Salfredstatic void 352139740Sphksis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off, int cnt) 35372197Swpaul{ 35472197Swpaul device_t bridge; 35572197Swpaul u_int8_t reg; 35672197Swpaul int i; 35772197Swpaul bus_space_tag_t btag; 35872197Swpaul 35972197Swpaul bridge = sis_find_bridge(dev); 36072197Swpaul if (bridge == NULL) 36172197Swpaul return; 36272197Swpaul reg = pci_read_config(bridge, 0x48, 1); 36372197Swpaul pci_write_config(bridge, 0x48, reg|0x40, 1); 36472197Swpaul 36572197Swpaul /* XXX */ 36672197Swpaul btag = I386_BUS_SPACE_IO; 36772197Swpaul 36872197Swpaul for (i = 0; i < cnt; i++) { 36972197Swpaul bus_space_write_1(btag, 0x0, 0x70, i + off); 37072197Swpaul *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 37172197Swpaul } 37272197Swpaul 37372197Swpaul pci_write_config(bridge, 0x48, reg & ~0x40, 1); 37472197Swpaul return; 37572197Swpaul} 37689296Swpaul 377102334Salfredstatic void 378139740Sphksis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest) 37989296Swpaul{ 38089296Swpaul u_int32_t filtsave, csrsave; 38189296Swpaul 38289296Swpaul filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 38389296Swpaul csrsave = CSR_READ_4(sc, SIS_CSR); 38489296Swpaul 38589296Swpaul CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 38689296Swpaul CSR_WRITE_4(sc, SIS_CSR, 0); 38789296Swpaul 38889296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 38989296Swpaul 39089296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 39189296Swpaul ((u_int16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 39289296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 39389296Swpaul ((u_int16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 39489296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 39589296Swpaul ((u_int16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 39689296Swpaul 39789296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 39889296Swpaul CSR_WRITE_4(sc, SIS_CSR, csrsave); 39989296Swpaul return; 40089296Swpaul} 40172197Swpaul#endif 40272197Swpaul 403109060Smbr/* 404109060Smbr * Sync the PHYs by setting data bit and strobing the clock 32 times. 405109060Smbr */ 406139740Sphkstatic void 407139740Sphksis_mii_sync(struct sis_softc *sc) 408109060Smbr{ 409139708Sphk int i; 410109060Smbr 411109060Smbr SIO_SET(SIS_MII_DIR|SIS_MII_DATA); 412109060Smbr 413109060Smbr for (i = 0; i < 32; i++) { 414109060Smbr SIO_SET(SIS_MII_CLK); 415109060Smbr DELAY(1); 416109060Smbr SIO_CLR(SIS_MII_CLK); 417109060Smbr DELAY(1); 418109060Smbr } 419109060Smbr} 420109060Smbr 421109060Smbr/* 422109060Smbr * Clock a series of bits through the MII. 423109060Smbr */ 424139740Sphkstatic void 425139740Sphksis_mii_send(struct sis_softc *sc, uint32_t bits, int cnt) 426109060Smbr{ 427109060Smbr int i; 428109060Smbr 429109060Smbr SIO_CLR(SIS_MII_CLK); 430109060Smbr 431109060Smbr for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 432109060Smbr if (bits & i) { 433109060Smbr SIO_SET(SIS_MII_DATA); 434109060Smbr } else { 435109060Smbr SIO_CLR(SIS_MII_DATA); 436109060Smbr } 437109060Smbr DELAY(1); 438109060Smbr SIO_CLR(SIS_MII_CLK); 439109060Smbr DELAY(1); 440109060Smbr SIO_SET(SIS_MII_CLK); 441109060Smbr } 442109060Smbr} 443109060Smbr 444109060Smbr/* 445109060Smbr * Read an PHY register through the MII. 446109060Smbr */ 447139740Sphkstatic int 448139740Sphksis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame) 449109060Smbr{ 450109060Smbr int i, ack, s; 451109060Smbr 452109060Smbr s = splimp(); 453109060Smbr 454109060Smbr /* 455109060Smbr * Set up frame for RX. 456109060Smbr */ 457109060Smbr frame->mii_stdelim = SIS_MII_STARTDELIM; 458109060Smbr frame->mii_opcode = SIS_MII_READOP; 459109060Smbr frame->mii_turnaround = 0; 460109060Smbr frame->mii_data = 0; 461109060Smbr 462109060Smbr /* 463109060Smbr * Turn on data xmit. 464109060Smbr */ 465109060Smbr SIO_SET(SIS_MII_DIR); 466109060Smbr 467109060Smbr sis_mii_sync(sc); 468109060Smbr 469109060Smbr /* 470109060Smbr * Send command/address info. 471109060Smbr */ 472109060Smbr sis_mii_send(sc, frame->mii_stdelim, 2); 473109060Smbr sis_mii_send(sc, frame->mii_opcode, 2); 474109060Smbr sis_mii_send(sc, frame->mii_phyaddr, 5); 475109060Smbr sis_mii_send(sc, frame->mii_regaddr, 5); 476109060Smbr 477109060Smbr /* Idle bit */ 478109060Smbr SIO_CLR((SIS_MII_CLK|SIS_MII_DATA)); 479109060Smbr DELAY(1); 480109060Smbr SIO_SET(SIS_MII_CLK); 481109060Smbr DELAY(1); 482109060Smbr 483109060Smbr /* Turn off xmit. */ 484109060Smbr SIO_CLR(SIS_MII_DIR); 485109060Smbr 486109060Smbr /* Check for ack */ 487109060Smbr SIO_CLR(SIS_MII_CLK); 488109060Smbr DELAY(1); 489109060Smbr ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA; 490109060Smbr SIO_SET(SIS_MII_CLK); 491109060Smbr DELAY(1); 492109060Smbr 493109060Smbr /* 494109060Smbr * Now try reading data bits. If the ack failed, we still 495109060Smbr * need to clock through 16 cycles to keep the PHY(s) in sync. 496109060Smbr */ 497109060Smbr if (ack) { 498109060Smbr for(i = 0; i < 16; i++) { 499109060Smbr SIO_CLR(SIS_MII_CLK); 500109060Smbr DELAY(1); 501109060Smbr SIO_SET(SIS_MII_CLK); 502109060Smbr DELAY(1); 503109060Smbr } 504109060Smbr goto fail; 505109060Smbr } 506109060Smbr 507109060Smbr for (i = 0x8000; i; i >>= 1) { 508109060Smbr SIO_CLR(SIS_MII_CLK); 509109060Smbr DELAY(1); 510109060Smbr if (!ack) { 511109060Smbr if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA) 512109060Smbr frame->mii_data |= i; 513109060Smbr DELAY(1); 514109060Smbr } 515109060Smbr SIO_SET(SIS_MII_CLK); 516109060Smbr DELAY(1); 517109060Smbr } 518109060Smbr 519109060Smbrfail: 520109060Smbr 521109060Smbr SIO_CLR(SIS_MII_CLK); 522109060Smbr DELAY(1); 523109060Smbr SIO_SET(SIS_MII_CLK); 524109060Smbr DELAY(1); 525109060Smbr 526109060Smbr splx(s); 527109060Smbr 528109060Smbr if (ack) 529109060Smbr return(1); 530109060Smbr return(0); 531109060Smbr} 532109060Smbr 533109060Smbr/* 534109060Smbr * Write to a PHY register through the MII. 535109060Smbr */ 536139740Sphkstatic int 537139740Sphksis_mii_writereg(struct sis_softc *sc, struct sis_mii_frame *frame) 538109060Smbr{ 539109060Smbr int s; 540109060Smbr 541109060Smbr s = splimp(); 542109060Smbr /* 543109060Smbr * Set up frame for TX. 544109060Smbr */ 545109060Smbr 546109060Smbr frame->mii_stdelim = SIS_MII_STARTDELIM; 547109060Smbr frame->mii_opcode = SIS_MII_WRITEOP; 548109060Smbr frame->mii_turnaround = SIS_MII_TURNAROUND; 549109060Smbr 550109060Smbr /* 551109060Smbr * Turn on data output. 552109060Smbr */ 553109060Smbr SIO_SET(SIS_MII_DIR); 554109060Smbr 555109060Smbr sis_mii_sync(sc); 556109060Smbr 557109060Smbr sis_mii_send(sc, frame->mii_stdelim, 2); 558109060Smbr sis_mii_send(sc, frame->mii_opcode, 2); 559109060Smbr sis_mii_send(sc, frame->mii_phyaddr, 5); 560109060Smbr sis_mii_send(sc, frame->mii_regaddr, 5); 561109060Smbr sis_mii_send(sc, frame->mii_turnaround, 2); 562109060Smbr sis_mii_send(sc, frame->mii_data, 16); 563109060Smbr 564109060Smbr /* Idle bit. */ 565109060Smbr SIO_SET(SIS_MII_CLK); 566109060Smbr DELAY(1); 567109060Smbr SIO_CLR(SIS_MII_CLK); 568109060Smbr DELAY(1); 569109060Smbr 570109060Smbr /* 571109060Smbr * Turn off xmit. 572109060Smbr */ 573109060Smbr SIO_CLR(SIS_MII_DIR); 574109060Smbr 575109060Smbr splx(s); 576109060Smbr 577109060Smbr return(0); 578109060Smbr} 579109060Smbr 580102334Salfredstatic int 581139740Sphksis_miibus_readreg(device_t dev, int phy, int reg) 58250974Swpaul{ 58350974Swpaul struct sis_softc *sc; 584109060Smbr struct sis_mii_frame frame; 58550974Swpaul 58650974Swpaul sc = device_get_softc(dev); 58750974Swpaul 58862672Swpaul if (sc->sis_type == SIS_TYPE_83815) { 58962672Swpaul if (phy != 0) 59062672Swpaul return(0); 59162672Swpaul /* 59262672Swpaul * The NatSemi chip can take a while after 59362672Swpaul * a reset to come ready, during which the BMSR 59462672Swpaul * returns a value of 0. This is *never* supposed 59562672Swpaul * to happen: some of the BMSR bits are meant to 59662672Swpaul * be hardwired in the on position, and this can 59762672Swpaul * confuse the miibus code a bit during the probe 59862672Swpaul * and attach phase. So we make an effort to check 59962672Swpaul * for this condition and wait for it to clear. 60062672Swpaul */ 60162672Swpaul if (!CSR_READ_4(sc, NS_BMSR)) 60262672Swpaul DELAY(1000); 603109060Smbr return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 60462672Swpaul } 60562672Swpaul 606109976Smbr /* 607109976Smbr * Chipsets < SIS_635 seem not to be able to read/write 608109976Smbr * through mdio. Use the enhanced PHY access register 609109976Smbr * again for them. 610109976Smbr */ 61189296Swpaul if (sc->sis_type == SIS_TYPE_900 && 612109976Smbr sc->sis_rev < SIS_REV_635) { 613109976Smbr int i, val = 0; 61450974Swpaul 615109976Smbr if (phy != 0) 616109976Smbr return(0); 61750974Swpaul 618109976Smbr CSR_WRITE_4(sc, SIS_PHYCTL, 619109976Smbr (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 620109976Smbr SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 62150974Swpaul 622109976Smbr for (i = 0; i < SIS_TIMEOUT; i++) { 623109976Smbr if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 624109976Smbr break; 625109976Smbr } 626109976Smbr 627109976Smbr if (i == SIS_TIMEOUT) { 628109976Smbr printf("sis%d: PHY failed to come ready\n", 629109976Smbr sc->sis_unit); 630109976Smbr return(0); 631109976Smbr } 632109976Smbr 633109976Smbr val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 634109976Smbr 635109976Smbr if (val == 0xFFFF) 636109976Smbr return(0); 637109976Smbr 638109976Smbr return(val); 639109976Smbr } else { 640109976Smbr bzero((char *)&frame, sizeof(frame)); 641109976Smbr 642109976Smbr frame.mii_phyaddr = phy; 643109976Smbr frame.mii_regaddr = reg; 644109976Smbr sis_mii_readreg(sc, &frame); 645109976Smbr 646109976Smbr return(frame.mii_data); 647109976Smbr } 64850974Swpaul} 64950974Swpaul 650102334Salfredstatic int 651139740Sphksis_miibus_writereg(device_t dev, int phy, int reg, int data) 65250974Swpaul{ 65350974Swpaul struct sis_softc *sc; 654109060Smbr struct sis_mii_frame frame; 65550974Swpaul 65650974Swpaul sc = device_get_softc(dev); 65750974Swpaul 65862672Swpaul if (sc->sis_type == SIS_TYPE_83815) { 65962672Swpaul if (phy != 0) 66062672Swpaul return(0); 66162672Swpaul CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 66262672Swpaul return(0); 66362672Swpaul } 66462672Swpaul 665109976Smbr /* 666109976Smbr * Chipsets < SIS_635 seem not to be able to read/write 667109976Smbr * through mdio. Use the enhanced PHY access register 668109976Smbr * again for them. 669109976Smbr */ 670109976Smbr if (sc->sis_type == SIS_TYPE_900 && 671109976Smbr sc->sis_rev < SIS_REV_635) { 672109976Smbr int i; 67350974Swpaul 674109976Smbr if (phy != 0) 675109976Smbr return(0); 67650974Swpaul 677109976Smbr CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 678109976Smbr (reg << 6) | SIS_PHYOP_WRITE); 679109976Smbr SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 68050974Swpaul 681109976Smbr for (i = 0; i < SIS_TIMEOUT; i++) { 682109976Smbr if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 683109976Smbr break; 684109976Smbr } 68550974Swpaul 686109976Smbr if (i == SIS_TIMEOUT) 687109976Smbr printf("sis%d: PHY failed to come ready\n", 688109976Smbr sc->sis_unit); 689109976Smbr } else { 690109976Smbr bzero((char *)&frame, sizeof(frame)); 691109976Smbr 692109976Smbr frame.mii_phyaddr = phy; 693109976Smbr frame.mii_regaddr = reg; 694109976Smbr frame.mii_data = data; 695109976Smbr sis_mii_writereg(sc, &frame); 696109976Smbr } 69750974Swpaul return(0); 69850974Swpaul} 69950974Swpaul 700102334Salfredstatic void 701139717Sphksis_miibus_statchg(device_t dev) 70250974Swpaul{ 70350974Swpaul struct sis_softc *sc; 70450974Swpaul 70550974Swpaul sc = device_get_softc(dev); 706139717Sphk SIS_LOCK_ASSERT(sc); 707139717Sphk sis_initl(sc); 70850974Swpaul} 70950974Swpaul 710139740Sphkstatic uint32_t 711139740Sphksis_mchash(struct sis_softc *sc, const uint8_t *addr) 71250974Swpaul{ 713130270Snaddy uint32_t crc; 71450974Swpaul 71550974Swpaul /* Compute CRC for the address value. */ 716130270Snaddy crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 71750974Swpaul 71862672Swpaul /* 71962672Swpaul * return the filter bit position 72062672Swpaul * 72162672Swpaul * The NatSemi chip has a 512-bit filter, which is 72262672Swpaul * different than the SiS, so we special-case it. 72362672Swpaul */ 72462672Swpaul if (sc->sis_type == SIS_TYPE_83815) 725109060Smbr return (crc >> 23); 726109976Smbr else if (sc->sis_rev >= SIS_REV_635 || 727109976Smbr sc->sis_rev == SIS_REV_900B) 728109060Smbr return (crc >> 24); 729109976Smbr else 730109976Smbr return (crc >> 25); 73150974Swpaul} 73250974Swpaul 733102334Salfredstatic void 734139740Sphksis_setmulti_ns(struct sis_softc *sc) 73550974Swpaul{ 73650974Swpaul struct ifnet *ifp; 73750974Swpaul struct ifmultiaddr *ifma; 73850974Swpaul u_int32_t h = 0, i, filtsave; 73962672Swpaul int bit, index; 74050974Swpaul 74150974Swpaul ifp = &sc->arpcom.ac_if; 74250974Swpaul 74350974Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 74462672Swpaul SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 74550974Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 74650974Swpaul return; 74750974Swpaul } 74850974Swpaul 74962672Swpaul /* 75062672Swpaul * We have to explicitly enable the multicast hash table 75162672Swpaul * on the NatSemi chip if we want to use it, which we do. 75262672Swpaul */ 75362672Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 75450974Swpaul SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 75550974Swpaul 75650974Swpaul filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 75750974Swpaul 75850974Swpaul /* first, zot all the existing hash bits */ 75962672Swpaul for (i = 0; i < 32; i++) { 76062672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 76162672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 76262672Swpaul } 76362672Swpaul 76472084Sphk TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 76562672Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 76662672Swpaul continue; 767122625Sobrien h = sis_mchash(sc, 768122625Sobrien LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 76962672Swpaul index = h >> 3; 77062672Swpaul bit = h & 0x1F; 77162672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 77262672Swpaul if (bit > 0xF) 77362672Swpaul bit -= 0x10; 77462672Swpaul SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 77562672Swpaul } 77662672Swpaul 77762672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 77862672Swpaul 77962672Swpaul return; 78062672Swpaul} 78162672Swpaul 782102334Salfredstatic void 783139740Sphksis_setmulti_sis(struct sis_softc *sc) 78462672Swpaul{ 78562672Swpaul struct ifnet *ifp; 78662672Swpaul struct ifmultiaddr *ifma; 787109060Smbr u_int32_t h, i, n, ctl; 788109060Smbr u_int16_t hashes[16]; 78962672Swpaul 79062672Swpaul ifp = &sc->arpcom.ac_if; 79162672Swpaul 792109060Smbr /* hash table size */ 793109976Smbr if (sc->sis_rev >= SIS_REV_635 || 794109976Smbr sc->sis_rev == SIS_REV_900B) 795109976Smbr n = 16; 796109976Smbr else 797109976Smbr n = 8; 79862672Swpaul 799109060Smbr ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE; 80062672Swpaul 801109060Smbr if (ifp->if_flags & IFF_BROADCAST) 802109060Smbr ctl |= SIS_RXFILTCTL_BROAD; 80362672Swpaul 804109060Smbr if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 805109060Smbr ctl |= SIS_RXFILTCTL_ALLMULTI; 806109060Smbr if (ifp->if_flags & IFF_PROMISC) 807109060Smbr ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS; 808109060Smbr for (i = 0; i < n; i++) 809109060Smbr hashes[i] = ~0; 810109060Smbr } else { 811109060Smbr for (i = 0; i < n; i++) 812109060Smbr hashes[i] = 0; 813109060Smbr i = 0; 814109060Smbr TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 815109060Smbr if (ifma->ifma_addr->sa_family != AF_LINK) 816109060Smbr continue; 817122625Sobrien h = sis_mchash(sc, 818109060Smbr LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 819109060Smbr hashes[h >> 4] |= 1 << (h & 0xf); 820109060Smbr i++; 821109060Smbr } 822109060Smbr if (i > n) { 823109060Smbr ctl |= SIS_RXFILTCTL_ALLMULTI; 824109060Smbr for (i = 0; i < n; i++) 825109060Smbr hashes[i] = ~0; 826109060Smbr } 82750974Swpaul } 82850974Swpaul 829109060Smbr for (i = 0; i < n; i++) { 830109060Smbr CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); 831109060Smbr CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); 83250974Swpaul } 83350974Swpaul 834109060Smbr CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl); 83550974Swpaul} 83650974Swpaul 837102334Salfredstatic void 838139717Sphksis_reset(struct sis_softc *sc) 83950974Swpaul{ 840139708Sphk int i; 84150974Swpaul 84250974Swpaul SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 84350974Swpaul 84450974Swpaul for (i = 0; i < SIS_TIMEOUT; i++) { 84550974Swpaul if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 84650974Swpaul break; 84750974Swpaul } 84850974Swpaul 84950974Swpaul if (i == SIS_TIMEOUT) 85050974Swpaul printf("sis%d: reset never completed\n", sc->sis_unit); 85150974Swpaul 85250974Swpaul /* Wait a little while for the chip to get its brains in order. */ 85350974Swpaul DELAY(1000); 85472813Swpaul 85572813Swpaul /* 85672813Swpaul * If this is a NetSemi chip, make sure to clear 85772813Swpaul * PME mode. 85872813Swpaul */ 85972813Swpaul if (sc->sis_type == SIS_TYPE_83815) { 86072813Swpaul CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 86172813Swpaul CSR_WRITE_4(sc, NS_CLKRUN, 0); 86272813Swpaul } 86372813Swpaul 86450974Swpaul return; 86550974Swpaul} 86650974Swpaul 86750974Swpaul/* 86850974Swpaul * Probe for an SiS chip. Check the PCI vendor and device 86950974Swpaul * IDs against our list and return a device name if we find a match. 87050974Swpaul */ 871102334Salfredstatic int 872139740Sphksis_probe(device_t dev) 87350974Swpaul{ 87450974Swpaul struct sis_type *t; 87550974Swpaul 87650974Swpaul t = sis_devs; 87750974Swpaul 87850974Swpaul while(t->sis_name != NULL) { 87950974Swpaul if ((pci_get_vendor(dev) == t->sis_vid) && 88050974Swpaul (pci_get_device(dev) == t->sis_did)) { 88150974Swpaul device_set_desc(dev, t->sis_name); 88250974Swpaul return(0); 88350974Swpaul } 88450974Swpaul t++; 88550974Swpaul } 88650974Swpaul 88750974Swpaul return(ENXIO); 88850974Swpaul} 88950974Swpaul 89050974Swpaul/* 89150974Swpaul * Attach the interface. Allocate softc structures, do ifmedia 89250974Swpaul * setup and ethernet/BPF attach. 89350974Swpaul */ 894102334Salfredstatic int 895139740Sphksis_attach(device_t dev) 89650974Swpaul{ 89750974Swpaul u_char eaddr[ETHER_ADDR_LEN]; 89850974Swpaul struct sis_softc *sc; 89950974Swpaul struct ifnet *ifp; 900109061Smbr int unit, error = 0, rid, waittime = 0; 90150974Swpaul 902109061Smbr waittime = 0; 90350974Swpaul sc = device_get_softc(dev); 90450974Swpaul unit = device_get_unit(dev); 90550974Swpaul 906119712Sphk sc->sis_self = dev; 907119712Sphk 90893818Sjhb mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 90993818Sjhb MTX_DEF | MTX_RECURSE); 91069583Swpaul 91150974Swpaul if (pci_get_device(dev) == SIS_DEVICEID_900) 91250974Swpaul sc->sis_type = SIS_TYPE_900; 91350974Swpaul if (pci_get_device(dev) == SIS_DEVICEID_7016) 91450974Swpaul sc->sis_type = SIS_TYPE_7016; 91562672Swpaul if (pci_get_vendor(dev) == NS_VENDORID) 91662672Swpaul sc->sis_type = SIS_TYPE_83815; 91750974Swpaul 91889296Swpaul sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 91950974Swpaul /* 92050974Swpaul * Map control/status registers. 92150974Swpaul */ 92272813Swpaul pci_enable_busmaster(dev); 92350974Swpaul 92450974Swpaul rid = SIS_RID; 925127135Snjl sc->sis_res = bus_alloc_resource_any(dev, SIS_RES, &rid, RF_ACTIVE); 92650974Swpaul 92750974Swpaul if (sc->sis_res == NULL) { 92850974Swpaul printf("sis%d: couldn't map ports/memory\n", unit); 92950974Swpaul error = ENXIO; 93050974Swpaul goto fail; 93150974Swpaul } 93250974Swpaul 93350974Swpaul sc->sis_btag = rman_get_bustag(sc->sis_res); 93450974Swpaul sc->sis_bhandle = rman_get_bushandle(sc->sis_res); 93550974Swpaul 93650974Swpaul /* Allocate interrupt */ 93750974Swpaul rid = 0; 938127135Snjl sc->sis_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 93950974Swpaul RF_SHAREABLE | RF_ACTIVE); 94050974Swpaul 94150974Swpaul if (sc->sis_irq == NULL) { 94250974Swpaul printf("sis%d: couldn't map interrupt\n", unit); 94350974Swpaul error = ENXIO; 94450974Swpaul goto fail; 94550974Swpaul } 94650974Swpaul 94750974Swpaul /* Reset the adapter. */ 94850974Swpaul sis_reset(sc); 94950974Swpaul 950109976Smbr if (sc->sis_type == SIS_TYPE_900 && 951109976Smbr (sc->sis_rev == SIS_REV_635 || 952109976Smbr sc->sis_rev == SIS_REV_900B)) { 953109976Smbr SIO_SET(SIS_CFG_RND_CNT); 954109976Smbr SIO_SET(SIS_CFG_PERR_DETECT); 955109976Smbr } 956109976Smbr 95750974Swpaul /* 95850974Swpaul * Get station address from the EEPROM. 95950974Swpaul */ 96062672Swpaul switch (pci_get_vendor(dev)) { 96162672Swpaul case NS_VENDORID: 962119712Sphk sc->sis_srr = CSR_READ_4(sc, NS_SRR); 963119712Sphk 964119712Sphk /* We can't update the device description, so spew */ 965119712Sphk if (sc->sis_srr == NS_SRR_15C) 966119712Sphk device_printf(dev, "Silicon Revision: DP83815C\n"); 967119712Sphk else if (sc->sis_srr == NS_SRR_15D) 968119712Sphk device_printf(dev, "Silicon Revision: DP83815D\n"); 969119712Sphk else if (sc->sis_srr == NS_SRR_16A) 970119712Sphk device_printf(dev, "Silicon Revision: DP83816A\n"); 971119712Sphk else 972119712Sphk device_printf(dev, "Silicon Revision %x\n", sc->sis_srr); 973119712Sphk 97462672Swpaul /* 97562672Swpaul * Reading the MAC address out of the EEPROM on 97662672Swpaul * the NatSemi chip takes a bit more work than 97762672Swpaul * you'd expect. The address spans 4 16-bit words, 97862672Swpaul * with the first word containing only a single bit. 97962672Swpaul * You have to shift everything over one bit to 98062672Swpaul * get it aligned properly. Also, the bits are 98162672Swpaul * stored backwards (the LSB is really the MSB, 98262672Swpaul * and so on) so you have to reverse them in order 98362672Swpaul * to get the MAC address into the form we want. 98462672Swpaul * Why? Who the hell knows. 98562672Swpaul */ 98662672Swpaul { 98762672Swpaul u_int16_t tmp[4]; 98850974Swpaul 98962672Swpaul sis_read_eeprom(sc, (caddr_t)&tmp, 99062672Swpaul NS_EE_NODEADDR, 4, 0); 99162672Swpaul 99262672Swpaul /* Shift everything over one bit. */ 99362672Swpaul tmp[3] = tmp[3] >> 1; 99462681Swpaul tmp[3] |= tmp[2] << 15; 99562672Swpaul tmp[2] = tmp[2] >> 1; 99662681Swpaul tmp[2] |= tmp[1] << 15; 99762672Swpaul tmp[1] = tmp[1] >> 1; 99862681Swpaul tmp[1] |= tmp[0] << 15; 99962672Swpaul 100062672Swpaul /* Now reverse all the bits. */ 100162672Swpaul tmp[3] = sis_reverse(tmp[3]); 100262672Swpaul tmp[2] = sis_reverse(tmp[2]); 100362672Swpaul tmp[1] = sis_reverse(tmp[1]); 100462672Swpaul 100562672Swpaul bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); 100662672Swpaul } 100762672Swpaul break; 100862672Swpaul case SIS_VENDORID: 100962672Swpaul default: 101072197Swpaul#ifdef __i386__ 101172197Swpaul /* 101272197Swpaul * If this is a SiS 630E chipset with an embedded 101372197Swpaul * SiS 900 controller, we have to read the MAC address 101472197Swpaul * from the APC CMOS RAM. Our method for doing this 101572197Swpaul * is very ugly since we have to reach out and grab 101672197Swpaul * ahold of hardware for which we cannot properly 101772197Swpaul * allocate resources. This code is only compiled on 101872197Swpaul * the i386 architecture since the SiS 630E chipset 101972197Swpaul * is for x86 motherboards only. Note that there are 102072197Swpaul * a lot of magic numbers in this hack. These are 102172197Swpaul * taken from SiS's Linux driver. I'd like to replace 102272197Swpaul * them with proper symbolic definitions, but that 102372197Swpaul * requires some datasheets that I don't have access 102472197Swpaul * to at the moment. 102572197Swpaul */ 102689296Swpaul if (sc->sis_rev == SIS_REV_630S || 102789296Swpaul sc->sis_rev == SIS_REV_630E || 102890328Sambrisko sc->sis_rev == SIS_REV_630EA1) 102972197Swpaul sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 103089296Swpaul 103190328Sambrisko else if (sc->sis_rev == SIS_REV_635 || 103290328Sambrisko sc->sis_rev == SIS_REV_630ET) 103389296Swpaul sis_read_mac(sc, dev, (caddr_t)&eaddr); 1034109061Smbr else if (sc->sis_rev == SIS_REV_96x) { 1035109061Smbr /* Allow to read EEPROM from LAN. It is shared 1036109061Smbr * between a 1394 controller and the NIC and each 1037109061Smbr * time we access it, we need to set SIS_EECMD_REQ. 1038109061Smbr */ 1039109061Smbr SIO_SET(SIS_EECMD_REQ); 1040109061Smbr for (waittime = 0; waittime < SIS_TIMEOUT; 1041109061Smbr waittime++) { 1042109061Smbr /* Force EEPROM to idle state. */ 1043109061Smbr sis_eeprom_idle(sc); 1044109061Smbr if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { 1045109061Smbr sis_read_eeprom(sc, (caddr_t)&eaddr, 1046109061Smbr SIS_EE_NODEADDR, 3, 0); 1047109061Smbr break; 1048109061Smbr } 1049109061Smbr DELAY(1); 1050109061Smbr } 1051109061Smbr /* 1052109061Smbr * Set SIS_EECTL_CLK to high, so a other master 1053109061Smbr * can operate on the i2c bus. 1054109061Smbr */ 1055109061Smbr SIO_SET(SIS_EECTL_CLK); 1056109061Smbr /* Refuse EEPROM access by LAN */ 1057109061Smbr SIO_SET(SIS_EECMD_DONE); 1058109061Smbr } else 105972197Swpaul#endif 106072197Swpaul sis_read_eeprom(sc, (caddr_t)&eaddr, 106172197Swpaul SIS_EE_NODEADDR, 3, 0); 106262672Swpaul break; 106362672Swpaul } 106462672Swpaul 106550974Swpaul sc->sis_unit = unit; 1066129636Srwatson if (debug_mpsafenet) 1067129636Srwatson callout_init(&sc->sis_stat_ch, CALLOUT_MPSAFE); 1068129636Srwatson else 1069129636Srwatson callout_init(&sc->sis_stat_ch, 0); 107050974Swpaul bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 107150974Swpaul 107281713Swpaul /* 107381713Swpaul * Allocate the parent bus DMA tag appropriate for PCI. 107481713Swpaul */ 107581713Swpaul#define SIS_NSEG_NEW 32 107681713Swpaul error = bus_dma_tag_create(NULL, /* parent */ 107781713Swpaul 1, 0, /* alignment, boundary */ 107881713Swpaul BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 107981713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 108081713Swpaul NULL, NULL, /* filter, filterarg */ 108181713Swpaul MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */ 108281713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 108381713Swpaul BUS_DMA_ALLOCNOW, /* flags */ 1084117126Sscottl NULL, NULL, /* lockfunc, lockarg */ 108581713Swpaul &sc->sis_parent_tag); 1086112872Snjl if (error) 1087112872Snjl goto fail; 108850974Swpaul 108981713Swpaul /* 1090112872Snjl * Now allocate a tag for the DMA descriptor lists and a chunk 1091112872Snjl * of DMA-able memory based on the tag. Also obtain the physical 1092112872Snjl * addresses of the RX and TX ring, which we'll need later. 109381713Swpaul * All of our lists are allocated as a contiguous block 109481713Swpaul * of memory. 109581713Swpaul */ 109681713Swpaul error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 109781713Swpaul 1, 0, /* alignment, boundary */ 109881713Swpaul BUS_SPACE_MAXADDR, /* lowaddr */ 109981713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 110081713Swpaul NULL, NULL, /* filter, filterarg */ 110181713Swpaul SIS_RX_LIST_SZ, 1, /* maxsize,nsegments */ 110281713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 110381713Swpaul 0, /* flags */ 1104117126Sscottl busdma_lock_mutex, /* lockfunc */ 1105117126Sscottl &Giant, /* lockarg */ 1106139690Sphk &sc->sis_rx_tag); 1107112872Snjl if (error) 1108112872Snjl goto fail; 110981713Swpaul 1110139690Sphk error = bus_dmamem_alloc(sc->sis_rx_tag, 1111139690Sphk (void **)&sc->sis_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1112139690Sphk &sc->sis_rx_dmamap); 1113112872Snjl 1114112872Snjl if (error) { 1115112872Snjl printf("sis%d: no memory for rx list buffers!\n", unit); 1116139690Sphk bus_dma_tag_destroy(sc->sis_rx_tag); 1117139690Sphk sc->sis_rx_tag = NULL; 1118112872Snjl goto fail; 1119112872Snjl } 1120112872Snjl 1121139690Sphk error = bus_dmamap_load(sc->sis_rx_tag, 1122139690Sphk sc->sis_rx_dmamap, &(sc->sis_rx_list[0]), 1123112872Snjl sizeof(struct sis_desc), sis_dma_map_ring, 1124139690Sphk &sc->sis_rx_paddr, 0); 1125112872Snjl 1126112872Snjl if (error) { 1127112872Snjl printf("sis%d: cannot get address of the rx ring!\n", unit); 1128139690Sphk bus_dmamem_free(sc->sis_rx_tag, 1129139690Sphk sc->sis_rx_list, sc->sis_rx_dmamap); 1130139690Sphk bus_dma_tag_destroy(sc->sis_rx_tag); 1131139690Sphk sc->sis_rx_tag = NULL; 1132112872Snjl goto fail; 1133112872Snjl } 1134112872Snjl 113581713Swpaul error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 113681713Swpaul 1, 0, /* alignment, boundary */ 113781713Swpaul BUS_SPACE_MAXADDR, /* lowaddr */ 113881713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 113981713Swpaul NULL, NULL, /* filter, filterarg */ 114081713Swpaul SIS_TX_LIST_SZ, 1, /* maxsize,nsegments */ 114181713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 114281713Swpaul 0, /* flags */ 1143117126Sscottl busdma_lock_mutex, /* lockfunc */ 1144117126Sscottl &Giant, /* lockarg */ 1145139690Sphk &sc->sis_tx_tag); 1146112872Snjl if (error) 1147112872Snjl goto fail; 114881713Swpaul 1149139690Sphk error = bus_dmamem_alloc(sc->sis_tx_tag, 1150139690Sphk (void **)&sc->sis_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1151139690Sphk &sc->sis_tx_dmamap); 115281713Swpaul 115381713Swpaul if (error) { 1154112872Snjl printf("sis%d: no memory for tx list buffers!\n", unit); 1155139690Sphk bus_dma_tag_destroy(sc->sis_tx_tag); 1156139690Sphk sc->sis_tx_tag = NULL; 115750974Swpaul goto fail; 115850974Swpaul } 115950974Swpaul 1160139690Sphk error = bus_dmamap_load(sc->sis_tx_tag, 1161139690Sphk sc->sis_tx_dmamap, &(sc->sis_tx_list[0]), 1162112872Snjl sizeof(struct sis_desc), sis_dma_map_ring, 1163139690Sphk &sc->sis_tx_paddr, 0); 116481713Swpaul 116581713Swpaul if (error) { 1166112872Snjl printf("sis%d: cannot get address of the tx ring!\n", unit); 1167139690Sphk bus_dmamem_free(sc->sis_tx_tag, 1168139690Sphk sc->sis_tx_list, sc->sis_tx_dmamap); 1169139690Sphk bus_dma_tag_destroy(sc->sis_tx_tag); 1170139690Sphk sc->sis_tx_tag = NULL; 117181713Swpaul goto fail; 117281713Swpaul } 117381713Swpaul 1174112872Snjl error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1175112872Snjl 1, 0, /* alignment, boundary */ 1176112872Snjl BUS_SPACE_MAXADDR, /* lowaddr */ 1177112872Snjl BUS_SPACE_MAXADDR, /* highaddr */ 1178112872Snjl NULL, NULL, /* filter, filterarg */ 1179112872Snjl MCLBYTES, 1, /* maxsize,nsegments */ 1180112872Snjl BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1181112872Snjl 0, /* flags */ 1182117126Sscottl busdma_lock_mutex, /* lockfunc */ 1183117126Sscottl &Giant, /* lockarg */ 1184112872Snjl &sc->sis_tag); 1185112872Snjl if (error) 1186112872Snjl goto fail; 118781713Swpaul 118881713Swpaul /* 118981713Swpaul * Obtain the physical addresses of the RX and TX 119081713Swpaul * rings which we'll need later in the init routine. 119181713Swpaul */ 119281713Swpaul 119350974Swpaul ifp = &sc->arpcom.ac_if; 119450974Swpaul ifp->if_softc = sc; 1195121816Sbrooks if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 119650974Swpaul ifp->if_mtu = ETHERMTU; 119750974Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 119850974Swpaul ifp->if_ioctl = sis_ioctl; 119950974Swpaul ifp->if_start = sis_start; 120050974Swpaul ifp->if_watchdog = sis_watchdog; 120150974Swpaul ifp->if_init = sis_init; 120250974Swpaul ifp->if_baudrate = 10000000; 1203131455Smlaier IFQ_SET_MAXLEN(&ifp->if_snd, SIS_TX_LIST_CNT - 1); 1204131455Smlaier ifp->if_snd.ifq_drv_maxlen = SIS_TX_LIST_CNT - 1; 1205131455Smlaier IFQ_SET_READY(&ifp->if_snd); 120650974Swpaul 120750974Swpaul /* 120850974Swpaul * Do MII setup. 120950974Swpaul */ 121050974Swpaul if (mii_phy_probe(dev, &sc->sis_miibus, 121150974Swpaul sis_ifmedia_upd, sis_ifmedia_sts)) { 121250974Swpaul printf("sis%d: MII without any PHY!\n", sc->sis_unit); 121350974Swpaul error = ENXIO; 121450974Swpaul goto fail; 121550974Swpaul } 121650974Swpaul 121750974Swpaul /* 121863090Sarchie * Call MI attach routine. 121950974Swpaul */ 1220106936Ssam ether_ifattach(ifp, eaddr); 122187390Sjhay 122287390Sjhay /* 122387390Sjhay * Tell the upper layer(s) we support long frames. 122487390Sjhay */ 122587390Sjhay ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1226106936Ssam ifp->if_capabilities |= IFCAP_VLAN_MTU; 122787390Sjhay 1228128138Sru#ifdef DEVICE_POLLING 1229128138Sru ifp->if_capabilities |= IFCAP_POLLING; 1230128138Sru#endif 1231128138Sru ifp->if_capenable = ifp->if_capabilities; 1232128138Sru 1233113609Snjl /* Hook interrupt last to avoid having to lock softc */ 1234121697Ssam error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET | INTR_MPSAFE, 1235112872Snjl sis_intr, sc, &sc->sis_intrhand); 123650974Swpaul 1237112872Snjl if (error) { 1238112872Snjl printf("sis%d: couldn't set up irq\n", unit); 1239113609Snjl ether_ifdetach(ifp); 1240112872Snjl goto fail; 1241112872Snjl } 1242112872Snjl 124350974Swpaulfail: 1244112872Snjl if (error) 1245112872Snjl sis_detach(dev); 1246112872Snjl 124750974Swpaul return(error); 124850974Swpaul} 124950974Swpaul 1250113609Snjl/* 1251113609Snjl * Shutdown hardware and free up resources. This can be called any 1252113609Snjl * time after the mutex has been initialized. It is called in both 1253113609Snjl * the error case in attach and the normal detach case so it needs 1254113609Snjl * to be careful about only freeing resources that have actually been 1255113609Snjl * allocated. 1256113609Snjl */ 1257102334Salfredstatic int 1258139740Sphksis_detach(device_t dev) 125950974Swpaul{ 126050974Swpaul struct sis_softc *sc; 126150974Swpaul struct ifnet *ifp; 126250974Swpaul 126350974Swpaul sc = device_get_softc(dev); 1264112880Sjhb KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized")); 126567087Swpaul SIS_LOCK(sc); 126650974Swpaul ifp = &sc->arpcom.ac_if; 126750974Swpaul 1268118089Smux /* These should only be active if attach succeeded. */ 1269113812Simp if (device_is_attached(dev)) { 1270113609Snjl sis_reset(sc); 1271113609Snjl sis_stop(sc); 1272112872Snjl ether_ifdetach(ifp); 1273113609Snjl } 1274113609Snjl if (sc->sis_miibus) 1275112872Snjl device_delete_child(dev, sc->sis_miibus); 1276113609Snjl bus_generic_detach(dev); 127750974Swpaul 1278112872Snjl if (sc->sis_intrhand) 1279112872Snjl bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1280112872Snjl if (sc->sis_irq) 1281112872Snjl bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1282112872Snjl if (sc->sis_res) 1283112872Snjl bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 128450974Swpaul 1285139690Sphk if (sc->sis_rx_tag) { 1286139690Sphk bus_dmamap_unload(sc->sis_rx_tag, 1287139690Sphk sc->sis_rx_dmamap); 1288139690Sphk bus_dmamem_free(sc->sis_rx_tag, 1289139690Sphk sc->sis_rx_list, sc->sis_rx_dmamap); 1290139690Sphk bus_dma_tag_destroy(sc->sis_rx_tag); 1291112872Snjl } 1292139690Sphk if (sc->sis_tx_tag) { 1293139690Sphk bus_dmamap_unload(sc->sis_tx_tag, 1294139690Sphk sc->sis_tx_dmamap); 1295139690Sphk bus_dmamem_free(sc->sis_tx_tag, 1296139690Sphk sc->sis_tx_list, sc->sis_tx_dmamap); 1297139690Sphk bus_dma_tag_destroy(sc->sis_tx_tag); 1298112872Snjl } 1299112872Snjl if (sc->sis_parent_tag) 1300112872Snjl bus_dma_tag_destroy(sc->sis_parent_tag); 1301112872Snjl if (sc->sis_tag) 1302112872Snjl bus_dma_tag_destroy(sc->sis_tag); 130350974Swpaul 130467087Swpaul SIS_UNLOCK(sc); 130567087Swpaul mtx_destroy(&sc->sis_mtx); 130650974Swpaul 130750974Swpaul return(0); 130850974Swpaul} 130950974Swpaul 131050974Swpaul/* 131150974Swpaul * Initialize the transmit descriptors. 131250974Swpaul */ 1313102334Salfredstatic int 1314139740Sphksis_list_tx_init(struct sis_softc *sc) 131550974Swpaul{ 131687059Sluigi int i, nexti; 131750974Swpaul 131850974Swpaul for (i = 0; i < SIS_TX_LIST_CNT; i++) { 131987102Sluigi nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1; 1320139690Sphk sc->sis_tx_list[i].sis_nextdesc = 1321139690Sphk &sc->sis_tx_list[nexti]; 1322139690Sphk bus_dmamap_load(sc->sis_tx_tag, 1323139690Sphk sc->sis_tx_dmamap, 1324139690Sphk &sc->sis_tx_list[nexti], sizeof(struct sis_desc), 1325139690Sphk sis_dma_map_desc_next, &sc->sis_tx_list[i], 0); 1326139690Sphk sc->sis_tx_list[i].sis_mbuf = NULL; 1327139690Sphk sc->sis_tx_list[i].sis_ptr = 0; 1328139690Sphk sc->sis_tx_list[i].sis_ctl = 0; 132950974Swpaul } 133050974Swpaul 1331139690Sphk sc->sis_tx_prod = sc->sis_tx_cons = sc->sis_tx_cnt = 0; 133250974Swpaul 1333139690Sphk bus_dmamap_sync(sc->sis_tx_tag, 1334139690Sphk sc->sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 133581713Swpaul 133650974Swpaul return(0); 133750974Swpaul} 133850974Swpaul 133950974Swpaul/* 134050974Swpaul * Initialize the RX descriptors and allocate mbufs for them. Note that 134150974Swpaul * we arrange the descriptors in a closed ring, so that the last descriptor 134250974Swpaul * points back to the first. 134350974Swpaul */ 1344102334Salfredstatic int 1345139740Sphksis_list_rx_init(struct sis_softc *sc) 134650974Swpaul{ 134787059Sluigi int i,nexti; 134850974Swpaul 134950974Swpaul for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1350139690Sphk if (sis_newbuf(sc, &sc->sis_rx_list[i], NULL) == ENOBUFS) 135150974Swpaul return(ENOBUFS); 135287102Sluigi nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1; 1353139690Sphk sc->sis_rx_list[i].sis_nextdesc = 1354139690Sphk &sc->sis_rx_list[nexti]; 1355139690Sphk bus_dmamap_load(sc->sis_rx_tag, 1356139690Sphk sc->sis_rx_dmamap, 1357139690Sphk &sc->sis_rx_list[nexti], 135881713Swpaul sizeof(struct sis_desc), sis_dma_map_desc_next, 1359139690Sphk &sc->sis_rx_list[i], 0); 136050974Swpaul } 136150974Swpaul 1362139690Sphk bus_dmamap_sync(sc->sis_rx_tag, 1363139690Sphk sc->sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 136481713Swpaul 1365139691Sphk sc->sis_rx_pdsc = &sc->sis_rx_list[0]; 136650974Swpaul 136750974Swpaul return(0); 136850974Swpaul} 136950974Swpaul 137050974Swpaul/* 137150974Swpaul * Initialize an RX descriptor and attach an MBUF cluster. 137250974Swpaul */ 1373102334Salfredstatic int 1374139740Sphksis_newbuf(struct sis_softc *sc, struct sis_desc *c, struct mbuf *m) 137550974Swpaul{ 137650974Swpaul 137781713Swpaul if (c == NULL) 137881713Swpaul return(EINVAL); 137981713Swpaul 138050974Swpaul if (m == NULL) { 1381111119Simp m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1382101340Sluigi if (m == NULL) 138350974Swpaul return(ENOBUFS); 1384101340Sluigi } else 1385101340Sluigi m->m_data = m->m_ext.ext_buf; 138650974Swpaul 1387101340Sluigi c->sis_mbuf = m; 138850974Swpaul c->sis_ctl = SIS_RXLEN; 138950974Swpaul 139081713Swpaul bus_dmamap_create(sc->sis_tag, 0, &c->sis_map); 139181713Swpaul bus_dmamap_load(sc->sis_tag, c->sis_map, 1392101464Sluigi mtod(m, void *), MCLBYTES, 139381713Swpaul sis_dma_map_desc_ptr, c, 0); 139481713Swpaul bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREWRITE); 139581713Swpaul 139650974Swpaul return(0); 139750974Swpaul} 139850974Swpaul 139950974Swpaul/* 140050974Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 140150974Swpaul * the higher level protocols. 140250974Swpaul */ 1403102334Salfredstatic void 1404139740Sphksis_rxeof(struct sis_softc *sc) 140550974Swpaul{ 140650974Swpaul struct mbuf *m; 140750974Swpaul struct ifnet *ifp; 140850974Swpaul struct sis_desc *cur_rx; 1409139691Sphk int total_len = 0; 141050974Swpaul u_int32_t rxstat; 141150974Swpaul 1412122689Ssam SIS_LOCK_ASSERT(sc); 1413122689Ssam 141450974Swpaul ifp = &sc->arpcom.ac_if; 141550974Swpaul 1416139691Sphk for(cur_rx = sc->sis_rx_pdsc; SIS_OWNDESC(cur_rx); 1417139691Sphk cur_rx = cur_rx->sis_nextdesc) { 141850974Swpaul 141987902Sluigi#ifdef DEVICE_POLLING 1420102052Ssobomax if (ifp->if_flags & IFF_POLLING) { 142187902Sluigi if (sc->rxcycles <= 0) 142287902Sluigi break; 142387902Sluigi sc->rxcycles--; 142487902Sluigi } 142587902Sluigi#endif /* DEVICE_POLLING */ 142650974Swpaul rxstat = cur_rx->sis_rxstat; 142781713Swpaul bus_dmamap_sync(sc->sis_tag, 142881713Swpaul cur_rx->sis_map, BUS_DMASYNC_POSTWRITE); 142981713Swpaul bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map); 143081713Swpaul bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map); 143150974Swpaul m = cur_rx->sis_mbuf; 143250974Swpaul cur_rx->sis_mbuf = NULL; 143350974Swpaul total_len = SIS_RXBYTES(cur_rx); 143450974Swpaul 143550974Swpaul /* 143650974Swpaul * If an error occurs, update stats, clear the 143750974Swpaul * status word and leave the mbuf cluster in place: 143850974Swpaul * it should simply get re-used next time this descriptor 143950974Swpaul * comes up in the ring. 144050974Swpaul */ 144150974Swpaul if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 144250974Swpaul ifp->if_ierrors++; 144350974Swpaul if (rxstat & SIS_RXSTAT_COLL) 144450974Swpaul ifp->if_collisions++; 144550974Swpaul sis_newbuf(sc, cur_rx, m); 144650974Swpaul continue; 144750974Swpaul } 144850974Swpaul 144950974Swpaul /* No errors; receive the packet. */ 145087059Sluigi#ifdef __i386__ 145187059Sluigi /* 145287059Sluigi * On the x86 we do not have alignment problems, so try to 145387059Sluigi * allocate a new buffer for the receive ring, and pass up 145487059Sluigi * the one where the packet is already, saving the expensive 145587059Sluigi * copy done in m_devget(). 145687059Sluigi * If we are on an architecture with alignment problems, or 145787059Sluigi * if the allocation fails, then use m_devget and leave the 145887059Sluigi * existing buffer in the receive ring. 145987059Sluigi */ 1460101464Sluigi if (sis_newbuf(sc, cur_rx, NULL) == 0) 146187059Sluigi m->m_pkthdr.len = m->m_len = total_len; 1462101464Sluigi else 146387059Sluigi#endif 146487059Sluigi { 146587059Sluigi struct mbuf *m0; 146687059Sluigi m0 = m_devget(mtod(m, char *), total_len, 146787059Sluigi ETHER_ALIGN, ifp, NULL); 146887059Sluigi sis_newbuf(sc, cur_rx, m); 146987059Sluigi if (m0 == NULL) { 147087059Sluigi ifp->if_ierrors++; 147187059Sluigi continue; 147287059Sluigi } 147387059Sluigi m = m0; 147450974Swpaul } 147550974Swpaul 147650974Swpaul ifp->if_ipackets++; 1477106936Ssam m->m_pkthdr.rcvif = ifp; 1478106936Ssam 1479122689Ssam SIS_UNLOCK(sc); 1480106936Ssam (*ifp->if_input)(ifp, m); 1481122689Ssam SIS_LOCK(sc); 148250974Swpaul } 148350974Swpaul 1484139691Sphk sc->sis_rx_pdsc = cur_rx; 148550974Swpaul} 148650974Swpaul 1487105219Sphkstatic void 1488139715Sphksis_rxeoc(struct sis_softc *sc) 148950974Swpaul{ 1490139715Sphk 1491139715Sphk SIS_LOCK_ASSERT(sc); 149250974Swpaul sis_rxeof(sc); 1493139715Sphk sis_initl(sc); 149450974Swpaul} 149550974Swpaul 149650974Swpaul/* 149750974Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 149850974Swpaul * the list buffers. 149950974Swpaul */ 150050974Swpaul 1501102334Salfredstatic void 1502139740Sphksis_txeof(struct sis_softc *sc) 150350974Swpaul{ 150450974Swpaul struct ifnet *ifp; 150550974Swpaul u_int32_t idx; 150650974Swpaul 1507139715Sphk SIS_LOCK_ASSERT(sc); 150850974Swpaul ifp = &sc->arpcom.ac_if; 150950974Swpaul 151050974Swpaul /* 151150974Swpaul * Go through our tx list and free mbufs for those 151250974Swpaul * frames that have been transmitted. 151350974Swpaul */ 1514139690Sphk for (idx = sc->sis_tx_cons; sc->sis_tx_cnt > 0; 1515139690Sphk sc->sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) { 1516139690Sphk struct sis_desc *cur_tx = &sc->sis_tx_list[idx]; 151750974Swpaul 151850974Swpaul if (SIS_OWNDESC(cur_tx)) 151950974Swpaul break; 152050974Swpaul 152199163Sluigi if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) 152250974Swpaul continue; 152350974Swpaul 152450974Swpaul if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 152550974Swpaul ifp->if_oerrors++; 152650974Swpaul if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 152750974Swpaul ifp->if_collisions++; 152850974Swpaul if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 152950974Swpaul ifp->if_collisions++; 153050974Swpaul } 153150974Swpaul 153250974Swpaul ifp->if_collisions += 153350974Swpaul (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 153450974Swpaul 153550974Swpaul ifp->if_opackets++; 153650974Swpaul if (cur_tx->sis_mbuf != NULL) { 153750974Swpaul m_freem(cur_tx->sis_mbuf); 153850974Swpaul cur_tx->sis_mbuf = NULL; 153981713Swpaul bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map); 154081713Swpaul bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map); 154150974Swpaul } 154299163Sluigi } 154350974Swpaul 1544139690Sphk if (idx != sc->sis_tx_cons) { 154599163Sluigi /* we freed up some buffers */ 1546139690Sphk sc->sis_tx_cons = idx; 154799163Sluigi ifp->if_flags &= ~IFF_OACTIVE; 154850974Swpaul } 154950974Swpaul 1550139690Sphk ifp->if_timer = (sc->sis_tx_cnt == 0) ? 0 : 5; 155150974Swpaul 155250974Swpaul return; 155350974Swpaul} 155450974Swpaul 1555102334Salfredstatic void 1556139740Sphksis_tick(void *xsc) 155750974Swpaul{ 155850974Swpaul struct sis_softc *sc; 155950974Swpaul struct mii_data *mii; 156064963Swpaul struct ifnet *ifp; 156150974Swpaul 156250974Swpaul sc = xsc; 156367087Swpaul SIS_LOCK(sc); 1564117858Scognet sc->in_tick = 1; 156564963Swpaul ifp = &sc->arpcom.ac_if; 156664963Swpaul 156750974Swpaul mii = device_get_softc(sc->sis_miibus); 156850974Swpaul mii_tick(mii); 156964963Swpaul 157084147Sjlemon if (!sc->sis_link && mii->mii_media_status & IFM_ACTIVE && 157184147Sjlemon IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 157284147Sjlemon sc->sis_link++; 1573131455Smlaier if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1574139714Sphk sis_startl(ifp); 157564963Swpaul } 157664963Swpaul 1577119785Ssam callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 1578117858Scognet sc->in_tick = 0; 157967087Swpaul SIS_UNLOCK(sc); 158050974Swpaul} 158150974Swpaul 158287902Sluigi#ifdef DEVICE_POLLING 158387902Sluigistatic poll_handler_t sis_poll; 158487902Sluigi 158587902Sluigistatic void 158687902Sluigisis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 158787902Sluigi{ 158887973Speter struct sis_softc *sc = ifp->if_softc; 158987973Speter 159087902Sluigi SIS_LOCK(sc); 1591128138Sru if (!(ifp->if_capenable & IFCAP_POLLING)) { 1592128138Sru ether_poll_deregister(ifp); 1593128138Sru cmd = POLL_DEREGISTER; 1594128138Sru } 159587902Sluigi if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 159687902Sluigi CSR_WRITE_4(sc, SIS_IER, 1); 159787902Sluigi goto done; 159887902Sluigi } 159987902Sluigi 160087902Sluigi /* 160187902Sluigi * On the sis, reading the status register also clears it. 160287902Sluigi * So before returning to intr mode we must make sure that all 160387902Sluigi * possible pending sources of interrupts have been served. 160487902Sluigi * In practice this means run to completion the *eof routines, 160587902Sluigi * and then call the interrupt routine 160687902Sluigi */ 160787902Sluigi sc->rxcycles = count; 160887902Sluigi sis_rxeof(sc); 160987902Sluigi sis_txeof(sc); 1610131455Smlaier if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1611139714Sphk sis_startl(ifp); 161287902Sluigi 161387902Sluigi if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 161487902Sluigi u_int32_t status; 161587902Sluigi 161687902Sluigi /* Reading the ISR register clears all interrupts. */ 161787902Sluigi status = CSR_READ_4(sc, SIS_ISR); 161887902Sluigi 161987902Sluigi if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 162087902Sluigi sis_rxeoc(sc); 162187902Sluigi 162287902Sluigi if (status & (SIS_ISR_RX_IDLE)) 162387902Sluigi SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 162487902Sluigi 162587902Sluigi if (status & SIS_ISR_SYSERR) { 162687902Sluigi sis_reset(sc); 1627139715Sphk sis_initl(sc); 162887902Sluigi } 162987902Sluigi } 163087902Sluigidone: 163187902Sluigi SIS_UNLOCK(sc); 163287902Sluigi} 163387902Sluigi#endif /* DEVICE_POLLING */ 163487902Sluigi 1635102334Salfredstatic void 1636139740Sphksis_intr(void *arg) 163750974Swpaul{ 163850974Swpaul struct sis_softc *sc; 163950974Swpaul struct ifnet *ifp; 164050974Swpaul u_int32_t status; 164150974Swpaul 164250974Swpaul sc = arg; 164350974Swpaul ifp = &sc->arpcom.ac_if; 164450974Swpaul 164586984Sluigi SIS_LOCK(sc); 164687902Sluigi#ifdef DEVICE_POLLING 1647102052Ssobomax if (ifp->if_flags & IFF_POLLING) 164887902Sluigi goto done; 1649128138Sru if ((ifp->if_capenable & IFCAP_POLLING) && 1650128138Sru ether_poll_register(sis_poll, ifp)) { /* ok, disable interrupts */ 165187902Sluigi CSR_WRITE_4(sc, SIS_IER, 0); 165287902Sluigi goto done; 165387902Sluigi } 165487902Sluigi#endif /* DEVICE_POLLING */ 165587902Sluigi 165650974Swpaul /* Supress unwanted interrupts */ 165750974Swpaul if (!(ifp->if_flags & IFF_UP)) { 165850974Swpaul sis_stop(sc); 165986984Sluigi goto done; 166050974Swpaul } 166150974Swpaul 166250974Swpaul /* Disable interrupts. */ 166350974Swpaul CSR_WRITE_4(sc, SIS_IER, 0); 166450974Swpaul 166550974Swpaul for (;;) { 1666139717Sphk SIS_LOCK_ASSERT(sc); 166750974Swpaul /* Reading the ISR register clears all interrupts. */ 166850974Swpaul status = CSR_READ_4(sc, SIS_ISR); 166950974Swpaul 167050974Swpaul if ((status & SIS_INTRS) == 0) 167150974Swpaul break; 167250974Swpaul 167386984Sluigi if (status & 167486984Sluigi (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | 167586984Sluigi SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) ) 167650974Swpaul sis_txeof(sc); 167750974Swpaul 167886984Sluigi if (status & (SIS_ISR_RX_DESC_OK|SIS_ISR_RX_OK|SIS_ISR_RX_IDLE)) 167950974Swpaul sis_rxeof(sc); 168050974Swpaul 168186984Sluigi if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW)) 168250974Swpaul sis_rxeoc(sc); 168350974Swpaul 168486984Sluigi if (status & (SIS_ISR_RX_IDLE)) 168586984Sluigi SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 168686984Sluigi 168750974Swpaul if (status & SIS_ISR_SYSERR) { 168850974Swpaul sis_reset(sc); 1689139715Sphk sis_initl(sc); 169050974Swpaul } 169150974Swpaul } 169250974Swpaul 169350974Swpaul /* Re-enable interrupts. */ 169450974Swpaul CSR_WRITE_4(sc, SIS_IER, 1); 169550974Swpaul 1696131455Smlaier if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1697139714Sphk sis_startl(ifp); 169886984Sluigidone: 169967087Swpaul SIS_UNLOCK(sc); 170067087Swpaul 170150974Swpaul return; 170250974Swpaul} 170350974Swpaul 170450974Swpaul/* 170550974Swpaul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 170650974Swpaul * pointers to the fragment pointers. 170750974Swpaul */ 1708102334Salfredstatic int 1709139740Sphksis_encap(struct sis_softc *sc, struct mbuf **m_head, uint32_t *txidx) 171050974Swpaul{ 171150974Swpaul struct sis_desc *f = NULL; 171250974Swpaul struct mbuf *m; 1713112808Ssilby int frag, cur, cnt = 0, chainlen = 0; 171450974Swpaul 171550974Swpaul /* 1716112808Ssilby * If there's no way we can send any packets, return now. 1717112808Ssilby */ 1718139690Sphk if (SIS_TX_LIST_CNT - sc->sis_tx_cnt < 2) 1719112808Ssilby return (ENOBUFS); 1720112808Ssilby 1721112808Ssilby /* 1722112808Ssilby * Count the number of frags in this chain to see if 1723112808Ssilby * we need to m_defrag. Since the descriptor list is shared 1724112808Ssilby * by all packets, we'll m_defrag long chains so that they 1725112808Ssilby * do not use up the entire list, even if they would fit. 1726112808Ssilby */ 1727112808Ssilby 1728121262Ssilby for (m = *m_head; m != NULL; m = m->m_next) 1729112808Ssilby chainlen++; 1730112808Ssilby 1731112808Ssilby if ((chainlen > SIS_TX_LIST_CNT / 4) || 1732139690Sphk ((SIS_TX_LIST_CNT - (chainlen + sc->sis_tx_cnt)) < 2)) { 1733121262Ssilby m = m_defrag(*m_head, M_DONTWAIT); 1734112808Ssilby if (m == NULL) 1735112808Ssilby return (ENOBUFS); 1736121262Ssilby *m_head = m; 1737112808Ssilby } 1738112808Ssilby 1739112808Ssilby /* 174050974Swpaul * Start packing the mbufs in this chain into 174150974Swpaul * the fragment pointers. Stop when we run out 174250974Swpaul * of fragments or hit the end of the mbuf chain. 174350974Swpaul */ 174450974Swpaul cur = frag = *txidx; 174550974Swpaul 1746121262Ssilby for (m = *m_head; m != NULL; m = m->m_next) { 174750974Swpaul if (m->m_len != 0) { 174851042Swpaul if ((SIS_TX_LIST_CNT - 1749139690Sphk (sc->sis_tx_cnt + cnt)) < 2) 175050974Swpaul return(ENOBUFS); 1751139690Sphk f = &sc->sis_tx_list[frag]; 175250974Swpaul f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; 175381713Swpaul bus_dmamap_create(sc->sis_tag, 0, &f->sis_map); 175481713Swpaul bus_dmamap_load(sc->sis_tag, f->sis_map, 175581713Swpaul mtod(m, void *), m->m_len, 175681713Swpaul sis_dma_map_desc_ptr, f, 0); 175781713Swpaul bus_dmamap_sync(sc->sis_tag, 175881713Swpaul f->sis_map, BUS_DMASYNC_PREREAD); 175950974Swpaul if (cnt != 0) 176050974Swpaul f->sis_ctl |= SIS_CMDSTS_OWN; 176150974Swpaul cur = frag; 176250974Swpaul SIS_INC(frag, SIS_TX_LIST_CNT); 176350974Swpaul cnt++; 176450974Swpaul } 176550974Swpaul } 176650974Swpaul 176750974Swpaul if (m != NULL) 176850974Swpaul return(ENOBUFS); 176950974Swpaul 1770139690Sphk sc->sis_tx_list[cur].sis_mbuf = *m_head; 1771139690Sphk sc->sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1772139690Sphk sc->sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1773139690Sphk sc->sis_tx_cnt += cnt; 177450974Swpaul *txidx = frag; 177550974Swpaul 177650974Swpaul return(0); 177750974Swpaul} 177850974Swpaul 177950974Swpaul/* 178050974Swpaul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 178150974Swpaul * to the mbuf data regions directly in the transmit lists. We also save a 178250974Swpaul * copy of the pointers since the transmit list fragment pointers are 178350974Swpaul * physical addresses. 178450974Swpaul */ 178550974Swpaul 1786102334Salfredstatic void 1787139717Sphksis_start(struct ifnet *ifp) 178850974Swpaul{ 178950974Swpaul struct sis_softc *sc; 1790139714Sphk 1791139714Sphk sc = ifp->if_softc; 1792139714Sphk SIS_LOCK(sc); 1793139714Sphk sis_startl(ifp); 1794139714Sphk SIS_UNLOCK(sc); 1795139714Sphk} 1796139714Sphk 1797139714Sphkstatic void 1798139714Sphksis_startl(struct ifnet *ifp) 1799139714Sphk{ 1800139714Sphk struct sis_softc *sc; 180150974Swpaul struct mbuf *m_head = NULL; 1802136269Smlaier u_int32_t idx, queued = 0; 180350974Swpaul 180450974Swpaul sc = ifp->if_softc; 180550974Swpaul 1806139714Sphk SIS_LOCK_ASSERT(sc); 1807139714Sphk 1808139714Sphk if (!sc->sis_link) 180964963Swpaul return; 181064963Swpaul 1811139690Sphk idx = sc->sis_tx_prod; 181250974Swpaul 1813139714Sphk if (ifp->if_flags & IFF_OACTIVE) 181450974Swpaul return; 181550974Swpaul 1816139690Sphk while(sc->sis_tx_list[idx].sis_mbuf == NULL) { 1817131455Smlaier IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 181850974Swpaul if (m_head == NULL) 181950974Swpaul break; 182050974Swpaul 1821121262Ssilby if (sis_encap(sc, &m_head, &idx)) { 1822131455Smlaier IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 182350974Swpaul ifp->if_flags |= IFF_OACTIVE; 182450974Swpaul break; 182550974Swpaul } 182650974Swpaul 1827136269Smlaier queued++; 1828136269Smlaier 182950974Swpaul /* 183050974Swpaul * If there's a BPF listener, bounce a copy of this frame 183150974Swpaul * to him. 183250974Swpaul */ 1833106936Ssam BPF_MTAP(ifp, m_head); 183451583Swpaul 183550974Swpaul } 183650974Swpaul 1837136269Smlaier if (queued) { 1838136269Smlaier /* Transmit */ 1839139690Sphk sc->sis_tx_prod = idx; 1840136269Smlaier SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 184150974Swpaul 1842136269Smlaier /* 1843136269Smlaier * Set a timeout in case the chip goes out to lunch. 1844136269Smlaier */ 1845136269Smlaier ifp->if_timer = 5; 1846136269Smlaier } 184750974Swpaul} 184850974Swpaul 1849102334Salfredstatic void 1850139715Sphksis_init(void *xsc) 185150974Swpaul{ 185250974Swpaul struct sis_softc *sc = xsc; 1853139715Sphk 1854139715Sphk SIS_LOCK(sc); 1855139717Sphk sis_initl(sc); 1856139715Sphk SIS_UNLOCK(sc); 1857139715Sphk} 1858139715Sphk 1859139715Sphkstatic void 1860139717Sphksis_initl(struct sis_softc *sc) 1861139715Sphk{ 186250974Swpaul struct ifnet *ifp = &sc->arpcom.ac_if; 186350974Swpaul struct mii_data *mii; 186450974Swpaul 1865139715Sphk SIS_LOCK_ASSERT(sc); 186650974Swpaul 186750974Swpaul /* 186850974Swpaul * Cancel pending I/O and free all RX/TX buffers. 186950974Swpaul */ 187050974Swpaul sis_stop(sc); 1871123833Sphk sc->sis_stopped = 0; 187250974Swpaul 1873119712Sphk#ifdef notyet 1874119712Sphk if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) { 1875119712Sphk /* 1876119712Sphk * Configure 400usec of interrupt holdoff. This is based 1877119712Sphk * on emperical tests on a Soekris 4801. 1878119712Sphk */ 1879119712Sphk CSR_WRITE_4(sc, NS_IHR, 0x100 | 4); 1880119712Sphk } 1881119712Sphk#endif 1882119712Sphk 188350974Swpaul mii = device_get_softc(sc->sis_miibus); 188450974Swpaul 188550974Swpaul /* Set MAC address */ 188662672Swpaul if (sc->sis_type == SIS_TYPE_83815) { 188762672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 188862672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 188962672Swpaul ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 189062672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 189162672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 189262672Swpaul ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 189362672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 189462672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 189562672Swpaul ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 189662672Swpaul } else { 189762672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 189862672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 189962672Swpaul ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 190062672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 190162672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 190262672Swpaul ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 190362672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 190462672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 190562672Swpaul ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 190662672Swpaul } 190750974Swpaul 190850974Swpaul /* Init circular RX list. */ 190950974Swpaul if (sis_list_rx_init(sc) == ENOBUFS) { 191050974Swpaul printf("sis%d: initialization failed: no " 191150974Swpaul "memory for rx buffers\n", sc->sis_unit); 191250974Swpaul sis_stop(sc); 191350974Swpaul return; 191450974Swpaul } 191550974Swpaul 191650974Swpaul /* 191750974Swpaul * Init tx descriptors. 191850974Swpaul */ 191950974Swpaul sis_list_tx_init(sc); 192050974Swpaul 192162672Swpaul /* 1922123491Sphk * Page 78 of the DP83815 data sheet (september 2002 version) 1923123491Sphk * recommends the following register settings "for optimum 1924123491Sphk * performance." for rev 15C. The driver from NS also sets 1925123491Sphk * the PHY_CR register for later versions. 1926123491Sphk */ 1927123491Sphk if (sc->sis_type == SIS_TYPE_83815) { 1928123491Sphk CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 1929123491Sphk /* DC speed = 01 */ 1930123491Sphk CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 1931123491Sphk if (sc->sis_srr == NS_SRR_15C) { 1932123491Sphk /* set val for c2 */ 1933123491Sphk CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 1934123491Sphk /* load/kill c2 */ 1935123491Sphk CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 1936123491Sphk /* rais SD off, from 4 to c */ 1937123491Sphk CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 1938123491Sphk } 1939123491Sphk CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 1940123491Sphk } 1941123491Sphk 1942123491Sphk 1943123491Sphk /* 194462672Swpaul * For the NatSemi chip, we have to explicitly enable the 194562672Swpaul * reception of ARP frames, as well as turn on the 'perfect 194662672Swpaul * match' filter where we store the station address, otherwise 194762672Swpaul * we won't receive unicasts meant for this host. 194862672Swpaul */ 194962672Swpaul if (sc->sis_type == SIS_TYPE_83815) { 195062672Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 195162672Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 195262672Swpaul } 195362672Swpaul 195450974Swpaul /* If we want promiscuous mode, set the allframes bit. */ 195550974Swpaul if (ifp->if_flags & IFF_PROMISC) { 195650974Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 195750974Swpaul } else { 195850974Swpaul SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 195950974Swpaul } 196050974Swpaul 196150974Swpaul /* 196250974Swpaul * Set the capture broadcast bit to capture broadcast frames. 196350974Swpaul */ 196450974Swpaul if (ifp->if_flags & IFF_BROADCAST) { 196550974Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 196650974Swpaul } else { 196750974Swpaul SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 196850974Swpaul } 196950974Swpaul 197050974Swpaul /* 197150974Swpaul * Load the multicast filter. 197250974Swpaul */ 197362672Swpaul if (sc->sis_type == SIS_TYPE_83815) 197462672Swpaul sis_setmulti_ns(sc); 197562672Swpaul else 197662672Swpaul sis_setmulti_sis(sc); 197750974Swpaul 197850974Swpaul /* Turn the receive filter on */ 197950974Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 198050974Swpaul 198150974Swpaul /* 198250974Swpaul * Load the address of the RX and TX lists. 198350974Swpaul */ 1984139690Sphk CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_rx_paddr); 1985139690Sphk CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_tx_paddr); 198650974Swpaul 1987109059Smbr /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of 1988109059Smbr * the PCI bus. When this bit is set, the Max DMA Burst Size 1989109059Smbr * for TX/RX DMA should be no larger than 16 double words. 1990109059Smbr */ 1991109059Smbr if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) { 1992109059Smbr CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); 1993109059Smbr } else { 1994109059Smbr CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); 1995109059Smbr } 199664963Swpaul 199787390Sjhay /* Accept Long Packets for VLAN support */ 199887390Sjhay SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 199987390Sjhay 200050974Swpaul /* Set TX configuration */ 200164963Swpaul if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 200264963Swpaul CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 200364963Swpaul } else { 200464963Swpaul CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 200564963Swpaul } 200650974Swpaul 200764963Swpaul /* Set full/half duplex mode. */ 200864963Swpaul if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 200964963Swpaul SIS_SETBIT(sc, SIS_TX_CFG, 201064963Swpaul (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 201164963Swpaul SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 201264963Swpaul } else { 201364963Swpaul SIS_CLRBIT(sc, SIS_TX_CFG, 201464963Swpaul (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 201564963Swpaul SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 201664963Swpaul } 201764963Swpaul 2018119712Sphk if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr < NS_SRR_16A && 2019119130Ssam IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 2020119130Ssam uint32_t reg; 2021119130Ssam 2022119130Ssam /* 2023119130Ssam * Some DP83815s experience problems when used with short 2024119130Ssam * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 2025119130Ssam * sequence adjusts the DSP's signal attenuation to fix the 2026119130Ssam * problem. 2027119130Ssam */ 2028119130Ssam CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 2029119130Ssam 2030119130Ssam reg = CSR_READ_4(sc, NS_PHY_DSPCFG); 2031123491Sphk /* Allow coefficient to be read */ 2032119130Ssam CSR_WRITE_4(sc, NS_PHY_DSPCFG, (reg & 0xfff) | 0x1000); 2033119130Ssam DELAY(100); 2034119130Ssam reg = CSR_READ_4(sc, NS_PHY_TDATA); 2035123491Sphk if ((reg & 0x0080) == 0 || 2036123491Sphk (reg > 0xd8 && reg <= 0xff)) { 2037119712Sphk device_printf(sc->sis_self, "Applying short cable fix (reg=%x)\n", reg); 2038119130Ssam CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8); 2039123491Sphk /* Adjust coefficient and prevent change */ 2040119130Ssam SIS_SETBIT(sc, NS_PHY_DSPCFG, 0x20); 2041119130Ssam } 2042119130Ssam CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 2043119130Ssam } 2044119130Ssam 204550974Swpaul /* 204650974Swpaul * Enable interrupts. 204750974Swpaul */ 204850974Swpaul CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 204987902Sluigi#ifdef DEVICE_POLLING 205087902Sluigi /* 205187902Sluigi * ... only enable interrupts if we are not polling, make sure 205287902Sluigi * they are off otherwise. 205387902Sluigi */ 2054102052Ssobomax if (ifp->if_flags & IFF_POLLING) 205587902Sluigi CSR_WRITE_4(sc, SIS_IER, 0); 205687902Sluigi else 205787902Sluigi#endif /* DEVICE_POLLING */ 205850974Swpaul CSR_WRITE_4(sc, SIS_IER, 1); 205950974Swpaul 206050974Swpaul /* Enable receiver and transmitter. */ 206150974Swpaul SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 206250974Swpaul SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 206350974Swpaul 206464963Swpaul#ifdef notdef 206550974Swpaul mii_mediachg(mii); 206664963Swpaul#endif 206750974Swpaul 206850974Swpaul ifp->if_flags |= IFF_RUNNING; 206950974Swpaul ifp->if_flags &= ~IFF_OACTIVE; 207050974Swpaul 2071117858Scognet if (!sc->in_tick) 2072119785Ssam callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 207350974Swpaul} 207450974Swpaul 207550974Swpaul/* 207650974Swpaul * Set media options. 207750974Swpaul */ 2078102334Salfredstatic int 2079139740Sphksis_ifmedia_upd(struct ifnet *ifp) 208050974Swpaul{ 208150974Swpaul struct sis_softc *sc; 208264963Swpaul struct mii_data *mii; 208350974Swpaul 208450974Swpaul sc = ifp->if_softc; 208550974Swpaul 208664963Swpaul mii = device_get_softc(sc->sis_miibus); 208764963Swpaul sc->sis_link = 0; 208864963Swpaul if (mii->mii_instance) { 208964963Swpaul struct mii_softc *miisc; 209072012Sphk LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 209164963Swpaul mii_phy_reset(miisc); 209264963Swpaul } 209364963Swpaul mii_mediachg(mii); 209450974Swpaul 209550974Swpaul return(0); 209650974Swpaul} 209750974Swpaul 209850974Swpaul/* 209950974Swpaul * Report current media status. 210050974Swpaul */ 2101102334Salfredstatic void 2102139740Sphksis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 210350974Swpaul{ 210450974Swpaul struct sis_softc *sc; 210550974Swpaul struct mii_data *mii; 210650974Swpaul 210750974Swpaul sc = ifp->if_softc; 210850974Swpaul 210950974Swpaul mii = device_get_softc(sc->sis_miibus); 211050974Swpaul mii_pollstat(mii); 211150974Swpaul ifmr->ifm_active = mii->mii_media_active; 211250974Swpaul ifmr->ifm_status = mii->mii_media_status; 211350974Swpaul} 211450974Swpaul 2115102334Salfredstatic int 2116139740Sphksis_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 211750974Swpaul{ 211850974Swpaul struct sis_softc *sc = ifp->if_softc; 211950974Swpaul struct ifreq *ifr = (struct ifreq *) data; 212050974Swpaul struct mii_data *mii; 212167087Swpaul int error = 0; 212250974Swpaul 212350974Swpaul switch(command) { 212450974Swpaul case SIOCSIFFLAGS: 212550974Swpaul if (ifp->if_flags & IFF_UP) { 212650974Swpaul sis_init(sc); 2127139741Sphk } else if (ifp->if_flags & IFF_RUNNING) { 2128139741Sphk SIS_LOCK(sc); 2129139741Sphk sis_stop(sc); 2130139741Sphk SIS_UNLOCK(sc); 213150974Swpaul } 213250974Swpaul error = 0; 213350974Swpaul break; 213450974Swpaul case SIOCADDMULTI: 213550974Swpaul case SIOCDELMULTI: 213681713Swpaul SIS_LOCK(sc); 213762672Swpaul if (sc->sis_type == SIS_TYPE_83815) 213862672Swpaul sis_setmulti_ns(sc); 213962672Swpaul else 214062672Swpaul sis_setmulti_sis(sc); 214181713Swpaul SIS_UNLOCK(sc); 214250974Swpaul error = 0; 214350974Swpaul break; 214450974Swpaul case SIOCGIFMEDIA: 214550974Swpaul case SIOCSIFMEDIA: 214650974Swpaul mii = device_get_softc(sc->sis_miibus); 214781713Swpaul SIS_LOCK(sc); 214850974Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 214981713Swpaul SIS_UNLOCK(sc); 215050974Swpaul break; 2151128138Sru case SIOCSIFCAP: 2152129633Syar ifp->if_capenable &= ~IFCAP_POLLING; 2153129633Syar ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_POLLING; 2154128138Sru break; 215550974Swpaul default: 2156106936Ssam error = ether_ioctl(ifp, command, data); 215750974Swpaul break; 215850974Swpaul } 215950974Swpaul 216050974Swpaul return(error); 216150974Swpaul} 216250974Swpaul 2163102334Salfredstatic void 2164139740Sphksis_watchdog(struct ifnet *ifp) 216550974Swpaul{ 2166139797Sphk struct sis_softc *sc; 216750974Swpaul 216850974Swpaul sc = ifp->if_softc; 216950974Swpaul 217067087Swpaul SIS_LOCK(sc); 2171139797Sphk if (sc->sis_stopped) { 2172139797Sphk SIS_UNLOCK(sc); 2173139797Sphk return; 2174139797Sphk } 217567087Swpaul 217650974Swpaul ifp->if_oerrors++; 217750974Swpaul printf("sis%d: watchdog timeout\n", sc->sis_unit); 217850974Swpaul 217950974Swpaul sis_stop(sc); 218050974Swpaul sis_reset(sc); 2181139715Sphk sis_initl(sc); 218250974Swpaul 2183131455Smlaier if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2184139714Sphk sis_startl(ifp); 218550974Swpaul 218667087Swpaul SIS_UNLOCK(sc); 218750974Swpaul} 218850974Swpaul 218950974Swpaul/* 219050974Swpaul * Stop the adapter and free any mbufs allocated to the 219150974Swpaul * RX and TX lists. 219250974Swpaul */ 2193102334Salfredstatic void 2194139740Sphksis_stop(struct sis_softc *sc) 219550974Swpaul{ 2196139708Sphk int i; 219750974Swpaul struct ifnet *ifp; 219850974Swpaul 2199123833Sphk if (sc->sis_stopped) 2200123833Sphk return; 2201139717Sphk SIS_LOCK_ASSERT(sc); 220250974Swpaul ifp = &sc->arpcom.ac_if; 220350974Swpaul ifp->if_timer = 0; 220450974Swpaul 2205119785Ssam callout_stop(&sc->sis_stat_ch); 220687472Speter 220787472Speter ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 220887902Sluigi#ifdef DEVICE_POLLING 220987902Sluigi ether_poll_deregister(ifp); 221087902Sluigi#endif 221150974Swpaul CSR_WRITE_4(sc, SIS_IER, 0); 221250974Swpaul CSR_WRITE_4(sc, SIS_IMR, 0); 2213139798Sphk CSR_READ_4(sc, SIS_ISR); /* clear any interrupts already pending */ 221450974Swpaul SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 221550974Swpaul DELAY(1000); 221650974Swpaul CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 221750974Swpaul CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 221850974Swpaul 221964963Swpaul sc->sis_link = 0; 222064963Swpaul 222150974Swpaul /* 222250974Swpaul * Free data in the RX lists. 222350974Swpaul */ 222450974Swpaul for (i = 0; i < SIS_RX_LIST_CNT; i++) { 2225139690Sphk if (sc->sis_rx_list[i].sis_mbuf != NULL) { 222681713Swpaul bus_dmamap_unload(sc->sis_tag, 2227139690Sphk sc->sis_rx_list[i].sis_map); 222881713Swpaul bus_dmamap_destroy(sc->sis_tag, 2229139690Sphk sc->sis_rx_list[i].sis_map); 2230139690Sphk m_freem(sc->sis_rx_list[i].sis_mbuf); 2231139690Sphk sc->sis_rx_list[i].sis_mbuf = NULL; 223250974Swpaul } 223350974Swpaul } 2234139690Sphk bzero(sc->sis_rx_list, 2235139690Sphk sizeof(sc->sis_rx_list)); 223650974Swpaul 223750974Swpaul /* 223850974Swpaul * Free the TX list buffers. 223950974Swpaul */ 224050974Swpaul for (i = 0; i < SIS_TX_LIST_CNT; i++) { 2241139690Sphk if (sc->sis_tx_list[i].sis_mbuf != NULL) { 224281713Swpaul bus_dmamap_unload(sc->sis_tag, 2243139690Sphk sc->sis_tx_list[i].sis_map); 224481713Swpaul bus_dmamap_destroy(sc->sis_tag, 2245139690Sphk sc->sis_tx_list[i].sis_map); 2246139690Sphk m_freem(sc->sis_tx_list[i].sis_mbuf); 2247139690Sphk sc->sis_tx_list[i].sis_mbuf = NULL; 224850974Swpaul } 224950974Swpaul } 225050974Swpaul 2251139690Sphk bzero(sc->sis_tx_list, 2252139690Sphk sizeof(sc->sis_tx_list)); 225350974Swpaul 2254123833Sphk sc->sis_stopped = 1; 225550974Swpaul} 225650974Swpaul 225750974Swpaul/* 225850974Swpaul * Stop all chip I/O so that the kernel's probe routines don't 225950974Swpaul * get confused by errant DMAs when rebooting. 226050974Swpaul */ 2261102334Salfredstatic void 2262139717Sphksis_shutdown(device_t dev) 226350974Swpaul{ 226450974Swpaul struct sis_softc *sc; 226550974Swpaul 226650974Swpaul sc = device_get_softc(dev); 226767087Swpaul SIS_LOCK(sc); 226850974Swpaul sis_reset(sc); 226950974Swpaul sis_stop(sc); 227067087Swpaul SIS_UNLOCK(sc); 227150974Swpaul} 2272139800Sphk 2273139800Sphkstatic device_method_t sis_methods[] = { 2274139800Sphk /* Device interface */ 2275139800Sphk DEVMETHOD(device_probe, sis_probe), 2276139800Sphk DEVMETHOD(device_attach, sis_attach), 2277139800Sphk DEVMETHOD(device_detach, sis_detach), 2278139800Sphk DEVMETHOD(device_shutdown, sis_shutdown), 2279139800Sphk 2280139800Sphk /* bus interface */ 2281139800Sphk DEVMETHOD(bus_print_child, bus_generic_print_child), 2282139800Sphk DEVMETHOD(bus_driver_added, bus_generic_driver_added), 2283139800Sphk 2284139800Sphk /* MII interface */ 2285139800Sphk DEVMETHOD(miibus_readreg, sis_miibus_readreg), 2286139800Sphk DEVMETHOD(miibus_writereg, sis_miibus_writereg), 2287139800Sphk DEVMETHOD(miibus_statchg, sis_miibus_statchg), 2288139800Sphk 2289139800Sphk { 0, 0 } 2290139800Sphk}; 2291139800Sphk 2292139800Sphkstatic driver_t sis_driver = { 2293139800Sphk "sis", 2294139800Sphk sis_methods, 2295139800Sphk sizeof(struct sis_softc) 2296139800Sphk}; 2297139800Sphk 2298139800Sphkstatic devclass_t sis_devclass; 2299139800Sphk 2300139800SphkDRIVER_MODULE(sis, pci, sis_driver, sis_devclass, 0, 0); 2301139800SphkDRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 2302