if_sis.c revision 139798
150974Swpaul/* 2139740Sphk * Copyright (c) 2005 Poul-Henning Kamp <phk@FreeBSD.org> 350974Swpaul * Copyright (c) 1997, 1998, 1999 450974Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 550974Swpaul * 650974Swpaul * Redistribution and use in source and binary forms, with or without 750974Swpaul * modification, are permitted provided that the following conditions 850974Swpaul * are met: 950974Swpaul * 1. Redistributions of source code must retain the above copyright 1050974Swpaul * notice, this list of conditions and the following disclaimer. 1150974Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1250974Swpaul * notice, this list of conditions and the following disclaimer in the 1350974Swpaul * documentation and/or other materials provided with the distribution. 1450974Swpaul * 3. All advertising materials mentioning features or use of this software 1550974Swpaul * must display the following acknowledgement: 1650974Swpaul * This product includes software developed by Bill Paul. 1750974Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1850974Swpaul * may be used to endorse or promote products derived from this software 1950974Swpaul * without specific prior written permission. 2050974Swpaul * 2150974Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2250974Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2350974Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2450974Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2550974Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2650974Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2750974Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2850974Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2950974Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3050974Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3150974Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3250974Swpaul */ 3350974Swpaul 34122678Sobrien#include <sys/cdefs.h> 35122678Sobrien__FBSDID("$FreeBSD: head/sys/pci/if_sis.c 139798 2005-01-06 23:18:44Z phk $"); 36122678Sobrien 3750974Swpaul/* 3850974Swpaul * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 3950974Swpaul * available from http://www.sis.com.tw. 4050974Swpaul * 4164963Swpaul * This driver also supports the NatSemi DP83815. Datasheets are 4264963Swpaul * available from http://www.national.com. 4364963Swpaul * 4450974Swpaul * Written by Bill Paul <wpaul@ee.columbia.edu> 4550974Swpaul * Electrical Engineering Department 4650974Swpaul * Columbia University, New York City 4750974Swpaul */ 4850974Swpaul/* 4950974Swpaul * The SiS 900 is a fairly simple chip. It uses bus master DMA with 5050974Swpaul * simple TX and RX descriptors of 3 longwords in size. The receiver 5150974Swpaul * has a single perfect filter entry for the station address and a 5250974Swpaul * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 5350974Swpaul * transceiver while the 7016 requires an external transceiver chip. 5450974Swpaul * Both chips offer the standard bit-bang MII interface as well as 5550974Swpaul * an enchanced PHY interface which simplifies accessing MII registers. 5650974Swpaul * 5750974Swpaul * The only downside to this chipset is that RX descriptors must be 5850974Swpaul * longword aligned. 5950974Swpaul */ 6050974Swpaul 6150974Swpaul#include <sys/param.h> 6250974Swpaul#include <sys/systm.h> 6350974Swpaul#include <sys/sockio.h> 6450974Swpaul#include <sys/mbuf.h> 6550974Swpaul#include <sys/malloc.h> 6650974Swpaul#include <sys/kernel.h> 67129876Sphk#include <sys/module.h> 6850974Swpaul#include <sys/socket.h> 6987059Sluigi#include <sys/sysctl.h> 7050974Swpaul 7150974Swpaul#include <net/if.h> 7250974Swpaul#include <net/if_arp.h> 7350974Swpaul#include <net/ethernet.h> 7450974Swpaul#include <net/if_dl.h> 7550974Swpaul#include <net/if_media.h> 7687390Sjhay#include <net/if_types.h> 7787390Sjhay#include <net/if_vlan_var.h> 7850974Swpaul 7950974Swpaul#include <net/bpf.h> 8050974Swpaul 8150974Swpaul#include <machine/bus_pio.h> 8250974Swpaul#include <machine/bus_memio.h> 8350974Swpaul#include <machine/bus.h> 8450974Swpaul#include <machine/resource.h> 8550974Swpaul#include <sys/bus.h> 8650974Swpaul#include <sys/rman.h> 8750974Swpaul 8850974Swpaul#include <dev/mii/mii.h> 8950974Swpaul#include <dev/mii/miivar.h> 9050974Swpaul 91119288Simp#include <dev/pci/pcireg.h> 92119288Simp#include <dev/pci/pcivar.h> 9350974Swpaul 9450974Swpaul#define SIS_USEIOSPACE 9550974Swpaul 9650974Swpaul#include <pci/if_sisreg.h> 9750974Swpaul 98113506SmdoddMODULE_DEPEND(sis, pci, 1, 1, 1); 99113506SmdoddMODULE_DEPEND(sis, ether, 1, 1, 1); 10059758SpeterMODULE_DEPEND(sis, miibus, 1, 1, 1); 10159758Speter 10251089Speter/* "controller miibus0" required. See GENERIC if you get errors here. */ 10350974Swpaul#include "miibus_if.h" 10450974Swpaul 10550974Swpaul/* 10650974Swpaul * Various supported device vendors/types and their names. 10750974Swpaul */ 10850974Swpaulstatic struct sis_type sis_devs[] = { 10950974Swpaul { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 11050974Swpaul { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 111119712Sphk { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" }, 11250974Swpaul { 0, 0, NULL } 11350974Swpaul}; 11450974Swpaul 11592739Salfredstatic int sis_probe (device_t); 11692739Salfredstatic int sis_attach (device_t); 11792739Salfredstatic int sis_detach (device_t); 11850974Swpaul 11992739Salfredstatic int sis_newbuf (struct sis_softc *, 12092739Salfred struct sis_desc *, struct mbuf *); 12192739Salfredstatic int sis_encap (struct sis_softc *, 122121262Ssilby struct mbuf **, u_int32_t *); 12392739Salfredstatic void sis_rxeof (struct sis_softc *); 12492739Salfredstatic void sis_rxeoc (struct sis_softc *); 12592739Salfredstatic void sis_txeof (struct sis_softc *); 12692739Salfredstatic void sis_intr (void *); 12792739Salfredstatic void sis_tick (void *); 12892739Salfredstatic void sis_start (struct ifnet *); 129139714Sphkstatic void sis_startl (struct ifnet *); 13092739Salfredstatic int sis_ioctl (struct ifnet *, u_long, caddr_t); 13192739Salfredstatic void sis_init (void *); 132139717Sphkstatic void sis_initl (struct sis_softc *); 13392739Salfredstatic void sis_stop (struct sis_softc *); 13492739Salfredstatic void sis_watchdog (struct ifnet *); 13592739Salfredstatic void sis_shutdown (device_t); 13692739Salfredstatic int sis_ifmedia_upd (struct ifnet *); 13792739Salfredstatic void sis_ifmedia_sts (struct ifnet *, struct ifmediareq *); 13850974Swpaul 13992739Salfredstatic u_int16_t sis_reverse (u_int16_t); 14092739Salfredstatic void sis_delay (struct sis_softc *); 14192739Salfredstatic void sis_eeprom_idle (struct sis_softc *); 14292739Salfredstatic void sis_eeprom_putbyte (struct sis_softc *, int); 14392739Salfredstatic void sis_eeprom_getword (struct sis_softc *, int, u_int16_t *); 14492739Salfredstatic void sis_read_eeprom (struct sis_softc *, caddr_t, int, int, int); 14572197Swpaul#ifdef __i386__ 14692739Salfredstatic void sis_read_cmos (struct sis_softc *, device_t, caddr_t, 14792739Salfred int, int); 14892739Salfredstatic void sis_read_mac (struct sis_softc *, device_t, caddr_t); 14992739Salfredstatic device_t sis_find_bridge (device_t); 15072197Swpaul#endif 15172197Swpaul 152109060Smbrstatic void sis_mii_sync (struct sis_softc *); 153109060Smbrstatic void sis_mii_send (struct sis_softc *, u_int32_t, int); 154109060Smbrstatic int sis_mii_readreg (struct sis_softc *, struct sis_mii_frame *); 155109060Smbrstatic int sis_mii_writereg (struct sis_softc *, struct sis_mii_frame *); 15692739Salfredstatic int sis_miibus_readreg (device_t, int, int); 15792739Salfredstatic int sis_miibus_writereg (device_t, int, int, int); 15892739Salfredstatic void sis_miibus_statchg (device_t); 15950974Swpaul 16092739Salfredstatic void sis_setmulti_sis (struct sis_softc *); 16192739Salfredstatic void sis_setmulti_ns (struct sis_softc *); 162123289Sobrienstatic uint32_t sis_mchash (struct sis_softc *, const uint8_t *); 16392739Salfredstatic void sis_reset (struct sis_softc *); 16492739Salfredstatic int sis_list_rx_init (struct sis_softc *); 16592739Salfredstatic int sis_list_tx_init (struct sis_softc *); 16650974Swpaul 167139689Sphkstatic bus_dmamap_callback_t sis_dma_map_desc_ptr; 16892739Salfredstatic void sis_dma_map_desc_next (void *, bus_dma_segment_t *, int, int); 16992739Salfredstatic void sis_dma_map_ring (void *, bus_dma_segment_t *, int, int); 17050974Swpaul#ifdef SIS_USEIOSPACE 17150974Swpaul#define SIS_RES SYS_RES_IOPORT 17250974Swpaul#define SIS_RID SIS_PCI_LOIO 17350974Swpaul#else 17451030Swpaul#define SIS_RES SYS_RES_MEMORY 17551030Swpaul#define SIS_RID SIS_PCI_LOMEM 17650974Swpaul#endif 17750974Swpaul 17850974Swpaulstatic device_method_t sis_methods[] = { 17950974Swpaul /* Device interface */ 18050974Swpaul DEVMETHOD(device_probe, sis_probe), 18150974Swpaul DEVMETHOD(device_attach, sis_attach), 18250974Swpaul DEVMETHOD(device_detach, sis_detach), 18350974Swpaul DEVMETHOD(device_shutdown, sis_shutdown), 18450974Swpaul 18550974Swpaul /* bus interface */ 18650974Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 18750974Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 18850974Swpaul 18950974Swpaul /* MII interface */ 19050974Swpaul DEVMETHOD(miibus_readreg, sis_miibus_readreg), 19150974Swpaul DEVMETHOD(miibus_writereg, sis_miibus_writereg), 19250974Swpaul DEVMETHOD(miibus_statchg, sis_miibus_statchg), 19350974Swpaul 19450974Swpaul { 0, 0 } 19550974Swpaul}; 19650974Swpaul 19750974Swpaulstatic driver_t sis_driver = { 19851455Swpaul "sis", 19950974Swpaul sis_methods, 20050974Swpaul sizeof(struct sis_softc) 20150974Swpaul}; 20250974Swpaul 20350974Swpaulstatic devclass_t sis_devclass; 20450974Swpaul 205113506SmdoddDRIVER_MODULE(sis, pci, sis_driver, sis_devclass, 0, 0); 20651473SwpaulDRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 20750974Swpaul 20850974Swpaul#define SIS_SETBIT(sc, reg, x) \ 20950974Swpaul CSR_WRITE_4(sc, reg, \ 21050974Swpaul CSR_READ_4(sc, reg) | (x)) 21150974Swpaul 21250974Swpaul#define SIS_CLRBIT(sc, reg, x) \ 21350974Swpaul CSR_WRITE_4(sc, reg, \ 21450974Swpaul CSR_READ_4(sc, reg) & ~(x)) 21550974Swpaul 21650974Swpaul#define SIO_SET(x) \ 21750974Swpaul CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 21850974Swpaul 21950974Swpaul#define SIO_CLR(x) \ 22050974Swpaul CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 22150974Swpaul 22281713Swpaulstatic void 223139740Sphksis_dma_map_desc_next(void *arg, bus_dma_segment_t *segs, int nseg, int error) 22481713Swpaul{ 22581713Swpaul struct sis_desc *r; 22681713Swpaul 22781713Swpaul r = arg; 22881713Swpaul r->sis_next = segs->ds_addr; 22981713Swpaul} 23081713Swpaul 23181713Swpaulstatic void 232139740Sphksis_dma_map_desc_ptr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 23381713Swpaul{ 23481713Swpaul struct sis_desc *r; 23581713Swpaul 23681713Swpaul r = arg; 23781713Swpaul r->sis_ptr = segs->ds_addr; 23881713Swpaul} 23981713Swpaul 24081713Swpaulstatic void 241139740Sphksis_dma_map_ring(void *arg, bus_dma_segment_t *segs, int nseg, int error) 24281713Swpaul{ 24381713Swpaul u_int32_t *p; 24481713Swpaul 24581713Swpaul p = arg; 24681713Swpaul *p = segs->ds_addr; 24781713Swpaul} 24881713Swpaul 24962672Swpaul/* 25062672Swpaul * Routine to reverse the bits in a word. Stolen almost 25162672Swpaul * verbatim from /usr/games/fortune. 25262672Swpaul */ 253139740Sphkstatic uint16_t 254139740Sphksis_reverse(uint16_t n) 25562672Swpaul{ 25662672Swpaul n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 25762672Swpaul n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 25862672Swpaul n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 25962672Swpaul n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 26062672Swpaul 26162672Swpaul return(n); 26262672Swpaul} 26362672Swpaul 264102334Salfredstatic void 265139740Sphksis_delay(struct sis_softc *sc) 26650974Swpaul{ 26750974Swpaul int idx; 26850974Swpaul 26950974Swpaul for (idx = (300 / 33) + 1; idx > 0; idx--) 27050974Swpaul CSR_READ_4(sc, SIS_CSR); 27150974Swpaul} 27250974Swpaul 273102334Salfredstatic void 274139740Sphksis_eeprom_idle(struct sis_softc *sc) 27550974Swpaul{ 276139708Sphk int i; 27750974Swpaul 27850974Swpaul SIO_SET(SIS_EECTL_CSEL); 27950974Swpaul sis_delay(sc); 28050974Swpaul SIO_SET(SIS_EECTL_CLK); 28150974Swpaul sis_delay(sc); 28250974Swpaul 28350974Swpaul for (i = 0; i < 25; i++) { 28450974Swpaul SIO_CLR(SIS_EECTL_CLK); 28550974Swpaul sis_delay(sc); 28650974Swpaul SIO_SET(SIS_EECTL_CLK); 28750974Swpaul sis_delay(sc); 28850974Swpaul } 28950974Swpaul 29050974Swpaul SIO_CLR(SIS_EECTL_CLK); 29150974Swpaul sis_delay(sc); 29250974Swpaul SIO_CLR(SIS_EECTL_CSEL); 29350974Swpaul sis_delay(sc); 29450974Swpaul CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 29550974Swpaul} 29650974Swpaul 29750974Swpaul/* 29850974Swpaul * Send a read command and address to the EEPROM, check for ACK. 29950974Swpaul */ 300102334Salfredstatic void 301139740Sphksis_eeprom_putbyte(struct sis_softc *sc, int addr) 30250974Swpaul{ 303139708Sphk int d, i; 30450974Swpaul 30550974Swpaul d = addr | SIS_EECMD_READ; 30650974Swpaul 30750974Swpaul /* 30850974Swpaul * Feed in each bit and stobe the clock. 30950974Swpaul */ 31050974Swpaul for (i = 0x400; i; i >>= 1) { 31150974Swpaul if (d & i) { 31250974Swpaul SIO_SET(SIS_EECTL_DIN); 31350974Swpaul } else { 31450974Swpaul SIO_CLR(SIS_EECTL_DIN); 31550974Swpaul } 31650974Swpaul sis_delay(sc); 31750974Swpaul SIO_SET(SIS_EECTL_CLK); 31850974Swpaul sis_delay(sc); 31950974Swpaul SIO_CLR(SIS_EECTL_CLK); 32050974Swpaul sis_delay(sc); 32150974Swpaul } 32250974Swpaul} 32350974Swpaul 32450974Swpaul/* 32550974Swpaul * Read a word of data stored in the EEPROM at address 'addr.' 32650974Swpaul */ 327102334Salfredstatic void 328139740Sphksis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest) 32950974Swpaul{ 330139708Sphk int i; 33150974Swpaul u_int16_t word = 0; 33250974Swpaul 33350974Swpaul /* Force EEPROM to idle state. */ 33450974Swpaul sis_eeprom_idle(sc); 33550974Swpaul 33650974Swpaul /* Enter EEPROM access mode. */ 33750974Swpaul sis_delay(sc); 33862672Swpaul SIO_CLR(SIS_EECTL_CLK); 33962672Swpaul sis_delay(sc); 34050974Swpaul SIO_SET(SIS_EECTL_CSEL); 34150974Swpaul sis_delay(sc); 34250974Swpaul 34350974Swpaul /* 34450974Swpaul * Send address of word we want to read. 34550974Swpaul */ 34650974Swpaul sis_eeprom_putbyte(sc, addr); 34750974Swpaul 34850974Swpaul /* 34950974Swpaul * Start reading bits from EEPROM. 35050974Swpaul */ 35150974Swpaul for (i = 0x8000; i; i >>= 1) { 35250974Swpaul SIO_SET(SIS_EECTL_CLK); 35350974Swpaul sis_delay(sc); 35450974Swpaul if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 35550974Swpaul word |= i; 35650974Swpaul sis_delay(sc); 35750974Swpaul SIO_CLR(SIS_EECTL_CLK); 35850974Swpaul sis_delay(sc); 35950974Swpaul } 36050974Swpaul 36150974Swpaul /* Turn off EEPROM access mode. */ 36250974Swpaul sis_eeprom_idle(sc); 36350974Swpaul 36450974Swpaul *dest = word; 36550974Swpaul} 36650974Swpaul 36750974Swpaul/* 36850974Swpaul * Read a sequence of words from the EEPROM. 36950974Swpaul */ 370102334Salfredstatic void 371139740Sphksis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap) 37250974Swpaul{ 37350974Swpaul int i; 37450974Swpaul u_int16_t word = 0, *ptr; 37550974Swpaul 37650974Swpaul for (i = 0; i < cnt; i++) { 37750974Swpaul sis_eeprom_getword(sc, off + i, &word); 37850974Swpaul ptr = (u_int16_t *)(dest + (i * 2)); 37950974Swpaul if (swap) 38050974Swpaul *ptr = ntohs(word); 38150974Swpaul else 38250974Swpaul *ptr = word; 38350974Swpaul } 38450974Swpaul} 38550974Swpaul 38672197Swpaul#ifdef __i386__ 387102334Salfredstatic device_t 388139740Sphksis_find_bridge(device_t dev) 38972197Swpaul{ 39072197Swpaul devclass_t pci_devclass; 39172197Swpaul device_t *pci_devices; 39272197Swpaul int pci_count = 0; 39372197Swpaul device_t *pci_children; 39472197Swpaul int pci_childcount = 0; 39572197Swpaul device_t *busp, *childp; 39687994Sarchie device_t child = NULL; 39772197Swpaul int i, j; 39872197Swpaul 39972197Swpaul if ((pci_devclass = devclass_find("pci")) == NULL) 40072197Swpaul return(NULL); 40172197Swpaul 40272197Swpaul devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 40372197Swpaul 40472197Swpaul for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 40572197Swpaul pci_childcount = 0; 40672197Swpaul device_get_children(*busp, &pci_children, &pci_childcount); 40772197Swpaul for (j = 0, childp = pci_children; 40872197Swpaul j < pci_childcount; j++, childp++) { 40972197Swpaul if (pci_get_vendor(*childp) == SIS_VENDORID && 41072197Swpaul pci_get_device(*childp) == 0x0008) { 41187994Sarchie child = *childp; 41287994Sarchie goto done; 41372197Swpaul } 41472197Swpaul } 41572197Swpaul } 41672197Swpaul 41787994Sarchiedone: 41872197Swpaul free(pci_devices, M_TEMP); 41972197Swpaul free(pci_children, M_TEMP); 42087994Sarchie return(child); 42172197Swpaul} 42272197Swpaul 423102334Salfredstatic void 424139740Sphksis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off, int cnt) 42572197Swpaul{ 42672197Swpaul device_t bridge; 42772197Swpaul u_int8_t reg; 42872197Swpaul int i; 42972197Swpaul bus_space_tag_t btag; 43072197Swpaul 43172197Swpaul bridge = sis_find_bridge(dev); 43272197Swpaul if (bridge == NULL) 43372197Swpaul return; 43472197Swpaul reg = pci_read_config(bridge, 0x48, 1); 43572197Swpaul pci_write_config(bridge, 0x48, reg|0x40, 1); 43672197Swpaul 43772197Swpaul /* XXX */ 43872197Swpaul btag = I386_BUS_SPACE_IO; 43972197Swpaul 44072197Swpaul for (i = 0; i < cnt; i++) { 44172197Swpaul bus_space_write_1(btag, 0x0, 0x70, i + off); 44272197Swpaul *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 44372197Swpaul } 44472197Swpaul 44572197Swpaul pci_write_config(bridge, 0x48, reg & ~0x40, 1); 44672197Swpaul return; 44772197Swpaul} 44889296Swpaul 449102334Salfredstatic void 450139740Sphksis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest) 45189296Swpaul{ 45289296Swpaul u_int32_t filtsave, csrsave; 45389296Swpaul 45489296Swpaul filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 45589296Swpaul csrsave = CSR_READ_4(sc, SIS_CSR); 45689296Swpaul 45789296Swpaul CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 45889296Swpaul CSR_WRITE_4(sc, SIS_CSR, 0); 45989296Swpaul 46089296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 46189296Swpaul 46289296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 46389296Swpaul ((u_int16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 46489296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 46589296Swpaul ((u_int16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 46689296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 46789296Swpaul ((u_int16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 46889296Swpaul 46989296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 47089296Swpaul CSR_WRITE_4(sc, SIS_CSR, csrsave); 47189296Swpaul return; 47289296Swpaul} 47372197Swpaul#endif 47472197Swpaul 475109060Smbr/* 476109060Smbr * Sync the PHYs by setting data bit and strobing the clock 32 times. 477109060Smbr */ 478139740Sphkstatic void 479139740Sphksis_mii_sync(struct sis_softc *sc) 480109060Smbr{ 481139708Sphk int i; 482109060Smbr 483109060Smbr SIO_SET(SIS_MII_DIR|SIS_MII_DATA); 484109060Smbr 485109060Smbr for (i = 0; i < 32; i++) { 486109060Smbr SIO_SET(SIS_MII_CLK); 487109060Smbr DELAY(1); 488109060Smbr SIO_CLR(SIS_MII_CLK); 489109060Smbr DELAY(1); 490109060Smbr } 491109060Smbr} 492109060Smbr 493109060Smbr/* 494109060Smbr * Clock a series of bits through the MII. 495109060Smbr */ 496139740Sphkstatic void 497139740Sphksis_mii_send(struct sis_softc *sc, uint32_t bits, int cnt) 498109060Smbr{ 499109060Smbr int i; 500109060Smbr 501109060Smbr SIO_CLR(SIS_MII_CLK); 502109060Smbr 503109060Smbr for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 504109060Smbr if (bits & i) { 505109060Smbr SIO_SET(SIS_MII_DATA); 506109060Smbr } else { 507109060Smbr SIO_CLR(SIS_MII_DATA); 508109060Smbr } 509109060Smbr DELAY(1); 510109060Smbr SIO_CLR(SIS_MII_CLK); 511109060Smbr DELAY(1); 512109060Smbr SIO_SET(SIS_MII_CLK); 513109060Smbr } 514109060Smbr} 515109060Smbr 516109060Smbr/* 517109060Smbr * Read an PHY register through the MII. 518109060Smbr */ 519139740Sphkstatic int 520139740Sphksis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame) 521109060Smbr{ 522109060Smbr int i, ack, s; 523109060Smbr 524109060Smbr s = splimp(); 525109060Smbr 526109060Smbr /* 527109060Smbr * Set up frame for RX. 528109060Smbr */ 529109060Smbr frame->mii_stdelim = SIS_MII_STARTDELIM; 530109060Smbr frame->mii_opcode = SIS_MII_READOP; 531109060Smbr frame->mii_turnaround = 0; 532109060Smbr frame->mii_data = 0; 533109060Smbr 534109060Smbr /* 535109060Smbr * Turn on data xmit. 536109060Smbr */ 537109060Smbr SIO_SET(SIS_MII_DIR); 538109060Smbr 539109060Smbr sis_mii_sync(sc); 540109060Smbr 541109060Smbr /* 542109060Smbr * Send command/address info. 543109060Smbr */ 544109060Smbr sis_mii_send(sc, frame->mii_stdelim, 2); 545109060Smbr sis_mii_send(sc, frame->mii_opcode, 2); 546109060Smbr sis_mii_send(sc, frame->mii_phyaddr, 5); 547109060Smbr sis_mii_send(sc, frame->mii_regaddr, 5); 548109060Smbr 549109060Smbr /* Idle bit */ 550109060Smbr SIO_CLR((SIS_MII_CLK|SIS_MII_DATA)); 551109060Smbr DELAY(1); 552109060Smbr SIO_SET(SIS_MII_CLK); 553109060Smbr DELAY(1); 554109060Smbr 555109060Smbr /* Turn off xmit. */ 556109060Smbr SIO_CLR(SIS_MII_DIR); 557109060Smbr 558109060Smbr /* Check for ack */ 559109060Smbr SIO_CLR(SIS_MII_CLK); 560109060Smbr DELAY(1); 561109060Smbr ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA; 562109060Smbr SIO_SET(SIS_MII_CLK); 563109060Smbr DELAY(1); 564109060Smbr 565109060Smbr /* 566109060Smbr * Now try reading data bits. If the ack failed, we still 567109060Smbr * need to clock through 16 cycles to keep the PHY(s) in sync. 568109060Smbr */ 569109060Smbr if (ack) { 570109060Smbr for(i = 0; i < 16; i++) { 571109060Smbr SIO_CLR(SIS_MII_CLK); 572109060Smbr DELAY(1); 573109060Smbr SIO_SET(SIS_MII_CLK); 574109060Smbr DELAY(1); 575109060Smbr } 576109060Smbr goto fail; 577109060Smbr } 578109060Smbr 579109060Smbr for (i = 0x8000; i; i >>= 1) { 580109060Smbr SIO_CLR(SIS_MII_CLK); 581109060Smbr DELAY(1); 582109060Smbr if (!ack) { 583109060Smbr if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA) 584109060Smbr frame->mii_data |= i; 585109060Smbr DELAY(1); 586109060Smbr } 587109060Smbr SIO_SET(SIS_MII_CLK); 588109060Smbr DELAY(1); 589109060Smbr } 590109060Smbr 591109060Smbrfail: 592109060Smbr 593109060Smbr SIO_CLR(SIS_MII_CLK); 594109060Smbr DELAY(1); 595109060Smbr SIO_SET(SIS_MII_CLK); 596109060Smbr DELAY(1); 597109060Smbr 598109060Smbr splx(s); 599109060Smbr 600109060Smbr if (ack) 601109060Smbr return(1); 602109060Smbr return(0); 603109060Smbr} 604109060Smbr 605109060Smbr/* 606109060Smbr * Write to a PHY register through the MII. 607109060Smbr */ 608139740Sphkstatic int 609139740Sphksis_mii_writereg(struct sis_softc *sc, struct sis_mii_frame *frame) 610109060Smbr{ 611109060Smbr int s; 612109060Smbr 613109060Smbr s = splimp(); 614109060Smbr /* 615109060Smbr * Set up frame for TX. 616109060Smbr */ 617109060Smbr 618109060Smbr frame->mii_stdelim = SIS_MII_STARTDELIM; 619109060Smbr frame->mii_opcode = SIS_MII_WRITEOP; 620109060Smbr frame->mii_turnaround = SIS_MII_TURNAROUND; 621109060Smbr 622109060Smbr /* 623109060Smbr * Turn on data output. 624109060Smbr */ 625109060Smbr SIO_SET(SIS_MII_DIR); 626109060Smbr 627109060Smbr sis_mii_sync(sc); 628109060Smbr 629109060Smbr sis_mii_send(sc, frame->mii_stdelim, 2); 630109060Smbr sis_mii_send(sc, frame->mii_opcode, 2); 631109060Smbr sis_mii_send(sc, frame->mii_phyaddr, 5); 632109060Smbr sis_mii_send(sc, frame->mii_regaddr, 5); 633109060Smbr sis_mii_send(sc, frame->mii_turnaround, 2); 634109060Smbr sis_mii_send(sc, frame->mii_data, 16); 635109060Smbr 636109060Smbr /* Idle bit. */ 637109060Smbr SIO_SET(SIS_MII_CLK); 638109060Smbr DELAY(1); 639109060Smbr SIO_CLR(SIS_MII_CLK); 640109060Smbr DELAY(1); 641109060Smbr 642109060Smbr /* 643109060Smbr * Turn off xmit. 644109060Smbr */ 645109060Smbr SIO_CLR(SIS_MII_DIR); 646109060Smbr 647109060Smbr splx(s); 648109060Smbr 649109060Smbr return(0); 650109060Smbr} 651109060Smbr 652102334Salfredstatic int 653139740Sphksis_miibus_readreg(device_t dev, int phy, int reg) 65450974Swpaul{ 65550974Swpaul struct sis_softc *sc; 656109060Smbr struct sis_mii_frame frame; 65750974Swpaul 65850974Swpaul sc = device_get_softc(dev); 65950974Swpaul 66062672Swpaul if (sc->sis_type == SIS_TYPE_83815) { 66162672Swpaul if (phy != 0) 66262672Swpaul return(0); 66362672Swpaul /* 66462672Swpaul * The NatSemi chip can take a while after 66562672Swpaul * a reset to come ready, during which the BMSR 66662672Swpaul * returns a value of 0. This is *never* supposed 66762672Swpaul * to happen: some of the BMSR bits are meant to 66862672Swpaul * be hardwired in the on position, and this can 66962672Swpaul * confuse the miibus code a bit during the probe 67062672Swpaul * and attach phase. So we make an effort to check 67162672Swpaul * for this condition and wait for it to clear. 67262672Swpaul */ 67362672Swpaul if (!CSR_READ_4(sc, NS_BMSR)) 67462672Swpaul DELAY(1000); 675109060Smbr return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 67662672Swpaul } 67762672Swpaul 678109976Smbr /* 679109976Smbr * Chipsets < SIS_635 seem not to be able to read/write 680109976Smbr * through mdio. Use the enhanced PHY access register 681109976Smbr * again for them. 682109976Smbr */ 68389296Swpaul if (sc->sis_type == SIS_TYPE_900 && 684109976Smbr sc->sis_rev < SIS_REV_635) { 685109976Smbr int i, val = 0; 68650974Swpaul 687109976Smbr if (phy != 0) 688109976Smbr return(0); 68950974Swpaul 690109976Smbr CSR_WRITE_4(sc, SIS_PHYCTL, 691109976Smbr (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 692109976Smbr SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 69350974Swpaul 694109976Smbr for (i = 0; i < SIS_TIMEOUT; i++) { 695109976Smbr if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 696109976Smbr break; 697109976Smbr } 698109976Smbr 699109976Smbr if (i == SIS_TIMEOUT) { 700109976Smbr printf("sis%d: PHY failed to come ready\n", 701109976Smbr sc->sis_unit); 702109976Smbr return(0); 703109976Smbr } 704109976Smbr 705109976Smbr val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 706109976Smbr 707109976Smbr if (val == 0xFFFF) 708109976Smbr return(0); 709109976Smbr 710109976Smbr return(val); 711109976Smbr } else { 712109976Smbr bzero((char *)&frame, sizeof(frame)); 713109976Smbr 714109976Smbr frame.mii_phyaddr = phy; 715109976Smbr frame.mii_regaddr = reg; 716109976Smbr sis_mii_readreg(sc, &frame); 717109976Smbr 718109976Smbr return(frame.mii_data); 719109976Smbr } 72050974Swpaul} 72150974Swpaul 722102334Salfredstatic int 723139740Sphksis_miibus_writereg(device_t dev, int phy, int reg, int data) 72450974Swpaul{ 72550974Swpaul struct sis_softc *sc; 726109060Smbr struct sis_mii_frame frame; 72750974Swpaul 72850974Swpaul sc = device_get_softc(dev); 72950974Swpaul 73062672Swpaul if (sc->sis_type == SIS_TYPE_83815) { 73162672Swpaul if (phy != 0) 73262672Swpaul return(0); 73362672Swpaul CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 73462672Swpaul return(0); 73562672Swpaul } 73662672Swpaul 737109976Smbr /* 738109976Smbr * Chipsets < SIS_635 seem not to be able to read/write 739109976Smbr * through mdio. Use the enhanced PHY access register 740109976Smbr * again for them. 741109976Smbr */ 742109976Smbr if (sc->sis_type == SIS_TYPE_900 && 743109976Smbr sc->sis_rev < SIS_REV_635) { 744109976Smbr int i; 74550974Swpaul 746109976Smbr if (phy != 0) 747109976Smbr return(0); 74850974Swpaul 749109976Smbr CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 750109976Smbr (reg << 6) | SIS_PHYOP_WRITE); 751109976Smbr SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 75250974Swpaul 753109976Smbr for (i = 0; i < SIS_TIMEOUT; i++) { 754109976Smbr if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 755109976Smbr break; 756109976Smbr } 75750974Swpaul 758109976Smbr if (i == SIS_TIMEOUT) 759109976Smbr printf("sis%d: PHY failed to come ready\n", 760109976Smbr sc->sis_unit); 761109976Smbr } else { 762109976Smbr bzero((char *)&frame, sizeof(frame)); 763109976Smbr 764109976Smbr frame.mii_phyaddr = phy; 765109976Smbr frame.mii_regaddr = reg; 766109976Smbr frame.mii_data = data; 767109976Smbr sis_mii_writereg(sc, &frame); 768109976Smbr } 76950974Swpaul return(0); 77050974Swpaul} 77150974Swpaul 772102334Salfredstatic void 773139717Sphksis_miibus_statchg(device_t dev) 77450974Swpaul{ 77550974Swpaul struct sis_softc *sc; 77650974Swpaul 77750974Swpaul sc = device_get_softc(dev); 778139717Sphk SIS_LOCK_ASSERT(sc); 779139717Sphk sis_initl(sc); 78050974Swpaul} 78150974Swpaul 782139740Sphkstatic uint32_t 783139740Sphksis_mchash(struct sis_softc *sc, const uint8_t *addr) 78450974Swpaul{ 785130270Snaddy uint32_t crc; 78650974Swpaul 78750974Swpaul /* Compute CRC for the address value. */ 788130270Snaddy crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 78950974Swpaul 79062672Swpaul /* 79162672Swpaul * return the filter bit position 79262672Swpaul * 79362672Swpaul * The NatSemi chip has a 512-bit filter, which is 79462672Swpaul * different than the SiS, so we special-case it. 79562672Swpaul */ 79662672Swpaul if (sc->sis_type == SIS_TYPE_83815) 797109060Smbr return (crc >> 23); 798109976Smbr else if (sc->sis_rev >= SIS_REV_635 || 799109976Smbr sc->sis_rev == SIS_REV_900B) 800109060Smbr return (crc >> 24); 801109976Smbr else 802109976Smbr return (crc >> 25); 80350974Swpaul} 80450974Swpaul 805102334Salfredstatic void 806139740Sphksis_setmulti_ns(struct sis_softc *sc) 80750974Swpaul{ 80850974Swpaul struct ifnet *ifp; 80950974Swpaul struct ifmultiaddr *ifma; 81050974Swpaul u_int32_t h = 0, i, filtsave; 81162672Swpaul int bit, index; 81250974Swpaul 81350974Swpaul ifp = &sc->arpcom.ac_if; 81450974Swpaul 81550974Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 81662672Swpaul SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 81750974Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 81850974Swpaul return; 81950974Swpaul } 82050974Swpaul 82162672Swpaul /* 82262672Swpaul * We have to explicitly enable the multicast hash table 82362672Swpaul * on the NatSemi chip if we want to use it, which we do. 82462672Swpaul */ 82562672Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 82650974Swpaul SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 82750974Swpaul 82850974Swpaul filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 82950974Swpaul 83050974Swpaul /* first, zot all the existing hash bits */ 83162672Swpaul for (i = 0; i < 32; i++) { 83262672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 83362672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 83462672Swpaul } 83562672Swpaul 83672084Sphk TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 83762672Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 83862672Swpaul continue; 839122625Sobrien h = sis_mchash(sc, 840122625Sobrien LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 84162672Swpaul index = h >> 3; 84262672Swpaul bit = h & 0x1F; 84362672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 84462672Swpaul if (bit > 0xF) 84562672Swpaul bit -= 0x10; 84662672Swpaul SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 84762672Swpaul } 84862672Swpaul 84962672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 85062672Swpaul 85162672Swpaul return; 85262672Swpaul} 85362672Swpaul 854102334Salfredstatic void 855139740Sphksis_setmulti_sis(struct sis_softc *sc) 85662672Swpaul{ 85762672Swpaul struct ifnet *ifp; 85862672Swpaul struct ifmultiaddr *ifma; 859109060Smbr u_int32_t h, i, n, ctl; 860109060Smbr u_int16_t hashes[16]; 86162672Swpaul 86262672Swpaul ifp = &sc->arpcom.ac_if; 86362672Swpaul 864109060Smbr /* hash table size */ 865109976Smbr if (sc->sis_rev >= SIS_REV_635 || 866109976Smbr sc->sis_rev == SIS_REV_900B) 867109976Smbr n = 16; 868109976Smbr else 869109976Smbr n = 8; 87062672Swpaul 871109060Smbr ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE; 87262672Swpaul 873109060Smbr if (ifp->if_flags & IFF_BROADCAST) 874109060Smbr ctl |= SIS_RXFILTCTL_BROAD; 87562672Swpaul 876109060Smbr if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 877109060Smbr ctl |= SIS_RXFILTCTL_ALLMULTI; 878109060Smbr if (ifp->if_flags & IFF_PROMISC) 879109060Smbr ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS; 880109060Smbr for (i = 0; i < n; i++) 881109060Smbr hashes[i] = ~0; 882109060Smbr } else { 883109060Smbr for (i = 0; i < n; i++) 884109060Smbr hashes[i] = 0; 885109060Smbr i = 0; 886109060Smbr TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 887109060Smbr if (ifma->ifma_addr->sa_family != AF_LINK) 888109060Smbr continue; 889122625Sobrien h = sis_mchash(sc, 890109060Smbr LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 891109060Smbr hashes[h >> 4] |= 1 << (h & 0xf); 892109060Smbr i++; 893109060Smbr } 894109060Smbr if (i > n) { 895109060Smbr ctl |= SIS_RXFILTCTL_ALLMULTI; 896109060Smbr for (i = 0; i < n; i++) 897109060Smbr hashes[i] = ~0; 898109060Smbr } 89950974Swpaul } 90050974Swpaul 901109060Smbr for (i = 0; i < n; i++) { 902109060Smbr CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); 903109060Smbr CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); 90450974Swpaul } 90550974Swpaul 906109060Smbr CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl); 90750974Swpaul} 90850974Swpaul 909102334Salfredstatic void 910139717Sphksis_reset(struct sis_softc *sc) 91150974Swpaul{ 912139708Sphk int i; 91350974Swpaul 91450974Swpaul SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 91550974Swpaul 91650974Swpaul for (i = 0; i < SIS_TIMEOUT; i++) { 91750974Swpaul if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 91850974Swpaul break; 91950974Swpaul } 92050974Swpaul 92150974Swpaul if (i == SIS_TIMEOUT) 92250974Swpaul printf("sis%d: reset never completed\n", sc->sis_unit); 92350974Swpaul 92450974Swpaul /* Wait a little while for the chip to get its brains in order. */ 92550974Swpaul DELAY(1000); 92672813Swpaul 92772813Swpaul /* 92872813Swpaul * If this is a NetSemi chip, make sure to clear 92972813Swpaul * PME mode. 93072813Swpaul */ 93172813Swpaul if (sc->sis_type == SIS_TYPE_83815) { 93272813Swpaul CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 93372813Swpaul CSR_WRITE_4(sc, NS_CLKRUN, 0); 93472813Swpaul } 93572813Swpaul 93650974Swpaul return; 93750974Swpaul} 93850974Swpaul 93950974Swpaul/* 94050974Swpaul * Probe for an SiS chip. Check the PCI vendor and device 94150974Swpaul * IDs against our list and return a device name if we find a match. 94250974Swpaul */ 943102334Salfredstatic int 944139740Sphksis_probe(device_t dev) 94550974Swpaul{ 94650974Swpaul struct sis_type *t; 94750974Swpaul 94850974Swpaul t = sis_devs; 94950974Swpaul 95050974Swpaul while(t->sis_name != NULL) { 95150974Swpaul if ((pci_get_vendor(dev) == t->sis_vid) && 95250974Swpaul (pci_get_device(dev) == t->sis_did)) { 95350974Swpaul device_set_desc(dev, t->sis_name); 95450974Swpaul return(0); 95550974Swpaul } 95650974Swpaul t++; 95750974Swpaul } 95850974Swpaul 95950974Swpaul return(ENXIO); 96050974Swpaul} 96150974Swpaul 96250974Swpaul/* 96350974Swpaul * Attach the interface. Allocate softc structures, do ifmedia 96450974Swpaul * setup and ethernet/BPF attach. 96550974Swpaul */ 966102334Salfredstatic int 967139740Sphksis_attach(device_t dev) 96850974Swpaul{ 96950974Swpaul u_char eaddr[ETHER_ADDR_LEN]; 97050974Swpaul struct sis_softc *sc; 97150974Swpaul struct ifnet *ifp; 972109061Smbr int unit, error = 0, rid, waittime = 0; 97350974Swpaul 974109061Smbr waittime = 0; 97550974Swpaul sc = device_get_softc(dev); 97650974Swpaul unit = device_get_unit(dev); 97750974Swpaul 978119712Sphk sc->sis_self = dev; 979119712Sphk 98093818Sjhb mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 98193818Sjhb MTX_DEF | MTX_RECURSE); 98269583Swpaul 98350974Swpaul if (pci_get_device(dev) == SIS_DEVICEID_900) 98450974Swpaul sc->sis_type = SIS_TYPE_900; 98550974Swpaul if (pci_get_device(dev) == SIS_DEVICEID_7016) 98650974Swpaul sc->sis_type = SIS_TYPE_7016; 98762672Swpaul if (pci_get_vendor(dev) == NS_VENDORID) 98862672Swpaul sc->sis_type = SIS_TYPE_83815; 98950974Swpaul 99089296Swpaul sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 99150974Swpaul /* 99250974Swpaul * Map control/status registers. 99350974Swpaul */ 99472813Swpaul pci_enable_busmaster(dev); 99550974Swpaul 99650974Swpaul rid = SIS_RID; 997127135Snjl sc->sis_res = bus_alloc_resource_any(dev, SIS_RES, &rid, RF_ACTIVE); 99850974Swpaul 99950974Swpaul if (sc->sis_res == NULL) { 100050974Swpaul printf("sis%d: couldn't map ports/memory\n", unit); 100150974Swpaul error = ENXIO; 100250974Swpaul goto fail; 100350974Swpaul } 100450974Swpaul 100550974Swpaul sc->sis_btag = rman_get_bustag(sc->sis_res); 100650974Swpaul sc->sis_bhandle = rman_get_bushandle(sc->sis_res); 100750974Swpaul 100850974Swpaul /* Allocate interrupt */ 100950974Swpaul rid = 0; 1010127135Snjl sc->sis_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 101150974Swpaul RF_SHAREABLE | RF_ACTIVE); 101250974Swpaul 101350974Swpaul if (sc->sis_irq == NULL) { 101450974Swpaul printf("sis%d: couldn't map interrupt\n", unit); 101550974Swpaul error = ENXIO; 101650974Swpaul goto fail; 101750974Swpaul } 101850974Swpaul 101950974Swpaul /* Reset the adapter. */ 102050974Swpaul sis_reset(sc); 102150974Swpaul 1022109976Smbr if (sc->sis_type == SIS_TYPE_900 && 1023109976Smbr (sc->sis_rev == SIS_REV_635 || 1024109976Smbr sc->sis_rev == SIS_REV_900B)) { 1025109976Smbr SIO_SET(SIS_CFG_RND_CNT); 1026109976Smbr SIO_SET(SIS_CFG_PERR_DETECT); 1027109976Smbr } 1028109976Smbr 102950974Swpaul /* 103050974Swpaul * Get station address from the EEPROM. 103150974Swpaul */ 103262672Swpaul switch (pci_get_vendor(dev)) { 103362672Swpaul case NS_VENDORID: 1034119712Sphk sc->sis_srr = CSR_READ_4(sc, NS_SRR); 1035119712Sphk 1036119712Sphk /* We can't update the device description, so spew */ 1037119712Sphk if (sc->sis_srr == NS_SRR_15C) 1038119712Sphk device_printf(dev, "Silicon Revision: DP83815C\n"); 1039119712Sphk else if (sc->sis_srr == NS_SRR_15D) 1040119712Sphk device_printf(dev, "Silicon Revision: DP83815D\n"); 1041119712Sphk else if (sc->sis_srr == NS_SRR_16A) 1042119712Sphk device_printf(dev, "Silicon Revision: DP83816A\n"); 1043119712Sphk else 1044119712Sphk device_printf(dev, "Silicon Revision %x\n", sc->sis_srr); 1045119712Sphk 104662672Swpaul /* 104762672Swpaul * Reading the MAC address out of the EEPROM on 104862672Swpaul * the NatSemi chip takes a bit more work than 104962672Swpaul * you'd expect. The address spans 4 16-bit words, 105062672Swpaul * with the first word containing only a single bit. 105162672Swpaul * You have to shift everything over one bit to 105262672Swpaul * get it aligned properly. Also, the bits are 105362672Swpaul * stored backwards (the LSB is really the MSB, 105462672Swpaul * and so on) so you have to reverse them in order 105562672Swpaul * to get the MAC address into the form we want. 105662672Swpaul * Why? Who the hell knows. 105762672Swpaul */ 105862672Swpaul { 105962672Swpaul u_int16_t tmp[4]; 106050974Swpaul 106162672Swpaul sis_read_eeprom(sc, (caddr_t)&tmp, 106262672Swpaul NS_EE_NODEADDR, 4, 0); 106362672Swpaul 106462672Swpaul /* Shift everything over one bit. */ 106562672Swpaul tmp[3] = tmp[3] >> 1; 106662681Swpaul tmp[3] |= tmp[2] << 15; 106762672Swpaul tmp[2] = tmp[2] >> 1; 106862681Swpaul tmp[2] |= tmp[1] << 15; 106962672Swpaul tmp[1] = tmp[1] >> 1; 107062681Swpaul tmp[1] |= tmp[0] << 15; 107162672Swpaul 107262672Swpaul /* Now reverse all the bits. */ 107362672Swpaul tmp[3] = sis_reverse(tmp[3]); 107462672Swpaul tmp[2] = sis_reverse(tmp[2]); 107562672Swpaul tmp[1] = sis_reverse(tmp[1]); 107662672Swpaul 107762672Swpaul bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); 107862672Swpaul } 107962672Swpaul break; 108062672Swpaul case SIS_VENDORID: 108162672Swpaul default: 108272197Swpaul#ifdef __i386__ 108372197Swpaul /* 108472197Swpaul * If this is a SiS 630E chipset with an embedded 108572197Swpaul * SiS 900 controller, we have to read the MAC address 108672197Swpaul * from the APC CMOS RAM. Our method for doing this 108772197Swpaul * is very ugly since we have to reach out and grab 108872197Swpaul * ahold of hardware for which we cannot properly 108972197Swpaul * allocate resources. This code is only compiled on 109072197Swpaul * the i386 architecture since the SiS 630E chipset 109172197Swpaul * is for x86 motherboards only. Note that there are 109272197Swpaul * a lot of magic numbers in this hack. These are 109372197Swpaul * taken from SiS's Linux driver. I'd like to replace 109472197Swpaul * them with proper symbolic definitions, but that 109572197Swpaul * requires some datasheets that I don't have access 109672197Swpaul * to at the moment. 109772197Swpaul */ 109889296Swpaul if (sc->sis_rev == SIS_REV_630S || 109989296Swpaul sc->sis_rev == SIS_REV_630E || 110090328Sambrisko sc->sis_rev == SIS_REV_630EA1) 110172197Swpaul sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 110289296Swpaul 110390328Sambrisko else if (sc->sis_rev == SIS_REV_635 || 110490328Sambrisko sc->sis_rev == SIS_REV_630ET) 110589296Swpaul sis_read_mac(sc, dev, (caddr_t)&eaddr); 1106109061Smbr else if (sc->sis_rev == SIS_REV_96x) { 1107109061Smbr /* Allow to read EEPROM from LAN. It is shared 1108109061Smbr * between a 1394 controller and the NIC and each 1109109061Smbr * time we access it, we need to set SIS_EECMD_REQ. 1110109061Smbr */ 1111109061Smbr SIO_SET(SIS_EECMD_REQ); 1112109061Smbr for (waittime = 0; waittime < SIS_TIMEOUT; 1113109061Smbr waittime++) { 1114109061Smbr /* Force EEPROM to idle state. */ 1115109061Smbr sis_eeprom_idle(sc); 1116109061Smbr if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { 1117109061Smbr sis_read_eeprom(sc, (caddr_t)&eaddr, 1118109061Smbr SIS_EE_NODEADDR, 3, 0); 1119109061Smbr break; 1120109061Smbr } 1121109061Smbr DELAY(1); 1122109061Smbr } 1123109061Smbr /* 1124109061Smbr * Set SIS_EECTL_CLK to high, so a other master 1125109061Smbr * can operate on the i2c bus. 1126109061Smbr */ 1127109061Smbr SIO_SET(SIS_EECTL_CLK); 1128109061Smbr /* Refuse EEPROM access by LAN */ 1129109061Smbr SIO_SET(SIS_EECMD_DONE); 1130109061Smbr } else 113172197Swpaul#endif 113272197Swpaul sis_read_eeprom(sc, (caddr_t)&eaddr, 113372197Swpaul SIS_EE_NODEADDR, 3, 0); 113462672Swpaul break; 113562672Swpaul } 113662672Swpaul 113750974Swpaul sc->sis_unit = unit; 1138129636Srwatson if (debug_mpsafenet) 1139129636Srwatson callout_init(&sc->sis_stat_ch, CALLOUT_MPSAFE); 1140129636Srwatson else 1141129636Srwatson callout_init(&sc->sis_stat_ch, 0); 114250974Swpaul bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 114350974Swpaul 114481713Swpaul /* 114581713Swpaul * Allocate the parent bus DMA tag appropriate for PCI. 114681713Swpaul */ 114781713Swpaul#define SIS_NSEG_NEW 32 114881713Swpaul error = bus_dma_tag_create(NULL, /* parent */ 114981713Swpaul 1, 0, /* alignment, boundary */ 115081713Swpaul BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 115181713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 115281713Swpaul NULL, NULL, /* filter, filterarg */ 115381713Swpaul MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */ 115481713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 115581713Swpaul BUS_DMA_ALLOCNOW, /* flags */ 1156117126Sscottl NULL, NULL, /* lockfunc, lockarg */ 115781713Swpaul &sc->sis_parent_tag); 1158112872Snjl if (error) 1159112872Snjl goto fail; 116050974Swpaul 116181713Swpaul /* 1162112872Snjl * Now allocate a tag for the DMA descriptor lists and a chunk 1163112872Snjl * of DMA-able memory based on the tag. Also obtain the physical 1164112872Snjl * addresses of the RX and TX ring, which we'll need later. 116581713Swpaul * All of our lists are allocated as a contiguous block 116681713Swpaul * of memory. 116781713Swpaul */ 116881713Swpaul error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 116981713Swpaul 1, 0, /* alignment, boundary */ 117081713Swpaul BUS_SPACE_MAXADDR, /* lowaddr */ 117181713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 117281713Swpaul NULL, NULL, /* filter, filterarg */ 117381713Swpaul SIS_RX_LIST_SZ, 1, /* maxsize,nsegments */ 117481713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 117581713Swpaul 0, /* flags */ 1176117126Sscottl busdma_lock_mutex, /* lockfunc */ 1177117126Sscottl &Giant, /* lockarg */ 1178139690Sphk &sc->sis_rx_tag); 1179112872Snjl if (error) 1180112872Snjl goto fail; 118181713Swpaul 1182139690Sphk error = bus_dmamem_alloc(sc->sis_rx_tag, 1183139690Sphk (void **)&sc->sis_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1184139690Sphk &sc->sis_rx_dmamap); 1185112872Snjl 1186112872Snjl if (error) { 1187112872Snjl printf("sis%d: no memory for rx list buffers!\n", unit); 1188139690Sphk bus_dma_tag_destroy(sc->sis_rx_tag); 1189139690Sphk sc->sis_rx_tag = NULL; 1190112872Snjl goto fail; 1191112872Snjl } 1192112872Snjl 1193139690Sphk error = bus_dmamap_load(sc->sis_rx_tag, 1194139690Sphk sc->sis_rx_dmamap, &(sc->sis_rx_list[0]), 1195112872Snjl sizeof(struct sis_desc), sis_dma_map_ring, 1196139690Sphk &sc->sis_rx_paddr, 0); 1197112872Snjl 1198112872Snjl if (error) { 1199112872Snjl printf("sis%d: cannot get address of the rx ring!\n", unit); 1200139690Sphk bus_dmamem_free(sc->sis_rx_tag, 1201139690Sphk sc->sis_rx_list, sc->sis_rx_dmamap); 1202139690Sphk bus_dma_tag_destroy(sc->sis_rx_tag); 1203139690Sphk sc->sis_rx_tag = NULL; 1204112872Snjl goto fail; 1205112872Snjl } 1206112872Snjl 120781713Swpaul error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 120881713Swpaul 1, 0, /* alignment, boundary */ 120981713Swpaul BUS_SPACE_MAXADDR, /* lowaddr */ 121081713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 121181713Swpaul NULL, NULL, /* filter, filterarg */ 121281713Swpaul SIS_TX_LIST_SZ, 1, /* maxsize,nsegments */ 121381713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 121481713Swpaul 0, /* flags */ 1215117126Sscottl busdma_lock_mutex, /* lockfunc */ 1216117126Sscottl &Giant, /* lockarg */ 1217139690Sphk &sc->sis_tx_tag); 1218112872Snjl if (error) 1219112872Snjl goto fail; 122081713Swpaul 1221139690Sphk error = bus_dmamem_alloc(sc->sis_tx_tag, 1222139690Sphk (void **)&sc->sis_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1223139690Sphk &sc->sis_tx_dmamap); 122481713Swpaul 122581713Swpaul if (error) { 1226112872Snjl printf("sis%d: no memory for tx list buffers!\n", unit); 1227139690Sphk bus_dma_tag_destroy(sc->sis_tx_tag); 1228139690Sphk sc->sis_tx_tag = NULL; 122950974Swpaul goto fail; 123050974Swpaul } 123150974Swpaul 1232139690Sphk error = bus_dmamap_load(sc->sis_tx_tag, 1233139690Sphk sc->sis_tx_dmamap, &(sc->sis_tx_list[0]), 1234112872Snjl sizeof(struct sis_desc), sis_dma_map_ring, 1235139690Sphk &sc->sis_tx_paddr, 0); 123681713Swpaul 123781713Swpaul if (error) { 1238112872Snjl printf("sis%d: cannot get address of the tx ring!\n", unit); 1239139690Sphk bus_dmamem_free(sc->sis_tx_tag, 1240139690Sphk sc->sis_tx_list, sc->sis_tx_dmamap); 1241139690Sphk bus_dma_tag_destroy(sc->sis_tx_tag); 1242139690Sphk sc->sis_tx_tag = NULL; 124381713Swpaul goto fail; 124481713Swpaul } 124581713Swpaul 1246112872Snjl error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1247112872Snjl 1, 0, /* alignment, boundary */ 1248112872Snjl BUS_SPACE_MAXADDR, /* lowaddr */ 1249112872Snjl BUS_SPACE_MAXADDR, /* highaddr */ 1250112872Snjl NULL, NULL, /* filter, filterarg */ 1251112872Snjl MCLBYTES, 1, /* maxsize,nsegments */ 1252112872Snjl BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1253112872Snjl 0, /* flags */ 1254117126Sscottl busdma_lock_mutex, /* lockfunc */ 1255117126Sscottl &Giant, /* lockarg */ 1256112872Snjl &sc->sis_tag); 1257112872Snjl if (error) 1258112872Snjl goto fail; 125981713Swpaul 126081713Swpaul /* 126181713Swpaul * Obtain the physical addresses of the RX and TX 126281713Swpaul * rings which we'll need later in the init routine. 126381713Swpaul */ 126481713Swpaul 126550974Swpaul ifp = &sc->arpcom.ac_if; 126650974Swpaul ifp->if_softc = sc; 1267121816Sbrooks if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 126850974Swpaul ifp->if_mtu = ETHERMTU; 126950974Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 127050974Swpaul ifp->if_ioctl = sis_ioctl; 127150974Swpaul ifp->if_start = sis_start; 127250974Swpaul ifp->if_watchdog = sis_watchdog; 127350974Swpaul ifp->if_init = sis_init; 127450974Swpaul ifp->if_baudrate = 10000000; 1275131455Smlaier IFQ_SET_MAXLEN(&ifp->if_snd, SIS_TX_LIST_CNT - 1); 1276131455Smlaier ifp->if_snd.ifq_drv_maxlen = SIS_TX_LIST_CNT - 1; 1277131455Smlaier IFQ_SET_READY(&ifp->if_snd); 127850974Swpaul 127950974Swpaul /* 128050974Swpaul * Do MII setup. 128150974Swpaul */ 128250974Swpaul if (mii_phy_probe(dev, &sc->sis_miibus, 128350974Swpaul sis_ifmedia_upd, sis_ifmedia_sts)) { 128450974Swpaul printf("sis%d: MII without any PHY!\n", sc->sis_unit); 128550974Swpaul error = ENXIO; 128650974Swpaul goto fail; 128750974Swpaul } 128850974Swpaul 128950974Swpaul /* 129063090Sarchie * Call MI attach routine. 129150974Swpaul */ 1292106936Ssam ether_ifattach(ifp, eaddr); 129387390Sjhay 129487390Sjhay /* 129587390Sjhay * Tell the upper layer(s) we support long frames. 129687390Sjhay */ 129787390Sjhay ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1298106936Ssam ifp->if_capabilities |= IFCAP_VLAN_MTU; 129987390Sjhay 1300128138Sru#ifdef DEVICE_POLLING 1301128138Sru ifp->if_capabilities |= IFCAP_POLLING; 1302128138Sru#endif 1303128138Sru ifp->if_capenable = ifp->if_capabilities; 1304128138Sru 1305113609Snjl /* Hook interrupt last to avoid having to lock softc */ 1306121697Ssam error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET | INTR_MPSAFE, 1307112872Snjl sis_intr, sc, &sc->sis_intrhand); 130850974Swpaul 1309112872Snjl if (error) { 1310112872Snjl printf("sis%d: couldn't set up irq\n", unit); 1311113609Snjl ether_ifdetach(ifp); 1312112872Snjl goto fail; 1313112872Snjl } 1314112872Snjl 131550974Swpaulfail: 1316112872Snjl if (error) 1317112872Snjl sis_detach(dev); 1318112872Snjl 131950974Swpaul return(error); 132050974Swpaul} 132150974Swpaul 1322113609Snjl/* 1323113609Snjl * Shutdown hardware and free up resources. This can be called any 1324113609Snjl * time after the mutex has been initialized. It is called in both 1325113609Snjl * the error case in attach and the normal detach case so it needs 1326113609Snjl * to be careful about only freeing resources that have actually been 1327113609Snjl * allocated. 1328113609Snjl */ 1329102334Salfredstatic int 1330139740Sphksis_detach(device_t dev) 133150974Swpaul{ 133250974Swpaul struct sis_softc *sc; 133350974Swpaul struct ifnet *ifp; 133450974Swpaul 133550974Swpaul sc = device_get_softc(dev); 1336112880Sjhb KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized")); 133767087Swpaul SIS_LOCK(sc); 133850974Swpaul ifp = &sc->arpcom.ac_if; 133950974Swpaul 1340118089Smux /* These should only be active if attach succeeded. */ 1341113812Simp if (device_is_attached(dev)) { 1342113609Snjl sis_reset(sc); 1343113609Snjl sis_stop(sc); 1344112872Snjl ether_ifdetach(ifp); 1345113609Snjl } 1346113609Snjl if (sc->sis_miibus) 1347112872Snjl device_delete_child(dev, sc->sis_miibus); 1348113609Snjl bus_generic_detach(dev); 134950974Swpaul 1350112872Snjl if (sc->sis_intrhand) 1351112872Snjl bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1352112872Snjl if (sc->sis_irq) 1353112872Snjl bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1354112872Snjl if (sc->sis_res) 1355112872Snjl bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 135650974Swpaul 1357139690Sphk if (sc->sis_rx_tag) { 1358139690Sphk bus_dmamap_unload(sc->sis_rx_tag, 1359139690Sphk sc->sis_rx_dmamap); 1360139690Sphk bus_dmamem_free(sc->sis_rx_tag, 1361139690Sphk sc->sis_rx_list, sc->sis_rx_dmamap); 1362139690Sphk bus_dma_tag_destroy(sc->sis_rx_tag); 1363112872Snjl } 1364139690Sphk if (sc->sis_tx_tag) { 1365139690Sphk bus_dmamap_unload(sc->sis_tx_tag, 1366139690Sphk sc->sis_tx_dmamap); 1367139690Sphk bus_dmamem_free(sc->sis_tx_tag, 1368139690Sphk sc->sis_tx_list, sc->sis_tx_dmamap); 1369139690Sphk bus_dma_tag_destroy(sc->sis_tx_tag); 1370112872Snjl } 1371112872Snjl if (sc->sis_parent_tag) 1372112872Snjl bus_dma_tag_destroy(sc->sis_parent_tag); 1373112872Snjl if (sc->sis_tag) 1374112872Snjl bus_dma_tag_destroy(sc->sis_tag); 137550974Swpaul 137667087Swpaul SIS_UNLOCK(sc); 137767087Swpaul mtx_destroy(&sc->sis_mtx); 137850974Swpaul 137950974Swpaul return(0); 138050974Swpaul} 138150974Swpaul 138250974Swpaul/* 138350974Swpaul * Initialize the transmit descriptors. 138450974Swpaul */ 1385102334Salfredstatic int 1386139740Sphksis_list_tx_init(struct sis_softc *sc) 138750974Swpaul{ 138887059Sluigi int i, nexti; 138950974Swpaul 139050974Swpaul for (i = 0; i < SIS_TX_LIST_CNT; i++) { 139187102Sluigi nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1; 1392139690Sphk sc->sis_tx_list[i].sis_nextdesc = 1393139690Sphk &sc->sis_tx_list[nexti]; 1394139690Sphk bus_dmamap_load(sc->sis_tx_tag, 1395139690Sphk sc->sis_tx_dmamap, 1396139690Sphk &sc->sis_tx_list[nexti], sizeof(struct sis_desc), 1397139690Sphk sis_dma_map_desc_next, &sc->sis_tx_list[i], 0); 1398139690Sphk sc->sis_tx_list[i].sis_mbuf = NULL; 1399139690Sphk sc->sis_tx_list[i].sis_ptr = 0; 1400139690Sphk sc->sis_tx_list[i].sis_ctl = 0; 140150974Swpaul } 140250974Swpaul 1403139690Sphk sc->sis_tx_prod = sc->sis_tx_cons = sc->sis_tx_cnt = 0; 140450974Swpaul 1405139690Sphk bus_dmamap_sync(sc->sis_tx_tag, 1406139690Sphk sc->sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 140781713Swpaul 140850974Swpaul return(0); 140950974Swpaul} 141050974Swpaul 141150974Swpaul/* 141250974Swpaul * Initialize the RX descriptors and allocate mbufs for them. Note that 141350974Swpaul * we arrange the descriptors in a closed ring, so that the last descriptor 141450974Swpaul * points back to the first. 141550974Swpaul */ 1416102334Salfredstatic int 1417139740Sphksis_list_rx_init(struct sis_softc *sc) 141850974Swpaul{ 141987059Sluigi int i,nexti; 142050974Swpaul 142150974Swpaul for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1422139690Sphk if (sis_newbuf(sc, &sc->sis_rx_list[i], NULL) == ENOBUFS) 142350974Swpaul return(ENOBUFS); 142487102Sluigi nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1; 1425139690Sphk sc->sis_rx_list[i].sis_nextdesc = 1426139690Sphk &sc->sis_rx_list[nexti]; 1427139690Sphk bus_dmamap_load(sc->sis_rx_tag, 1428139690Sphk sc->sis_rx_dmamap, 1429139690Sphk &sc->sis_rx_list[nexti], 143081713Swpaul sizeof(struct sis_desc), sis_dma_map_desc_next, 1431139690Sphk &sc->sis_rx_list[i], 0); 143250974Swpaul } 143350974Swpaul 1434139690Sphk bus_dmamap_sync(sc->sis_rx_tag, 1435139690Sphk sc->sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 143681713Swpaul 1437139691Sphk sc->sis_rx_pdsc = &sc->sis_rx_list[0]; 143850974Swpaul 143950974Swpaul return(0); 144050974Swpaul} 144150974Swpaul 144250974Swpaul/* 144350974Swpaul * Initialize an RX descriptor and attach an MBUF cluster. 144450974Swpaul */ 1445102334Salfredstatic int 1446139740Sphksis_newbuf(struct sis_softc *sc, struct sis_desc *c, struct mbuf *m) 144750974Swpaul{ 144850974Swpaul 144981713Swpaul if (c == NULL) 145081713Swpaul return(EINVAL); 145181713Swpaul 145250974Swpaul if (m == NULL) { 1453111119Simp m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1454101340Sluigi if (m == NULL) 145550974Swpaul return(ENOBUFS); 1456101340Sluigi } else 1457101340Sluigi m->m_data = m->m_ext.ext_buf; 145850974Swpaul 1459101340Sluigi c->sis_mbuf = m; 146050974Swpaul c->sis_ctl = SIS_RXLEN; 146150974Swpaul 146281713Swpaul bus_dmamap_create(sc->sis_tag, 0, &c->sis_map); 146381713Swpaul bus_dmamap_load(sc->sis_tag, c->sis_map, 1464101464Sluigi mtod(m, void *), MCLBYTES, 146581713Swpaul sis_dma_map_desc_ptr, c, 0); 146681713Swpaul bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREWRITE); 146781713Swpaul 146850974Swpaul return(0); 146950974Swpaul} 147050974Swpaul 147150974Swpaul/* 147250974Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 147350974Swpaul * the higher level protocols. 147450974Swpaul */ 1475102334Salfredstatic void 1476139740Sphksis_rxeof(struct sis_softc *sc) 147750974Swpaul{ 147850974Swpaul struct mbuf *m; 147950974Swpaul struct ifnet *ifp; 148050974Swpaul struct sis_desc *cur_rx; 1481139691Sphk int total_len = 0; 148250974Swpaul u_int32_t rxstat; 148350974Swpaul 1484122689Ssam SIS_LOCK_ASSERT(sc); 1485122689Ssam 148650974Swpaul ifp = &sc->arpcom.ac_if; 148750974Swpaul 1488139691Sphk for(cur_rx = sc->sis_rx_pdsc; SIS_OWNDESC(cur_rx); 1489139691Sphk cur_rx = cur_rx->sis_nextdesc) { 149050974Swpaul 149187902Sluigi#ifdef DEVICE_POLLING 1492102052Ssobomax if (ifp->if_flags & IFF_POLLING) { 149387902Sluigi if (sc->rxcycles <= 0) 149487902Sluigi break; 149587902Sluigi sc->rxcycles--; 149687902Sluigi } 149787902Sluigi#endif /* DEVICE_POLLING */ 149850974Swpaul rxstat = cur_rx->sis_rxstat; 149981713Swpaul bus_dmamap_sync(sc->sis_tag, 150081713Swpaul cur_rx->sis_map, BUS_DMASYNC_POSTWRITE); 150181713Swpaul bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map); 150281713Swpaul bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map); 150350974Swpaul m = cur_rx->sis_mbuf; 150450974Swpaul cur_rx->sis_mbuf = NULL; 150550974Swpaul total_len = SIS_RXBYTES(cur_rx); 150650974Swpaul 150750974Swpaul /* 150850974Swpaul * If an error occurs, update stats, clear the 150950974Swpaul * status word and leave the mbuf cluster in place: 151050974Swpaul * it should simply get re-used next time this descriptor 151150974Swpaul * comes up in the ring. 151250974Swpaul */ 151350974Swpaul if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 151450974Swpaul ifp->if_ierrors++; 151550974Swpaul if (rxstat & SIS_RXSTAT_COLL) 151650974Swpaul ifp->if_collisions++; 151750974Swpaul sis_newbuf(sc, cur_rx, m); 151850974Swpaul continue; 151950974Swpaul } 152050974Swpaul 152150974Swpaul /* No errors; receive the packet. */ 152287059Sluigi#ifdef __i386__ 152387059Sluigi /* 152487059Sluigi * On the x86 we do not have alignment problems, so try to 152587059Sluigi * allocate a new buffer for the receive ring, and pass up 152687059Sluigi * the one where the packet is already, saving the expensive 152787059Sluigi * copy done in m_devget(). 152887059Sluigi * If we are on an architecture with alignment problems, or 152987059Sluigi * if the allocation fails, then use m_devget and leave the 153087059Sluigi * existing buffer in the receive ring. 153187059Sluigi */ 1532101464Sluigi if (sis_newbuf(sc, cur_rx, NULL) == 0) 153387059Sluigi m->m_pkthdr.len = m->m_len = total_len; 1534101464Sluigi else 153587059Sluigi#endif 153687059Sluigi { 153787059Sluigi struct mbuf *m0; 153887059Sluigi m0 = m_devget(mtod(m, char *), total_len, 153987059Sluigi ETHER_ALIGN, ifp, NULL); 154087059Sluigi sis_newbuf(sc, cur_rx, m); 154187059Sluigi if (m0 == NULL) { 154287059Sluigi ifp->if_ierrors++; 154387059Sluigi continue; 154487059Sluigi } 154587059Sluigi m = m0; 154650974Swpaul } 154750974Swpaul 154850974Swpaul ifp->if_ipackets++; 1549106936Ssam m->m_pkthdr.rcvif = ifp; 1550106936Ssam 1551122689Ssam SIS_UNLOCK(sc); 1552106936Ssam (*ifp->if_input)(ifp, m); 1553122689Ssam SIS_LOCK(sc); 155450974Swpaul } 155550974Swpaul 1556139691Sphk sc->sis_rx_pdsc = cur_rx; 155750974Swpaul} 155850974Swpaul 1559105219Sphkstatic void 1560139715Sphksis_rxeoc(struct sis_softc *sc) 156150974Swpaul{ 1562139715Sphk 1563139715Sphk SIS_LOCK_ASSERT(sc); 156450974Swpaul sis_rxeof(sc); 1565139715Sphk sis_initl(sc); 156650974Swpaul} 156750974Swpaul 156850974Swpaul/* 156950974Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 157050974Swpaul * the list buffers. 157150974Swpaul */ 157250974Swpaul 1573102334Salfredstatic void 1574139740Sphksis_txeof(struct sis_softc *sc) 157550974Swpaul{ 157650974Swpaul struct ifnet *ifp; 157750974Swpaul u_int32_t idx; 157850974Swpaul 1579139715Sphk SIS_LOCK_ASSERT(sc); 158050974Swpaul ifp = &sc->arpcom.ac_if; 158150974Swpaul 158250974Swpaul /* 158350974Swpaul * Go through our tx list and free mbufs for those 158450974Swpaul * frames that have been transmitted. 158550974Swpaul */ 1586139690Sphk for (idx = sc->sis_tx_cons; sc->sis_tx_cnt > 0; 1587139690Sphk sc->sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) { 1588139690Sphk struct sis_desc *cur_tx = &sc->sis_tx_list[idx]; 158950974Swpaul 159050974Swpaul if (SIS_OWNDESC(cur_tx)) 159150974Swpaul break; 159250974Swpaul 159399163Sluigi if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) 159450974Swpaul continue; 159550974Swpaul 159650974Swpaul if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 159750974Swpaul ifp->if_oerrors++; 159850974Swpaul if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 159950974Swpaul ifp->if_collisions++; 160050974Swpaul if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 160150974Swpaul ifp->if_collisions++; 160250974Swpaul } 160350974Swpaul 160450974Swpaul ifp->if_collisions += 160550974Swpaul (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 160650974Swpaul 160750974Swpaul ifp->if_opackets++; 160850974Swpaul if (cur_tx->sis_mbuf != NULL) { 160950974Swpaul m_freem(cur_tx->sis_mbuf); 161050974Swpaul cur_tx->sis_mbuf = NULL; 161181713Swpaul bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map); 161281713Swpaul bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map); 161350974Swpaul } 161499163Sluigi } 161550974Swpaul 1616139690Sphk if (idx != sc->sis_tx_cons) { 161799163Sluigi /* we freed up some buffers */ 1618139690Sphk sc->sis_tx_cons = idx; 161999163Sluigi ifp->if_flags &= ~IFF_OACTIVE; 162050974Swpaul } 162150974Swpaul 1622139690Sphk ifp->if_timer = (sc->sis_tx_cnt == 0) ? 0 : 5; 162350974Swpaul 162450974Swpaul return; 162550974Swpaul} 162650974Swpaul 1627102334Salfredstatic void 1628139740Sphksis_tick(void *xsc) 162950974Swpaul{ 163050974Swpaul struct sis_softc *sc; 163150974Swpaul struct mii_data *mii; 163264963Swpaul struct ifnet *ifp; 163350974Swpaul 163450974Swpaul sc = xsc; 163567087Swpaul SIS_LOCK(sc); 1636117858Scognet sc->in_tick = 1; 163764963Swpaul ifp = &sc->arpcom.ac_if; 163864963Swpaul 163950974Swpaul mii = device_get_softc(sc->sis_miibus); 164050974Swpaul mii_tick(mii); 164164963Swpaul 164284147Sjlemon if (!sc->sis_link && mii->mii_media_status & IFM_ACTIVE && 164384147Sjlemon IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 164484147Sjlemon sc->sis_link++; 1645131455Smlaier if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1646139714Sphk sis_startl(ifp); 164764963Swpaul } 164864963Swpaul 1649119785Ssam callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 1650117858Scognet sc->in_tick = 0; 165167087Swpaul SIS_UNLOCK(sc); 165250974Swpaul} 165350974Swpaul 165487902Sluigi#ifdef DEVICE_POLLING 165587902Sluigistatic poll_handler_t sis_poll; 165687902Sluigi 165787902Sluigistatic void 165887902Sluigisis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 165987902Sluigi{ 166087973Speter struct sis_softc *sc = ifp->if_softc; 166187973Speter 166287902Sluigi SIS_LOCK(sc); 1663128138Sru if (!(ifp->if_capenable & IFCAP_POLLING)) { 1664128138Sru ether_poll_deregister(ifp); 1665128138Sru cmd = POLL_DEREGISTER; 1666128138Sru } 166787902Sluigi if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 166887902Sluigi CSR_WRITE_4(sc, SIS_IER, 1); 166987902Sluigi goto done; 167087902Sluigi } 167187902Sluigi 167287902Sluigi /* 167387902Sluigi * On the sis, reading the status register also clears it. 167487902Sluigi * So before returning to intr mode we must make sure that all 167587902Sluigi * possible pending sources of interrupts have been served. 167687902Sluigi * In practice this means run to completion the *eof routines, 167787902Sluigi * and then call the interrupt routine 167887902Sluigi */ 167987902Sluigi sc->rxcycles = count; 168087902Sluigi sis_rxeof(sc); 168187902Sluigi sis_txeof(sc); 1682131455Smlaier if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1683139714Sphk sis_startl(ifp); 168487902Sluigi 168587902Sluigi if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 168687902Sluigi u_int32_t status; 168787902Sluigi 168887902Sluigi /* Reading the ISR register clears all interrupts. */ 168987902Sluigi status = CSR_READ_4(sc, SIS_ISR); 169087902Sluigi 169187902Sluigi if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 169287902Sluigi sis_rxeoc(sc); 169387902Sluigi 169487902Sluigi if (status & (SIS_ISR_RX_IDLE)) 169587902Sluigi SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 169687902Sluigi 169787902Sluigi if (status & SIS_ISR_SYSERR) { 169887902Sluigi sis_reset(sc); 1699139715Sphk sis_initl(sc); 170087902Sluigi } 170187902Sluigi } 170287902Sluigidone: 170387902Sluigi SIS_UNLOCK(sc); 170487902Sluigi} 170587902Sluigi#endif /* DEVICE_POLLING */ 170687902Sluigi 1707102334Salfredstatic void 1708139740Sphksis_intr(void *arg) 170950974Swpaul{ 171050974Swpaul struct sis_softc *sc; 171150974Swpaul struct ifnet *ifp; 171250974Swpaul u_int32_t status; 171350974Swpaul 171450974Swpaul sc = arg; 171550974Swpaul ifp = &sc->arpcom.ac_if; 171650974Swpaul 171786984Sluigi SIS_LOCK(sc); 171887902Sluigi#ifdef DEVICE_POLLING 1719102052Ssobomax if (ifp->if_flags & IFF_POLLING) 172087902Sluigi goto done; 1721128138Sru if ((ifp->if_capenable & IFCAP_POLLING) && 1722128138Sru ether_poll_register(sis_poll, ifp)) { /* ok, disable interrupts */ 172387902Sluigi CSR_WRITE_4(sc, SIS_IER, 0); 172487902Sluigi goto done; 172587902Sluigi } 172687902Sluigi#endif /* DEVICE_POLLING */ 172787902Sluigi 172850974Swpaul /* Supress unwanted interrupts */ 172950974Swpaul if (!(ifp->if_flags & IFF_UP)) { 173050974Swpaul sis_stop(sc); 173186984Sluigi goto done; 173250974Swpaul } 173350974Swpaul 173450974Swpaul /* Disable interrupts. */ 173550974Swpaul CSR_WRITE_4(sc, SIS_IER, 0); 173650974Swpaul 173750974Swpaul for (;;) { 1738139717Sphk SIS_LOCK_ASSERT(sc); 173950974Swpaul /* Reading the ISR register clears all interrupts. */ 174050974Swpaul status = CSR_READ_4(sc, SIS_ISR); 174150974Swpaul 174250974Swpaul if ((status & SIS_INTRS) == 0) 174350974Swpaul break; 174450974Swpaul 174586984Sluigi if (status & 174686984Sluigi (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | 174786984Sluigi SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) ) 174850974Swpaul sis_txeof(sc); 174950974Swpaul 175086984Sluigi if (status & (SIS_ISR_RX_DESC_OK|SIS_ISR_RX_OK|SIS_ISR_RX_IDLE)) 175150974Swpaul sis_rxeof(sc); 175250974Swpaul 175386984Sluigi if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW)) 175450974Swpaul sis_rxeoc(sc); 175550974Swpaul 175686984Sluigi if (status & (SIS_ISR_RX_IDLE)) 175786984Sluigi SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 175886984Sluigi 175950974Swpaul if (status & SIS_ISR_SYSERR) { 176050974Swpaul sis_reset(sc); 1761139715Sphk sis_initl(sc); 176250974Swpaul } 176350974Swpaul } 176450974Swpaul 176550974Swpaul /* Re-enable interrupts. */ 176650974Swpaul CSR_WRITE_4(sc, SIS_IER, 1); 176750974Swpaul 1768131455Smlaier if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1769139714Sphk sis_startl(ifp); 177086984Sluigidone: 177167087Swpaul SIS_UNLOCK(sc); 177267087Swpaul 177350974Swpaul return; 177450974Swpaul} 177550974Swpaul 177650974Swpaul/* 177750974Swpaul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 177850974Swpaul * pointers to the fragment pointers. 177950974Swpaul */ 1780102334Salfredstatic int 1781139740Sphksis_encap(struct sis_softc *sc, struct mbuf **m_head, uint32_t *txidx) 178250974Swpaul{ 178350974Swpaul struct sis_desc *f = NULL; 178450974Swpaul struct mbuf *m; 1785112808Ssilby int frag, cur, cnt = 0, chainlen = 0; 178650974Swpaul 178750974Swpaul /* 1788112808Ssilby * If there's no way we can send any packets, return now. 1789112808Ssilby */ 1790139690Sphk if (SIS_TX_LIST_CNT - sc->sis_tx_cnt < 2) 1791112808Ssilby return (ENOBUFS); 1792112808Ssilby 1793112808Ssilby /* 1794112808Ssilby * Count the number of frags in this chain to see if 1795112808Ssilby * we need to m_defrag. Since the descriptor list is shared 1796112808Ssilby * by all packets, we'll m_defrag long chains so that they 1797112808Ssilby * do not use up the entire list, even if they would fit. 1798112808Ssilby */ 1799112808Ssilby 1800121262Ssilby for (m = *m_head; m != NULL; m = m->m_next) 1801112808Ssilby chainlen++; 1802112808Ssilby 1803112808Ssilby if ((chainlen > SIS_TX_LIST_CNT / 4) || 1804139690Sphk ((SIS_TX_LIST_CNT - (chainlen + sc->sis_tx_cnt)) < 2)) { 1805121262Ssilby m = m_defrag(*m_head, M_DONTWAIT); 1806112808Ssilby if (m == NULL) 1807112808Ssilby return (ENOBUFS); 1808121262Ssilby *m_head = m; 1809112808Ssilby } 1810112808Ssilby 1811112808Ssilby /* 181250974Swpaul * Start packing the mbufs in this chain into 181350974Swpaul * the fragment pointers. Stop when we run out 181450974Swpaul * of fragments or hit the end of the mbuf chain. 181550974Swpaul */ 181650974Swpaul cur = frag = *txidx; 181750974Swpaul 1818121262Ssilby for (m = *m_head; m != NULL; m = m->m_next) { 181950974Swpaul if (m->m_len != 0) { 182051042Swpaul if ((SIS_TX_LIST_CNT - 1821139690Sphk (sc->sis_tx_cnt + cnt)) < 2) 182250974Swpaul return(ENOBUFS); 1823139690Sphk f = &sc->sis_tx_list[frag]; 182450974Swpaul f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; 182581713Swpaul bus_dmamap_create(sc->sis_tag, 0, &f->sis_map); 182681713Swpaul bus_dmamap_load(sc->sis_tag, f->sis_map, 182781713Swpaul mtod(m, void *), m->m_len, 182881713Swpaul sis_dma_map_desc_ptr, f, 0); 182981713Swpaul bus_dmamap_sync(sc->sis_tag, 183081713Swpaul f->sis_map, BUS_DMASYNC_PREREAD); 183150974Swpaul if (cnt != 0) 183250974Swpaul f->sis_ctl |= SIS_CMDSTS_OWN; 183350974Swpaul cur = frag; 183450974Swpaul SIS_INC(frag, SIS_TX_LIST_CNT); 183550974Swpaul cnt++; 183650974Swpaul } 183750974Swpaul } 183850974Swpaul 183950974Swpaul if (m != NULL) 184050974Swpaul return(ENOBUFS); 184150974Swpaul 1842139690Sphk sc->sis_tx_list[cur].sis_mbuf = *m_head; 1843139690Sphk sc->sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1844139690Sphk sc->sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1845139690Sphk sc->sis_tx_cnt += cnt; 184650974Swpaul *txidx = frag; 184750974Swpaul 184850974Swpaul return(0); 184950974Swpaul} 185050974Swpaul 185150974Swpaul/* 185250974Swpaul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 185350974Swpaul * to the mbuf data regions directly in the transmit lists. We also save a 185450974Swpaul * copy of the pointers since the transmit list fragment pointers are 185550974Swpaul * physical addresses. 185650974Swpaul */ 185750974Swpaul 1858102334Salfredstatic void 1859139717Sphksis_start(struct ifnet *ifp) 186050974Swpaul{ 186150974Swpaul struct sis_softc *sc; 1862139714Sphk 1863139714Sphk sc = ifp->if_softc; 1864139714Sphk SIS_LOCK(sc); 1865139714Sphk sis_startl(ifp); 1866139714Sphk SIS_UNLOCK(sc); 1867139714Sphk} 1868139714Sphk 1869139714Sphkstatic void 1870139714Sphksis_startl(struct ifnet *ifp) 1871139714Sphk{ 1872139714Sphk struct sis_softc *sc; 187350974Swpaul struct mbuf *m_head = NULL; 1874136269Smlaier u_int32_t idx, queued = 0; 187550974Swpaul 187650974Swpaul sc = ifp->if_softc; 187750974Swpaul 1878139714Sphk SIS_LOCK_ASSERT(sc); 1879139714Sphk 1880139714Sphk if (!sc->sis_link) 188164963Swpaul return; 188264963Swpaul 1883139690Sphk idx = sc->sis_tx_prod; 188450974Swpaul 1885139714Sphk if (ifp->if_flags & IFF_OACTIVE) 188650974Swpaul return; 188750974Swpaul 1888139690Sphk while(sc->sis_tx_list[idx].sis_mbuf == NULL) { 1889131455Smlaier IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 189050974Swpaul if (m_head == NULL) 189150974Swpaul break; 189250974Swpaul 1893121262Ssilby if (sis_encap(sc, &m_head, &idx)) { 1894131455Smlaier IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 189550974Swpaul ifp->if_flags |= IFF_OACTIVE; 189650974Swpaul break; 189750974Swpaul } 189850974Swpaul 1899136269Smlaier queued++; 1900136269Smlaier 190150974Swpaul /* 190250974Swpaul * If there's a BPF listener, bounce a copy of this frame 190350974Swpaul * to him. 190450974Swpaul */ 1905106936Ssam BPF_MTAP(ifp, m_head); 190651583Swpaul 190750974Swpaul } 190850974Swpaul 1909136269Smlaier if (queued) { 1910136269Smlaier /* Transmit */ 1911139690Sphk sc->sis_tx_prod = idx; 1912136269Smlaier SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 191350974Swpaul 1914136269Smlaier /* 1915136269Smlaier * Set a timeout in case the chip goes out to lunch. 1916136269Smlaier */ 1917136269Smlaier ifp->if_timer = 5; 1918136269Smlaier } 191950974Swpaul} 192050974Swpaul 1921102334Salfredstatic void 1922139715Sphksis_init(void *xsc) 192350974Swpaul{ 192450974Swpaul struct sis_softc *sc = xsc; 1925139715Sphk 1926139715Sphk SIS_LOCK(sc); 1927139717Sphk sis_initl(sc); 1928139715Sphk SIS_UNLOCK(sc); 1929139715Sphk} 1930139715Sphk 1931139715Sphkstatic void 1932139717Sphksis_initl(struct sis_softc *sc) 1933139715Sphk{ 193450974Swpaul struct ifnet *ifp = &sc->arpcom.ac_if; 193550974Swpaul struct mii_data *mii; 193650974Swpaul 1937139715Sphk SIS_LOCK_ASSERT(sc); 193850974Swpaul 193950974Swpaul /* 194050974Swpaul * Cancel pending I/O and free all RX/TX buffers. 194150974Swpaul */ 194250974Swpaul sis_stop(sc); 1943123833Sphk sc->sis_stopped = 0; 194450974Swpaul 1945119712Sphk#ifdef notyet 1946119712Sphk if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) { 1947119712Sphk /* 1948119712Sphk * Configure 400usec of interrupt holdoff. This is based 1949119712Sphk * on emperical tests on a Soekris 4801. 1950119712Sphk */ 1951119712Sphk CSR_WRITE_4(sc, NS_IHR, 0x100 | 4); 1952119712Sphk } 1953119712Sphk#endif 1954119712Sphk 195550974Swpaul mii = device_get_softc(sc->sis_miibus); 195650974Swpaul 195750974Swpaul /* Set MAC address */ 195862672Swpaul if (sc->sis_type == SIS_TYPE_83815) { 195962672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 196062672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 196162672Swpaul ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 196262672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 196362672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 196462672Swpaul ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 196562672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 196662672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 196762672Swpaul ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 196862672Swpaul } else { 196962672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 197062672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 197162672Swpaul ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 197262672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 197362672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 197462672Swpaul ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 197562672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 197662672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 197762672Swpaul ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 197862672Swpaul } 197950974Swpaul 198050974Swpaul /* Init circular RX list. */ 198150974Swpaul if (sis_list_rx_init(sc) == ENOBUFS) { 198250974Swpaul printf("sis%d: initialization failed: no " 198350974Swpaul "memory for rx buffers\n", sc->sis_unit); 198450974Swpaul sis_stop(sc); 198550974Swpaul return; 198650974Swpaul } 198750974Swpaul 198850974Swpaul /* 198950974Swpaul * Init tx descriptors. 199050974Swpaul */ 199150974Swpaul sis_list_tx_init(sc); 199250974Swpaul 199362672Swpaul /* 1994123491Sphk * Page 78 of the DP83815 data sheet (september 2002 version) 1995123491Sphk * recommends the following register settings "for optimum 1996123491Sphk * performance." for rev 15C. The driver from NS also sets 1997123491Sphk * the PHY_CR register for later versions. 1998123491Sphk */ 1999123491Sphk if (sc->sis_type == SIS_TYPE_83815) { 2000123491Sphk CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 2001123491Sphk /* DC speed = 01 */ 2002123491Sphk CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 2003123491Sphk if (sc->sis_srr == NS_SRR_15C) { 2004123491Sphk /* set val for c2 */ 2005123491Sphk CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 2006123491Sphk /* load/kill c2 */ 2007123491Sphk CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 2008123491Sphk /* rais SD off, from 4 to c */ 2009123491Sphk CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 2010123491Sphk } 2011123491Sphk CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 2012123491Sphk } 2013123491Sphk 2014123491Sphk 2015123491Sphk /* 201662672Swpaul * For the NatSemi chip, we have to explicitly enable the 201762672Swpaul * reception of ARP frames, as well as turn on the 'perfect 201862672Swpaul * match' filter where we store the station address, otherwise 201962672Swpaul * we won't receive unicasts meant for this host. 202062672Swpaul */ 202162672Swpaul if (sc->sis_type == SIS_TYPE_83815) { 202262672Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 202362672Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 202462672Swpaul } 202562672Swpaul 202650974Swpaul /* If we want promiscuous mode, set the allframes bit. */ 202750974Swpaul if (ifp->if_flags & IFF_PROMISC) { 202850974Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 202950974Swpaul } else { 203050974Swpaul SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 203150974Swpaul } 203250974Swpaul 203350974Swpaul /* 203450974Swpaul * Set the capture broadcast bit to capture broadcast frames. 203550974Swpaul */ 203650974Swpaul if (ifp->if_flags & IFF_BROADCAST) { 203750974Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 203850974Swpaul } else { 203950974Swpaul SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 204050974Swpaul } 204150974Swpaul 204250974Swpaul /* 204350974Swpaul * Load the multicast filter. 204450974Swpaul */ 204562672Swpaul if (sc->sis_type == SIS_TYPE_83815) 204662672Swpaul sis_setmulti_ns(sc); 204762672Swpaul else 204862672Swpaul sis_setmulti_sis(sc); 204950974Swpaul 205050974Swpaul /* Turn the receive filter on */ 205150974Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 205250974Swpaul 205350974Swpaul /* 205450974Swpaul * Load the address of the RX and TX lists. 205550974Swpaul */ 2056139690Sphk CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_rx_paddr); 2057139690Sphk CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_tx_paddr); 205850974Swpaul 2059109059Smbr /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of 2060109059Smbr * the PCI bus. When this bit is set, the Max DMA Burst Size 2061109059Smbr * for TX/RX DMA should be no larger than 16 double words. 2062109059Smbr */ 2063109059Smbr if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) { 2064109059Smbr CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); 2065109059Smbr } else { 2066109059Smbr CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); 2067109059Smbr } 206864963Swpaul 206987390Sjhay /* Accept Long Packets for VLAN support */ 207087390Sjhay SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 207187390Sjhay 207250974Swpaul /* Set TX configuration */ 207364963Swpaul if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 207464963Swpaul CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 207564963Swpaul } else { 207664963Swpaul CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 207764963Swpaul } 207850974Swpaul 207964963Swpaul /* Set full/half duplex mode. */ 208064963Swpaul if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 208164963Swpaul SIS_SETBIT(sc, SIS_TX_CFG, 208264963Swpaul (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 208364963Swpaul SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 208464963Swpaul } else { 208564963Swpaul SIS_CLRBIT(sc, SIS_TX_CFG, 208664963Swpaul (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 208764963Swpaul SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 208864963Swpaul } 208964963Swpaul 2090119712Sphk if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr < NS_SRR_16A && 2091119130Ssam IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 2092119130Ssam uint32_t reg; 2093119130Ssam 2094119130Ssam /* 2095119130Ssam * Some DP83815s experience problems when used with short 2096119130Ssam * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 2097119130Ssam * sequence adjusts the DSP's signal attenuation to fix the 2098119130Ssam * problem. 2099119130Ssam */ 2100119130Ssam CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 2101119130Ssam 2102119130Ssam reg = CSR_READ_4(sc, NS_PHY_DSPCFG); 2103123491Sphk /* Allow coefficient to be read */ 2104119130Ssam CSR_WRITE_4(sc, NS_PHY_DSPCFG, (reg & 0xfff) | 0x1000); 2105119130Ssam DELAY(100); 2106119130Ssam reg = CSR_READ_4(sc, NS_PHY_TDATA); 2107123491Sphk if ((reg & 0x0080) == 0 || 2108123491Sphk (reg > 0xd8 && reg <= 0xff)) { 2109119712Sphk device_printf(sc->sis_self, "Applying short cable fix (reg=%x)\n", reg); 2110119130Ssam CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8); 2111123491Sphk /* Adjust coefficient and prevent change */ 2112119130Ssam SIS_SETBIT(sc, NS_PHY_DSPCFG, 0x20); 2113119130Ssam } 2114119130Ssam CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 2115119130Ssam } 2116119130Ssam 211750974Swpaul /* 211850974Swpaul * Enable interrupts. 211950974Swpaul */ 212050974Swpaul CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 212187902Sluigi#ifdef DEVICE_POLLING 212287902Sluigi /* 212387902Sluigi * ... only enable interrupts if we are not polling, make sure 212487902Sluigi * they are off otherwise. 212587902Sluigi */ 2126102052Ssobomax if (ifp->if_flags & IFF_POLLING) 212787902Sluigi CSR_WRITE_4(sc, SIS_IER, 0); 212887902Sluigi else 212987902Sluigi#endif /* DEVICE_POLLING */ 213050974Swpaul CSR_WRITE_4(sc, SIS_IER, 1); 213150974Swpaul 213250974Swpaul /* Enable receiver and transmitter. */ 213350974Swpaul SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 213450974Swpaul SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 213550974Swpaul 213664963Swpaul#ifdef notdef 213750974Swpaul mii_mediachg(mii); 213864963Swpaul#endif 213950974Swpaul 214050974Swpaul ifp->if_flags |= IFF_RUNNING; 214150974Swpaul ifp->if_flags &= ~IFF_OACTIVE; 214250974Swpaul 2143117858Scognet if (!sc->in_tick) 2144119785Ssam callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 214550974Swpaul} 214650974Swpaul 214750974Swpaul/* 214850974Swpaul * Set media options. 214950974Swpaul */ 2150102334Salfredstatic int 2151139740Sphksis_ifmedia_upd(struct ifnet *ifp) 215250974Swpaul{ 215350974Swpaul struct sis_softc *sc; 215464963Swpaul struct mii_data *mii; 215550974Swpaul 215650974Swpaul sc = ifp->if_softc; 215750974Swpaul 215864963Swpaul mii = device_get_softc(sc->sis_miibus); 215964963Swpaul sc->sis_link = 0; 216064963Swpaul if (mii->mii_instance) { 216164963Swpaul struct mii_softc *miisc; 216272012Sphk LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 216364963Swpaul mii_phy_reset(miisc); 216464963Swpaul } 216564963Swpaul mii_mediachg(mii); 216650974Swpaul 216750974Swpaul return(0); 216850974Swpaul} 216950974Swpaul 217050974Swpaul/* 217150974Swpaul * Report current media status. 217250974Swpaul */ 2173102334Salfredstatic void 2174139740Sphksis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 217550974Swpaul{ 217650974Swpaul struct sis_softc *sc; 217750974Swpaul struct mii_data *mii; 217850974Swpaul 217950974Swpaul sc = ifp->if_softc; 218050974Swpaul 218150974Swpaul mii = device_get_softc(sc->sis_miibus); 218250974Swpaul mii_pollstat(mii); 218350974Swpaul ifmr->ifm_active = mii->mii_media_active; 218450974Swpaul ifmr->ifm_status = mii->mii_media_status; 218550974Swpaul} 218650974Swpaul 2187102334Salfredstatic int 2188139740Sphksis_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 218950974Swpaul{ 219050974Swpaul struct sis_softc *sc = ifp->if_softc; 219150974Swpaul struct ifreq *ifr = (struct ifreq *) data; 219250974Swpaul struct mii_data *mii; 219367087Swpaul int error = 0; 219450974Swpaul 219550974Swpaul switch(command) { 219650974Swpaul case SIOCSIFFLAGS: 219750974Swpaul if (ifp->if_flags & IFF_UP) { 219850974Swpaul sis_init(sc); 2199139741Sphk } else if (ifp->if_flags & IFF_RUNNING) { 2200139741Sphk SIS_LOCK(sc); 2201139741Sphk sis_stop(sc); 2202139741Sphk SIS_UNLOCK(sc); 220350974Swpaul } 220450974Swpaul error = 0; 220550974Swpaul break; 220650974Swpaul case SIOCADDMULTI: 220750974Swpaul case SIOCDELMULTI: 220881713Swpaul SIS_LOCK(sc); 220962672Swpaul if (sc->sis_type == SIS_TYPE_83815) 221062672Swpaul sis_setmulti_ns(sc); 221162672Swpaul else 221262672Swpaul sis_setmulti_sis(sc); 221381713Swpaul SIS_UNLOCK(sc); 221450974Swpaul error = 0; 221550974Swpaul break; 221650974Swpaul case SIOCGIFMEDIA: 221750974Swpaul case SIOCSIFMEDIA: 221850974Swpaul mii = device_get_softc(sc->sis_miibus); 221981713Swpaul SIS_LOCK(sc); 222050974Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 222181713Swpaul SIS_UNLOCK(sc); 222250974Swpaul break; 2223128138Sru case SIOCSIFCAP: 2224129633Syar ifp->if_capenable &= ~IFCAP_POLLING; 2225129633Syar ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_POLLING; 2226128138Sru break; 222750974Swpaul default: 2228106936Ssam error = ether_ioctl(ifp, command, data); 222950974Swpaul break; 223050974Swpaul } 223150974Swpaul 223250974Swpaul return(error); 223350974Swpaul} 223450974Swpaul 2235102334Salfredstatic void 2236139740Sphksis_watchdog(struct ifnet *ifp) 223750974Swpaul{ 2238139797Sphk struct sis_softc *sc; 223950974Swpaul 224050974Swpaul sc = ifp->if_softc; 224150974Swpaul 224267087Swpaul SIS_LOCK(sc); 2243139797Sphk if (sc->sis_stopped) { 2244139797Sphk SIS_UNLOCK(sc); 2245139797Sphk return; 2246139797Sphk } 224767087Swpaul 224850974Swpaul ifp->if_oerrors++; 224950974Swpaul printf("sis%d: watchdog timeout\n", sc->sis_unit); 225050974Swpaul 225150974Swpaul sis_stop(sc); 225250974Swpaul sis_reset(sc); 2253139715Sphk sis_initl(sc); 225450974Swpaul 2255131455Smlaier if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2256139714Sphk sis_startl(ifp); 225750974Swpaul 225867087Swpaul SIS_UNLOCK(sc); 225950974Swpaul} 226050974Swpaul 226150974Swpaul/* 226250974Swpaul * Stop the adapter and free any mbufs allocated to the 226350974Swpaul * RX and TX lists. 226450974Swpaul */ 2265102334Salfredstatic void 2266139740Sphksis_stop(struct sis_softc *sc) 226750974Swpaul{ 2268139708Sphk int i; 226950974Swpaul struct ifnet *ifp; 227050974Swpaul 2271123833Sphk if (sc->sis_stopped) 2272123833Sphk return; 2273139717Sphk SIS_LOCK_ASSERT(sc); 227450974Swpaul ifp = &sc->arpcom.ac_if; 227550974Swpaul ifp->if_timer = 0; 227650974Swpaul 2277119785Ssam callout_stop(&sc->sis_stat_ch); 227887472Speter 227987472Speter ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 228087902Sluigi#ifdef DEVICE_POLLING 228187902Sluigi ether_poll_deregister(ifp); 228287902Sluigi#endif 228350974Swpaul CSR_WRITE_4(sc, SIS_IER, 0); 228450974Swpaul CSR_WRITE_4(sc, SIS_IMR, 0); 2285139798Sphk CSR_READ_4(sc, SIS_ISR); /* clear any interrupts already pending */ 228650974Swpaul SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 228750974Swpaul DELAY(1000); 228850974Swpaul CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 228950974Swpaul CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 229050974Swpaul 229164963Swpaul sc->sis_link = 0; 229264963Swpaul 229350974Swpaul /* 229450974Swpaul * Free data in the RX lists. 229550974Swpaul */ 229650974Swpaul for (i = 0; i < SIS_RX_LIST_CNT; i++) { 2297139690Sphk if (sc->sis_rx_list[i].sis_mbuf != NULL) { 229881713Swpaul bus_dmamap_unload(sc->sis_tag, 2299139690Sphk sc->sis_rx_list[i].sis_map); 230081713Swpaul bus_dmamap_destroy(sc->sis_tag, 2301139690Sphk sc->sis_rx_list[i].sis_map); 2302139690Sphk m_freem(sc->sis_rx_list[i].sis_mbuf); 2303139690Sphk sc->sis_rx_list[i].sis_mbuf = NULL; 230450974Swpaul } 230550974Swpaul } 2306139690Sphk bzero(sc->sis_rx_list, 2307139690Sphk sizeof(sc->sis_rx_list)); 230850974Swpaul 230950974Swpaul /* 231050974Swpaul * Free the TX list buffers. 231150974Swpaul */ 231250974Swpaul for (i = 0; i < SIS_TX_LIST_CNT; i++) { 2313139690Sphk if (sc->sis_tx_list[i].sis_mbuf != NULL) { 231481713Swpaul bus_dmamap_unload(sc->sis_tag, 2315139690Sphk sc->sis_tx_list[i].sis_map); 231681713Swpaul bus_dmamap_destroy(sc->sis_tag, 2317139690Sphk sc->sis_tx_list[i].sis_map); 2318139690Sphk m_freem(sc->sis_tx_list[i].sis_mbuf); 2319139690Sphk sc->sis_tx_list[i].sis_mbuf = NULL; 232050974Swpaul } 232150974Swpaul } 232250974Swpaul 2323139690Sphk bzero(sc->sis_tx_list, 2324139690Sphk sizeof(sc->sis_tx_list)); 232550974Swpaul 2326123833Sphk sc->sis_stopped = 1; 232750974Swpaul} 232850974Swpaul 232950974Swpaul/* 233050974Swpaul * Stop all chip I/O so that the kernel's probe routines don't 233150974Swpaul * get confused by errant DMAs when rebooting. 233250974Swpaul */ 2333102334Salfredstatic void 2334139717Sphksis_shutdown(device_t dev) 233550974Swpaul{ 233650974Swpaul struct sis_softc *sc; 233750974Swpaul 233850974Swpaul sc = device_get_softc(dev); 233967087Swpaul SIS_LOCK(sc); 234050974Swpaul sis_reset(sc); 234150974Swpaul sis_stop(sc); 234267087Swpaul SIS_UNLOCK(sc); 234350974Swpaul} 2344