if_sis.c revision 139708
150974Swpaul/* 250974Swpaul * Copyright (c) 1997, 1998, 1999 350974Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 450974Swpaul * 550974Swpaul * Redistribution and use in source and binary forms, with or without 650974Swpaul * modification, are permitted provided that the following conditions 750974Swpaul * are met: 850974Swpaul * 1. Redistributions of source code must retain the above copyright 950974Swpaul * notice, this list of conditions and the following disclaimer. 1050974Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1150974Swpaul * notice, this list of conditions and the following disclaimer in the 1250974Swpaul * documentation and/or other materials provided with the distribution. 1350974Swpaul * 3. All advertising materials mentioning features or use of this software 1450974Swpaul * must display the following acknowledgement: 1550974Swpaul * This product includes software developed by Bill Paul. 1650974Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1750974Swpaul * may be used to endorse or promote products derived from this software 1850974Swpaul * without specific prior written permission. 1950974Swpaul * 2050974Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2150974Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2250974Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2350974Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2450974Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2550974Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2650974Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2750974Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2850974Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2950974Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3050974Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3150974Swpaul */ 3250974Swpaul 33122678Sobrien#include <sys/cdefs.h> 34122678Sobrien__FBSDID("$FreeBSD: head/sys/pci/if_sis.c 139708 2005-01-05 09:02:05Z phk $"); 35122678Sobrien 3650974Swpaul/* 3750974Swpaul * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 3850974Swpaul * available from http://www.sis.com.tw. 3950974Swpaul * 4064963Swpaul * This driver also supports the NatSemi DP83815. Datasheets are 4164963Swpaul * available from http://www.national.com. 4264963Swpaul * 4350974Swpaul * Written by Bill Paul <wpaul@ee.columbia.edu> 4450974Swpaul * Electrical Engineering Department 4550974Swpaul * Columbia University, New York City 4650974Swpaul */ 4750974Swpaul/* 4850974Swpaul * The SiS 900 is a fairly simple chip. It uses bus master DMA with 4950974Swpaul * simple TX and RX descriptors of 3 longwords in size. The receiver 5050974Swpaul * has a single perfect filter entry for the station address and a 5150974Swpaul * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 5250974Swpaul * transceiver while the 7016 requires an external transceiver chip. 5350974Swpaul * Both chips offer the standard bit-bang MII interface as well as 5450974Swpaul * an enchanced PHY interface which simplifies accessing MII registers. 5550974Swpaul * 5650974Swpaul * The only downside to this chipset is that RX descriptors must be 5750974Swpaul * longword aligned. 5850974Swpaul */ 5950974Swpaul 6050974Swpaul#include <sys/param.h> 6150974Swpaul#include <sys/systm.h> 6250974Swpaul#include <sys/sockio.h> 6350974Swpaul#include <sys/mbuf.h> 6450974Swpaul#include <sys/malloc.h> 6550974Swpaul#include <sys/kernel.h> 66129876Sphk#include <sys/module.h> 6750974Swpaul#include <sys/socket.h> 6887059Sluigi#include <sys/sysctl.h> 6950974Swpaul 7050974Swpaul#include <net/if.h> 7150974Swpaul#include <net/if_arp.h> 7250974Swpaul#include <net/ethernet.h> 7350974Swpaul#include <net/if_dl.h> 7450974Swpaul#include <net/if_media.h> 7587390Sjhay#include <net/if_types.h> 7687390Sjhay#include <net/if_vlan_var.h> 7750974Swpaul 7850974Swpaul#include <net/bpf.h> 7950974Swpaul 8050974Swpaul#include <machine/bus_pio.h> 8150974Swpaul#include <machine/bus_memio.h> 8250974Swpaul#include <machine/bus.h> 8350974Swpaul#include <machine/resource.h> 8450974Swpaul#include <sys/bus.h> 8550974Swpaul#include <sys/rman.h> 8650974Swpaul 8750974Swpaul#include <dev/mii/mii.h> 8850974Swpaul#include <dev/mii/miivar.h> 8950974Swpaul 90119288Simp#include <dev/pci/pcireg.h> 91119288Simp#include <dev/pci/pcivar.h> 9250974Swpaul 9350974Swpaul#define SIS_USEIOSPACE 9450974Swpaul 9550974Swpaul#include <pci/if_sisreg.h> 9650974Swpaul 97113506SmdoddMODULE_DEPEND(sis, pci, 1, 1, 1); 98113506SmdoddMODULE_DEPEND(sis, ether, 1, 1, 1); 9959758SpeterMODULE_DEPEND(sis, miibus, 1, 1, 1); 10059758Speter 10151089Speter/* "controller miibus0" required. See GENERIC if you get errors here. */ 10250974Swpaul#include "miibus_if.h" 10350974Swpaul 10450974Swpaul/* 10550974Swpaul * Various supported device vendors/types and their names. 10650974Swpaul */ 10750974Swpaulstatic struct sis_type sis_devs[] = { 10850974Swpaul { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 10950974Swpaul { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 110119712Sphk { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" }, 11150974Swpaul { 0, 0, NULL } 11250974Swpaul}; 11350974Swpaul 11492739Salfredstatic int sis_probe (device_t); 11592739Salfredstatic int sis_attach (device_t); 11692739Salfredstatic int sis_detach (device_t); 11750974Swpaul 11892739Salfredstatic int sis_newbuf (struct sis_softc *, 11992739Salfred struct sis_desc *, struct mbuf *); 12092739Salfredstatic int sis_encap (struct sis_softc *, 121121262Ssilby struct mbuf **, u_int32_t *); 12292739Salfredstatic void sis_rxeof (struct sis_softc *); 12392739Salfredstatic void sis_rxeoc (struct sis_softc *); 12492739Salfredstatic void sis_txeof (struct sis_softc *); 12592739Salfredstatic void sis_intr (void *); 12692739Salfredstatic void sis_tick (void *); 12792739Salfredstatic void sis_start (struct ifnet *); 12892739Salfredstatic int sis_ioctl (struct ifnet *, u_long, caddr_t); 12992739Salfredstatic void sis_init (void *); 13092739Salfredstatic void sis_stop (struct sis_softc *); 13192739Salfredstatic void sis_watchdog (struct ifnet *); 13292739Salfredstatic void sis_shutdown (device_t); 13392739Salfredstatic int sis_ifmedia_upd (struct ifnet *); 13492739Salfredstatic void sis_ifmedia_sts (struct ifnet *, struct ifmediareq *); 13550974Swpaul 13692739Salfredstatic u_int16_t sis_reverse (u_int16_t); 13792739Salfredstatic void sis_delay (struct sis_softc *); 13892739Salfredstatic void sis_eeprom_idle (struct sis_softc *); 13992739Salfredstatic void sis_eeprom_putbyte (struct sis_softc *, int); 14092739Salfredstatic void sis_eeprom_getword (struct sis_softc *, int, u_int16_t *); 14192739Salfredstatic void sis_read_eeprom (struct sis_softc *, caddr_t, int, int, int); 14272197Swpaul#ifdef __i386__ 14392739Salfredstatic void sis_read_cmos (struct sis_softc *, device_t, caddr_t, 14492739Salfred int, int); 14592739Salfredstatic void sis_read_mac (struct sis_softc *, device_t, caddr_t); 14692739Salfredstatic device_t sis_find_bridge (device_t); 14772197Swpaul#endif 14872197Swpaul 149109060Smbrstatic void sis_mii_sync (struct sis_softc *); 150109060Smbrstatic void sis_mii_send (struct sis_softc *, u_int32_t, int); 151109060Smbrstatic int sis_mii_readreg (struct sis_softc *, struct sis_mii_frame *); 152109060Smbrstatic int sis_mii_writereg (struct sis_softc *, struct sis_mii_frame *); 15392739Salfredstatic int sis_miibus_readreg (device_t, int, int); 15492739Salfredstatic int sis_miibus_writereg (device_t, int, int, int); 15592739Salfredstatic void sis_miibus_statchg (device_t); 15650974Swpaul 15792739Salfredstatic void sis_setmulti_sis (struct sis_softc *); 15892739Salfredstatic void sis_setmulti_ns (struct sis_softc *); 159123289Sobrienstatic uint32_t sis_mchash (struct sis_softc *, const uint8_t *); 16092739Salfredstatic void sis_reset (struct sis_softc *); 16192739Salfredstatic int sis_list_rx_init (struct sis_softc *); 16292739Salfredstatic int sis_list_tx_init (struct sis_softc *); 16350974Swpaul 164139689Sphkstatic bus_dmamap_callback_t sis_dma_map_desc_ptr; 16592739Salfredstatic void sis_dma_map_desc_next (void *, bus_dma_segment_t *, int, int); 16692739Salfredstatic void sis_dma_map_ring (void *, bus_dma_segment_t *, int, int); 16750974Swpaul#ifdef SIS_USEIOSPACE 16850974Swpaul#define SIS_RES SYS_RES_IOPORT 16950974Swpaul#define SIS_RID SIS_PCI_LOIO 17050974Swpaul#else 17151030Swpaul#define SIS_RES SYS_RES_MEMORY 17251030Swpaul#define SIS_RID SIS_PCI_LOMEM 17350974Swpaul#endif 17450974Swpaul 17550974Swpaulstatic device_method_t sis_methods[] = { 17650974Swpaul /* Device interface */ 17750974Swpaul DEVMETHOD(device_probe, sis_probe), 17850974Swpaul DEVMETHOD(device_attach, sis_attach), 17950974Swpaul DEVMETHOD(device_detach, sis_detach), 18050974Swpaul DEVMETHOD(device_shutdown, sis_shutdown), 18150974Swpaul 18250974Swpaul /* bus interface */ 18350974Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 18450974Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 18550974Swpaul 18650974Swpaul /* MII interface */ 18750974Swpaul DEVMETHOD(miibus_readreg, sis_miibus_readreg), 18850974Swpaul DEVMETHOD(miibus_writereg, sis_miibus_writereg), 18950974Swpaul DEVMETHOD(miibus_statchg, sis_miibus_statchg), 19050974Swpaul 19150974Swpaul { 0, 0 } 19250974Swpaul}; 19350974Swpaul 19450974Swpaulstatic driver_t sis_driver = { 19551455Swpaul "sis", 19650974Swpaul sis_methods, 19750974Swpaul sizeof(struct sis_softc) 19850974Swpaul}; 19950974Swpaul 20050974Swpaulstatic devclass_t sis_devclass; 20150974Swpaul 202113506SmdoddDRIVER_MODULE(sis, pci, sis_driver, sis_devclass, 0, 0); 20351473SwpaulDRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 20450974Swpaul 20550974Swpaul#define SIS_SETBIT(sc, reg, x) \ 20650974Swpaul CSR_WRITE_4(sc, reg, \ 20750974Swpaul CSR_READ_4(sc, reg) | (x)) 20850974Swpaul 20950974Swpaul#define SIS_CLRBIT(sc, reg, x) \ 21050974Swpaul CSR_WRITE_4(sc, reg, \ 21150974Swpaul CSR_READ_4(sc, reg) & ~(x)) 21250974Swpaul 21350974Swpaul#define SIO_SET(x) \ 21450974Swpaul CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 21550974Swpaul 21650974Swpaul#define SIO_CLR(x) \ 21750974Swpaul CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 21850974Swpaul 21981713Swpaulstatic void 22081713Swpaulsis_dma_map_desc_next(arg, segs, nseg, error) 22181713Swpaul void *arg; 22281713Swpaul bus_dma_segment_t *segs; 22381713Swpaul int nseg, error; 22481713Swpaul{ 22581713Swpaul struct sis_desc *r; 22681713Swpaul 22781713Swpaul r = arg; 22881713Swpaul r->sis_next = segs->ds_addr; 22981713Swpaul 23081713Swpaul return; 23181713Swpaul} 23281713Swpaul 23381713Swpaulstatic void 23481713Swpaulsis_dma_map_desc_ptr(arg, segs, nseg, error) 23581713Swpaul void *arg; 23681713Swpaul bus_dma_segment_t *segs; 23781713Swpaul int nseg, error; 23881713Swpaul{ 23981713Swpaul struct sis_desc *r; 24081713Swpaul 24181713Swpaul r = arg; 24281713Swpaul r->sis_ptr = segs->ds_addr; 24381713Swpaul 24481713Swpaul return; 24581713Swpaul} 24681713Swpaul 24781713Swpaulstatic void 24881713Swpaulsis_dma_map_ring(arg, segs, nseg, error) 24981713Swpaul void *arg; 25081713Swpaul bus_dma_segment_t *segs; 25181713Swpaul int nseg, error; 25281713Swpaul{ 25381713Swpaul u_int32_t *p; 25481713Swpaul 25581713Swpaul p = arg; 25681713Swpaul *p = segs->ds_addr; 25781713Swpaul 25881713Swpaul return; 25981713Swpaul} 26081713Swpaul 26162672Swpaul/* 26262672Swpaul * Routine to reverse the bits in a word. Stolen almost 26362672Swpaul * verbatim from /usr/games/fortune. 26462672Swpaul */ 265102334Salfredstatic u_int16_t 266102334Salfredsis_reverse(n) 26762672Swpaul u_int16_t n; 26862672Swpaul{ 26962672Swpaul n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 27062672Swpaul n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 27162672Swpaul n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 27262672Swpaul n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 27362672Swpaul 27462672Swpaul return(n); 27562672Swpaul} 27662672Swpaul 277102334Salfredstatic void 278102334Salfredsis_delay(sc) 27950974Swpaul struct sis_softc *sc; 28050974Swpaul{ 28150974Swpaul int idx; 28250974Swpaul 28350974Swpaul for (idx = (300 / 33) + 1; idx > 0; idx--) 28450974Swpaul CSR_READ_4(sc, SIS_CSR); 28550974Swpaul 28650974Swpaul return; 28750974Swpaul} 28850974Swpaul 289102334Salfredstatic void 290102334Salfredsis_eeprom_idle(sc) 29150974Swpaul struct sis_softc *sc; 29250974Swpaul{ 293139708Sphk int i; 29450974Swpaul 29550974Swpaul SIO_SET(SIS_EECTL_CSEL); 29650974Swpaul sis_delay(sc); 29750974Swpaul SIO_SET(SIS_EECTL_CLK); 29850974Swpaul sis_delay(sc); 29950974Swpaul 30050974Swpaul for (i = 0; i < 25; i++) { 30150974Swpaul SIO_CLR(SIS_EECTL_CLK); 30250974Swpaul sis_delay(sc); 30350974Swpaul SIO_SET(SIS_EECTL_CLK); 30450974Swpaul sis_delay(sc); 30550974Swpaul } 30650974Swpaul 30750974Swpaul SIO_CLR(SIS_EECTL_CLK); 30850974Swpaul sis_delay(sc); 30950974Swpaul SIO_CLR(SIS_EECTL_CSEL); 31050974Swpaul sis_delay(sc); 31150974Swpaul CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 31250974Swpaul 31350974Swpaul return; 31450974Swpaul} 31550974Swpaul 31650974Swpaul/* 31750974Swpaul * Send a read command and address to the EEPROM, check for ACK. 31850974Swpaul */ 319102334Salfredstatic void 320102334Salfredsis_eeprom_putbyte(sc, addr) 32150974Swpaul struct sis_softc *sc; 32250974Swpaul int addr; 32350974Swpaul{ 324139708Sphk int d, i; 32550974Swpaul 32650974Swpaul d = addr | SIS_EECMD_READ; 32750974Swpaul 32850974Swpaul /* 32950974Swpaul * Feed in each bit and stobe the clock. 33050974Swpaul */ 33150974Swpaul for (i = 0x400; i; i >>= 1) { 33250974Swpaul if (d & i) { 33350974Swpaul SIO_SET(SIS_EECTL_DIN); 33450974Swpaul } else { 33550974Swpaul SIO_CLR(SIS_EECTL_DIN); 33650974Swpaul } 33750974Swpaul sis_delay(sc); 33850974Swpaul SIO_SET(SIS_EECTL_CLK); 33950974Swpaul sis_delay(sc); 34050974Swpaul SIO_CLR(SIS_EECTL_CLK); 34150974Swpaul sis_delay(sc); 34250974Swpaul } 34350974Swpaul 34450974Swpaul return; 34550974Swpaul} 34650974Swpaul 34750974Swpaul/* 34850974Swpaul * Read a word of data stored in the EEPROM at address 'addr.' 34950974Swpaul */ 350102334Salfredstatic void 351102334Salfredsis_eeprom_getword(sc, addr, dest) 35250974Swpaul struct sis_softc *sc; 35350974Swpaul int addr; 35450974Swpaul u_int16_t *dest; 35550974Swpaul{ 356139708Sphk int i; 35750974Swpaul u_int16_t word = 0; 35850974Swpaul 35950974Swpaul /* Force EEPROM to idle state. */ 36050974Swpaul sis_eeprom_idle(sc); 36150974Swpaul 36250974Swpaul /* Enter EEPROM access mode. */ 36350974Swpaul sis_delay(sc); 36462672Swpaul SIO_CLR(SIS_EECTL_CLK); 36562672Swpaul sis_delay(sc); 36650974Swpaul SIO_SET(SIS_EECTL_CSEL); 36750974Swpaul sis_delay(sc); 36850974Swpaul 36950974Swpaul /* 37050974Swpaul * Send address of word we want to read. 37150974Swpaul */ 37250974Swpaul sis_eeprom_putbyte(sc, addr); 37350974Swpaul 37450974Swpaul /* 37550974Swpaul * Start reading bits from EEPROM. 37650974Swpaul */ 37750974Swpaul for (i = 0x8000; i; i >>= 1) { 37850974Swpaul SIO_SET(SIS_EECTL_CLK); 37950974Swpaul sis_delay(sc); 38050974Swpaul if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 38150974Swpaul word |= i; 38250974Swpaul sis_delay(sc); 38350974Swpaul SIO_CLR(SIS_EECTL_CLK); 38450974Swpaul sis_delay(sc); 38550974Swpaul } 38650974Swpaul 38750974Swpaul /* Turn off EEPROM access mode. */ 38850974Swpaul sis_eeprom_idle(sc); 38950974Swpaul 39050974Swpaul *dest = word; 39150974Swpaul 39250974Swpaul return; 39350974Swpaul} 39450974Swpaul 39550974Swpaul/* 39650974Swpaul * Read a sequence of words from the EEPROM. 39750974Swpaul */ 398102334Salfredstatic void 399102334Salfredsis_read_eeprom(sc, dest, off, cnt, swap) 40050974Swpaul struct sis_softc *sc; 40150974Swpaul caddr_t dest; 40250974Swpaul int off; 40350974Swpaul int cnt; 40450974Swpaul int swap; 40550974Swpaul{ 40650974Swpaul int i; 40750974Swpaul u_int16_t word = 0, *ptr; 40850974Swpaul 40950974Swpaul for (i = 0; i < cnt; i++) { 41050974Swpaul sis_eeprom_getword(sc, off + i, &word); 41150974Swpaul ptr = (u_int16_t *)(dest + (i * 2)); 41250974Swpaul if (swap) 41350974Swpaul *ptr = ntohs(word); 41450974Swpaul else 41550974Swpaul *ptr = word; 41650974Swpaul } 41750974Swpaul 41850974Swpaul return; 41950974Swpaul} 42050974Swpaul 42172197Swpaul#ifdef __i386__ 422102334Salfredstatic device_t 423102334Salfredsis_find_bridge(dev) 42472197Swpaul device_t dev; 42572197Swpaul{ 42672197Swpaul devclass_t pci_devclass; 42772197Swpaul device_t *pci_devices; 42872197Swpaul int pci_count = 0; 42972197Swpaul device_t *pci_children; 43072197Swpaul int pci_childcount = 0; 43172197Swpaul device_t *busp, *childp; 43287994Sarchie device_t child = NULL; 43372197Swpaul int i, j; 43472197Swpaul 43572197Swpaul if ((pci_devclass = devclass_find("pci")) == NULL) 43672197Swpaul return(NULL); 43772197Swpaul 43872197Swpaul devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 43972197Swpaul 44072197Swpaul for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 44172197Swpaul pci_childcount = 0; 44272197Swpaul device_get_children(*busp, &pci_children, &pci_childcount); 44372197Swpaul for (j = 0, childp = pci_children; 44472197Swpaul j < pci_childcount; j++, childp++) { 44572197Swpaul if (pci_get_vendor(*childp) == SIS_VENDORID && 44672197Swpaul pci_get_device(*childp) == 0x0008) { 44787994Sarchie child = *childp; 44887994Sarchie goto done; 44972197Swpaul } 45072197Swpaul } 45172197Swpaul } 45272197Swpaul 45387994Sarchiedone: 45472197Swpaul free(pci_devices, M_TEMP); 45572197Swpaul free(pci_children, M_TEMP); 45687994Sarchie return(child); 45772197Swpaul} 45872197Swpaul 459102334Salfredstatic void 460102334Salfredsis_read_cmos(sc, dev, dest, off, cnt) 46172197Swpaul struct sis_softc *sc; 46272197Swpaul device_t dev; 46372197Swpaul caddr_t dest; 46472197Swpaul int off; 46572197Swpaul int cnt; 46672197Swpaul{ 46772197Swpaul device_t bridge; 46872197Swpaul u_int8_t reg; 46972197Swpaul int i; 47072197Swpaul bus_space_tag_t btag; 47172197Swpaul 47272197Swpaul bridge = sis_find_bridge(dev); 47372197Swpaul if (bridge == NULL) 47472197Swpaul return; 47572197Swpaul reg = pci_read_config(bridge, 0x48, 1); 47672197Swpaul pci_write_config(bridge, 0x48, reg|0x40, 1); 47772197Swpaul 47872197Swpaul /* XXX */ 47972197Swpaul btag = I386_BUS_SPACE_IO; 48072197Swpaul 48172197Swpaul for (i = 0; i < cnt; i++) { 48272197Swpaul bus_space_write_1(btag, 0x0, 0x70, i + off); 48372197Swpaul *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 48472197Swpaul } 48572197Swpaul 48672197Swpaul pci_write_config(bridge, 0x48, reg & ~0x40, 1); 48772197Swpaul return; 48872197Swpaul} 48989296Swpaul 490102334Salfredstatic void 491102334Salfredsis_read_mac(sc, dev, dest) 49289296Swpaul struct sis_softc *sc; 49389296Swpaul device_t dev; 49489296Swpaul caddr_t dest; 49589296Swpaul{ 49689296Swpaul u_int32_t filtsave, csrsave; 49789296Swpaul 49889296Swpaul filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 49989296Swpaul csrsave = CSR_READ_4(sc, SIS_CSR); 50089296Swpaul 50189296Swpaul CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 50289296Swpaul CSR_WRITE_4(sc, SIS_CSR, 0); 50389296Swpaul 50489296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 50589296Swpaul 50689296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 50789296Swpaul ((u_int16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 50889296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 50989296Swpaul ((u_int16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 51089296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 51189296Swpaul ((u_int16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 51289296Swpaul 51389296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 51489296Swpaul CSR_WRITE_4(sc, SIS_CSR, csrsave); 51589296Swpaul return; 51689296Swpaul} 51772197Swpaul#endif 51872197Swpaul 519109060Smbr/* 520109060Smbr * Sync the PHYs by setting data bit and strobing the clock 32 times. 521109060Smbr */ 522109060Smbrstatic void sis_mii_sync(sc) 523109060Smbr struct sis_softc *sc; 524109060Smbr{ 525139708Sphk int i; 526109060Smbr 527109060Smbr SIO_SET(SIS_MII_DIR|SIS_MII_DATA); 528109060Smbr 529109060Smbr for (i = 0; i < 32; i++) { 530109060Smbr SIO_SET(SIS_MII_CLK); 531109060Smbr DELAY(1); 532109060Smbr SIO_CLR(SIS_MII_CLK); 533109060Smbr DELAY(1); 534109060Smbr } 535109060Smbr 536109060Smbr return; 537109060Smbr} 538109060Smbr 539109060Smbr/* 540109060Smbr * Clock a series of bits through the MII. 541109060Smbr */ 542109060Smbrstatic void sis_mii_send(sc, bits, cnt) 543109060Smbr struct sis_softc *sc; 544109060Smbr u_int32_t bits; 545109060Smbr int cnt; 546109060Smbr{ 547109060Smbr int i; 548109060Smbr 549109060Smbr SIO_CLR(SIS_MII_CLK); 550109060Smbr 551109060Smbr for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 552109060Smbr if (bits & i) { 553109060Smbr SIO_SET(SIS_MII_DATA); 554109060Smbr } else { 555109060Smbr SIO_CLR(SIS_MII_DATA); 556109060Smbr } 557109060Smbr DELAY(1); 558109060Smbr SIO_CLR(SIS_MII_CLK); 559109060Smbr DELAY(1); 560109060Smbr SIO_SET(SIS_MII_CLK); 561109060Smbr } 562109060Smbr} 563109060Smbr 564109060Smbr/* 565109060Smbr * Read an PHY register through the MII. 566109060Smbr */ 567109060Smbrstatic int sis_mii_readreg(sc, frame) 568109060Smbr struct sis_softc *sc; 569109060Smbr struct sis_mii_frame *frame; 570109060Smbr 571109060Smbr{ 572109060Smbr int i, ack, s; 573109060Smbr 574109060Smbr s = splimp(); 575109060Smbr 576109060Smbr /* 577109060Smbr * Set up frame for RX. 578109060Smbr */ 579109060Smbr frame->mii_stdelim = SIS_MII_STARTDELIM; 580109060Smbr frame->mii_opcode = SIS_MII_READOP; 581109060Smbr frame->mii_turnaround = 0; 582109060Smbr frame->mii_data = 0; 583109060Smbr 584109060Smbr /* 585109060Smbr * Turn on data xmit. 586109060Smbr */ 587109060Smbr SIO_SET(SIS_MII_DIR); 588109060Smbr 589109060Smbr sis_mii_sync(sc); 590109060Smbr 591109060Smbr /* 592109060Smbr * Send command/address info. 593109060Smbr */ 594109060Smbr sis_mii_send(sc, frame->mii_stdelim, 2); 595109060Smbr sis_mii_send(sc, frame->mii_opcode, 2); 596109060Smbr sis_mii_send(sc, frame->mii_phyaddr, 5); 597109060Smbr sis_mii_send(sc, frame->mii_regaddr, 5); 598109060Smbr 599109060Smbr /* Idle bit */ 600109060Smbr SIO_CLR((SIS_MII_CLK|SIS_MII_DATA)); 601109060Smbr DELAY(1); 602109060Smbr SIO_SET(SIS_MII_CLK); 603109060Smbr DELAY(1); 604109060Smbr 605109060Smbr /* Turn off xmit. */ 606109060Smbr SIO_CLR(SIS_MII_DIR); 607109060Smbr 608109060Smbr /* Check for ack */ 609109060Smbr SIO_CLR(SIS_MII_CLK); 610109060Smbr DELAY(1); 611109060Smbr ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA; 612109060Smbr SIO_SET(SIS_MII_CLK); 613109060Smbr DELAY(1); 614109060Smbr 615109060Smbr /* 616109060Smbr * Now try reading data bits. If the ack failed, we still 617109060Smbr * need to clock through 16 cycles to keep the PHY(s) in sync. 618109060Smbr */ 619109060Smbr if (ack) { 620109060Smbr for(i = 0; i < 16; i++) { 621109060Smbr SIO_CLR(SIS_MII_CLK); 622109060Smbr DELAY(1); 623109060Smbr SIO_SET(SIS_MII_CLK); 624109060Smbr DELAY(1); 625109060Smbr } 626109060Smbr goto fail; 627109060Smbr } 628109060Smbr 629109060Smbr for (i = 0x8000; i; i >>= 1) { 630109060Smbr SIO_CLR(SIS_MII_CLK); 631109060Smbr DELAY(1); 632109060Smbr if (!ack) { 633109060Smbr if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA) 634109060Smbr frame->mii_data |= i; 635109060Smbr DELAY(1); 636109060Smbr } 637109060Smbr SIO_SET(SIS_MII_CLK); 638109060Smbr DELAY(1); 639109060Smbr } 640109060Smbr 641109060Smbrfail: 642109060Smbr 643109060Smbr SIO_CLR(SIS_MII_CLK); 644109060Smbr DELAY(1); 645109060Smbr SIO_SET(SIS_MII_CLK); 646109060Smbr DELAY(1); 647109060Smbr 648109060Smbr splx(s); 649109060Smbr 650109060Smbr if (ack) 651109060Smbr return(1); 652109060Smbr return(0); 653109060Smbr} 654109060Smbr 655109060Smbr/* 656109060Smbr * Write to a PHY register through the MII. 657109060Smbr */ 658109060Smbrstatic int sis_mii_writereg(sc, frame) 659109060Smbr struct sis_softc *sc; 660109060Smbr struct sis_mii_frame *frame; 661109060Smbr 662109060Smbr{ 663109060Smbr int s; 664109060Smbr 665109060Smbr s = splimp(); 666109060Smbr /* 667109060Smbr * Set up frame for TX. 668109060Smbr */ 669109060Smbr 670109060Smbr frame->mii_stdelim = SIS_MII_STARTDELIM; 671109060Smbr frame->mii_opcode = SIS_MII_WRITEOP; 672109060Smbr frame->mii_turnaround = SIS_MII_TURNAROUND; 673109060Smbr 674109060Smbr /* 675109060Smbr * Turn on data output. 676109060Smbr */ 677109060Smbr SIO_SET(SIS_MII_DIR); 678109060Smbr 679109060Smbr sis_mii_sync(sc); 680109060Smbr 681109060Smbr sis_mii_send(sc, frame->mii_stdelim, 2); 682109060Smbr sis_mii_send(sc, frame->mii_opcode, 2); 683109060Smbr sis_mii_send(sc, frame->mii_phyaddr, 5); 684109060Smbr sis_mii_send(sc, frame->mii_regaddr, 5); 685109060Smbr sis_mii_send(sc, frame->mii_turnaround, 2); 686109060Smbr sis_mii_send(sc, frame->mii_data, 16); 687109060Smbr 688109060Smbr /* Idle bit. */ 689109060Smbr SIO_SET(SIS_MII_CLK); 690109060Smbr DELAY(1); 691109060Smbr SIO_CLR(SIS_MII_CLK); 692109060Smbr DELAY(1); 693109060Smbr 694109060Smbr /* 695109060Smbr * Turn off xmit. 696109060Smbr */ 697109060Smbr SIO_CLR(SIS_MII_DIR); 698109060Smbr 699109060Smbr splx(s); 700109060Smbr 701109060Smbr return(0); 702109060Smbr} 703109060Smbr 704102334Salfredstatic int 705102334Salfredsis_miibus_readreg(dev, phy, reg) 70650974Swpaul device_t dev; 70750974Swpaul int phy, reg; 70850974Swpaul{ 70950974Swpaul struct sis_softc *sc; 710109060Smbr struct sis_mii_frame frame; 71150974Swpaul 71250974Swpaul sc = device_get_softc(dev); 71350974Swpaul 71462672Swpaul if (sc->sis_type == SIS_TYPE_83815) { 71562672Swpaul if (phy != 0) 71662672Swpaul return(0); 71762672Swpaul /* 71862672Swpaul * The NatSemi chip can take a while after 71962672Swpaul * a reset to come ready, during which the BMSR 72062672Swpaul * returns a value of 0. This is *never* supposed 72162672Swpaul * to happen: some of the BMSR bits are meant to 72262672Swpaul * be hardwired in the on position, and this can 72362672Swpaul * confuse the miibus code a bit during the probe 72462672Swpaul * and attach phase. So we make an effort to check 72562672Swpaul * for this condition and wait for it to clear. 72662672Swpaul */ 72762672Swpaul if (!CSR_READ_4(sc, NS_BMSR)) 72862672Swpaul DELAY(1000); 729109060Smbr return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 73062672Swpaul } 73162672Swpaul 732109976Smbr /* 733109976Smbr * Chipsets < SIS_635 seem not to be able to read/write 734109976Smbr * through mdio. Use the enhanced PHY access register 735109976Smbr * again for them. 736109976Smbr */ 73789296Swpaul if (sc->sis_type == SIS_TYPE_900 && 738109976Smbr sc->sis_rev < SIS_REV_635) { 739109976Smbr int i, val = 0; 74050974Swpaul 741109976Smbr if (phy != 0) 742109976Smbr return(0); 74350974Swpaul 744109976Smbr CSR_WRITE_4(sc, SIS_PHYCTL, 745109976Smbr (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 746109976Smbr SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 74750974Swpaul 748109976Smbr for (i = 0; i < SIS_TIMEOUT; i++) { 749109976Smbr if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 750109976Smbr break; 751109976Smbr } 752109976Smbr 753109976Smbr if (i == SIS_TIMEOUT) { 754109976Smbr printf("sis%d: PHY failed to come ready\n", 755109976Smbr sc->sis_unit); 756109976Smbr return(0); 757109976Smbr } 758109976Smbr 759109976Smbr val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 760109976Smbr 761109976Smbr if (val == 0xFFFF) 762109976Smbr return(0); 763109976Smbr 764109976Smbr return(val); 765109976Smbr } else { 766109976Smbr bzero((char *)&frame, sizeof(frame)); 767109976Smbr 768109976Smbr frame.mii_phyaddr = phy; 769109976Smbr frame.mii_regaddr = reg; 770109976Smbr sis_mii_readreg(sc, &frame); 771109976Smbr 772109976Smbr return(frame.mii_data); 773109976Smbr } 77450974Swpaul} 77550974Swpaul 776102334Salfredstatic int 777102334Salfredsis_miibus_writereg(dev, phy, reg, data) 77850974Swpaul device_t dev; 77950974Swpaul int phy, reg, data; 78050974Swpaul{ 78150974Swpaul struct sis_softc *sc; 782109060Smbr struct sis_mii_frame frame; 78350974Swpaul 78450974Swpaul sc = device_get_softc(dev); 78550974Swpaul 78662672Swpaul if (sc->sis_type == SIS_TYPE_83815) { 78762672Swpaul if (phy != 0) 78862672Swpaul return(0); 78962672Swpaul CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 79062672Swpaul return(0); 79162672Swpaul } 79262672Swpaul 793109976Smbr /* 794109976Smbr * Chipsets < SIS_635 seem not to be able to read/write 795109976Smbr * through mdio. Use the enhanced PHY access register 796109976Smbr * again for them. 797109976Smbr */ 798109976Smbr if (sc->sis_type == SIS_TYPE_900 && 799109976Smbr sc->sis_rev < SIS_REV_635) { 800109976Smbr int i; 80150974Swpaul 802109976Smbr if (phy != 0) 803109976Smbr return(0); 80450974Swpaul 805109976Smbr CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 806109976Smbr (reg << 6) | SIS_PHYOP_WRITE); 807109976Smbr SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 80850974Swpaul 809109976Smbr for (i = 0; i < SIS_TIMEOUT; i++) { 810109976Smbr if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 811109976Smbr break; 812109976Smbr } 81350974Swpaul 814109976Smbr if (i == SIS_TIMEOUT) 815109976Smbr printf("sis%d: PHY failed to come ready\n", 816109976Smbr sc->sis_unit); 817109976Smbr } else { 818109976Smbr bzero((char *)&frame, sizeof(frame)); 819109976Smbr 820109976Smbr frame.mii_phyaddr = phy; 821109976Smbr frame.mii_regaddr = reg; 822109976Smbr frame.mii_data = data; 823109976Smbr sis_mii_writereg(sc, &frame); 824109976Smbr } 82550974Swpaul return(0); 82650974Swpaul} 82750974Swpaul 828102334Salfredstatic void 829102334Salfredsis_miibus_statchg(dev) 83050974Swpaul device_t dev; 83150974Swpaul{ 83250974Swpaul struct sis_softc *sc; 83350974Swpaul 83450974Swpaul sc = device_get_softc(dev); 83564963Swpaul sis_init(sc); 83650974Swpaul 83750974Swpaul return; 83850974Swpaul} 83950974Swpaul 840102334Salfredstatic u_int32_t 841122625Sobriensis_mchash(sc, addr) 84262672Swpaul struct sis_softc *sc; 843123289Sobrien const uint8_t *addr; 84450974Swpaul{ 845130270Snaddy uint32_t crc; 84650974Swpaul 84750974Swpaul /* Compute CRC for the address value. */ 848130270Snaddy crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 84950974Swpaul 85062672Swpaul /* 85162672Swpaul * return the filter bit position 85262672Swpaul * 85362672Swpaul * The NatSemi chip has a 512-bit filter, which is 85462672Swpaul * different than the SiS, so we special-case it. 85562672Swpaul */ 85662672Swpaul if (sc->sis_type == SIS_TYPE_83815) 857109060Smbr return (crc >> 23); 858109976Smbr else if (sc->sis_rev >= SIS_REV_635 || 859109976Smbr sc->sis_rev == SIS_REV_900B) 860109060Smbr return (crc >> 24); 861109976Smbr else 862109976Smbr return (crc >> 25); 86350974Swpaul} 86450974Swpaul 865102334Salfredstatic void 866102334Salfredsis_setmulti_ns(sc) 86750974Swpaul struct sis_softc *sc; 86850974Swpaul{ 86950974Swpaul struct ifnet *ifp; 87050974Swpaul struct ifmultiaddr *ifma; 87150974Swpaul u_int32_t h = 0, i, filtsave; 87262672Swpaul int bit, index; 87350974Swpaul 87450974Swpaul ifp = &sc->arpcom.ac_if; 87550974Swpaul 87650974Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 87762672Swpaul SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 87850974Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 87950974Swpaul return; 88050974Swpaul } 88150974Swpaul 88262672Swpaul /* 88362672Swpaul * We have to explicitly enable the multicast hash table 88462672Swpaul * on the NatSemi chip if we want to use it, which we do. 88562672Swpaul */ 88662672Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 88750974Swpaul SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 88850974Swpaul 88950974Swpaul filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 89050974Swpaul 89150974Swpaul /* first, zot all the existing hash bits */ 89262672Swpaul for (i = 0; i < 32; i++) { 89362672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 89462672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 89562672Swpaul } 89662672Swpaul 89772084Sphk TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 89862672Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 89962672Swpaul continue; 900122625Sobrien h = sis_mchash(sc, 901122625Sobrien LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 90262672Swpaul index = h >> 3; 90362672Swpaul bit = h & 0x1F; 90462672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 90562672Swpaul if (bit > 0xF) 90662672Swpaul bit -= 0x10; 90762672Swpaul SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 90862672Swpaul } 90962672Swpaul 91062672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 91162672Swpaul 91262672Swpaul return; 91362672Swpaul} 91462672Swpaul 915102334Salfredstatic void 916102334Salfredsis_setmulti_sis(sc) 91762672Swpaul struct sis_softc *sc; 91862672Swpaul{ 91962672Swpaul struct ifnet *ifp; 92062672Swpaul struct ifmultiaddr *ifma; 921109060Smbr u_int32_t h, i, n, ctl; 922109060Smbr u_int16_t hashes[16]; 92362672Swpaul 92462672Swpaul ifp = &sc->arpcom.ac_if; 92562672Swpaul 926109060Smbr /* hash table size */ 927109976Smbr if (sc->sis_rev >= SIS_REV_635 || 928109976Smbr sc->sis_rev == SIS_REV_900B) 929109976Smbr n = 16; 930109976Smbr else 931109976Smbr n = 8; 93262672Swpaul 933109060Smbr ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE; 93462672Swpaul 935109060Smbr if (ifp->if_flags & IFF_BROADCAST) 936109060Smbr ctl |= SIS_RXFILTCTL_BROAD; 93762672Swpaul 938109060Smbr if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 939109060Smbr ctl |= SIS_RXFILTCTL_ALLMULTI; 940109060Smbr if (ifp->if_flags & IFF_PROMISC) 941109060Smbr ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS; 942109060Smbr for (i = 0; i < n; i++) 943109060Smbr hashes[i] = ~0; 944109060Smbr } else { 945109060Smbr for (i = 0; i < n; i++) 946109060Smbr hashes[i] = 0; 947109060Smbr i = 0; 948109060Smbr TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 949109060Smbr if (ifma->ifma_addr->sa_family != AF_LINK) 950109060Smbr continue; 951122625Sobrien h = sis_mchash(sc, 952109060Smbr LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 953109060Smbr hashes[h >> 4] |= 1 << (h & 0xf); 954109060Smbr i++; 955109060Smbr } 956109060Smbr if (i > n) { 957109060Smbr ctl |= SIS_RXFILTCTL_ALLMULTI; 958109060Smbr for (i = 0; i < n; i++) 959109060Smbr hashes[i] = ~0; 960109060Smbr } 96150974Swpaul } 96250974Swpaul 963109060Smbr for (i = 0; i < n; i++) { 964109060Smbr CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); 965109060Smbr CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); 96650974Swpaul } 96750974Swpaul 968109060Smbr CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl); 96950974Swpaul} 97050974Swpaul 971102334Salfredstatic void 972102334Salfredsis_reset(sc) 97350974Swpaul struct sis_softc *sc; 97450974Swpaul{ 975139708Sphk int i; 97650974Swpaul 97750974Swpaul SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 97850974Swpaul 97950974Swpaul for (i = 0; i < SIS_TIMEOUT; i++) { 98050974Swpaul if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 98150974Swpaul break; 98250974Swpaul } 98350974Swpaul 98450974Swpaul if (i == SIS_TIMEOUT) 98550974Swpaul printf("sis%d: reset never completed\n", sc->sis_unit); 98650974Swpaul 98750974Swpaul /* Wait a little while for the chip to get its brains in order. */ 98850974Swpaul DELAY(1000); 98972813Swpaul 99072813Swpaul /* 99172813Swpaul * If this is a NetSemi chip, make sure to clear 99272813Swpaul * PME mode. 99372813Swpaul */ 99472813Swpaul if (sc->sis_type == SIS_TYPE_83815) { 99572813Swpaul CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 99672813Swpaul CSR_WRITE_4(sc, NS_CLKRUN, 0); 99772813Swpaul } 99872813Swpaul 99950974Swpaul return; 100050974Swpaul} 100150974Swpaul 100250974Swpaul/* 100350974Swpaul * Probe for an SiS chip. Check the PCI vendor and device 100450974Swpaul * IDs against our list and return a device name if we find a match. 100550974Swpaul */ 1006102334Salfredstatic int 1007102334Salfredsis_probe(dev) 100850974Swpaul device_t dev; 100950974Swpaul{ 101050974Swpaul struct sis_type *t; 101150974Swpaul 101250974Swpaul t = sis_devs; 101350974Swpaul 101450974Swpaul while(t->sis_name != NULL) { 101550974Swpaul if ((pci_get_vendor(dev) == t->sis_vid) && 101650974Swpaul (pci_get_device(dev) == t->sis_did)) { 101750974Swpaul device_set_desc(dev, t->sis_name); 101850974Swpaul return(0); 101950974Swpaul } 102050974Swpaul t++; 102150974Swpaul } 102250974Swpaul 102350974Swpaul return(ENXIO); 102450974Swpaul} 102550974Swpaul 102650974Swpaul/* 102750974Swpaul * Attach the interface. Allocate softc structures, do ifmedia 102850974Swpaul * setup and ethernet/BPF attach. 102950974Swpaul */ 1030102334Salfredstatic int 1031102334Salfredsis_attach(dev) 103250974Swpaul device_t dev; 103350974Swpaul{ 103450974Swpaul u_char eaddr[ETHER_ADDR_LEN]; 103550974Swpaul struct sis_softc *sc; 103650974Swpaul struct ifnet *ifp; 1037109061Smbr int unit, error = 0, rid, waittime = 0; 103850974Swpaul 1039109061Smbr waittime = 0; 104050974Swpaul sc = device_get_softc(dev); 104150974Swpaul unit = device_get_unit(dev); 104250974Swpaul 1043119712Sphk sc->sis_self = dev; 1044119712Sphk 104593818Sjhb mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 104693818Sjhb MTX_DEF | MTX_RECURSE); 104769583Swpaul 104850974Swpaul if (pci_get_device(dev) == SIS_DEVICEID_900) 104950974Swpaul sc->sis_type = SIS_TYPE_900; 105050974Swpaul if (pci_get_device(dev) == SIS_DEVICEID_7016) 105150974Swpaul sc->sis_type = SIS_TYPE_7016; 105262672Swpaul if (pci_get_vendor(dev) == NS_VENDORID) 105362672Swpaul sc->sis_type = SIS_TYPE_83815; 105450974Swpaul 105589296Swpaul sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 105650974Swpaul /* 105750974Swpaul * Map control/status registers. 105850974Swpaul */ 105972813Swpaul pci_enable_busmaster(dev); 106050974Swpaul 106150974Swpaul rid = SIS_RID; 1062127135Snjl sc->sis_res = bus_alloc_resource_any(dev, SIS_RES, &rid, RF_ACTIVE); 106350974Swpaul 106450974Swpaul if (sc->sis_res == NULL) { 106550974Swpaul printf("sis%d: couldn't map ports/memory\n", unit); 106650974Swpaul error = ENXIO; 106750974Swpaul goto fail; 106850974Swpaul } 106950974Swpaul 107050974Swpaul sc->sis_btag = rman_get_bustag(sc->sis_res); 107150974Swpaul sc->sis_bhandle = rman_get_bushandle(sc->sis_res); 107250974Swpaul 107350974Swpaul /* Allocate interrupt */ 107450974Swpaul rid = 0; 1075127135Snjl sc->sis_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 107650974Swpaul RF_SHAREABLE | RF_ACTIVE); 107750974Swpaul 107850974Swpaul if (sc->sis_irq == NULL) { 107950974Swpaul printf("sis%d: couldn't map interrupt\n", unit); 108050974Swpaul error = ENXIO; 108150974Swpaul goto fail; 108250974Swpaul } 108350974Swpaul 108450974Swpaul /* Reset the adapter. */ 108550974Swpaul sis_reset(sc); 108650974Swpaul 1087109976Smbr if (sc->sis_type == SIS_TYPE_900 && 1088109976Smbr (sc->sis_rev == SIS_REV_635 || 1089109976Smbr sc->sis_rev == SIS_REV_900B)) { 1090109976Smbr SIO_SET(SIS_CFG_RND_CNT); 1091109976Smbr SIO_SET(SIS_CFG_PERR_DETECT); 1092109976Smbr } 1093109976Smbr 109450974Swpaul /* 109550974Swpaul * Get station address from the EEPROM. 109650974Swpaul */ 109762672Swpaul switch (pci_get_vendor(dev)) { 109862672Swpaul case NS_VENDORID: 1099119712Sphk sc->sis_srr = CSR_READ_4(sc, NS_SRR); 1100119712Sphk 1101119712Sphk /* We can't update the device description, so spew */ 1102119712Sphk if (sc->sis_srr == NS_SRR_15C) 1103119712Sphk device_printf(dev, "Silicon Revision: DP83815C\n"); 1104119712Sphk else if (sc->sis_srr == NS_SRR_15D) 1105119712Sphk device_printf(dev, "Silicon Revision: DP83815D\n"); 1106119712Sphk else if (sc->sis_srr == NS_SRR_16A) 1107119712Sphk device_printf(dev, "Silicon Revision: DP83816A\n"); 1108119712Sphk else 1109119712Sphk device_printf(dev, "Silicon Revision %x\n", sc->sis_srr); 1110119712Sphk 111162672Swpaul /* 111262672Swpaul * Reading the MAC address out of the EEPROM on 111362672Swpaul * the NatSemi chip takes a bit more work than 111462672Swpaul * you'd expect. The address spans 4 16-bit words, 111562672Swpaul * with the first word containing only a single bit. 111662672Swpaul * You have to shift everything over one bit to 111762672Swpaul * get it aligned properly. Also, the bits are 111862672Swpaul * stored backwards (the LSB is really the MSB, 111962672Swpaul * and so on) so you have to reverse them in order 112062672Swpaul * to get the MAC address into the form we want. 112162672Swpaul * Why? Who the hell knows. 112262672Swpaul */ 112362672Swpaul { 112462672Swpaul u_int16_t tmp[4]; 112550974Swpaul 112662672Swpaul sis_read_eeprom(sc, (caddr_t)&tmp, 112762672Swpaul NS_EE_NODEADDR, 4, 0); 112862672Swpaul 112962672Swpaul /* Shift everything over one bit. */ 113062672Swpaul tmp[3] = tmp[3] >> 1; 113162681Swpaul tmp[3] |= tmp[2] << 15; 113262672Swpaul tmp[2] = tmp[2] >> 1; 113362681Swpaul tmp[2] |= tmp[1] << 15; 113462672Swpaul tmp[1] = tmp[1] >> 1; 113562681Swpaul tmp[1] |= tmp[0] << 15; 113662672Swpaul 113762672Swpaul /* Now reverse all the bits. */ 113862672Swpaul tmp[3] = sis_reverse(tmp[3]); 113962672Swpaul tmp[2] = sis_reverse(tmp[2]); 114062672Swpaul tmp[1] = sis_reverse(tmp[1]); 114162672Swpaul 114262672Swpaul bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); 114362672Swpaul } 114462672Swpaul break; 114562672Swpaul case SIS_VENDORID: 114662672Swpaul default: 114772197Swpaul#ifdef __i386__ 114872197Swpaul /* 114972197Swpaul * If this is a SiS 630E chipset with an embedded 115072197Swpaul * SiS 900 controller, we have to read the MAC address 115172197Swpaul * from the APC CMOS RAM. Our method for doing this 115272197Swpaul * is very ugly since we have to reach out and grab 115372197Swpaul * ahold of hardware for which we cannot properly 115472197Swpaul * allocate resources. This code is only compiled on 115572197Swpaul * the i386 architecture since the SiS 630E chipset 115672197Swpaul * is for x86 motherboards only. Note that there are 115772197Swpaul * a lot of magic numbers in this hack. These are 115872197Swpaul * taken from SiS's Linux driver. I'd like to replace 115972197Swpaul * them with proper symbolic definitions, but that 116072197Swpaul * requires some datasheets that I don't have access 116172197Swpaul * to at the moment. 116272197Swpaul */ 116389296Swpaul if (sc->sis_rev == SIS_REV_630S || 116489296Swpaul sc->sis_rev == SIS_REV_630E || 116590328Sambrisko sc->sis_rev == SIS_REV_630EA1) 116672197Swpaul sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 116789296Swpaul 116890328Sambrisko else if (sc->sis_rev == SIS_REV_635 || 116990328Sambrisko sc->sis_rev == SIS_REV_630ET) 117089296Swpaul sis_read_mac(sc, dev, (caddr_t)&eaddr); 1171109061Smbr else if (sc->sis_rev == SIS_REV_96x) { 1172109061Smbr /* Allow to read EEPROM from LAN. It is shared 1173109061Smbr * between a 1394 controller and the NIC and each 1174109061Smbr * time we access it, we need to set SIS_EECMD_REQ. 1175109061Smbr */ 1176109061Smbr SIO_SET(SIS_EECMD_REQ); 1177109061Smbr for (waittime = 0; waittime < SIS_TIMEOUT; 1178109061Smbr waittime++) { 1179109061Smbr /* Force EEPROM to idle state. */ 1180109061Smbr sis_eeprom_idle(sc); 1181109061Smbr if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { 1182109061Smbr sis_read_eeprom(sc, (caddr_t)&eaddr, 1183109061Smbr SIS_EE_NODEADDR, 3, 0); 1184109061Smbr break; 1185109061Smbr } 1186109061Smbr DELAY(1); 1187109061Smbr } 1188109061Smbr /* 1189109061Smbr * Set SIS_EECTL_CLK to high, so a other master 1190109061Smbr * can operate on the i2c bus. 1191109061Smbr */ 1192109061Smbr SIO_SET(SIS_EECTL_CLK); 1193109061Smbr /* Refuse EEPROM access by LAN */ 1194109061Smbr SIO_SET(SIS_EECMD_DONE); 1195109061Smbr } else 119672197Swpaul#endif 119772197Swpaul sis_read_eeprom(sc, (caddr_t)&eaddr, 119872197Swpaul SIS_EE_NODEADDR, 3, 0); 119962672Swpaul break; 120062672Swpaul } 120162672Swpaul 120250974Swpaul sc->sis_unit = unit; 1203129636Srwatson if (debug_mpsafenet) 1204129636Srwatson callout_init(&sc->sis_stat_ch, CALLOUT_MPSAFE); 1205129636Srwatson else 1206129636Srwatson callout_init(&sc->sis_stat_ch, 0); 120750974Swpaul bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 120850974Swpaul 120981713Swpaul /* 121081713Swpaul * Allocate the parent bus DMA tag appropriate for PCI. 121181713Swpaul */ 121281713Swpaul#define SIS_NSEG_NEW 32 121381713Swpaul error = bus_dma_tag_create(NULL, /* parent */ 121481713Swpaul 1, 0, /* alignment, boundary */ 121581713Swpaul BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 121681713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 121781713Swpaul NULL, NULL, /* filter, filterarg */ 121881713Swpaul MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */ 121981713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 122081713Swpaul BUS_DMA_ALLOCNOW, /* flags */ 1221117126Sscottl NULL, NULL, /* lockfunc, lockarg */ 122281713Swpaul &sc->sis_parent_tag); 1223112872Snjl if (error) 1224112872Snjl goto fail; 122550974Swpaul 122681713Swpaul /* 1227112872Snjl * Now allocate a tag for the DMA descriptor lists and a chunk 1228112872Snjl * of DMA-able memory based on the tag. Also obtain the physical 1229112872Snjl * addresses of the RX and TX ring, which we'll need later. 123081713Swpaul * All of our lists are allocated as a contiguous block 123181713Swpaul * of memory. 123281713Swpaul */ 123381713Swpaul error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 123481713Swpaul 1, 0, /* alignment, boundary */ 123581713Swpaul BUS_SPACE_MAXADDR, /* lowaddr */ 123681713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 123781713Swpaul NULL, NULL, /* filter, filterarg */ 123881713Swpaul SIS_RX_LIST_SZ, 1, /* maxsize,nsegments */ 123981713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 124081713Swpaul 0, /* flags */ 1241117126Sscottl busdma_lock_mutex, /* lockfunc */ 1242117126Sscottl &Giant, /* lockarg */ 1243139690Sphk &sc->sis_rx_tag); 1244112872Snjl if (error) 1245112872Snjl goto fail; 124681713Swpaul 1247139690Sphk error = bus_dmamem_alloc(sc->sis_rx_tag, 1248139690Sphk (void **)&sc->sis_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1249139690Sphk &sc->sis_rx_dmamap); 1250112872Snjl 1251112872Snjl if (error) { 1252112872Snjl printf("sis%d: no memory for rx list buffers!\n", unit); 1253139690Sphk bus_dma_tag_destroy(sc->sis_rx_tag); 1254139690Sphk sc->sis_rx_tag = NULL; 1255112872Snjl goto fail; 1256112872Snjl } 1257112872Snjl 1258139690Sphk error = bus_dmamap_load(sc->sis_rx_tag, 1259139690Sphk sc->sis_rx_dmamap, &(sc->sis_rx_list[0]), 1260112872Snjl sizeof(struct sis_desc), sis_dma_map_ring, 1261139690Sphk &sc->sis_rx_paddr, 0); 1262112872Snjl 1263112872Snjl if (error) { 1264112872Snjl printf("sis%d: cannot get address of the rx ring!\n", unit); 1265139690Sphk bus_dmamem_free(sc->sis_rx_tag, 1266139690Sphk sc->sis_rx_list, sc->sis_rx_dmamap); 1267139690Sphk bus_dma_tag_destroy(sc->sis_rx_tag); 1268139690Sphk sc->sis_rx_tag = NULL; 1269112872Snjl goto fail; 1270112872Snjl } 1271112872Snjl 127281713Swpaul error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 127381713Swpaul 1, 0, /* alignment, boundary */ 127481713Swpaul BUS_SPACE_MAXADDR, /* lowaddr */ 127581713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 127681713Swpaul NULL, NULL, /* filter, filterarg */ 127781713Swpaul SIS_TX_LIST_SZ, 1, /* maxsize,nsegments */ 127881713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 127981713Swpaul 0, /* flags */ 1280117126Sscottl busdma_lock_mutex, /* lockfunc */ 1281117126Sscottl &Giant, /* lockarg */ 1282139690Sphk &sc->sis_tx_tag); 1283112872Snjl if (error) 1284112872Snjl goto fail; 128581713Swpaul 1286139690Sphk error = bus_dmamem_alloc(sc->sis_tx_tag, 1287139690Sphk (void **)&sc->sis_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1288139690Sphk &sc->sis_tx_dmamap); 128981713Swpaul 129081713Swpaul if (error) { 1291112872Snjl printf("sis%d: no memory for tx list buffers!\n", unit); 1292139690Sphk bus_dma_tag_destroy(sc->sis_tx_tag); 1293139690Sphk sc->sis_tx_tag = NULL; 129450974Swpaul goto fail; 129550974Swpaul } 129650974Swpaul 1297139690Sphk error = bus_dmamap_load(sc->sis_tx_tag, 1298139690Sphk sc->sis_tx_dmamap, &(sc->sis_tx_list[0]), 1299112872Snjl sizeof(struct sis_desc), sis_dma_map_ring, 1300139690Sphk &sc->sis_tx_paddr, 0); 130181713Swpaul 130281713Swpaul if (error) { 1303112872Snjl printf("sis%d: cannot get address of the tx ring!\n", unit); 1304139690Sphk bus_dmamem_free(sc->sis_tx_tag, 1305139690Sphk sc->sis_tx_list, sc->sis_tx_dmamap); 1306139690Sphk bus_dma_tag_destroy(sc->sis_tx_tag); 1307139690Sphk sc->sis_tx_tag = NULL; 130881713Swpaul goto fail; 130981713Swpaul } 131081713Swpaul 1311112872Snjl error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1312112872Snjl 1, 0, /* alignment, boundary */ 1313112872Snjl BUS_SPACE_MAXADDR, /* lowaddr */ 1314112872Snjl BUS_SPACE_MAXADDR, /* highaddr */ 1315112872Snjl NULL, NULL, /* filter, filterarg */ 1316112872Snjl MCLBYTES, 1, /* maxsize,nsegments */ 1317112872Snjl BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1318112872Snjl 0, /* flags */ 1319117126Sscottl busdma_lock_mutex, /* lockfunc */ 1320117126Sscottl &Giant, /* lockarg */ 1321112872Snjl &sc->sis_tag); 1322112872Snjl if (error) 1323112872Snjl goto fail; 132481713Swpaul 132581713Swpaul /* 132681713Swpaul * Obtain the physical addresses of the RX and TX 132781713Swpaul * rings which we'll need later in the init routine. 132881713Swpaul */ 132981713Swpaul 133050974Swpaul ifp = &sc->arpcom.ac_if; 133150974Swpaul ifp->if_softc = sc; 1332121816Sbrooks if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 133350974Swpaul ifp->if_mtu = ETHERMTU; 133450974Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 133550974Swpaul ifp->if_ioctl = sis_ioctl; 133650974Swpaul ifp->if_start = sis_start; 133750974Swpaul ifp->if_watchdog = sis_watchdog; 133850974Swpaul ifp->if_init = sis_init; 133950974Swpaul ifp->if_baudrate = 10000000; 1340131455Smlaier IFQ_SET_MAXLEN(&ifp->if_snd, SIS_TX_LIST_CNT - 1); 1341131455Smlaier ifp->if_snd.ifq_drv_maxlen = SIS_TX_LIST_CNT - 1; 1342131455Smlaier IFQ_SET_READY(&ifp->if_snd); 134350974Swpaul 134450974Swpaul /* 134550974Swpaul * Do MII setup. 134650974Swpaul */ 134750974Swpaul if (mii_phy_probe(dev, &sc->sis_miibus, 134850974Swpaul sis_ifmedia_upd, sis_ifmedia_sts)) { 134950974Swpaul printf("sis%d: MII without any PHY!\n", sc->sis_unit); 135050974Swpaul error = ENXIO; 135150974Swpaul goto fail; 135250974Swpaul } 135350974Swpaul 135450974Swpaul /* 135563090Sarchie * Call MI attach routine. 135650974Swpaul */ 1357106936Ssam ether_ifattach(ifp, eaddr); 135887390Sjhay 135987390Sjhay /* 136087390Sjhay * Tell the upper layer(s) we support long frames. 136187390Sjhay */ 136287390Sjhay ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1363106936Ssam ifp->if_capabilities |= IFCAP_VLAN_MTU; 136487390Sjhay 1365128138Sru#ifdef DEVICE_POLLING 1366128138Sru ifp->if_capabilities |= IFCAP_POLLING; 1367128138Sru#endif 1368128138Sru ifp->if_capenable = ifp->if_capabilities; 1369128138Sru 1370113609Snjl /* Hook interrupt last to avoid having to lock softc */ 1371121697Ssam error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET | INTR_MPSAFE, 1372112872Snjl sis_intr, sc, &sc->sis_intrhand); 137350974Swpaul 1374112872Snjl if (error) { 1375112872Snjl printf("sis%d: couldn't set up irq\n", unit); 1376113609Snjl ether_ifdetach(ifp); 1377112872Snjl goto fail; 1378112872Snjl } 1379112872Snjl 138050974Swpaulfail: 1381112872Snjl if (error) 1382112872Snjl sis_detach(dev); 1383112872Snjl 138450974Swpaul return(error); 138550974Swpaul} 138650974Swpaul 1387113609Snjl/* 1388113609Snjl * Shutdown hardware and free up resources. This can be called any 1389113609Snjl * time after the mutex has been initialized. It is called in both 1390113609Snjl * the error case in attach and the normal detach case so it needs 1391113609Snjl * to be careful about only freeing resources that have actually been 1392113609Snjl * allocated. 1393113609Snjl */ 1394102334Salfredstatic int 1395102334Salfredsis_detach(dev) 139650974Swpaul device_t dev; 139750974Swpaul{ 139850974Swpaul struct sis_softc *sc; 139950974Swpaul struct ifnet *ifp; 140050974Swpaul 140150974Swpaul sc = device_get_softc(dev); 1402112880Sjhb KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized")); 140367087Swpaul SIS_LOCK(sc); 140450974Swpaul ifp = &sc->arpcom.ac_if; 140550974Swpaul 1406118089Smux /* These should only be active if attach succeeded. */ 1407113812Simp if (device_is_attached(dev)) { 1408113609Snjl sis_reset(sc); 1409113609Snjl sis_stop(sc); 1410112872Snjl ether_ifdetach(ifp); 1411113609Snjl } 1412113609Snjl if (sc->sis_miibus) 1413112872Snjl device_delete_child(dev, sc->sis_miibus); 1414113609Snjl bus_generic_detach(dev); 141550974Swpaul 1416112872Snjl if (sc->sis_intrhand) 1417112872Snjl bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1418112872Snjl if (sc->sis_irq) 1419112872Snjl bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1420112872Snjl if (sc->sis_res) 1421112872Snjl bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 142250974Swpaul 1423139690Sphk if (sc->sis_rx_tag) { 1424139690Sphk bus_dmamap_unload(sc->sis_rx_tag, 1425139690Sphk sc->sis_rx_dmamap); 1426139690Sphk bus_dmamem_free(sc->sis_rx_tag, 1427139690Sphk sc->sis_rx_list, sc->sis_rx_dmamap); 1428139690Sphk bus_dma_tag_destroy(sc->sis_rx_tag); 1429112872Snjl } 1430139690Sphk if (sc->sis_tx_tag) { 1431139690Sphk bus_dmamap_unload(sc->sis_tx_tag, 1432139690Sphk sc->sis_tx_dmamap); 1433139690Sphk bus_dmamem_free(sc->sis_tx_tag, 1434139690Sphk sc->sis_tx_list, sc->sis_tx_dmamap); 1435139690Sphk bus_dma_tag_destroy(sc->sis_tx_tag); 1436112872Snjl } 1437112872Snjl if (sc->sis_parent_tag) 1438112872Snjl bus_dma_tag_destroy(sc->sis_parent_tag); 1439112872Snjl if (sc->sis_tag) 1440112872Snjl bus_dma_tag_destroy(sc->sis_tag); 144150974Swpaul 144267087Swpaul SIS_UNLOCK(sc); 144367087Swpaul mtx_destroy(&sc->sis_mtx); 144450974Swpaul 144550974Swpaul return(0); 144650974Swpaul} 144750974Swpaul 144850974Swpaul/* 144950974Swpaul * Initialize the transmit descriptors. 145050974Swpaul */ 1451102334Salfredstatic int 1452102334Salfredsis_list_tx_init(sc) 145350974Swpaul struct sis_softc *sc; 145450974Swpaul{ 145587059Sluigi int i, nexti; 145650974Swpaul 145750974Swpaul for (i = 0; i < SIS_TX_LIST_CNT; i++) { 145887102Sluigi nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1; 1459139690Sphk sc->sis_tx_list[i].sis_nextdesc = 1460139690Sphk &sc->sis_tx_list[nexti]; 1461139690Sphk bus_dmamap_load(sc->sis_tx_tag, 1462139690Sphk sc->sis_tx_dmamap, 1463139690Sphk &sc->sis_tx_list[nexti], sizeof(struct sis_desc), 1464139690Sphk sis_dma_map_desc_next, &sc->sis_tx_list[i], 0); 1465139690Sphk sc->sis_tx_list[i].sis_mbuf = NULL; 1466139690Sphk sc->sis_tx_list[i].sis_ptr = 0; 1467139690Sphk sc->sis_tx_list[i].sis_ctl = 0; 146850974Swpaul } 146950974Swpaul 1470139690Sphk sc->sis_tx_prod = sc->sis_tx_cons = sc->sis_tx_cnt = 0; 147150974Swpaul 1472139690Sphk bus_dmamap_sync(sc->sis_tx_tag, 1473139690Sphk sc->sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 147481713Swpaul 147550974Swpaul return(0); 147650974Swpaul} 147750974Swpaul 147850974Swpaul/* 147950974Swpaul * Initialize the RX descriptors and allocate mbufs for them. Note that 148050974Swpaul * we arrange the descriptors in a closed ring, so that the last descriptor 148150974Swpaul * points back to the first. 148250974Swpaul */ 1483102334Salfredstatic int 1484102334Salfredsis_list_rx_init(sc) 148550974Swpaul struct sis_softc *sc; 148650974Swpaul{ 148787059Sluigi int i,nexti; 148850974Swpaul 148950974Swpaul for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1490139690Sphk if (sis_newbuf(sc, &sc->sis_rx_list[i], NULL) == ENOBUFS) 149150974Swpaul return(ENOBUFS); 149287102Sluigi nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1; 1493139690Sphk sc->sis_rx_list[i].sis_nextdesc = 1494139690Sphk &sc->sis_rx_list[nexti]; 1495139690Sphk bus_dmamap_load(sc->sis_rx_tag, 1496139690Sphk sc->sis_rx_dmamap, 1497139690Sphk &sc->sis_rx_list[nexti], 149881713Swpaul sizeof(struct sis_desc), sis_dma_map_desc_next, 1499139690Sphk &sc->sis_rx_list[i], 0); 150050974Swpaul } 150150974Swpaul 1502139690Sphk bus_dmamap_sync(sc->sis_rx_tag, 1503139690Sphk sc->sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 150481713Swpaul 1505139691Sphk sc->sis_rx_pdsc = &sc->sis_rx_list[0]; 150650974Swpaul 150750974Swpaul return(0); 150850974Swpaul} 150950974Swpaul 151050974Swpaul/* 151150974Swpaul * Initialize an RX descriptor and attach an MBUF cluster. 151250974Swpaul */ 1513102334Salfredstatic int 1514102334Salfredsis_newbuf(sc, c, m) 151550974Swpaul struct sis_softc *sc; 151650974Swpaul struct sis_desc *c; 151750974Swpaul struct mbuf *m; 151850974Swpaul{ 151950974Swpaul 152081713Swpaul if (c == NULL) 152181713Swpaul return(EINVAL); 152281713Swpaul 152350974Swpaul if (m == NULL) { 1524111119Simp m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1525101340Sluigi if (m == NULL) 152650974Swpaul return(ENOBUFS); 1527101340Sluigi } else 1528101340Sluigi m->m_data = m->m_ext.ext_buf; 152950974Swpaul 1530101340Sluigi c->sis_mbuf = m; 153150974Swpaul c->sis_ctl = SIS_RXLEN; 153250974Swpaul 153381713Swpaul bus_dmamap_create(sc->sis_tag, 0, &c->sis_map); 153481713Swpaul bus_dmamap_load(sc->sis_tag, c->sis_map, 1535101464Sluigi mtod(m, void *), MCLBYTES, 153681713Swpaul sis_dma_map_desc_ptr, c, 0); 153781713Swpaul bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREWRITE); 153881713Swpaul 153950974Swpaul return(0); 154050974Swpaul} 154150974Swpaul 154250974Swpaul/* 154350974Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 154450974Swpaul * the higher level protocols. 154550974Swpaul */ 1546102334Salfredstatic void 1547102334Salfredsis_rxeof(sc) 154850974Swpaul struct sis_softc *sc; 154950974Swpaul{ 155050974Swpaul struct mbuf *m; 155150974Swpaul struct ifnet *ifp; 155250974Swpaul struct sis_desc *cur_rx; 1553139691Sphk int total_len = 0; 155450974Swpaul u_int32_t rxstat; 155550974Swpaul 1556122689Ssam SIS_LOCK_ASSERT(sc); 1557122689Ssam 155850974Swpaul ifp = &sc->arpcom.ac_if; 155950974Swpaul 1560139691Sphk for(cur_rx = sc->sis_rx_pdsc; SIS_OWNDESC(cur_rx); 1561139691Sphk cur_rx = cur_rx->sis_nextdesc) { 156250974Swpaul 156387902Sluigi#ifdef DEVICE_POLLING 1564102052Ssobomax if (ifp->if_flags & IFF_POLLING) { 156587902Sluigi if (sc->rxcycles <= 0) 156687902Sluigi break; 156787902Sluigi sc->rxcycles--; 156887902Sluigi } 156987902Sluigi#endif /* DEVICE_POLLING */ 157050974Swpaul rxstat = cur_rx->sis_rxstat; 157181713Swpaul bus_dmamap_sync(sc->sis_tag, 157281713Swpaul cur_rx->sis_map, BUS_DMASYNC_POSTWRITE); 157381713Swpaul bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map); 157481713Swpaul bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map); 157550974Swpaul m = cur_rx->sis_mbuf; 157650974Swpaul cur_rx->sis_mbuf = NULL; 157750974Swpaul total_len = SIS_RXBYTES(cur_rx); 157850974Swpaul 157950974Swpaul /* 158050974Swpaul * If an error occurs, update stats, clear the 158150974Swpaul * status word and leave the mbuf cluster in place: 158250974Swpaul * it should simply get re-used next time this descriptor 158350974Swpaul * comes up in the ring. 158450974Swpaul */ 158550974Swpaul if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 158650974Swpaul ifp->if_ierrors++; 158750974Swpaul if (rxstat & SIS_RXSTAT_COLL) 158850974Swpaul ifp->if_collisions++; 158950974Swpaul sis_newbuf(sc, cur_rx, m); 159050974Swpaul continue; 159150974Swpaul } 159250974Swpaul 159350974Swpaul /* No errors; receive the packet. */ 159487059Sluigi#ifdef __i386__ 159587059Sluigi /* 159687059Sluigi * On the x86 we do not have alignment problems, so try to 159787059Sluigi * allocate a new buffer for the receive ring, and pass up 159887059Sluigi * the one where the packet is already, saving the expensive 159987059Sluigi * copy done in m_devget(). 160087059Sluigi * If we are on an architecture with alignment problems, or 160187059Sluigi * if the allocation fails, then use m_devget and leave the 160287059Sluigi * existing buffer in the receive ring. 160387059Sluigi */ 1604101464Sluigi if (sis_newbuf(sc, cur_rx, NULL) == 0) 160587059Sluigi m->m_pkthdr.len = m->m_len = total_len; 1606101464Sluigi else 160787059Sluigi#endif 160887059Sluigi { 160987059Sluigi struct mbuf *m0; 161087059Sluigi m0 = m_devget(mtod(m, char *), total_len, 161187059Sluigi ETHER_ALIGN, ifp, NULL); 161287059Sluigi sis_newbuf(sc, cur_rx, m); 161387059Sluigi if (m0 == NULL) { 161487059Sluigi ifp->if_ierrors++; 161587059Sluigi continue; 161687059Sluigi } 161787059Sluigi m = m0; 161850974Swpaul } 161950974Swpaul 162050974Swpaul ifp->if_ipackets++; 1621106936Ssam m->m_pkthdr.rcvif = ifp; 1622106936Ssam 1623122689Ssam SIS_UNLOCK(sc); 1624106936Ssam (*ifp->if_input)(ifp, m); 1625122689Ssam SIS_LOCK(sc); 162650974Swpaul } 162750974Swpaul 1628139691Sphk sc->sis_rx_pdsc = cur_rx; 162950974Swpaul 163050974Swpaul return; 163150974Swpaul} 163250974Swpaul 1633105219Sphkstatic void 1634102334Salfredsis_rxeoc(sc) 163550974Swpaul struct sis_softc *sc; 163650974Swpaul{ 163750974Swpaul sis_rxeof(sc); 163850974Swpaul sis_init(sc); 163950974Swpaul return; 164050974Swpaul} 164150974Swpaul 164250974Swpaul/* 164350974Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 164450974Swpaul * the list buffers. 164550974Swpaul */ 164650974Swpaul 1647102334Salfredstatic void 1648102334Salfredsis_txeof(sc) 164950974Swpaul struct sis_softc *sc; 165050974Swpaul{ 165150974Swpaul struct ifnet *ifp; 165250974Swpaul u_int32_t idx; 165350974Swpaul 165450974Swpaul ifp = &sc->arpcom.ac_if; 165550974Swpaul 165650974Swpaul /* 165750974Swpaul * Go through our tx list and free mbufs for those 165850974Swpaul * frames that have been transmitted. 165950974Swpaul */ 1660139690Sphk for (idx = sc->sis_tx_cons; sc->sis_tx_cnt > 0; 1661139690Sphk sc->sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) { 1662139690Sphk struct sis_desc *cur_tx = &sc->sis_tx_list[idx]; 166350974Swpaul 166450974Swpaul if (SIS_OWNDESC(cur_tx)) 166550974Swpaul break; 166650974Swpaul 166799163Sluigi if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) 166850974Swpaul continue; 166950974Swpaul 167050974Swpaul if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 167150974Swpaul ifp->if_oerrors++; 167250974Swpaul if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 167350974Swpaul ifp->if_collisions++; 167450974Swpaul if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 167550974Swpaul ifp->if_collisions++; 167650974Swpaul } 167750974Swpaul 167850974Swpaul ifp->if_collisions += 167950974Swpaul (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 168050974Swpaul 168150974Swpaul ifp->if_opackets++; 168250974Swpaul if (cur_tx->sis_mbuf != NULL) { 168350974Swpaul m_freem(cur_tx->sis_mbuf); 168450974Swpaul cur_tx->sis_mbuf = NULL; 168581713Swpaul bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map); 168681713Swpaul bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map); 168750974Swpaul } 168899163Sluigi } 168950974Swpaul 1690139690Sphk if (idx != sc->sis_tx_cons) { 169199163Sluigi /* we freed up some buffers */ 1692139690Sphk sc->sis_tx_cons = idx; 169399163Sluigi ifp->if_flags &= ~IFF_OACTIVE; 169450974Swpaul } 169550974Swpaul 1696139690Sphk ifp->if_timer = (sc->sis_tx_cnt == 0) ? 0 : 5; 169750974Swpaul 169850974Swpaul return; 169950974Swpaul} 170050974Swpaul 1701102334Salfredstatic void 1702102334Salfredsis_tick(xsc) 170350974Swpaul void *xsc; 170450974Swpaul{ 170550974Swpaul struct sis_softc *sc; 170650974Swpaul struct mii_data *mii; 170764963Swpaul struct ifnet *ifp; 170850974Swpaul 170950974Swpaul sc = xsc; 171067087Swpaul SIS_LOCK(sc); 1711117858Scognet sc->in_tick = 1; 171264963Swpaul ifp = &sc->arpcom.ac_if; 171364963Swpaul 171450974Swpaul mii = device_get_softc(sc->sis_miibus); 171550974Swpaul mii_tick(mii); 171664963Swpaul 171784147Sjlemon if (!sc->sis_link && mii->mii_media_status & IFM_ACTIVE && 171884147Sjlemon IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 171984147Sjlemon sc->sis_link++; 1720131455Smlaier if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 172184147Sjlemon sis_start(ifp); 172264963Swpaul } 172364963Swpaul 1724119785Ssam callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 1725117858Scognet sc->in_tick = 0; 172667087Swpaul SIS_UNLOCK(sc); 172750974Swpaul 172850974Swpaul return; 172950974Swpaul} 173050974Swpaul 173187902Sluigi#ifdef DEVICE_POLLING 173287902Sluigistatic poll_handler_t sis_poll; 173387902Sluigi 173487902Sluigistatic void 173587902Sluigisis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 173687902Sluigi{ 173787973Speter struct sis_softc *sc = ifp->if_softc; 173887973Speter 173987902Sluigi SIS_LOCK(sc); 1740128138Sru if (!(ifp->if_capenable & IFCAP_POLLING)) { 1741128138Sru ether_poll_deregister(ifp); 1742128138Sru cmd = POLL_DEREGISTER; 1743128138Sru } 174487902Sluigi if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 174587902Sluigi CSR_WRITE_4(sc, SIS_IER, 1); 174687902Sluigi goto done; 174787902Sluigi } 174887902Sluigi 174987902Sluigi /* 175087902Sluigi * On the sis, reading the status register also clears it. 175187902Sluigi * So before returning to intr mode we must make sure that all 175287902Sluigi * possible pending sources of interrupts have been served. 175387902Sluigi * In practice this means run to completion the *eof routines, 175487902Sluigi * and then call the interrupt routine 175587902Sluigi */ 175687902Sluigi sc->rxcycles = count; 175787902Sluigi sis_rxeof(sc); 175887902Sluigi sis_txeof(sc); 1759131455Smlaier if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 176087902Sluigi sis_start(ifp); 176187902Sluigi 176287902Sluigi if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 176387902Sluigi u_int32_t status; 176487902Sluigi 176587902Sluigi /* Reading the ISR register clears all interrupts. */ 176687902Sluigi status = CSR_READ_4(sc, SIS_ISR); 176787902Sluigi 176887902Sluigi if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 176987902Sluigi sis_rxeoc(sc); 177087902Sluigi 177187902Sluigi if (status & (SIS_ISR_RX_IDLE)) 177287902Sluigi SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 177387902Sluigi 177487902Sluigi if (status & SIS_ISR_SYSERR) { 177587902Sluigi sis_reset(sc); 177687902Sluigi sis_init(sc); 177787902Sluigi } 177887902Sluigi } 177987902Sluigidone: 178087902Sluigi SIS_UNLOCK(sc); 178187902Sluigi return; 178287902Sluigi} 178387902Sluigi#endif /* DEVICE_POLLING */ 178487902Sluigi 1785102334Salfredstatic void 1786102334Salfredsis_intr(arg) 178750974Swpaul void *arg; 178850974Swpaul{ 178950974Swpaul struct sis_softc *sc; 179050974Swpaul struct ifnet *ifp; 179150974Swpaul u_int32_t status; 179250974Swpaul 179350974Swpaul sc = arg; 179450974Swpaul ifp = &sc->arpcom.ac_if; 179550974Swpaul 179686984Sluigi SIS_LOCK(sc); 179787902Sluigi#ifdef DEVICE_POLLING 1798102052Ssobomax if (ifp->if_flags & IFF_POLLING) 179987902Sluigi goto done; 1800128138Sru if ((ifp->if_capenable & IFCAP_POLLING) && 1801128138Sru ether_poll_register(sis_poll, ifp)) { /* ok, disable interrupts */ 180287902Sluigi CSR_WRITE_4(sc, SIS_IER, 0); 180387902Sluigi goto done; 180487902Sluigi } 180587902Sluigi#endif /* DEVICE_POLLING */ 180687902Sluigi 180750974Swpaul /* Supress unwanted interrupts */ 180850974Swpaul if (!(ifp->if_flags & IFF_UP)) { 180950974Swpaul sis_stop(sc); 181086984Sluigi goto done; 181150974Swpaul } 181250974Swpaul 181350974Swpaul /* Disable interrupts. */ 181450974Swpaul CSR_WRITE_4(sc, SIS_IER, 0); 181550974Swpaul 181650974Swpaul for (;;) { 181750974Swpaul /* Reading the ISR register clears all interrupts. */ 181850974Swpaul status = CSR_READ_4(sc, SIS_ISR); 181950974Swpaul 182050974Swpaul if ((status & SIS_INTRS) == 0) 182150974Swpaul break; 182250974Swpaul 182386984Sluigi if (status & 182486984Sluigi (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | 182586984Sluigi SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) ) 182650974Swpaul sis_txeof(sc); 182750974Swpaul 182886984Sluigi if (status & (SIS_ISR_RX_DESC_OK|SIS_ISR_RX_OK|SIS_ISR_RX_IDLE)) 182950974Swpaul sis_rxeof(sc); 183050974Swpaul 183186984Sluigi if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW)) 183250974Swpaul sis_rxeoc(sc); 183350974Swpaul 183486984Sluigi if (status & (SIS_ISR_RX_IDLE)) 183586984Sluigi SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 183686984Sluigi 183750974Swpaul if (status & SIS_ISR_SYSERR) { 183850974Swpaul sis_reset(sc); 183950974Swpaul sis_init(sc); 184050974Swpaul } 184150974Swpaul } 184250974Swpaul 184350974Swpaul /* Re-enable interrupts. */ 184450974Swpaul CSR_WRITE_4(sc, SIS_IER, 1); 184550974Swpaul 1846131455Smlaier if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 184750974Swpaul sis_start(ifp); 184886984Sluigidone: 184967087Swpaul SIS_UNLOCK(sc); 185067087Swpaul 185150974Swpaul return; 185250974Swpaul} 185350974Swpaul 185450974Swpaul/* 185550974Swpaul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 185650974Swpaul * pointers to the fragment pointers. 185750974Swpaul */ 1858102334Salfredstatic int 1859102334Salfredsis_encap(sc, m_head, txidx) 186050974Swpaul struct sis_softc *sc; 1861121262Ssilby struct mbuf **m_head; 186250974Swpaul u_int32_t *txidx; 186350974Swpaul{ 186450974Swpaul struct sis_desc *f = NULL; 186550974Swpaul struct mbuf *m; 1866112808Ssilby int frag, cur, cnt = 0, chainlen = 0; 186750974Swpaul 186850974Swpaul /* 1869112808Ssilby * If there's no way we can send any packets, return now. 1870112808Ssilby */ 1871139690Sphk if (SIS_TX_LIST_CNT - sc->sis_tx_cnt < 2) 1872112808Ssilby return (ENOBUFS); 1873112808Ssilby 1874112808Ssilby /* 1875112808Ssilby * Count the number of frags in this chain to see if 1876112808Ssilby * we need to m_defrag. Since the descriptor list is shared 1877112808Ssilby * by all packets, we'll m_defrag long chains so that they 1878112808Ssilby * do not use up the entire list, even if they would fit. 1879112808Ssilby */ 1880112808Ssilby 1881121262Ssilby for (m = *m_head; m != NULL; m = m->m_next) 1882112808Ssilby chainlen++; 1883112808Ssilby 1884112808Ssilby if ((chainlen > SIS_TX_LIST_CNT / 4) || 1885139690Sphk ((SIS_TX_LIST_CNT - (chainlen + sc->sis_tx_cnt)) < 2)) { 1886121262Ssilby m = m_defrag(*m_head, M_DONTWAIT); 1887112808Ssilby if (m == NULL) 1888112808Ssilby return (ENOBUFS); 1889121262Ssilby *m_head = m; 1890112808Ssilby } 1891112808Ssilby 1892112808Ssilby /* 189350974Swpaul * Start packing the mbufs in this chain into 189450974Swpaul * the fragment pointers. Stop when we run out 189550974Swpaul * of fragments or hit the end of the mbuf chain. 189650974Swpaul */ 189750974Swpaul cur = frag = *txidx; 189850974Swpaul 1899121262Ssilby for (m = *m_head; m != NULL; m = m->m_next) { 190050974Swpaul if (m->m_len != 0) { 190151042Swpaul if ((SIS_TX_LIST_CNT - 1902139690Sphk (sc->sis_tx_cnt + cnt)) < 2) 190350974Swpaul return(ENOBUFS); 1904139690Sphk f = &sc->sis_tx_list[frag]; 190550974Swpaul f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; 190681713Swpaul bus_dmamap_create(sc->sis_tag, 0, &f->sis_map); 190781713Swpaul bus_dmamap_load(sc->sis_tag, f->sis_map, 190881713Swpaul mtod(m, void *), m->m_len, 190981713Swpaul sis_dma_map_desc_ptr, f, 0); 191081713Swpaul bus_dmamap_sync(sc->sis_tag, 191181713Swpaul f->sis_map, BUS_DMASYNC_PREREAD); 191250974Swpaul if (cnt != 0) 191350974Swpaul f->sis_ctl |= SIS_CMDSTS_OWN; 191450974Swpaul cur = frag; 191550974Swpaul SIS_INC(frag, SIS_TX_LIST_CNT); 191650974Swpaul cnt++; 191750974Swpaul } 191850974Swpaul } 191950974Swpaul 192050974Swpaul if (m != NULL) 192150974Swpaul return(ENOBUFS); 192250974Swpaul 1923139690Sphk sc->sis_tx_list[cur].sis_mbuf = *m_head; 1924139690Sphk sc->sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1925139690Sphk sc->sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1926139690Sphk sc->sis_tx_cnt += cnt; 192750974Swpaul *txidx = frag; 192850974Swpaul 192950974Swpaul return(0); 193050974Swpaul} 193150974Swpaul 193250974Swpaul/* 193350974Swpaul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 193450974Swpaul * to the mbuf data regions directly in the transmit lists. We also save a 193550974Swpaul * copy of the pointers since the transmit list fragment pointers are 193650974Swpaul * physical addresses. 193750974Swpaul */ 193850974Swpaul 1939102334Salfredstatic void 1940102334Salfredsis_start(ifp) 194150974Swpaul struct ifnet *ifp; 194250974Swpaul{ 194350974Swpaul struct sis_softc *sc; 194450974Swpaul struct mbuf *m_head = NULL; 1945136269Smlaier u_int32_t idx, queued = 0; 194650974Swpaul 194750974Swpaul sc = ifp->if_softc; 194867087Swpaul SIS_LOCK(sc); 194950974Swpaul 195067087Swpaul if (!sc->sis_link) { 195167087Swpaul SIS_UNLOCK(sc); 195264963Swpaul return; 195367087Swpaul } 195464963Swpaul 1955139690Sphk idx = sc->sis_tx_prod; 195650974Swpaul 195767087Swpaul if (ifp->if_flags & IFF_OACTIVE) { 195867087Swpaul SIS_UNLOCK(sc); 195950974Swpaul return; 196067087Swpaul } 196150974Swpaul 1962139690Sphk while(sc->sis_tx_list[idx].sis_mbuf == NULL) { 1963131455Smlaier IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 196450974Swpaul if (m_head == NULL) 196550974Swpaul break; 196650974Swpaul 1967121262Ssilby if (sis_encap(sc, &m_head, &idx)) { 1968131455Smlaier IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 196950974Swpaul ifp->if_flags |= IFF_OACTIVE; 197050974Swpaul break; 197150974Swpaul } 197250974Swpaul 1973136269Smlaier queued++; 1974136269Smlaier 197550974Swpaul /* 197650974Swpaul * If there's a BPF listener, bounce a copy of this frame 197750974Swpaul * to him. 197850974Swpaul */ 1979106936Ssam BPF_MTAP(ifp, m_head); 198051583Swpaul 198150974Swpaul } 198250974Swpaul 1983136269Smlaier if (queued) { 1984136269Smlaier /* Transmit */ 1985139690Sphk sc->sis_tx_prod = idx; 1986136269Smlaier SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 198750974Swpaul 1988136269Smlaier /* 1989136269Smlaier * Set a timeout in case the chip goes out to lunch. 1990136269Smlaier */ 1991136269Smlaier ifp->if_timer = 5; 1992136269Smlaier } 199350974Swpaul 199467087Swpaul SIS_UNLOCK(sc); 199567087Swpaul 199650974Swpaul return; 199750974Swpaul} 199850974Swpaul 1999102334Salfredstatic void 2000102334Salfredsis_init(xsc) 200150974Swpaul void *xsc; 200250974Swpaul{ 200350974Swpaul struct sis_softc *sc = xsc; 200450974Swpaul struct ifnet *ifp = &sc->arpcom.ac_if; 200550974Swpaul struct mii_data *mii; 200650974Swpaul 200767087Swpaul SIS_LOCK(sc); 200850974Swpaul 200950974Swpaul /* 201050974Swpaul * Cancel pending I/O and free all RX/TX buffers. 201150974Swpaul */ 201250974Swpaul sis_stop(sc); 2013123833Sphk sc->sis_stopped = 0; 201450974Swpaul 2015119712Sphk#ifdef notyet 2016119712Sphk if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) { 2017119712Sphk /* 2018119712Sphk * Configure 400usec of interrupt holdoff. This is based 2019119712Sphk * on emperical tests on a Soekris 4801. 2020119712Sphk */ 2021119712Sphk CSR_WRITE_4(sc, NS_IHR, 0x100 | 4); 2022119712Sphk } 2023119712Sphk#endif 2024119712Sphk 202550974Swpaul mii = device_get_softc(sc->sis_miibus); 202650974Swpaul 202750974Swpaul /* Set MAC address */ 202862672Swpaul if (sc->sis_type == SIS_TYPE_83815) { 202962672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 203062672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 203162672Swpaul ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 203262672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 203362672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 203462672Swpaul ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 203562672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 203662672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 203762672Swpaul ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 203862672Swpaul } else { 203962672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 204062672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 204162672Swpaul ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 204262672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 204362672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 204462672Swpaul ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 204562672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 204662672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 204762672Swpaul ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 204862672Swpaul } 204950974Swpaul 205050974Swpaul /* Init circular RX list. */ 205150974Swpaul if (sis_list_rx_init(sc) == ENOBUFS) { 205250974Swpaul printf("sis%d: initialization failed: no " 205350974Swpaul "memory for rx buffers\n", sc->sis_unit); 205450974Swpaul sis_stop(sc); 205567087Swpaul SIS_UNLOCK(sc); 205650974Swpaul return; 205750974Swpaul } 205850974Swpaul 205950974Swpaul /* 206050974Swpaul * Init tx descriptors. 206150974Swpaul */ 206250974Swpaul sis_list_tx_init(sc); 206350974Swpaul 206462672Swpaul /* 2065123491Sphk * Page 78 of the DP83815 data sheet (september 2002 version) 2066123491Sphk * recommends the following register settings "for optimum 2067123491Sphk * performance." for rev 15C. The driver from NS also sets 2068123491Sphk * the PHY_CR register for later versions. 2069123491Sphk */ 2070123491Sphk if (sc->sis_type == SIS_TYPE_83815) { 2071123491Sphk CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 2072123491Sphk /* DC speed = 01 */ 2073123491Sphk CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 2074123491Sphk if (sc->sis_srr == NS_SRR_15C) { 2075123491Sphk /* set val for c2 */ 2076123491Sphk CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 2077123491Sphk /* load/kill c2 */ 2078123491Sphk CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 2079123491Sphk /* rais SD off, from 4 to c */ 2080123491Sphk CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 2081123491Sphk } 2082123491Sphk CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 2083123491Sphk } 2084123491Sphk 2085123491Sphk 2086123491Sphk /* 208762672Swpaul * For the NatSemi chip, we have to explicitly enable the 208862672Swpaul * reception of ARP frames, as well as turn on the 'perfect 208962672Swpaul * match' filter where we store the station address, otherwise 209062672Swpaul * we won't receive unicasts meant for this host. 209162672Swpaul */ 209262672Swpaul if (sc->sis_type == SIS_TYPE_83815) { 209362672Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 209462672Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 209562672Swpaul } 209662672Swpaul 209750974Swpaul /* If we want promiscuous mode, set the allframes bit. */ 209850974Swpaul if (ifp->if_flags & IFF_PROMISC) { 209950974Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 210050974Swpaul } else { 210150974Swpaul SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 210250974Swpaul } 210350974Swpaul 210450974Swpaul /* 210550974Swpaul * Set the capture broadcast bit to capture broadcast frames. 210650974Swpaul */ 210750974Swpaul if (ifp->if_flags & IFF_BROADCAST) { 210850974Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 210950974Swpaul } else { 211050974Swpaul SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 211150974Swpaul } 211250974Swpaul 211350974Swpaul /* 211450974Swpaul * Load the multicast filter. 211550974Swpaul */ 211662672Swpaul if (sc->sis_type == SIS_TYPE_83815) 211762672Swpaul sis_setmulti_ns(sc); 211862672Swpaul else 211962672Swpaul sis_setmulti_sis(sc); 212050974Swpaul 212150974Swpaul /* Turn the receive filter on */ 212250974Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 212350974Swpaul 212450974Swpaul /* 212550974Swpaul * Load the address of the RX and TX lists. 212650974Swpaul */ 2127139690Sphk CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_rx_paddr); 2128139690Sphk CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_tx_paddr); 212950974Swpaul 2130109059Smbr /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of 2131109059Smbr * the PCI bus. When this bit is set, the Max DMA Burst Size 2132109059Smbr * for TX/RX DMA should be no larger than 16 double words. 2133109059Smbr */ 2134109059Smbr if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) { 2135109059Smbr CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); 2136109059Smbr } else { 2137109059Smbr CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); 2138109059Smbr } 213964963Swpaul 214087390Sjhay /* Accept Long Packets for VLAN support */ 214187390Sjhay SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 214287390Sjhay 214350974Swpaul /* Set TX configuration */ 214464963Swpaul if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 214564963Swpaul CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 214664963Swpaul } else { 214764963Swpaul CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 214864963Swpaul } 214950974Swpaul 215064963Swpaul /* Set full/half duplex mode. */ 215164963Swpaul if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 215264963Swpaul SIS_SETBIT(sc, SIS_TX_CFG, 215364963Swpaul (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 215464963Swpaul SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 215564963Swpaul } else { 215664963Swpaul SIS_CLRBIT(sc, SIS_TX_CFG, 215764963Swpaul (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 215864963Swpaul SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 215964963Swpaul } 216064963Swpaul 2161119712Sphk if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr < NS_SRR_16A && 2162119130Ssam IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 2163119130Ssam uint32_t reg; 2164119130Ssam 2165119130Ssam /* 2166119130Ssam * Some DP83815s experience problems when used with short 2167119130Ssam * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 2168119130Ssam * sequence adjusts the DSP's signal attenuation to fix the 2169119130Ssam * problem. 2170119130Ssam */ 2171119130Ssam CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 2172119130Ssam 2173119130Ssam reg = CSR_READ_4(sc, NS_PHY_DSPCFG); 2174123491Sphk /* Allow coefficient to be read */ 2175119130Ssam CSR_WRITE_4(sc, NS_PHY_DSPCFG, (reg & 0xfff) | 0x1000); 2176119130Ssam DELAY(100); 2177119130Ssam reg = CSR_READ_4(sc, NS_PHY_TDATA); 2178123491Sphk if ((reg & 0x0080) == 0 || 2179123491Sphk (reg > 0xd8 && reg <= 0xff)) { 2180119712Sphk device_printf(sc->sis_self, "Applying short cable fix (reg=%x)\n", reg); 2181119130Ssam CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8); 2182123491Sphk /* Adjust coefficient and prevent change */ 2183119130Ssam SIS_SETBIT(sc, NS_PHY_DSPCFG, 0x20); 2184119130Ssam } 2185119130Ssam CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 2186119130Ssam } 2187119130Ssam 218850974Swpaul /* 218950974Swpaul * Enable interrupts. 219050974Swpaul */ 219150974Swpaul CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 219287902Sluigi#ifdef DEVICE_POLLING 219387902Sluigi /* 219487902Sluigi * ... only enable interrupts if we are not polling, make sure 219587902Sluigi * they are off otherwise. 219687902Sluigi */ 2197102052Ssobomax if (ifp->if_flags & IFF_POLLING) 219887902Sluigi CSR_WRITE_4(sc, SIS_IER, 0); 219987902Sluigi else 220087902Sluigi#endif /* DEVICE_POLLING */ 220150974Swpaul CSR_WRITE_4(sc, SIS_IER, 1); 220250974Swpaul 220350974Swpaul /* Enable receiver and transmitter. */ 220450974Swpaul SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 220550974Swpaul SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 220650974Swpaul 220764963Swpaul#ifdef notdef 220850974Swpaul mii_mediachg(mii); 220964963Swpaul#endif 221050974Swpaul 221150974Swpaul ifp->if_flags |= IFF_RUNNING; 221250974Swpaul ifp->if_flags &= ~IFF_OACTIVE; 221350974Swpaul 2214117858Scognet if (!sc->in_tick) 2215119785Ssam callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 221650974Swpaul 221767087Swpaul SIS_UNLOCK(sc); 221867087Swpaul 221950974Swpaul return; 222050974Swpaul} 222150974Swpaul 222250974Swpaul/* 222350974Swpaul * Set media options. 222450974Swpaul */ 2225102334Salfredstatic int 2226102334Salfredsis_ifmedia_upd(ifp) 222750974Swpaul struct ifnet *ifp; 222850974Swpaul{ 222950974Swpaul struct sis_softc *sc; 223064963Swpaul struct mii_data *mii; 223150974Swpaul 223250974Swpaul sc = ifp->if_softc; 223350974Swpaul 223464963Swpaul mii = device_get_softc(sc->sis_miibus); 223564963Swpaul sc->sis_link = 0; 223664963Swpaul if (mii->mii_instance) { 223764963Swpaul struct mii_softc *miisc; 223872012Sphk LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 223964963Swpaul mii_phy_reset(miisc); 224064963Swpaul } 224164963Swpaul mii_mediachg(mii); 224250974Swpaul 224350974Swpaul return(0); 224450974Swpaul} 224550974Swpaul 224650974Swpaul/* 224750974Swpaul * Report current media status. 224850974Swpaul */ 2249102334Salfredstatic void 2250102334Salfredsis_ifmedia_sts(ifp, ifmr) 225150974Swpaul struct ifnet *ifp; 225250974Swpaul struct ifmediareq *ifmr; 225350974Swpaul{ 225450974Swpaul struct sis_softc *sc; 225550974Swpaul struct mii_data *mii; 225650974Swpaul 225750974Swpaul sc = ifp->if_softc; 225850974Swpaul 225950974Swpaul mii = device_get_softc(sc->sis_miibus); 226050974Swpaul mii_pollstat(mii); 226150974Swpaul ifmr->ifm_active = mii->mii_media_active; 226250974Swpaul ifmr->ifm_status = mii->mii_media_status; 226350974Swpaul 226450974Swpaul return; 226550974Swpaul} 226650974Swpaul 2267102334Salfredstatic int 2268102334Salfredsis_ioctl(ifp, command, data) 226950974Swpaul struct ifnet *ifp; 227050974Swpaul u_long command; 227150974Swpaul caddr_t data; 227250974Swpaul{ 227350974Swpaul struct sis_softc *sc = ifp->if_softc; 227450974Swpaul struct ifreq *ifr = (struct ifreq *) data; 227550974Swpaul struct mii_data *mii; 227667087Swpaul int error = 0; 227750974Swpaul 227850974Swpaul switch(command) { 227950974Swpaul case SIOCSIFFLAGS: 228050974Swpaul if (ifp->if_flags & IFF_UP) { 228150974Swpaul sis_init(sc); 228250974Swpaul } else { 228350974Swpaul if (ifp->if_flags & IFF_RUNNING) 228450974Swpaul sis_stop(sc); 228550974Swpaul } 228650974Swpaul error = 0; 228750974Swpaul break; 228850974Swpaul case SIOCADDMULTI: 228950974Swpaul case SIOCDELMULTI: 229081713Swpaul SIS_LOCK(sc); 229162672Swpaul if (sc->sis_type == SIS_TYPE_83815) 229262672Swpaul sis_setmulti_ns(sc); 229362672Swpaul else 229462672Swpaul sis_setmulti_sis(sc); 229581713Swpaul SIS_UNLOCK(sc); 229650974Swpaul error = 0; 229750974Swpaul break; 229850974Swpaul case SIOCGIFMEDIA: 229950974Swpaul case SIOCSIFMEDIA: 230050974Swpaul mii = device_get_softc(sc->sis_miibus); 230181713Swpaul SIS_LOCK(sc); 230250974Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 230381713Swpaul SIS_UNLOCK(sc); 230450974Swpaul break; 2305128138Sru case SIOCSIFCAP: 2306129633Syar ifp->if_capenable &= ~IFCAP_POLLING; 2307129633Syar ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_POLLING; 2308128138Sru break; 230950974Swpaul default: 2310106936Ssam error = ether_ioctl(ifp, command, data); 231150974Swpaul break; 231250974Swpaul } 231350974Swpaul 231450974Swpaul return(error); 231550974Swpaul} 231650974Swpaul 2317102334Salfredstatic void 2318102334Salfredsis_watchdog(ifp) 231950974Swpaul struct ifnet *ifp; 232050974Swpaul{ 232150974Swpaul struct sis_softc *sc; 232250974Swpaul 232350974Swpaul sc = ifp->if_softc; 232450974Swpaul 232567087Swpaul SIS_LOCK(sc); 232667087Swpaul 232750974Swpaul ifp->if_oerrors++; 232850974Swpaul printf("sis%d: watchdog timeout\n", sc->sis_unit); 232950974Swpaul 233050974Swpaul sis_stop(sc); 233150974Swpaul sis_reset(sc); 233250974Swpaul sis_init(sc); 233350974Swpaul 2334131455Smlaier if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 233550974Swpaul sis_start(ifp); 233650974Swpaul 233767087Swpaul SIS_UNLOCK(sc); 233867087Swpaul 233950974Swpaul return; 234050974Swpaul} 234150974Swpaul 234250974Swpaul/* 234350974Swpaul * Stop the adapter and free any mbufs allocated to the 234450974Swpaul * RX and TX lists. 234550974Swpaul */ 2346102334Salfredstatic void 2347102334Salfredsis_stop(sc) 234850974Swpaul struct sis_softc *sc; 234950974Swpaul{ 2350139708Sphk int i; 235150974Swpaul struct ifnet *ifp; 235250974Swpaul 2353123833Sphk if (sc->sis_stopped) 2354123833Sphk return; 235567087Swpaul SIS_LOCK(sc); 235650974Swpaul ifp = &sc->arpcom.ac_if; 235750974Swpaul ifp->if_timer = 0; 235850974Swpaul 2359119785Ssam callout_stop(&sc->sis_stat_ch); 236087472Speter 236187472Speter ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 236287902Sluigi#ifdef DEVICE_POLLING 236387902Sluigi ether_poll_deregister(ifp); 236487902Sluigi#endif 236550974Swpaul CSR_WRITE_4(sc, SIS_IER, 0); 236650974Swpaul CSR_WRITE_4(sc, SIS_IMR, 0); 236750974Swpaul SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 236850974Swpaul DELAY(1000); 236950974Swpaul CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 237050974Swpaul CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 237150974Swpaul 237264963Swpaul sc->sis_link = 0; 237364963Swpaul 237450974Swpaul /* 237550974Swpaul * Free data in the RX lists. 237650974Swpaul */ 237750974Swpaul for (i = 0; i < SIS_RX_LIST_CNT; i++) { 2378139690Sphk if (sc->sis_rx_list[i].sis_mbuf != NULL) { 237981713Swpaul bus_dmamap_unload(sc->sis_tag, 2380139690Sphk sc->sis_rx_list[i].sis_map); 238181713Swpaul bus_dmamap_destroy(sc->sis_tag, 2382139690Sphk sc->sis_rx_list[i].sis_map); 2383139690Sphk m_freem(sc->sis_rx_list[i].sis_mbuf); 2384139690Sphk sc->sis_rx_list[i].sis_mbuf = NULL; 238550974Swpaul } 238650974Swpaul } 2387139690Sphk bzero(sc->sis_rx_list, 2388139690Sphk sizeof(sc->sis_rx_list)); 238950974Swpaul 239050974Swpaul /* 239150974Swpaul * Free the TX list buffers. 239250974Swpaul */ 239350974Swpaul for (i = 0; i < SIS_TX_LIST_CNT; i++) { 2394139690Sphk if (sc->sis_tx_list[i].sis_mbuf != NULL) { 239581713Swpaul bus_dmamap_unload(sc->sis_tag, 2396139690Sphk sc->sis_tx_list[i].sis_map); 239781713Swpaul bus_dmamap_destroy(sc->sis_tag, 2398139690Sphk sc->sis_tx_list[i].sis_map); 2399139690Sphk m_freem(sc->sis_tx_list[i].sis_mbuf); 2400139690Sphk sc->sis_tx_list[i].sis_mbuf = NULL; 240150974Swpaul } 240250974Swpaul } 240350974Swpaul 2404139690Sphk bzero(sc->sis_tx_list, 2405139690Sphk sizeof(sc->sis_tx_list)); 240650974Swpaul 2407123833Sphk sc->sis_stopped = 1; 240867087Swpaul SIS_UNLOCK(sc); 240967087Swpaul 241050974Swpaul return; 241150974Swpaul} 241250974Swpaul 241350974Swpaul/* 241450974Swpaul * Stop all chip I/O so that the kernel's probe routines don't 241550974Swpaul * get confused by errant DMAs when rebooting. 241650974Swpaul */ 2417102334Salfredstatic void 2418102334Salfredsis_shutdown(dev) 241950974Swpaul device_t dev; 242050974Swpaul{ 242150974Swpaul struct sis_softc *sc; 242250974Swpaul 242350974Swpaul sc = device_get_softc(dev); 242467087Swpaul SIS_LOCK(sc); 242550974Swpaul sis_reset(sc); 242650974Swpaul sis_stop(sc); 242767087Swpaul SIS_UNLOCK(sc); 242850974Swpaul 242950974Swpaul return; 243050974Swpaul} 2431