if_sis.c revision 122689
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/pci/if_sis.c 122689 2003-11-14 19:00:32Z sam $"); 35 36/* 37 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 38 * available from http://www.sis.com.tw. 39 * 40 * This driver also supports the NatSemi DP83815. Datasheets are 41 * available from http://www.national.com. 42 * 43 * Written by Bill Paul <wpaul@ee.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47/* 48 * The SiS 900 is a fairly simple chip. It uses bus master DMA with 49 * simple TX and RX descriptors of 3 longwords in size. The receiver 50 * has a single perfect filter entry for the station address and a 51 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 52 * transceiver while the 7016 requires an external transceiver chip. 53 * Both chips offer the standard bit-bang MII interface as well as 54 * an enchanced PHY interface which simplifies accessing MII registers. 55 * 56 * The only downside to this chipset is that RX descriptors must be 57 * longword aligned. 58 */ 59 60#include <sys/param.h> 61#include <sys/systm.h> 62#include <sys/sockio.h> 63#include <sys/mbuf.h> 64#include <sys/malloc.h> 65#include <sys/kernel.h> 66#include <sys/socket.h> 67#include <sys/sysctl.h> 68 69#include <net/if.h> 70#include <net/if_arp.h> 71#include <net/ethernet.h> 72#include <net/if_dl.h> 73#include <net/if_media.h> 74#include <net/if_types.h> 75#include <net/if_vlan_var.h> 76 77#include <net/bpf.h> 78 79#include <machine/bus_pio.h> 80#include <machine/bus_memio.h> 81#include <machine/bus.h> 82#include <machine/resource.h> 83#include <sys/bus.h> 84#include <sys/rman.h> 85 86#include <dev/mii/mii.h> 87#include <dev/mii/miivar.h> 88 89#include <dev/pci/pcireg.h> 90#include <dev/pci/pcivar.h> 91 92#define SIS_USEIOSPACE 93 94#include <pci/if_sisreg.h> 95 96MODULE_DEPEND(sis, pci, 1, 1, 1); 97MODULE_DEPEND(sis, ether, 1, 1, 1); 98MODULE_DEPEND(sis, miibus, 1, 1, 1); 99 100/* "controller miibus0" required. See GENERIC if you get errors here. */ 101#include "miibus_if.h" 102 103/* 104 * Various supported device vendors/types and their names. 105 */ 106static struct sis_type sis_devs[] = { 107 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 108 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 109 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" }, 110 { 0, 0, NULL } 111}; 112 113static int sis_probe (device_t); 114static int sis_attach (device_t); 115static int sis_detach (device_t); 116 117static int sis_newbuf (struct sis_softc *, 118 struct sis_desc *, struct mbuf *); 119static int sis_encap (struct sis_softc *, 120 struct mbuf **, u_int32_t *); 121static void sis_rxeof (struct sis_softc *); 122static void sis_rxeoc (struct sis_softc *); 123static void sis_txeof (struct sis_softc *); 124static void sis_intr (void *); 125static void sis_tick (void *); 126static void sis_start (struct ifnet *); 127static int sis_ioctl (struct ifnet *, u_long, caddr_t); 128static void sis_init (void *); 129static void sis_stop (struct sis_softc *); 130static void sis_watchdog (struct ifnet *); 131static void sis_shutdown (device_t); 132static int sis_ifmedia_upd (struct ifnet *); 133static void sis_ifmedia_sts (struct ifnet *, struct ifmediareq *); 134 135static u_int16_t sis_reverse (u_int16_t); 136static void sis_delay (struct sis_softc *); 137static void sis_eeprom_idle (struct sis_softc *); 138static void sis_eeprom_putbyte (struct sis_softc *, int); 139static void sis_eeprom_getword (struct sis_softc *, int, u_int16_t *); 140static void sis_read_eeprom (struct sis_softc *, caddr_t, int, int, int); 141#ifdef __i386__ 142static void sis_read_cmos (struct sis_softc *, device_t, caddr_t, 143 int, int); 144static void sis_read_mac (struct sis_softc *, device_t, caddr_t); 145static device_t sis_find_bridge (device_t); 146#endif 147 148static void sis_mii_sync (struct sis_softc *); 149static void sis_mii_send (struct sis_softc *, u_int32_t, int); 150static int sis_mii_readreg (struct sis_softc *, struct sis_mii_frame *); 151static int sis_mii_writereg (struct sis_softc *, struct sis_mii_frame *); 152static int sis_miibus_readreg (device_t, int, int); 153static int sis_miibus_writereg (device_t, int, int, int); 154static void sis_miibus_statchg (device_t); 155 156static void sis_setmulti_sis (struct sis_softc *); 157static void sis_setmulti_ns (struct sis_softc *); 158static u_int32_t sis_mchash (struct sis_softc *, caddr_t); 159static void sis_reset (struct sis_softc *); 160static int sis_list_rx_init (struct sis_softc *); 161static int sis_list_tx_init (struct sis_softc *); 162 163static void sis_dma_map_desc_ptr (void *, bus_dma_segment_t *, int, int); 164static void sis_dma_map_desc_next (void *, bus_dma_segment_t *, int, int); 165static void sis_dma_map_ring (void *, bus_dma_segment_t *, int, int); 166#ifdef SIS_USEIOSPACE 167#define SIS_RES SYS_RES_IOPORT 168#define SIS_RID SIS_PCI_LOIO 169#else 170#define SIS_RES SYS_RES_MEMORY 171#define SIS_RID SIS_PCI_LOMEM 172#endif 173 174static device_method_t sis_methods[] = { 175 /* Device interface */ 176 DEVMETHOD(device_probe, sis_probe), 177 DEVMETHOD(device_attach, sis_attach), 178 DEVMETHOD(device_detach, sis_detach), 179 DEVMETHOD(device_shutdown, sis_shutdown), 180 181 /* bus interface */ 182 DEVMETHOD(bus_print_child, bus_generic_print_child), 183 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 184 185 /* MII interface */ 186 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 187 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 188 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 189 190 { 0, 0 } 191}; 192 193static driver_t sis_driver = { 194 "sis", 195 sis_methods, 196 sizeof(struct sis_softc) 197}; 198 199static devclass_t sis_devclass; 200 201DRIVER_MODULE(sis, pci, sis_driver, sis_devclass, 0, 0); 202DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 203 204#define SIS_SETBIT(sc, reg, x) \ 205 CSR_WRITE_4(sc, reg, \ 206 CSR_READ_4(sc, reg) | (x)) 207 208#define SIS_CLRBIT(sc, reg, x) \ 209 CSR_WRITE_4(sc, reg, \ 210 CSR_READ_4(sc, reg) & ~(x)) 211 212#define SIO_SET(x) \ 213 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 214 215#define SIO_CLR(x) \ 216 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 217 218static void 219sis_dma_map_desc_next(arg, segs, nseg, error) 220 void *arg; 221 bus_dma_segment_t *segs; 222 int nseg, error; 223{ 224 struct sis_desc *r; 225 226 r = arg; 227 r->sis_next = segs->ds_addr; 228 229 return; 230} 231 232static void 233sis_dma_map_desc_ptr(arg, segs, nseg, error) 234 void *arg; 235 bus_dma_segment_t *segs; 236 int nseg, error; 237{ 238 struct sis_desc *r; 239 240 r = arg; 241 r->sis_ptr = segs->ds_addr; 242 243 return; 244} 245 246static void 247sis_dma_map_ring(arg, segs, nseg, error) 248 void *arg; 249 bus_dma_segment_t *segs; 250 int nseg, error; 251{ 252 u_int32_t *p; 253 254 p = arg; 255 *p = segs->ds_addr; 256 257 return; 258} 259 260/* 261 * Routine to reverse the bits in a word. Stolen almost 262 * verbatim from /usr/games/fortune. 263 */ 264static u_int16_t 265sis_reverse(n) 266 u_int16_t n; 267{ 268 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 269 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 270 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 271 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 272 273 return(n); 274} 275 276static void 277sis_delay(sc) 278 struct sis_softc *sc; 279{ 280 int idx; 281 282 for (idx = (300 / 33) + 1; idx > 0; idx--) 283 CSR_READ_4(sc, SIS_CSR); 284 285 return; 286} 287 288static void 289sis_eeprom_idle(sc) 290 struct sis_softc *sc; 291{ 292 register int i; 293 294 SIO_SET(SIS_EECTL_CSEL); 295 sis_delay(sc); 296 SIO_SET(SIS_EECTL_CLK); 297 sis_delay(sc); 298 299 for (i = 0; i < 25; i++) { 300 SIO_CLR(SIS_EECTL_CLK); 301 sis_delay(sc); 302 SIO_SET(SIS_EECTL_CLK); 303 sis_delay(sc); 304 } 305 306 SIO_CLR(SIS_EECTL_CLK); 307 sis_delay(sc); 308 SIO_CLR(SIS_EECTL_CSEL); 309 sis_delay(sc); 310 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 311 312 return; 313} 314 315/* 316 * Send a read command and address to the EEPROM, check for ACK. 317 */ 318static void 319sis_eeprom_putbyte(sc, addr) 320 struct sis_softc *sc; 321 int addr; 322{ 323 register int d, i; 324 325 d = addr | SIS_EECMD_READ; 326 327 /* 328 * Feed in each bit and stobe the clock. 329 */ 330 for (i = 0x400; i; i >>= 1) { 331 if (d & i) { 332 SIO_SET(SIS_EECTL_DIN); 333 } else { 334 SIO_CLR(SIS_EECTL_DIN); 335 } 336 sis_delay(sc); 337 SIO_SET(SIS_EECTL_CLK); 338 sis_delay(sc); 339 SIO_CLR(SIS_EECTL_CLK); 340 sis_delay(sc); 341 } 342 343 return; 344} 345 346/* 347 * Read a word of data stored in the EEPROM at address 'addr.' 348 */ 349static void 350sis_eeprom_getword(sc, addr, dest) 351 struct sis_softc *sc; 352 int addr; 353 u_int16_t *dest; 354{ 355 register int i; 356 u_int16_t word = 0; 357 358 /* Force EEPROM to idle state. */ 359 sis_eeprom_idle(sc); 360 361 /* Enter EEPROM access mode. */ 362 sis_delay(sc); 363 SIO_CLR(SIS_EECTL_CLK); 364 sis_delay(sc); 365 SIO_SET(SIS_EECTL_CSEL); 366 sis_delay(sc); 367 368 /* 369 * Send address of word we want to read. 370 */ 371 sis_eeprom_putbyte(sc, addr); 372 373 /* 374 * Start reading bits from EEPROM. 375 */ 376 for (i = 0x8000; i; i >>= 1) { 377 SIO_SET(SIS_EECTL_CLK); 378 sis_delay(sc); 379 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 380 word |= i; 381 sis_delay(sc); 382 SIO_CLR(SIS_EECTL_CLK); 383 sis_delay(sc); 384 } 385 386 /* Turn off EEPROM access mode. */ 387 sis_eeprom_idle(sc); 388 389 *dest = word; 390 391 return; 392} 393 394/* 395 * Read a sequence of words from the EEPROM. 396 */ 397static void 398sis_read_eeprom(sc, dest, off, cnt, swap) 399 struct sis_softc *sc; 400 caddr_t dest; 401 int off; 402 int cnt; 403 int swap; 404{ 405 int i; 406 u_int16_t word = 0, *ptr; 407 408 for (i = 0; i < cnt; i++) { 409 sis_eeprom_getword(sc, off + i, &word); 410 ptr = (u_int16_t *)(dest + (i * 2)); 411 if (swap) 412 *ptr = ntohs(word); 413 else 414 *ptr = word; 415 } 416 417 return; 418} 419 420#ifdef __i386__ 421static device_t 422sis_find_bridge(dev) 423 device_t dev; 424{ 425 devclass_t pci_devclass; 426 device_t *pci_devices; 427 int pci_count = 0; 428 device_t *pci_children; 429 int pci_childcount = 0; 430 device_t *busp, *childp; 431 device_t child = NULL; 432 int i, j; 433 434 if ((pci_devclass = devclass_find("pci")) == NULL) 435 return(NULL); 436 437 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 438 439 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 440 pci_childcount = 0; 441 device_get_children(*busp, &pci_children, &pci_childcount); 442 for (j = 0, childp = pci_children; 443 j < pci_childcount; j++, childp++) { 444 if (pci_get_vendor(*childp) == SIS_VENDORID && 445 pci_get_device(*childp) == 0x0008) { 446 child = *childp; 447 goto done; 448 } 449 } 450 } 451 452done: 453 free(pci_devices, M_TEMP); 454 free(pci_children, M_TEMP); 455 return(child); 456} 457 458static void 459sis_read_cmos(sc, dev, dest, off, cnt) 460 struct sis_softc *sc; 461 device_t dev; 462 caddr_t dest; 463 int off; 464 int cnt; 465{ 466 device_t bridge; 467 u_int8_t reg; 468 int i; 469 bus_space_tag_t btag; 470 471 bridge = sis_find_bridge(dev); 472 if (bridge == NULL) 473 return; 474 reg = pci_read_config(bridge, 0x48, 1); 475 pci_write_config(bridge, 0x48, reg|0x40, 1); 476 477 /* XXX */ 478 btag = I386_BUS_SPACE_IO; 479 480 for (i = 0; i < cnt; i++) { 481 bus_space_write_1(btag, 0x0, 0x70, i + off); 482 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 483 } 484 485 pci_write_config(bridge, 0x48, reg & ~0x40, 1); 486 return; 487} 488 489static void 490sis_read_mac(sc, dev, dest) 491 struct sis_softc *sc; 492 device_t dev; 493 caddr_t dest; 494{ 495 u_int32_t filtsave, csrsave; 496 497 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 498 csrsave = CSR_READ_4(sc, SIS_CSR); 499 500 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 501 CSR_WRITE_4(sc, SIS_CSR, 0); 502 503 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 504 505 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 506 ((u_int16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 507 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 508 ((u_int16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 509 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 510 ((u_int16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 511 512 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 513 CSR_WRITE_4(sc, SIS_CSR, csrsave); 514 return; 515} 516#endif 517 518/* 519 * Sync the PHYs by setting data bit and strobing the clock 32 times. 520 */ 521static void sis_mii_sync(sc) 522 struct sis_softc *sc; 523{ 524 register int i; 525 526 SIO_SET(SIS_MII_DIR|SIS_MII_DATA); 527 528 for (i = 0; i < 32; i++) { 529 SIO_SET(SIS_MII_CLK); 530 DELAY(1); 531 SIO_CLR(SIS_MII_CLK); 532 DELAY(1); 533 } 534 535 return; 536} 537 538/* 539 * Clock a series of bits through the MII. 540 */ 541static void sis_mii_send(sc, bits, cnt) 542 struct sis_softc *sc; 543 u_int32_t bits; 544 int cnt; 545{ 546 int i; 547 548 SIO_CLR(SIS_MII_CLK); 549 550 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 551 if (bits & i) { 552 SIO_SET(SIS_MII_DATA); 553 } else { 554 SIO_CLR(SIS_MII_DATA); 555 } 556 DELAY(1); 557 SIO_CLR(SIS_MII_CLK); 558 DELAY(1); 559 SIO_SET(SIS_MII_CLK); 560 } 561} 562 563/* 564 * Read an PHY register through the MII. 565 */ 566static int sis_mii_readreg(sc, frame) 567 struct sis_softc *sc; 568 struct sis_mii_frame *frame; 569 570{ 571 int i, ack, s; 572 573 s = splimp(); 574 575 /* 576 * Set up frame for RX. 577 */ 578 frame->mii_stdelim = SIS_MII_STARTDELIM; 579 frame->mii_opcode = SIS_MII_READOP; 580 frame->mii_turnaround = 0; 581 frame->mii_data = 0; 582 583 /* 584 * Turn on data xmit. 585 */ 586 SIO_SET(SIS_MII_DIR); 587 588 sis_mii_sync(sc); 589 590 /* 591 * Send command/address info. 592 */ 593 sis_mii_send(sc, frame->mii_stdelim, 2); 594 sis_mii_send(sc, frame->mii_opcode, 2); 595 sis_mii_send(sc, frame->mii_phyaddr, 5); 596 sis_mii_send(sc, frame->mii_regaddr, 5); 597 598 /* Idle bit */ 599 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA)); 600 DELAY(1); 601 SIO_SET(SIS_MII_CLK); 602 DELAY(1); 603 604 /* Turn off xmit. */ 605 SIO_CLR(SIS_MII_DIR); 606 607 /* Check for ack */ 608 SIO_CLR(SIS_MII_CLK); 609 DELAY(1); 610 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA; 611 SIO_SET(SIS_MII_CLK); 612 DELAY(1); 613 614 /* 615 * Now try reading data bits. If the ack failed, we still 616 * need to clock through 16 cycles to keep the PHY(s) in sync. 617 */ 618 if (ack) { 619 for(i = 0; i < 16; i++) { 620 SIO_CLR(SIS_MII_CLK); 621 DELAY(1); 622 SIO_SET(SIS_MII_CLK); 623 DELAY(1); 624 } 625 goto fail; 626 } 627 628 for (i = 0x8000; i; i >>= 1) { 629 SIO_CLR(SIS_MII_CLK); 630 DELAY(1); 631 if (!ack) { 632 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA) 633 frame->mii_data |= i; 634 DELAY(1); 635 } 636 SIO_SET(SIS_MII_CLK); 637 DELAY(1); 638 } 639 640fail: 641 642 SIO_CLR(SIS_MII_CLK); 643 DELAY(1); 644 SIO_SET(SIS_MII_CLK); 645 DELAY(1); 646 647 splx(s); 648 649 if (ack) 650 return(1); 651 return(0); 652} 653 654/* 655 * Write to a PHY register through the MII. 656 */ 657static int sis_mii_writereg(sc, frame) 658 struct sis_softc *sc; 659 struct sis_mii_frame *frame; 660 661{ 662 int s; 663 664 s = splimp(); 665 /* 666 * Set up frame for TX. 667 */ 668 669 frame->mii_stdelim = SIS_MII_STARTDELIM; 670 frame->mii_opcode = SIS_MII_WRITEOP; 671 frame->mii_turnaround = SIS_MII_TURNAROUND; 672 673 /* 674 * Turn on data output. 675 */ 676 SIO_SET(SIS_MII_DIR); 677 678 sis_mii_sync(sc); 679 680 sis_mii_send(sc, frame->mii_stdelim, 2); 681 sis_mii_send(sc, frame->mii_opcode, 2); 682 sis_mii_send(sc, frame->mii_phyaddr, 5); 683 sis_mii_send(sc, frame->mii_regaddr, 5); 684 sis_mii_send(sc, frame->mii_turnaround, 2); 685 sis_mii_send(sc, frame->mii_data, 16); 686 687 /* Idle bit. */ 688 SIO_SET(SIS_MII_CLK); 689 DELAY(1); 690 SIO_CLR(SIS_MII_CLK); 691 DELAY(1); 692 693 /* 694 * Turn off xmit. 695 */ 696 SIO_CLR(SIS_MII_DIR); 697 698 splx(s); 699 700 return(0); 701} 702 703static int 704sis_miibus_readreg(dev, phy, reg) 705 device_t dev; 706 int phy, reg; 707{ 708 struct sis_softc *sc; 709 struct sis_mii_frame frame; 710 711 sc = device_get_softc(dev); 712 713 if (sc->sis_type == SIS_TYPE_83815) { 714 if (phy != 0) 715 return(0); 716 /* 717 * The NatSemi chip can take a while after 718 * a reset to come ready, during which the BMSR 719 * returns a value of 0. This is *never* supposed 720 * to happen: some of the BMSR bits are meant to 721 * be hardwired in the on position, and this can 722 * confuse the miibus code a bit during the probe 723 * and attach phase. So we make an effort to check 724 * for this condition and wait for it to clear. 725 */ 726 if (!CSR_READ_4(sc, NS_BMSR)) 727 DELAY(1000); 728 return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 729 } 730 731 /* 732 * Chipsets < SIS_635 seem not to be able to read/write 733 * through mdio. Use the enhanced PHY access register 734 * again for them. 735 */ 736 if (sc->sis_type == SIS_TYPE_900 && 737 sc->sis_rev < SIS_REV_635) { 738 int i, val = 0; 739 740 if (phy != 0) 741 return(0); 742 743 CSR_WRITE_4(sc, SIS_PHYCTL, 744 (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 745 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 746 747 for (i = 0; i < SIS_TIMEOUT; i++) { 748 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 749 break; 750 } 751 752 if (i == SIS_TIMEOUT) { 753 printf("sis%d: PHY failed to come ready\n", 754 sc->sis_unit); 755 return(0); 756 } 757 758 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 759 760 if (val == 0xFFFF) 761 return(0); 762 763 return(val); 764 } else { 765 bzero((char *)&frame, sizeof(frame)); 766 767 frame.mii_phyaddr = phy; 768 frame.mii_regaddr = reg; 769 sis_mii_readreg(sc, &frame); 770 771 return(frame.mii_data); 772 } 773} 774 775static int 776sis_miibus_writereg(dev, phy, reg, data) 777 device_t dev; 778 int phy, reg, data; 779{ 780 struct sis_softc *sc; 781 struct sis_mii_frame frame; 782 783 sc = device_get_softc(dev); 784 785 if (sc->sis_type == SIS_TYPE_83815) { 786 if (phy != 0) 787 return(0); 788 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 789 return(0); 790 } 791 792 /* 793 * Chipsets < SIS_635 seem not to be able to read/write 794 * through mdio. Use the enhanced PHY access register 795 * again for them. 796 */ 797 if (sc->sis_type == SIS_TYPE_900 && 798 sc->sis_rev < SIS_REV_635) { 799 int i; 800 801 if (phy != 0) 802 return(0); 803 804 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 805 (reg << 6) | SIS_PHYOP_WRITE); 806 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 807 808 for (i = 0; i < SIS_TIMEOUT; i++) { 809 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 810 break; 811 } 812 813 if (i == SIS_TIMEOUT) 814 printf("sis%d: PHY failed to come ready\n", 815 sc->sis_unit); 816 } else { 817 bzero((char *)&frame, sizeof(frame)); 818 819 frame.mii_phyaddr = phy; 820 frame.mii_regaddr = reg; 821 frame.mii_data = data; 822 sis_mii_writereg(sc, &frame); 823 } 824 return(0); 825} 826 827static void 828sis_miibus_statchg(dev) 829 device_t dev; 830{ 831 struct sis_softc *sc; 832 833 sc = device_get_softc(dev); 834 sis_init(sc); 835 836 return; 837} 838 839static u_int32_t 840sis_mchash(sc, addr) 841 struct sis_softc *sc; 842 caddr_t addr; 843{ 844 u_int32_t crc, carry; 845 int idx, bit; 846 u_int8_t data; 847 848 /* Compute CRC for the address value. */ 849 crc = 0xFFFFFFFF; /* initial value */ 850 851 for (idx = 0; idx < 6; idx++) { 852 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 853 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 854 crc <<= 1; 855 if (carry) 856 crc = (crc ^ 0x04c11db6) | carry; 857 } 858 } 859 860 /* 861 * return the filter bit position 862 * 863 * The NatSemi chip has a 512-bit filter, which is 864 * different than the SiS, so we special-case it. 865 */ 866 if (sc->sis_type == SIS_TYPE_83815) 867 return (crc >> 23); 868 else if (sc->sis_rev >= SIS_REV_635 || 869 sc->sis_rev == SIS_REV_900B) 870 return (crc >> 24); 871 else 872 return (crc >> 25); 873} 874 875static void 876sis_setmulti_ns(sc) 877 struct sis_softc *sc; 878{ 879 struct ifnet *ifp; 880 struct ifmultiaddr *ifma; 881 u_int32_t h = 0, i, filtsave; 882 int bit, index; 883 884 ifp = &sc->arpcom.ac_if; 885 886 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 887 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 888 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 889 return; 890 } 891 892 /* 893 * We have to explicitly enable the multicast hash table 894 * on the NatSemi chip if we want to use it, which we do. 895 */ 896 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 897 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 898 899 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 900 901 /* first, zot all the existing hash bits */ 902 for (i = 0; i < 32; i++) { 903 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 904 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 905 } 906 907 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 908 if (ifma->ifma_addr->sa_family != AF_LINK) 909 continue; 910 h = sis_mchash(sc, 911 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 912 index = h >> 3; 913 bit = h & 0x1F; 914 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 915 if (bit > 0xF) 916 bit -= 0x10; 917 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 918 } 919 920 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 921 922 return; 923} 924 925static void 926sis_setmulti_sis(sc) 927 struct sis_softc *sc; 928{ 929 struct ifnet *ifp; 930 struct ifmultiaddr *ifma; 931 u_int32_t h, i, n, ctl; 932 u_int16_t hashes[16]; 933 934 ifp = &sc->arpcom.ac_if; 935 936 /* hash table size */ 937 if (sc->sis_rev >= SIS_REV_635 || 938 sc->sis_rev == SIS_REV_900B) 939 n = 16; 940 else 941 n = 8; 942 943 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE; 944 945 if (ifp->if_flags & IFF_BROADCAST) 946 ctl |= SIS_RXFILTCTL_BROAD; 947 948 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 949 ctl |= SIS_RXFILTCTL_ALLMULTI; 950 if (ifp->if_flags & IFF_PROMISC) 951 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS; 952 for (i = 0; i < n; i++) 953 hashes[i] = ~0; 954 } else { 955 for (i = 0; i < n; i++) 956 hashes[i] = 0; 957 i = 0; 958 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 959 if (ifma->ifma_addr->sa_family != AF_LINK) 960 continue; 961 h = sis_mchash(sc, 962 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 963 hashes[h >> 4] |= 1 << (h & 0xf); 964 i++; 965 } 966 if (i > n) { 967 ctl |= SIS_RXFILTCTL_ALLMULTI; 968 for (i = 0; i < n; i++) 969 hashes[i] = ~0; 970 } 971 } 972 973 for (i = 0; i < n; i++) { 974 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); 975 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); 976 } 977 978 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl); 979} 980 981static void 982sis_reset(sc) 983 struct sis_softc *sc; 984{ 985 register int i; 986 987 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 988 989 for (i = 0; i < SIS_TIMEOUT; i++) { 990 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 991 break; 992 } 993 994 if (i == SIS_TIMEOUT) 995 printf("sis%d: reset never completed\n", sc->sis_unit); 996 997 /* Wait a little while for the chip to get its brains in order. */ 998 DELAY(1000); 999 1000 /* 1001 * If this is a NetSemi chip, make sure to clear 1002 * PME mode. 1003 */ 1004 if (sc->sis_type == SIS_TYPE_83815) { 1005 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 1006 CSR_WRITE_4(sc, NS_CLKRUN, 0); 1007 } 1008 1009 return; 1010} 1011 1012/* 1013 * Probe for an SiS chip. Check the PCI vendor and device 1014 * IDs against our list and return a device name if we find a match. 1015 */ 1016static int 1017sis_probe(dev) 1018 device_t dev; 1019{ 1020 struct sis_type *t; 1021 1022 t = sis_devs; 1023 1024 while(t->sis_name != NULL) { 1025 if ((pci_get_vendor(dev) == t->sis_vid) && 1026 (pci_get_device(dev) == t->sis_did)) { 1027 device_set_desc(dev, t->sis_name); 1028 return(0); 1029 } 1030 t++; 1031 } 1032 1033 return(ENXIO); 1034} 1035 1036/* 1037 * Attach the interface. Allocate softc structures, do ifmedia 1038 * setup and ethernet/BPF attach. 1039 */ 1040static int 1041sis_attach(dev) 1042 device_t dev; 1043{ 1044 u_char eaddr[ETHER_ADDR_LEN]; 1045 struct sis_softc *sc; 1046 struct ifnet *ifp; 1047 int unit, error = 0, rid, waittime = 0; 1048 1049 waittime = 0; 1050 sc = device_get_softc(dev); 1051 unit = device_get_unit(dev); 1052 1053 sc->sis_self = dev; 1054 1055 mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1056 MTX_DEF | MTX_RECURSE); 1057 1058 if (pci_get_device(dev) == SIS_DEVICEID_900) 1059 sc->sis_type = SIS_TYPE_900; 1060 if (pci_get_device(dev) == SIS_DEVICEID_7016) 1061 sc->sis_type = SIS_TYPE_7016; 1062 if (pci_get_vendor(dev) == NS_VENDORID) 1063 sc->sis_type = SIS_TYPE_83815; 1064 1065 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 1066#ifndef BURN_BRIDGES 1067 /* 1068 * Handle power management nonsense. 1069 */ 1070 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1071 u_int32_t iobase, membase, irq; 1072 1073 /* Save important PCI config data. */ 1074 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4); 1075 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4); 1076 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4); 1077 1078 /* Reset the power state. */ 1079 printf("sis%d: chip is in D%d power mode " 1080 "-- setting to D0\n", unit, 1081 pci_get_powerstate(dev)); 1082 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1083 1084 /* Restore PCI config data. */ 1085 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4); 1086 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4); 1087 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4); 1088 } 1089#endif 1090 /* 1091 * Map control/status registers. 1092 */ 1093 pci_enable_busmaster(dev); 1094 1095 rid = SIS_RID; 1096 sc->sis_res = bus_alloc_resource(dev, SIS_RES, &rid, 1097 0, ~0, 1, RF_ACTIVE); 1098 1099 if (sc->sis_res == NULL) { 1100 printf("sis%d: couldn't map ports/memory\n", unit); 1101 error = ENXIO; 1102 goto fail; 1103 } 1104 1105 sc->sis_btag = rman_get_bustag(sc->sis_res); 1106 sc->sis_bhandle = rman_get_bushandle(sc->sis_res); 1107 1108 /* Allocate interrupt */ 1109 rid = 0; 1110 sc->sis_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1111 RF_SHAREABLE | RF_ACTIVE); 1112 1113 if (sc->sis_irq == NULL) { 1114 printf("sis%d: couldn't map interrupt\n", unit); 1115 error = ENXIO; 1116 goto fail; 1117 } 1118 1119 /* Reset the adapter. */ 1120 sis_reset(sc); 1121 1122 if (sc->sis_type == SIS_TYPE_900 && 1123 (sc->sis_rev == SIS_REV_635 || 1124 sc->sis_rev == SIS_REV_900B)) { 1125 SIO_SET(SIS_CFG_RND_CNT); 1126 SIO_SET(SIS_CFG_PERR_DETECT); 1127 } 1128 1129 /* 1130 * Get station address from the EEPROM. 1131 */ 1132 switch (pci_get_vendor(dev)) { 1133 case NS_VENDORID: 1134 sc->sis_srr = CSR_READ_4(sc, NS_SRR); 1135 1136 /* We can't update the device description, so spew */ 1137 if (sc->sis_srr == NS_SRR_15C) 1138 device_printf(dev, "Silicon Revision: DP83815C\n"); 1139 else if (sc->sis_srr == NS_SRR_15D) 1140 device_printf(dev, "Silicon Revision: DP83815D\n"); 1141 else if (sc->sis_srr == NS_SRR_16A) 1142 device_printf(dev, "Silicon Revision: DP83816A\n"); 1143 else 1144 device_printf(dev, "Silicon Revision %x\n", sc->sis_srr); 1145 1146 /* 1147 * Reading the MAC address out of the EEPROM on 1148 * the NatSemi chip takes a bit more work than 1149 * you'd expect. The address spans 4 16-bit words, 1150 * with the first word containing only a single bit. 1151 * You have to shift everything over one bit to 1152 * get it aligned properly. Also, the bits are 1153 * stored backwards (the LSB is really the MSB, 1154 * and so on) so you have to reverse them in order 1155 * to get the MAC address into the form we want. 1156 * Why? Who the hell knows. 1157 */ 1158 { 1159 u_int16_t tmp[4]; 1160 1161 sis_read_eeprom(sc, (caddr_t)&tmp, 1162 NS_EE_NODEADDR, 4, 0); 1163 1164 /* Shift everything over one bit. */ 1165 tmp[3] = tmp[3] >> 1; 1166 tmp[3] |= tmp[2] << 15; 1167 tmp[2] = tmp[2] >> 1; 1168 tmp[2] |= tmp[1] << 15; 1169 tmp[1] = tmp[1] >> 1; 1170 tmp[1] |= tmp[0] << 15; 1171 1172 /* Now reverse all the bits. */ 1173 tmp[3] = sis_reverse(tmp[3]); 1174 tmp[2] = sis_reverse(tmp[2]); 1175 tmp[1] = sis_reverse(tmp[1]); 1176 1177 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); 1178 } 1179 break; 1180 case SIS_VENDORID: 1181 default: 1182#ifdef __i386__ 1183 /* 1184 * If this is a SiS 630E chipset with an embedded 1185 * SiS 900 controller, we have to read the MAC address 1186 * from the APC CMOS RAM. Our method for doing this 1187 * is very ugly since we have to reach out and grab 1188 * ahold of hardware for which we cannot properly 1189 * allocate resources. This code is only compiled on 1190 * the i386 architecture since the SiS 630E chipset 1191 * is for x86 motherboards only. Note that there are 1192 * a lot of magic numbers in this hack. These are 1193 * taken from SiS's Linux driver. I'd like to replace 1194 * them with proper symbolic definitions, but that 1195 * requires some datasheets that I don't have access 1196 * to at the moment. 1197 */ 1198 if (sc->sis_rev == SIS_REV_630S || 1199 sc->sis_rev == SIS_REV_630E || 1200 sc->sis_rev == SIS_REV_630EA1) 1201 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 1202 1203 else if (sc->sis_rev == SIS_REV_635 || 1204 sc->sis_rev == SIS_REV_630ET) 1205 sis_read_mac(sc, dev, (caddr_t)&eaddr); 1206 else if (sc->sis_rev == SIS_REV_96x) { 1207 /* Allow to read EEPROM from LAN. It is shared 1208 * between a 1394 controller and the NIC and each 1209 * time we access it, we need to set SIS_EECMD_REQ. 1210 */ 1211 SIO_SET(SIS_EECMD_REQ); 1212 for (waittime = 0; waittime < SIS_TIMEOUT; 1213 waittime++) { 1214 /* Force EEPROM to idle state. */ 1215 sis_eeprom_idle(sc); 1216 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { 1217 sis_read_eeprom(sc, (caddr_t)&eaddr, 1218 SIS_EE_NODEADDR, 3, 0); 1219 break; 1220 } 1221 DELAY(1); 1222 } 1223 /* 1224 * Set SIS_EECTL_CLK to high, so a other master 1225 * can operate on the i2c bus. 1226 */ 1227 SIO_SET(SIS_EECTL_CLK); 1228 /* Refuse EEPROM access by LAN */ 1229 SIO_SET(SIS_EECMD_DONE); 1230 } else 1231#endif 1232 sis_read_eeprom(sc, (caddr_t)&eaddr, 1233 SIS_EE_NODEADDR, 3, 0); 1234 break; 1235 } 1236 1237 /* 1238 * A SiS chip was detected. Inform the world. 1239 */ 1240 printf("sis%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1241 1242 sc->sis_unit = unit; 1243 callout_init(&sc->sis_stat_ch, CALLOUT_MPSAFE); 1244 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1245 1246 /* 1247 * Allocate the parent bus DMA tag appropriate for PCI. 1248 */ 1249#define SIS_NSEG_NEW 32 1250 error = bus_dma_tag_create(NULL, /* parent */ 1251 1, 0, /* alignment, boundary */ 1252 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1253 BUS_SPACE_MAXADDR, /* highaddr */ 1254 NULL, NULL, /* filter, filterarg */ 1255 MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */ 1256 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1257 BUS_DMA_ALLOCNOW, /* flags */ 1258 NULL, NULL, /* lockfunc, lockarg */ 1259 &sc->sis_parent_tag); 1260 if (error) 1261 goto fail; 1262 1263 /* 1264 * Now allocate a tag for the DMA descriptor lists and a chunk 1265 * of DMA-able memory based on the tag. Also obtain the physical 1266 * addresses of the RX and TX ring, which we'll need later. 1267 * All of our lists are allocated as a contiguous block 1268 * of memory. 1269 */ 1270 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1271 1, 0, /* alignment, boundary */ 1272 BUS_SPACE_MAXADDR, /* lowaddr */ 1273 BUS_SPACE_MAXADDR, /* highaddr */ 1274 NULL, NULL, /* filter, filterarg */ 1275 SIS_RX_LIST_SZ, 1, /* maxsize,nsegments */ 1276 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1277 0, /* flags */ 1278 busdma_lock_mutex, /* lockfunc */ 1279 &Giant, /* lockarg */ 1280 &sc->sis_ldata.sis_rx_tag); 1281 if (error) 1282 goto fail; 1283 1284 error = bus_dmamem_alloc(sc->sis_ldata.sis_rx_tag, 1285 (void **)&sc->sis_ldata.sis_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1286 &sc->sis_ldata.sis_rx_dmamap); 1287 1288 if (error) { 1289 printf("sis%d: no memory for rx list buffers!\n", unit); 1290 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1291 sc->sis_ldata.sis_rx_tag = NULL; 1292 goto fail; 1293 } 1294 1295 error = bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1296 sc->sis_ldata.sis_rx_dmamap, &(sc->sis_ldata.sis_rx_list[0]), 1297 sizeof(struct sis_desc), sis_dma_map_ring, 1298 &sc->sis_cdata.sis_rx_paddr, 0); 1299 1300 if (error) { 1301 printf("sis%d: cannot get address of the rx ring!\n", unit); 1302 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1303 sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap); 1304 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1305 sc->sis_ldata.sis_rx_tag = NULL; 1306 goto fail; 1307 } 1308 1309 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1310 1, 0, /* alignment, boundary */ 1311 BUS_SPACE_MAXADDR, /* lowaddr */ 1312 BUS_SPACE_MAXADDR, /* highaddr */ 1313 NULL, NULL, /* filter, filterarg */ 1314 SIS_TX_LIST_SZ, 1, /* maxsize,nsegments */ 1315 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1316 0, /* flags */ 1317 busdma_lock_mutex, /* lockfunc */ 1318 &Giant, /* lockarg */ 1319 &sc->sis_ldata.sis_tx_tag); 1320 if (error) 1321 goto fail; 1322 1323 error = bus_dmamem_alloc(sc->sis_ldata.sis_tx_tag, 1324 (void **)&sc->sis_ldata.sis_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1325 &sc->sis_ldata.sis_tx_dmamap); 1326 1327 if (error) { 1328 printf("sis%d: no memory for tx list buffers!\n", unit); 1329 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1330 sc->sis_ldata.sis_tx_tag = NULL; 1331 goto fail; 1332 } 1333 1334 error = bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1335 sc->sis_ldata.sis_tx_dmamap, &(sc->sis_ldata.sis_tx_list[0]), 1336 sizeof(struct sis_desc), sis_dma_map_ring, 1337 &sc->sis_cdata.sis_tx_paddr, 0); 1338 1339 if (error) { 1340 printf("sis%d: cannot get address of the tx ring!\n", unit); 1341 bus_dmamem_free(sc->sis_ldata.sis_tx_tag, 1342 sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 1343 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1344 sc->sis_ldata.sis_tx_tag = NULL; 1345 goto fail; 1346 } 1347 1348 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1349 1, 0, /* alignment, boundary */ 1350 BUS_SPACE_MAXADDR, /* lowaddr */ 1351 BUS_SPACE_MAXADDR, /* highaddr */ 1352 NULL, NULL, /* filter, filterarg */ 1353 MCLBYTES, 1, /* maxsize,nsegments */ 1354 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1355 0, /* flags */ 1356 busdma_lock_mutex, /* lockfunc */ 1357 &Giant, /* lockarg */ 1358 &sc->sis_tag); 1359 if (error) 1360 goto fail; 1361 1362 /* 1363 * Obtain the physical addresses of the RX and TX 1364 * rings which we'll need later in the init routine. 1365 */ 1366 1367 ifp = &sc->arpcom.ac_if; 1368 ifp->if_softc = sc; 1369 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1370 ifp->if_mtu = ETHERMTU; 1371 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1372 ifp->if_ioctl = sis_ioctl; 1373 ifp->if_output = ether_output; 1374 ifp->if_start = sis_start; 1375 ifp->if_watchdog = sis_watchdog; 1376 ifp->if_init = sis_init; 1377 ifp->if_baudrate = 10000000; 1378 ifp->if_snd.ifq_maxlen = SIS_TX_LIST_CNT - 1; 1379 1380 /* 1381 * Do MII setup. 1382 */ 1383 if (mii_phy_probe(dev, &sc->sis_miibus, 1384 sis_ifmedia_upd, sis_ifmedia_sts)) { 1385 printf("sis%d: MII without any PHY!\n", sc->sis_unit); 1386 error = ENXIO; 1387 goto fail; 1388 } 1389 1390 /* 1391 * Call MI attach routine. 1392 */ 1393 ether_ifattach(ifp, eaddr); 1394 1395 /* 1396 * Tell the upper layer(s) we support long frames. 1397 */ 1398 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1399 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1400 1401 /* Hook interrupt last to avoid having to lock softc */ 1402 error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET | INTR_MPSAFE, 1403 sis_intr, sc, &sc->sis_intrhand); 1404 1405 if (error) { 1406 printf("sis%d: couldn't set up irq\n", unit); 1407 ether_ifdetach(ifp); 1408 goto fail; 1409 } 1410 1411fail: 1412 if (error) 1413 sis_detach(dev); 1414 1415 return(error); 1416} 1417 1418/* 1419 * Shutdown hardware and free up resources. This can be called any 1420 * time after the mutex has been initialized. It is called in both 1421 * the error case in attach and the normal detach case so it needs 1422 * to be careful about only freeing resources that have actually been 1423 * allocated. 1424 */ 1425static int 1426sis_detach(dev) 1427 device_t dev; 1428{ 1429 struct sis_softc *sc; 1430 struct ifnet *ifp; 1431 1432 sc = device_get_softc(dev); 1433 KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized")); 1434 SIS_LOCK(sc); 1435 ifp = &sc->arpcom.ac_if; 1436 1437 /* These should only be active if attach succeeded. */ 1438 if (device_is_attached(dev)) { 1439 sis_reset(sc); 1440 sis_stop(sc); 1441 ether_ifdetach(ifp); 1442 } 1443 if (sc->sis_miibus) 1444 device_delete_child(dev, sc->sis_miibus); 1445 bus_generic_detach(dev); 1446 1447 if (sc->sis_intrhand) 1448 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1449 if (sc->sis_irq) 1450 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1451 if (sc->sis_res) 1452 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1453 1454 if (sc->sis_ldata.sis_rx_tag) { 1455 bus_dmamap_unload(sc->sis_ldata.sis_rx_tag, 1456 sc->sis_ldata.sis_rx_dmamap); 1457 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1458 sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap); 1459 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1460 } 1461 if (sc->sis_ldata.sis_tx_tag) { 1462 bus_dmamap_unload(sc->sis_ldata.sis_tx_tag, 1463 sc->sis_ldata.sis_tx_dmamap); 1464 bus_dmamem_free(sc->sis_ldata.sis_tx_tag, 1465 sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 1466 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1467 } 1468 if (sc->sis_parent_tag) 1469 bus_dma_tag_destroy(sc->sis_parent_tag); 1470 if (sc->sis_tag) 1471 bus_dma_tag_destroy(sc->sis_tag); 1472 1473 SIS_UNLOCK(sc); 1474 mtx_destroy(&sc->sis_mtx); 1475 1476 return(0); 1477} 1478 1479/* 1480 * Initialize the transmit descriptors. 1481 */ 1482static int 1483sis_list_tx_init(sc) 1484 struct sis_softc *sc; 1485{ 1486 struct sis_list_data *ld; 1487 struct sis_ring_data *cd; 1488 int i, nexti; 1489 1490 cd = &sc->sis_cdata; 1491 ld = &sc->sis_ldata; 1492 1493 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1494 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1; 1495 ld->sis_tx_list[i].sis_nextdesc = 1496 &ld->sis_tx_list[nexti]; 1497 bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1498 sc->sis_ldata.sis_tx_dmamap, 1499 &ld->sis_tx_list[nexti], sizeof(struct sis_desc), 1500 sis_dma_map_desc_next, &ld->sis_tx_list[i], 0); 1501 ld->sis_tx_list[i].sis_mbuf = NULL; 1502 ld->sis_tx_list[i].sis_ptr = 0; 1503 ld->sis_tx_list[i].sis_ctl = 0; 1504 } 1505 1506 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0; 1507 1508 bus_dmamap_sync(sc->sis_ldata.sis_tx_tag, 1509 sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 1510 1511 return(0); 1512} 1513 1514/* 1515 * Initialize the RX descriptors and allocate mbufs for them. Note that 1516 * we arrange the descriptors in a closed ring, so that the last descriptor 1517 * points back to the first. 1518 */ 1519static int 1520sis_list_rx_init(sc) 1521 struct sis_softc *sc; 1522{ 1523 struct sis_list_data *ld; 1524 struct sis_ring_data *cd; 1525 int i,nexti; 1526 1527 ld = &sc->sis_ldata; 1528 cd = &sc->sis_cdata; 1529 1530 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1531 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS) 1532 return(ENOBUFS); 1533 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1; 1534 ld->sis_rx_list[i].sis_nextdesc = 1535 &ld->sis_rx_list[nexti]; 1536 bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1537 sc->sis_ldata.sis_rx_dmamap, 1538 &ld->sis_rx_list[nexti], 1539 sizeof(struct sis_desc), sis_dma_map_desc_next, 1540 &ld->sis_rx_list[i], 0); 1541 } 1542 1543 bus_dmamap_sync(sc->sis_ldata.sis_rx_tag, 1544 sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 1545 1546 cd->sis_rx_prod = 0; 1547 1548 return(0); 1549} 1550 1551/* 1552 * Initialize an RX descriptor and attach an MBUF cluster. 1553 */ 1554static int 1555sis_newbuf(sc, c, m) 1556 struct sis_softc *sc; 1557 struct sis_desc *c; 1558 struct mbuf *m; 1559{ 1560 1561 if (c == NULL) 1562 return(EINVAL); 1563 1564 if (m == NULL) { 1565 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1566 if (m == NULL) 1567 return(ENOBUFS); 1568 } else 1569 m->m_data = m->m_ext.ext_buf; 1570 1571 c->sis_mbuf = m; 1572 c->sis_ctl = SIS_RXLEN; 1573 1574 bus_dmamap_create(sc->sis_tag, 0, &c->sis_map); 1575 bus_dmamap_load(sc->sis_tag, c->sis_map, 1576 mtod(m, void *), MCLBYTES, 1577 sis_dma_map_desc_ptr, c, 0); 1578 bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREWRITE); 1579 1580 return(0); 1581} 1582 1583/* 1584 * A frame has been uploaded: pass the resulting mbuf chain up to 1585 * the higher level protocols. 1586 */ 1587static void 1588sis_rxeof(sc) 1589 struct sis_softc *sc; 1590{ 1591 struct mbuf *m; 1592 struct ifnet *ifp; 1593 struct sis_desc *cur_rx; 1594 int i, total_len = 0; 1595 u_int32_t rxstat; 1596 1597 SIS_LOCK_ASSERT(sc); 1598 1599 ifp = &sc->arpcom.ac_if; 1600 i = sc->sis_cdata.sis_rx_prod; 1601 1602 while(SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) { 1603 1604#ifdef DEVICE_POLLING 1605 if (ifp->if_flags & IFF_POLLING) { 1606 if (sc->rxcycles <= 0) 1607 break; 1608 sc->rxcycles--; 1609 } 1610#endif /* DEVICE_POLLING */ 1611 cur_rx = &sc->sis_ldata.sis_rx_list[i]; 1612 rxstat = cur_rx->sis_rxstat; 1613 bus_dmamap_sync(sc->sis_tag, 1614 cur_rx->sis_map, BUS_DMASYNC_POSTWRITE); 1615 bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map); 1616 bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map); 1617 m = cur_rx->sis_mbuf; 1618 cur_rx->sis_mbuf = NULL; 1619 total_len = SIS_RXBYTES(cur_rx); 1620 SIS_INC(i, SIS_RX_LIST_CNT); 1621 1622 /* 1623 * If an error occurs, update stats, clear the 1624 * status word and leave the mbuf cluster in place: 1625 * it should simply get re-used next time this descriptor 1626 * comes up in the ring. 1627 */ 1628 if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 1629 ifp->if_ierrors++; 1630 if (rxstat & SIS_RXSTAT_COLL) 1631 ifp->if_collisions++; 1632 sis_newbuf(sc, cur_rx, m); 1633 continue; 1634 } 1635 1636 /* No errors; receive the packet. */ 1637#ifdef __i386__ 1638 /* 1639 * On the x86 we do not have alignment problems, so try to 1640 * allocate a new buffer for the receive ring, and pass up 1641 * the one where the packet is already, saving the expensive 1642 * copy done in m_devget(). 1643 * If we are on an architecture with alignment problems, or 1644 * if the allocation fails, then use m_devget and leave the 1645 * existing buffer in the receive ring. 1646 */ 1647 if (sis_newbuf(sc, cur_rx, NULL) == 0) 1648 m->m_pkthdr.len = m->m_len = total_len; 1649 else 1650#endif 1651 { 1652 struct mbuf *m0; 1653 m0 = m_devget(mtod(m, char *), total_len, 1654 ETHER_ALIGN, ifp, NULL); 1655 sis_newbuf(sc, cur_rx, m); 1656 if (m0 == NULL) { 1657 ifp->if_ierrors++; 1658 continue; 1659 } 1660 m = m0; 1661 } 1662 1663 ifp->if_ipackets++; 1664 m->m_pkthdr.rcvif = ifp; 1665 1666 SIS_UNLOCK(sc); 1667 (*ifp->if_input)(ifp, m); 1668 SIS_LOCK(sc); 1669 } 1670 1671 sc->sis_cdata.sis_rx_prod = i; 1672 1673 return; 1674} 1675 1676static void 1677sis_rxeoc(sc) 1678 struct sis_softc *sc; 1679{ 1680 sis_rxeof(sc); 1681 sis_init(sc); 1682 return; 1683} 1684 1685/* 1686 * A frame was downloaded to the chip. It's safe for us to clean up 1687 * the list buffers. 1688 */ 1689 1690static void 1691sis_txeof(sc) 1692 struct sis_softc *sc; 1693{ 1694 struct ifnet *ifp; 1695 u_int32_t idx; 1696 1697 ifp = &sc->arpcom.ac_if; 1698 1699 /* 1700 * Go through our tx list and free mbufs for those 1701 * frames that have been transmitted. 1702 */ 1703 for (idx = sc->sis_cdata.sis_tx_cons; sc->sis_cdata.sis_tx_cnt > 0; 1704 sc->sis_cdata.sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) { 1705 struct sis_desc *cur_tx = &sc->sis_ldata.sis_tx_list[idx]; 1706 1707 if (SIS_OWNDESC(cur_tx)) 1708 break; 1709 1710 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) 1711 continue; 1712 1713 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 1714 ifp->if_oerrors++; 1715 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 1716 ifp->if_collisions++; 1717 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 1718 ifp->if_collisions++; 1719 } 1720 1721 ifp->if_collisions += 1722 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 1723 1724 ifp->if_opackets++; 1725 if (cur_tx->sis_mbuf != NULL) { 1726 m_freem(cur_tx->sis_mbuf); 1727 cur_tx->sis_mbuf = NULL; 1728 bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map); 1729 bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map); 1730 } 1731 } 1732 1733 if (idx != sc->sis_cdata.sis_tx_cons) { 1734 /* we freed up some buffers */ 1735 sc->sis_cdata.sis_tx_cons = idx; 1736 ifp->if_flags &= ~IFF_OACTIVE; 1737 } 1738 1739 ifp->if_timer = (sc->sis_cdata.sis_tx_cnt == 0) ? 0 : 5; 1740 1741 return; 1742} 1743 1744static void 1745sis_tick(xsc) 1746 void *xsc; 1747{ 1748 struct sis_softc *sc; 1749 struct mii_data *mii; 1750 struct ifnet *ifp; 1751 1752 sc = xsc; 1753 SIS_LOCK(sc); 1754 sc->in_tick = 1; 1755 ifp = &sc->arpcom.ac_if; 1756 1757 mii = device_get_softc(sc->sis_miibus); 1758 mii_tick(mii); 1759 1760 if (!sc->sis_link && mii->mii_media_status & IFM_ACTIVE && 1761 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1762 sc->sis_link++; 1763 if (ifp->if_snd.ifq_head != NULL) 1764 sis_start(ifp); 1765 } 1766 1767 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 1768 sc->in_tick = 0; 1769 SIS_UNLOCK(sc); 1770 1771 return; 1772} 1773 1774#ifdef DEVICE_POLLING 1775static poll_handler_t sis_poll; 1776 1777static void 1778sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1779{ 1780 struct sis_softc *sc = ifp->if_softc; 1781 1782 SIS_LOCK(sc); 1783 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1784 CSR_WRITE_4(sc, SIS_IER, 1); 1785 goto done; 1786 } 1787 1788 /* 1789 * On the sis, reading the status register also clears it. 1790 * So before returning to intr mode we must make sure that all 1791 * possible pending sources of interrupts have been served. 1792 * In practice this means run to completion the *eof routines, 1793 * and then call the interrupt routine 1794 */ 1795 sc->rxcycles = count; 1796 sis_rxeof(sc); 1797 sis_txeof(sc); 1798 if (ifp->if_snd.ifq_head != NULL) 1799 sis_start(ifp); 1800 1801 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1802 u_int32_t status; 1803 1804 /* Reading the ISR register clears all interrupts. */ 1805 status = CSR_READ_4(sc, SIS_ISR); 1806 1807 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 1808 sis_rxeoc(sc); 1809 1810 if (status & (SIS_ISR_RX_IDLE)) 1811 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1812 1813 if (status & SIS_ISR_SYSERR) { 1814 sis_reset(sc); 1815 sis_init(sc); 1816 } 1817 } 1818done: 1819 SIS_UNLOCK(sc); 1820 return; 1821} 1822#endif /* DEVICE_POLLING */ 1823 1824static void 1825sis_intr(arg) 1826 void *arg; 1827{ 1828 struct sis_softc *sc; 1829 struct ifnet *ifp; 1830 u_int32_t status; 1831 1832 sc = arg; 1833 ifp = &sc->arpcom.ac_if; 1834 1835 SIS_LOCK(sc); 1836#ifdef DEVICE_POLLING 1837 if (ifp->if_flags & IFF_POLLING) 1838 goto done; 1839 if (ether_poll_register(sis_poll, ifp)) { /* ok, disable interrupts */ 1840 CSR_WRITE_4(sc, SIS_IER, 0); 1841 goto done; 1842 } 1843#endif /* DEVICE_POLLING */ 1844 1845 /* Supress unwanted interrupts */ 1846 if (!(ifp->if_flags & IFF_UP)) { 1847 sis_stop(sc); 1848 goto done; 1849 } 1850 1851 /* Disable interrupts. */ 1852 CSR_WRITE_4(sc, SIS_IER, 0); 1853 1854 for (;;) { 1855 /* Reading the ISR register clears all interrupts. */ 1856 status = CSR_READ_4(sc, SIS_ISR); 1857 1858 if ((status & SIS_INTRS) == 0) 1859 break; 1860 1861 if (status & 1862 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | 1863 SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) ) 1864 sis_txeof(sc); 1865 1866 if (status & (SIS_ISR_RX_DESC_OK|SIS_ISR_RX_OK|SIS_ISR_RX_IDLE)) 1867 sis_rxeof(sc); 1868 1869 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW)) 1870 sis_rxeoc(sc); 1871 1872 if (status & (SIS_ISR_RX_IDLE)) 1873 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1874 1875 if (status & SIS_ISR_SYSERR) { 1876 sis_reset(sc); 1877 sis_init(sc); 1878 } 1879 } 1880 1881 /* Re-enable interrupts. */ 1882 CSR_WRITE_4(sc, SIS_IER, 1); 1883 1884 if (ifp->if_snd.ifq_head != NULL) 1885 sis_start(ifp); 1886done: 1887 SIS_UNLOCK(sc); 1888 1889 return; 1890} 1891 1892/* 1893 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1894 * pointers to the fragment pointers. 1895 */ 1896static int 1897sis_encap(sc, m_head, txidx) 1898 struct sis_softc *sc; 1899 struct mbuf **m_head; 1900 u_int32_t *txidx; 1901{ 1902 struct sis_desc *f = NULL; 1903 struct mbuf *m; 1904 int frag, cur, cnt = 0, chainlen = 0; 1905 1906 /* 1907 * If there's no way we can send any packets, return now. 1908 */ 1909 if (SIS_TX_LIST_CNT - sc->sis_cdata.sis_tx_cnt < 2) 1910 return (ENOBUFS); 1911 1912 /* 1913 * Count the number of frags in this chain to see if 1914 * we need to m_defrag. Since the descriptor list is shared 1915 * by all packets, we'll m_defrag long chains so that they 1916 * do not use up the entire list, even if they would fit. 1917 */ 1918 1919 for (m = *m_head; m != NULL; m = m->m_next) 1920 chainlen++; 1921 1922 if ((chainlen > SIS_TX_LIST_CNT / 4) || 1923 ((SIS_TX_LIST_CNT - (chainlen + sc->sis_cdata.sis_tx_cnt)) < 2)) { 1924 m = m_defrag(*m_head, M_DONTWAIT); 1925 if (m == NULL) 1926 return (ENOBUFS); 1927 *m_head = m; 1928 } 1929 1930 /* 1931 * Start packing the mbufs in this chain into 1932 * the fragment pointers. Stop when we run out 1933 * of fragments or hit the end of the mbuf chain. 1934 */ 1935 cur = frag = *txidx; 1936 1937 for (m = *m_head; m != NULL; m = m->m_next) { 1938 if (m->m_len != 0) { 1939 if ((SIS_TX_LIST_CNT - 1940 (sc->sis_cdata.sis_tx_cnt + cnt)) < 2) 1941 return(ENOBUFS); 1942 f = &sc->sis_ldata.sis_tx_list[frag]; 1943 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; 1944 bus_dmamap_create(sc->sis_tag, 0, &f->sis_map); 1945 bus_dmamap_load(sc->sis_tag, f->sis_map, 1946 mtod(m, void *), m->m_len, 1947 sis_dma_map_desc_ptr, f, 0); 1948 bus_dmamap_sync(sc->sis_tag, 1949 f->sis_map, BUS_DMASYNC_PREREAD); 1950 if (cnt != 0) 1951 f->sis_ctl |= SIS_CMDSTS_OWN; 1952 cur = frag; 1953 SIS_INC(frag, SIS_TX_LIST_CNT); 1954 cnt++; 1955 } 1956 } 1957 1958 if (m != NULL) 1959 return(ENOBUFS); 1960 1961 sc->sis_ldata.sis_tx_list[cur].sis_mbuf = *m_head; 1962 sc->sis_ldata.sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1963 sc->sis_ldata.sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1964 sc->sis_cdata.sis_tx_cnt += cnt; 1965 *txidx = frag; 1966 1967 return(0); 1968} 1969 1970/* 1971 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1972 * to the mbuf data regions directly in the transmit lists. We also save a 1973 * copy of the pointers since the transmit list fragment pointers are 1974 * physical addresses. 1975 */ 1976 1977static void 1978sis_start(ifp) 1979 struct ifnet *ifp; 1980{ 1981 struct sis_softc *sc; 1982 struct mbuf *m_head = NULL; 1983 u_int32_t idx; 1984 1985 sc = ifp->if_softc; 1986 SIS_LOCK(sc); 1987 1988 if (!sc->sis_link) { 1989 SIS_UNLOCK(sc); 1990 return; 1991 } 1992 1993 idx = sc->sis_cdata.sis_tx_prod; 1994 1995 if (ifp->if_flags & IFF_OACTIVE) { 1996 SIS_UNLOCK(sc); 1997 return; 1998 } 1999 2000 while(sc->sis_ldata.sis_tx_list[idx].sis_mbuf == NULL) { 2001 IF_DEQUEUE(&ifp->if_snd, m_head); 2002 if (m_head == NULL) 2003 break; 2004 2005 if (sis_encap(sc, &m_head, &idx)) { 2006 IF_PREPEND(&ifp->if_snd, m_head); 2007 ifp->if_flags |= IFF_OACTIVE; 2008 break; 2009 } 2010 2011 /* 2012 * If there's a BPF listener, bounce a copy of this frame 2013 * to him. 2014 */ 2015 BPF_MTAP(ifp, m_head); 2016 2017 } 2018 2019 /* Transmit */ 2020 sc->sis_cdata.sis_tx_prod = idx; 2021 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 2022 2023 /* 2024 * Set a timeout in case the chip goes out to lunch. 2025 */ 2026 ifp->if_timer = 5; 2027 2028 SIS_UNLOCK(sc); 2029 2030 return; 2031} 2032 2033static void 2034sis_init(xsc) 2035 void *xsc; 2036{ 2037 struct sis_softc *sc = xsc; 2038 struct ifnet *ifp = &sc->arpcom.ac_if; 2039 struct mii_data *mii; 2040 2041 SIS_LOCK(sc); 2042 2043 /* 2044 * Cancel pending I/O and free all RX/TX buffers. 2045 */ 2046 sis_stop(sc); 2047 2048#ifdef notyet 2049 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) { 2050 /* 2051 * Configure 400usec of interrupt holdoff. This is based 2052 * on emperical tests on a Soekris 4801. 2053 */ 2054 CSR_WRITE_4(sc, NS_IHR, 0x100 | 4); 2055 } 2056#endif 2057 2058 mii = device_get_softc(sc->sis_miibus); 2059 2060 /* Set MAC address */ 2061 if (sc->sis_type == SIS_TYPE_83815) { 2062 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 2063 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2064 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 2065 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 2066 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2067 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 2068 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 2069 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2070 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 2071 } else { 2072 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 2073 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2074 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 2075 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 2076 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2077 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 2078 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 2079 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2080 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 2081 } 2082 2083 /* Init circular RX list. */ 2084 if (sis_list_rx_init(sc) == ENOBUFS) { 2085 printf("sis%d: initialization failed: no " 2086 "memory for rx buffers\n", sc->sis_unit); 2087 sis_stop(sc); 2088 SIS_UNLOCK(sc); 2089 return; 2090 } 2091 2092 /* 2093 * Init tx descriptors. 2094 */ 2095 sis_list_tx_init(sc); 2096 2097 /* 2098 * For the NatSemi chip, we have to explicitly enable the 2099 * reception of ARP frames, as well as turn on the 'perfect 2100 * match' filter where we store the station address, otherwise 2101 * we won't receive unicasts meant for this host. 2102 */ 2103 if (sc->sis_type == SIS_TYPE_83815) { 2104 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 2105 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 2106 } 2107 2108 /* If we want promiscuous mode, set the allframes bit. */ 2109 if (ifp->if_flags & IFF_PROMISC) { 2110 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 2111 } else { 2112 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 2113 } 2114 2115 /* 2116 * Set the capture broadcast bit to capture broadcast frames. 2117 */ 2118 if (ifp->if_flags & IFF_BROADCAST) { 2119 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 2120 } else { 2121 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 2122 } 2123 2124 /* 2125 * Load the multicast filter. 2126 */ 2127 if (sc->sis_type == SIS_TYPE_83815) 2128 sis_setmulti_ns(sc); 2129 else 2130 sis_setmulti_sis(sc); 2131 2132 /* Turn the receive filter on */ 2133 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 2134 2135 /* 2136 * Load the address of the RX and TX lists. 2137 */ 2138 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_cdata.sis_rx_paddr); 2139 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_cdata.sis_tx_paddr); 2140 2141 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of 2142 * the PCI bus. When this bit is set, the Max DMA Burst Size 2143 * for TX/RX DMA should be no larger than 16 double words. 2144 */ 2145 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) { 2146 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); 2147 } else { 2148 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); 2149 } 2150 2151 2152 /* Accept Long Packets for VLAN support */ 2153 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 2154 2155 /* Set TX configuration */ 2156 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 2157 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 2158 } else { 2159 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 2160 } 2161 2162 /* Set full/half duplex mode. */ 2163 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 2164 SIS_SETBIT(sc, SIS_TX_CFG, 2165 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 2166 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 2167 } else { 2168 SIS_CLRBIT(sc, SIS_TX_CFG, 2169 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 2170 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 2171 } 2172 2173 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr < NS_SRR_16A && 2174 IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 2175 uint32_t reg; 2176 2177 /* 2178 * Some DP83815s experience problems when used with short 2179 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 2180 * sequence adjusts the DSP's signal attenuation to fix the 2181 * problem. 2182 */ 2183 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 2184 2185 reg = CSR_READ_4(sc, NS_PHY_DSPCFG); 2186 CSR_WRITE_4(sc, NS_PHY_DSPCFG, (reg & 0xfff) | 0x1000); 2187 DELAY(100); 2188 reg = CSR_READ_4(sc, NS_PHY_TDATA); 2189 if ((reg & 0x0080) == 0 || (reg & 0xff) >= 0xd8) { 2190 device_printf(sc->sis_self, "Applying short cable fix (reg=%x)\n", reg); 2191 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8); 2192 SIS_SETBIT(sc, NS_PHY_DSPCFG, 0x20); 2193 } 2194 CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 2195 } 2196 2197 /* 2198 * Enable interrupts. 2199 */ 2200 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 2201#ifdef DEVICE_POLLING 2202 /* 2203 * ... only enable interrupts if we are not polling, make sure 2204 * they are off otherwise. 2205 */ 2206 if (ifp->if_flags & IFF_POLLING) 2207 CSR_WRITE_4(sc, SIS_IER, 0); 2208 else 2209#endif /* DEVICE_POLLING */ 2210 CSR_WRITE_4(sc, SIS_IER, 1); 2211 2212 /* Enable receiver and transmitter. */ 2213 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2214 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 2215 2216#ifdef notdef 2217 mii_mediachg(mii); 2218#endif 2219 2220 /* 2221 * Page 75 of the DP83815 manual recommends the 2222 * following register settings "for optimum 2223 * performance." Note however that at least three 2224 * of the registers are listed as "reserved" in 2225 * the register map, so who knows what they do. 2226 */ 2227 if (sc->sis_type == SIS_TYPE_83815) { 2228 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 2229 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 2230 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 2231 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 2232 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 2233 } 2234 2235 ifp->if_flags |= IFF_RUNNING; 2236 ifp->if_flags &= ~IFF_OACTIVE; 2237 2238 if (!sc->in_tick) 2239 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 2240 2241 SIS_UNLOCK(sc); 2242 2243 return; 2244} 2245 2246/* 2247 * Set media options. 2248 */ 2249static int 2250sis_ifmedia_upd(ifp) 2251 struct ifnet *ifp; 2252{ 2253 struct sis_softc *sc; 2254 struct mii_data *mii; 2255 2256 sc = ifp->if_softc; 2257 2258 mii = device_get_softc(sc->sis_miibus); 2259 sc->sis_link = 0; 2260 if (mii->mii_instance) { 2261 struct mii_softc *miisc; 2262 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2263 mii_phy_reset(miisc); 2264 } 2265 mii_mediachg(mii); 2266 2267 return(0); 2268} 2269 2270/* 2271 * Report current media status. 2272 */ 2273static void 2274sis_ifmedia_sts(ifp, ifmr) 2275 struct ifnet *ifp; 2276 struct ifmediareq *ifmr; 2277{ 2278 struct sis_softc *sc; 2279 struct mii_data *mii; 2280 2281 sc = ifp->if_softc; 2282 2283 mii = device_get_softc(sc->sis_miibus); 2284 mii_pollstat(mii); 2285 ifmr->ifm_active = mii->mii_media_active; 2286 ifmr->ifm_status = mii->mii_media_status; 2287 2288 return; 2289} 2290 2291static int 2292sis_ioctl(ifp, command, data) 2293 struct ifnet *ifp; 2294 u_long command; 2295 caddr_t data; 2296{ 2297 struct sis_softc *sc = ifp->if_softc; 2298 struct ifreq *ifr = (struct ifreq *) data; 2299 struct mii_data *mii; 2300 int error = 0; 2301 2302 switch(command) { 2303 case SIOCSIFFLAGS: 2304 if (ifp->if_flags & IFF_UP) { 2305 sis_init(sc); 2306 } else { 2307 if (ifp->if_flags & IFF_RUNNING) 2308 sis_stop(sc); 2309 } 2310 error = 0; 2311 break; 2312 case SIOCADDMULTI: 2313 case SIOCDELMULTI: 2314 SIS_LOCK(sc); 2315 if (sc->sis_type == SIS_TYPE_83815) 2316 sis_setmulti_ns(sc); 2317 else 2318 sis_setmulti_sis(sc); 2319 SIS_UNLOCK(sc); 2320 error = 0; 2321 break; 2322 case SIOCGIFMEDIA: 2323 case SIOCSIFMEDIA: 2324 mii = device_get_softc(sc->sis_miibus); 2325 SIS_LOCK(sc); 2326 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2327 SIS_UNLOCK(sc); 2328 break; 2329 default: 2330 error = ether_ioctl(ifp, command, data); 2331 break; 2332 } 2333 2334 return(error); 2335} 2336 2337static void 2338sis_watchdog(ifp) 2339 struct ifnet *ifp; 2340{ 2341 struct sis_softc *sc; 2342 2343 sc = ifp->if_softc; 2344 2345 SIS_LOCK(sc); 2346 2347 ifp->if_oerrors++; 2348 printf("sis%d: watchdog timeout\n", sc->sis_unit); 2349 2350 sis_stop(sc); 2351 sis_reset(sc); 2352 sis_init(sc); 2353 2354 if (ifp->if_snd.ifq_head != NULL) 2355 sis_start(ifp); 2356 2357 SIS_UNLOCK(sc); 2358 2359 return; 2360} 2361 2362/* 2363 * Stop the adapter and free any mbufs allocated to the 2364 * RX and TX lists. 2365 */ 2366static void 2367sis_stop(sc) 2368 struct sis_softc *sc; 2369{ 2370 register int i; 2371 struct ifnet *ifp; 2372 2373 SIS_LOCK(sc); 2374 ifp = &sc->arpcom.ac_if; 2375 ifp->if_timer = 0; 2376 2377 callout_stop(&sc->sis_stat_ch); 2378 2379 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2380#ifdef DEVICE_POLLING 2381 ether_poll_deregister(ifp); 2382#endif 2383 CSR_WRITE_4(sc, SIS_IER, 0); 2384 CSR_WRITE_4(sc, SIS_IMR, 0); 2385 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2386 DELAY(1000); 2387 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 2388 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2389 2390 sc->sis_link = 0; 2391 2392 /* 2393 * Free data in the RX lists. 2394 */ 2395 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 2396 if (sc->sis_ldata.sis_rx_list[i].sis_mbuf != NULL) { 2397 bus_dmamap_unload(sc->sis_tag, 2398 sc->sis_ldata.sis_rx_list[i].sis_map); 2399 bus_dmamap_destroy(sc->sis_tag, 2400 sc->sis_ldata.sis_rx_list[i].sis_map); 2401 m_freem(sc->sis_ldata.sis_rx_list[i].sis_mbuf); 2402 sc->sis_ldata.sis_rx_list[i].sis_mbuf = NULL; 2403 } 2404 } 2405 bzero(sc->sis_ldata.sis_rx_list, 2406 sizeof(sc->sis_ldata.sis_rx_list)); 2407 2408 /* 2409 * Free the TX list buffers. 2410 */ 2411 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 2412 if (sc->sis_ldata.sis_tx_list[i].sis_mbuf != NULL) { 2413 bus_dmamap_unload(sc->sis_tag, 2414 sc->sis_ldata.sis_tx_list[i].sis_map); 2415 bus_dmamap_destroy(sc->sis_tag, 2416 sc->sis_ldata.sis_tx_list[i].sis_map); 2417 m_freem(sc->sis_ldata.sis_tx_list[i].sis_mbuf); 2418 sc->sis_ldata.sis_tx_list[i].sis_mbuf = NULL; 2419 } 2420 } 2421 2422 bzero(sc->sis_ldata.sis_tx_list, 2423 sizeof(sc->sis_ldata.sis_tx_list)); 2424 2425 SIS_UNLOCK(sc); 2426 2427 return; 2428} 2429 2430/* 2431 * Stop all chip I/O so that the kernel's probe routines don't 2432 * get confused by errant DMAs when rebooting. 2433 */ 2434static void 2435sis_shutdown(dev) 2436 device_t dev; 2437{ 2438 struct sis_softc *sc; 2439 2440 sc = device_get_softc(dev); 2441 SIS_LOCK(sc); 2442 sis_reset(sc); 2443 sis_stop(sc); 2444 SIS_UNLOCK(sc); 2445 2446 return; 2447} 2448