if_sis.c revision 119785
1274958Sdim/* 2274958Sdim * Copyright (c) 1997, 1998, 1999 3274958Sdim * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4274958Sdim * 5274958Sdim * Redistribution and use in source and binary forms, with or without 6274958Sdim * modification, are permitted provided that the following conditions 7274958Sdim * are met: 8274958Sdim * 1. Redistributions of source code must retain the above copyright 9274958Sdim * notice, this list of conditions and the following disclaimer. 10274958Sdim * 2. Redistributions in binary form must reproduce the above copyright 11274958Sdim * notice, this list of conditions and the following disclaimer in the 12274958Sdim * documentation and/or other materials provided with the distribution. 13280031Sdim * 3. All advertising materials mentioning features or use of this software 14296417Sdim * must display the following acknowledgement: 15274958Sdim * This product includes software developed by Bill Paul. 16274958Sdim * 4. Neither the name of the author nor the names of any co-contributors 17274958Sdim * may be used to endorse or promote products derived from this software 18274958Sdim * without specific prior written permission. 19274958Sdim * 20274958Sdim * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21274958Sdim * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22274958Sdim * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23274958Sdim * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24274958Sdim * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25314564Sdim * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26314564Sdim * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27274958Sdim * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28274958Sdim * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29327952Sdim * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30327952Sdim * THE POSSIBILITY OF SUCH DAMAGE. 31274958Sdim */ 32274958Sdim 33274958Sdim/* 34274958Sdim * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 35341825Sdim * available from http://www.sis.com.tw. 36280031Sdim * 37280031Sdim * This driver also supports the NatSemi DP83815. Datasheets are 38296417Sdim * available from http://www.national.com. 39280031Sdim * 40274958Sdim * Written by Bill Paul <wpaul@ee.columbia.edu> 41274958Sdim * Electrical Engineering Department 42274958Sdim * Columbia University, New York City 43274958Sdim */ 44 45/* 46 * The SiS 900 is a fairly simple chip. It uses bus master DMA with 47 * simple TX and RX descriptors of 3 longwords in size. The receiver 48 * has a single perfect filter entry for the station address and a 49 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 50 * transceiver while the 7016 requires an external transceiver chip. 51 * Both chips offer the standard bit-bang MII interface as well as 52 * an enchanced PHY interface which simplifies accessing MII registers. 53 * 54 * The only downside to this chipset is that RX descriptors must be 55 * longword aligned. 56 */ 57 58#include <sys/cdefs.h> 59__FBSDID("$FreeBSD: head/sys/pci/if_sis.c 119785 2003-09-05 22:33:44Z sam $"); 60 61#include <sys/param.h> 62#include <sys/systm.h> 63#include <sys/sockio.h> 64#include <sys/mbuf.h> 65#include <sys/malloc.h> 66#include <sys/kernel.h> 67#include <sys/socket.h> 68#include <sys/sysctl.h> 69 70#include <net/if.h> 71#include <net/if_arp.h> 72#include <net/ethernet.h> 73#include <net/if_dl.h> 74#include <net/if_media.h> 75#include <net/if_types.h> 76#include <net/if_vlan_var.h> 77 78#include <net/bpf.h> 79 80#include <machine/bus_pio.h> 81#include <machine/bus_memio.h> 82#include <machine/bus.h> 83#include <machine/resource.h> 84#include <sys/bus.h> 85#include <sys/rman.h> 86 87#include <dev/mii/mii.h> 88#include <dev/mii/miivar.h> 89 90#include <dev/pci/pcireg.h> 91#include <dev/pci/pcivar.h> 92 93#define SIS_USEIOSPACE 94 95#include <pci/if_sisreg.h> 96 97MODULE_DEPEND(sis, pci, 1, 1, 1); 98MODULE_DEPEND(sis, ether, 1, 1, 1); 99MODULE_DEPEND(sis, miibus, 1, 1, 1); 100 101/* "controller miibus0" required. See GENERIC if you get errors here. */ 102#include "miibus_if.h" 103 104/* 105 * Various supported device vendors/types and their names. 106 */ 107static struct sis_type sis_devs[] = { 108 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 109 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 110 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" }, 111 { 0, 0, NULL } 112}; 113 114static int sis_probe (device_t); 115static int sis_attach (device_t); 116static int sis_detach (device_t); 117 118static int sis_newbuf (struct sis_softc *, 119 struct sis_desc *, struct mbuf *); 120static int sis_encap (struct sis_softc *, 121 struct mbuf *, u_int32_t *); 122static void sis_rxeof (struct sis_softc *); 123static void sis_rxeoc (struct sis_softc *); 124static void sis_txeof (struct sis_softc *); 125static void sis_intr (void *); 126static void sis_tick (void *); 127static void sis_start (struct ifnet *); 128static int sis_ioctl (struct ifnet *, u_long, caddr_t); 129static void sis_init (void *); 130static void sis_stop (struct sis_softc *); 131static void sis_watchdog (struct ifnet *); 132static void sis_shutdown (device_t); 133static int sis_ifmedia_upd (struct ifnet *); 134static void sis_ifmedia_sts (struct ifnet *, struct ifmediareq *); 135 136static u_int16_t sis_reverse (u_int16_t); 137static void sis_delay (struct sis_softc *); 138static void sis_eeprom_idle (struct sis_softc *); 139static void sis_eeprom_putbyte (struct sis_softc *, int); 140static void sis_eeprom_getword (struct sis_softc *, int, u_int16_t *); 141static void sis_read_eeprom (struct sis_softc *, caddr_t, int, int, int); 142#ifdef __i386__ 143static void sis_read_cmos (struct sis_softc *, device_t, caddr_t, 144 int, int); 145static void sis_read_mac (struct sis_softc *, device_t, caddr_t); 146static device_t sis_find_bridge (device_t); 147#endif 148 149static void sis_mii_sync (struct sis_softc *); 150static void sis_mii_send (struct sis_softc *, u_int32_t, int); 151static int sis_mii_readreg (struct sis_softc *, struct sis_mii_frame *); 152static int sis_mii_writereg (struct sis_softc *, struct sis_mii_frame *); 153static int sis_miibus_readreg (device_t, int, int); 154static int sis_miibus_writereg (device_t, int, int, int); 155static void sis_miibus_statchg (device_t); 156 157static void sis_setmulti_sis (struct sis_softc *); 158static void sis_setmulti_ns (struct sis_softc *); 159static u_int32_t sis_crc (struct sis_softc *, caddr_t); 160static void sis_reset (struct sis_softc *); 161static int sis_list_rx_init (struct sis_softc *); 162static int sis_list_tx_init (struct sis_softc *); 163 164static void sis_dma_map_desc_ptr (void *, bus_dma_segment_t *, int, int); 165static void sis_dma_map_desc_next (void *, bus_dma_segment_t *, int, int); 166static void sis_dma_map_ring (void *, bus_dma_segment_t *, int, int); 167#ifdef SIS_USEIOSPACE 168#define SIS_RES SYS_RES_IOPORT 169#define SIS_RID SIS_PCI_LOIO 170#else 171#define SIS_RES SYS_RES_MEMORY 172#define SIS_RID SIS_PCI_LOMEM 173#endif 174 175static device_method_t sis_methods[] = { 176 /* Device interface */ 177 DEVMETHOD(device_probe, sis_probe), 178 DEVMETHOD(device_attach, sis_attach), 179 DEVMETHOD(device_detach, sis_detach), 180 DEVMETHOD(device_shutdown, sis_shutdown), 181 182 /* bus interface */ 183 DEVMETHOD(bus_print_child, bus_generic_print_child), 184 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 185 186 /* MII interface */ 187 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 188 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 189 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 190 191 { 0, 0 } 192}; 193 194static driver_t sis_driver = { 195 "sis", 196 sis_methods, 197 sizeof(struct sis_softc) 198}; 199 200static devclass_t sis_devclass; 201 202DRIVER_MODULE(sis, pci, sis_driver, sis_devclass, 0, 0); 203DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 204 205#define SIS_SETBIT(sc, reg, x) \ 206 CSR_WRITE_4(sc, reg, \ 207 CSR_READ_4(sc, reg) | (x)) 208 209#define SIS_CLRBIT(sc, reg, x) \ 210 CSR_WRITE_4(sc, reg, \ 211 CSR_READ_4(sc, reg) & ~(x)) 212 213#define SIO_SET(x) \ 214 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 215 216#define SIO_CLR(x) \ 217 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 218 219static void 220sis_dma_map_desc_next(arg, segs, nseg, error) 221 void *arg; 222 bus_dma_segment_t *segs; 223 int nseg, error; 224{ 225 struct sis_desc *r; 226 227 r = arg; 228 r->sis_next = segs->ds_addr; 229 230 return; 231} 232 233static void 234sis_dma_map_desc_ptr(arg, segs, nseg, error) 235 void *arg; 236 bus_dma_segment_t *segs; 237 int nseg, error; 238{ 239 struct sis_desc *r; 240 241 r = arg; 242 r->sis_ptr = segs->ds_addr; 243 244 return; 245} 246 247static void 248sis_dma_map_ring(arg, segs, nseg, error) 249 void *arg; 250 bus_dma_segment_t *segs; 251 int nseg, error; 252{ 253 u_int32_t *p; 254 255 p = arg; 256 *p = segs->ds_addr; 257 258 return; 259} 260 261/* 262 * Routine to reverse the bits in a word. Stolen almost 263 * verbatim from /usr/games/fortune. 264 */ 265static u_int16_t 266sis_reverse(n) 267 u_int16_t n; 268{ 269 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 270 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 271 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 272 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 273 274 return(n); 275} 276 277static void 278sis_delay(sc) 279 struct sis_softc *sc; 280{ 281 int idx; 282 283 for (idx = (300 / 33) + 1; idx > 0; idx--) 284 CSR_READ_4(sc, SIS_CSR); 285 286 return; 287} 288 289static void 290sis_eeprom_idle(sc) 291 struct sis_softc *sc; 292{ 293 register int i; 294 295 SIO_SET(SIS_EECTL_CSEL); 296 sis_delay(sc); 297 SIO_SET(SIS_EECTL_CLK); 298 sis_delay(sc); 299 300 for (i = 0; i < 25; i++) { 301 SIO_CLR(SIS_EECTL_CLK); 302 sis_delay(sc); 303 SIO_SET(SIS_EECTL_CLK); 304 sis_delay(sc); 305 } 306 307 SIO_CLR(SIS_EECTL_CLK); 308 sis_delay(sc); 309 SIO_CLR(SIS_EECTL_CSEL); 310 sis_delay(sc); 311 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 312 313 return; 314} 315 316/* 317 * Send a read command and address to the EEPROM, check for ACK. 318 */ 319static void 320sis_eeprom_putbyte(sc, addr) 321 struct sis_softc *sc; 322 int addr; 323{ 324 register int d, i; 325 326 d = addr | SIS_EECMD_READ; 327 328 /* 329 * Feed in each bit and stobe the clock. 330 */ 331 for (i = 0x400; i; i >>= 1) { 332 if (d & i) { 333 SIO_SET(SIS_EECTL_DIN); 334 } else { 335 SIO_CLR(SIS_EECTL_DIN); 336 } 337 sis_delay(sc); 338 SIO_SET(SIS_EECTL_CLK); 339 sis_delay(sc); 340 SIO_CLR(SIS_EECTL_CLK); 341 sis_delay(sc); 342 } 343 344 return; 345} 346 347/* 348 * Read a word of data stored in the EEPROM at address 'addr.' 349 */ 350static void 351sis_eeprom_getword(sc, addr, dest) 352 struct sis_softc *sc; 353 int addr; 354 u_int16_t *dest; 355{ 356 register int i; 357 u_int16_t word = 0; 358 359 /* Force EEPROM to idle state. */ 360 sis_eeprom_idle(sc); 361 362 /* Enter EEPROM access mode. */ 363 sis_delay(sc); 364 SIO_CLR(SIS_EECTL_CLK); 365 sis_delay(sc); 366 SIO_SET(SIS_EECTL_CSEL); 367 sis_delay(sc); 368 369 /* 370 * Send address of word we want to read. 371 */ 372 sis_eeprom_putbyte(sc, addr); 373 374 /* 375 * Start reading bits from EEPROM. 376 */ 377 for (i = 0x8000; i; i >>= 1) { 378 SIO_SET(SIS_EECTL_CLK); 379 sis_delay(sc); 380 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 381 word |= i; 382 sis_delay(sc); 383 SIO_CLR(SIS_EECTL_CLK); 384 sis_delay(sc); 385 } 386 387 /* Turn off EEPROM access mode. */ 388 sis_eeprom_idle(sc); 389 390 *dest = word; 391 392 return; 393} 394 395/* 396 * Read a sequence of words from the EEPROM. 397 */ 398static void 399sis_read_eeprom(sc, dest, off, cnt, swap) 400 struct sis_softc *sc; 401 caddr_t dest; 402 int off; 403 int cnt; 404 int swap; 405{ 406 int i; 407 u_int16_t word = 0, *ptr; 408 409 for (i = 0; i < cnt; i++) { 410 sis_eeprom_getword(sc, off + i, &word); 411 ptr = (u_int16_t *)(dest + (i * 2)); 412 if (swap) 413 *ptr = ntohs(word); 414 else 415 *ptr = word; 416 } 417 418 return; 419} 420 421#ifdef __i386__ 422static device_t 423sis_find_bridge(dev) 424 device_t dev; 425{ 426 devclass_t pci_devclass; 427 device_t *pci_devices; 428 int pci_count = 0; 429 device_t *pci_children; 430 int pci_childcount = 0; 431 device_t *busp, *childp; 432 device_t child = NULL; 433 int i, j; 434 435 if ((pci_devclass = devclass_find("pci")) == NULL) 436 return(NULL); 437 438 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 439 440 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 441 pci_childcount = 0; 442 device_get_children(*busp, &pci_children, &pci_childcount); 443 for (j = 0, childp = pci_children; 444 j < pci_childcount; j++, childp++) { 445 if (pci_get_vendor(*childp) == SIS_VENDORID && 446 pci_get_device(*childp) == 0x0008) { 447 child = *childp; 448 goto done; 449 } 450 } 451 } 452 453done: 454 free(pci_devices, M_TEMP); 455 free(pci_children, M_TEMP); 456 return(child); 457} 458 459static void 460sis_read_cmos(sc, dev, dest, off, cnt) 461 struct sis_softc *sc; 462 device_t dev; 463 caddr_t dest; 464 int off; 465 int cnt; 466{ 467 device_t bridge; 468 u_int8_t reg; 469 int i; 470 bus_space_tag_t btag; 471 472 bridge = sis_find_bridge(dev); 473 if (bridge == NULL) 474 return; 475 reg = pci_read_config(bridge, 0x48, 1); 476 pci_write_config(bridge, 0x48, reg|0x40, 1); 477 478 /* XXX */ 479 btag = I386_BUS_SPACE_IO; 480 481 for (i = 0; i < cnt; i++) { 482 bus_space_write_1(btag, 0x0, 0x70, i + off); 483 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 484 } 485 486 pci_write_config(bridge, 0x48, reg & ~0x40, 1); 487 return; 488} 489 490static void 491sis_read_mac(sc, dev, dest) 492 struct sis_softc *sc; 493 device_t dev; 494 caddr_t dest; 495{ 496 u_int32_t filtsave, csrsave; 497 498 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 499 csrsave = CSR_READ_4(sc, SIS_CSR); 500 501 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 502 CSR_WRITE_4(sc, SIS_CSR, 0); 503 504 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 505 506 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 507 ((u_int16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 508 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 509 ((u_int16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 510 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 511 ((u_int16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 512 513 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 514 CSR_WRITE_4(sc, SIS_CSR, csrsave); 515 return; 516} 517#endif 518 519/* 520 * Sync the PHYs by setting data bit and strobing the clock 32 times. 521 */ 522static void sis_mii_sync(sc) 523 struct sis_softc *sc; 524{ 525 register int i; 526 527 SIO_SET(SIS_MII_DIR|SIS_MII_DATA); 528 529 for (i = 0; i < 32; i++) { 530 SIO_SET(SIS_MII_CLK); 531 DELAY(1); 532 SIO_CLR(SIS_MII_CLK); 533 DELAY(1); 534 } 535 536 return; 537} 538 539/* 540 * Clock a series of bits through the MII. 541 */ 542static void sis_mii_send(sc, bits, cnt) 543 struct sis_softc *sc; 544 u_int32_t bits; 545 int cnt; 546{ 547 int i; 548 549 SIO_CLR(SIS_MII_CLK); 550 551 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 552 if (bits & i) { 553 SIO_SET(SIS_MII_DATA); 554 } else { 555 SIO_CLR(SIS_MII_DATA); 556 } 557 DELAY(1); 558 SIO_CLR(SIS_MII_CLK); 559 DELAY(1); 560 SIO_SET(SIS_MII_CLK); 561 } 562} 563 564/* 565 * Read an PHY register through the MII. 566 */ 567static int sis_mii_readreg(sc, frame) 568 struct sis_softc *sc; 569 struct sis_mii_frame *frame; 570 571{ 572 int i, ack, s; 573 574 s = splimp(); 575 576 /* 577 * Set up frame for RX. 578 */ 579 frame->mii_stdelim = SIS_MII_STARTDELIM; 580 frame->mii_opcode = SIS_MII_READOP; 581 frame->mii_turnaround = 0; 582 frame->mii_data = 0; 583 584 /* 585 * Turn on data xmit. 586 */ 587 SIO_SET(SIS_MII_DIR); 588 589 sis_mii_sync(sc); 590 591 /* 592 * Send command/address info. 593 */ 594 sis_mii_send(sc, frame->mii_stdelim, 2); 595 sis_mii_send(sc, frame->mii_opcode, 2); 596 sis_mii_send(sc, frame->mii_phyaddr, 5); 597 sis_mii_send(sc, frame->mii_regaddr, 5); 598 599 /* Idle bit */ 600 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA)); 601 DELAY(1); 602 SIO_SET(SIS_MII_CLK); 603 DELAY(1); 604 605 /* Turn off xmit. */ 606 SIO_CLR(SIS_MII_DIR); 607 608 /* Check for ack */ 609 SIO_CLR(SIS_MII_CLK); 610 DELAY(1); 611 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA; 612 SIO_SET(SIS_MII_CLK); 613 DELAY(1); 614 615 /* 616 * Now try reading data bits. If the ack failed, we still 617 * need to clock through 16 cycles to keep the PHY(s) in sync. 618 */ 619 if (ack) { 620 for(i = 0; i < 16; i++) { 621 SIO_CLR(SIS_MII_CLK); 622 DELAY(1); 623 SIO_SET(SIS_MII_CLK); 624 DELAY(1); 625 } 626 goto fail; 627 } 628 629 for (i = 0x8000; i; i >>= 1) { 630 SIO_CLR(SIS_MII_CLK); 631 DELAY(1); 632 if (!ack) { 633 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA) 634 frame->mii_data |= i; 635 DELAY(1); 636 } 637 SIO_SET(SIS_MII_CLK); 638 DELAY(1); 639 } 640 641fail: 642 643 SIO_CLR(SIS_MII_CLK); 644 DELAY(1); 645 SIO_SET(SIS_MII_CLK); 646 DELAY(1); 647 648 splx(s); 649 650 if (ack) 651 return(1); 652 return(0); 653} 654 655/* 656 * Write to a PHY register through the MII. 657 */ 658static int sis_mii_writereg(sc, frame) 659 struct sis_softc *sc; 660 struct sis_mii_frame *frame; 661 662{ 663 int s; 664 665 s = splimp(); 666 /* 667 * Set up frame for TX. 668 */ 669 670 frame->mii_stdelim = SIS_MII_STARTDELIM; 671 frame->mii_opcode = SIS_MII_WRITEOP; 672 frame->mii_turnaround = SIS_MII_TURNAROUND; 673 674 /* 675 * Turn on data output. 676 */ 677 SIO_SET(SIS_MII_DIR); 678 679 sis_mii_sync(sc); 680 681 sis_mii_send(sc, frame->mii_stdelim, 2); 682 sis_mii_send(sc, frame->mii_opcode, 2); 683 sis_mii_send(sc, frame->mii_phyaddr, 5); 684 sis_mii_send(sc, frame->mii_regaddr, 5); 685 sis_mii_send(sc, frame->mii_turnaround, 2); 686 sis_mii_send(sc, frame->mii_data, 16); 687 688 /* Idle bit. */ 689 SIO_SET(SIS_MII_CLK); 690 DELAY(1); 691 SIO_CLR(SIS_MII_CLK); 692 DELAY(1); 693 694 /* 695 * Turn off xmit. 696 */ 697 SIO_CLR(SIS_MII_DIR); 698 699 splx(s); 700 701 return(0); 702} 703 704static int 705sis_miibus_readreg(dev, phy, reg) 706 device_t dev; 707 int phy, reg; 708{ 709 struct sis_softc *sc; 710 struct sis_mii_frame frame; 711 712 sc = device_get_softc(dev); 713 714 if (sc->sis_type == SIS_TYPE_83815) { 715 if (phy != 0) 716 return(0); 717 /* 718 * The NatSemi chip can take a while after 719 * a reset to come ready, during which the BMSR 720 * returns a value of 0. This is *never* supposed 721 * to happen: some of the BMSR bits are meant to 722 * be hardwired in the on position, and this can 723 * confuse the miibus code a bit during the probe 724 * and attach phase. So we make an effort to check 725 * for this condition and wait for it to clear. 726 */ 727 if (!CSR_READ_4(sc, NS_BMSR)) 728 DELAY(1000); 729 return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 730 } 731 732 /* 733 * Chipsets < SIS_635 seem not to be able to read/write 734 * through mdio. Use the enhanced PHY access register 735 * again for them. 736 */ 737 if (sc->sis_type == SIS_TYPE_900 && 738 sc->sis_rev < SIS_REV_635) { 739 int i, val = 0; 740 741 if (phy != 0) 742 return(0); 743 744 CSR_WRITE_4(sc, SIS_PHYCTL, 745 (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 746 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 747 748 for (i = 0; i < SIS_TIMEOUT; i++) { 749 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 750 break; 751 } 752 753 if (i == SIS_TIMEOUT) { 754 printf("sis%d: PHY failed to come ready\n", 755 sc->sis_unit); 756 return(0); 757 } 758 759 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 760 761 if (val == 0xFFFF) 762 return(0); 763 764 return(val); 765 } else { 766 bzero((char *)&frame, sizeof(frame)); 767 768 frame.mii_phyaddr = phy; 769 frame.mii_regaddr = reg; 770 sis_mii_readreg(sc, &frame); 771 772 return(frame.mii_data); 773 } 774} 775 776static int 777sis_miibus_writereg(dev, phy, reg, data) 778 device_t dev; 779 int phy, reg, data; 780{ 781 struct sis_softc *sc; 782 struct sis_mii_frame frame; 783 784 sc = device_get_softc(dev); 785 786 if (sc->sis_type == SIS_TYPE_83815) { 787 if (phy != 0) 788 return(0); 789 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 790 return(0); 791 } 792 793 /* 794 * Chipsets < SIS_635 seem not to be able to read/write 795 * through mdio. Use the enhanced PHY access register 796 * again for them. 797 */ 798 if (sc->sis_type == SIS_TYPE_900 && 799 sc->sis_rev < SIS_REV_635) { 800 int i; 801 802 if (phy != 0) 803 return(0); 804 805 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 806 (reg << 6) | SIS_PHYOP_WRITE); 807 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 808 809 for (i = 0; i < SIS_TIMEOUT; i++) { 810 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 811 break; 812 } 813 814 if (i == SIS_TIMEOUT) 815 printf("sis%d: PHY failed to come ready\n", 816 sc->sis_unit); 817 } else { 818 bzero((char *)&frame, sizeof(frame)); 819 820 frame.mii_phyaddr = phy; 821 frame.mii_regaddr = reg; 822 frame.mii_data = data; 823 sis_mii_writereg(sc, &frame); 824 } 825 return(0); 826} 827 828static void 829sis_miibus_statchg(dev) 830 device_t dev; 831{ 832 struct sis_softc *sc; 833 834 sc = device_get_softc(dev); 835 sis_init(sc); 836 837 return; 838} 839 840static u_int32_t 841sis_crc(sc, addr) 842 struct sis_softc *sc; 843 caddr_t addr; 844{ 845 u_int32_t crc, carry; 846 int i, j; 847 u_int8_t c; 848 849 /* Compute CRC for the address value. */ 850 crc = 0xFFFFFFFF; /* initial value */ 851 852 for (i = 0; i < 6; i++) { 853 c = *(addr + i); 854 for (j = 0; j < 8; j++) { 855 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 856 crc <<= 1; 857 c >>= 1; 858 if (carry) 859 crc = (crc ^ 0x04c11db6) | carry; 860 } 861 } 862 863 /* 864 * return the filter bit position 865 * 866 * The NatSemi chip has a 512-bit filter, which is 867 * different than the SiS, so we special-case it. 868 */ 869 if (sc->sis_type == SIS_TYPE_83815) 870 return (crc >> 23); 871 else if (sc->sis_rev >= SIS_REV_635 || 872 sc->sis_rev == SIS_REV_900B) 873 return (crc >> 24); 874 else 875 return (crc >> 25); 876} 877 878static void 879sis_setmulti_ns(sc) 880 struct sis_softc *sc; 881{ 882 struct ifnet *ifp; 883 struct ifmultiaddr *ifma; 884 u_int32_t h = 0, i, filtsave; 885 int bit, index; 886 887 ifp = &sc->arpcom.ac_if; 888 889 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 890 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 891 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 892 return; 893 } 894 895 /* 896 * We have to explicitly enable the multicast hash table 897 * on the NatSemi chip if we want to use it, which we do. 898 */ 899 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 900 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 901 902 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 903 904 /* first, zot all the existing hash bits */ 905 for (i = 0; i < 32; i++) { 906 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 907 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 908 } 909 910 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 911 if (ifma->ifma_addr->sa_family != AF_LINK) 912 continue; 913 h = sis_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 914 index = h >> 3; 915 bit = h & 0x1F; 916 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 917 if (bit > 0xF) 918 bit -= 0x10; 919 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 920 } 921 922 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 923 924 return; 925} 926 927static void 928sis_setmulti_sis(sc) 929 struct sis_softc *sc; 930{ 931 struct ifnet *ifp; 932 struct ifmultiaddr *ifma; 933 u_int32_t h, i, n, ctl; 934 u_int16_t hashes[16]; 935 936 ifp = &sc->arpcom.ac_if; 937 938 /* hash table size */ 939 if (sc->sis_rev >= SIS_REV_635 || 940 sc->sis_rev == SIS_REV_900B) 941 n = 16; 942 else 943 n = 8; 944 945 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE; 946 947 if (ifp->if_flags & IFF_BROADCAST) 948 ctl |= SIS_RXFILTCTL_BROAD; 949 950 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 951 ctl |= SIS_RXFILTCTL_ALLMULTI; 952 if (ifp->if_flags & IFF_PROMISC) 953 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS; 954 for (i = 0; i < n; i++) 955 hashes[i] = ~0; 956 } else { 957 for (i = 0; i < n; i++) 958 hashes[i] = 0; 959 i = 0; 960 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 961 if (ifma->ifma_addr->sa_family != AF_LINK) 962 continue; 963 h = sis_crc(sc, 964 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 965 hashes[h >> 4] |= 1 << (h & 0xf); 966 i++; 967 } 968 if (i > n) { 969 ctl |= SIS_RXFILTCTL_ALLMULTI; 970 for (i = 0; i < n; i++) 971 hashes[i] = ~0; 972 } 973 } 974 975 for (i = 0; i < n; i++) { 976 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); 977 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); 978 } 979 980 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl); 981} 982 983static void 984sis_reset(sc) 985 struct sis_softc *sc; 986{ 987 register int i; 988 989 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 990 991 for (i = 0; i < SIS_TIMEOUT; i++) { 992 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 993 break; 994 } 995 996 if (i == SIS_TIMEOUT) 997 printf("sis%d: reset never completed\n", sc->sis_unit); 998 999 /* Wait a little while for the chip to get its brains in order. */ 1000 DELAY(1000); 1001 1002 /* 1003 * If this is a NetSemi chip, make sure to clear 1004 * PME mode. 1005 */ 1006 if (sc->sis_type == SIS_TYPE_83815) { 1007 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 1008 CSR_WRITE_4(sc, NS_CLKRUN, 0); 1009 } 1010 1011 return; 1012} 1013 1014/* 1015 * Probe for an SiS chip. Check the PCI vendor and device 1016 * IDs against our list and return a device name if we find a match. 1017 */ 1018static int 1019sis_probe(dev) 1020 device_t dev; 1021{ 1022 struct sis_type *t; 1023 1024 t = sis_devs; 1025 1026 while(t->sis_name != NULL) { 1027 if ((pci_get_vendor(dev) == t->sis_vid) && 1028 (pci_get_device(dev) == t->sis_did)) { 1029 device_set_desc(dev, t->sis_name); 1030 return(0); 1031 } 1032 t++; 1033 } 1034 1035 return(ENXIO); 1036} 1037 1038/* 1039 * Attach the interface. Allocate softc structures, do ifmedia 1040 * setup and ethernet/BPF attach. 1041 */ 1042static int 1043sis_attach(dev) 1044 device_t dev; 1045{ 1046 u_char eaddr[ETHER_ADDR_LEN]; 1047 struct sis_softc *sc; 1048 struct ifnet *ifp; 1049 int unit, error = 0, rid, waittime = 0; 1050 1051 waittime = 0; 1052 sc = device_get_softc(dev); 1053 unit = device_get_unit(dev); 1054 1055 sc->sis_self = dev; 1056 1057 mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1058 MTX_DEF | MTX_RECURSE); 1059 1060 if (pci_get_device(dev) == SIS_DEVICEID_900) 1061 sc->sis_type = SIS_TYPE_900; 1062 if (pci_get_device(dev) == SIS_DEVICEID_7016) 1063 sc->sis_type = SIS_TYPE_7016; 1064 if (pci_get_vendor(dev) == NS_VENDORID) 1065 sc->sis_type = SIS_TYPE_83815; 1066 1067 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 1068#ifndef BURN_BRIDGES 1069 /* 1070 * Handle power management nonsense. 1071 */ 1072 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1073 u_int32_t iobase, membase, irq; 1074 1075 /* Save important PCI config data. */ 1076 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4); 1077 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4); 1078 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4); 1079 1080 /* Reset the power state. */ 1081 printf("sis%d: chip is in D%d power mode " 1082 "-- setting to D0\n", unit, 1083 pci_get_powerstate(dev)); 1084 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1085 1086 /* Restore PCI config data. */ 1087 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4); 1088 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4); 1089 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4); 1090 } 1091#endif 1092 /* 1093 * Map control/status registers. 1094 */ 1095 pci_enable_busmaster(dev); 1096 1097 rid = SIS_RID; 1098 sc->sis_res = bus_alloc_resource(dev, SIS_RES, &rid, 1099 0, ~0, 1, RF_ACTIVE); 1100 1101 if (sc->sis_res == NULL) { 1102 printf("sis%d: couldn't map ports/memory\n", unit); 1103 error = ENXIO; 1104 goto fail; 1105 } 1106 1107 sc->sis_btag = rman_get_bustag(sc->sis_res); 1108 sc->sis_bhandle = rman_get_bushandle(sc->sis_res); 1109 1110 /* Allocate interrupt */ 1111 rid = 0; 1112 sc->sis_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1113 RF_SHAREABLE | RF_ACTIVE); 1114 1115 if (sc->sis_irq == NULL) { 1116 printf("sis%d: couldn't map interrupt\n", unit); 1117 error = ENXIO; 1118 goto fail; 1119 } 1120 1121 /* Reset the adapter. */ 1122 sis_reset(sc); 1123 1124 if (sc->sis_type == SIS_TYPE_900 && 1125 (sc->sis_rev == SIS_REV_635 || 1126 sc->sis_rev == SIS_REV_900B)) { 1127 SIO_SET(SIS_CFG_RND_CNT); 1128 SIO_SET(SIS_CFG_PERR_DETECT); 1129 } 1130 1131 /* 1132 * Get station address from the EEPROM. 1133 */ 1134 switch (pci_get_vendor(dev)) { 1135 case NS_VENDORID: 1136 sc->sis_srr = CSR_READ_4(sc, NS_SRR); 1137 1138 /* We can't update the device description, so spew */ 1139 if (sc->sis_srr == NS_SRR_15C) 1140 device_printf(dev, "Silicon Revision: DP83815C\n"); 1141 else if (sc->sis_srr == NS_SRR_15D) 1142 device_printf(dev, "Silicon Revision: DP83815D\n"); 1143 else if (sc->sis_srr == NS_SRR_16A) 1144 device_printf(dev, "Silicon Revision: DP83816A\n"); 1145 else 1146 device_printf(dev, "Silicon Revision %x\n", sc->sis_srr); 1147 1148 /* 1149 * Reading the MAC address out of the EEPROM on 1150 * the NatSemi chip takes a bit more work than 1151 * you'd expect. The address spans 4 16-bit words, 1152 * with the first word containing only a single bit. 1153 * You have to shift everything over one bit to 1154 * get it aligned properly. Also, the bits are 1155 * stored backwards (the LSB is really the MSB, 1156 * and so on) so you have to reverse them in order 1157 * to get the MAC address into the form we want. 1158 * Why? Who the hell knows. 1159 */ 1160 { 1161 u_int16_t tmp[4]; 1162 1163 sis_read_eeprom(sc, (caddr_t)&tmp, 1164 NS_EE_NODEADDR, 4, 0); 1165 1166 /* Shift everything over one bit. */ 1167 tmp[3] = tmp[3] >> 1; 1168 tmp[3] |= tmp[2] << 15; 1169 tmp[2] = tmp[2] >> 1; 1170 tmp[2] |= tmp[1] << 15; 1171 tmp[1] = tmp[1] >> 1; 1172 tmp[1] |= tmp[0] << 15; 1173 1174 /* Now reverse all the bits. */ 1175 tmp[3] = sis_reverse(tmp[3]); 1176 tmp[2] = sis_reverse(tmp[2]); 1177 tmp[1] = sis_reverse(tmp[1]); 1178 1179 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); 1180 } 1181 break; 1182 case SIS_VENDORID: 1183 default: 1184#ifdef __i386__ 1185 /* 1186 * If this is a SiS 630E chipset with an embedded 1187 * SiS 900 controller, we have to read the MAC address 1188 * from the APC CMOS RAM. Our method for doing this 1189 * is very ugly since we have to reach out and grab 1190 * ahold of hardware for which we cannot properly 1191 * allocate resources. This code is only compiled on 1192 * the i386 architecture since the SiS 630E chipset 1193 * is for x86 motherboards only. Note that there are 1194 * a lot of magic numbers in this hack. These are 1195 * taken from SiS's Linux driver. I'd like to replace 1196 * them with proper symbolic definitions, but that 1197 * requires some datasheets that I don't have access 1198 * to at the moment. 1199 */ 1200 if (sc->sis_rev == SIS_REV_630S || 1201 sc->sis_rev == SIS_REV_630E || 1202 sc->sis_rev == SIS_REV_630EA1) 1203 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 1204 1205 else if (sc->sis_rev == SIS_REV_635 || 1206 sc->sis_rev == SIS_REV_630ET) 1207 sis_read_mac(sc, dev, (caddr_t)&eaddr); 1208 else if (sc->sis_rev == SIS_REV_96x) { 1209 /* Allow to read EEPROM from LAN. It is shared 1210 * between a 1394 controller and the NIC and each 1211 * time we access it, we need to set SIS_EECMD_REQ. 1212 */ 1213 SIO_SET(SIS_EECMD_REQ); 1214 for (waittime = 0; waittime < SIS_TIMEOUT; 1215 waittime++) { 1216 /* Force EEPROM to idle state. */ 1217 sis_eeprom_idle(sc); 1218 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { 1219 sis_read_eeprom(sc, (caddr_t)&eaddr, 1220 SIS_EE_NODEADDR, 3, 0); 1221 break; 1222 } 1223 DELAY(1); 1224 } 1225 /* 1226 * Set SIS_EECTL_CLK to high, so a other master 1227 * can operate on the i2c bus. 1228 */ 1229 SIO_SET(SIS_EECTL_CLK); 1230 /* Refuse EEPROM access by LAN */ 1231 SIO_SET(SIS_EECMD_DONE); 1232 } else 1233#endif 1234 sis_read_eeprom(sc, (caddr_t)&eaddr, 1235 SIS_EE_NODEADDR, 3, 0); 1236 break; 1237 } 1238 1239 /* 1240 * A SiS chip was detected. Inform the world. 1241 */ 1242 printf("sis%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1243 1244 sc->sis_unit = unit; 1245 callout_init(&sc->sis_stat_ch, CALLOUT_MPSAFE); 1246 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1247 1248 /* 1249 * Allocate the parent bus DMA tag appropriate for PCI. 1250 */ 1251#define SIS_NSEG_NEW 32 1252 error = bus_dma_tag_create(NULL, /* parent */ 1253 1, 0, /* alignment, boundary */ 1254 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1255 BUS_SPACE_MAXADDR, /* highaddr */ 1256 NULL, NULL, /* filter, filterarg */ 1257 MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */ 1258 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1259 BUS_DMA_ALLOCNOW, /* flags */ 1260 NULL, NULL, /* lockfunc, lockarg */ 1261 &sc->sis_parent_tag); 1262 if (error) 1263 goto fail; 1264 1265 /* 1266 * Now allocate a tag for the DMA descriptor lists and a chunk 1267 * of DMA-able memory based on the tag. Also obtain the physical 1268 * addresses of the RX and TX ring, which we'll need later. 1269 * All of our lists are allocated as a contiguous block 1270 * of memory. 1271 */ 1272 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1273 1, 0, /* alignment, boundary */ 1274 BUS_SPACE_MAXADDR, /* lowaddr */ 1275 BUS_SPACE_MAXADDR, /* highaddr */ 1276 NULL, NULL, /* filter, filterarg */ 1277 SIS_RX_LIST_SZ, 1, /* maxsize,nsegments */ 1278 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1279 0, /* flags */ 1280 busdma_lock_mutex, /* lockfunc */ 1281 &Giant, /* lockarg */ 1282 &sc->sis_ldata.sis_rx_tag); 1283 if (error) 1284 goto fail; 1285 1286 error = bus_dmamem_alloc(sc->sis_ldata.sis_rx_tag, 1287 (void **)&sc->sis_ldata.sis_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1288 &sc->sis_ldata.sis_rx_dmamap); 1289 1290 if (error) { 1291 printf("sis%d: no memory for rx list buffers!\n", unit); 1292 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1293 sc->sis_ldata.sis_rx_tag = NULL; 1294 goto fail; 1295 } 1296 1297 error = bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1298 sc->sis_ldata.sis_rx_dmamap, &(sc->sis_ldata.sis_rx_list[0]), 1299 sizeof(struct sis_desc), sis_dma_map_ring, 1300 &sc->sis_cdata.sis_rx_paddr, 0); 1301 1302 if (error) { 1303 printf("sis%d: cannot get address of the rx ring!\n", unit); 1304 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1305 sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap); 1306 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1307 sc->sis_ldata.sis_rx_tag = NULL; 1308 goto fail; 1309 } 1310 1311 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1312 1, 0, /* alignment, boundary */ 1313 BUS_SPACE_MAXADDR, /* lowaddr */ 1314 BUS_SPACE_MAXADDR, /* highaddr */ 1315 NULL, NULL, /* filter, filterarg */ 1316 SIS_TX_LIST_SZ, 1, /* maxsize,nsegments */ 1317 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1318 0, /* flags */ 1319 busdma_lock_mutex, /* lockfunc */ 1320 &Giant, /* lockarg */ 1321 &sc->sis_ldata.sis_tx_tag); 1322 if (error) 1323 goto fail; 1324 1325 error = bus_dmamem_alloc(sc->sis_ldata.sis_tx_tag, 1326 (void **)&sc->sis_ldata.sis_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1327 &sc->sis_ldata.sis_tx_dmamap); 1328 1329 if (error) { 1330 printf("sis%d: no memory for tx list buffers!\n", unit); 1331 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1332 sc->sis_ldata.sis_tx_tag = NULL; 1333 goto fail; 1334 } 1335 1336 error = bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1337 sc->sis_ldata.sis_tx_dmamap, &(sc->sis_ldata.sis_tx_list[0]), 1338 sizeof(struct sis_desc), sis_dma_map_ring, 1339 &sc->sis_cdata.sis_tx_paddr, 0); 1340 1341 if (error) { 1342 printf("sis%d: cannot get address of the tx ring!\n", unit); 1343 bus_dmamem_free(sc->sis_ldata.sis_tx_tag, 1344 sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 1345 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1346 sc->sis_ldata.sis_tx_tag = NULL; 1347 goto fail; 1348 } 1349 1350 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1351 1, 0, /* alignment, boundary */ 1352 BUS_SPACE_MAXADDR, /* lowaddr */ 1353 BUS_SPACE_MAXADDR, /* highaddr */ 1354 NULL, NULL, /* filter, filterarg */ 1355 MCLBYTES, 1, /* maxsize,nsegments */ 1356 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1357 0, /* flags */ 1358 busdma_lock_mutex, /* lockfunc */ 1359 &Giant, /* lockarg */ 1360 &sc->sis_tag); 1361 if (error) 1362 goto fail; 1363 1364 /* 1365 * Obtain the physical addresses of the RX and TX 1366 * rings which we'll need later in the init routine. 1367 */ 1368 1369 ifp = &sc->arpcom.ac_if; 1370 ifp->if_softc = sc; 1371 ifp->if_unit = unit; 1372 ifp->if_name = "sis"; 1373 ifp->if_mtu = ETHERMTU; 1374 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1375 ifp->if_ioctl = sis_ioctl; 1376 ifp->if_output = ether_output; 1377 ifp->if_start = sis_start; 1378 ifp->if_watchdog = sis_watchdog; 1379 ifp->if_init = sis_init; 1380 ifp->if_baudrate = 10000000; 1381 ifp->if_snd.ifq_maxlen = SIS_TX_LIST_CNT - 1; 1382 1383 /* 1384 * Do MII setup. 1385 */ 1386 if (mii_phy_probe(dev, &sc->sis_miibus, 1387 sis_ifmedia_upd, sis_ifmedia_sts)) { 1388 printf("sis%d: MII without any PHY!\n", sc->sis_unit); 1389 error = ENXIO; 1390 goto fail; 1391 } 1392 1393 /* 1394 * Call MI attach routine. 1395 */ 1396 ether_ifattach(ifp, eaddr); 1397 1398 /* 1399 * Tell the upper layer(s) we support long frames. 1400 */ 1401 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1402 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1403 1404 /* Hook interrupt last to avoid having to lock softc */ 1405 error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET, 1406 sis_intr, sc, &sc->sis_intrhand); 1407 1408 if (error) { 1409 printf("sis%d: couldn't set up irq\n", unit); 1410 ether_ifdetach(ifp); 1411 goto fail; 1412 } 1413 1414fail: 1415 if (error) 1416 sis_detach(dev); 1417 1418 return(error); 1419} 1420 1421/* 1422 * Shutdown hardware and free up resources. This can be called any 1423 * time after the mutex has been initialized. It is called in both 1424 * the error case in attach and the normal detach case so it needs 1425 * to be careful about only freeing resources that have actually been 1426 * allocated. 1427 */ 1428static int 1429sis_detach(dev) 1430 device_t dev; 1431{ 1432 struct sis_softc *sc; 1433 struct ifnet *ifp; 1434 1435 sc = device_get_softc(dev); 1436 KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized")); 1437 SIS_LOCK(sc); 1438 ifp = &sc->arpcom.ac_if; 1439 1440 /* These should only be active if attach succeeded. */ 1441 if (device_is_attached(dev)) { 1442 sis_reset(sc); 1443 sis_stop(sc); 1444 ether_ifdetach(ifp); 1445 } 1446 if (sc->sis_miibus) 1447 device_delete_child(dev, sc->sis_miibus); 1448 bus_generic_detach(dev); 1449 1450 if (sc->sis_intrhand) 1451 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1452 if (sc->sis_irq) 1453 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1454 if (sc->sis_res) 1455 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1456 1457 if (sc->sis_ldata.sis_rx_tag) { 1458 bus_dmamap_unload(sc->sis_ldata.sis_rx_tag, 1459 sc->sis_ldata.sis_rx_dmamap); 1460 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1461 sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap); 1462 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1463 } 1464 if (sc->sis_ldata.sis_tx_tag) { 1465 bus_dmamap_unload(sc->sis_ldata.sis_tx_tag, 1466 sc->sis_ldata.sis_tx_dmamap); 1467 bus_dmamem_free(sc->sis_ldata.sis_tx_tag, 1468 sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 1469 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1470 } 1471 if (sc->sis_parent_tag) 1472 bus_dma_tag_destroy(sc->sis_parent_tag); 1473 if (sc->sis_tag) 1474 bus_dma_tag_destroy(sc->sis_tag); 1475 1476 SIS_UNLOCK(sc); 1477 mtx_destroy(&sc->sis_mtx); 1478 1479 return(0); 1480} 1481 1482/* 1483 * Initialize the transmit descriptors. 1484 */ 1485static int 1486sis_list_tx_init(sc) 1487 struct sis_softc *sc; 1488{ 1489 struct sis_list_data *ld; 1490 struct sis_ring_data *cd; 1491 int i, nexti; 1492 1493 cd = &sc->sis_cdata; 1494 ld = &sc->sis_ldata; 1495 1496 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1497 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1; 1498 ld->sis_tx_list[i].sis_nextdesc = 1499 &ld->sis_tx_list[nexti]; 1500 bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1501 sc->sis_ldata.sis_tx_dmamap, 1502 &ld->sis_tx_list[nexti], sizeof(struct sis_desc), 1503 sis_dma_map_desc_next, &ld->sis_tx_list[i], 0); 1504 ld->sis_tx_list[i].sis_mbuf = NULL; 1505 ld->sis_tx_list[i].sis_ptr = 0; 1506 ld->sis_tx_list[i].sis_ctl = 0; 1507 } 1508 1509 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0; 1510 1511 bus_dmamap_sync(sc->sis_ldata.sis_tx_tag, 1512 sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 1513 1514 return(0); 1515} 1516 1517/* 1518 * Initialize the RX descriptors and allocate mbufs for them. Note that 1519 * we arrange the descriptors in a closed ring, so that the last descriptor 1520 * points back to the first. 1521 */ 1522static int 1523sis_list_rx_init(sc) 1524 struct sis_softc *sc; 1525{ 1526 struct sis_list_data *ld; 1527 struct sis_ring_data *cd; 1528 int i,nexti; 1529 1530 ld = &sc->sis_ldata; 1531 cd = &sc->sis_cdata; 1532 1533 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1534 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS) 1535 return(ENOBUFS); 1536 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1; 1537 ld->sis_rx_list[i].sis_nextdesc = 1538 &ld->sis_rx_list[nexti]; 1539 bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1540 sc->sis_ldata.sis_rx_dmamap, 1541 &ld->sis_rx_list[nexti], 1542 sizeof(struct sis_desc), sis_dma_map_desc_next, 1543 &ld->sis_rx_list[i], 0); 1544 } 1545 1546 bus_dmamap_sync(sc->sis_ldata.sis_rx_tag, 1547 sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 1548 1549 cd->sis_rx_prod = 0; 1550 1551 return(0); 1552} 1553 1554/* 1555 * Initialize an RX descriptor and attach an MBUF cluster. 1556 */ 1557static int 1558sis_newbuf(sc, c, m) 1559 struct sis_softc *sc; 1560 struct sis_desc *c; 1561 struct mbuf *m; 1562{ 1563 1564 if (c == NULL) 1565 return(EINVAL); 1566 1567 if (m == NULL) { 1568 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1569 if (m == NULL) 1570 return(ENOBUFS); 1571 } else 1572 m->m_data = m->m_ext.ext_buf; 1573 1574 c->sis_mbuf = m; 1575 c->sis_ctl = SIS_RXLEN; 1576 1577 bus_dmamap_create(sc->sis_tag, 0, &c->sis_map); 1578 bus_dmamap_load(sc->sis_tag, c->sis_map, 1579 mtod(m, void *), MCLBYTES, 1580 sis_dma_map_desc_ptr, c, 0); 1581 bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREWRITE); 1582 1583 return(0); 1584} 1585 1586/* 1587 * A frame has been uploaded: pass the resulting mbuf chain up to 1588 * the higher level protocols. 1589 */ 1590static void 1591sis_rxeof(sc) 1592 struct sis_softc *sc; 1593{ 1594 struct mbuf *m; 1595 struct ifnet *ifp; 1596 struct sis_desc *cur_rx; 1597 int i, total_len = 0; 1598 u_int32_t rxstat; 1599 1600 ifp = &sc->arpcom.ac_if; 1601 i = sc->sis_cdata.sis_rx_prod; 1602 1603 while(SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) { 1604 1605#ifdef DEVICE_POLLING 1606 if (ifp->if_flags & IFF_POLLING) { 1607 if (sc->rxcycles <= 0) 1608 break; 1609 sc->rxcycles--; 1610 } 1611#endif /* DEVICE_POLLING */ 1612 cur_rx = &sc->sis_ldata.sis_rx_list[i]; 1613 rxstat = cur_rx->sis_rxstat; 1614 bus_dmamap_sync(sc->sis_tag, 1615 cur_rx->sis_map, BUS_DMASYNC_POSTWRITE); 1616 bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map); 1617 bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map); 1618 m = cur_rx->sis_mbuf; 1619 cur_rx->sis_mbuf = NULL; 1620 total_len = SIS_RXBYTES(cur_rx); 1621 SIS_INC(i, SIS_RX_LIST_CNT); 1622 1623 /* 1624 * If an error occurs, update stats, clear the 1625 * status word and leave the mbuf cluster in place: 1626 * it should simply get re-used next time this descriptor 1627 * comes up in the ring. 1628 */ 1629 if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 1630 ifp->if_ierrors++; 1631 if (rxstat & SIS_RXSTAT_COLL) 1632 ifp->if_collisions++; 1633 sis_newbuf(sc, cur_rx, m); 1634 continue; 1635 } 1636 1637 /* No errors; receive the packet. */ 1638#ifdef __i386__ 1639 /* 1640 * On the x86 we do not have alignment problems, so try to 1641 * allocate a new buffer for the receive ring, and pass up 1642 * the one where the packet is already, saving the expensive 1643 * copy done in m_devget(). 1644 * If we are on an architecture with alignment problems, or 1645 * if the allocation fails, then use m_devget and leave the 1646 * existing buffer in the receive ring. 1647 */ 1648 if (sis_newbuf(sc, cur_rx, NULL) == 0) 1649 m->m_pkthdr.len = m->m_len = total_len; 1650 else 1651#endif 1652 { 1653 struct mbuf *m0; 1654 m0 = m_devget(mtod(m, char *), total_len, 1655 ETHER_ALIGN, ifp, NULL); 1656 sis_newbuf(sc, cur_rx, m); 1657 if (m0 == NULL) { 1658 ifp->if_ierrors++; 1659 continue; 1660 } 1661 m = m0; 1662 } 1663 1664 ifp->if_ipackets++; 1665 m->m_pkthdr.rcvif = ifp; 1666 1667 (*ifp->if_input)(ifp, m); 1668 } 1669 1670 sc->sis_cdata.sis_rx_prod = i; 1671 1672 return; 1673} 1674 1675static void 1676sis_rxeoc(sc) 1677 struct sis_softc *sc; 1678{ 1679 sis_rxeof(sc); 1680 sis_init(sc); 1681 return; 1682} 1683 1684/* 1685 * A frame was downloaded to the chip. It's safe for us to clean up 1686 * the list buffers. 1687 */ 1688 1689static void 1690sis_txeof(sc) 1691 struct sis_softc *sc; 1692{ 1693 struct ifnet *ifp; 1694 u_int32_t idx; 1695 1696 ifp = &sc->arpcom.ac_if; 1697 1698 /* 1699 * Go through our tx list and free mbufs for those 1700 * frames that have been transmitted. 1701 */ 1702 for (idx = sc->sis_cdata.sis_tx_cons; sc->sis_cdata.sis_tx_cnt > 0; 1703 sc->sis_cdata.sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) { 1704 struct sis_desc *cur_tx = &sc->sis_ldata.sis_tx_list[idx]; 1705 1706 if (SIS_OWNDESC(cur_tx)) 1707 break; 1708 1709 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) 1710 continue; 1711 1712 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 1713 ifp->if_oerrors++; 1714 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 1715 ifp->if_collisions++; 1716 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 1717 ifp->if_collisions++; 1718 } 1719 1720 ifp->if_collisions += 1721 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 1722 1723 ifp->if_opackets++; 1724 if (cur_tx->sis_mbuf != NULL) { 1725 m_freem(cur_tx->sis_mbuf); 1726 cur_tx->sis_mbuf = NULL; 1727 bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map); 1728 bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map); 1729 } 1730 } 1731 1732 if (idx != sc->sis_cdata.sis_tx_cons) { 1733 /* we freed up some buffers */ 1734 sc->sis_cdata.sis_tx_cons = idx; 1735 ifp->if_flags &= ~IFF_OACTIVE; 1736 } 1737 1738 ifp->if_timer = (sc->sis_cdata.sis_tx_cnt == 0) ? 0 : 5; 1739 1740 return; 1741} 1742 1743static void 1744sis_tick(xsc) 1745 void *xsc; 1746{ 1747 struct sis_softc *sc; 1748 struct mii_data *mii; 1749 struct ifnet *ifp; 1750 1751 sc = xsc; 1752 SIS_LOCK(sc); 1753 sc->in_tick = 1; 1754 ifp = &sc->arpcom.ac_if; 1755 1756 mii = device_get_softc(sc->sis_miibus); 1757 mii_tick(mii); 1758 1759 if (!sc->sis_link && mii->mii_media_status & IFM_ACTIVE && 1760 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1761 sc->sis_link++; 1762 if (ifp->if_snd.ifq_head != NULL) 1763 sis_start(ifp); 1764 } 1765 1766 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 1767 sc->in_tick = 0; 1768 SIS_UNLOCK(sc); 1769 1770 return; 1771} 1772 1773#ifdef DEVICE_POLLING 1774static poll_handler_t sis_poll; 1775 1776static void 1777sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1778{ 1779 struct sis_softc *sc = ifp->if_softc; 1780 1781 SIS_LOCK(sc); 1782 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1783 CSR_WRITE_4(sc, SIS_IER, 1); 1784 goto done; 1785 } 1786 1787 /* 1788 * On the sis, reading the status register also clears it. 1789 * So before returning to intr mode we must make sure that all 1790 * possible pending sources of interrupts have been served. 1791 * In practice this means run to completion the *eof routines, 1792 * and then call the interrupt routine 1793 */ 1794 sc->rxcycles = count; 1795 sis_rxeof(sc); 1796 sis_txeof(sc); 1797 if (ifp->if_snd.ifq_head != NULL) 1798 sis_start(ifp); 1799 1800 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1801 u_int32_t status; 1802 1803 /* Reading the ISR register clears all interrupts. */ 1804 status = CSR_READ_4(sc, SIS_ISR); 1805 1806 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 1807 sis_rxeoc(sc); 1808 1809 if (status & (SIS_ISR_RX_IDLE)) 1810 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1811 1812 if (status & SIS_ISR_SYSERR) { 1813 sis_reset(sc); 1814 sis_init(sc); 1815 } 1816 } 1817done: 1818 SIS_UNLOCK(sc); 1819 return; 1820} 1821#endif /* DEVICE_POLLING */ 1822 1823static void 1824sis_intr(arg) 1825 void *arg; 1826{ 1827 struct sis_softc *sc; 1828 struct ifnet *ifp; 1829 u_int32_t status; 1830 1831 sc = arg; 1832 ifp = &sc->arpcom.ac_if; 1833 1834 SIS_LOCK(sc); 1835#ifdef DEVICE_POLLING 1836 if (ifp->if_flags & IFF_POLLING) 1837 goto done; 1838 if (ether_poll_register(sis_poll, ifp)) { /* ok, disable interrupts */ 1839 CSR_WRITE_4(sc, SIS_IER, 0); 1840 goto done; 1841 } 1842#endif /* DEVICE_POLLING */ 1843 1844 /* Supress unwanted interrupts */ 1845 if (!(ifp->if_flags & IFF_UP)) { 1846 sis_stop(sc); 1847 goto done; 1848 } 1849 1850 /* Disable interrupts. */ 1851 CSR_WRITE_4(sc, SIS_IER, 0); 1852 1853 for (;;) { 1854 /* Reading the ISR register clears all interrupts. */ 1855 status = CSR_READ_4(sc, SIS_ISR); 1856 1857 if ((status & SIS_INTRS) == 0) 1858 break; 1859 1860 if (status & 1861 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | 1862 SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) ) 1863 sis_txeof(sc); 1864 1865 if (status & (SIS_ISR_RX_DESC_OK|SIS_ISR_RX_OK|SIS_ISR_RX_IDLE)) 1866 sis_rxeof(sc); 1867 1868 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW)) 1869 sis_rxeoc(sc); 1870 1871 if (status & (SIS_ISR_RX_IDLE)) 1872 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1873 1874 if (status & SIS_ISR_SYSERR) { 1875 sis_reset(sc); 1876 sis_init(sc); 1877 } 1878 } 1879 1880 /* Re-enable interrupts. */ 1881 CSR_WRITE_4(sc, SIS_IER, 1); 1882 1883 if (ifp->if_snd.ifq_head != NULL) 1884 sis_start(ifp); 1885done: 1886 SIS_UNLOCK(sc); 1887 1888 return; 1889} 1890 1891/* 1892 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1893 * pointers to the fragment pointers. 1894 */ 1895static int 1896sis_encap(sc, m_head, txidx) 1897 struct sis_softc *sc; 1898 struct mbuf *m_head; 1899 u_int32_t *txidx; 1900{ 1901 struct sis_desc *f = NULL; 1902 struct mbuf *m; 1903 int frag, cur, cnt = 0, chainlen = 0; 1904 1905 /* 1906 * If there's no way we can send any packets, return now. 1907 */ 1908 if (SIS_TX_LIST_CNT - sc->sis_cdata.sis_tx_cnt < 2) 1909 return (ENOBUFS); 1910 1911 /* 1912 * Count the number of frags in this chain to see if 1913 * we need to m_defrag. Since the descriptor list is shared 1914 * by all packets, we'll m_defrag long chains so that they 1915 * do not use up the entire list, even if they would fit. 1916 */ 1917 1918 for (m = m_head; m != NULL; m = m->m_next) 1919 chainlen++; 1920 1921 if ((chainlen > SIS_TX_LIST_CNT / 4) || 1922 ((SIS_TX_LIST_CNT - (chainlen + sc->sis_cdata.sis_tx_cnt)) < 2)) { 1923 m = m_defrag(m_head, M_DONTWAIT); 1924 if (m == NULL) 1925 return (ENOBUFS); 1926 m_head = m; 1927 } 1928 1929 /* 1930 * Start packing the mbufs in this chain into 1931 * the fragment pointers. Stop when we run out 1932 * of fragments or hit the end of the mbuf chain. 1933 */ 1934 m = m_head; 1935 cur = frag = *txidx; 1936 1937 for (m = m_head; m != NULL; m = m->m_next) { 1938 if (m->m_len != 0) { 1939 if ((SIS_TX_LIST_CNT - 1940 (sc->sis_cdata.sis_tx_cnt + cnt)) < 2) 1941 return(ENOBUFS); 1942 f = &sc->sis_ldata.sis_tx_list[frag]; 1943 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; 1944 bus_dmamap_create(sc->sis_tag, 0, &f->sis_map); 1945 bus_dmamap_load(sc->sis_tag, f->sis_map, 1946 mtod(m, void *), m->m_len, 1947 sis_dma_map_desc_ptr, f, 0); 1948 bus_dmamap_sync(sc->sis_tag, 1949 f->sis_map, BUS_DMASYNC_PREREAD); 1950 if (cnt != 0) 1951 f->sis_ctl |= SIS_CMDSTS_OWN; 1952 cur = frag; 1953 SIS_INC(frag, SIS_TX_LIST_CNT); 1954 cnt++; 1955 } 1956 } 1957 1958 if (m != NULL) 1959 return(ENOBUFS); 1960 1961 sc->sis_ldata.sis_tx_list[cur].sis_mbuf = m_head; 1962 sc->sis_ldata.sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1963 sc->sis_ldata.sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1964 sc->sis_cdata.sis_tx_cnt += cnt; 1965 *txidx = frag; 1966 1967 return(0); 1968} 1969 1970/* 1971 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1972 * to the mbuf data regions directly in the transmit lists. We also save a 1973 * copy of the pointers since the transmit list fragment pointers are 1974 * physical addresses. 1975 */ 1976 1977static void 1978sis_start(ifp) 1979 struct ifnet *ifp; 1980{ 1981 struct sis_softc *sc; 1982 struct mbuf *m_head = NULL; 1983 u_int32_t idx; 1984 1985 sc = ifp->if_softc; 1986 SIS_LOCK(sc); 1987 1988 if (!sc->sis_link) { 1989 SIS_UNLOCK(sc); 1990 return; 1991 } 1992 1993 idx = sc->sis_cdata.sis_tx_prod; 1994 1995 if (ifp->if_flags & IFF_OACTIVE) { 1996 SIS_UNLOCK(sc); 1997 return; 1998 } 1999 2000 while(sc->sis_ldata.sis_tx_list[idx].sis_mbuf == NULL) { 2001 IF_DEQUEUE(&ifp->if_snd, m_head); 2002 if (m_head == NULL) 2003 break; 2004 2005 if (sis_encap(sc, m_head, &idx)) { 2006 IF_PREPEND(&ifp->if_snd, m_head); 2007 ifp->if_flags |= IFF_OACTIVE; 2008 break; 2009 } 2010 2011 /* 2012 * If there's a BPF listener, bounce a copy of this frame 2013 * to him. 2014 */ 2015 BPF_MTAP(ifp, m_head); 2016 2017 } 2018 2019 /* Transmit */ 2020 sc->sis_cdata.sis_tx_prod = idx; 2021 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 2022 2023 /* 2024 * Set a timeout in case the chip goes out to lunch. 2025 */ 2026 ifp->if_timer = 5; 2027 2028 SIS_UNLOCK(sc); 2029 2030 return; 2031} 2032 2033static void 2034sis_init(xsc) 2035 void *xsc; 2036{ 2037 struct sis_softc *sc = xsc; 2038 struct ifnet *ifp = &sc->arpcom.ac_if; 2039 struct mii_data *mii; 2040 2041 SIS_LOCK(sc); 2042 2043 /* 2044 * Cancel pending I/O and free all RX/TX buffers. 2045 */ 2046 sis_stop(sc); 2047 2048#ifdef notyet 2049 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) { 2050 /* 2051 * Configure 400usec of interrupt holdoff. This is based 2052 * on emperical tests on a Soekris 4801. 2053 */ 2054 CSR_WRITE_4(sc, NS_IHR, 0x100 | 4); 2055 } 2056#endif 2057 2058 mii = device_get_softc(sc->sis_miibus); 2059 2060 /* Set MAC address */ 2061 if (sc->sis_type == SIS_TYPE_83815) { 2062 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 2063 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2064 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 2065 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 2066 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2067 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 2068 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 2069 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2070 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 2071 } else { 2072 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 2073 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2074 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 2075 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 2076 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2077 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 2078 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 2079 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2080 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 2081 } 2082 2083 /* Init circular RX list. */ 2084 if (sis_list_rx_init(sc) == ENOBUFS) { 2085 printf("sis%d: initialization failed: no " 2086 "memory for rx buffers\n", sc->sis_unit); 2087 sis_stop(sc); 2088 SIS_UNLOCK(sc); 2089 return; 2090 } 2091 2092 /* 2093 * Init tx descriptors. 2094 */ 2095 sis_list_tx_init(sc); 2096 2097 /* 2098 * For the NatSemi chip, we have to explicitly enable the 2099 * reception of ARP frames, as well as turn on the 'perfect 2100 * match' filter where we store the station address, otherwise 2101 * we won't receive unicasts meant for this host. 2102 */ 2103 if (sc->sis_type == SIS_TYPE_83815) { 2104 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 2105 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 2106 } 2107 2108 /* If we want promiscuous mode, set the allframes bit. */ 2109 if (ifp->if_flags & IFF_PROMISC) { 2110 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 2111 } else { 2112 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 2113 } 2114 2115 /* 2116 * Set the capture broadcast bit to capture broadcast frames. 2117 */ 2118 if (ifp->if_flags & IFF_BROADCAST) { 2119 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 2120 } else { 2121 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 2122 } 2123 2124 /* 2125 * Load the multicast filter. 2126 */ 2127 if (sc->sis_type == SIS_TYPE_83815) 2128 sis_setmulti_ns(sc); 2129 else 2130 sis_setmulti_sis(sc); 2131 2132 /* Turn the receive filter on */ 2133 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 2134 2135 /* 2136 * Load the address of the RX and TX lists. 2137 */ 2138 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_cdata.sis_rx_paddr); 2139 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_cdata.sis_tx_paddr); 2140 2141 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of 2142 * the PCI bus. When this bit is set, the Max DMA Burst Size 2143 * for TX/RX DMA should be no larger than 16 double words. 2144 */ 2145 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) { 2146 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); 2147 } else { 2148 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); 2149 } 2150 2151 2152 /* Accept Long Packets for VLAN support */ 2153 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 2154 2155 /* Set TX configuration */ 2156 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 2157 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 2158 } else { 2159 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 2160 } 2161 2162 /* Set full/half duplex mode. */ 2163 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 2164 SIS_SETBIT(sc, SIS_TX_CFG, 2165 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 2166 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 2167 } else { 2168 SIS_CLRBIT(sc, SIS_TX_CFG, 2169 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 2170 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 2171 } 2172 2173 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr < NS_SRR_16A && 2174 IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 2175 uint32_t reg; 2176 2177 /* 2178 * Some DP83815s experience problems when used with short 2179 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 2180 * sequence adjusts the DSP's signal attenuation to fix the 2181 * problem. 2182 */ 2183 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 2184 2185 reg = CSR_READ_4(sc, NS_PHY_DSPCFG); 2186 CSR_WRITE_4(sc, NS_PHY_DSPCFG, (reg & 0xfff) | 0x1000); 2187 DELAY(100); 2188 reg = CSR_READ_4(sc, NS_PHY_TDATA); 2189 if ((reg & 0x0080) == 0 || (reg & 0xff) >= 0xd8) { 2190 device_printf(sc->sis_self, "Applying short cable fix (reg=%x)\n", reg); 2191 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8); 2192 SIS_SETBIT(sc, NS_PHY_DSPCFG, 0x20); 2193 } 2194 CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 2195 } 2196 2197 /* 2198 * Enable interrupts. 2199 */ 2200 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 2201#ifdef DEVICE_POLLING 2202 /* 2203 * ... only enable interrupts if we are not polling, make sure 2204 * they are off otherwise. 2205 */ 2206 if (ifp->if_flags & IFF_POLLING) 2207 CSR_WRITE_4(sc, SIS_IER, 0); 2208 else 2209#endif /* DEVICE_POLLING */ 2210 CSR_WRITE_4(sc, SIS_IER, 1); 2211 2212 /* Enable receiver and transmitter. */ 2213 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2214 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 2215 2216#ifdef notdef 2217 mii_mediachg(mii); 2218#endif 2219 2220 /* 2221 * Page 75 of the DP83815 manual recommends the 2222 * following register settings "for optimum 2223 * performance." Note however that at least three 2224 * of the registers are listed as "reserved" in 2225 * the register map, so who knows what they do. 2226 */ 2227 if (sc->sis_type == SIS_TYPE_83815) { 2228 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 2229 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 2230 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 2231 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 2232 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 2233 } 2234 2235 ifp->if_flags |= IFF_RUNNING; 2236 ifp->if_flags &= ~IFF_OACTIVE; 2237 2238 if (!sc->in_tick) 2239 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 2240 2241 SIS_UNLOCK(sc); 2242 2243 return; 2244} 2245 2246/* 2247 * Set media options. 2248 */ 2249static int 2250sis_ifmedia_upd(ifp) 2251 struct ifnet *ifp; 2252{ 2253 struct sis_softc *sc; 2254 struct mii_data *mii; 2255 2256 sc = ifp->if_softc; 2257 2258 mii = device_get_softc(sc->sis_miibus); 2259 sc->sis_link = 0; 2260 if (mii->mii_instance) { 2261 struct mii_softc *miisc; 2262 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2263 mii_phy_reset(miisc); 2264 } 2265 mii_mediachg(mii); 2266 2267 return(0); 2268} 2269 2270/* 2271 * Report current media status. 2272 */ 2273static void 2274sis_ifmedia_sts(ifp, ifmr) 2275 struct ifnet *ifp; 2276 struct ifmediareq *ifmr; 2277{ 2278 struct sis_softc *sc; 2279 struct mii_data *mii; 2280 2281 sc = ifp->if_softc; 2282 2283 mii = device_get_softc(sc->sis_miibus); 2284 mii_pollstat(mii); 2285 ifmr->ifm_active = mii->mii_media_active; 2286 ifmr->ifm_status = mii->mii_media_status; 2287 2288 return; 2289} 2290 2291static int 2292sis_ioctl(ifp, command, data) 2293 struct ifnet *ifp; 2294 u_long command; 2295 caddr_t data; 2296{ 2297 struct sis_softc *sc = ifp->if_softc; 2298 struct ifreq *ifr = (struct ifreq *) data; 2299 struct mii_data *mii; 2300 int error = 0; 2301 2302 switch(command) { 2303 case SIOCSIFFLAGS: 2304 if (ifp->if_flags & IFF_UP) { 2305 sis_init(sc); 2306 } else { 2307 if (ifp->if_flags & IFF_RUNNING) 2308 sis_stop(sc); 2309 } 2310 error = 0; 2311 break; 2312 case SIOCADDMULTI: 2313 case SIOCDELMULTI: 2314 SIS_LOCK(sc); 2315 if (sc->sis_type == SIS_TYPE_83815) 2316 sis_setmulti_ns(sc); 2317 else 2318 sis_setmulti_sis(sc); 2319 SIS_UNLOCK(sc); 2320 error = 0; 2321 break; 2322 case SIOCGIFMEDIA: 2323 case SIOCSIFMEDIA: 2324 mii = device_get_softc(sc->sis_miibus); 2325 SIS_LOCK(sc); 2326 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2327 SIS_UNLOCK(sc); 2328 break; 2329 default: 2330 error = ether_ioctl(ifp, command, data); 2331 break; 2332 } 2333 2334 return(error); 2335} 2336 2337static void 2338sis_watchdog(ifp) 2339 struct ifnet *ifp; 2340{ 2341 struct sis_softc *sc; 2342 2343 sc = ifp->if_softc; 2344 2345 SIS_LOCK(sc); 2346 2347 ifp->if_oerrors++; 2348 printf("sis%d: watchdog timeout\n", sc->sis_unit); 2349 2350 sis_stop(sc); 2351 sis_reset(sc); 2352 sis_init(sc); 2353 2354 if (ifp->if_snd.ifq_head != NULL) 2355 sis_start(ifp); 2356 2357 SIS_UNLOCK(sc); 2358 2359 return; 2360} 2361 2362/* 2363 * Stop the adapter and free any mbufs allocated to the 2364 * RX and TX lists. 2365 */ 2366static void 2367sis_stop(sc) 2368 struct sis_softc *sc; 2369{ 2370 register int i; 2371 struct ifnet *ifp; 2372 2373 SIS_LOCK(sc); 2374 ifp = &sc->arpcom.ac_if; 2375 ifp->if_timer = 0; 2376 2377 callout_stop(&sc->sis_stat_ch); 2378 2379 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2380#ifdef DEVICE_POLLING 2381 ether_poll_deregister(ifp); 2382#endif 2383 CSR_WRITE_4(sc, SIS_IER, 0); 2384 CSR_WRITE_4(sc, SIS_IMR, 0); 2385 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2386 DELAY(1000); 2387 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 2388 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2389 2390 sc->sis_link = 0; 2391 2392 /* 2393 * Free data in the RX lists. 2394 */ 2395 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 2396 if (sc->sis_ldata.sis_rx_list[i].sis_mbuf != NULL) { 2397 bus_dmamap_unload(sc->sis_tag, 2398 sc->sis_ldata.sis_rx_list[i].sis_map); 2399 bus_dmamap_destroy(sc->sis_tag, 2400 sc->sis_ldata.sis_rx_list[i].sis_map); 2401 m_freem(sc->sis_ldata.sis_rx_list[i].sis_mbuf); 2402 sc->sis_ldata.sis_rx_list[i].sis_mbuf = NULL; 2403 } 2404 } 2405 bzero(sc->sis_ldata.sis_rx_list, 2406 sizeof(sc->sis_ldata.sis_rx_list)); 2407 2408 /* 2409 * Free the TX list buffers. 2410 */ 2411 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 2412 if (sc->sis_ldata.sis_tx_list[i].sis_mbuf != NULL) { 2413 bus_dmamap_unload(sc->sis_tag, 2414 sc->sis_ldata.sis_tx_list[i].sis_map); 2415 bus_dmamap_destroy(sc->sis_tag, 2416 sc->sis_ldata.sis_tx_list[i].sis_map); 2417 m_freem(sc->sis_ldata.sis_tx_list[i].sis_mbuf); 2418 sc->sis_ldata.sis_tx_list[i].sis_mbuf = NULL; 2419 } 2420 } 2421 2422 bzero(sc->sis_ldata.sis_tx_list, 2423 sizeof(sc->sis_ldata.sis_tx_list)); 2424 2425 SIS_UNLOCK(sc); 2426 2427 return; 2428} 2429 2430/* 2431 * Stop all chip I/O so that the kernel's probe routines don't 2432 * get confused by errant DMAs when rebooting. 2433 */ 2434static void 2435sis_shutdown(dev) 2436 device_t dev; 2437{ 2438 struct sis_softc *sc; 2439 2440 sc = device_get_softc(dev); 2441 SIS_LOCK(sc); 2442 sis_reset(sc); 2443 sis_stop(sc); 2444 SIS_UNLOCK(sc); 2445 2446 return; 2447} 2448