if_sis.c revision 112880
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_sis.c 112880 2003-03-31 20:22:00Z jhb $ 33 */ 34 35/* 36 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 37 * available from http://www.sis.com.tw. 38 * 39 * This driver also supports the NatSemi DP83815. Datasheets are 40 * available from http://www.national.com. 41 * 42 * Written by Bill Paul <wpaul@ee.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47/* 48 * The SiS 900 is a fairly simple chip. It uses bus master DMA with 49 * simple TX and RX descriptors of 3 longwords in size. The receiver 50 * has a single perfect filter entry for the station address and a 51 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 52 * transceiver while the 7016 requires an external transceiver chip. 53 * Both chips offer the standard bit-bang MII interface as well as 54 * an enchanced PHY interface which simplifies accessing MII registers. 55 * 56 * The only downside to this chipset is that RX descriptors must be 57 * longword aligned. 58 */ 59 60#include <sys/param.h> 61#include <sys/systm.h> 62#include <sys/sockio.h> 63#include <sys/mbuf.h> 64#include <sys/malloc.h> 65#include <sys/kernel.h> 66#include <sys/socket.h> 67#include <sys/sysctl.h> 68 69#include <net/if.h> 70#include <net/if_arp.h> 71#include <net/ethernet.h> 72#include <net/if_dl.h> 73#include <net/if_media.h> 74#include <net/if_types.h> 75#include <net/if_vlan_var.h> 76 77#include <net/bpf.h> 78 79#include <machine/bus_pio.h> 80#include <machine/bus_memio.h> 81#include <machine/bus.h> 82#include <machine/resource.h> 83#include <sys/bus.h> 84#include <sys/rman.h> 85 86#include <dev/mii/mii.h> 87#include <dev/mii/miivar.h> 88 89#include <pci/pcireg.h> 90#include <pci/pcivar.h> 91 92#define SIS_USEIOSPACE 93 94#include <pci/if_sisreg.h> 95 96MODULE_DEPEND(sis, miibus, 1, 1, 1); 97 98/* "controller miibus0" required. See GENERIC if you get errors here. */ 99#include "miibus_if.h" 100 101#ifndef lint 102static const char rcsid[] = 103 "$FreeBSD: head/sys/pci/if_sis.c 112880 2003-03-31 20:22:00Z jhb $"; 104#endif 105 106/* 107 * Various supported device vendors/types and their names. 108 */ 109static struct sis_type sis_devs[] = { 110 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 111 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 112 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP83815 10/100BaseTX" }, 113 { 0, 0, NULL } 114}; 115 116static int sis_probe (device_t); 117static int sis_attach (device_t); 118static int sis_detach (device_t); 119 120static int sis_newbuf (struct sis_softc *, 121 struct sis_desc *, struct mbuf *); 122static int sis_encap (struct sis_softc *, 123 struct mbuf *, u_int32_t *); 124static void sis_rxeof (struct sis_softc *); 125static void sis_rxeoc (struct sis_softc *); 126static void sis_txeof (struct sis_softc *); 127static void sis_intr (void *); 128static void sis_tick (void *); 129static void sis_start (struct ifnet *); 130static int sis_ioctl (struct ifnet *, u_long, caddr_t); 131static void sis_init (void *); 132static void sis_stop (struct sis_softc *); 133static void sis_watchdog (struct ifnet *); 134static void sis_shutdown (device_t); 135static int sis_ifmedia_upd (struct ifnet *); 136static void sis_ifmedia_sts (struct ifnet *, struct ifmediareq *); 137 138static u_int16_t sis_reverse (u_int16_t); 139static void sis_delay (struct sis_softc *); 140static void sis_eeprom_idle (struct sis_softc *); 141static void sis_eeprom_putbyte (struct sis_softc *, int); 142static void sis_eeprom_getword (struct sis_softc *, int, u_int16_t *); 143static void sis_read_eeprom (struct sis_softc *, caddr_t, int, int, int); 144#ifdef __i386__ 145static void sis_read_cmos (struct sis_softc *, device_t, caddr_t, 146 int, int); 147static void sis_read_mac (struct sis_softc *, device_t, caddr_t); 148static device_t sis_find_bridge (device_t); 149#endif 150 151static void sis_mii_sync (struct sis_softc *); 152static void sis_mii_send (struct sis_softc *, u_int32_t, int); 153static int sis_mii_readreg (struct sis_softc *, struct sis_mii_frame *); 154static int sis_mii_writereg (struct sis_softc *, struct sis_mii_frame *); 155static int sis_miibus_readreg (device_t, int, int); 156static int sis_miibus_writereg (device_t, int, int, int); 157static void sis_miibus_statchg (device_t); 158 159static void sis_setmulti_sis (struct sis_softc *); 160static void sis_setmulti_ns (struct sis_softc *); 161static u_int32_t sis_crc (struct sis_softc *, caddr_t); 162static void sis_reset (struct sis_softc *); 163static int sis_list_rx_init (struct sis_softc *); 164static int sis_list_tx_init (struct sis_softc *); 165 166static void sis_dma_map_desc_ptr (void *, bus_dma_segment_t *, int, int); 167static void sis_dma_map_desc_next (void *, bus_dma_segment_t *, int, int); 168static void sis_dma_map_ring (void *, bus_dma_segment_t *, int, int); 169#ifdef SIS_USEIOSPACE 170#define SIS_RES SYS_RES_IOPORT 171#define SIS_RID SIS_PCI_LOIO 172#else 173#define SIS_RES SYS_RES_MEMORY 174#define SIS_RID SIS_PCI_LOMEM 175#endif 176 177static device_method_t sis_methods[] = { 178 /* Device interface */ 179 DEVMETHOD(device_probe, sis_probe), 180 DEVMETHOD(device_attach, sis_attach), 181 DEVMETHOD(device_detach, sis_detach), 182 DEVMETHOD(device_shutdown, sis_shutdown), 183 184 /* bus interface */ 185 DEVMETHOD(bus_print_child, bus_generic_print_child), 186 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 187 188 /* MII interface */ 189 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 190 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 191 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 192 193 { 0, 0 } 194}; 195 196static driver_t sis_driver = { 197 "sis", 198 sis_methods, 199 sizeof(struct sis_softc) 200}; 201 202static devclass_t sis_devclass; 203 204DRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, 0, 0); 205DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 206 207#define SIS_SETBIT(sc, reg, x) \ 208 CSR_WRITE_4(sc, reg, \ 209 CSR_READ_4(sc, reg) | (x)) 210 211#define SIS_CLRBIT(sc, reg, x) \ 212 CSR_WRITE_4(sc, reg, \ 213 CSR_READ_4(sc, reg) & ~(x)) 214 215#define SIO_SET(x) \ 216 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 217 218#define SIO_CLR(x) \ 219 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 220 221static void 222sis_dma_map_desc_next(arg, segs, nseg, error) 223 void *arg; 224 bus_dma_segment_t *segs; 225 int nseg, error; 226{ 227 struct sis_desc *r; 228 229 r = arg; 230 r->sis_next = segs->ds_addr; 231 232 return; 233} 234 235static void 236sis_dma_map_desc_ptr(arg, segs, nseg, error) 237 void *arg; 238 bus_dma_segment_t *segs; 239 int nseg, error; 240{ 241 struct sis_desc *r; 242 243 r = arg; 244 r->sis_ptr = segs->ds_addr; 245 246 return; 247} 248 249static void 250sis_dma_map_ring(arg, segs, nseg, error) 251 void *arg; 252 bus_dma_segment_t *segs; 253 int nseg, error; 254{ 255 u_int32_t *p; 256 257 p = arg; 258 *p = segs->ds_addr; 259 260 return; 261} 262 263/* 264 * Routine to reverse the bits in a word. Stolen almost 265 * verbatim from /usr/games/fortune. 266 */ 267static u_int16_t 268sis_reverse(n) 269 u_int16_t n; 270{ 271 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 272 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 273 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 274 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 275 276 return(n); 277} 278 279static void 280sis_delay(sc) 281 struct sis_softc *sc; 282{ 283 int idx; 284 285 for (idx = (300 / 33) + 1; idx > 0; idx--) 286 CSR_READ_4(sc, SIS_CSR); 287 288 return; 289} 290 291static void 292sis_eeprom_idle(sc) 293 struct sis_softc *sc; 294{ 295 register int i; 296 297 SIO_SET(SIS_EECTL_CSEL); 298 sis_delay(sc); 299 SIO_SET(SIS_EECTL_CLK); 300 sis_delay(sc); 301 302 for (i = 0; i < 25; i++) { 303 SIO_CLR(SIS_EECTL_CLK); 304 sis_delay(sc); 305 SIO_SET(SIS_EECTL_CLK); 306 sis_delay(sc); 307 } 308 309 SIO_CLR(SIS_EECTL_CLK); 310 sis_delay(sc); 311 SIO_CLR(SIS_EECTL_CSEL); 312 sis_delay(sc); 313 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 314 315 return; 316} 317 318/* 319 * Send a read command and address to the EEPROM, check for ACK. 320 */ 321static void 322sis_eeprom_putbyte(sc, addr) 323 struct sis_softc *sc; 324 int addr; 325{ 326 register int d, i; 327 328 d = addr | SIS_EECMD_READ; 329 330 /* 331 * Feed in each bit and stobe the clock. 332 */ 333 for (i = 0x400; i; i >>= 1) { 334 if (d & i) { 335 SIO_SET(SIS_EECTL_DIN); 336 } else { 337 SIO_CLR(SIS_EECTL_DIN); 338 } 339 sis_delay(sc); 340 SIO_SET(SIS_EECTL_CLK); 341 sis_delay(sc); 342 SIO_CLR(SIS_EECTL_CLK); 343 sis_delay(sc); 344 } 345 346 return; 347} 348 349/* 350 * Read a word of data stored in the EEPROM at address 'addr.' 351 */ 352static void 353sis_eeprom_getword(sc, addr, dest) 354 struct sis_softc *sc; 355 int addr; 356 u_int16_t *dest; 357{ 358 register int i; 359 u_int16_t word = 0; 360 361 /* Force EEPROM to idle state. */ 362 sis_eeprom_idle(sc); 363 364 /* Enter EEPROM access mode. */ 365 sis_delay(sc); 366 SIO_CLR(SIS_EECTL_CLK); 367 sis_delay(sc); 368 SIO_SET(SIS_EECTL_CSEL); 369 sis_delay(sc); 370 371 /* 372 * Send address of word we want to read. 373 */ 374 sis_eeprom_putbyte(sc, addr); 375 376 /* 377 * Start reading bits from EEPROM. 378 */ 379 for (i = 0x8000; i; i >>= 1) { 380 SIO_SET(SIS_EECTL_CLK); 381 sis_delay(sc); 382 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 383 word |= i; 384 sis_delay(sc); 385 SIO_CLR(SIS_EECTL_CLK); 386 sis_delay(sc); 387 } 388 389 /* Turn off EEPROM access mode. */ 390 sis_eeprom_idle(sc); 391 392 *dest = word; 393 394 return; 395} 396 397/* 398 * Read a sequence of words from the EEPROM. 399 */ 400static void 401sis_read_eeprom(sc, dest, off, cnt, swap) 402 struct sis_softc *sc; 403 caddr_t dest; 404 int off; 405 int cnt; 406 int swap; 407{ 408 int i; 409 u_int16_t word = 0, *ptr; 410 411 for (i = 0; i < cnt; i++) { 412 sis_eeprom_getword(sc, off + i, &word); 413 ptr = (u_int16_t *)(dest + (i * 2)); 414 if (swap) 415 *ptr = ntohs(word); 416 else 417 *ptr = word; 418 } 419 420 return; 421} 422 423#ifdef __i386__ 424static device_t 425sis_find_bridge(dev) 426 device_t dev; 427{ 428 devclass_t pci_devclass; 429 device_t *pci_devices; 430 int pci_count = 0; 431 device_t *pci_children; 432 int pci_childcount = 0; 433 device_t *busp, *childp; 434 device_t child = NULL; 435 int i, j; 436 437 if ((pci_devclass = devclass_find("pci")) == NULL) 438 return(NULL); 439 440 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 441 442 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 443 pci_childcount = 0; 444 device_get_children(*busp, &pci_children, &pci_childcount); 445 for (j = 0, childp = pci_children; 446 j < pci_childcount; j++, childp++) { 447 if (pci_get_vendor(*childp) == SIS_VENDORID && 448 pci_get_device(*childp) == 0x0008) { 449 child = *childp; 450 goto done; 451 } 452 } 453 } 454 455done: 456 free(pci_devices, M_TEMP); 457 free(pci_children, M_TEMP); 458 return(child); 459} 460 461static void 462sis_read_cmos(sc, dev, dest, off, cnt) 463 struct sis_softc *sc; 464 device_t dev; 465 caddr_t dest; 466 int off; 467 int cnt; 468{ 469 device_t bridge; 470 u_int8_t reg; 471 int i; 472 bus_space_tag_t btag; 473 474 bridge = sis_find_bridge(dev); 475 if (bridge == NULL) 476 return; 477 reg = pci_read_config(bridge, 0x48, 1); 478 pci_write_config(bridge, 0x48, reg|0x40, 1); 479 480 /* XXX */ 481 btag = I386_BUS_SPACE_IO; 482 483 for (i = 0; i < cnt; i++) { 484 bus_space_write_1(btag, 0x0, 0x70, i + off); 485 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 486 } 487 488 pci_write_config(bridge, 0x48, reg & ~0x40, 1); 489 return; 490} 491 492static void 493sis_read_mac(sc, dev, dest) 494 struct sis_softc *sc; 495 device_t dev; 496 caddr_t dest; 497{ 498 u_int32_t filtsave, csrsave; 499 500 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 501 csrsave = CSR_READ_4(sc, SIS_CSR); 502 503 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 504 CSR_WRITE_4(sc, SIS_CSR, 0); 505 506 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 507 508 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 509 ((u_int16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 510 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 511 ((u_int16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 512 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 513 ((u_int16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 514 515 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 516 CSR_WRITE_4(sc, SIS_CSR, csrsave); 517 return; 518} 519#endif 520 521/* 522 * Sync the PHYs by setting data bit and strobing the clock 32 times. 523 */ 524static void sis_mii_sync(sc) 525 struct sis_softc *sc; 526{ 527 register int i; 528 529 SIO_SET(SIS_MII_DIR|SIS_MII_DATA); 530 531 for (i = 0; i < 32; i++) { 532 SIO_SET(SIS_MII_CLK); 533 DELAY(1); 534 SIO_CLR(SIS_MII_CLK); 535 DELAY(1); 536 } 537 538 return; 539} 540 541/* 542 * Clock a series of bits through the MII. 543 */ 544static void sis_mii_send(sc, bits, cnt) 545 struct sis_softc *sc; 546 u_int32_t bits; 547 int cnt; 548{ 549 int i; 550 551 SIO_CLR(SIS_MII_CLK); 552 553 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 554 if (bits & i) { 555 SIO_SET(SIS_MII_DATA); 556 } else { 557 SIO_CLR(SIS_MII_DATA); 558 } 559 DELAY(1); 560 SIO_CLR(SIS_MII_CLK); 561 DELAY(1); 562 SIO_SET(SIS_MII_CLK); 563 } 564} 565 566/* 567 * Read an PHY register through the MII. 568 */ 569static int sis_mii_readreg(sc, frame) 570 struct sis_softc *sc; 571 struct sis_mii_frame *frame; 572 573{ 574 int i, ack, s; 575 576 s = splimp(); 577 578 /* 579 * Set up frame for RX. 580 */ 581 frame->mii_stdelim = SIS_MII_STARTDELIM; 582 frame->mii_opcode = SIS_MII_READOP; 583 frame->mii_turnaround = 0; 584 frame->mii_data = 0; 585 586 /* 587 * Turn on data xmit. 588 */ 589 SIO_SET(SIS_MII_DIR); 590 591 sis_mii_sync(sc); 592 593 /* 594 * Send command/address info. 595 */ 596 sis_mii_send(sc, frame->mii_stdelim, 2); 597 sis_mii_send(sc, frame->mii_opcode, 2); 598 sis_mii_send(sc, frame->mii_phyaddr, 5); 599 sis_mii_send(sc, frame->mii_regaddr, 5); 600 601 /* Idle bit */ 602 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA)); 603 DELAY(1); 604 SIO_SET(SIS_MII_CLK); 605 DELAY(1); 606 607 /* Turn off xmit. */ 608 SIO_CLR(SIS_MII_DIR); 609 610 /* Check for ack */ 611 SIO_CLR(SIS_MII_CLK); 612 DELAY(1); 613 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA; 614 SIO_SET(SIS_MII_CLK); 615 DELAY(1); 616 617 /* 618 * Now try reading data bits. If the ack failed, we still 619 * need to clock through 16 cycles to keep the PHY(s) in sync. 620 */ 621 if (ack) { 622 for(i = 0; i < 16; i++) { 623 SIO_CLR(SIS_MII_CLK); 624 DELAY(1); 625 SIO_SET(SIS_MII_CLK); 626 DELAY(1); 627 } 628 goto fail; 629 } 630 631 for (i = 0x8000; i; i >>= 1) { 632 SIO_CLR(SIS_MII_CLK); 633 DELAY(1); 634 if (!ack) { 635 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA) 636 frame->mii_data |= i; 637 DELAY(1); 638 } 639 SIO_SET(SIS_MII_CLK); 640 DELAY(1); 641 } 642 643fail: 644 645 SIO_CLR(SIS_MII_CLK); 646 DELAY(1); 647 SIO_SET(SIS_MII_CLK); 648 DELAY(1); 649 650 splx(s); 651 652 if (ack) 653 return(1); 654 return(0); 655} 656 657/* 658 * Write to a PHY register through the MII. 659 */ 660static int sis_mii_writereg(sc, frame) 661 struct sis_softc *sc; 662 struct sis_mii_frame *frame; 663 664{ 665 int s; 666 667 s = splimp(); 668 /* 669 * Set up frame for TX. 670 */ 671 672 frame->mii_stdelim = SIS_MII_STARTDELIM; 673 frame->mii_opcode = SIS_MII_WRITEOP; 674 frame->mii_turnaround = SIS_MII_TURNAROUND; 675 676 /* 677 * Turn on data output. 678 */ 679 SIO_SET(SIS_MII_DIR); 680 681 sis_mii_sync(sc); 682 683 sis_mii_send(sc, frame->mii_stdelim, 2); 684 sis_mii_send(sc, frame->mii_opcode, 2); 685 sis_mii_send(sc, frame->mii_phyaddr, 5); 686 sis_mii_send(sc, frame->mii_regaddr, 5); 687 sis_mii_send(sc, frame->mii_turnaround, 2); 688 sis_mii_send(sc, frame->mii_data, 16); 689 690 /* Idle bit. */ 691 SIO_SET(SIS_MII_CLK); 692 DELAY(1); 693 SIO_CLR(SIS_MII_CLK); 694 DELAY(1); 695 696 /* 697 * Turn off xmit. 698 */ 699 SIO_CLR(SIS_MII_DIR); 700 701 splx(s); 702 703 return(0); 704} 705 706static int 707sis_miibus_readreg(dev, phy, reg) 708 device_t dev; 709 int phy, reg; 710{ 711 struct sis_softc *sc; 712 struct sis_mii_frame frame; 713 714 sc = device_get_softc(dev); 715 716 if (sc->sis_type == SIS_TYPE_83815) { 717 if (phy != 0) 718 return(0); 719 /* 720 * The NatSemi chip can take a while after 721 * a reset to come ready, during which the BMSR 722 * returns a value of 0. This is *never* supposed 723 * to happen: some of the BMSR bits are meant to 724 * be hardwired in the on position, and this can 725 * confuse the miibus code a bit during the probe 726 * and attach phase. So we make an effort to check 727 * for this condition and wait for it to clear. 728 */ 729 if (!CSR_READ_4(sc, NS_BMSR)) 730 DELAY(1000); 731 return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 732 } 733 734 /* 735 * Chipsets < SIS_635 seem not to be able to read/write 736 * through mdio. Use the enhanced PHY access register 737 * again for them. 738 */ 739 if (sc->sis_type == SIS_TYPE_900 && 740 sc->sis_rev < SIS_REV_635) { 741 int i, val = 0; 742 743 if (phy != 0) 744 return(0); 745 746 CSR_WRITE_4(sc, SIS_PHYCTL, 747 (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 748 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 749 750 for (i = 0; i < SIS_TIMEOUT; i++) { 751 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 752 break; 753 } 754 755 if (i == SIS_TIMEOUT) { 756 printf("sis%d: PHY failed to come ready\n", 757 sc->sis_unit); 758 return(0); 759 } 760 761 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 762 763 if (val == 0xFFFF) 764 return(0); 765 766 return(val); 767 } else { 768 bzero((char *)&frame, sizeof(frame)); 769 770 frame.mii_phyaddr = phy; 771 frame.mii_regaddr = reg; 772 sis_mii_readreg(sc, &frame); 773 774 return(frame.mii_data); 775 } 776} 777 778static int 779sis_miibus_writereg(dev, phy, reg, data) 780 device_t dev; 781 int phy, reg, data; 782{ 783 struct sis_softc *sc; 784 struct sis_mii_frame frame; 785 786 sc = device_get_softc(dev); 787 788 if (sc->sis_type == SIS_TYPE_83815) { 789 if (phy != 0) 790 return(0); 791 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 792 return(0); 793 } 794 795 /* 796 * Chipsets < SIS_635 seem not to be able to read/write 797 * through mdio. Use the enhanced PHY access register 798 * again for them. 799 */ 800 if (sc->sis_type == SIS_TYPE_900 && 801 sc->sis_rev < SIS_REV_635) { 802 int i; 803 804 if (phy != 0) 805 return(0); 806 807 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 808 (reg << 6) | SIS_PHYOP_WRITE); 809 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 810 811 for (i = 0; i < SIS_TIMEOUT; i++) { 812 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 813 break; 814 } 815 816 if (i == SIS_TIMEOUT) 817 printf("sis%d: PHY failed to come ready\n", 818 sc->sis_unit); 819 } else { 820 bzero((char *)&frame, sizeof(frame)); 821 822 frame.mii_phyaddr = phy; 823 frame.mii_regaddr = reg; 824 frame.mii_data = data; 825 sis_mii_writereg(sc, &frame); 826 } 827 return(0); 828} 829 830static void 831sis_miibus_statchg(dev) 832 device_t dev; 833{ 834 struct sis_softc *sc; 835 836 sc = device_get_softc(dev); 837 sis_init(sc); 838 839 return; 840} 841 842static u_int32_t 843sis_crc(sc, addr) 844 struct sis_softc *sc; 845 caddr_t addr; 846{ 847 u_int32_t crc, carry; 848 int i, j; 849 u_int8_t c; 850 851 /* Compute CRC for the address value. */ 852 crc = 0xFFFFFFFF; /* initial value */ 853 854 for (i = 0; i < 6; i++) { 855 c = *(addr + i); 856 for (j = 0; j < 8; j++) { 857 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 858 crc <<= 1; 859 c >>= 1; 860 if (carry) 861 crc = (crc ^ 0x04c11db6) | carry; 862 } 863 } 864 865 /* 866 * return the filter bit position 867 * 868 * The NatSemi chip has a 512-bit filter, which is 869 * different than the SiS, so we special-case it. 870 */ 871 if (sc->sis_type == SIS_TYPE_83815) 872 return (crc >> 23); 873 else if (sc->sis_rev >= SIS_REV_635 || 874 sc->sis_rev == SIS_REV_900B) 875 return (crc >> 24); 876 else 877 return (crc >> 25); 878} 879 880static void 881sis_setmulti_ns(sc) 882 struct sis_softc *sc; 883{ 884 struct ifnet *ifp; 885 struct ifmultiaddr *ifma; 886 u_int32_t h = 0, i, filtsave; 887 int bit, index; 888 889 ifp = &sc->arpcom.ac_if; 890 891 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 892 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 893 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 894 return; 895 } 896 897 /* 898 * We have to explicitly enable the multicast hash table 899 * on the NatSemi chip if we want to use it, which we do. 900 */ 901 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 902 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 903 904 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 905 906 /* first, zot all the existing hash bits */ 907 for (i = 0; i < 32; i++) { 908 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 909 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 910 } 911 912 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 913 if (ifma->ifma_addr->sa_family != AF_LINK) 914 continue; 915 h = sis_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 916 index = h >> 3; 917 bit = h & 0x1F; 918 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 919 if (bit > 0xF) 920 bit -= 0x10; 921 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 922 } 923 924 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 925 926 return; 927} 928 929static void 930sis_setmulti_sis(sc) 931 struct sis_softc *sc; 932{ 933 struct ifnet *ifp; 934 struct ifmultiaddr *ifma; 935 u_int32_t h, i, n, ctl; 936 u_int16_t hashes[16]; 937 938 ifp = &sc->arpcom.ac_if; 939 940 /* hash table size */ 941 if (sc->sis_rev >= SIS_REV_635 || 942 sc->sis_rev == SIS_REV_900B) 943 n = 16; 944 else 945 n = 8; 946 947 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE; 948 949 if (ifp->if_flags & IFF_BROADCAST) 950 ctl |= SIS_RXFILTCTL_BROAD; 951 952 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 953 ctl |= SIS_RXFILTCTL_ALLMULTI; 954 if (ifp->if_flags & IFF_PROMISC) 955 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS; 956 for (i = 0; i < n; i++) 957 hashes[i] = ~0; 958 } else { 959 for (i = 0; i < n; i++) 960 hashes[i] = 0; 961 i = 0; 962 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 963 if (ifma->ifma_addr->sa_family != AF_LINK) 964 continue; 965 h = sis_crc(sc, 966 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 967 hashes[h >> 4] |= 1 << (h & 0xf); 968 i++; 969 } 970 if (i > n) { 971 ctl |= SIS_RXFILTCTL_ALLMULTI; 972 for (i = 0; i < n; i++) 973 hashes[i] = ~0; 974 } 975 } 976 977 for (i = 0; i < n; i++) { 978 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); 979 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); 980 } 981 982 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl); 983} 984 985static void 986sis_reset(sc) 987 struct sis_softc *sc; 988{ 989 register int i; 990 991 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 992 993 for (i = 0; i < SIS_TIMEOUT; i++) { 994 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 995 break; 996 } 997 998 if (i == SIS_TIMEOUT) 999 printf("sis%d: reset never completed\n", sc->sis_unit); 1000 1001 /* Wait a little while for the chip to get its brains in order. */ 1002 DELAY(1000); 1003 1004 /* 1005 * If this is a NetSemi chip, make sure to clear 1006 * PME mode. 1007 */ 1008 if (sc->sis_type == SIS_TYPE_83815) { 1009 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 1010 CSR_WRITE_4(sc, NS_CLKRUN, 0); 1011 } 1012 1013 return; 1014} 1015 1016/* 1017 * Probe for an SiS chip. Check the PCI vendor and device 1018 * IDs against our list and return a device name if we find a match. 1019 */ 1020static int 1021sis_probe(dev) 1022 device_t dev; 1023{ 1024 struct sis_type *t; 1025 1026 t = sis_devs; 1027 1028 while(t->sis_name != NULL) { 1029 if ((pci_get_vendor(dev) == t->sis_vid) && 1030 (pci_get_device(dev) == t->sis_did)) { 1031 device_set_desc(dev, t->sis_name); 1032 return(0); 1033 } 1034 t++; 1035 } 1036 1037 return(ENXIO); 1038} 1039 1040/* 1041 * Attach the interface. Allocate softc structures, do ifmedia 1042 * setup and ethernet/BPF attach. 1043 */ 1044static int 1045sis_attach(dev) 1046 device_t dev; 1047{ 1048 u_char eaddr[ETHER_ADDR_LEN]; 1049 u_int32_t command; 1050 struct sis_softc *sc; 1051 struct ifnet *ifp; 1052 int unit, error = 0, rid, waittime = 0; 1053 1054 waittime = 0; 1055 sc = device_get_softc(dev); 1056 unit = device_get_unit(dev); 1057 1058 mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1059 MTX_DEF | MTX_RECURSE); 1060 1061 if (pci_get_device(dev) == SIS_DEVICEID_900) 1062 sc->sis_type = SIS_TYPE_900; 1063 if (pci_get_device(dev) == SIS_DEVICEID_7016) 1064 sc->sis_type = SIS_TYPE_7016; 1065 if (pci_get_vendor(dev) == NS_VENDORID) 1066 sc->sis_type = SIS_TYPE_83815; 1067 1068 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 1069 1070 /* 1071 * Handle power management nonsense. 1072 */ 1073 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1074 u_int32_t iobase, membase, irq; 1075 1076 /* Save important PCI config data. */ 1077 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4); 1078 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4); 1079 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4); 1080 1081 /* Reset the power state. */ 1082 printf("sis%d: chip is in D%d power mode " 1083 "-- setting to D0\n", unit, 1084 pci_get_powerstate(dev)); 1085 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1086 1087 /* Restore PCI config data. */ 1088 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4); 1089 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4); 1090 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4); 1091 } 1092 1093 /* 1094 * Map control/status registers. 1095 */ 1096 pci_enable_busmaster(dev); 1097 pci_enable_io(dev, SYS_RES_IOPORT); 1098 pci_enable_io(dev, SYS_RES_MEMORY); 1099 command = pci_read_config(dev, PCIR_COMMAND, 4); 1100 1101#ifdef SIS_USEIOSPACE 1102 if (!(command & PCIM_CMD_PORTEN)) { 1103 printf("sis%d: failed to enable I/O ports!\n", unit); 1104 error = ENXIO; 1105 goto fail; 1106 } 1107#else 1108 if (!(command & PCIM_CMD_MEMEN)) { 1109 printf("sis%d: failed to enable memory mapping!\n", unit); 1110 error = ENXIO; 1111 goto fail; 1112 } 1113#endif 1114 1115 rid = SIS_RID; 1116 sc->sis_res = bus_alloc_resource(dev, SIS_RES, &rid, 1117 0, ~0, 1, RF_ACTIVE); 1118 1119 if (sc->sis_res == NULL) { 1120 printf("sis%d: couldn't map ports/memory\n", unit); 1121 error = ENXIO; 1122 goto fail; 1123 } 1124 1125 sc->sis_btag = rman_get_bustag(sc->sis_res); 1126 sc->sis_bhandle = rman_get_bushandle(sc->sis_res); 1127 1128 /* Allocate interrupt */ 1129 rid = 0; 1130 sc->sis_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1131 RF_SHAREABLE | RF_ACTIVE); 1132 1133 if (sc->sis_irq == NULL) { 1134 printf("sis%d: couldn't map interrupt\n", unit); 1135 error = ENXIO; 1136 goto fail; 1137 } 1138 1139 /* Reset the adapter. */ 1140 sis_reset(sc); 1141 1142 if (sc->sis_type == SIS_TYPE_900 && 1143 (sc->sis_rev == SIS_REV_635 || 1144 sc->sis_rev == SIS_REV_900B)) { 1145 SIO_SET(SIS_CFG_RND_CNT); 1146 SIO_SET(SIS_CFG_PERR_DETECT); 1147 } 1148 1149 /* 1150 * Get station address from the EEPROM. 1151 */ 1152 switch (pci_get_vendor(dev)) { 1153 case NS_VENDORID: 1154 /* 1155 * Reading the MAC address out of the EEPROM on 1156 * the NatSemi chip takes a bit more work than 1157 * you'd expect. The address spans 4 16-bit words, 1158 * with the first word containing only a single bit. 1159 * You have to shift everything over one bit to 1160 * get it aligned properly. Also, the bits are 1161 * stored backwards (the LSB is really the MSB, 1162 * and so on) so you have to reverse them in order 1163 * to get the MAC address into the form we want. 1164 * Why? Who the hell knows. 1165 */ 1166 { 1167 u_int16_t tmp[4]; 1168 1169 sis_read_eeprom(sc, (caddr_t)&tmp, 1170 NS_EE_NODEADDR, 4, 0); 1171 1172 /* Shift everything over one bit. */ 1173 tmp[3] = tmp[3] >> 1; 1174 tmp[3] |= tmp[2] << 15; 1175 tmp[2] = tmp[2] >> 1; 1176 tmp[2] |= tmp[1] << 15; 1177 tmp[1] = tmp[1] >> 1; 1178 tmp[1] |= tmp[0] << 15; 1179 1180 /* Now reverse all the bits. */ 1181 tmp[3] = sis_reverse(tmp[3]); 1182 tmp[2] = sis_reverse(tmp[2]); 1183 tmp[1] = sis_reverse(tmp[1]); 1184 1185 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); 1186 } 1187 break; 1188 case SIS_VENDORID: 1189 default: 1190#ifdef __i386__ 1191 /* 1192 * If this is a SiS 630E chipset with an embedded 1193 * SiS 900 controller, we have to read the MAC address 1194 * from the APC CMOS RAM. Our method for doing this 1195 * is very ugly since we have to reach out and grab 1196 * ahold of hardware for which we cannot properly 1197 * allocate resources. This code is only compiled on 1198 * the i386 architecture since the SiS 630E chipset 1199 * is for x86 motherboards only. Note that there are 1200 * a lot of magic numbers in this hack. These are 1201 * taken from SiS's Linux driver. I'd like to replace 1202 * them with proper symbolic definitions, but that 1203 * requires some datasheets that I don't have access 1204 * to at the moment. 1205 */ 1206 if (sc->sis_rev == SIS_REV_630S || 1207 sc->sis_rev == SIS_REV_630E || 1208 sc->sis_rev == SIS_REV_630EA1) 1209 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 1210 1211 else if (sc->sis_rev == SIS_REV_635 || 1212 sc->sis_rev == SIS_REV_630ET) 1213 sis_read_mac(sc, dev, (caddr_t)&eaddr); 1214 else if (sc->sis_rev == SIS_REV_96x) { 1215 /* Allow to read EEPROM from LAN. It is shared 1216 * between a 1394 controller and the NIC and each 1217 * time we access it, we need to set SIS_EECMD_REQ. 1218 */ 1219 SIO_SET(SIS_EECMD_REQ); 1220 for (waittime = 0; waittime < SIS_TIMEOUT; 1221 waittime++) { 1222 /* Force EEPROM to idle state. */ 1223 sis_eeprom_idle(sc); 1224 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { 1225 sis_read_eeprom(sc, (caddr_t)&eaddr, 1226 SIS_EE_NODEADDR, 3, 0); 1227 break; 1228 } 1229 DELAY(1); 1230 } 1231 /* 1232 * Set SIS_EECTL_CLK to high, so a other master 1233 * can operate on the i2c bus. 1234 */ 1235 SIO_SET(SIS_EECTL_CLK); 1236 /* Refuse EEPROM access by LAN */ 1237 SIO_SET(SIS_EECMD_DONE); 1238 } else 1239#endif 1240 sis_read_eeprom(sc, (caddr_t)&eaddr, 1241 SIS_EE_NODEADDR, 3, 0); 1242 break; 1243 } 1244 1245 /* 1246 * A SiS chip was detected. Inform the world. 1247 */ 1248 printf("sis%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1249 1250 sc->sis_unit = unit; 1251 callout_handle_init(&sc->sis_stat_ch); 1252 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1253 1254 /* 1255 * Allocate the parent bus DMA tag appropriate for PCI. 1256 */ 1257#define SIS_NSEG_NEW 32 1258 error = bus_dma_tag_create(NULL, /* parent */ 1259 1, 0, /* alignment, boundary */ 1260 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1261 BUS_SPACE_MAXADDR, /* highaddr */ 1262 NULL, NULL, /* filter, filterarg */ 1263 MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */ 1264 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1265 BUS_DMA_ALLOCNOW, /* flags */ 1266 &sc->sis_parent_tag); 1267 if (error) 1268 goto fail; 1269 1270 /* 1271 * Now allocate a tag for the DMA descriptor lists and a chunk 1272 * of DMA-able memory based on the tag. Also obtain the physical 1273 * addresses of the RX and TX ring, which we'll need later. 1274 * All of our lists are allocated as a contiguous block 1275 * of memory. 1276 */ 1277 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1278 1, 0, /* alignment, boundary */ 1279 BUS_SPACE_MAXADDR, /* lowaddr */ 1280 BUS_SPACE_MAXADDR, /* highaddr */ 1281 NULL, NULL, /* filter, filterarg */ 1282 SIS_RX_LIST_SZ, 1, /* maxsize,nsegments */ 1283 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1284 0, /* flags */ 1285 &sc->sis_ldata.sis_rx_tag); 1286 if (error) 1287 goto fail; 1288 1289 error = bus_dmamem_alloc(sc->sis_ldata.sis_rx_tag, 1290 (void **)&sc->sis_ldata.sis_rx_list, BUS_DMA_NOWAIT, 1291 &sc->sis_ldata.sis_rx_dmamap); 1292 1293 if (error) { 1294 printf("sis%d: no memory for rx list buffers!\n", unit); 1295 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1296 sc->sis_ldata.sis_rx_tag = NULL; 1297 goto fail; 1298 } 1299 1300 error = bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1301 sc->sis_ldata.sis_rx_dmamap, &(sc->sis_ldata.sis_rx_list[0]), 1302 sizeof(struct sis_desc), sis_dma_map_ring, 1303 &sc->sis_cdata.sis_rx_paddr, 0); 1304 1305 if (error) { 1306 printf("sis%d: cannot get address of the rx ring!\n", unit); 1307 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1308 sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap); 1309 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1310 sc->sis_ldata.sis_rx_tag = NULL; 1311 goto fail; 1312 } 1313 1314 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1315 1, 0, /* alignment, boundary */ 1316 BUS_SPACE_MAXADDR, /* lowaddr */ 1317 BUS_SPACE_MAXADDR, /* highaddr */ 1318 NULL, NULL, /* filter, filterarg */ 1319 SIS_TX_LIST_SZ, 1, /* maxsize,nsegments */ 1320 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1321 0, /* flags */ 1322 &sc->sis_ldata.sis_tx_tag); 1323 if (error) 1324 goto fail; 1325 1326 error = bus_dmamem_alloc(sc->sis_ldata.sis_tx_tag, 1327 (void **)&sc->sis_ldata.sis_tx_list, BUS_DMA_NOWAIT, 1328 &sc->sis_ldata.sis_tx_dmamap); 1329 1330 if (error) { 1331 printf("sis%d: no memory for tx list buffers!\n", unit); 1332 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1333 sc->sis_ldata.sis_tx_tag = NULL; 1334 goto fail; 1335 } 1336 1337 error = bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1338 sc->sis_ldata.sis_tx_dmamap, &(sc->sis_ldata.sis_tx_list[0]), 1339 sizeof(struct sis_desc), sis_dma_map_ring, 1340 &sc->sis_cdata.sis_tx_paddr, 0); 1341 1342 if (error) { 1343 printf("sis%d: cannot get address of the tx ring!\n", unit); 1344 bus_dmamem_free(sc->sis_ldata.sis_tx_tag, 1345 sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 1346 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1347 sc->sis_ldata.sis_tx_tag = NULL; 1348 goto fail; 1349 } 1350 1351 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1352 1, 0, /* alignment, boundary */ 1353 BUS_SPACE_MAXADDR, /* lowaddr */ 1354 BUS_SPACE_MAXADDR, /* highaddr */ 1355 NULL, NULL, /* filter, filterarg */ 1356 MCLBYTES, 1, /* maxsize,nsegments */ 1357 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1358 0, /* flags */ 1359 &sc->sis_tag); 1360 if (error) 1361 goto fail; 1362 1363 bzero(sc->sis_ldata.sis_tx_list, SIS_TX_LIST_SZ); 1364 bzero(sc->sis_ldata.sis_rx_list, SIS_RX_LIST_SZ); 1365 1366 /* 1367 * Obtain the physical addresses of the RX and TX 1368 * rings which we'll need later in the init routine. 1369 */ 1370 1371 ifp = &sc->arpcom.ac_if; 1372 ifp->if_softc = sc; 1373 ifp->if_unit = unit; 1374 ifp->if_name = "sis"; 1375 ifp->if_mtu = ETHERMTU; 1376 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1377 ifp->if_ioctl = sis_ioctl; 1378 ifp->if_output = ether_output; 1379 ifp->if_start = sis_start; 1380 ifp->if_watchdog = sis_watchdog; 1381 ifp->if_init = sis_init; 1382 ifp->if_baudrate = 10000000; 1383 ifp->if_snd.ifq_maxlen = SIS_TX_LIST_CNT - 1; 1384 1385 /* 1386 * Do MII setup. 1387 */ 1388 if (mii_phy_probe(dev, &sc->sis_miibus, 1389 sis_ifmedia_upd, sis_ifmedia_sts)) { 1390 printf("sis%d: MII without any PHY!\n", sc->sis_unit); 1391 error = ENXIO; 1392 goto fail; 1393 } 1394 1395 callout_handle_init(&sc->sis_stat_ch); 1396 1397 /* 1398 * Call MI attach routine. 1399 */ 1400 ether_ifattach(ifp, eaddr); 1401 1402 /* 1403 * Tell the upper layer(s) we support long frames. 1404 */ 1405 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1406 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1407 1408 error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET, 1409 sis_intr, sc, &sc->sis_intrhand); 1410 1411 if (error) { 1412 printf("sis%d: couldn't set up irq\n", unit); 1413 goto fail; 1414 } 1415 1416fail: 1417 if (error) 1418 sis_detach(dev); 1419 1420 return(error); 1421} 1422 1423static int 1424sis_detach(dev) 1425 device_t dev; 1426{ 1427 struct sis_softc *sc; 1428 struct ifnet *ifp; 1429 1430 sc = device_get_softc(dev); 1431 KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized")); 1432 SIS_LOCK(sc); 1433 ifp = &sc->arpcom.ac_if; 1434 1435 if (device_is_alive(dev)) { 1436 if (bus_child_present(dev)) { 1437 sis_reset(sc); 1438 sis_stop(sc); 1439 } 1440 ether_ifdetach(ifp); 1441 device_delete_child(dev, sc->sis_miibus); 1442 bus_generic_detach(dev); 1443 } 1444 1445 if (sc->sis_intrhand) 1446 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1447 if (sc->sis_irq) 1448 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1449 if (sc->sis_res) 1450 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1451 1452 if (sc->sis_ldata.sis_rx_tag) { 1453 bus_dmamap_unload(sc->sis_ldata.sis_rx_tag, 1454 sc->sis_ldata.sis_rx_dmamap); 1455 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1456 sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap); 1457 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1458 } 1459 if (sc->sis_ldata.sis_tx_tag) { 1460 bus_dmamap_unload(sc->sis_ldata.sis_tx_tag, 1461 sc->sis_ldata.sis_tx_dmamap); 1462 bus_dmamem_free(sc->sis_ldata.sis_tx_tag, 1463 sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 1464 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1465 } 1466 if (sc->sis_parent_tag) 1467 bus_dma_tag_destroy(sc->sis_parent_tag); 1468 if (sc->sis_tag) 1469 bus_dma_tag_destroy(sc->sis_tag); 1470 1471 SIS_UNLOCK(sc); 1472 mtx_destroy(&sc->sis_mtx); 1473 1474 return(0); 1475} 1476 1477/* 1478 * Initialize the transmit descriptors. 1479 */ 1480static int 1481sis_list_tx_init(sc) 1482 struct sis_softc *sc; 1483{ 1484 struct sis_list_data *ld; 1485 struct sis_ring_data *cd; 1486 int i, nexti; 1487 1488 cd = &sc->sis_cdata; 1489 ld = &sc->sis_ldata; 1490 1491 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1492 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1; 1493 ld->sis_tx_list[i].sis_nextdesc = 1494 &ld->sis_tx_list[nexti]; 1495 bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1496 sc->sis_ldata.sis_tx_dmamap, 1497 &ld->sis_tx_list[nexti], sizeof(struct sis_desc), 1498 sis_dma_map_desc_next, &ld->sis_tx_list[i], 0); 1499 ld->sis_tx_list[i].sis_mbuf = NULL; 1500 ld->sis_tx_list[i].sis_ptr = 0; 1501 ld->sis_tx_list[i].sis_ctl = 0; 1502 } 1503 1504 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0; 1505 1506 bus_dmamap_sync(sc->sis_ldata.sis_tx_tag, 1507 sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 1508 1509 return(0); 1510} 1511 1512/* 1513 * Initialize the RX descriptors and allocate mbufs for them. Note that 1514 * we arrange the descriptors in a closed ring, so that the last descriptor 1515 * points back to the first. 1516 */ 1517static int 1518sis_list_rx_init(sc) 1519 struct sis_softc *sc; 1520{ 1521 struct sis_list_data *ld; 1522 struct sis_ring_data *cd; 1523 int i,nexti; 1524 1525 ld = &sc->sis_ldata; 1526 cd = &sc->sis_cdata; 1527 1528 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1529 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS) 1530 return(ENOBUFS); 1531 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1; 1532 ld->sis_rx_list[i].sis_nextdesc = 1533 &ld->sis_rx_list[nexti]; 1534 bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1535 sc->sis_ldata.sis_rx_dmamap, 1536 &ld->sis_rx_list[nexti], 1537 sizeof(struct sis_desc), sis_dma_map_desc_next, 1538 &ld->sis_rx_list[i], 0); 1539 } 1540 1541 bus_dmamap_sync(sc->sis_ldata.sis_rx_tag, 1542 sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 1543 1544 cd->sis_rx_prod = 0; 1545 1546 return(0); 1547} 1548 1549/* 1550 * Initialize an RX descriptor and attach an MBUF cluster. 1551 */ 1552static int 1553sis_newbuf(sc, c, m) 1554 struct sis_softc *sc; 1555 struct sis_desc *c; 1556 struct mbuf *m; 1557{ 1558 1559 if (c == NULL) 1560 return(EINVAL); 1561 1562 if (m == NULL) { 1563 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1564 if (m == NULL) 1565 return(ENOBUFS); 1566 } else 1567 m->m_data = m->m_ext.ext_buf; 1568 1569 c->sis_mbuf = m; 1570 c->sis_ctl = SIS_RXLEN; 1571 1572 bus_dmamap_create(sc->sis_tag, 0, &c->sis_map); 1573 bus_dmamap_load(sc->sis_tag, c->sis_map, 1574 mtod(m, void *), MCLBYTES, 1575 sis_dma_map_desc_ptr, c, 0); 1576 bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREWRITE); 1577 1578 return(0); 1579} 1580 1581/* 1582 * A frame has been uploaded: pass the resulting mbuf chain up to 1583 * the higher level protocols. 1584 */ 1585static void 1586sis_rxeof(sc) 1587 struct sis_softc *sc; 1588{ 1589 struct mbuf *m; 1590 struct ifnet *ifp; 1591 struct sis_desc *cur_rx; 1592 int i, total_len = 0; 1593 u_int32_t rxstat; 1594 1595 ifp = &sc->arpcom.ac_if; 1596 i = sc->sis_cdata.sis_rx_prod; 1597 1598 while(SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) { 1599 1600#ifdef DEVICE_POLLING 1601 if (ifp->if_flags & IFF_POLLING) { 1602 if (sc->rxcycles <= 0) 1603 break; 1604 sc->rxcycles--; 1605 } 1606#endif /* DEVICE_POLLING */ 1607 cur_rx = &sc->sis_ldata.sis_rx_list[i]; 1608 rxstat = cur_rx->sis_rxstat; 1609 bus_dmamap_sync(sc->sis_tag, 1610 cur_rx->sis_map, BUS_DMASYNC_POSTWRITE); 1611 bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map); 1612 bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map); 1613 m = cur_rx->sis_mbuf; 1614 cur_rx->sis_mbuf = NULL; 1615 total_len = SIS_RXBYTES(cur_rx); 1616 SIS_INC(i, SIS_RX_LIST_CNT); 1617 1618 /* 1619 * If an error occurs, update stats, clear the 1620 * status word and leave the mbuf cluster in place: 1621 * it should simply get re-used next time this descriptor 1622 * comes up in the ring. 1623 */ 1624 if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 1625 ifp->if_ierrors++; 1626 if (rxstat & SIS_RXSTAT_COLL) 1627 ifp->if_collisions++; 1628 sis_newbuf(sc, cur_rx, m); 1629 continue; 1630 } 1631 1632 /* No errors; receive the packet. */ 1633#ifdef __i386__ 1634 /* 1635 * On the x86 we do not have alignment problems, so try to 1636 * allocate a new buffer for the receive ring, and pass up 1637 * the one where the packet is already, saving the expensive 1638 * copy done in m_devget(). 1639 * If we are on an architecture with alignment problems, or 1640 * if the allocation fails, then use m_devget and leave the 1641 * existing buffer in the receive ring. 1642 */ 1643 if (sis_newbuf(sc, cur_rx, NULL) == 0) 1644 m->m_pkthdr.len = m->m_len = total_len; 1645 else 1646#endif 1647 { 1648 struct mbuf *m0; 1649 m0 = m_devget(mtod(m, char *), total_len, 1650 ETHER_ALIGN, ifp, NULL); 1651 sis_newbuf(sc, cur_rx, m); 1652 if (m0 == NULL) { 1653 ifp->if_ierrors++; 1654 continue; 1655 } 1656 m = m0; 1657 } 1658 1659 ifp->if_ipackets++; 1660 m->m_pkthdr.rcvif = ifp; 1661 1662 (*ifp->if_input)(ifp, m); 1663 } 1664 1665 sc->sis_cdata.sis_rx_prod = i; 1666 1667 return; 1668} 1669 1670static void 1671sis_rxeoc(sc) 1672 struct sis_softc *sc; 1673{ 1674 sis_rxeof(sc); 1675 sis_init(sc); 1676 return; 1677} 1678 1679/* 1680 * A frame was downloaded to the chip. It's safe for us to clean up 1681 * the list buffers. 1682 */ 1683 1684static void 1685sis_txeof(sc) 1686 struct sis_softc *sc; 1687{ 1688 struct ifnet *ifp; 1689 u_int32_t idx; 1690 1691 ifp = &sc->arpcom.ac_if; 1692 1693 /* 1694 * Go through our tx list and free mbufs for those 1695 * frames that have been transmitted. 1696 */ 1697 for (idx = sc->sis_cdata.sis_tx_cons; sc->sis_cdata.sis_tx_cnt > 0; 1698 sc->sis_cdata.sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) { 1699 struct sis_desc *cur_tx = &sc->sis_ldata.sis_tx_list[idx]; 1700 1701 if (SIS_OWNDESC(cur_tx)) 1702 break; 1703 1704 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) 1705 continue; 1706 1707 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 1708 ifp->if_oerrors++; 1709 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 1710 ifp->if_collisions++; 1711 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 1712 ifp->if_collisions++; 1713 } 1714 1715 ifp->if_collisions += 1716 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 1717 1718 ifp->if_opackets++; 1719 if (cur_tx->sis_mbuf != NULL) { 1720 m_freem(cur_tx->sis_mbuf); 1721 cur_tx->sis_mbuf = NULL; 1722 bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map); 1723 bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map); 1724 } 1725 } 1726 1727 if (idx != sc->sis_cdata.sis_tx_cons) { 1728 /* we freed up some buffers */ 1729 sc->sis_cdata.sis_tx_cons = idx; 1730 ifp->if_flags &= ~IFF_OACTIVE; 1731 } 1732 1733 ifp->if_timer = (sc->sis_cdata.sis_tx_cnt == 0) ? 0 : 5; 1734 1735 return; 1736} 1737 1738static void 1739sis_tick(xsc) 1740 void *xsc; 1741{ 1742 struct sis_softc *sc; 1743 struct mii_data *mii; 1744 struct ifnet *ifp; 1745 1746 sc = xsc; 1747 SIS_LOCK(sc); 1748 ifp = &sc->arpcom.ac_if; 1749 1750 mii = device_get_softc(sc->sis_miibus); 1751 mii_tick(mii); 1752 1753 if (!sc->sis_link && mii->mii_media_status & IFM_ACTIVE && 1754 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1755 sc->sis_link++; 1756 if (ifp->if_snd.ifq_head != NULL) 1757 sis_start(ifp); 1758 } 1759 1760 sc->sis_stat_ch = timeout(sis_tick, sc, hz); 1761 1762 SIS_UNLOCK(sc); 1763 1764 return; 1765} 1766 1767#ifdef DEVICE_POLLING 1768static poll_handler_t sis_poll; 1769 1770static void 1771sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1772{ 1773 struct sis_softc *sc = ifp->if_softc; 1774 1775 SIS_LOCK(sc); 1776 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1777 CSR_WRITE_4(sc, SIS_IER, 1); 1778 goto done; 1779 } 1780 1781 /* 1782 * On the sis, reading the status register also clears it. 1783 * So before returning to intr mode we must make sure that all 1784 * possible pending sources of interrupts have been served. 1785 * In practice this means run to completion the *eof routines, 1786 * and then call the interrupt routine 1787 */ 1788 sc->rxcycles = count; 1789 sis_rxeof(sc); 1790 sis_txeof(sc); 1791 if (ifp->if_snd.ifq_head != NULL) 1792 sis_start(ifp); 1793 1794 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1795 u_int32_t status; 1796 1797 /* Reading the ISR register clears all interrupts. */ 1798 status = CSR_READ_4(sc, SIS_ISR); 1799 1800 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 1801 sis_rxeoc(sc); 1802 1803 if (status & (SIS_ISR_RX_IDLE)) 1804 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1805 1806 if (status & SIS_ISR_SYSERR) { 1807 sis_reset(sc); 1808 sis_init(sc); 1809 } 1810 } 1811done: 1812 SIS_UNLOCK(sc); 1813 return; 1814} 1815#endif /* DEVICE_POLLING */ 1816 1817static void 1818sis_intr(arg) 1819 void *arg; 1820{ 1821 struct sis_softc *sc; 1822 struct ifnet *ifp; 1823 u_int32_t status; 1824 1825 sc = arg; 1826 ifp = &sc->arpcom.ac_if; 1827 1828 SIS_LOCK(sc); 1829#ifdef DEVICE_POLLING 1830 if (ifp->if_flags & IFF_POLLING) 1831 goto done; 1832 if (ether_poll_register(sis_poll, ifp)) { /* ok, disable interrupts */ 1833 CSR_WRITE_4(sc, SIS_IER, 0); 1834 goto done; 1835 } 1836#endif /* DEVICE_POLLING */ 1837 1838 /* Supress unwanted interrupts */ 1839 if (!(ifp->if_flags & IFF_UP)) { 1840 sis_stop(sc); 1841 goto done; 1842 } 1843 1844 /* Disable interrupts. */ 1845 CSR_WRITE_4(sc, SIS_IER, 0); 1846 1847 for (;;) { 1848 /* Reading the ISR register clears all interrupts. */ 1849 status = CSR_READ_4(sc, SIS_ISR); 1850 1851 if ((status & SIS_INTRS) == 0) 1852 break; 1853 1854 if (status & 1855 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | 1856 SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) ) 1857 sis_txeof(sc); 1858 1859 if (status & (SIS_ISR_RX_DESC_OK|SIS_ISR_RX_OK|SIS_ISR_RX_IDLE)) 1860 sis_rxeof(sc); 1861 1862 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW)) 1863 sis_rxeoc(sc); 1864 1865 if (status & (SIS_ISR_RX_IDLE)) 1866 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1867 1868 if (status & SIS_ISR_SYSERR) { 1869 sis_reset(sc); 1870 sis_init(sc); 1871 } 1872 } 1873 1874 /* Re-enable interrupts. */ 1875 CSR_WRITE_4(sc, SIS_IER, 1); 1876 1877 if (ifp->if_snd.ifq_head != NULL) 1878 sis_start(ifp); 1879done: 1880 SIS_UNLOCK(sc); 1881 1882 return; 1883} 1884 1885/* 1886 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1887 * pointers to the fragment pointers. 1888 */ 1889static int 1890sis_encap(sc, m_head, txidx) 1891 struct sis_softc *sc; 1892 struct mbuf *m_head; 1893 u_int32_t *txidx; 1894{ 1895 struct sis_desc *f = NULL; 1896 struct mbuf *m; 1897 int frag, cur, cnt = 0, chainlen = 0; 1898 1899 /* 1900 * If there's no way we can send any packets, return now. 1901 */ 1902 if (SIS_TX_LIST_CNT - sc->sis_cdata.sis_tx_cnt < 2) 1903 return (ENOBUFS); 1904 1905 /* 1906 * Count the number of frags in this chain to see if 1907 * we need to m_defrag. Since the descriptor list is shared 1908 * by all packets, we'll m_defrag long chains so that they 1909 * do not use up the entire list, even if they would fit. 1910 */ 1911 1912 for (m = m_head; m != NULL; m = m->m_next) 1913 chainlen++; 1914 1915 if ((chainlen > SIS_TX_LIST_CNT / 4) || 1916 ((SIS_TX_LIST_CNT - (chainlen + sc->sis_cdata.sis_tx_cnt)) < 2)) { 1917 m = m_defrag(m_head, M_DONTWAIT); 1918 if (m == NULL) 1919 return (ENOBUFS); 1920 m_head = m; 1921 } 1922 1923 /* 1924 * Start packing the mbufs in this chain into 1925 * the fragment pointers. Stop when we run out 1926 * of fragments or hit the end of the mbuf chain. 1927 */ 1928 m = m_head; 1929 cur = frag = *txidx; 1930 1931 for (m = m_head; m != NULL; m = m->m_next) { 1932 if (m->m_len != 0) { 1933 if ((SIS_TX_LIST_CNT - 1934 (sc->sis_cdata.sis_tx_cnt + cnt)) < 2) 1935 return(ENOBUFS); 1936 f = &sc->sis_ldata.sis_tx_list[frag]; 1937 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; 1938 bus_dmamap_create(sc->sis_tag, 0, &f->sis_map); 1939 bus_dmamap_load(sc->sis_tag, f->sis_map, 1940 mtod(m, void *), m->m_len, 1941 sis_dma_map_desc_ptr, f, 0); 1942 bus_dmamap_sync(sc->sis_tag, 1943 f->sis_map, BUS_DMASYNC_PREREAD); 1944 if (cnt != 0) 1945 f->sis_ctl |= SIS_CMDSTS_OWN; 1946 cur = frag; 1947 SIS_INC(frag, SIS_TX_LIST_CNT); 1948 cnt++; 1949 } 1950 } 1951 1952 if (m != NULL) 1953 return(ENOBUFS); 1954 1955 sc->sis_ldata.sis_tx_list[cur].sis_mbuf = m_head; 1956 sc->sis_ldata.sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1957 sc->sis_ldata.sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1958 sc->sis_cdata.sis_tx_cnt += cnt; 1959 *txidx = frag; 1960 1961 return(0); 1962} 1963 1964/* 1965 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1966 * to the mbuf data regions directly in the transmit lists. We also save a 1967 * copy of the pointers since the transmit list fragment pointers are 1968 * physical addresses. 1969 */ 1970 1971static void 1972sis_start(ifp) 1973 struct ifnet *ifp; 1974{ 1975 struct sis_softc *sc; 1976 struct mbuf *m_head = NULL; 1977 u_int32_t idx; 1978 1979 sc = ifp->if_softc; 1980 SIS_LOCK(sc); 1981 1982 if (!sc->sis_link) { 1983 SIS_UNLOCK(sc); 1984 return; 1985 } 1986 1987 idx = sc->sis_cdata.sis_tx_prod; 1988 1989 if (ifp->if_flags & IFF_OACTIVE) { 1990 SIS_UNLOCK(sc); 1991 return; 1992 } 1993 1994 while(sc->sis_ldata.sis_tx_list[idx].sis_mbuf == NULL) { 1995 IF_DEQUEUE(&ifp->if_snd, m_head); 1996 if (m_head == NULL) 1997 break; 1998 1999 if (sis_encap(sc, m_head, &idx)) { 2000 IF_PREPEND(&ifp->if_snd, m_head); 2001 ifp->if_flags |= IFF_OACTIVE; 2002 break; 2003 } 2004 2005 /* 2006 * If there's a BPF listener, bounce a copy of this frame 2007 * to him. 2008 */ 2009 BPF_MTAP(ifp, m_head); 2010 2011 } 2012 2013 /* Transmit */ 2014 sc->sis_cdata.sis_tx_prod = idx; 2015 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 2016 2017 /* 2018 * Set a timeout in case the chip goes out to lunch. 2019 */ 2020 ifp->if_timer = 5; 2021 2022 SIS_UNLOCK(sc); 2023 2024 return; 2025} 2026 2027static void 2028sis_init(xsc) 2029 void *xsc; 2030{ 2031 struct sis_softc *sc = xsc; 2032 struct ifnet *ifp = &sc->arpcom.ac_if; 2033 struct mii_data *mii; 2034 2035 SIS_LOCK(sc); 2036 2037 /* 2038 * Cancel pending I/O and free all RX/TX buffers. 2039 */ 2040 sis_stop(sc); 2041 2042 mii = device_get_softc(sc->sis_miibus); 2043 2044 /* Set MAC address */ 2045 if (sc->sis_type == SIS_TYPE_83815) { 2046 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 2047 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2048 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 2049 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 2050 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2051 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 2052 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 2053 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2054 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 2055 } else { 2056 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 2057 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2058 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 2059 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 2060 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2061 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 2062 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 2063 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 2064 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 2065 } 2066 2067 /* Init circular RX list. */ 2068 if (sis_list_rx_init(sc) == ENOBUFS) { 2069 printf("sis%d: initialization failed: no " 2070 "memory for rx buffers\n", sc->sis_unit); 2071 sis_stop(sc); 2072 SIS_UNLOCK(sc); 2073 return; 2074 } 2075 2076 /* 2077 * Init tx descriptors. 2078 */ 2079 sis_list_tx_init(sc); 2080 2081 /* 2082 * For the NatSemi chip, we have to explicitly enable the 2083 * reception of ARP frames, as well as turn on the 'perfect 2084 * match' filter where we store the station address, otherwise 2085 * we won't receive unicasts meant for this host. 2086 */ 2087 if (sc->sis_type == SIS_TYPE_83815) { 2088 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 2089 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 2090 } 2091 2092 /* If we want promiscuous mode, set the allframes bit. */ 2093 if (ifp->if_flags & IFF_PROMISC) { 2094 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 2095 } else { 2096 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 2097 } 2098 2099 /* 2100 * Set the capture broadcast bit to capture broadcast frames. 2101 */ 2102 if (ifp->if_flags & IFF_BROADCAST) { 2103 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 2104 } else { 2105 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 2106 } 2107 2108 /* 2109 * Load the multicast filter. 2110 */ 2111 if (sc->sis_type == SIS_TYPE_83815) 2112 sis_setmulti_ns(sc); 2113 else 2114 sis_setmulti_sis(sc); 2115 2116 /* Turn the receive filter on */ 2117 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 2118 2119 /* 2120 * Load the address of the RX and TX lists. 2121 */ 2122 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_cdata.sis_rx_paddr); 2123 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_cdata.sis_tx_paddr); 2124 2125 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of 2126 * the PCI bus. When this bit is set, the Max DMA Burst Size 2127 * for TX/RX DMA should be no larger than 16 double words. 2128 */ 2129 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) { 2130 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); 2131 } else { 2132 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); 2133 } 2134 2135 2136 /* Accept Long Packets for VLAN support */ 2137 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 2138 2139 /* Set TX configuration */ 2140 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 2141 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 2142 } else { 2143 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 2144 } 2145 2146 /* Set full/half duplex mode. */ 2147 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 2148 SIS_SETBIT(sc, SIS_TX_CFG, 2149 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 2150 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 2151 } else { 2152 SIS_CLRBIT(sc, SIS_TX_CFG, 2153 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 2154 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 2155 } 2156 2157 /* 2158 * Enable interrupts. 2159 */ 2160 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 2161#ifdef DEVICE_POLLING 2162 /* 2163 * ... only enable interrupts if we are not polling, make sure 2164 * they are off otherwise. 2165 */ 2166 if (ifp->if_flags & IFF_POLLING) 2167 CSR_WRITE_4(sc, SIS_IER, 0); 2168 else 2169#endif /* DEVICE_POLLING */ 2170 CSR_WRITE_4(sc, SIS_IER, 1); 2171 2172 /* Enable receiver and transmitter. */ 2173 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2174 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 2175 2176#ifdef notdef 2177 mii_mediachg(mii); 2178#endif 2179 2180 /* 2181 * Page 75 of the DP83815 manual recommends the 2182 * following register settings "for optimum 2183 * performance." Note however that at least three 2184 * of the registers are listed as "reserved" in 2185 * the register map, so who knows what they do. 2186 */ 2187 if (sc->sis_type == SIS_TYPE_83815) { 2188 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 2189 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 2190 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 2191 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 2192 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 2193 } 2194 2195 ifp->if_flags |= IFF_RUNNING; 2196 ifp->if_flags &= ~IFF_OACTIVE; 2197 2198 sc->sis_stat_ch = timeout(sis_tick, sc, hz); 2199 2200 SIS_UNLOCK(sc); 2201 2202 return; 2203} 2204 2205/* 2206 * Set media options. 2207 */ 2208static int 2209sis_ifmedia_upd(ifp) 2210 struct ifnet *ifp; 2211{ 2212 struct sis_softc *sc; 2213 struct mii_data *mii; 2214 2215 sc = ifp->if_softc; 2216 2217 mii = device_get_softc(sc->sis_miibus); 2218 sc->sis_link = 0; 2219 if (mii->mii_instance) { 2220 struct mii_softc *miisc; 2221 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2222 mii_phy_reset(miisc); 2223 } 2224 mii_mediachg(mii); 2225 2226 return(0); 2227} 2228 2229/* 2230 * Report current media status. 2231 */ 2232static void 2233sis_ifmedia_sts(ifp, ifmr) 2234 struct ifnet *ifp; 2235 struct ifmediareq *ifmr; 2236{ 2237 struct sis_softc *sc; 2238 struct mii_data *mii; 2239 2240 sc = ifp->if_softc; 2241 2242 mii = device_get_softc(sc->sis_miibus); 2243 mii_pollstat(mii); 2244 ifmr->ifm_active = mii->mii_media_active; 2245 ifmr->ifm_status = mii->mii_media_status; 2246 2247 return; 2248} 2249 2250static int 2251sis_ioctl(ifp, command, data) 2252 struct ifnet *ifp; 2253 u_long command; 2254 caddr_t data; 2255{ 2256 struct sis_softc *sc = ifp->if_softc; 2257 struct ifreq *ifr = (struct ifreq *) data; 2258 struct mii_data *mii; 2259 int error = 0; 2260 2261 switch(command) { 2262 case SIOCSIFFLAGS: 2263 if (ifp->if_flags & IFF_UP) { 2264 sis_init(sc); 2265 } else { 2266 if (ifp->if_flags & IFF_RUNNING) 2267 sis_stop(sc); 2268 } 2269 error = 0; 2270 break; 2271 case SIOCADDMULTI: 2272 case SIOCDELMULTI: 2273 SIS_LOCK(sc); 2274 if (sc->sis_type == SIS_TYPE_83815) 2275 sis_setmulti_ns(sc); 2276 else 2277 sis_setmulti_sis(sc); 2278 SIS_UNLOCK(sc); 2279 error = 0; 2280 break; 2281 case SIOCGIFMEDIA: 2282 case SIOCSIFMEDIA: 2283 mii = device_get_softc(sc->sis_miibus); 2284 SIS_LOCK(sc); 2285 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2286 SIS_UNLOCK(sc); 2287 break; 2288 default: 2289 error = ether_ioctl(ifp, command, data); 2290 break; 2291 } 2292 2293 return(error); 2294} 2295 2296static void 2297sis_watchdog(ifp) 2298 struct ifnet *ifp; 2299{ 2300 struct sis_softc *sc; 2301 2302 sc = ifp->if_softc; 2303 2304 SIS_LOCK(sc); 2305 2306 ifp->if_oerrors++; 2307 printf("sis%d: watchdog timeout\n", sc->sis_unit); 2308 2309 sis_stop(sc); 2310 sis_reset(sc); 2311 sis_init(sc); 2312 2313 if (ifp->if_snd.ifq_head != NULL) 2314 sis_start(ifp); 2315 2316 SIS_UNLOCK(sc); 2317 2318 return; 2319} 2320 2321/* 2322 * Stop the adapter and free any mbufs allocated to the 2323 * RX and TX lists. 2324 */ 2325static void 2326sis_stop(sc) 2327 struct sis_softc *sc; 2328{ 2329 register int i; 2330 struct ifnet *ifp; 2331 2332 SIS_LOCK(sc); 2333 ifp = &sc->arpcom.ac_if; 2334 ifp->if_timer = 0; 2335 2336 untimeout(sis_tick, sc, sc->sis_stat_ch); 2337 2338 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2339#ifdef DEVICE_POLLING 2340 ether_poll_deregister(ifp); 2341#endif 2342 CSR_WRITE_4(sc, SIS_IER, 0); 2343 CSR_WRITE_4(sc, SIS_IMR, 0); 2344 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2345 DELAY(1000); 2346 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 2347 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2348 2349 sc->sis_link = 0; 2350 2351 /* 2352 * Free data in the RX lists. 2353 */ 2354 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 2355 if (sc->sis_ldata.sis_rx_list[i].sis_mbuf != NULL) { 2356 bus_dmamap_unload(sc->sis_tag, 2357 sc->sis_ldata.sis_rx_list[i].sis_map); 2358 bus_dmamap_destroy(sc->sis_tag, 2359 sc->sis_ldata.sis_rx_list[i].sis_map); 2360 m_freem(sc->sis_ldata.sis_rx_list[i].sis_mbuf); 2361 sc->sis_ldata.sis_rx_list[i].sis_mbuf = NULL; 2362 } 2363 } 2364 bzero(sc->sis_ldata.sis_rx_list, 2365 sizeof(sc->sis_ldata.sis_rx_list)); 2366 2367 /* 2368 * Free the TX list buffers. 2369 */ 2370 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 2371 if (sc->sis_ldata.sis_tx_list[i].sis_mbuf != NULL) { 2372 bus_dmamap_unload(sc->sis_tag, 2373 sc->sis_ldata.sis_tx_list[i].sis_map); 2374 bus_dmamap_destroy(sc->sis_tag, 2375 sc->sis_ldata.sis_tx_list[i].sis_map); 2376 m_freem(sc->sis_ldata.sis_tx_list[i].sis_mbuf); 2377 sc->sis_ldata.sis_tx_list[i].sis_mbuf = NULL; 2378 } 2379 } 2380 2381 bzero(sc->sis_ldata.sis_tx_list, 2382 sizeof(sc->sis_ldata.sis_tx_list)); 2383 2384 SIS_UNLOCK(sc); 2385 2386 return; 2387} 2388 2389/* 2390 * Stop all chip I/O so that the kernel's probe routines don't 2391 * get confused by errant DMAs when rebooting. 2392 */ 2393static void 2394sis_shutdown(dev) 2395 device_t dev; 2396{ 2397 struct sis_softc *sc; 2398 2399 sc = device_get_softc(dev); 2400 SIS_LOCK(sc); 2401 sis_reset(sc); 2402 sis_stop(sc); 2403 SIS_UNLOCK(sc); 2404 2405 return; 2406} 2407