if_sis.c revision 109976
150974Swpaul/* 250974Swpaul * Copyright (c) 1997, 1998, 1999 350974Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 450974Swpaul * 550974Swpaul * Redistribution and use in source and binary forms, with or without 650974Swpaul * modification, are permitted provided that the following conditions 750974Swpaul * are met: 850974Swpaul * 1. Redistributions of source code must retain the above copyright 950974Swpaul * notice, this list of conditions and the following disclaimer. 1050974Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1150974Swpaul * notice, this list of conditions and the following disclaimer in the 1250974Swpaul * documentation and/or other materials provided with the distribution. 1350974Swpaul * 3. All advertising materials mentioning features or use of this software 1450974Swpaul * must display the following acknowledgement: 1550974Swpaul * This product includes software developed by Bill Paul. 1650974Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1750974Swpaul * may be used to endorse or promote products derived from this software 1850974Swpaul * without specific prior written permission. 1950974Swpaul * 2050974Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2150974Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2250974Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2350974Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2450974Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2550974Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2650974Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2750974Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2850974Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2950974Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3050974Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3150974Swpaul * 3250974Swpaul * $FreeBSD: head/sys/pci/if_sis.c 109976 2003-01-28 10:55:38Z mbr $ 3350974Swpaul */ 3450974Swpaul 3550974Swpaul/* 3650974Swpaul * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 3750974Swpaul * available from http://www.sis.com.tw. 3850974Swpaul * 3964963Swpaul * This driver also supports the NatSemi DP83815. Datasheets are 4064963Swpaul * available from http://www.national.com. 4164963Swpaul * 4250974Swpaul * Written by Bill Paul <wpaul@ee.columbia.edu> 4350974Swpaul * Electrical Engineering Department 4450974Swpaul * Columbia University, New York City 4550974Swpaul */ 4650974Swpaul 4750974Swpaul/* 4850974Swpaul * The SiS 900 is a fairly simple chip. It uses bus master DMA with 4950974Swpaul * simple TX and RX descriptors of 3 longwords in size. The receiver 5050974Swpaul * has a single perfect filter entry for the station address and a 5150974Swpaul * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 5250974Swpaul * transceiver while the 7016 requires an external transceiver chip. 5350974Swpaul * Both chips offer the standard bit-bang MII interface as well as 5450974Swpaul * an enchanced PHY interface which simplifies accessing MII registers. 5550974Swpaul * 5650974Swpaul * The only downside to this chipset is that RX descriptors must be 5750974Swpaul * longword aligned. 5850974Swpaul */ 5950974Swpaul 6050974Swpaul#include <sys/param.h> 6150974Swpaul#include <sys/systm.h> 6250974Swpaul#include <sys/sockio.h> 6350974Swpaul#include <sys/mbuf.h> 6450974Swpaul#include <sys/malloc.h> 6550974Swpaul#include <sys/kernel.h> 6650974Swpaul#include <sys/socket.h> 6787059Sluigi#include <sys/sysctl.h> 6850974Swpaul 6950974Swpaul#include <net/if.h> 7050974Swpaul#include <net/if_arp.h> 7150974Swpaul#include <net/ethernet.h> 7250974Swpaul#include <net/if_dl.h> 7350974Swpaul#include <net/if_media.h> 7487390Sjhay#include <net/if_types.h> 7587390Sjhay#include <net/if_vlan_var.h> 7650974Swpaul 7750974Swpaul#include <net/bpf.h> 7850974Swpaul 7950974Swpaul#include <machine/bus_pio.h> 8050974Swpaul#include <machine/bus_memio.h> 8150974Swpaul#include <machine/bus.h> 8250974Swpaul#include <machine/resource.h> 8350974Swpaul#include <sys/bus.h> 8450974Swpaul#include <sys/rman.h> 8550974Swpaul 8650974Swpaul#include <dev/mii/mii.h> 8750974Swpaul#include <dev/mii/miivar.h> 8850974Swpaul 8950974Swpaul#include <pci/pcireg.h> 9050974Swpaul#include <pci/pcivar.h> 9150974Swpaul 9250974Swpaul#define SIS_USEIOSPACE 9350974Swpaul 9450974Swpaul#include <pci/if_sisreg.h> 9550974Swpaul 9659758SpeterMODULE_DEPEND(sis, miibus, 1, 1, 1); 9759758Speter 9851089Speter/* "controller miibus0" required. See GENERIC if you get errors here. */ 9950974Swpaul#include "miibus_if.h" 10050974Swpaul 10150974Swpaul#ifndef lint 10250974Swpaulstatic const char rcsid[] = 10350974Swpaul "$FreeBSD: head/sys/pci/if_sis.c 109976 2003-01-28 10:55:38Z mbr $"; 10450974Swpaul#endif 10550974Swpaul 10650974Swpaul/* 10750974Swpaul * Various supported device vendors/types and their names. 10850974Swpaul */ 10950974Swpaulstatic struct sis_type sis_devs[] = { 11050974Swpaul { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 11150974Swpaul { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 11262672Swpaul { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP83815 10/100BaseTX" }, 11350974Swpaul { 0, 0, NULL } 11450974Swpaul}; 11550974Swpaul 11692739Salfredstatic int sis_probe (device_t); 11792739Salfredstatic int sis_attach (device_t); 11892739Salfredstatic int sis_detach (device_t); 11950974Swpaul 12092739Salfredstatic int sis_newbuf (struct sis_softc *, 12192739Salfred struct sis_desc *, struct mbuf *); 12292739Salfredstatic int sis_encap (struct sis_softc *, 12392739Salfred struct mbuf *, u_int32_t *); 12492739Salfredstatic void sis_rxeof (struct sis_softc *); 12592739Salfredstatic void sis_rxeoc (struct sis_softc *); 12692739Salfredstatic void sis_txeof (struct sis_softc *); 12792739Salfredstatic void sis_intr (void *); 12892739Salfredstatic void sis_tick (void *); 12992739Salfredstatic void sis_start (struct ifnet *); 13092739Salfredstatic int sis_ioctl (struct ifnet *, u_long, caddr_t); 13192739Salfredstatic void sis_init (void *); 13292739Salfredstatic void sis_stop (struct sis_softc *); 13392739Salfredstatic void sis_watchdog (struct ifnet *); 13492739Salfredstatic void sis_shutdown (device_t); 13592739Salfredstatic int sis_ifmedia_upd (struct ifnet *); 13692739Salfredstatic void sis_ifmedia_sts (struct ifnet *, struct ifmediareq *); 13750974Swpaul 13892739Salfredstatic u_int16_t sis_reverse (u_int16_t); 13992739Salfredstatic void sis_delay (struct sis_softc *); 14092739Salfredstatic void sis_eeprom_idle (struct sis_softc *); 14192739Salfredstatic void sis_eeprom_putbyte (struct sis_softc *, int); 14292739Salfredstatic void sis_eeprom_getword (struct sis_softc *, int, u_int16_t *); 14392739Salfredstatic void sis_read_eeprom (struct sis_softc *, caddr_t, int, int, int); 14472197Swpaul#ifdef __i386__ 14592739Salfredstatic void sis_read_cmos (struct sis_softc *, device_t, caddr_t, 14692739Salfred int, int); 14792739Salfredstatic void sis_read_mac (struct sis_softc *, device_t, caddr_t); 14892739Salfredstatic device_t sis_find_bridge (device_t); 14972197Swpaul#endif 15072197Swpaul 151109060Smbrstatic void sis_mii_sync (struct sis_softc *); 152109060Smbrstatic void sis_mii_send (struct sis_softc *, u_int32_t, int); 153109060Smbrstatic int sis_mii_readreg (struct sis_softc *, struct sis_mii_frame *); 154109060Smbrstatic int sis_mii_writereg (struct sis_softc *, struct sis_mii_frame *); 15592739Salfredstatic int sis_miibus_readreg (device_t, int, int); 15692739Salfredstatic int sis_miibus_writereg (device_t, int, int, int); 15792739Salfredstatic void sis_miibus_statchg (device_t); 15850974Swpaul 15992739Salfredstatic void sis_setmulti_sis (struct sis_softc *); 16092739Salfredstatic void sis_setmulti_ns (struct sis_softc *); 16192739Salfredstatic u_int32_t sis_crc (struct sis_softc *, caddr_t); 16292739Salfredstatic void sis_reset (struct sis_softc *); 16392739Salfredstatic int sis_list_rx_init (struct sis_softc *); 16492739Salfredstatic int sis_list_tx_init (struct sis_softc *); 16550974Swpaul 16692739Salfredstatic void sis_dma_map_desc_ptr (void *, bus_dma_segment_t *, int, int); 16792739Salfredstatic void sis_dma_map_desc_next (void *, bus_dma_segment_t *, int, int); 16892739Salfredstatic void sis_dma_map_ring (void *, bus_dma_segment_t *, int, int); 16950974Swpaul#ifdef SIS_USEIOSPACE 17050974Swpaul#define SIS_RES SYS_RES_IOPORT 17150974Swpaul#define SIS_RID SIS_PCI_LOIO 17250974Swpaul#else 17351030Swpaul#define SIS_RES SYS_RES_MEMORY 17451030Swpaul#define SIS_RID SIS_PCI_LOMEM 17550974Swpaul#endif 17650974Swpaul 17750974Swpaulstatic device_method_t sis_methods[] = { 17850974Swpaul /* Device interface */ 17950974Swpaul DEVMETHOD(device_probe, sis_probe), 18050974Swpaul DEVMETHOD(device_attach, sis_attach), 18150974Swpaul DEVMETHOD(device_detach, sis_detach), 18250974Swpaul DEVMETHOD(device_shutdown, sis_shutdown), 18350974Swpaul 18450974Swpaul /* bus interface */ 18550974Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 18650974Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 18750974Swpaul 18850974Swpaul /* MII interface */ 18950974Swpaul DEVMETHOD(miibus_readreg, sis_miibus_readreg), 19050974Swpaul DEVMETHOD(miibus_writereg, sis_miibus_writereg), 19150974Swpaul DEVMETHOD(miibus_statchg, sis_miibus_statchg), 19250974Swpaul 19350974Swpaul { 0, 0 } 19450974Swpaul}; 19550974Swpaul 19650974Swpaulstatic driver_t sis_driver = { 19751455Swpaul "sis", 19850974Swpaul sis_methods, 19950974Swpaul sizeof(struct sis_softc) 20050974Swpaul}; 20150974Swpaul 20250974Swpaulstatic devclass_t sis_devclass; 20350974Swpaul 20451533SwpaulDRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, 0, 0); 20551473SwpaulDRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 20650974Swpaul 20750974Swpaul#define SIS_SETBIT(sc, reg, x) \ 20850974Swpaul CSR_WRITE_4(sc, reg, \ 20950974Swpaul CSR_READ_4(sc, reg) | (x)) 21050974Swpaul 21150974Swpaul#define SIS_CLRBIT(sc, reg, x) \ 21250974Swpaul CSR_WRITE_4(sc, reg, \ 21350974Swpaul CSR_READ_4(sc, reg) & ~(x)) 21450974Swpaul 21550974Swpaul#define SIO_SET(x) \ 21650974Swpaul CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 21750974Swpaul 21850974Swpaul#define SIO_CLR(x) \ 21950974Swpaul CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 22050974Swpaul 22181713Swpaulstatic void 22281713Swpaulsis_dma_map_desc_next(arg, segs, nseg, error) 22381713Swpaul void *arg; 22481713Swpaul bus_dma_segment_t *segs; 22581713Swpaul int nseg, error; 22681713Swpaul{ 22781713Swpaul struct sis_desc *r; 22881713Swpaul 22981713Swpaul r = arg; 23081713Swpaul r->sis_next = segs->ds_addr; 23181713Swpaul 23281713Swpaul return; 23381713Swpaul} 23481713Swpaul 23581713Swpaulstatic void 23681713Swpaulsis_dma_map_desc_ptr(arg, segs, nseg, error) 23781713Swpaul void *arg; 23881713Swpaul bus_dma_segment_t *segs; 23981713Swpaul int nseg, error; 24081713Swpaul{ 24181713Swpaul struct sis_desc *r; 24281713Swpaul 24381713Swpaul r = arg; 24481713Swpaul r->sis_ptr = segs->ds_addr; 24581713Swpaul 24681713Swpaul return; 24781713Swpaul} 24881713Swpaul 24981713Swpaulstatic void 25081713Swpaulsis_dma_map_ring(arg, segs, nseg, error) 25181713Swpaul void *arg; 25281713Swpaul bus_dma_segment_t *segs; 25381713Swpaul int nseg, error; 25481713Swpaul{ 25581713Swpaul u_int32_t *p; 25681713Swpaul 25781713Swpaul p = arg; 25881713Swpaul *p = segs->ds_addr; 25981713Swpaul 26081713Swpaul return; 26181713Swpaul} 26281713Swpaul 26362672Swpaul/* 26462672Swpaul * Routine to reverse the bits in a word. Stolen almost 26562672Swpaul * verbatim from /usr/games/fortune. 26662672Swpaul */ 267102334Salfredstatic u_int16_t 268102334Salfredsis_reverse(n) 26962672Swpaul u_int16_t n; 27062672Swpaul{ 27162672Swpaul n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 27262672Swpaul n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 27362672Swpaul n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 27462672Swpaul n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 27562672Swpaul 27662672Swpaul return(n); 27762672Swpaul} 27862672Swpaul 279102334Salfredstatic void 280102334Salfredsis_delay(sc) 28150974Swpaul struct sis_softc *sc; 28250974Swpaul{ 28350974Swpaul int idx; 28450974Swpaul 28550974Swpaul for (idx = (300 / 33) + 1; idx > 0; idx--) 28650974Swpaul CSR_READ_4(sc, SIS_CSR); 28750974Swpaul 28850974Swpaul return; 28950974Swpaul} 29050974Swpaul 291102334Salfredstatic void 292102334Salfredsis_eeprom_idle(sc) 29350974Swpaul struct sis_softc *sc; 29450974Swpaul{ 29550974Swpaul register int i; 29650974Swpaul 29750974Swpaul SIO_SET(SIS_EECTL_CSEL); 29850974Swpaul sis_delay(sc); 29950974Swpaul SIO_SET(SIS_EECTL_CLK); 30050974Swpaul sis_delay(sc); 30150974Swpaul 30250974Swpaul for (i = 0; i < 25; i++) { 30350974Swpaul SIO_CLR(SIS_EECTL_CLK); 30450974Swpaul sis_delay(sc); 30550974Swpaul SIO_SET(SIS_EECTL_CLK); 30650974Swpaul sis_delay(sc); 30750974Swpaul } 30850974Swpaul 30950974Swpaul SIO_CLR(SIS_EECTL_CLK); 31050974Swpaul sis_delay(sc); 31150974Swpaul SIO_CLR(SIS_EECTL_CSEL); 31250974Swpaul sis_delay(sc); 31350974Swpaul CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 31450974Swpaul 31550974Swpaul return; 31650974Swpaul} 31750974Swpaul 31850974Swpaul/* 31950974Swpaul * Send a read command and address to the EEPROM, check for ACK. 32050974Swpaul */ 321102334Salfredstatic void 322102334Salfredsis_eeprom_putbyte(sc, addr) 32350974Swpaul struct sis_softc *sc; 32450974Swpaul int addr; 32550974Swpaul{ 32650974Swpaul register int d, i; 32750974Swpaul 32850974Swpaul d = addr | SIS_EECMD_READ; 32950974Swpaul 33050974Swpaul /* 33150974Swpaul * Feed in each bit and stobe the clock. 33250974Swpaul */ 33350974Swpaul for (i = 0x400; i; i >>= 1) { 33450974Swpaul if (d & i) { 33550974Swpaul SIO_SET(SIS_EECTL_DIN); 33650974Swpaul } else { 33750974Swpaul SIO_CLR(SIS_EECTL_DIN); 33850974Swpaul } 33950974Swpaul sis_delay(sc); 34050974Swpaul SIO_SET(SIS_EECTL_CLK); 34150974Swpaul sis_delay(sc); 34250974Swpaul SIO_CLR(SIS_EECTL_CLK); 34350974Swpaul sis_delay(sc); 34450974Swpaul } 34550974Swpaul 34650974Swpaul return; 34750974Swpaul} 34850974Swpaul 34950974Swpaul/* 35050974Swpaul * Read a word of data stored in the EEPROM at address 'addr.' 35150974Swpaul */ 352102334Salfredstatic void 353102334Salfredsis_eeprom_getword(sc, addr, dest) 35450974Swpaul struct sis_softc *sc; 35550974Swpaul int addr; 35650974Swpaul u_int16_t *dest; 35750974Swpaul{ 35850974Swpaul register int i; 35950974Swpaul u_int16_t word = 0; 36050974Swpaul 36150974Swpaul /* Force EEPROM to idle state. */ 36250974Swpaul sis_eeprom_idle(sc); 36350974Swpaul 36450974Swpaul /* Enter EEPROM access mode. */ 36550974Swpaul sis_delay(sc); 36662672Swpaul SIO_CLR(SIS_EECTL_CLK); 36762672Swpaul sis_delay(sc); 36850974Swpaul SIO_SET(SIS_EECTL_CSEL); 36950974Swpaul sis_delay(sc); 37050974Swpaul 37150974Swpaul /* 37250974Swpaul * Send address of word we want to read. 37350974Swpaul */ 37450974Swpaul sis_eeprom_putbyte(sc, addr); 37550974Swpaul 37650974Swpaul /* 37750974Swpaul * Start reading bits from EEPROM. 37850974Swpaul */ 37950974Swpaul for (i = 0x8000; i; i >>= 1) { 38050974Swpaul SIO_SET(SIS_EECTL_CLK); 38150974Swpaul sis_delay(sc); 38250974Swpaul if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 38350974Swpaul word |= i; 38450974Swpaul sis_delay(sc); 38550974Swpaul SIO_CLR(SIS_EECTL_CLK); 38650974Swpaul sis_delay(sc); 38750974Swpaul } 38850974Swpaul 38950974Swpaul /* Turn off EEPROM access mode. */ 39050974Swpaul sis_eeprom_idle(sc); 39150974Swpaul 39250974Swpaul *dest = word; 39350974Swpaul 39450974Swpaul return; 39550974Swpaul} 39650974Swpaul 39750974Swpaul/* 39850974Swpaul * Read a sequence of words from the EEPROM. 39950974Swpaul */ 400102334Salfredstatic void 401102334Salfredsis_read_eeprom(sc, dest, off, cnt, swap) 40250974Swpaul struct sis_softc *sc; 40350974Swpaul caddr_t dest; 40450974Swpaul int off; 40550974Swpaul int cnt; 40650974Swpaul int swap; 40750974Swpaul{ 40850974Swpaul int i; 40950974Swpaul u_int16_t word = 0, *ptr; 41050974Swpaul 41150974Swpaul for (i = 0; i < cnt; i++) { 41250974Swpaul sis_eeprom_getword(sc, off + i, &word); 41350974Swpaul ptr = (u_int16_t *)(dest + (i * 2)); 41450974Swpaul if (swap) 41550974Swpaul *ptr = ntohs(word); 41650974Swpaul else 41750974Swpaul *ptr = word; 41850974Swpaul } 41950974Swpaul 42050974Swpaul return; 42150974Swpaul} 42250974Swpaul 42372197Swpaul#ifdef __i386__ 424102334Salfredstatic device_t 425102334Salfredsis_find_bridge(dev) 42672197Swpaul device_t dev; 42772197Swpaul{ 42872197Swpaul devclass_t pci_devclass; 42972197Swpaul device_t *pci_devices; 43072197Swpaul int pci_count = 0; 43172197Swpaul device_t *pci_children; 43272197Swpaul int pci_childcount = 0; 43372197Swpaul device_t *busp, *childp; 43487994Sarchie device_t child = NULL; 43572197Swpaul int i, j; 43672197Swpaul 43772197Swpaul if ((pci_devclass = devclass_find("pci")) == NULL) 43872197Swpaul return(NULL); 43972197Swpaul 44072197Swpaul devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 44172197Swpaul 44272197Swpaul for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 44372197Swpaul pci_childcount = 0; 44472197Swpaul device_get_children(*busp, &pci_children, &pci_childcount); 44572197Swpaul for (j = 0, childp = pci_children; 44672197Swpaul j < pci_childcount; j++, childp++) { 44772197Swpaul if (pci_get_vendor(*childp) == SIS_VENDORID && 44872197Swpaul pci_get_device(*childp) == 0x0008) { 44987994Sarchie child = *childp; 45087994Sarchie goto done; 45172197Swpaul } 45272197Swpaul } 45372197Swpaul } 45472197Swpaul 45587994Sarchiedone: 45672197Swpaul free(pci_devices, M_TEMP); 45772197Swpaul free(pci_children, M_TEMP); 45887994Sarchie return(child); 45972197Swpaul} 46072197Swpaul 461102334Salfredstatic void 462102334Salfredsis_read_cmos(sc, dev, dest, off, cnt) 46372197Swpaul struct sis_softc *sc; 46472197Swpaul device_t dev; 46572197Swpaul caddr_t dest; 46672197Swpaul int off; 46772197Swpaul int cnt; 46872197Swpaul{ 46972197Swpaul device_t bridge; 47072197Swpaul u_int8_t reg; 47172197Swpaul int i; 47272197Swpaul bus_space_tag_t btag; 47372197Swpaul 47472197Swpaul bridge = sis_find_bridge(dev); 47572197Swpaul if (bridge == NULL) 47672197Swpaul return; 47772197Swpaul reg = pci_read_config(bridge, 0x48, 1); 47872197Swpaul pci_write_config(bridge, 0x48, reg|0x40, 1); 47972197Swpaul 48072197Swpaul /* XXX */ 48172197Swpaul btag = I386_BUS_SPACE_IO; 48272197Swpaul 48372197Swpaul for (i = 0; i < cnt; i++) { 48472197Swpaul bus_space_write_1(btag, 0x0, 0x70, i + off); 48572197Swpaul *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 48672197Swpaul } 48772197Swpaul 48872197Swpaul pci_write_config(bridge, 0x48, reg & ~0x40, 1); 48972197Swpaul return; 49072197Swpaul} 49189296Swpaul 492102334Salfredstatic void 493102334Salfredsis_read_mac(sc, dev, dest) 49489296Swpaul struct sis_softc *sc; 49589296Swpaul device_t dev; 49689296Swpaul caddr_t dest; 49789296Swpaul{ 49889296Swpaul u_int32_t filtsave, csrsave; 49989296Swpaul 50089296Swpaul filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 50189296Swpaul csrsave = CSR_READ_4(sc, SIS_CSR); 50289296Swpaul 50389296Swpaul CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 50489296Swpaul CSR_WRITE_4(sc, SIS_CSR, 0); 50589296Swpaul 50689296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 50789296Swpaul 50889296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 50989296Swpaul ((u_int16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 51089296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 51189296Swpaul ((u_int16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 51289296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 51389296Swpaul ((u_int16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 51489296Swpaul 51589296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 51689296Swpaul CSR_WRITE_4(sc, SIS_CSR, csrsave); 51789296Swpaul return; 51889296Swpaul} 51972197Swpaul#endif 52072197Swpaul 521109060Smbr/* 522109060Smbr * Sync the PHYs by setting data bit and strobing the clock 32 times. 523109060Smbr */ 524109060Smbrstatic void sis_mii_sync(sc) 525109060Smbr struct sis_softc *sc; 526109060Smbr{ 527109060Smbr register int i; 528109060Smbr 529109060Smbr SIO_SET(SIS_MII_DIR|SIS_MII_DATA); 530109060Smbr 531109060Smbr for (i = 0; i < 32; i++) { 532109060Smbr SIO_SET(SIS_MII_CLK); 533109060Smbr DELAY(1); 534109060Smbr SIO_CLR(SIS_MII_CLK); 535109060Smbr DELAY(1); 536109060Smbr } 537109060Smbr 538109060Smbr return; 539109060Smbr} 540109060Smbr 541109060Smbr/* 542109060Smbr * Clock a series of bits through the MII. 543109060Smbr */ 544109060Smbrstatic void sis_mii_send(sc, bits, cnt) 545109060Smbr struct sis_softc *sc; 546109060Smbr u_int32_t bits; 547109060Smbr int cnt; 548109060Smbr{ 549109060Smbr int i; 550109060Smbr 551109060Smbr SIO_CLR(SIS_MII_CLK); 552109060Smbr 553109060Smbr for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 554109060Smbr if (bits & i) { 555109060Smbr SIO_SET(SIS_MII_DATA); 556109060Smbr } else { 557109060Smbr SIO_CLR(SIS_MII_DATA); 558109060Smbr } 559109060Smbr DELAY(1); 560109060Smbr SIO_CLR(SIS_MII_CLK); 561109060Smbr DELAY(1); 562109060Smbr SIO_SET(SIS_MII_CLK); 563109060Smbr } 564109060Smbr} 565109060Smbr 566109060Smbr/* 567109060Smbr * Read an PHY register through the MII. 568109060Smbr */ 569109060Smbrstatic int sis_mii_readreg(sc, frame) 570109060Smbr struct sis_softc *sc; 571109060Smbr struct sis_mii_frame *frame; 572109060Smbr 573109060Smbr{ 574109060Smbr int i, ack, s; 575109060Smbr 576109060Smbr s = splimp(); 577109060Smbr 578109060Smbr /* 579109060Smbr * Set up frame for RX. 580109060Smbr */ 581109060Smbr frame->mii_stdelim = SIS_MII_STARTDELIM; 582109060Smbr frame->mii_opcode = SIS_MII_READOP; 583109060Smbr frame->mii_turnaround = 0; 584109060Smbr frame->mii_data = 0; 585109060Smbr 586109060Smbr /* 587109060Smbr * Turn on data xmit. 588109060Smbr */ 589109060Smbr SIO_SET(SIS_MII_DIR); 590109060Smbr 591109060Smbr sis_mii_sync(sc); 592109060Smbr 593109060Smbr /* 594109060Smbr * Send command/address info. 595109060Smbr */ 596109060Smbr sis_mii_send(sc, frame->mii_stdelim, 2); 597109060Smbr sis_mii_send(sc, frame->mii_opcode, 2); 598109060Smbr sis_mii_send(sc, frame->mii_phyaddr, 5); 599109060Smbr sis_mii_send(sc, frame->mii_regaddr, 5); 600109060Smbr 601109060Smbr /* Idle bit */ 602109060Smbr SIO_CLR((SIS_MII_CLK|SIS_MII_DATA)); 603109060Smbr DELAY(1); 604109060Smbr SIO_SET(SIS_MII_CLK); 605109060Smbr DELAY(1); 606109060Smbr 607109060Smbr /* Turn off xmit. */ 608109060Smbr SIO_CLR(SIS_MII_DIR); 609109060Smbr 610109060Smbr /* Check for ack */ 611109060Smbr SIO_CLR(SIS_MII_CLK); 612109060Smbr DELAY(1); 613109060Smbr ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA; 614109060Smbr SIO_SET(SIS_MII_CLK); 615109060Smbr DELAY(1); 616109060Smbr 617109060Smbr /* 618109060Smbr * Now try reading data bits. If the ack failed, we still 619109060Smbr * need to clock through 16 cycles to keep the PHY(s) in sync. 620109060Smbr */ 621109060Smbr if (ack) { 622109060Smbr for(i = 0; i < 16; i++) { 623109060Smbr SIO_CLR(SIS_MII_CLK); 624109060Smbr DELAY(1); 625109060Smbr SIO_SET(SIS_MII_CLK); 626109060Smbr DELAY(1); 627109060Smbr } 628109060Smbr goto fail; 629109060Smbr } 630109060Smbr 631109060Smbr for (i = 0x8000; i; i >>= 1) { 632109060Smbr SIO_CLR(SIS_MII_CLK); 633109060Smbr DELAY(1); 634109060Smbr if (!ack) { 635109060Smbr if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA) 636109060Smbr frame->mii_data |= i; 637109060Smbr DELAY(1); 638109060Smbr } 639109060Smbr SIO_SET(SIS_MII_CLK); 640109060Smbr DELAY(1); 641109060Smbr } 642109060Smbr 643109060Smbrfail: 644109060Smbr 645109060Smbr SIO_CLR(SIS_MII_CLK); 646109060Smbr DELAY(1); 647109060Smbr SIO_SET(SIS_MII_CLK); 648109060Smbr DELAY(1); 649109060Smbr 650109060Smbr splx(s); 651109060Smbr 652109060Smbr if (ack) 653109060Smbr return(1); 654109060Smbr return(0); 655109060Smbr} 656109060Smbr 657109060Smbr/* 658109060Smbr * Write to a PHY register through the MII. 659109060Smbr */ 660109060Smbrstatic int sis_mii_writereg(sc, frame) 661109060Smbr struct sis_softc *sc; 662109060Smbr struct sis_mii_frame *frame; 663109060Smbr 664109060Smbr{ 665109060Smbr int s; 666109060Smbr 667109060Smbr s = splimp(); 668109060Smbr /* 669109060Smbr * Set up frame for TX. 670109060Smbr */ 671109060Smbr 672109060Smbr frame->mii_stdelim = SIS_MII_STARTDELIM; 673109060Smbr frame->mii_opcode = SIS_MII_WRITEOP; 674109060Smbr frame->mii_turnaround = SIS_MII_TURNAROUND; 675109060Smbr 676109060Smbr /* 677109060Smbr * Turn on data output. 678109060Smbr */ 679109060Smbr SIO_SET(SIS_MII_DIR); 680109060Smbr 681109060Smbr sis_mii_sync(sc); 682109060Smbr 683109060Smbr sis_mii_send(sc, frame->mii_stdelim, 2); 684109060Smbr sis_mii_send(sc, frame->mii_opcode, 2); 685109060Smbr sis_mii_send(sc, frame->mii_phyaddr, 5); 686109060Smbr sis_mii_send(sc, frame->mii_regaddr, 5); 687109060Smbr sis_mii_send(sc, frame->mii_turnaround, 2); 688109060Smbr sis_mii_send(sc, frame->mii_data, 16); 689109060Smbr 690109060Smbr /* Idle bit. */ 691109060Smbr SIO_SET(SIS_MII_CLK); 692109060Smbr DELAY(1); 693109060Smbr SIO_CLR(SIS_MII_CLK); 694109060Smbr DELAY(1); 695109060Smbr 696109060Smbr /* 697109060Smbr * Turn off xmit. 698109060Smbr */ 699109060Smbr SIO_CLR(SIS_MII_DIR); 700109060Smbr 701109060Smbr splx(s); 702109060Smbr 703109060Smbr return(0); 704109060Smbr} 705109060Smbr 706102334Salfredstatic int 707102334Salfredsis_miibus_readreg(dev, phy, reg) 70850974Swpaul device_t dev; 70950974Swpaul int phy, reg; 71050974Swpaul{ 71150974Swpaul struct sis_softc *sc; 712109060Smbr struct sis_mii_frame frame; 71350974Swpaul 71450974Swpaul sc = device_get_softc(dev); 71550974Swpaul 71662672Swpaul if (sc->sis_type == SIS_TYPE_83815) { 71762672Swpaul if (phy != 0) 71862672Swpaul return(0); 71962672Swpaul /* 72062672Swpaul * The NatSemi chip can take a while after 72162672Swpaul * a reset to come ready, during which the BMSR 72262672Swpaul * returns a value of 0. This is *never* supposed 72362672Swpaul * to happen: some of the BMSR bits are meant to 72462672Swpaul * be hardwired in the on position, and this can 72562672Swpaul * confuse the miibus code a bit during the probe 72662672Swpaul * and attach phase. So we make an effort to check 72762672Swpaul * for this condition and wait for it to clear. 72862672Swpaul */ 72962672Swpaul if (!CSR_READ_4(sc, NS_BMSR)) 73062672Swpaul DELAY(1000); 731109060Smbr return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 73262672Swpaul } 73362672Swpaul 734109976Smbr /* 735109976Smbr * Chipsets < SIS_635 seem not to be able to read/write 736109976Smbr * through mdio. Use the enhanced PHY access register 737109976Smbr * again for them. 738109976Smbr */ 73989296Swpaul if (sc->sis_type == SIS_TYPE_900 && 740109976Smbr sc->sis_rev < SIS_REV_635) { 741109976Smbr int i, val = 0; 74250974Swpaul 743109976Smbr if (phy != 0) 744109976Smbr return(0); 74550974Swpaul 746109976Smbr CSR_WRITE_4(sc, SIS_PHYCTL, 747109976Smbr (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 748109976Smbr SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 74950974Swpaul 750109976Smbr for (i = 0; i < SIS_TIMEOUT; i++) { 751109976Smbr if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 752109976Smbr break; 753109976Smbr } 754109976Smbr 755109976Smbr if (i == SIS_TIMEOUT) { 756109976Smbr printf("sis%d: PHY failed to come ready\n", 757109976Smbr sc->sis_unit); 758109976Smbr return(0); 759109976Smbr } 760109976Smbr 761109976Smbr val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 762109976Smbr 763109976Smbr if (val == 0xFFFF) 764109976Smbr return(0); 765109976Smbr 766109976Smbr return(val); 767109976Smbr } else { 768109976Smbr bzero((char *)&frame, sizeof(frame)); 769109976Smbr 770109976Smbr frame.mii_phyaddr = phy; 771109976Smbr frame.mii_regaddr = reg; 772109976Smbr sis_mii_readreg(sc, &frame); 773109976Smbr 774109976Smbr return(frame.mii_data); 775109976Smbr } 77650974Swpaul} 77750974Swpaul 778102334Salfredstatic int 779102334Salfredsis_miibus_writereg(dev, phy, reg, data) 78050974Swpaul device_t dev; 78150974Swpaul int phy, reg, data; 78250974Swpaul{ 78350974Swpaul struct sis_softc *sc; 784109060Smbr struct sis_mii_frame frame; 78550974Swpaul 78650974Swpaul sc = device_get_softc(dev); 78750974Swpaul 78862672Swpaul if (sc->sis_type == SIS_TYPE_83815) { 78962672Swpaul if (phy != 0) 79062672Swpaul return(0); 79162672Swpaul CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 79262672Swpaul return(0); 79362672Swpaul } 79462672Swpaul 795109976Smbr /* 796109976Smbr * Chipsets < SIS_635 seem not to be able to read/write 797109976Smbr * through mdio. Use the enhanced PHY access register 798109976Smbr * again for them. 799109976Smbr */ 800109976Smbr if (sc->sis_type == SIS_TYPE_900 && 801109976Smbr sc->sis_rev < SIS_REV_635) { 802109976Smbr int i; 80350974Swpaul 804109976Smbr if (phy != 0) 805109976Smbr return(0); 80650974Swpaul 807109976Smbr CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 808109976Smbr (reg << 6) | SIS_PHYOP_WRITE); 809109976Smbr SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 81050974Swpaul 811109976Smbr for (i = 0; i < SIS_TIMEOUT; i++) { 812109976Smbr if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 813109976Smbr break; 814109976Smbr } 81550974Swpaul 816109976Smbr if (i == SIS_TIMEOUT) 817109976Smbr printf("sis%d: PHY failed to come ready\n", 818109976Smbr sc->sis_unit); 819109976Smbr } else { 820109976Smbr bzero((char *)&frame, sizeof(frame)); 821109976Smbr 822109976Smbr frame.mii_phyaddr = phy; 823109976Smbr frame.mii_regaddr = reg; 824109976Smbr frame.mii_data = data; 825109976Smbr sis_mii_writereg(sc, &frame); 826109976Smbr } 82750974Swpaul return(0); 82850974Swpaul} 82950974Swpaul 830102334Salfredstatic void 831102334Salfredsis_miibus_statchg(dev) 83250974Swpaul device_t dev; 83350974Swpaul{ 83450974Swpaul struct sis_softc *sc; 83550974Swpaul 83650974Swpaul sc = device_get_softc(dev); 83764963Swpaul sis_init(sc); 83850974Swpaul 83950974Swpaul return; 84050974Swpaul} 84150974Swpaul 842102334Salfredstatic u_int32_t 843102334Salfredsis_crc(sc, addr) 84462672Swpaul struct sis_softc *sc; 84550974Swpaul caddr_t addr; 84650974Swpaul{ 84750974Swpaul u_int32_t crc, carry; 84850974Swpaul int i, j; 84950974Swpaul u_int8_t c; 85050974Swpaul 85150974Swpaul /* Compute CRC for the address value. */ 85250974Swpaul crc = 0xFFFFFFFF; /* initial value */ 85350974Swpaul 85450974Swpaul for (i = 0; i < 6; i++) { 85550974Swpaul c = *(addr + i); 85650974Swpaul for (j = 0; j < 8; j++) { 85750974Swpaul carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 85850974Swpaul crc <<= 1; 85950974Swpaul c >>= 1; 86050974Swpaul if (carry) 86150974Swpaul crc = (crc ^ 0x04c11db6) | carry; 86250974Swpaul } 86350974Swpaul } 86450974Swpaul 86562672Swpaul /* 86662672Swpaul * return the filter bit position 86762672Swpaul * 86862672Swpaul * The NatSemi chip has a 512-bit filter, which is 86962672Swpaul * different than the SiS, so we special-case it. 87062672Swpaul */ 87162672Swpaul if (sc->sis_type == SIS_TYPE_83815) 872109060Smbr return (crc >> 23); 873109976Smbr else if (sc->sis_rev >= SIS_REV_635 || 874109976Smbr sc->sis_rev == SIS_REV_900B) 875109060Smbr return (crc >> 24); 876109976Smbr else 877109976Smbr return (crc >> 25); 87850974Swpaul} 87950974Swpaul 880102334Salfredstatic void 881102334Salfredsis_setmulti_ns(sc) 88250974Swpaul struct sis_softc *sc; 88350974Swpaul{ 88450974Swpaul struct ifnet *ifp; 88550974Swpaul struct ifmultiaddr *ifma; 88650974Swpaul u_int32_t h = 0, i, filtsave; 88762672Swpaul int bit, index; 88850974Swpaul 88950974Swpaul ifp = &sc->arpcom.ac_if; 89050974Swpaul 89150974Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 89262672Swpaul SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 89350974Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 89450974Swpaul return; 89550974Swpaul } 89650974Swpaul 89762672Swpaul /* 89862672Swpaul * We have to explicitly enable the multicast hash table 89962672Swpaul * on the NatSemi chip if we want to use it, which we do. 90062672Swpaul */ 90162672Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 90250974Swpaul SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 90350974Swpaul 90450974Swpaul filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 90550974Swpaul 90650974Swpaul /* first, zot all the existing hash bits */ 90762672Swpaul for (i = 0; i < 32; i++) { 90862672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 90962672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 91062672Swpaul } 91162672Swpaul 91272084Sphk TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 91362672Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 91462672Swpaul continue; 91562672Swpaul h = sis_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 91662672Swpaul index = h >> 3; 91762672Swpaul bit = h & 0x1F; 91862672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 91962672Swpaul if (bit > 0xF) 92062672Swpaul bit -= 0x10; 92162672Swpaul SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 92262672Swpaul } 92362672Swpaul 92462672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 92562672Swpaul 92662672Swpaul return; 92762672Swpaul} 92862672Swpaul 929102334Salfredstatic void 930102334Salfredsis_setmulti_sis(sc) 93162672Swpaul struct sis_softc *sc; 93262672Swpaul{ 93362672Swpaul struct ifnet *ifp; 93462672Swpaul struct ifmultiaddr *ifma; 935109060Smbr u_int32_t h, i, n, ctl; 936109060Smbr u_int16_t hashes[16]; 93762672Swpaul 93862672Swpaul ifp = &sc->arpcom.ac_if; 93962672Swpaul 940109060Smbr /* hash table size */ 941109976Smbr if (sc->sis_rev >= SIS_REV_635 || 942109976Smbr sc->sis_rev == SIS_REV_900B) 943109976Smbr n = 16; 944109976Smbr else 945109976Smbr n = 8; 94662672Swpaul 947109060Smbr ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE; 94862672Swpaul 949109060Smbr if (ifp->if_flags & IFF_BROADCAST) 950109060Smbr ctl |= SIS_RXFILTCTL_BROAD; 95162672Swpaul 952109060Smbr if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 953109060Smbr ctl |= SIS_RXFILTCTL_ALLMULTI; 954109060Smbr if (ifp->if_flags & IFF_PROMISC) 955109060Smbr ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS; 956109060Smbr for (i = 0; i < n; i++) 957109060Smbr hashes[i] = ~0; 958109060Smbr } else { 959109060Smbr for (i = 0; i < n; i++) 960109060Smbr hashes[i] = 0; 961109060Smbr i = 0; 962109060Smbr TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 963109060Smbr if (ifma->ifma_addr->sa_family != AF_LINK) 964109060Smbr continue; 965109060Smbr h = sis_crc(sc, 966109060Smbr LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 967109060Smbr hashes[h >> 4] |= 1 << (h & 0xf); 968109060Smbr i++; 969109060Smbr } 970109060Smbr if (i > n) { 971109060Smbr ctl |= SIS_RXFILTCTL_ALLMULTI; 972109060Smbr for (i = 0; i < n; i++) 973109060Smbr hashes[i] = ~0; 974109060Smbr } 97550974Swpaul } 97650974Swpaul 977109060Smbr for (i = 0; i < n; i++) { 978109060Smbr CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); 979109060Smbr CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); 98050974Swpaul } 98150974Swpaul 982109060Smbr CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl); 98350974Swpaul} 98450974Swpaul 985102334Salfredstatic void 986102334Salfredsis_reset(sc) 98750974Swpaul struct sis_softc *sc; 98850974Swpaul{ 98950974Swpaul register int i; 99050974Swpaul 99150974Swpaul SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 99250974Swpaul 99350974Swpaul for (i = 0; i < SIS_TIMEOUT; i++) { 99450974Swpaul if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 99550974Swpaul break; 99650974Swpaul } 99750974Swpaul 99850974Swpaul if (i == SIS_TIMEOUT) 99950974Swpaul printf("sis%d: reset never completed\n", sc->sis_unit); 100050974Swpaul 100150974Swpaul /* Wait a little while for the chip to get its brains in order. */ 100250974Swpaul DELAY(1000); 100372813Swpaul 100472813Swpaul /* 100572813Swpaul * If this is a NetSemi chip, make sure to clear 100672813Swpaul * PME mode. 100772813Swpaul */ 100872813Swpaul if (sc->sis_type == SIS_TYPE_83815) { 100972813Swpaul CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 101072813Swpaul CSR_WRITE_4(sc, NS_CLKRUN, 0); 101172813Swpaul } 101272813Swpaul 101350974Swpaul return; 101450974Swpaul} 101550974Swpaul 101650974Swpaul/* 101750974Swpaul * Probe for an SiS chip. Check the PCI vendor and device 101850974Swpaul * IDs against our list and return a device name if we find a match. 101950974Swpaul */ 1020102334Salfredstatic int 1021102334Salfredsis_probe(dev) 102250974Swpaul device_t dev; 102350974Swpaul{ 102450974Swpaul struct sis_type *t; 102550974Swpaul 102650974Swpaul t = sis_devs; 102750974Swpaul 102850974Swpaul while(t->sis_name != NULL) { 102950974Swpaul if ((pci_get_vendor(dev) == t->sis_vid) && 103050974Swpaul (pci_get_device(dev) == t->sis_did)) { 103150974Swpaul device_set_desc(dev, t->sis_name); 103250974Swpaul return(0); 103350974Swpaul } 103450974Swpaul t++; 103550974Swpaul } 103650974Swpaul 103750974Swpaul return(ENXIO); 103850974Swpaul} 103950974Swpaul 104050974Swpaul/* 104150974Swpaul * Attach the interface. Allocate softc structures, do ifmedia 104250974Swpaul * setup and ethernet/BPF attach. 104350974Swpaul */ 1044102334Salfredstatic int 1045102334Salfredsis_attach(dev) 104650974Swpaul device_t dev; 104750974Swpaul{ 104850974Swpaul u_char eaddr[ETHER_ADDR_LEN]; 104950974Swpaul u_int32_t command; 105050974Swpaul struct sis_softc *sc; 105150974Swpaul struct ifnet *ifp; 1052109061Smbr int unit, error = 0, rid, waittime = 0; 105350974Swpaul 1054109061Smbr waittime = 0; 105550974Swpaul sc = device_get_softc(dev); 105650974Swpaul unit = device_get_unit(dev); 105750974Swpaul bzero(sc, sizeof(struct sis_softc)); 105850974Swpaul 105993818Sjhb mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 106093818Sjhb MTX_DEF | MTX_RECURSE); 106169583Swpaul 106250974Swpaul if (pci_get_device(dev) == SIS_DEVICEID_900) 106350974Swpaul sc->sis_type = SIS_TYPE_900; 106450974Swpaul if (pci_get_device(dev) == SIS_DEVICEID_7016) 106550974Swpaul sc->sis_type = SIS_TYPE_7016; 106662672Swpaul if (pci_get_vendor(dev) == NS_VENDORID) 106762672Swpaul sc->sis_type = SIS_TYPE_83815; 106850974Swpaul 106989296Swpaul sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 107089296Swpaul 107150974Swpaul /* 107250974Swpaul * Handle power management nonsense. 107350974Swpaul */ 107472813Swpaul if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 107572813Swpaul u_int32_t iobase, membase, irq; 107650974Swpaul 107772813Swpaul /* Save important PCI config data. */ 107872813Swpaul iobase = pci_read_config(dev, SIS_PCI_LOIO, 4); 107972813Swpaul membase = pci_read_config(dev, SIS_PCI_LOMEM, 4); 108072813Swpaul irq = pci_read_config(dev, SIS_PCI_INTLINE, 4); 108150974Swpaul 108272813Swpaul /* Reset the power state. */ 108372813Swpaul printf("sis%d: chip is in D%d power mode " 108472813Swpaul "-- setting to D0\n", unit, 108572813Swpaul pci_get_powerstate(dev)); 108672813Swpaul pci_set_powerstate(dev, PCI_POWERSTATE_D0); 108750974Swpaul 108872813Swpaul /* Restore PCI config data. */ 108972813Swpaul pci_write_config(dev, SIS_PCI_LOIO, iobase, 4); 109072813Swpaul pci_write_config(dev, SIS_PCI_LOMEM, membase, 4); 109172813Swpaul pci_write_config(dev, SIS_PCI_INTLINE, irq, 4); 109250974Swpaul } 109350974Swpaul 109450974Swpaul /* 109550974Swpaul * Map control/status registers. 109650974Swpaul */ 109772813Swpaul pci_enable_busmaster(dev); 109879472Swpaul pci_enable_io(dev, SYS_RES_IOPORT); 109979472Swpaul pci_enable_io(dev, SYS_RES_MEMORY); 110061041Speter command = pci_read_config(dev, PCIR_COMMAND, 4); 110150974Swpaul 110250974Swpaul#ifdef SIS_USEIOSPACE 110350974Swpaul if (!(command & PCIM_CMD_PORTEN)) { 110450974Swpaul printf("sis%d: failed to enable I/O ports!\n", unit); 110550974Swpaul error = ENXIO;; 110650974Swpaul goto fail; 110750974Swpaul } 110850974Swpaul#else 110950974Swpaul if (!(command & PCIM_CMD_MEMEN)) { 111050974Swpaul printf("sis%d: failed to enable memory mapping!\n", unit); 111150974Swpaul error = ENXIO;; 111250974Swpaul goto fail; 111350974Swpaul } 111450974Swpaul#endif 111550974Swpaul 111650974Swpaul rid = SIS_RID; 111750974Swpaul sc->sis_res = bus_alloc_resource(dev, SIS_RES, &rid, 111850974Swpaul 0, ~0, 1, RF_ACTIVE); 111950974Swpaul 112050974Swpaul if (sc->sis_res == NULL) { 112150974Swpaul printf("sis%d: couldn't map ports/memory\n", unit); 112250974Swpaul error = ENXIO; 112350974Swpaul goto fail; 112450974Swpaul } 112550974Swpaul 112650974Swpaul sc->sis_btag = rman_get_bustag(sc->sis_res); 112750974Swpaul sc->sis_bhandle = rman_get_bushandle(sc->sis_res); 112850974Swpaul 112950974Swpaul /* Allocate interrupt */ 113050974Swpaul rid = 0; 113150974Swpaul sc->sis_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 113250974Swpaul RF_SHAREABLE | RF_ACTIVE); 113350974Swpaul 113450974Swpaul if (sc->sis_irq == NULL) { 113550974Swpaul printf("sis%d: couldn't map interrupt\n", unit); 113650974Swpaul bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 113750974Swpaul error = ENXIO; 113850974Swpaul goto fail; 113950974Swpaul } 114050974Swpaul 114150974Swpaul error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET, 114250974Swpaul sis_intr, sc, &sc->sis_intrhand); 114350974Swpaul 114450974Swpaul if (error) { 114568216Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 114650974Swpaul bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 114750974Swpaul printf("sis%d: couldn't set up irq\n", unit); 114850974Swpaul goto fail; 114950974Swpaul } 115050974Swpaul 115150974Swpaul /* Reset the adapter. */ 115250974Swpaul sis_reset(sc); 115350974Swpaul 1154109976Smbr if (sc->sis_type == SIS_TYPE_900 && 1155109976Smbr (sc->sis_rev == SIS_REV_635 || 1156109976Smbr sc->sis_rev == SIS_REV_900B)) { 1157109976Smbr SIO_SET(SIS_CFG_RND_CNT); 1158109976Smbr SIO_SET(SIS_CFG_PERR_DETECT); 1159109976Smbr } 1160109976Smbr 116150974Swpaul /* 116250974Swpaul * Get station address from the EEPROM. 116350974Swpaul */ 116462672Swpaul switch (pci_get_vendor(dev)) { 116562672Swpaul case NS_VENDORID: 116662672Swpaul /* 116762672Swpaul * Reading the MAC address out of the EEPROM on 116862672Swpaul * the NatSemi chip takes a bit more work than 116962672Swpaul * you'd expect. The address spans 4 16-bit words, 117062672Swpaul * with the first word containing only a single bit. 117162672Swpaul * You have to shift everything over one bit to 117262672Swpaul * get it aligned properly. Also, the bits are 117362672Swpaul * stored backwards (the LSB is really the MSB, 117462672Swpaul * and so on) so you have to reverse them in order 117562672Swpaul * to get the MAC address into the form we want. 117662672Swpaul * Why? Who the hell knows. 117762672Swpaul */ 117862672Swpaul { 117962672Swpaul u_int16_t tmp[4]; 118050974Swpaul 118162672Swpaul sis_read_eeprom(sc, (caddr_t)&tmp, 118262672Swpaul NS_EE_NODEADDR, 4, 0); 118362672Swpaul 118462672Swpaul /* Shift everything over one bit. */ 118562672Swpaul tmp[3] = tmp[3] >> 1; 118662681Swpaul tmp[3] |= tmp[2] << 15; 118762672Swpaul tmp[2] = tmp[2] >> 1; 118862681Swpaul tmp[2] |= tmp[1] << 15; 118962672Swpaul tmp[1] = tmp[1] >> 1; 119062681Swpaul tmp[1] |= tmp[0] << 15; 119162672Swpaul 119262672Swpaul /* Now reverse all the bits. */ 119362672Swpaul tmp[3] = sis_reverse(tmp[3]); 119462672Swpaul tmp[2] = sis_reverse(tmp[2]); 119562672Swpaul tmp[1] = sis_reverse(tmp[1]); 119662672Swpaul 119762672Swpaul bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); 119862672Swpaul } 119962672Swpaul break; 120062672Swpaul case SIS_VENDORID: 120162672Swpaul default: 120272197Swpaul#ifdef __i386__ 120372197Swpaul /* 120472197Swpaul * If this is a SiS 630E chipset with an embedded 120572197Swpaul * SiS 900 controller, we have to read the MAC address 120672197Swpaul * from the APC CMOS RAM. Our method for doing this 120772197Swpaul * is very ugly since we have to reach out and grab 120872197Swpaul * ahold of hardware for which we cannot properly 120972197Swpaul * allocate resources. This code is only compiled on 121072197Swpaul * the i386 architecture since the SiS 630E chipset 121172197Swpaul * is for x86 motherboards only. Note that there are 121272197Swpaul * a lot of magic numbers in this hack. These are 121372197Swpaul * taken from SiS's Linux driver. I'd like to replace 121472197Swpaul * them with proper symbolic definitions, but that 121572197Swpaul * requires some datasheets that I don't have access 121672197Swpaul * to at the moment. 121772197Swpaul */ 121889296Swpaul if (sc->sis_rev == SIS_REV_630S || 121989296Swpaul sc->sis_rev == SIS_REV_630E || 122090328Sambrisko sc->sis_rev == SIS_REV_630EA1) 122172197Swpaul sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 122289296Swpaul 122390328Sambrisko else if (sc->sis_rev == SIS_REV_635 || 122490328Sambrisko sc->sis_rev == SIS_REV_630ET) 122589296Swpaul sis_read_mac(sc, dev, (caddr_t)&eaddr); 1226109061Smbr else if (sc->sis_rev == SIS_REV_96x) { 1227109061Smbr /* Allow to read EEPROM from LAN. It is shared 1228109061Smbr * between a 1394 controller and the NIC and each 1229109061Smbr * time we access it, we need to set SIS_EECMD_REQ. 1230109061Smbr */ 1231109061Smbr SIO_SET(SIS_EECMD_REQ); 1232109061Smbr for (waittime = 0; waittime < SIS_TIMEOUT; 1233109061Smbr waittime++) { 1234109061Smbr /* Force EEPROM to idle state. */ 1235109061Smbr sis_eeprom_idle(sc); 1236109061Smbr if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { 1237109061Smbr sis_read_eeprom(sc, (caddr_t)&eaddr, 1238109061Smbr SIS_EE_NODEADDR, 3, 0); 1239109061Smbr break; 1240109061Smbr } 1241109061Smbr DELAY(1); 1242109061Smbr } 1243109061Smbr /* 1244109061Smbr * Set SIS_EECTL_CLK to high, so a other master 1245109061Smbr * can operate on the i2c bus. 1246109061Smbr */ 1247109061Smbr SIO_SET(SIS_EECTL_CLK); 1248109061Smbr /* Refuse EEPROM access by LAN */ 1249109061Smbr SIO_SET(SIS_EECMD_DONE); 1250109061Smbr } else 125172197Swpaul#endif 125272197Swpaul sis_read_eeprom(sc, (caddr_t)&eaddr, 125372197Swpaul SIS_EE_NODEADDR, 3, 0); 125462672Swpaul break; 125562672Swpaul } 125662672Swpaul 125750974Swpaul /* 125850974Swpaul * A SiS chip was detected. Inform the world. 125950974Swpaul */ 126050974Swpaul printf("sis%d: Ethernet address: %6D\n", unit, eaddr, ":"); 126150974Swpaul 126250974Swpaul sc->sis_unit = unit; 126350974Swpaul callout_handle_init(&sc->sis_stat_ch); 126450974Swpaul bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 126550974Swpaul 126681713Swpaul /* 126781713Swpaul * Allocate the parent bus DMA tag appropriate for PCI. 126881713Swpaul */ 126981713Swpaul#define SIS_NSEG_NEW 32 127081713Swpaul error = bus_dma_tag_create(NULL, /* parent */ 127181713Swpaul 1, 0, /* alignment, boundary */ 127281713Swpaul BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 127381713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 127481713Swpaul NULL, NULL, /* filter, filterarg */ 127581713Swpaul MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */ 127681713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 127781713Swpaul BUS_DMA_ALLOCNOW, /* flags */ 127881713Swpaul &sc->sis_parent_tag); 127950974Swpaul 128081713Swpaul /* 128181713Swpaul * Now allocate a tag for the DMA descriptor lists. 128281713Swpaul * All of our lists are allocated as a contiguous block 128381713Swpaul * of memory. 128481713Swpaul */ 128581713Swpaul error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 128681713Swpaul 1, 0, /* alignment, boundary */ 128781713Swpaul BUS_SPACE_MAXADDR, /* lowaddr */ 128881713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 128981713Swpaul NULL, NULL, /* filter, filterarg */ 129081713Swpaul SIS_RX_LIST_SZ, 1, /* maxsize,nsegments */ 129181713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 129281713Swpaul 0, /* flags */ 129381713Swpaul &sc->sis_ldata.sis_rx_tag); 129481713Swpaul 129581713Swpaul error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 129681713Swpaul 1, 0, /* alignment, boundary */ 129781713Swpaul BUS_SPACE_MAXADDR, /* lowaddr */ 129881713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 129981713Swpaul NULL, NULL, /* filter, filterarg */ 130081713Swpaul SIS_TX_LIST_SZ, 1, /* maxsize,nsegments */ 130181713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 130281713Swpaul 0, /* flags */ 130381713Swpaul &sc->sis_ldata.sis_tx_tag); 130481713Swpaul 130581713Swpaul error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 130681713Swpaul 1, 0, /* alignment, boundary */ 130781713Swpaul BUS_SPACE_MAXADDR, /* lowaddr */ 130881713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 130981713Swpaul NULL, NULL, /* filter, filterarg */ 1310107833Smux MCLBYTES, 1, /* maxsize,nsegments */ 131181713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 131281713Swpaul 0, /* flags */ 131381713Swpaul &sc->sis_tag); 131481713Swpaul 131581713Swpaul /* 131681713Swpaul * Now allocate a chunk of DMA-able memory based on the 131781713Swpaul * tag we just created. 131881713Swpaul */ 131981713Swpaul error = bus_dmamem_alloc(sc->sis_ldata.sis_tx_tag, 132081713Swpaul (void **)&sc->sis_ldata.sis_tx_list, BUS_DMA_NOWAIT, 132181713Swpaul &sc->sis_ldata.sis_tx_dmamap); 132281713Swpaul 132381713Swpaul if (error) { 132450974Swpaul printf("sis%d: no memory for list buffers!\n", unit); 132550974Swpaul bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 132650974Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 132750974Swpaul bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 132881713Swpaul bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 132981713Swpaul bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 133050974Swpaul error = ENXIO; 133150974Swpaul goto fail; 133250974Swpaul } 133350974Swpaul 133481713Swpaul error = bus_dmamem_alloc(sc->sis_ldata.sis_rx_tag, 133581713Swpaul (void **)&sc->sis_ldata.sis_rx_list, BUS_DMA_NOWAIT, 133681713Swpaul &sc->sis_ldata.sis_rx_dmamap); 133781713Swpaul 133881713Swpaul if (error) { 133981713Swpaul printf("sis%d: no memory for list buffers!\n", unit); 134081713Swpaul bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 134181713Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 134281713Swpaul bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 134381713Swpaul bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 134481713Swpaul sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 134581713Swpaul bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 134681713Swpaul bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 134781713Swpaul error = ENXIO; 134881713Swpaul goto fail; 134981713Swpaul } 135081713Swpaul 135181713Swpaul 135281713Swpaul bzero(sc->sis_ldata.sis_tx_list, SIS_TX_LIST_SZ); 135381713Swpaul bzero(sc->sis_ldata.sis_rx_list, SIS_RX_LIST_SZ); 135481713Swpaul 135581713Swpaul /* 135681713Swpaul * Obtain the physical addresses of the RX and TX 135781713Swpaul * rings which we'll need later in the init routine. 135881713Swpaul */ 135981713Swpaul bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 136081713Swpaul sc->sis_ldata.sis_tx_dmamap, &(sc->sis_ldata.sis_tx_list[0]), 136181713Swpaul sizeof(struct sis_desc), sis_dma_map_ring, 136281713Swpaul &sc->sis_cdata.sis_tx_paddr, 0); 136381713Swpaul bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 136481713Swpaul sc->sis_ldata.sis_rx_dmamap, &(sc->sis_ldata.sis_rx_list[0]), 136581713Swpaul sizeof(struct sis_desc), sis_dma_map_ring, 136681713Swpaul &sc->sis_cdata.sis_rx_paddr, 0); 136781713Swpaul 136850974Swpaul ifp = &sc->arpcom.ac_if; 136950974Swpaul ifp->if_softc = sc; 137050974Swpaul ifp->if_unit = unit; 137150974Swpaul ifp->if_name = "sis"; 137250974Swpaul ifp->if_mtu = ETHERMTU; 137350974Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 137450974Swpaul ifp->if_ioctl = sis_ioctl; 137550974Swpaul ifp->if_output = ether_output; 137650974Swpaul ifp->if_start = sis_start; 137750974Swpaul ifp->if_watchdog = sis_watchdog; 137850974Swpaul ifp->if_init = sis_init; 137950974Swpaul ifp->if_baudrate = 10000000; 138050974Swpaul ifp->if_snd.ifq_maxlen = SIS_TX_LIST_CNT - 1; 138150974Swpaul 138250974Swpaul /* 138350974Swpaul * Do MII setup. 138450974Swpaul */ 138550974Swpaul if (mii_phy_probe(dev, &sc->sis_miibus, 138650974Swpaul sis_ifmedia_upd, sis_ifmedia_sts)) { 138750974Swpaul printf("sis%d: MII without any PHY!\n", sc->sis_unit); 138850974Swpaul bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 138950974Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 139050974Swpaul bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 139181713Swpaul bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 139281713Swpaul sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap); 139381713Swpaul bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 139481713Swpaul sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 139581713Swpaul bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 139681713Swpaul bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 139750974Swpaul error = ENXIO; 139850974Swpaul goto fail; 139950974Swpaul } 140050974Swpaul 140150974Swpaul /* 140263090Sarchie * Call MI attach routine. 140350974Swpaul */ 1404106936Ssam ether_ifattach(ifp, eaddr); 140587390Sjhay 140687390Sjhay /* 140787390Sjhay * Tell the upper layer(s) we support long frames. 140887390Sjhay */ 140987390Sjhay ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1410106936Ssam ifp->if_capabilities |= IFCAP_VLAN_MTU; 141187390Sjhay 141250974Swpaul callout_handle_init(&sc->sis_stat_ch); 141367087Swpaul return(0); 141450974Swpaul 141550974Swpaulfail: 141667087Swpaul mtx_destroy(&sc->sis_mtx); 141750974Swpaul return(error); 141850974Swpaul} 141950974Swpaul 1420102334Salfredstatic int 1421102334Salfredsis_detach(dev) 142250974Swpaul device_t dev; 142350974Swpaul{ 142450974Swpaul struct sis_softc *sc; 142550974Swpaul struct ifnet *ifp; 142650974Swpaul 142750974Swpaul 142850974Swpaul sc = device_get_softc(dev); 142967087Swpaul SIS_LOCK(sc); 143050974Swpaul ifp = &sc->arpcom.ac_if; 143150974Swpaul 143250974Swpaul sis_reset(sc); 143350974Swpaul sis_stop(sc); 1434106936Ssam ether_ifdetach(ifp); 143550974Swpaul 143650974Swpaul bus_generic_detach(dev); 143750974Swpaul device_delete_child(dev, sc->sis_miibus); 143850974Swpaul 143950974Swpaul bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 144050974Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 144150974Swpaul bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 144250974Swpaul 144381713Swpaul bus_dmamap_unload(sc->sis_ldata.sis_rx_tag, 144481713Swpaul sc->sis_ldata.sis_rx_dmamap); 144581713Swpaul bus_dmamap_unload(sc->sis_ldata.sis_tx_tag, 144681713Swpaul sc->sis_ldata.sis_tx_dmamap); 144781713Swpaul bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 144881713Swpaul sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap); 144981713Swpaul bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 145081713Swpaul sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 145181713Swpaul bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 145281713Swpaul bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 145381713Swpaul bus_dma_tag_destroy(sc->sis_parent_tag); 145450974Swpaul 145567087Swpaul SIS_UNLOCK(sc); 145667087Swpaul mtx_destroy(&sc->sis_mtx); 145750974Swpaul 145850974Swpaul return(0); 145950974Swpaul} 146050974Swpaul 146150974Swpaul/* 146250974Swpaul * Initialize the transmit descriptors. 146350974Swpaul */ 1464102334Salfredstatic int 1465102334Salfredsis_list_tx_init(sc) 146650974Swpaul struct sis_softc *sc; 146750974Swpaul{ 146850974Swpaul struct sis_list_data *ld; 146950974Swpaul struct sis_ring_data *cd; 147087059Sluigi int i, nexti; 147150974Swpaul 147250974Swpaul cd = &sc->sis_cdata; 147381713Swpaul ld = &sc->sis_ldata; 147450974Swpaul 147550974Swpaul for (i = 0; i < SIS_TX_LIST_CNT; i++) { 147687102Sluigi nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1; 147750974Swpaul ld->sis_tx_list[i].sis_nextdesc = 147887059Sluigi &ld->sis_tx_list[nexti]; 147981713Swpaul bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 148081713Swpaul sc->sis_ldata.sis_tx_dmamap, 148187059Sluigi &ld->sis_tx_list[nexti], sizeof(struct sis_desc), 148281713Swpaul sis_dma_map_desc_next, &ld->sis_tx_list[i], 0); 148350974Swpaul ld->sis_tx_list[i].sis_mbuf = NULL; 148450974Swpaul ld->sis_tx_list[i].sis_ptr = 0; 148550974Swpaul ld->sis_tx_list[i].sis_ctl = 0; 148650974Swpaul } 148750974Swpaul 148850974Swpaul cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0; 148950974Swpaul 149081713Swpaul bus_dmamap_sync(sc->sis_ldata.sis_tx_tag, 149181713Swpaul sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 149281713Swpaul 149350974Swpaul return(0); 149450974Swpaul} 149550974Swpaul 149650974Swpaul/* 149750974Swpaul * Initialize the RX descriptors and allocate mbufs for them. Note that 149850974Swpaul * we arrange the descriptors in a closed ring, so that the last descriptor 149950974Swpaul * points back to the first. 150050974Swpaul */ 1501102334Salfredstatic int 1502102334Salfredsis_list_rx_init(sc) 150350974Swpaul struct sis_softc *sc; 150450974Swpaul{ 150550974Swpaul struct sis_list_data *ld; 150650974Swpaul struct sis_ring_data *cd; 150787059Sluigi int i,nexti; 150850974Swpaul 150981713Swpaul ld = &sc->sis_ldata; 151050974Swpaul cd = &sc->sis_cdata; 151150974Swpaul 151250974Swpaul for (i = 0; i < SIS_RX_LIST_CNT; i++) { 151350974Swpaul if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS) 151450974Swpaul return(ENOBUFS); 151587102Sluigi nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1; 151650974Swpaul ld->sis_rx_list[i].sis_nextdesc = 151787059Sluigi &ld->sis_rx_list[nexti]; 151881713Swpaul bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 151981713Swpaul sc->sis_ldata.sis_rx_dmamap, 152087059Sluigi &ld->sis_rx_list[nexti], 152181713Swpaul sizeof(struct sis_desc), sis_dma_map_desc_next, 152281713Swpaul &ld->sis_rx_list[i], 0); 152350974Swpaul } 152450974Swpaul 152581713Swpaul bus_dmamap_sync(sc->sis_ldata.sis_rx_tag, 152681713Swpaul sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 152781713Swpaul 152850974Swpaul cd->sis_rx_prod = 0; 152950974Swpaul 153050974Swpaul return(0); 153150974Swpaul} 153250974Swpaul 153350974Swpaul/* 153450974Swpaul * Initialize an RX descriptor and attach an MBUF cluster. 153550974Swpaul */ 1536102334Salfredstatic int 1537102334Salfredsis_newbuf(sc, c, m) 153850974Swpaul struct sis_softc *sc; 153950974Swpaul struct sis_desc *c; 154050974Swpaul struct mbuf *m; 154150974Swpaul{ 154250974Swpaul 154381713Swpaul if (c == NULL) 154481713Swpaul return(EINVAL); 154581713Swpaul 154650974Swpaul if (m == NULL) { 1547109623Salfred m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1548101340Sluigi if (m == NULL) 154950974Swpaul return(ENOBUFS); 1550101340Sluigi } else 1551101340Sluigi m->m_data = m->m_ext.ext_buf; 155250974Swpaul 1553101340Sluigi c->sis_mbuf = m; 155450974Swpaul c->sis_ctl = SIS_RXLEN; 155550974Swpaul 155681713Swpaul bus_dmamap_create(sc->sis_tag, 0, &c->sis_map); 155781713Swpaul bus_dmamap_load(sc->sis_tag, c->sis_map, 1558101464Sluigi mtod(m, void *), MCLBYTES, 155981713Swpaul sis_dma_map_desc_ptr, c, 0); 156081713Swpaul bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREWRITE); 156181713Swpaul 156250974Swpaul return(0); 156350974Swpaul} 156450974Swpaul 156550974Swpaul/* 156650974Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 156750974Swpaul * the higher level protocols. 156850974Swpaul */ 1569102334Salfredstatic void 1570102334Salfredsis_rxeof(sc) 157150974Swpaul struct sis_softc *sc; 157250974Swpaul{ 157350974Swpaul struct mbuf *m; 157450974Swpaul struct ifnet *ifp; 157550974Swpaul struct sis_desc *cur_rx; 157650974Swpaul int i, total_len = 0; 157750974Swpaul u_int32_t rxstat; 157850974Swpaul 157950974Swpaul ifp = &sc->arpcom.ac_if; 158050974Swpaul i = sc->sis_cdata.sis_rx_prod; 158150974Swpaul 158281713Swpaul while(SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) { 158350974Swpaul 158487902Sluigi#ifdef DEVICE_POLLING 1585102052Ssobomax if (ifp->if_flags & IFF_POLLING) { 158687902Sluigi if (sc->rxcycles <= 0) 158787902Sluigi break; 158887902Sluigi sc->rxcycles--; 158987902Sluigi } 159087902Sluigi#endif /* DEVICE_POLLING */ 159181713Swpaul cur_rx = &sc->sis_ldata.sis_rx_list[i]; 159250974Swpaul rxstat = cur_rx->sis_rxstat; 159381713Swpaul bus_dmamap_sync(sc->sis_tag, 159481713Swpaul cur_rx->sis_map, BUS_DMASYNC_POSTWRITE); 159581713Swpaul bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map); 159681713Swpaul bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map); 159750974Swpaul m = cur_rx->sis_mbuf; 159850974Swpaul cur_rx->sis_mbuf = NULL; 159950974Swpaul total_len = SIS_RXBYTES(cur_rx); 160050974Swpaul SIS_INC(i, SIS_RX_LIST_CNT); 160150974Swpaul 160250974Swpaul /* 160350974Swpaul * If an error occurs, update stats, clear the 160450974Swpaul * status word and leave the mbuf cluster in place: 160550974Swpaul * it should simply get re-used next time this descriptor 160650974Swpaul * comes up in the ring. 160750974Swpaul */ 160850974Swpaul if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 160950974Swpaul ifp->if_ierrors++; 161050974Swpaul if (rxstat & SIS_RXSTAT_COLL) 161150974Swpaul ifp->if_collisions++; 161250974Swpaul sis_newbuf(sc, cur_rx, m); 161350974Swpaul continue; 161450974Swpaul } 161550974Swpaul 161650974Swpaul /* No errors; receive the packet. */ 161787059Sluigi#ifdef __i386__ 161887059Sluigi /* 161987059Sluigi * On the x86 we do not have alignment problems, so try to 162087059Sluigi * allocate a new buffer for the receive ring, and pass up 162187059Sluigi * the one where the packet is already, saving the expensive 162287059Sluigi * copy done in m_devget(). 162387059Sluigi * If we are on an architecture with alignment problems, or 162487059Sluigi * if the allocation fails, then use m_devget and leave the 162587059Sluigi * existing buffer in the receive ring. 162687059Sluigi */ 1627101464Sluigi if (sis_newbuf(sc, cur_rx, NULL) == 0) 162887059Sluigi m->m_pkthdr.len = m->m_len = total_len; 1629101464Sluigi else 163087059Sluigi#endif 163187059Sluigi { 163287059Sluigi struct mbuf *m0; 163387059Sluigi m0 = m_devget(mtod(m, char *), total_len, 163487059Sluigi ETHER_ALIGN, ifp, NULL); 163587059Sluigi sis_newbuf(sc, cur_rx, m); 163687059Sluigi if (m0 == NULL) { 163787059Sluigi ifp->if_ierrors++; 163887059Sluigi continue; 163987059Sluigi } 164087059Sluigi m = m0; 164150974Swpaul } 164250974Swpaul 164350974Swpaul ifp->if_ipackets++; 1644106936Ssam m->m_pkthdr.rcvif = ifp; 1645106936Ssam 1646106936Ssam (*ifp->if_input)(ifp, m); 164750974Swpaul } 164850974Swpaul 164950974Swpaul sc->sis_cdata.sis_rx_prod = i; 165050974Swpaul 165150974Swpaul return; 165250974Swpaul} 165350974Swpaul 1654105219Sphkstatic void 1655102334Salfredsis_rxeoc(sc) 165650974Swpaul struct sis_softc *sc; 165750974Swpaul{ 165850974Swpaul sis_rxeof(sc); 165950974Swpaul sis_init(sc); 166050974Swpaul return; 166150974Swpaul} 166250974Swpaul 166350974Swpaul/* 166450974Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 166550974Swpaul * the list buffers. 166650974Swpaul */ 166750974Swpaul 1668102334Salfredstatic void 1669102334Salfredsis_txeof(sc) 167050974Swpaul struct sis_softc *sc; 167150974Swpaul{ 167250974Swpaul struct ifnet *ifp; 167350974Swpaul u_int32_t idx; 167450974Swpaul 167550974Swpaul ifp = &sc->arpcom.ac_if; 167650974Swpaul 167750974Swpaul /* 167850974Swpaul * Go through our tx list and free mbufs for those 167950974Swpaul * frames that have been transmitted. 168050974Swpaul */ 168199163Sluigi for (idx = sc->sis_cdata.sis_tx_cons; sc->sis_cdata.sis_tx_cnt > 0; 168299163Sluigi sc->sis_cdata.sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) { 168399163Sluigi struct sis_desc *cur_tx = &sc->sis_ldata.sis_tx_list[idx]; 168450974Swpaul 168550974Swpaul if (SIS_OWNDESC(cur_tx)) 168650974Swpaul break; 168750974Swpaul 168899163Sluigi if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) 168950974Swpaul continue; 169050974Swpaul 169150974Swpaul if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 169250974Swpaul ifp->if_oerrors++; 169350974Swpaul if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 169450974Swpaul ifp->if_collisions++; 169550974Swpaul if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 169650974Swpaul ifp->if_collisions++; 169750974Swpaul } 169850974Swpaul 169950974Swpaul ifp->if_collisions += 170050974Swpaul (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 170150974Swpaul 170250974Swpaul ifp->if_opackets++; 170350974Swpaul if (cur_tx->sis_mbuf != NULL) { 170450974Swpaul m_freem(cur_tx->sis_mbuf); 170550974Swpaul cur_tx->sis_mbuf = NULL; 170681713Swpaul bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map); 170781713Swpaul bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map); 170850974Swpaul } 170999163Sluigi } 171050974Swpaul 171199163Sluigi if (idx != sc->sis_cdata.sis_tx_cons) { 171299163Sluigi /* we freed up some buffers */ 171399163Sluigi sc->sis_cdata.sis_tx_cons = idx; 171499163Sluigi ifp->if_flags &= ~IFF_OACTIVE; 171550974Swpaul } 171650974Swpaul 171799163Sluigi ifp->if_timer = (sc->sis_cdata.sis_tx_cnt == 0) ? 0 : 5; 171850974Swpaul 171950974Swpaul return; 172050974Swpaul} 172150974Swpaul 1722102334Salfredstatic void 1723102334Salfredsis_tick(xsc) 172450974Swpaul void *xsc; 172550974Swpaul{ 172650974Swpaul struct sis_softc *sc; 172750974Swpaul struct mii_data *mii; 172864963Swpaul struct ifnet *ifp; 172950974Swpaul 173050974Swpaul sc = xsc; 173167087Swpaul SIS_LOCK(sc); 173264963Swpaul ifp = &sc->arpcom.ac_if; 173364963Swpaul 173450974Swpaul mii = device_get_softc(sc->sis_miibus); 173550974Swpaul mii_tick(mii); 173664963Swpaul 173784147Sjlemon if (!sc->sis_link && mii->mii_media_status & IFM_ACTIVE && 173884147Sjlemon IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 173984147Sjlemon sc->sis_link++; 174084147Sjlemon if (ifp->if_snd.ifq_head != NULL) 174184147Sjlemon sis_start(ifp); 174264963Swpaul } 174364963Swpaul 174451031Swpaul sc->sis_stat_ch = timeout(sis_tick, sc, hz); 174550974Swpaul 174667087Swpaul SIS_UNLOCK(sc); 174750974Swpaul 174850974Swpaul return; 174950974Swpaul} 175050974Swpaul 175187902Sluigi#ifdef DEVICE_POLLING 175287902Sluigistatic poll_handler_t sis_poll; 175387902Sluigi 175487902Sluigistatic void 175587902Sluigisis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 175687902Sluigi{ 175787973Speter struct sis_softc *sc = ifp->if_softc; 175887973Speter 175987902Sluigi SIS_LOCK(sc); 176087902Sluigi if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 176187902Sluigi CSR_WRITE_4(sc, SIS_IER, 1); 176287902Sluigi goto done; 176387902Sluigi } 176487902Sluigi 176587902Sluigi /* 176687902Sluigi * On the sis, reading the status register also clears it. 176787902Sluigi * So before returning to intr mode we must make sure that all 176887902Sluigi * possible pending sources of interrupts have been served. 176987902Sluigi * In practice this means run to completion the *eof routines, 177087902Sluigi * and then call the interrupt routine 177187902Sluigi */ 177287902Sluigi sc->rxcycles = count; 177387902Sluigi sis_rxeof(sc); 177487902Sluigi sis_txeof(sc); 177587902Sluigi if (ifp->if_snd.ifq_head != NULL) 177687902Sluigi sis_start(ifp); 177787902Sluigi 177887902Sluigi if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 177987902Sluigi u_int32_t status; 178087902Sluigi 178187902Sluigi /* Reading the ISR register clears all interrupts. */ 178287902Sluigi status = CSR_READ_4(sc, SIS_ISR); 178387902Sluigi 178487902Sluigi if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 178587902Sluigi sis_rxeoc(sc); 178687902Sluigi 178787902Sluigi if (status & (SIS_ISR_RX_IDLE)) 178887902Sluigi SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 178987902Sluigi 179087902Sluigi if (status & SIS_ISR_SYSERR) { 179187902Sluigi sis_reset(sc); 179287902Sluigi sis_init(sc); 179387902Sluigi } 179487902Sluigi } 179587902Sluigidone: 179687902Sluigi SIS_UNLOCK(sc); 179787902Sluigi return; 179887902Sluigi} 179987902Sluigi#endif /* DEVICE_POLLING */ 180087902Sluigi 1801102334Salfredstatic void 1802102334Salfredsis_intr(arg) 180350974Swpaul void *arg; 180450974Swpaul{ 180550974Swpaul struct sis_softc *sc; 180650974Swpaul struct ifnet *ifp; 180750974Swpaul u_int32_t status; 180850974Swpaul 180950974Swpaul sc = arg; 181050974Swpaul ifp = &sc->arpcom.ac_if; 181150974Swpaul 181286984Sluigi SIS_LOCK(sc); 181387902Sluigi#ifdef DEVICE_POLLING 1814102052Ssobomax if (ifp->if_flags & IFF_POLLING) 181587902Sluigi goto done; 181687902Sluigi if (ether_poll_register(sis_poll, ifp)) { /* ok, disable interrupts */ 181787902Sluigi CSR_WRITE_4(sc, SIS_IER, 0); 181887902Sluigi goto done; 181987902Sluigi } 182087902Sluigi#endif /* DEVICE_POLLING */ 182187902Sluigi 182250974Swpaul /* Supress unwanted interrupts */ 182350974Swpaul if (!(ifp->if_flags & IFF_UP)) { 182450974Swpaul sis_stop(sc); 182586984Sluigi goto done; 182650974Swpaul } 182750974Swpaul 182850974Swpaul /* Disable interrupts. */ 182950974Swpaul CSR_WRITE_4(sc, SIS_IER, 0); 183050974Swpaul 183150974Swpaul for (;;) { 183250974Swpaul /* Reading the ISR register clears all interrupts. */ 183350974Swpaul status = CSR_READ_4(sc, SIS_ISR); 183450974Swpaul 183550974Swpaul if ((status & SIS_INTRS) == 0) 183650974Swpaul break; 183750974Swpaul 183886984Sluigi if (status & 183986984Sluigi (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | 184086984Sluigi SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) ) 184150974Swpaul sis_txeof(sc); 184250974Swpaul 184386984Sluigi if (status & (SIS_ISR_RX_DESC_OK|SIS_ISR_RX_OK|SIS_ISR_RX_IDLE)) 184450974Swpaul sis_rxeof(sc); 184550974Swpaul 184686984Sluigi if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW)) 184750974Swpaul sis_rxeoc(sc); 184850974Swpaul 184986984Sluigi if (status & (SIS_ISR_RX_IDLE)) 185086984Sluigi SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 185186984Sluigi 185250974Swpaul if (status & SIS_ISR_SYSERR) { 185350974Swpaul sis_reset(sc); 185450974Swpaul sis_init(sc); 185550974Swpaul } 185650974Swpaul } 185750974Swpaul 185850974Swpaul /* Re-enable interrupts. */ 185950974Swpaul CSR_WRITE_4(sc, SIS_IER, 1); 186050974Swpaul 186150974Swpaul if (ifp->if_snd.ifq_head != NULL) 186250974Swpaul sis_start(ifp); 186386984Sluigidone: 186467087Swpaul SIS_UNLOCK(sc); 186567087Swpaul 186650974Swpaul return; 186750974Swpaul} 186850974Swpaul 186950974Swpaul/* 187050974Swpaul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 187150974Swpaul * pointers to the fragment pointers. 187250974Swpaul */ 1873102334Salfredstatic int 1874102334Salfredsis_encap(sc, m_head, txidx) 187550974Swpaul struct sis_softc *sc; 187650974Swpaul struct mbuf *m_head; 187750974Swpaul u_int32_t *txidx; 187850974Swpaul{ 187950974Swpaul struct sis_desc *f = NULL; 188050974Swpaul struct mbuf *m; 188150974Swpaul int frag, cur, cnt = 0; 188250974Swpaul 188350974Swpaul /* 188450974Swpaul * Start packing the mbufs in this chain into 188550974Swpaul * the fragment pointers. Stop when we run out 188650974Swpaul * of fragments or hit the end of the mbuf chain. 188750974Swpaul */ 188850974Swpaul m = m_head; 188950974Swpaul cur = frag = *txidx; 189050974Swpaul 189150974Swpaul for (m = m_head; m != NULL; m = m->m_next) { 189250974Swpaul if (m->m_len != 0) { 189351042Swpaul if ((SIS_TX_LIST_CNT - 189450974Swpaul (sc->sis_cdata.sis_tx_cnt + cnt)) < 2) 189550974Swpaul return(ENOBUFS); 189681713Swpaul f = &sc->sis_ldata.sis_tx_list[frag]; 189750974Swpaul f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; 189881713Swpaul bus_dmamap_create(sc->sis_tag, 0, &f->sis_map); 189981713Swpaul bus_dmamap_load(sc->sis_tag, f->sis_map, 190081713Swpaul mtod(m, void *), m->m_len, 190181713Swpaul sis_dma_map_desc_ptr, f, 0); 190281713Swpaul bus_dmamap_sync(sc->sis_tag, 190381713Swpaul f->sis_map, BUS_DMASYNC_PREREAD); 190450974Swpaul if (cnt != 0) 190550974Swpaul f->sis_ctl |= SIS_CMDSTS_OWN; 190650974Swpaul cur = frag; 190750974Swpaul SIS_INC(frag, SIS_TX_LIST_CNT); 190850974Swpaul cnt++; 190950974Swpaul } 191050974Swpaul } 191150974Swpaul 191250974Swpaul if (m != NULL) 191350974Swpaul return(ENOBUFS); 191450974Swpaul 191581713Swpaul sc->sis_ldata.sis_tx_list[cur].sis_mbuf = m_head; 191681713Swpaul sc->sis_ldata.sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 191781713Swpaul sc->sis_ldata.sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 191850974Swpaul sc->sis_cdata.sis_tx_cnt += cnt; 191950974Swpaul *txidx = frag; 192050974Swpaul 192150974Swpaul return(0); 192250974Swpaul} 192350974Swpaul 192450974Swpaul/* 192550974Swpaul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 192650974Swpaul * to the mbuf data regions directly in the transmit lists. We also save a 192750974Swpaul * copy of the pointers since the transmit list fragment pointers are 192850974Swpaul * physical addresses. 192950974Swpaul */ 193050974Swpaul 1931102334Salfredstatic void 1932102334Salfredsis_start(ifp) 193350974Swpaul struct ifnet *ifp; 193450974Swpaul{ 193550974Swpaul struct sis_softc *sc; 193650974Swpaul struct mbuf *m_head = NULL; 193750974Swpaul u_int32_t idx; 193850974Swpaul 193950974Swpaul sc = ifp->if_softc; 194067087Swpaul SIS_LOCK(sc); 194150974Swpaul 194267087Swpaul if (!sc->sis_link) { 194367087Swpaul SIS_UNLOCK(sc); 194464963Swpaul return; 194567087Swpaul } 194664963Swpaul 194750974Swpaul idx = sc->sis_cdata.sis_tx_prod; 194850974Swpaul 194967087Swpaul if (ifp->if_flags & IFF_OACTIVE) { 195067087Swpaul SIS_UNLOCK(sc); 195150974Swpaul return; 195267087Swpaul } 195350974Swpaul 195481713Swpaul while(sc->sis_ldata.sis_tx_list[idx].sis_mbuf == NULL) { 195550974Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 195650974Swpaul if (m_head == NULL) 195750974Swpaul break; 195850974Swpaul 195950974Swpaul if (sis_encap(sc, m_head, &idx)) { 196050974Swpaul IF_PREPEND(&ifp->if_snd, m_head); 196150974Swpaul ifp->if_flags |= IFF_OACTIVE; 196250974Swpaul break; 196350974Swpaul } 196450974Swpaul 196550974Swpaul /* 196650974Swpaul * If there's a BPF listener, bounce a copy of this frame 196750974Swpaul * to him. 196850974Swpaul */ 1969106936Ssam BPF_MTAP(ifp, m_head); 197051583Swpaul 197150974Swpaul } 197250974Swpaul 197350974Swpaul /* Transmit */ 197450974Swpaul sc->sis_cdata.sis_tx_prod = idx; 197550974Swpaul SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 197650974Swpaul 197750974Swpaul /* 197850974Swpaul * Set a timeout in case the chip goes out to lunch. 197950974Swpaul */ 198050974Swpaul ifp->if_timer = 5; 198150974Swpaul 198267087Swpaul SIS_UNLOCK(sc); 198367087Swpaul 198450974Swpaul return; 198550974Swpaul} 198650974Swpaul 1987102334Salfredstatic void 1988102334Salfredsis_init(xsc) 198950974Swpaul void *xsc; 199050974Swpaul{ 199150974Swpaul struct sis_softc *sc = xsc; 199250974Swpaul struct ifnet *ifp = &sc->arpcom.ac_if; 199350974Swpaul struct mii_data *mii; 199450974Swpaul 199567087Swpaul SIS_LOCK(sc); 199650974Swpaul 199750974Swpaul /* 199850974Swpaul * Cancel pending I/O and free all RX/TX buffers. 199950974Swpaul */ 200050974Swpaul sis_stop(sc); 200150974Swpaul 200250974Swpaul mii = device_get_softc(sc->sis_miibus); 200350974Swpaul 200450974Swpaul /* Set MAC address */ 200562672Swpaul if (sc->sis_type == SIS_TYPE_83815) { 200662672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 200762672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 200862672Swpaul ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 200962672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 201062672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 201162672Swpaul ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 201262672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 201362672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 201462672Swpaul ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 201562672Swpaul } else { 201662672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 201762672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 201862672Swpaul ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 201962672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 202062672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 202162672Swpaul ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 202262672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 202362672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 202462672Swpaul ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 202562672Swpaul } 202650974Swpaul 202750974Swpaul /* Init circular RX list. */ 202850974Swpaul if (sis_list_rx_init(sc) == ENOBUFS) { 202950974Swpaul printf("sis%d: initialization failed: no " 203050974Swpaul "memory for rx buffers\n", sc->sis_unit); 203150974Swpaul sis_stop(sc); 203267087Swpaul SIS_UNLOCK(sc); 203350974Swpaul return; 203450974Swpaul } 203550974Swpaul 203650974Swpaul /* 203750974Swpaul * Init tx descriptors. 203850974Swpaul */ 203950974Swpaul sis_list_tx_init(sc); 204050974Swpaul 204162672Swpaul /* 204262672Swpaul * For the NatSemi chip, we have to explicitly enable the 204362672Swpaul * reception of ARP frames, as well as turn on the 'perfect 204462672Swpaul * match' filter where we store the station address, otherwise 204562672Swpaul * we won't receive unicasts meant for this host. 204662672Swpaul */ 204762672Swpaul if (sc->sis_type == SIS_TYPE_83815) { 204862672Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 204962672Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 205062672Swpaul } 205162672Swpaul 205250974Swpaul /* If we want promiscuous mode, set the allframes bit. */ 205350974Swpaul if (ifp->if_flags & IFF_PROMISC) { 205450974Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 205550974Swpaul } else { 205650974Swpaul SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 205750974Swpaul } 205850974Swpaul 205950974Swpaul /* 206050974Swpaul * Set the capture broadcast bit to capture broadcast frames. 206150974Swpaul */ 206250974Swpaul if (ifp->if_flags & IFF_BROADCAST) { 206350974Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 206450974Swpaul } else { 206550974Swpaul SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 206650974Swpaul } 206750974Swpaul 206850974Swpaul /* 206950974Swpaul * Load the multicast filter. 207050974Swpaul */ 207162672Swpaul if (sc->sis_type == SIS_TYPE_83815) 207262672Swpaul sis_setmulti_ns(sc); 207362672Swpaul else 207462672Swpaul sis_setmulti_sis(sc); 207550974Swpaul 207650974Swpaul /* Turn the receive filter on */ 207750974Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 207850974Swpaul 207950974Swpaul /* 208050974Swpaul * Load the address of the RX and TX lists. 208150974Swpaul */ 208281713Swpaul CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_cdata.sis_rx_paddr); 208381713Swpaul CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_cdata.sis_tx_paddr); 208450974Swpaul 2085109059Smbr /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of 2086109059Smbr * the PCI bus. When this bit is set, the Max DMA Burst Size 2087109059Smbr * for TX/RX DMA should be no larger than 16 double words. 2088109059Smbr */ 2089109059Smbr if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) { 2090109059Smbr CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); 2091109059Smbr } else { 2092109059Smbr CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); 2093109059Smbr } 209464963Swpaul 2095109059Smbr 209687390Sjhay /* Accept Long Packets for VLAN support */ 209787390Sjhay SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 209887390Sjhay 209950974Swpaul /* Set TX configuration */ 210064963Swpaul if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 210164963Swpaul CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 210264963Swpaul } else { 210364963Swpaul CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 210464963Swpaul } 210550974Swpaul 210664963Swpaul /* Set full/half duplex mode. */ 210764963Swpaul if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 210864963Swpaul SIS_SETBIT(sc, SIS_TX_CFG, 210964963Swpaul (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 211064963Swpaul SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 211164963Swpaul } else { 211264963Swpaul SIS_CLRBIT(sc, SIS_TX_CFG, 211364963Swpaul (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 211464963Swpaul SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 211564963Swpaul } 211664963Swpaul 211750974Swpaul /* 211850974Swpaul * Enable interrupts. 211950974Swpaul */ 212050974Swpaul CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 212187902Sluigi#ifdef DEVICE_POLLING 212287902Sluigi /* 212387902Sluigi * ... only enable interrupts if we are not polling, make sure 212487902Sluigi * they are off otherwise. 212587902Sluigi */ 2126102052Ssobomax if (ifp->if_flags & IFF_POLLING) 212787902Sluigi CSR_WRITE_4(sc, SIS_IER, 0); 212887902Sluigi else 212987902Sluigi#endif /* DEVICE_POLLING */ 213050974Swpaul CSR_WRITE_4(sc, SIS_IER, 1); 213150974Swpaul 213250974Swpaul /* Enable receiver and transmitter. */ 213350974Swpaul SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 213450974Swpaul SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 213550974Swpaul 213664963Swpaul#ifdef notdef 213750974Swpaul mii_mediachg(mii); 213864963Swpaul#endif 213950974Swpaul 214064963Swpaul /* 214164963Swpaul * Page 75 of the DP83815 manual recommends the 214264963Swpaul * following register settings "for optimum 214364963Swpaul * performance." Note however that at least three 214464963Swpaul * of the registers are listed as "reserved" in 214564963Swpaul * the register map, so who knows what they do. 214664963Swpaul */ 214764963Swpaul if (sc->sis_type == SIS_TYPE_83815) { 214864963Swpaul CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 214964963Swpaul CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 215064963Swpaul CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 215164963Swpaul CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 215264963Swpaul CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 215364963Swpaul } 215464963Swpaul 215550974Swpaul ifp->if_flags |= IFF_RUNNING; 215650974Swpaul ifp->if_flags &= ~IFF_OACTIVE; 215750974Swpaul 215850974Swpaul sc->sis_stat_ch = timeout(sis_tick, sc, hz); 215950974Swpaul 216067087Swpaul SIS_UNLOCK(sc); 216167087Swpaul 216250974Swpaul return; 216350974Swpaul} 216450974Swpaul 216550974Swpaul/* 216650974Swpaul * Set media options. 216750974Swpaul */ 2168102334Salfredstatic int 2169102334Salfredsis_ifmedia_upd(ifp) 217050974Swpaul struct ifnet *ifp; 217150974Swpaul{ 217250974Swpaul struct sis_softc *sc; 217364963Swpaul struct mii_data *mii; 217450974Swpaul 217550974Swpaul sc = ifp->if_softc; 217650974Swpaul 217764963Swpaul mii = device_get_softc(sc->sis_miibus); 217864963Swpaul sc->sis_link = 0; 217964963Swpaul if (mii->mii_instance) { 218064963Swpaul struct mii_softc *miisc; 218172012Sphk LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 218264963Swpaul mii_phy_reset(miisc); 218364963Swpaul } 218464963Swpaul mii_mediachg(mii); 218550974Swpaul 218650974Swpaul return(0); 218750974Swpaul} 218850974Swpaul 218950974Swpaul/* 219050974Swpaul * Report current media status. 219150974Swpaul */ 2192102334Salfredstatic void 2193102334Salfredsis_ifmedia_sts(ifp, ifmr) 219450974Swpaul struct ifnet *ifp; 219550974Swpaul struct ifmediareq *ifmr; 219650974Swpaul{ 219750974Swpaul struct sis_softc *sc; 219850974Swpaul struct mii_data *mii; 219950974Swpaul 220050974Swpaul sc = ifp->if_softc; 220150974Swpaul 220250974Swpaul mii = device_get_softc(sc->sis_miibus); 220350974Swpaul mii_pollstat(mii); 220450974Swpaul ifmr->ifm_active = mii->mii_media_active; 220550974Swpaul ifmr->ifm_status = mii->mii_media_status; 220650974Swpaul 220750974Swpaul return; 220850974Swpaul} 220950974Swpaul 2210102334Salfredstatic int 2211102334Salfredsis_ioctl(ifp, command, data) 221250974Swpaul struct ifnet *ifp; 221350974Swpaul u_long command; 221450974Swpaul caddr_t data; 221550974Swpaul{ 221650974Swpaul struct sis_softc *sc = ifp->if_softc; 221750974Swpaul struct ifreq *ifr = (struct ifreq *) data; 221850974Swpaul struct mii_data *mii; 221967087Swpaul int error = 0; 222050974Swpaul 222150974Swpaul switch(command) { 222250974Swpaul case SIOCSIFFLAGS: 222350974Swpaul if (ifp->if_flags & IFF_UP) { 222450974Swpaul sis_init(sc); 222550974Swpaul } else { 222650974Swpaul if (ifp->if_flags & IFF_RUNNING) 222750974Swpaul sis_stop(sc); 222850974Swpaul } 222950974Swpaul error = 0; 223050974Swpaul break; 223150974Swpaul case SIOCADDMULTI: 223250974Swpaul case SIOCDELMULTI: 223381713Swpaul SIS_LOCK(sc); 223462672Swpaul if (sc->sis_type == SIS_TYPE_83815) 223562672Swpaul sis_setmulti_ns(sc); 223662672Swpaul else 223762672Swpaul sis_setmulti_sis(sc); 223881713Swpaul SIS_UNLOCK(sc); 223950974Swpaul error = 0; 224050974Swpaul break; 224150974Swpaul case SIOCGIFMEDIA: 224250974Swpaul case SIOCSIFMEDIA: 224350974Swpaul mii = device_get_softc(sc->sis_miibus); 224481713Swpaul SIS_LOCK(sc); 224550974Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 224681713Swpaul SIS_UNLOCK(sc); 224750974Swpaul break; 224850974Swpaul default: 2249106936Ssam error = ether_ioctl(ifp, command, data); 225050974Swpaul break; 225150974Swpaul } 225250974Swpaul 225350974Swpaul return(error); 225450974Swpaul} 225550974Swpaul 2256102334Salfredstatic void 2257102334Salfredsis_watchdog(ifp) 225850974Swpaul struct ifnet *ifp; 225950974Swpaul{ 226050974Swpaul struct sis_softc *sc; 226150974Swpaul 226250974Swpaul sc = ifp->if_softc; 226350974Swpaul 226467087Swpaul SIS_LOCK(sc); 226567087Swpaul 226650974Swpaul ifp->if_oerrors++; 226750974Swpaul printf("sis%d: watchdog timeout\n", sc->sis_unit); 226850974Swpaul 226950974Swpaul sis_stop(sc); 227050974Swpaul sis_reset(sc); 227150974Swpaul sis_init(sc); 227250974Swpaul 227350974Swpaul if (ifp->if_snd.ifq_head != NULL) 227450974Swpaul sis_start(ifp); 227550974Swpaul 227667087Swpaul SIS_UNLOCK(sc); 227767087Swpaul 227850974Swpaul return; 227950974Swpaul} 228050974Swpaul 228150974Swpaul/* 228250974Swpaul * Stop the adapter and free any mbufs allocated to the 228350974Swpaul * RX and TX lists. 228450974Swpaul */ 2285102334Salfredstatic void 2286102334Salfredsis_stop(sc) 228750974Swpaul struct sis_softc *sc; 228850974Swpaul{ 228950974Swpaul register int i; 229050974Swpaul struct ifnet *ifp; 229150974Swpaul 229267087Swpaul SIS_LOCK(sc); 229350974Swpaul ifp = &sc->arpcom.ac_if; 229450974Swpaul ifp->if_timer = 0; 229550974Swpaul 229650974Swpaul untimeout(sis_tick, sc, sc->sis_stat_ch); 229787472Speter 229887472Speter ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 229987902Sluigi#ifdef DEVICE_POLLING 230087902Sluigi ether_poll_deregister(ifp); 230187902Sluigi#endif 230250974Swpaul CSR_WRITE_4(sc, SIS_IER, 0); 230350974Swpaul CSR_WRITE_4(sc, SIS_IMR, 0); 230450974Swpaul SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 230550974Swpaul DELAY(1000); 230650974Swpaul CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 230750974Swpaul CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 230850974Swpaul 230964963Swpaul sc->sis_link = 0; 231064963Swpaul 231150974Swpaul /* 231250974Swpaul * Free data in the RX lists. 231350974Swpaul */ 231450974Swpaul for (i = 0; i < SIS_RX_LIST_CNT; i++) { 231581713Swpaul if (sc->sis_ldata.sis_rx_list[i].sis_mbuf != NULL) { 231681713Swpaul bus_dmamap_unload(sc->sis_tag, 231781713Swpaul sc->sis_ldata.sis_rx_list[i].sis_map); 231881713Swpaul bus_dmamap_destroy(sc->sis_tag, 231981713Swpaul sc->sis_ldata.sis_rx_list[i].sis_map); 232081713Swpaul m_freem(sc->sis_ldata.sis_rx_list[i].sis_mbuf); 232181713Swpaul sc->sis_ldata.sis_rx_list[i].sis_mbuf = NULL; 232250974Swpaul } 232350974Swpaul } 232481713Swpaul bzero(sc->sis_ldata.sis_rx_list, 232581713Swpaul sizeof(sc->sis_ldata.sis_rx_list)); 232650974Swpaul 232750974Swpaul /* 232850974Swpaul * Free the TX list buffers. 232950974Swpaul */ 233050974Swpaul for (i = 0; i < SIS_TX_LIST_CNT; i++) { 233181713Swpaul if (sc->sis_ldata.sis_tx_list[i].sis_mbuf != NULL) { 233281713Swpaul bus_dmamap_unload(sc->sis_tag, 233381713Swpaul sc->sis_ldata.sis_tx_list[i].sis_map); 233481713Swpaul bus_dmamap_destroy(sc->sis_tag, 233581713Swpaul sc->sis_ldata.sis_tx_list[i].sis_map); 233681713Swpaul m_freem(sc->sis_ldata.sis_tx_list[i].sis_mbuf); 233781713Swpaul sc->sis_ldata.sis_tx_list[i].sis_mbuf = NULL; 233850974Swpaul } 233950974Swpaul } 234050974Swpaul 234181713Swpaul bzero(sc->sis_ldata.sis_tx_list, 234281713Swpaul sizeof(sc->sis_ldata.sis_tx_list)); 234350974Swpaul 234467087Swpaul SIS_UNLOCK(sc); 234567087Swpaul 234650974Swpaul return; 234750974Swpaul} 234850974Swpaul 234950974Swpaul/* 235050974Swpaul * Stop all chip I/O so that the kernel's probe routines don't 235150974Swpaul * get confused by errant DMAs when rebooting. 235250974Swpaul */ 2353102334Salfredstatic void 2354102334Salfredsis_shutdown(dev) 235550974Swpaul device_t dev; 235650974Swpaul{ 235750974Swpaul struct sis_softc *sc; 235850974Swpaul 235950974Swpaul sc = device_get_softc(dev); 236067087Swpaul SIS_LOCK(sc); 236150974Swpaul sis_reset(sc); 236250974Swpaul sis_stop(sc); 236367087Swpaul SIS_UNLOCK(sc); 236450974Swpaul 236550974Swpaul return; 236650974Swpaul} 2367