if_sis.c revision 109623
150974Swpaul/* 250974Swpaul * Copyright (c) 1997, 1998, 1999 350974Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 450974Swpaul * 550974Swpaul * Redistribution and use in source and binary forms, with or without 650974Swpaul * modification, are permitted provided that the following conditions 750974Swpaul * are met: 850974Swpaul * 1. Redistributions of source code must retain the above copyright 950974Swpaul * notice, this list of conditions and the following disclaimer. 1050974Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1150974Swpaul * notice, this list of conditions and the following disclaimer in the 1250974Swpaul * documentation and/or other materials provided with the distribution. 1350974Swpaul * 3. All advertising materials mentioning features or use of this software 1450974Swpaul * must display the following acknowledgement: 1550974Swpaul * This product includes software developed by Bill Paul. 1650974Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1750974Swpaul * may be used to endorse or promote products derived from this software 1850974Swpaul * without specific prior written permission. 1950974Swpaul * 2050974Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2150974Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2250974Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2350974Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2450974Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2550974Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2650974Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2750974Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2850974Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2950974Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3050974Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3150974Swpaul * 3250974Swpaul * $FreeBSD: head/sys/pci/if_sis.c 109623 2003-01-21 08:56:16Z alfred $ 3350974Swpaul */ 3450974Swpaul 3550974Swpaul/* 3650974Swpaul * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 3750974Swpaul * available from http://www.sis.com.tw. 3850974Swpaul * 3964963Swpaul * This driver also supports the NatSemi DP83815. Datasheets are 4064963Swpaul * available from http://www.national.com. 4164963Swpaul * 4250974Swpaul * Written by Bill Paul <wpaul@ee.columbia.edu> 4350974Swpaul * Electrical Engineering Department 4450974Swpaul * Columbia University, New York City 4550974Swpaul */ 4650974Swpaul 4750974Swpaul/* 4850974Swpaul * The SiS 900 is a fairly simple chip. It uses bus master DMA with 4950974Swpaul * simple TX and RX descriptors of 3 longwords in size. The receiver 5050974Swpaul * has a single perfect filter entry for the station address and a 5150974Swpaul * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 5250974Swpaul * transceiver while the 7016 requires an external transceiver chip. 5350974Swpaul * Both chips offer the standard bit-bang MII interface as well as 5450974Swpaul * an enchanced PHY interface which simplifies accessing MII registers. 5550974Swpaul * 5650974Swpaul * The only downside to this chipset is that RX descriptors must be 5750974Swpaul * longword aligned. 5850974Swpaul */ 5950974Swpaul 6050974Swpaul#include <sys/param.h> 6150974Swpaul#include <sys/systm.h> 6250974Swpaul#include <sys/sockio.h> 6350974Swpaul#include <sys/mbuf.h> 6450974Swpaul#include <sys/malloc.h> 6550974Swpaul#include <sys/kernel.h> 6650974Swpaul#include <sys/socket.h> 6787059Sluigi#include <sys/sysctl.h> 6850974Swpaul 6950974Swpaul#include <net/if.h> 7050974Swpaul#include <net/if_arp.h> 7150974Swpaul#include <net/ethernet.h> 7250974Swpaul#include <net/if_dl.h> 7350974Swpaul#include <net/if_media.h> 7487390Sjhay#include <net/if_types.h> 7587390Sjhay#include <net/if_vlan_var.h> 7650974Swpaul 7750974Swpaul#include <net/bpf.h> 7850974Swpaul 7950974Swpaul#include <machine/bus_pio.h> 8050974Swpaul#include <machine/bus_memio.h> 8150974Swpaul#include <machine/bus.h> 8250974Swpaul#include <machine/resource.h> 8350974Swpaul#include <sys/bus.h> 8450974Swpaul#include <sys/rman.h> 8550974Swpaul 8650974Swpaul#include <dev/mii/mii.h> 8750974Swpaul#include <dev/mii/miivar.h> 8850974Swpaul 8950974Swpaul#include <pci/pcireg.h> 9050974Swpaul#include <pci/pcivar.h> 9150974Swpaul 9250974Swpaul#define SIS_USEIOSPACE 9350974Swpaul 9450974Swpaul#include <pci/if_sisreg.h> 9550974Swpaul 9659758SpeterMODULE_DEPEND(sis, miibus, 1, 1, 1); 9759758Speter 9851089Speter/* "controller miibus0" required. See GENERIC if you get errors here. */ 9950974Swpaul#include "miibus_if.h" 10050974Swpaul 10150974Swpaul#ifndef lint 10250974Swpaulstatic const char rcsid[] = 10350974Swpaul "$FreeBSD: head/sys/pci/if_sis.c 109623 2003-01-21 08:56:16Z alfred $"; 10450974Swpaul#endif 10550974Swpaul 10650974Swpaul/* 10750974Swpaul * Various supported device vendors/types and their names. 10850974Swpaul */ 10950974Swpaulstatic struct sis_type sis_devs[] = { 11050974Swpaul { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 11150974Swpaul { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 11262672Swpaul { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP83815 10/100BaseTX" }, 11350974Swpaul { 0, 0, NULL } 11450974Swpaul}; 11550974Swpaul 11692739Salfredstatic int sis_probe (device_t); 11792739Salfredstatic int sis_attach (device_t); 11892739Salfredstatic int sis_detach (device_t); 11950974Swpaul 12092739Salfredstatic int sis_newbuf (struct sis_softc *, 12192739Salfred struct sis_desc *, struct mbuf *); 12292739Salfredstatic int sis_encap (struct sis_softc *, 12392739Salfred struct mbuf *, u_int32_t *); 12492739Salfredstatic void sis_rxeof (struct sis_softc *); 12592739Salfredstatic void sis_rxeoc (struct sis_softc *); 12692739Salfredstatic void sis_txeof (struct sis_softc *); 12792739Salfredstatic void sis_intr (void *); 12892739Salfredstatic void sis_tick (void *); 12992739Salfredstatic void sis_start (struct ifnet *); 13092739Salfredstatic int sis_ioctl (struct ifnet *, u_long, caddr_t); 13192739Salfredstatic void sis_init (void *); 13292739Salfredstatic void sis_stop (struct sis_softc *); 13392739Salfredstatic void sis_watchdog (struct ifnet *); 13492739Salfredstatic void sis_shutdown (device_t); 13592739Salfredstatic int sis_ifmedia_upd (struct ifnet *); 13692739Salfredstatic void sis_ifmedia_sts (struct ifnet *, struct ifmediareq *); 13750974Swpaul 13892739Salfredstatic u_int16_t sis_reverse (u_int16_t); 13992739Salfredstatic void sis_delay (struct sis_softc *); 14092739Salfredstatic void sis_eeprom_idle (struct sis_softc *); 14192739Salfredstatic void sis_eeprom_putbyte (struct sis_softc *, int); 14292739Salfredstatic void sis_eeprom_getword (struct sis_softc *, int, u_int16_t *); 14392739Salfredstatic void sis_read_eeprom (struct sis_softc *, caddr_t, int, int, int); 14472197Swpaul#ifdef __i386__ 14592739Salfredstatic void sis_read_cmos (struct sis_softc *, device_t, caddr_t, 14692739Salfred int, int); 14792739Salfredstatic void sis_read_mac (struct sis_softc *, device_t, caddr_t); 14892739Salfredstatic device_t sis_find_bridge (device_t); 14972197Swpaul#endif 15072197Swpaul 151109060Smbrstatic void sis_mii_sync (struct sis_softc *); 152109060Smbrstatic void sis_mii_send (struct sis_softc *, u_int32_t, int); 153109060Smbrstatic int sis_mii_readreg (struct sis_softc *, struct sis_mii_frame *); 154109060Smbrstatic int sis_mii_writereg (struct sis_softc *, struct sis_mii_frame *); 15592739Salfredstatic int sis_miibus_readreg (device_t, int, int); 15692739Salfredstatic int sis_miibus_writereg (device_t, int, int, int); 15792739Salfredstatic void sis_miibus_statchg (device_t); 15850974Swpaul 15992739Salfredstatic void sis_setmulti_sis (struct sis_softc *); 16092739Salfredstatic void sis_setmulti_ns (struct sis_softc *); 16192739Salfredstatic u_int32_t sis_crc (struct sis_softc *, caddr_t); 16292739Salfredstatic void sis_reset (struct sis_softc *); 16392739Salfredstatic int sis_list_rx_init (struct sis_softc *); 16492739Salfredstatic int sis_list_tx_init (struct sis_softc *); 16550974Swpaul 16692739Salfredstatic void sis_dma_map_desc_ptr (void *, bus_dma_segment_t *, int, int); 16792739Salfredstatic void sis_dma_map_desc_next (void *, bus_dma_segment_t *, int, int); 16892739Salfredstatic void sis_dma_map_ring (void *, bus_dma_segment_t *, int, int); 16950974Swpaul#ifdef SIS_USEIOSPACE 17050974Swpaul#define SIS_RES SYS_RES_IOPORT 17150974Swpaul#define SIS_RID SIS_PCI_LOIO 17250974Swpaul#else 17351030Swpaul#define SIS_RES SYS_RES_MEMORY 17451030Swpaul#define SIS_RID SIS_PCI_LOMEM 17550974Swpaul#endif 17650974Swpaul 17750974Swpaulstatic device_method_t sis_methods[] = { 17850974Swpaul /* Device interface */ 17950974Swpaul DEVMETHOD(device_probe, sis_probe), 18050974Swpaul DEVMETHOD(device_attach, sis_attach), 18150974Swpaul DEVMETHOD(device_detach, sis_detach), 18250974Swpaul DEVMETHOD(device_shutdown, sis_shutdown), 18350974Swpaul 18450974Swpaul /* bus interface */ 18550974Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 18650974Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 18750974Swpaul 18850974Swpaul /* MII interface */ 18950974Swpaul DEVMETHOD(miibus_readreg, sis_miibus_readreg), 19050974Swpaul DEVMETHOD(miibus_writereg, sis_miibus_writereg), 19150974Swpaul DEVMETHOD(miibus_statchg, sis_miibus_statchg), 19250974Swpaul 19350974Swpaul { 0, 0 } 19450974Swpaul}; 19550974Swpaul 19650974Swpaulstatic driver_t sis_driver = { 19751455Swpaul "sis", 19850974Swpaul sis_methods, 19950974Swpaul sizeof(struct sis_softc) 20050974Swpaul}; 20150974Swpaul 20250974Swpaulstatic devclass_t sis_devclass; 20350974Swpaul 20451533SwpaulDRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, 0, 0); 20551473SwpaulDRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 20650974Swpaul 20750974Swpaul#define SIS_SETBIT(sc, reg, x) \ 20850974Swpaul CSR_WRITE_4(sc, reg, \ 20950974Swpaul CSR_READ_4(sc, reg) | (x)) 21050974Swpaul 21150974Swpaul#define SIS_CLRBIT(sc, reg, x) \ 21250974Swpaul CSR_WRITE_4(sc, reg, \ 21350974Swpaul CSR_READ_4(sc, reg) & ~(x)) 21450974Swpaul 21550974Swpaul#define SIO_SET(x) \ 21650974Swpaul CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 21750974Swpaul 21850974Swpaul#define SIO_CLR(x) \ 21950974Swpaul CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 22050974Swpaul 22181713Swpaulstatic void 22281713Swpaulsis_dma_map_desc_next(arg, segs, nseg, error) 22381713Swpaul void *arg; 22481713Swpaul bus_dma_segment_t *segs; 22581713Swpaul int nseg, error; 22681713Swpaul{ 22781713Swpaul struct sis_desc *r; 22881713Swpaul 22981713Swpaul r = arg; 23081713Swpaul r->sis_next = segs->ds_addr; 23181713Swpaul 23281713Swpaul return; 23381713Swpaul} 23481713Swpaul 23581713Swpaulstatic void 23681713Swpaulsis_dma_map_desc_ptr(arg, segs, nseg, error) 23781713Swpaul void *arg; 23881713Swpaul bus_dma_segment_t *segs; 23981713Swpaul int nseg, error; 24081713Swpaul{ 24181713Swpaul struct sis_desc *r; 24281713Swpaul 24381713Swpaul r = arg; 24481713Swpaul r->sis_ptr = segs->ds_addr; 24581713Swpaul 24681713Swpaul return; 24781713Swpaul} 24881713Swpaul 24981713Swpaulstatic void 25081713Swpaulsis_dma_map_ring(arg, segs, nseg, error) 25181713Swpaul void *arg; 25281713Swpaul bus_dma_segment_t *segs; 25381713Swpaul int nseg, error; 25481713Swpaul{ 25581713Swpaul u_int32_t *p; 25681713Swpaul 25781713Swpaul p = arg; 25881713Swpaul *p = segs->ds_addr; 25981713Swpaul 26081713Swpaul return; 26181713Swpaul} 26281713Swpaul 26362672Swpaul/* 26462672Swpaul * Routine to reverse the bits in a word. Stolen almost 26562672Swpaul * verbatim from /usr/games/fortune. 26662672Swpaul */ 267102334Salfredstatic u_int16_t 268102334Salfredsis_reverse(n) 26962672Swpaul u_int16_t n; 27062672Swpaul{ 27162672Swpaul n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 27262672Swpaul n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 27362672Swpaul n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 27462672Swpaul n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 27562672Swpaul 27662672Swpaul return(n); 27762672Swpaul} 27862672Swpaul 279102334Salfredstatic void 280102334Salfredsis_delay(sc) 28150974Swpaul struct sis_softc *sc; 28250974Swpaul{ 28350974Swpaul int idx; 28450974Swpaul 28550974Swpaul for (idx = (300 / 33) + 1; idx > 0; idx--) 28650974Swpaul CSR_READ_4(sc, SIS_CSR); 28750974Swpaul 28850974Swpaul return; 28950974Swpaul} 29050974Swpaul 291102334Salfredstatic void 292102334Salfredsis_eeprom_idle(sc) 29350974Swpaul struct sis_softc *sc; 29450974Swpaul{ 29550974Swpaul register int i; 29650974Swpaul 29750974Swpaul SIO_SET(SIS_EECTL_CSEL); 29850974Swpaul sis_delay(sc); 29950974Swpaul SIO_SET(SIS_EECTL_CLK); 30050974Swpaul sis_delay(sc); 30150974Swpaul 30250974Swpaul for (i = 0; i < 25; i++) { 30350974Swpaul SIO_CLR(SIS_EECTL_CLK); 30450974Swpaul sis_delay(sc); 30550974Swpaul SIO_SET(SIS_EECTL_CLK); 30650974Swpaul sis_delay(sc); 30750974Swpaul } 30850974Swpaul 30950974Swpaul SIO_CLR(SIS_EECTL_CLK); 31050974Swpaul sis_delay(sc); 31150974Swpaul SIO_CLR(SIS_EECTL_CSEL); 31250974Swpaul sis_delay(sc); 31350974Swpaul CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 31450974Swpaul 31550974Swpaul return; 31650974Swpaul} 31750974Swpaul 31850974Swpaul/* 31950974Swpaul * Send a read command and address to the EEPROM, check for ACK. 32050974Swpaul */ 321102334Salfredstatic void 322102334Salfredsis_eeprom_putbyte(sc, addr) 32350974Swpaul struct sis_softc *sc; 32450974Swpaul int addr; 32550974Swpaul{ 32650974Swpaul register int d, i; 32750974Swpaul 32850974Swpaul d = addr | SIS_EECMD_READ; 32950974Swpaul 33050974Swpaul /* 33150974Swpaul * Feed in each bit and stobe the clock. 33250974Swpaul */ 33350974Swpaul for (i = 0x400; i; i >>= 1) { 33450974Swpaul if (d & i) { 33550974Swpaul SIO_SET(SIS_EECTL_DIN); 33650974Swpaul } else { 33750974Swpaul SIO_CLR(SIS_EECTL_DIN); 33850974Swpaul } 33950974Swpaul sis_delay(sc); 34050974Swpaul SIO_SET(SIS_EECTL_CLK); 34150974Swpaul sis_delay(sc); 34250974Swpaul SIO_CLR(SIS_EECTL_CLK); 34350974Swpaul sis_delay(sc); 34450974Swpaul } 34550974Swpaul 34650974Swpaul return; 34750974Swpaul} 34850974Swpaul 34950974Swpaul/* 35050974Swpaul * Read a word of data stored in the EEPROM at address 'addr.' 35150974Swpaul */ 352102334Salfredstatic void 353102334Salfredsis_eeprom_getword(sc, addr, dest) 35450974Swpaul struct sis_softc *sc; 35550974Swpaul int addr; 35650974Swpaul u_int16_t *dest; 35750974Swpaul{ 35850974Swpaul register int i; 35950974Swpaul u_int16_t word = 0; 36050974Swpaul 36150974Swpaul /* Force EEPROM to idle state. */ 36250974Swpaul sis_eeprom_idle(sc); 36350974Swpaul 36450974Swpaul /* Enter EEPROM access mode. */ 36550974Swpaul sis_delay(sc); 36662672Swpaul SIO_CLR(SIS_EECTL_CLK); 36762672Swpaul sis_delay(sc); 36850974Swpaul SIO_SET(SIS_EECTL_CSEL); 36950974Swpaul sis_delay(sc); 37050974Swpaul 37150974Swpaul /* 37250974Swpaul * Send address of word we want to read. 37350974Swpaul */ 37450974Swpaul sis_eeprom_putbyte(sc, addr); 37550974Swpaul 37650974Swpaul /* 37750974Swpaul * Start reading bits from EEPROM. 37850974Swpaul */ 37950974Swpaul for (i = 0x8000; i; i >>= 1) { 38050974Swpaul SIO_SET(SIS_EECTL_CLK); 38150974Swpaul sis_delay(sc); 38250974Swpaul if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 38350974Swpaul word |= i; 38450974Swpaul sis_delay(sc); 38550974Swpaul SIO_CLR(SIS_EECTL_CLK); 38650974Swpaul sis_delay(sc); 38750974Swpaul } 38850974Swpaul 38950974Swpaul /* Turn off EEPROM access mode. */ 39050974Swpaul sis_eeprom_idle(sc); 39150974Swpaul 39250974Swpaul *dest = word; 39350974Swpaul 39450974Swpaul return; 39550974Swpaul} 39650974Swpaul 39750974Swpaul/* 39850974Swpaul * Read a sequence of words from the EEPROM. 39950974Swpaul */ 400102334Salfredstatic void 401102334Salfredsis_read_eeprom(sc, dest, off, cnt, swap) 40250974Swpaul struct sis_softc *sc; 40350974Swpaul caddr_t dest; 40450974Swpaul int off; 40550974Swpaul int cnt; 40650974Swpaul int swap; 40750974Swpaul{ 40850974Swpaul int i; 40950974Swpaul u_int16_t word = 0, *ptr; 41050974Swpaul 41150974Swpaul for (i = 0; i < cnt; i++) { 41250974Swpaul sis_eeprom_getword(sc, off + i, &word); 41350974Swpaul ptr = (u_int16_t *)(dest + (i * 2)); 41450974Swpaul if (swap) 41550974Swpaul *ptr = ntohs(word); 41650974Swpaul else 41750974Swpaul *ptr = word; 41850974Swpaul } 41950974Swpaul 42050974Swpaul return; 42150974Swpaul} 42250974Swpaul 42372197Swpaul#ifdef __i386__ 424102334Salfredstatic device_t 425102334Salfredsis_find_bridge(dev) 42672197Swpaul device_t dev; 42772197Swpaul{ 42872197Swpaul devclass_t pci_devclass; 42972197Swpaul device_t *pci_devices; 43072197Swpaul int pci_count = 0; 43172197Swpaul device_t *pci_children; 43272197Swpaul int pci_childcount = 0; 43372197Swpaul device_t *busp, *childp; 43487994Sarchie device_t child = NULL; 43572197Swpaul int i, j; 43672197Swpaul 43772197Swpaul if ((pci_devclass = devclass_find("pci")) == NULL) 43872197Swpaul return(NULL); 43972197Swpaul 44072197Swpaul devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 44172197Swpaul 44272197Swpaul for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 44372197Swpaul pci_childcount = 0; 44472197Swpaul device_get_children(*busp, &pci_children, &pci_childcount); 44572197Swpaul for (j = 0, childp = pci_children; 44672197Swpaul j < pci_childcount; j++, childp++) { 44772197Swpaul if (pci_get_vendor(*childp) == SIS_VENDORID && 44872197Swpaul pci_get_device(*childp) == 0x0008) { 44987994Sarchie child = *childp; 45087994Sarchie goto done; 45172197Swpaul } 45272197Swpaul } 45372197Swpaul } 45472197Swpaul 45587994Sarchiedone: 45672197Swpaul free(pci_devices, M_TEMP); 45772197Swpaul free(pci_children, M_TEMP); 45887994Sarchie return(child); 45972197Swpaul} 46072197Swpaul 461102334Salfredstatic void 462102334Salfredsis_read_cmos(sc, dev, dest, off, cnt) 46372197Swpaul struct sis_softc *sc; 46472197Swpaul device_t dev; 46572197Swpaul caddr_t dest; 46672197Swpaul int off; 46772197Swpaul int cnt; 46872197Swpaul{ 46972197Swpaul device_t bridge; 47072197Swpaul u_int8_t reg; 47172197Swpaul int i; 47272197Swpaul bus_space_tag_t btag; 47372197Swpaul 47472197Swpaul bridge = sis_find_bridge(dev); 47572197Swpaul if (bridge == NULL) 47672197Swpaul return; 47772197Swpaul reg = pci_read_config(bridge, 0x48, 1); 47872197Swpaul pci_write_config(bridge, 0x48, reg|0x40, 1); 47972197Swpaul 48072197Swpaul /* XXX */ 48172197Swpaul btag = I386_BUS_SPACE_IO; 48272197Swpaul 48372197Swpaul for (i = 0; i < cnt; i++) { 48472197Swpaul bus_space_write_1(btag, 0x0, 0x70, i + off); 48572197Swpaul *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 48672197Swpaul } 48772197Swpaul 48872197Swpaul pci_write_config(bridge, 0x48, reg & ~0x40, 1); 48972197Swpaul return; 49072197Swpaul} 49189296Swpaul 492102334Salfredstatic void 493102334Salfredsis_read_mac(sc, dev, dest) 49489296Swpaul struct sis_softc *sc; 49589296Swpaul device_t dev; 49689296Swpaul caddr_t dest; 49789296Swpaul{ 49889296Swpaul u_int32_t filtsave, csrsave; 49989296Swpaul 50089296Swpaul filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 50189296Swpaul csrsave = CSR_READ_4(sc, SIS_CSR); 50289296Swpaul 50389296Swpaul CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 50489296Swpaul CSR_WRITE_4(sc, SIS_CSR, 0); 50589296Swpaul 50689296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 50789296Swpaul 50889296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 50989296Swpaul ((u_int16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 51089296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 51189296Swpaul ((u_int16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 51289296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 51389296Swpaul ((u_int16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 51489296Swpaul 51589296Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 51689296Swpaul CSR_WRITE_4(sc, SIS_CSR, csrsave); 51789296Swpaul return; 51889296Swpaul} 51972197Swpaul#endif 52072197Swpaul 521109060Smbr/* 522109060Smbr * Sync the PHYs by setting data bit and strobing the clock 32 times. 523109060Smbr */ 524109060Smbrstatic void sis_mii_sync(sc) 525109060Smbr struct sis_softc *sc; 526109060Smbr{ 527109060Smbr register int i; 528109060Smbr 529109060Smbr SIO_SET(SIS_MII_DIR|SIS_MII_DATA); 530109060Smbr 531109060Smbr for (i = 0; i < 32; i++) { 532109060Smbr SIO_SET(SIS_MII_CLK); 533109060Smbr DELAY(1); 534109060Smbr SIO_CLR(SIS_MII_CLK); 535109060Smbr DELAY(1); 536109060Smbr } 537109060Smbr 538109060Smbr return; 539109060Smbr} 540109060Smbr 541109060Smbr/* 542109060Smbr * Clock a series of bits through the MII. 543109060Smbr */ 544109060Smbrstatic void sis_mii_send(sc, bits, cnt) 545109060Smbr struct sis_softc *sc; 546109060Smbr u_int32_t bits; 547109060Smbr int cnt; 548109060Smbr{ 549109060Smbr int i; 550109060Smbr 551109060Smbr SIO_CLR(SIS_MII_CLK); 552109060Smbr 553109060Smbr for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 554109060Smbr if (bits & i) { 555109060Smbr SIO_SET(SIS_MII_DATA); 556109060Smbr } else { 557109060Smbr SIO_CLR(SIS_MII_DATA); 558109060Smbr } 559109060Smbr DELAY(1); 560109060Smbr SIO_CLR(SIS_MII_CLK); 561109060Smbr DELAY(1); 562109060Smbr SIO_SET(SIS_MII_CLK); 563109060Smbr } 564109060Smbr} 565109060Smbr 566109060Smbr/* 567109060Smbr * Read an PHY register through the MII. 568109060Smbr */ 569109060Smbrstatic int sis_mii_readreg(sc, frame) 570109060Smbr struct sis_softc *sc; 571109060Smbr struct sis_mii_frame *frame; 572109060Smbr 573109060Smbr{ 574109060Smbr int i, ack, s; 575109060Smbr 576109060Smbr s = splimp(); 577109060Smbr 578109060Smbr /* 579109060Smbr * Set up frame for RX. 580109060Smbr */ 581109060Smbr frame->mii_stdelim = SIS_MII_STARTDELIM; 582109060Smbr frame->mii_opcode = SIS_MII_READOP; 583109060Smbr frame->mii_turnaround = 0; 584109060Smbr frame->mii_data = 0; 585109060Smbr 586109060Smbr /* 587109060Smbr * Turn on data xmit. 588109060Smbr */ 589109060Smbr SIO_SET(SIS_MII_DIR); 590109060Smbr 591109060Smbr sis_mii_sync(sc); 592109060Smbr 593109060Smbr /* 594109060Smbr * Send command/address info. 595109060Smbr */ 596109060Smbr sis_mii_send(sc, frame->mii_stdelim, 2); 597109060Smbr sis_mii_send(sc, frame->mii_opcode, 2); 598109060Smbr sis_mii_send(sc, frame->mii_phyaddr, 5); 599109060Smbr sis_mii_send(sc, frame->mii_regaddr, 5); 600109060Smbr 601109060Smbr /* Idle bit */ 602109060Smbr SIO_CLR((SIS_MII_CLK|SIS_MII_DATA)); 603109060Smbr DELAY(1); 604109060Smbr SIO_SET(SIS_MII_CLK); 605109060Smbr DELAY(1); 606109060Smbr 607109060Smbr /* Turn off xmit. */ 608109060Smbr SIO_CLR(SIS_MII_DIR); 609109060Smbr 610109060Smbr /* Check for ack */ 611109060Smbr SIO_CLR(SIS_MII_CLK); 612109060Smbr DELAY(1); 613109060Smbr ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA; 614109060Smbr SIO_SET(SIS_MII_CLK); 615109060Smbr DELAY(1); 616109060Smbr 617109060Smbr /* 618109060Smbr * Now try reading data bits. If the ack failed, we still 619109060Smbr * need to clock through 16 cycles to keep the PHY(s) in sync. 620109060Smbr */ 621109060Smbr if (ack) { 622109060Smbr for(i = 0; i < 16; i++) { 623109060Smbr SIO_CLR(SIS_MII_CLK); 624109060Smbr DELAY(1); 625109060Smbr SIO_SET(SIS_MII_CLK); 626109060Smbr DELAY(1); 627109060Smbr } 628109060Smbr goto fail; 629109060Smbr } 630109060Smbr 631109060Smbr for (i = 0x8000; i; i >>= 1) { 632109060Smbr SIO_CLR(SIS_MII_CLK); 633109060Smbr DELAY(1); 634109060Smbr if (!ack) { 635109060Smbr if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA) 636109060Smbr frame->mii_data |= i; 637109060Smbr DELAY(1); 638109060Smbr } 639109060Smbr SIO_SET(SIS_MII_CLK); 640109060Smbr DELAY(1); 641109060Smbr } 642109060Smbr 643109060Smbrfail: 644109060Smbr 645109060Smbr SIO_CLR(SIS_MII_CLK); 646109060Smbr DELAY(1); 647109060Smbr SIO_SET(SIS_MII_CLK); 648109060Smbr DELAY(1); 649109060Smbr 650109060Smbr splx(s); 651109060Smbr 652109060Smbr if (ack) 653109060Smbr return(1); 654109060Smbr return(0); 655109060Smbr} 656109060Smbr 657109060Smbr/* 658109060Smbr * Write to a PHY register through the MII. 659109060Smbr */ 660109060Smbrstatic int sis_mii_writereg(sc, frame) 661109060Smbr struct sis_softc *sc; 662109060Smbr struct sis_mii_frame *frame; 663109060Smbr 664109060Smbr{ 665109060Smbr int s; 666109060Smbr 667109060Smbr s = splimp(); 668109060Smbr /* 669109060Smbr * Set up frame for TX. 670109060Smbr */ 671109060Smbr 672109060Smbr frame->mii_stdelim = SIS_MII_STARTDELIM; 673109060Smbr frame->mii_opcode = SIS_MII_WRITEOP; 674109060Smbr frame->mii_turnaround = SIS_MII_TURNAROUND; 675109060Smbr 676109060Smbr /* 677109060Smbr * Turn on data output. 678109060Smbr */ 679109060Smbr SIO_SET(SIS_MII_DIR); 680109060Smbr 681109060Smbr sis_mii_sync(sc); 682109060Smbr 683109060Smbr sis_mii_send(sc, frame->mii_stdelim, 2); 684109060Smbr sis_mii_send(sc, frame->mii_opcode, 2); 685109060Smbr sis_mii_send(sc, frame->mii_phyaddr, 5); 686109060Smbr sis_mii_send(sc, frame->mii_regaddr, 5); 687109060Smbr sis_mii_send(sc, frame->mii_turnaround, 2); 688109060Smbr sis_mii_send(sc, frame->mii_data, 16); 689109060Smbr 690109060Smbr /* Idle bit. */ 691109060Smbr SIO_SET(SIS_MII_CLK); 692109060Smbr DELAY(1); 693109060Smbr SIO_CLR(SIS_MII_CLK); 694109060Smbr DELAY(1); 695109060Smbr 696109060Smbr /* 697109060Smbr * Turn off xmit. 698109060Smbr */ 699109060Smbr SIO_CLR(SIS_MII_DIR); 700109060Smbr 701109060Smbr splx(s); 702109060Smbr 703109060Smbr return(0); 704109060Smbr} 705109060Smbr 706102334Salfredstatic int 707102334Salfredsis_miibus_readreg(dev, phy, reg) 70850974Swpaul device_t dev; 70950974Swpaul int phy, reg; 71050974Swpaul{ 71150974Swpaul struct sis_softc *sc; 712109060Smbr struct sis_mii_frame frame; 71350974Swpaul 71450974Swpaul sc = device_get_softc(dev); 71550974Swpaul 71662672Swpaul if (sc->sis_type == SIS_TYPE_83815) { 71762672Swpaul if (phy != 0) 71862672Swpaul return(0); 71962672Swpaul /* 72062672Swpaul * The NatSemi chip can take a while after 72162672Swpaul * a reset to come ready, during which the BMSR 72262672Swpaul * returns a value of 0. This is *never* supposed 72362672Swpaul * to happen: some of the BMSR bits are meant to 72462672Swpaul * be hardwired in the on position, and this can 72562672Swpaul * confuse the miibus code a bit during the probe 72662672Swpaul * and attach phase. So we make an effort to check 72762672Swpaul * for this condition and wait for it to clear. 72862672Swpaul */ 72962672Swpaul if (!CSR_READ_4(sc, NS_BMSR)) 73062672Swpaul DELAY(1000); 731109060Smbr return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 73262672Swpaul } 73362672Swpaul 73489296Swpaul if (sc->sis_type == SIS_TYPE_900 && 73589296Swpaul sc->sis_rev < SIS_REV_635 && phy != 0) 73650974Swpaul return(0); 73750974Swpaul 738109060Smbr bzero((char *)&frame, sizeof(frame)); 73950974Swpaul 740109060Smbr frame.mii_phyaddr = phy; 741109060Smbr frame.mii_regaddr = reg; 742109060Smbr sis_mii_readreg(sc, &frame); 74350974Swpaul 744109060Smbr return(frame.mii_data); 74550974Swpaul} 74650974Swpaul 747102334Salfredstatic int 748102334Salfredsis_miibus_writereg(dev, phy, reg, data) 74950974Swpaul device_t dev; 75050974Swpaul int phy, reg, data; 75150974Swpaul{ 75250974Swpaul struct sis_softc *sc; 753109060Smbr struct sis_mii_frame frame; 75450974Swpaul 75550974Swpaul sc = device_get_softc(dev); 75650974Swpaul 75762672Swpaul if (sc->sis_type == SIS_TYPE_83815) { 75862672Swpaul if (phy != 0) 75962672Swpaul return(0); 76062672Swpaul CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 76162672Swpaul return(0); 76262672Swpaul } 76362672Swpaul 76450974Swpaul if (sc->sis_type == SIS_TYPE_900 && phy != 0) 76550974Swpaul return(0); 76650974Swpaul 767109060Smbr bzero((char *)&frame, sizeof(frame)); 76850974Swpaul 769109060Smbr frame.mii_phyaddr = phy; 770109060Smbr frame.mii_regaddr = reg; 771109060Smbr frame.mii_data = data; 77250974Swpaul 773109060Smbr sis_mii_writereg(sc, &frame); 77450974Swpaul 77550974Swpaul return(0); 77650974Swpaul} 77750974Swpaul 778102334Salfredstatic void 779102334Salfredsis_miibus_statchg(dev) 78050974Swpaul device_t dev; 78150974Swpaul{ 78250974Swpaul struct sis_softc *sc; 78350974Swpaul 78450974Swpaul sc = device_get_softc(dev); 78564963Swpaul sis_init(sc); 78650974Swpaul 78750974Swpaul return; 78850974Swpaul} 78950974Swpaul 790102334Salfredstatic u_int32_t 791102334Salfredsis_crc(sc, addr) 79262672Swpaul struct sis_softc *sc; 79350974Swpaul caddr_t addr; 79450974Swpaul{ 79550974Swpaul u_int32_t crc, carry; 79650974Swpaul int i, j; 79750974Swpaul u_int8_t c; 79850974Swpaul 79950974Swpaul /* Compute CRC for the address value. */ 80050974Swpaul crc = 0xFFFFFFFF; /* initial value */ 80150974Swpaul 80250974Swpaul for (i = 0; i < 6; i++) { 80350974Swpaul c = *(addr + i); 80450974Swpaul for (j = 0; j < 8; j++) { 80550974Swpaul carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 80650974Swpaul crc <<= 1; 80750974Swpaul c >>= 1; 80850974Swpaul if (carry) 80950974Swpaul crc = (crc ^ 0x04c11db6) | carry; 81050974Swpaul } 81150974Swpaul } 81250974Swpaul 81362672Swpaul /* 81462672Swpaul * return the filter bit position 81562672Swpaul * 81662672Swpaul * The NatSemi chip has a 512-bit filter, which is 81762672Swpaul * different than the SiS, so we special-case it. 81862672Swpaul */ 81962672Swpaul if (sc->sis_type == SIS_TYPE_83815) 820109060Smbr return (crc >> 23); 82162672Swpaul 822109060Smbr if (sc->sis_rev >= SIS_REV_635) 823109060Smbr return (crc >> 24); 824109060Smbr 825109060Smbr return (crc >> 25); 82650974Swpaul} 82750974Swpaul 828102334Salfredstatic void 829102334Salfredsis_setmulti_ns(sc) 83050974Swpaul struct sis_softc *sc; 83150974Swpaul{ 83250974Swpaul struct ifnet *ifp; 83350974Swpaul struct ifmultiaddr *ifma; 83450974Swpaul u_int32_t h = 0, i, filtsave; 83562672Swpaul int bit, index; 83650974Swpaul 83750974Swpaul ifp = &sc->arpcom.ac_if; 83850974Swpaul 83950974Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 84062672Swpaul SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 84150974Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 84250974Swpaul return; 84350974Swpaul } 84450974Swpaul 84562672Swpaul /* 84662672Swpaul * We have to explicitly enable the multicast hash table 84762672Swpaul * on the NatSemi chip if we want to use it, which we do. 84862672Swpaul */ 84962672Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 85050974Swpaul SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 85150974Swpaul 85250974Swpaul filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 85350974Swpaul 85450974Swpaul /* first, zot all the existing hash bits */ 85562672Swpaul for (i = 0; i < 32; i++) { 85662672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 85762672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 85862672Swpaul } 85962672Swpaul 86072084Sphk TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 86162672Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 86262672Swpaul continue; 86362672Swpaul h = sis_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 86462672Swpaul index = h >> 3; 86562672Swpaul bit = h & 0x1F; 86662672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 86762672Swpaul if (bit > 0xF) 86862672Swpaul bit -= 0x10; 86962672Swpaul SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 87062672Swpaul } 87162672Swpaul 87262672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 87362672Swpaul 87462672Swpaul return; 87562672Swpaul} 87662672Swpaul 877102334Salfredstatic void 878102334Salfredsis_setmulti_sis(sc) 87962672Swpaul struct sis_softc *sc; 88062672Swpaul{ 88162672Swpaul struct ifnet *ifp; 88262672Swpaul struct ifmultiaddr *ifma; 883109060Smbr u_int32_t h, i, n, ctl; 884109060Smbr u_int16_t hashes[16]; 88562672Swpaul 88662672Swpaul ifp = &sc->arpcom.ac_if; 88762672Swpaul 888109060Smbr /* hash table size */ 889109060Smbr n = sc->sis_rev >= SIS_REV_635 ? 16 : 8; 89062672Swpaul 891109060Smbr ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE; 89262672Swpaul 893109060Smbr if (ifp->if_flags & IFF_BROADCAST) 894109060Smbr ctl |= SIS_RXFILTCTL_BROAD; 89562672Swpaul 896109060Smbr if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 897109060Smbr ctl |= SIS_RXFILTCTL_ALLMULTI; 898109060Smbr if (ifp->if_flags & IFF_PROMISC) 899109060Smbr ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS; 900109060Smbr for (i = 0; i < n; i++) 901109060Smbr hashes[i] = ~0; 902109060Smbr } else { 903109060Smbr for (i = 0; i < n; i++) 904109060Smbr hashes[i] = 0; 905109060Smbr i = 0; 906109060Smbr TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 907109060Smbr if (ifma->ifma_addr->sa_family != AF_LINK) 908109060Smbr continue; 909109060Smbr h = sis_crc(sc, 910109060Smbr LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 911109060Smbr hashes[h >> 4] |= 1 << (h & 0xf); 912109060Smbr i++; 913109060Smbr } 914109060Smbr if (i > n) { 915109060Smbr ctl |= SIS_RXFILTCTL_ALLMULTI; 916109060Smbr for (i = 0; i < n; i++) 917109060Smbr hashes[i] = ~0; 918109060Smbr } 91950974Swpaul } 92050974Swpaul 921109060Smbr for (i = 0; i < n; i++) { 922109060Smbr CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); 923109060Smbr CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); 92450974Swpaul } 92550974Swpaul 926109060Smbr CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl); 92750974Swpaul} 92850974Swpaul 929102334Salfredstatic void 930102334Salfredsis_reset(sc) 93150974Swpaul struct sis_softc *sc; 93250974Swpaul{ 93350974Swpaul register int i; 93450974Swpaul 93550974Swpaul SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 93650974Swpaul 93750974Swpaul for (i = 0; i < SIS_TIMEOUT; i++) { 93850974Swpaul if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 93950974Swpaul break; 94050974Swpaul } 94150974Swpaul 94250974Swpaul if (i == SIS_TIMEOUT) 94350974Swpaul printf("sis%d: reset never completed\n", sc->sis_unit); 94450974Swpaul 94550974Swpaul /* Wait a little while for the chip to get its brains in order. */ 94650974Swpaul DELAY(1000); 94772813Swpaul 94872813Swpaul /* 94972813Swpaul * If this is a NetSemi chip, make sure to clear 95072813Swpaul * PME mode. 95172813Swpaul */ 95272813Swpaul if (sc->sis_type == SIS_TYPE_83815) { 95372813Swpaul CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 95472813Swpaul CSR_WRITE_4(sc, NS_CLKRUN, 0); 95572813Swpaul } 95672813Swpaul 95750974Swpaul return; 95850974Swpaul} 95950974Swpaul 96050974Swpaul/* 96150974Swpaul * Probe for an SiS chip. Check the PCI vendor and device 96250974Swpaul * IDs against our list and return a device name if we find a match. 96350974Swpaul */ 964102334Salfredstatic int 965102334Salfredsis_probe(dev) 96650974Swpaul device_t dev; 96750974Swpaul{ 96850974Swpaul struct sis_type *t; 96950974Swpaul 97050974Swpaul t = sis_devs; 97150974Swpaul 97250974Swpaul while(t->sis_name != NULL) { 97350974Swpaul if ((pci_get_vendor(dev) == t->sis_vid) && 97450974Swpaul (pci_get_device(dev) == t->sis_did)) { 97550974Swpaul device_set_desc(dev, t->sis_name); 97650974Swpaul return(0); 97750974Swpaul } 97850974Swpaul t++; 97950974Swpaul } 98050974Swpaul 98150974Swpaul return(ENXIO); 98250974Swpaul} 98350974Swpaul 98450974Swpaul/* 98550974Swpaul * Attach the interface. Allocate softc structures, do ifmedia 98650974Swpaul * setup and ethernet/BPF attach. 98750974Swpaul */ 988102334Salfredstatic int 989102334Salfredsis_attach(dev) 99050974Swpaul device_t dev; 99150974Swpaul{ 99250974Swpaul u_char eaddr[ETHER_ADDR_LEN]; 99350974Swpaul u_int32_t command; 99450974Swpaul struct sis_softc *sc; 99550974Swpaul struct ifnet *ifp; 996109061Smbr int unit, error = 0, rid, waittime = 0; 99750974Swpaul 998109061Smbr waittime = 0; 99950974Swpaul sc = device_get_softc(dev); 100050974Swpaul unit = device_get_unit(dev); 100150974Swpaul bzero(sc, sizeof(struct sis_softc)); 100250974Swpaul 100393818Sjhb mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 100493818Sjhb MTX_DEF | MTX_RECURSE); 100569583Swpaul 100650974Swpaul if (pci_get_device(dev) == SIS_DEVICEID_900) 100750974Swpaul sc->sis_type = SIS_TYPE_900; 100850974Swpaul if (pci_get_device(dev) == SIS_DEVICEID_7016) 100950974Swpaul sc->sis_type = SIS_TYPE_7016; 101062672Swpaul if (pci_get_vendor(dev) == NS_VENDORID) 101162672Swpaul sc->sis_type = SIS_TYPE_83815; 101250974Swpaul 101389296Swpaul sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 101489296Swpaul 101550974Swpaul /* 101650974Swpaul * Handle power management nonsense. 101750974Swpaul */ 101872813Swpaul if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 101972813Swpaul u_int32_t iobase, membase, irq; 102050974Swpaul 102172813Swpaul /* Save important PCI config data. */ 102272813Swpaul iobase = pci_read_config(dev, SIS_PCI_LOIO, 4); 102372813Swpaul membase = pci_read_config(dev, SIS_PCI_LOMEM, 4); 102472813Swpaul irq = pci_read_config(dev, SIS_PCI_INTLINE, 4); 102550974Swpaul 102672813Swpaul /* Reset the power state. */ 102772813Swpaul printf("sis%d: chip is in D%d power mode " 102872813Swpaul "-- setting to D0\n", unit, 102972813Swpaul pci_get_powerstate(dev)); 103072813Swpaul pci_set_powerstate(dev, PCI_POWERSTATE_D0); 103150974Swpaul 103272813Swpaul /* Restore PCI config data. */ 103372813Swpaul pci_write_config(dev, SIS_PCI_LOIO, iobase, 4); 103472813Swpaul pci_write_config(dev, SIS_PCI_LOMEM, membase, 4); 103572813Swpaul pci_write_config(dev, SIS_PCI_INTLINE, irq, 4); 103650974Swpaul } 103750974Swpaul 103850974Swpaul /* 103950974Swpaul * Map control/status registers. 104050974Swpaul */ 104172813Swpaul pci_enable_busmaster(dev); 104279472Swpaul pci_enable_io(dev, SYS_RES_IOPORT); 104379472Swpaul pci_enable_io(dev, SYS_RES_MEMORY); 104461041Speter command = pci_read_config(dev, PCIR_COMMAND, 4); 104550974Swpaul 104650974Swpaul#ifdef SIS_USEIOSPACE 104750974Swpaul if (!(command & PCIM_CMD_PORTEN)) { 104850974Swpaul printf("sis%d: failed to enable I/O ports!\n", unit); 104950974Swpaul error = ENXIO;; 105050974Swpaul goto fail; 105150974Swpaul } 105250974Swpaul#else 105350974Swpaul if (!(command & PCIM_CMD_MEMEN)) { 105450974Swpaul printf("sis%d: failed to enable memory mapping!\n", unit); 105550974Swpaul error = ENXIO;; 105650974Swpaul goto fail; 105750974Swpaul } 105850974Swpaul#endif 105950974Swpaul 106050974Swpaul rid = SIS_RID; 106150974Swpaul sc->sis_res = bus_alloc_resource(dev, SIS_RES, &rid, 106250974Swpaul 0, ~0, 1, RF_ACTIVE); 106350974Swpaul 106450974Swpaul if (sc->sis_res == NULL) { 106550974Swpaul printf("sis%d: couldn't map ports/memory\n", unit); 106650974Swpaul error = ENXIO; 106750974Swpaul goto fail; 106850974Swpaul } 106950974Swpaul 107050974Swpaul sc->sis_btag = rman_get_bustag(sc->sis_res); 107150974Swpaul sc->sis_bhandle = rman_get_bushandle(sc->sis_res); 107250974Swpaul 107350974Swpaul /* Allocate interrupt */ 107450974Swpaul rid = 0; 107550974Swpaul sc->sis_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 107650974Swpaul RF_SHAREABLE | RF_ACTIVE); 107750974Swpaul 107850974Swpaul if (sc->sis_irq == NULL) { 107950974Swpaul printf("sis%d: couldn't map interrupt\n", unit); 108050974Swpaul bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 108150974Swpaul error = ENXIO; 108250974Swpaul goto fail; 108350974Swpaul } 108450974Swpaul 108550974Swpaul error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET, 108650974Swpaul sis_intr, sc, &sc->sis_intrhand); 108750974Swpaul 108850974Swpaul if (error) { 108968216Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 109050974Swpaul bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 109150974Swpaul printf("sis%d: couldn't set up irq\n", unit); 109250974Swpaul goto fail; 109350974Swpaul } 109450974Swpaul 109550974Swpaul /* Reset the adapter. */ 109650974Swpaul sis_reset(sc); 109750974Swpaul 109850974Swpaul /* 109950974Swpaul * Get station address from the EEPROM. 110050974Swpaul */ 110162672Swpaul switch (pci_get_vendor(dev)) { 110262672Swpaul case NS_VENDORID: 110362672Swpaul /* 110462672Swpaul * Reading the MAC address out of the EEPROM on 110562672Swpaul * the NatSemi chip takes a bit more work than 110662672Swpaul * you'd expect. The address spans 4 16-bit words, 110762672Swpaul * with the first word containing only a single bit. 110862672Swpaul * You have to shift everything over one bit to 110962672Swpaul * get it aligned properly. Also, the bits are 111062672Swpaul * stored backwards (the LSB is really the MSB, 111162672Swpaul * and so on) so you have to reverse them in order 111262672Swpaul * to get the MAC address into the form we want. 111362672Swpaul * Why? Who the hell knows. 111462672Swpaul */ 111562672Swpaul { 111662672Swpaul u_int16_t tmp[4]; 111750974Swpaul 111862672Swpaul sis_read_eeprom(sc, (caddr_t)&tmp, 111962672Swpaul NS_EE_NODEADDR, 4, 0); 112062672Swpaul 112162672Swpaul /* Shift everything over one bit. */ 112262672Swpaul tmp[3] = tmp[3] >> 1; 112362681Swpaul tmp[3] |= tmp[2] << 15; 112462672Swpaul tmp[2] = tmp[2] >> 1; 112562681Swpaul tmp[2] |= tmp[1] << 15; 112662672Swpaul tmp[1] = tmp[1] >> 1; 112762681Swpaul tmp[1] |= tmp[0] << 15; 112862672Swpaul 112962672Swpaul /* Now reverse all the bits. */ 113062672Swpaul tmp[3] = sis_reverse(tmp[3]); 113162672Swpaul tmp[2] = sis_reverse(tmp[2]); 113262672Swpaul tmp[1] = sis_reverse(tmp[1]); 113362672Swpaul 113462672Swpaul bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); 113562672Swpaul } 113662672Swpaul break; 113762672Swpaul case SIS_VENDORID: 113862672Swpaul default: 113972197Swpaul#ifdef __i386__ 114072197Swpaul /* 114172197Swpaul * If this is a SiS 630E chipset with an embedded 114272197Swpaul * SiS 900 controller, we have to read the MAC address 114372197Swpaul * from the APC CMOS RAM. Our method for doing this 114472197Swpaul * is very ugly since we have to reach out and grab 114572197Swpaul * ahold of hardware for which we cannot properly 114672197Swpaul * allocate resources. This code is only compiled on 114772197Swpaul * the i386 architecture since the SiS 630E chipset 114872197Swpaul * is for x86 motherboards only. Note that there are 114972197Swpaul * a lot of magic numbers in this hack. These are 115072197Swpaul * taken from SiS's Linux driver. I'd like to replace 115172197Swpaul * them with proper symbolic definitions, but that 115272197Swpaul * requires some datasheets that I don't have access 115372197Swpaul * to at the moment. 115472197Swpaul */ 115589296Swpaul if (sc->sis_rev == SIS_REV_630S || 115689296Swpaul sc->sis_rev == SIS_REV_630E || 115790328Sambrisko sc->sis_rev == SIS_REV_630EA1) 115872197Swpaul sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 115989296Swpaul 116090328Sambrisko else if (sc->sis_rev == SIS_REV_635 || 116190328Sambrisko sc->sis_rev == SIS_REV_630ET) 116289296Swpaul sis_read_mac(sc, dev, (caddr_t)&eaddr); 1163109061Smbr else if (sc->sis_rev == SIS_REV_96x) { 1164109061Smbr /* Allow to read EEPROM from LAN. It is shared 1165109061Smbr * between a 1394 controller and the NIC and each 1166109061Smbr * time we access it, we need to set SIS_EECMD_REQ. 1167109061Smbr */ 1168109061Smbr SIO_SET(SIS_EECMD_REQ); 1169109061Smbr for (waittime = 0; waittime < SIS_TIMEOUT; 1170109061Smbr waittime++) { 1171109061Smbr /* Force EEPROM to idle state. */ 1172109061Smbr sis_eeprom_idle(sc); 1173109061Smbr if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { 1174109061Smbr sis_read_eeprom(sc, (caddr_t)&eaddr, 1175109061Smbr SIS_EE_NODEADDR, 3, 0); 1176109061Smbr break; 1177109061Smbr } 1178109061Smbr DELAY(1); 1179109061Smbr } 1180109061Smbr /* 1181109061Smbr * Set SIS_EECTL_CLK to high, so a other master 1182109061Smbr * can operate on the i2c bus. 1183109061Smbr */ 1184109061Smbr SIO_SET(SIS_EECTL_CLK); 1185109061Smbr /* Refuse EEPROM access by LAN */ 1186109061Smbr SIO_SET(SIS_EECMD_DONE); 1187109061Smbr } else 118872197Swpaul#endif 118972197Swpaul sis_read_eeprom(sc, (caddr_t)&eaddr, 119072197Swpaul SIS_EE_NODEADDR, 3, 0); 119162672Swpaul break; 119262672Swpaul } 119362672Swpaul 119450974Swpaul /* 119550974Swpaul * A SiS chip was detected. Inform the world. 119650974Swpaul */ 119750974Swpaul printf("sis%d: Ethernet address: %6D\n", unit, eaddr, ":"); 119850974Swpaul 119950974Swpaul sc->sis_unit = unit; 120050974Swpaul callout_handle_init(&sc->sis_stat_ch); 120150974Swpaul bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 120250974Swpaul 120381713Swpaul /* 120481713Swpaul * Allocate the parent bus DMA tag appropriate for PCI. 120581713Swpaul */ 120681713Swpaul#define SIS_NSEG_NEW 32 120781713Swpaul error = bus_dma_tag_create(NULL, /* parent */ 120881713Swpaul 1, 0, /* alignment, boundary */ 120981713Swpaul BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 121081713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 121181713Swpaul NULL, NULL, /* filter, filterarg */ 121281713Swpaul MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */ 121381713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 121481713Swpaul BUS_DMA_ALLOCNOW, /* flags */ 121581713Swpaul &sc->sis_parent_tag); 121650974Swpaul 121781713Swpaul /* 121881713Swpaul * Now allocate a tag for the DMA descriptor lists. 121981713Swpaul * All of our lists are allocated as a contiguous block 122081713Swpaul * of memory. 122181713Swpaul */ 122281713Swpaul error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 122381713Swpaul 1, 0, /* alignment, boundary */ 122481713Swpaul BUS_SPACE_MAXADDR, /* lowaddr */ 122581713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 122681713Swpaul NULL, NULL, /* filter, filterarg */ 122781713Swpaul SIS_RX_LIST_SZ, 1, /* maxsize,nsegments */ 122881713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 122981713Swpaul 0, /* flags */ 123081713Swpaul &sc->sis_ldata.sis_rx_tag); 123181713Swpaul 123281713Swpaul error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 123381713Swpaul 1, 0, /* alignment, boundary */ 123481713Swpaul BUS_SPACE_MAXADDR, /* lowaddr */ 123581713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 123681713Swpaul NULL, NULL, /* filter, filterarg */ 123781713Swpaul SIS_TX_LIST_SZ, 1, /* maxsize,nsegments */ 123881713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 123981713Swpaul 0, /* flags */ 124081713Swpaul &sc->sis_ldata.sis_tx_tag); 124181713Swpaul 124281713Swpaul error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 124381713Swpaul 1, 0, /* alignment, boundary */ 124481713Swpaul BUS_SPACE_MAXADDR, /* lowaddr */ 124581713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 124681713Swpaul NULL, NULL, /* filter, filterarg */ 1247107833Smux MCLBYTES, 1, /* maxsize,nsegments */ 124881713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 124981713Swpaul 0, /* flags */ 125081713Swpaul &sc->sis_tag); 125181713Swpaul 125281713Swpaul /* 125381713Swpaul * Now allocate a chunk of DMA-able memory based on the 125481713Swpaul * tag we just created. 125581713Swpaul */ 125681713Swpaul error = bus_dmamem_alloc(sc->sis_ldata.sis_tx_tag, 125781713Swpaul (void **)&sc->sis_ldata.sis_tx_list, BUS_DMA_NOWAIT, 125881713Swpaul &sc->sis_ldata.sis_tx_dmamap); 125981713Swpaul 126081713Swpaul if (error) { 126150974Swpaul printf("sis%d: no memory for list buffers!\n", unit); 126250974Swpaul bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 126350974Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 126450974Swpaul bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 126581713Swpaul bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 126681713Swpaul bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 126750974Swpaul error = ENXIO; 126850974Swpaul goto fail; 126950974Swpaul } 127050974Swpaul 127181713Swpaul error = bus_dmamem_alloc(sc->sis_ldata.sis_rx_tag, 127281713Swpaul (void **)&sc->sis_ldata.sis_rx_list, BUS_DMA_NOWAIT, 127381713Swpaul &sc->sis_ldata.sis_rx_dmamap); 127481713Swpaul 127581713Swpaul if (error) { 127681713Swpaul printf("sis%d: no memory for list buffers!\n", unit); 127781713Swpaul bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 127881713Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 127981713Swpaul bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 128081713Swpaul bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 128181713Swpaul sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 128281713Swpaul bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 128381713Swpaul bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 128481713Swpaul error = ENXIO; 128581713Swpaul goto fail; 128681713Swpaul } 128781713Swpaul 128881713Swpaul 128981713Swpaul bzero(sc->sis_ldata.sis_tx_list, SIS_TX_LIST_SZ); 129081713Swpaul bzero(sc->sis_ldata.sis_rx_list, SIS_RX_LIST_SZ); 129181713Swpaul 129281713Swpaul /* 129381713Swpaul * Obtain the physical addresses of the RX and TX 129481713Swpaul * rings which we'll need later in the init routine. 129581713Swpaul */ 129681713Swpaul bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 129781713Swpaul sc->sis_ldata.sis_tx_dmamap, &(sc->sis_ldata.sis_tx_list[0]), 129881713Swpaul sizeof(struct sis_desc), sis_dma_map_ring, 129981713Swpaul &sc->sis_cdata.sis_tx_paddr, 0); 130081713Swpaul bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 130181713Swpaul sc->sis_ldata.sis_rx_dmamap, &(sc->sis_ldata.sis_rx_list[0]), 130281713Swpaul sizeof(struct sis_desc), sis_dma_map_ring, 130381713Swpaul &sc->sis_cdata.sis_rx_paddr, 0); 130481713Swpaul 130550974Swpaul ifp = &sc->arpcom.ac_if; 130650974Swpaul ifp->if_softc = sc; 130750974Swpaul ifp->if_unit = unit; 130850974Swpaul ifp->if_name = "sis"; 130950974Swpaul ifp->if_mtu = ETHERMTU; 131050974Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 131150974Swpaul ifp->if_ioctl = sis_ioctl; 131250974Swpaul ifp->if_output = ether_output; 131350974Swpaul ifp->if_start = sis_start; 131450974Swpaul ifp->if_watchdog = sis_watchdog; 131550974Swpaul ifp->if_init = sis_init; 131650974Swpaul ifp->if_baudrate = 10000000; 131750974Swpaul ifp->if_snd.ifq_maxlen = SIS_TX_LIST_CNT - 1; 131850974Swpaul 131950974Swpaul /* 132050974Swpaul * Do MII setup. 132150974Swpaul */ 132250974Swpaul if (mii_phy_probe(dev, &sc->sis_miibus, 132350974Swpaul sis_ifmedia_upd, sis_ifmedia_sts)) { 132450974Swpaul printf("sis%d: MII without any PHY!\n", sc->sis_unit); 132550974Swpaul bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 132650974Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 132750974Swpaul bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 132881713Swpaul bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 132981713Swpaul sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap); 133081713Swpaul bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 133181713Swpaul sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 133281713Swpaul bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 133381713Swpaul bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 133450974Swpaul error = ENXIO; 133550974Swpaul goto fail; 133650974Swpaul } 133750974Swpaul 133850974Swpaul /* 133963090Sarchie * Call MI attach routine. 134050974Swpaul */ 1341106936Ssam ether_ifattach(ifp, eaddr); 134287390Sjhay 134387390Sjhay /* 134487390Sjhay * Tell the upper layer(s) we support long frames. 134587390Sjhay */ 134687390Sjhay ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1347106936Ssam ifp->if_capabilities |= IFCAP_VLAN_MTU; 134887390Sjhay 134950974Swpaul callout_handle_init(&sc->sis_stat_ch); 135067087Swpaul return(0); 135150974Swpaul 135250974Swpaulfail: 135367087Swpaul mtx_destroy(&sc->sis_mtx); 135450974Swpaul return(error); 135550974Swpaul} 135650974Swpaul 1357102334Salfredstatic int 1358102334Salfredsis_detach(dev) 135950974Swpaul device_t dev; 136050974Swpaul{ 136150974Swpaul struct sis_softc *sc; 136250974Swpaul struct ifnet *ifp; 136350974Swpaul 136450974Swpaul 136550974Swpaul sc = device_get_softc(dev); 136667087Swpaul SIS_LOCK(sc); 136750974Swpaul ifp = &sc->arpcom.ac_if; 136850974Swpaul 136950974Swpaul sis_reset(sc); 137050974Swpaul sis_stop(sc); 1371106936Ssam ether_ifdetach(ifp); 137250974Swpaul 137350974Swpaul bus_generic_detach(dev); 137450974Swpaul device_delete_child(dev, sc->sis_miibus); 137550974Swpaul 137650974Swpaul bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 137750974Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 137850974Swpaul bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 137950974Swpaul 138081713Swpaul bus_dmamap_unload(sc->sis_ldata.sis_rx_tag, 138181713Swpaul sc->sis_ldata.sis_rx_dmamap); 138281713Swpaul bus_dmamap_unload(sc->sis_ldata.sis_tx_tag, 138381713Swpaul sc->sis_ldata.sis_tx_dmamap); 138481713Swpaul bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 138581713Swpaul sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap); 138681713Swpaul bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 138781713Swpaul sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 138881713Swpaul bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 138981713Swpaul bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 139081713Swpaul bus_dma_tag_destroy(sc->sis_parent_tag); 139150974Swpaul 139267087Swpaul SIS_UNLOCK(sc); 139367087Swpaul mtx_destroy(&sc->sis_mtx); 139450974Swpaul 139550974Swpaul return(0); 139650974Swpaul} 139750974Swpaul 139850974Swpaul/* 139950974Swpaul * Initialize the transmit descriptors. 140050974Swpaul */ 1401102334Salfredstatic int 1402102334Salfredsis_list_tx_init(sc) 140350974Swpaul struct sis_softc *sc; 140450974Swpaul{ 140550974Swpaul struct sis_list_data *ld; 140650974Swpaul struct sis_ring_data *cd; 140787059Sluigi int i, nexti; 140850974Swpaul 140950974Swpaul cd = &sc->sis_cdata; 141081713Swpaul ld = &sc->sis_ldata; 141150974Swpaul 141250974Swpaul for (i = 0; i < SIS_TX_LIST_CNT; i++) { 141387102Sluigi nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1; 141450974Swpaul ld->sis_tx_list[i].sis_nextdesc = 141587059Sluigi &ld->sis_tx_list[nexti]; 141681713Swpaul bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 141781713Swpaul sc->sis_ldata.sis_tx_dmamap, 141887059Sluigi &ld->sis_tx_list[nexti], sizeof(struct sis_desc), 141981713Swpaul sis_dma_map_desc_next, &ld->sis_tx_list[i], 0); 142050974Swpaul ld->sis_tx_list[i].sis_mbuf = NULL; 142150974Swpaul ld->sis_tx_list[i].sis_ptr = 0; 142250974Swpaul ld->sis_tx_list[i].sis_ctl = 0; 142350974Swpaul } 142450974Swpaul 142550974Swpaul cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0; 142650974Swpaul 142781713Swpaul bus_dmamap_sync(sc->sis_ldata.sis_tx_tag, 142881713Swpaul sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 142981713Swpaul 143050974Swpaul return(0); 143150974Swpaul} 143250974Swpaul 143350974Swpaul/* 143450974Swpaul * Initialize the RX descriptors and allocate mbufs for them. Note that 143550974Swpaul * we arrange the descriptors in a closed ring, so that the last descriptor 143650974Swpaul * points back to the first. 143750974Swpaul */ 1438102334Salfredstatic int 1439102334Salfredsis_list_rx_init(sc) 144050974Swpaul struct sis_softc *sc; 144150974Swpaul{ 144250974Swpaul struct sis_list_data *ld; 144350974Swpaul struct sis_ring_data *cd; 144487059Sluigi int i,nexti; 144550974Swpaul 144681713Swpaul ld = &sc->sis_ldata; 144750974Swpaul cd = &sc->sis_cdata; 144850974Swpaul 144950974Swpaul for (i = 0; i < SIS_RX_LIST_CNT; i++) { 145050974Swpaul if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS) 145150974Swpaul return(ENOBUFS); 145287102Sluigi nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1; 145350974Swpaul ld->sis_rx_list[i].sis_nextdesc = 145487059Sluigi &ld->sis_rx_list[nexti]; 145581713Swpaul bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 145681713Swpaul sc->sis_ldata.sis_rx_dmamap, 145787059Sluigi &ld->sis_rx_list[nexti], 145881713Swpaul sizeof(struct sis_desc), sis_dma_map_desc_next, 145981713Swpaul &ld->sis_rx_list[i], 0); 146050974Swpaul } 146150974Swpaul 146281713Swpaul bus_dmamap_sync(sc->sis_ldata.sis_rx_tag, 146381713Swpaul sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 146481713Swpaul 146550974Swpaul cd->sis_rx_prod = 0; 146650974Swpaul 146750974Swpaul return(0); 146850974Swpaul} 146950974Swpaul 147050974Swpaul/* 147150974Swpaul * Initialize an RX descriptor and attach an MBUF cluster. 147250974Swpaul */ 1473102334Salfredstatic int 1474102334Salfredsis_newbuf(sc, c, m) 147550974Swpaul struct sis_softc *sc; 147650974Swpaul struct sis_desc *c; 147750974Swpaul struct mbuf *m; 147850974Swpaul{ 147950974Swpaul 148081713Swpaul if (c == NULL) 148181713Swpaul return(EINVAL); 148281713Swpaul 148350974Swpaul if (m == NULL) { 1484109623Salfred m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1485101340Sluigi if (m == NULL) 148650974Swpaul return(ENOBUFS); 1487101340Sluigi } else 1488101340Sluigi m->m_data = m->m_ext.ext_buf; 148950974Swpaul 1490101340Sluigi c->sis_mbuf = m; 149150974Swpaul c->sis_ctl = SIS_RXLEN; 149250974Swpaul 149381713Swpaul bus_dmamap_create(sc->sis_tag, 0, &c->sis_map); 149481713Swpaul bus_dmamap_load(sc->sis_tag, c->sis_map, 1495101464Sluigi mtod(m, void *), MCLBYTES, 149681713Swpaul sis_dma_map_desc_ptr, c, 0); 149781713Swpaul bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREWRITE); 149881713Swpaul 149950974Swpaul return(0); 150050974Swpaul} 150150974Swpaul 150250974Swpaul/* 150350974Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 150450974Swpaul * the higher level protocols. 150550974Swpaul */ 1506102334Salfredstatic void 1507102334Salfredsis_rxeof(sc) 150850974Swpaul struct sis_softc *sc; 150950974Swpaul{ 151050974Swpaul struct mbuf *m; 151150974Swpaul struct ifnet *ifp; 151250974Swpaul struct sis_desc *cur_rx; 151350974Swpaul int i, total_len = 0; 151450974Swpaul u_int32_t rxstat; 151550974Swpaul 151650974Swpaul ifp = &sc->arpcom.ac_if; 151750974Swpaul i = sc->sis_cdata.sis_rx_prod; 151850974Swpaul 151981713Swpaul while(SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) { 152050974Swpaul 152187902Sluigi#ifdef DEVICE_POLLING 1522102052Ssobomax if (ifp->if_flags & IFF_POLLING) { 152387902Sluigi if (sc->rxcycles <= 0) 152487902Sluigi break; 152587902Sluigi sc->rxcycles--; 152687902Sluigi } 152787902Sluigi#endif /* DEVICE_POLLING */ 152881713Swpaul cur_rx = &sc->sis_ldata.sis_rx_list[i]; 152950974Swpaul rxstat = cur_rx->sis_rxstat; 153081713Swpaul bus_dmamap_sync(sc->sis_tag, 153181713Swpaul cur_rx->sis_map, BUS_DMASYNC_POSTWRITE); 153281713Swpaul bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map); 153381713Swpaul bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map); 153450974Swpaul m = cur_rx->sis_mbuf; 153550974Swpaul cur_rx->sis_mbuf = NULL; 153650974Swpaul total_len = SIS_RXBYTES(cur_rx); 153750974Swpaul SIS_INC(i, SIS_RX_LIST_CNT); 153850974Swpaul 153950974Swpaul /* 154050974Swpaul * If an error occurs, update stats, clear the 154150974Swpaul * status word and leave the mbuf cluster in place: 154250974Swpaul * it should simply get re-used next time this descriptor 154350974Swpaul * comes up in the ring. 154450974Swpaul */ 154550974Swpaul if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 154650974Swpaul ifp->if_ierrors++; 154750974Swpaul if (rxstat & SIS_RXSTAT_COLL) 154850974Swpaul ifp->if_collisions++; 154950974Swpaul sis_newbuf(sc, cur_rx, m); 155050974Swpaul continue; 155150974Swpaul } 155250974Swpaul 155350974Swpaul /* No errors; receive the packet. */ 155487059Sluigi#ifdef __i386__ 155587059Sluigi /* 155687059Sluigi * On the x86 we do not have alignment problems, so try to 155787059Sluigi * allocate a new buffer for the receive ring, and pass up 155887059Sluigi * the one where the packet is already, saving the expensive 155987059Sluigi * copy done in m_devget(). 156087059Sluigi * If we are on an architecture with alignment problems, or 156187059Sluigi * if the allocation fails, then use m_devget and leave the 156287059Sluigi * existing buffer in the receive ring. 156387059Sluigi */ 1564101464Sluigi if (sis_newbuf(sc, cur_rx, NULL) == 0) 156587059Sluigi m->m_pkthdr.len = m->m_len = total_len; 1566101464Sluigi else 156787059Sluigi#endif 156887059Sluigi { 156987059Sluigi struct mbuf *m0; 157087059Sluigi m0 = m_devget(mtod(m, char *), total_len, 157187059Sluigi ETHER_ALIGN, ifp, NULL); 157287059Sluigi sis_newbuf(sc, cur_rx, m); 157387059Sluigi if (m0 == NULL) { 157487059Sluigi ifp->if_ierrors++; 157587059Sluigi continue; 157687059Sluigi } 157787059Sluigi m = m0; 157850974Swpaul } 157950974Swpaul 158050974Swpaul ifp->if_ipackets++; 1581106936Ssam m->m_pkthdr.rcvif = ifp; 1582106936Ssam 1583106936Ssam (*ifp->if_input)(ifp, m); 158450974Swpaul } 158550974Swpaul 158650974Swpaul sc->sis_cdata.sis_rx_prod = i; 158750974Swpaul 158850974Swpaul return; 158950974Swpaul} 159050974Swpaul 1591105219Sphkstatic void 1592102334Salfredsis_rxeoc(sc) 159350974Swpaul struct sis_softc *sc; 159450974Swpaul{ 159550974Swpaul sis_rxeof(sc); 159650974Swpaul sis_init(sc); 159750974Swpaul return; 159850974Swpaul} 159950974Swpaul 160050974Swpaul/* 160150974Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 160250974Swpaul * the list buffers. 160350974Swpaul */ 160450974Swpaul 1605102334Salfredstatic void 1606102334Salfredsis_txeof(sc) 160750974Swpaul struct sis_softc *sc; 160850974Swpaul{ 160950974Swpaul struct ifnet *ifp; 161050974Swpaul u_int32_t idx; 161150974Swpaul 161250974Swpaul ifp = &sc->arpcom.ac_if; 161350974Swpaul 161450974Swpaul /* 161550974Swpaul * Go through our tx list and free mbufs for those 161650974Swpaul * frames that have been transmitted. 161750974Swpaul */ 161899163Sluigi for (idx = sc->sis_cdata.sis_tx_cons; sc->sis_cdata.sis_tx_cnt > 0; 161999163Sluigi sc->sis_cdata.sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) { 162099163Sluigi struct sis_desc *cur_tx = &sc->sis_ldata.sis_tx_list[idx]; 162150974Swpaul 162250974Swpaul if (SIS_OWNDESC(cur_tx)) 162350974Swpaul break; 162450974Swpaul 162599163Sluigi if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) 162650974Swpaul continue; 162750974Swpaul 162850974Swpaul if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 162950974Swpaul ifp->if_oerrors++; 163050974Swpaul if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 163150974Swpaul ifp->if_collisions++; 163250974Swpaul if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 163350974Swpaul ifp->if_collisions++; 163450974Swpaul } 163550974Swpaul 163650974Swpaul ifp->if_collisions += 163750974Swpaul (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 163850974Swpaul 163950974Swpaul ifp->if_opackets++; 164050974Swpaul if (cur_tx->sis_mbuf != NULL) { 164150974Swpaul m_freem(cur_tx->sis_mbuf); 164250974Swpaul cur_tx->sis_mbuf = NULL; 164381713Swpaul bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map); 164481713Swpaul bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map); 164550974Swpaul } 164699163Sluigi } 164750974Swpaul 164899163Sluigi if (idx != sc->sis_cdata.sis_tx_cons) { 164999163Sluigi /* we freed up some buffers */ 165099163Sluigi sc->sis_cdata.sis_tx_cons = idx; 165199163Sluigi ifp->if_flags &= ~IFF_OACTIVE; 165250974Swpaul } 165350974Swpaul 165499163Sluigi ifp->if_timer = (sc->sis_cdata.sis_tx_cnt == 0) ? 0 : 5; 165550974Swpaul 165650974Swpaul return; 165750974Swpaul} 165850974Swpaul 1659102334Salfredstatic void 1660102334Salfredsis_tick(xsc) 166150974Swpaul void *xsc; 166250974Swpaul{ 166350974Swpaul struct sis_softc *sc; 166450974Swpaul struct mii_data *mii; 166564963Swpaul struct ifnet *ifp; 166650974Swpaul 166750974Swpaul sc = xsc; 166867087Swpaul SIS_LOCK(sc); 166964963Swpaul ifp = &sc->arpcom.ac_if; 167064963Swpaul 167150974Swpaul mii = device_get_softc(sc->sis_miibus); 167250974Swpaul mii_tick(mii); 167364963Swpaul 167484147Sjlemon if (!sc->sis_link && mii->mii_media_status & IFM_ACTIVE && 167584147Sjlemon IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 167684147Sjlemon sc->sis_link++; 167784147Sjlemon if (ifp->if_snd.ifq_head != NULL) 167884147Sjlemon sis_start(ifp); 167964963Swpaul } 168064963Swpaul 168151031Swpaul sc->sis_stat_ch = timeout(sis_tick, sc, hz); 168250974Swpaul 168367087Swpaul SIS_UNLOCK(sc); 168450974Swpaul 168550974Swpaul return; 168650974Swpaul} 168750974Swpaul 168887902Sluigi#ifdef DEVICE_POLLING 168987902Sluigistatic poll_handler_t sis_poll; 169087902Sluigi 169187902Sluigistatic void 169287902Sluigisis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 169387902Sluigi{ 169487973Speter struct sis_softc *sc = ifp->if_softc; 169587973Speter 169687902Sluigi SIS_LOCK(sc); 169787902Sluigi if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 169887902Sluigi CSR_WRITE_4(sc, SIS_IER, 1); 169987902Sluigi goto done; 170087902Sluigi } 170187902Sluigi 170287902Sluigi /* 170387902Sluigi * On the sis, reading the status register also clears it. 170487902Sluigi * So before returning to intr mode we must make sure that all 170587902Sluigi * possible pending sources of interrupts have been served. 170687902Sluigi * In practice this means run to completion the *eof routines, 170787902Sluigi * and then call the interrupt routine 170887902Sluigi */ 170987902Sluigi sc->rxcycles = count; 171087902Sluigi sis_rxeof(sc); 171187902Sluigi sis_txeof(sc); 171287902Sluigi if (ifp->if_snd.ifq_head != NULL) 171387902Sluigi sis_start(ifp); 171487902Sluigi 171587902Sluigi if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 171687902Sluigi u_int32_t status; 171787902Sluigi 171887902Sluigi /* Reading the ISR register clears all interrupts. */ 171987902Sluigi status = CSR_READ_4(sc, SIS_ISR); 172087902Sluigi 172187902Sluigi if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 172287902Sluigi sis_rxeoc(sc); 172387902Sluigi 172487902Sluigi if (status & (SIS_ISR_RX_IDLE)) 172587902Sluigi SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 172687902Sluigi 172787902Sluigi if (status & SIS_ISR_SYSERR) { 172887902Sluigi sis_reset(sc); 172987902Sluigi sis_init(sc); 173087902Sluigi } 173187902Sluigi } 173287902Sluigidone: 173387902Sluigi SIS_UNLOCK(sc); 173487902Sluigi return; 173587902Sluigi} 173687902Sluigi#endif /* DEVICE_POLLING */ 173787902Sluigi 1738102334Salfredstatic void 1739102334Salfredsis_intr(arg) 174050974Swpaul void *arg; 174150974Swpaul{ 174250974Swpaul struct sis_softc *sc; 174350974Swpaul struct ifnet *ifp; 174450974Swpaul u_int32_t status; 174550974Swpaul 174650974Swpaul sc = arg; 174750974Swpaul ifp = &sc->arpcom.ac_if; 174850974Swpaul 174986984Sluigi SIS_LOCK(sc); 175087902Sluigi#ifdef DEVICE_POLLING 1751102052Ssobomax if (ifp->if_flags & IFF_POLLING) 175287902Sluigi goto done; 175387902Sluigi if (ether_poll_register(sis_poll, ifp)) { /* ok, disable interrupts */ 175487902Sluigi CSR_WRITE_4(sc, SIS_IER, 0); 175587902Sluigi goto done; 175687902Sluigi } 175787902Sluigi#endif /* DEVICE_POLLING */ 175887902Sluigi 175950974Swpaul /* Supress unwanted interrupts */ 176050974Swpaul if (!(ifp->if_flags & IFF_UP)) { 176150974Swpaul sis_stop(sc); 176286984Sluigi goto done; 176350974Swpaul } 176450974Swpaul 176550974Swpaul /* Disable interrupts. */ 176650974Swpaul CSR_WRITE_4(sc, SIS_IER, 0); 176750974Swpaul 176850974Swpaul for (;;) { 176950974Swpaul /* Reading the ISR register clears all interrupts. */ 177050974Swpaul status = CSR_READ_4(sc, SIS_ISR); 177150974Swpaul 177250974Swpaul if ((status & SIS_INTRS) == 0) 177350974Swpaul break; 177450974Swpaul 177586984Sluigi if (status & 177686984Sluigi (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | 177786984Sluigi SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) ) 177850974Swpaul sis_txeof(sc); 177950974Swpaul 178086984Sluigi if (status & (SIS_ISR_RX_DESC_OK|SIS_ISR_RX_OK|SIS_ISR_RX_IDLE)) 178150974Swpaul sis_rxeof(sc); 178250974Swpaul 178386984Sluigi if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW)) 178450974Swpaul sis_rxeoc(sc); 178550974Swpaul 178686984Sluigi if (status & (SIS_ISR_RX_IDLE)) 178786984Sluigi SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 178886984Sluigi 178950974Swpaul if (status & SIS_ISR_SYSERR) { 179050974Swpaul sis_reset(sc); 179150974Swpaul sis_init(sc); 179250974Swpaul } 179350974Swpaul } 179450974Swpaul 179550974Swpaul /* Re-enable interrupts. */ 179650974Swpaul CSR_WRITE_4(sc, SIS_IER, 1); 179750974Swpaul 179850974Swpaul if (ifp->if_snd.ifq_head != NULL) 179950974Swpaul sis_start(ifp); 180086984Sluigidone: 180167087Swpaul SIS_UNLOCK(sc); 180267087Swpaul 180350974Swpaul return; 180450974Swpaul} 180550974Swpaul 180650974Swpaul/* 180750974Swpaul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 180850974Swpaul * pointers to the fragment pointers. 180950974Swpaul */ 1810102334Salfredstatic int 1811102334Salfredsis_encap(sc, m_head, txidx) 181250974Swpaul struct sis_softc *sc; 181350974Swpaul struct mbuf *m_head; 181450974Swpaul u_int32_t *txidx; 181550974Swpaul{ 181650974Swpaul struct sis_desc *f = NULL; 181750974Swpaul struct mbuf *m; 181850974Swpaul int frag, cur, cnt = 0; 181950974Swpaul 182050974Swpaul /* 182150974Swpaul * Start packing the mbufs in this chain into 182250974Swpaul * the fragment pointers. Stop when we run out 182350974Swpaul * of fragments or hit the end of the mbuf chain. 182450974Swpaul */ 182550974Swpaul m = m_head; 182650974Swpaul cur = frag = *txidx; 182750974Swpaul 182850974Swpaul for (m = m_head; m != NULL; m = m->m_next) { 182950974Swpaul if (m->m_len != 0) { 183051042Swpaul if ((SIS_TX_LIST_CNT - 183150974Swpaul (sc->sis_cdata.sis_tx_cnt + cnt)) < 2) 183250974Swpaul return(ENOBUFS); 183381713Swpaul f = &sc->sis_ldata.sis_tx_list[frag]; 183450974Swpaul f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; 183581713Swpaul bus_dmamap_create(sc->sis_tag, 0, &f->sis_map); 183681713Swpaul bus_dmamap_load(sc->sis_tag, f->sis_map, 183781713Swpaul mtod(m, void *), m->m_len, 183881713Swpaul sis_dma_map_desc_ptr, f, 0); 183981713Swpaul bus_dmamap_sync(sc->sis_tag, 184081713Swpaul f->sis_map, BUS_DMASYNC_PREREAD); 184150974Swpaul if (cnt != 0) 184250974Swpaul f->sis_ctl |= SIS_CMDSTS_OWN; 184350974Swpaul cur = frag; 184450974Swpaul SIS_INC(frag, SIS_TX_LIST_CNT); 184550974Swpaul cnt++; 184650974Swpaul } 184750974Swpaul } 184850974Swpaul 184950974Swpaul if (m != NULL) 185050974Swpaul return(ENOBUFS); 185150974Swpaul 185281713Swpaul sc->sis_ldata.sis_tx_list[cur].sis_mbuf = m_head; 185381713Swpaul sc->sis_ldata.sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 185481713Swpaul sc->sis_ldata.sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 185550974Swpaul sc->sis_cdata.sis_tx_cnt += cnt; 185650974Swpaul *txidx = frag; 185750974Swpaul 185850974Swpaul return(0); 185950974Swpaul} 186050974Swpaul 186150974Swpaul/* 186250974Swpaul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 186350974Swpaul * to the mbuf data regions directly in the transmit lists. We also save a 186450974Swpaul * copy of the pointers since the transmit list fragment pointers are 186550974Swpaul * physical addresses. 186650974Swpaul */ 186750974Swpaul 1868102334Salfredstatic void 1869102334Salfredsis_start(ifp) 187050974Swpaul struct ifnet *ifp; 187150974Swpaul{ 187250974Swpaul struct sis_softc *sc; 187350974Swpaul struct mbuf *m_head = NULL; 187450974Swpaul u_int32_t idx; 187550974Swpaul 187650974Swpaul sc = ifp->if_softc; 187767087Swpaul SIS_LOCK(sc); 187850974Swpaul 187967087Swpaul if (!sc->sis_link) { 188067087Swpaul SIS_UNLOCK(sc); 188164963Swpaul return; 188267087Swpaul } 188364963Swpaul 188450974Swpaul idx = sc->sis_cdata.sis_tx_prod; 188550974Swpaul 188667087Swpaul if (ifp->if_flags & IFF_OACTIVE) { 188767087Swpaul SIS_UNLOCK(sc); 188850974Swpaul return; 188967087Swpaul } 189050974Swpaul 189181713Swpaul while(sc->sis_ldata.sis_tx_list[idx].sis_mbuf == NULL) { 189250974Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 189350974Swpaul if (m_head == NULL) 189450974Swpaul break; 189550974Swpaul 189650974Swpaul if (sis_encap(sc, m_head, &idx)) { 189750974Swpaul IF_PREPEND(&ifp->if_snd, m_head); 189850974Swpaul ifp->if_flags |= IFF_OACTIVE; 189950974Swpaul break; 190050974Swpaul } 190150974Swpaul 190250974Swpaul /* 190350974Swpaul * If there's a BPF listener, bounce a copy of this frame 190450974Swpaul * to him. 190550974Swpaul */ 1906106936Ssam BPF_MTAP(ifp, m_head); 190751583Swpaul 190850974Swpaul } 190950974Swpaul 191050974Swpaul /* Transmit */ 191150974Swpaul sc->sis_cdata.sis_tx_prod = idx; 191250974Swpaul SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 191350974Swpaul 191450974Swpaul /* 191550974Swpaul * Set a timeout in case the chip goes out to lunch. 191650974Swpaul */ 191750974Swpaul ifp->if_timer = 5; 191850974Swpaul 191967087Swpaul SIS_UNLOCK(sc); 192067087Swpaul 192150974Swpaul return; 192250974Swpaul} 192350974Swpaul 1924102334Salfredstatic void 1925102334Salfredsis_init(xsc) 192650974Swpaul void *xsc; 192750974Swpaul{ 192850974Swpaul struct sis_softc *sc = xsc; 192950974Swpaul struct ifnet *ifp = &sc->arpcom.ac_if; 193050974Swpaul struct mii_data *mii; 193150974Swpaul 193267087Swpaul SIS_LOCK(sc); 193350974Swpaul 193450974Swpaul /* 193550974Swpaul * Cancel pending I/O and free all RX/TX buffers. 193650974Swpaul */ 193750974Swpaul sis_stop(sc); 193850974Swpaul 193950974Swpaul mii = device_get_softc(sc->sis_miibus); 194050974Swpaul 194150974Swpaul /* Set MAC address */ 194262672Swpaul if (sc->sis_type == SIS_TYPE_83815) { 194362672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 194462672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 194562672Swpaul ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 194662672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 194762672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 194862672Swpaul ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 194962672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 195062672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 195162672Swpaul ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 195262672Swpaul } else { 195362672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 195462672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 195562672Swpaul ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 195662672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 195762672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 195862672Swpaul ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 195962672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 196062672Swpaul CSR_WRITE_4(sc, SIS_RXFILT_DATA, 196162672Swpaul ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 196262672Swpaul } 196350974Swpaul 196450974Swpaul /* Init circular RX list. */ 196550974Swpaul if (sis_list_rx_init(sc) == ENOBUFS) { 196650974Swpaul printf("sis%d: initialization failed: no " 196750974Swpaul "memory for rx buffers\n", sc->sis_unit); 196850974Swpaul sis_stop(sc); 196967087Swpaul SIS_UNLOCK(sc); 197050974Swpaul return; 197150974Swpaul } 197250974Swpaul 197350974Swpaul /* 197450974Swpaul * Init tx descriptors. 197550974Swpaul */ 197650974Swpaul sis_list_tx_init(sc); 197750974Swpaul 197862672Swpaul /* 197962672Swpaul * For the NatSemi chip, we have to explicitly enable the 198062672Swpaul * reception of ARP frames, as well as turn on the 'perfect 198162672Swpaul * match' filter where we store the station address, otherwise 198262672Swpaul * we won't receive unicasts meant for this host. 198362672Swpaul */ 198462672Swpaul if (sc->sis_type == SIS_TYPE_83815) { 198562672Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 198662672Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 198762672Swpaul } 198862672Swpaul 198950974Swpaul /* If we want promiscuous mode, set the allframes bit. */ 199050974Swpaul if (ifp->if_flags & IFF_PROMISC) { 199150974Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 199250974Swpaul } else { 199350974Swpaul SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 199450974Swpaul } 199550974Swpaul 199650974Swpaul /* 199750974Swpaul * Set the capture broadcast bit to capture broadcast frames. 199850974Swpaul */ 199950974Swpaul if (ifp->if_flags & IFF_BROADCAST) { 200050974Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 200150974Swpaul } else { 200250974Swpaul SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 200350974Swpaul } 200450974Swpaul 200550974Swpaul /* 200650974Swpaul * Load the multicast filter. 200750974Swpaul */ 200862672Swpaul if (sc->sis_type == SIS_TYPE_83815) 200962672Swpaul sis_setmulti_ns(sc); 201062672Swpaul else 201162672Swpaul sis_setmulti_sis(sc); 201250974Swpaul 201350974Swpaul /* Turn the receive filter on */ 201450974Swpaul SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 201550974Swpaul 201650974Swpaul /* 201750974Swpaul * Load the address of the RX and TX lists. 201850974Swpaul */ 201981713Swpaul CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_cdata.sis_rx_paddr); 202081713Swpaul CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_cdata.sis_tx_paddr); 202150974Swpaul 2022109059Smbr /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of 2023109059Smbr * the PCI bus. When this bit is set, the Max DMA Burst Size 2024109059Smbr * for TX/RX DMA should be no larger than 16 double words. 2025109059Smbr */ 2026109059Smbr if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) { 2027109059Smbr CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); 2028109059Smbr } else { 2029109059Smbr CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); 2030109059Smbr } 203164963Swpaul 2032109059Smbr 203387390Sjhay /* Accept Long Packets for VLAN support */ 203487390Sjhay SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 203587390Sjhay 203650974Swpaul /* Set TX configuration */ 203764963Swpaul if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 203864963Swpaul CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 203964963Swpaul } else { 204064963Swpaul CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 204164963Swpaul } 204250974Swpaul 204364963Swpaul /* Set full/half duplex mode. */ 204464963Swpaul if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 204564963Swpaul SIS_SETBIT(sc, SIS_TX_CFG, 204664963Swpaul (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 204764963Swpaul SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 204864963Swpaul } else { 204964963Swpaul SIS_CLRBIT(sc, SIS_TX_CFG, 205064963Swpaul (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 205164963Swpaul SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 205264963Swpaul } 205364963Swpaul 205450974Swpaul /* 205550974Swpaul * Enable interrupts. 205650974Swpaul */ 205750974Swpaul CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 205887902Sluigi#ifdef DEVICE_POLLING 205987902Sluigi /* 206087902Sluigi * ... only enable interrupts if we are not polling, make sure 206187902Sluigi * they are off otherwise. 206287902Sluigi */ 2063102052Ssobomax if (ifp->if_flags & IFF_POLLING) 206487902Sluigi CSR_WRITE_4(sc, SIS_IER, 0); 206587902Sluigi else 206687902Sluigi#endif /* DEVICE_POLLING */ 206750974Swpaul CSR_WRITE_4(sc, SIS_IER, 1); 206850974Swpaul 206950974Swpaul /* Enable receiver and transmitter. */ 207050974Swpaul SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 207150974Swpaul SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 207250974Swpaul 207364963Swpaul#ifdef notdef 207450974Swpaul mii_mediachg(mii); 207564963Swpaul#endif 207650974Swpaul 207764963Swpaul /* 207864963Swpaul * Page 75 of the DP83815 manual recommends the 207964963Swpaul * following register settings "for optimum 208064963Swpaul * performance." Note however that at least three 208164963Swpaul * of the registers are listed as "reserved" in 208264963Swpaul * the register map, so who knows what they do. 208364963Swpaul */ 208464963Swpaul if (sc->sis_type == SIS_TYPE_83815) { 208564963Swpaul CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 208664963Swpaul CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 208764963Swpaul CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 208864963Swpaul CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 208964963Swpaul CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 209064963Swpaul } 209164963Swpaul 209250974Swpaul ifp->if_flags |= IFF_RUNNING; 209350974Swpaul ifp->if_flags &= ~IFF_OACTIVE; 209450974Swpaul 209550974Swpaul sc->sis_stat_ch = timeout(sis_tick, sc, hz); 209650974Swpaul 209767087Swpaul SIS_UNLOCK(sc); 209867087Swpaul 209950974Swpaul return; 210050974Swpaul} 210150974Swpaul 210250974Swpaul/* 210350974Swpaul * Set media options. 210450974Swpaul */ 2105102334Salfredstatic int 2106102334Salfredsis_ifmedia_upd(ifp) 210750974Swpaul struct ifnet *ifp; 210850974Swpaul{ 210950974Swpaul struct sis_softc *sc; 211064963Swpaul struct mii_data *mii; 211150974Swpaul 211250974Swpaul sc = ifp->if_softc; 211350974Swpaul 211464963Swpaul mii = device_get_softc(sc->sis_miibus); 211564963Swpaul sc->sis_link = 0; 211664963Swpaul if (mii->mii_instance) { 211764963Swpaul struct mii_softc *miisc; 211872012Sphk LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 211964963Swpaul mii_phy_reset(miisc); 212064963Swpaul } 212164963Swpaul mii_mediachg(mii); 212250974Swpaul 212350974Swpaul return(0); 212450974Swpaul} 212550974Swpaul 212650974Swpaul/* 212750974Swpaul * Report current media status. 212850974Swpaul */ 2129102334Salfredstatic void 2130102334Salfredsis_ifmedia_sts(ifp, ifmr) 213150974Swpaul struct ifnet *ifp; 213250974Swpaul struct ifmediareq *ifmr; 213350974Swpaul{ 213450974Swpaul struct sis_softc *sc; 213550974Swpaul struct mii_data *mii; 213650974Swpaul 213750974Swpaul sc = ifp->if_softc; 213850974Swpaul 213950974Swpaul mii = device_get_softc(sc->sis_miibus); 214050974Swpaul mii_pollstat(mii); 214150974Swpaul ifmr->ifm_active = mii->mii_media_active; 214250974Swpaul ifmr->ifm_status = mii->mii_media_status; 214350974Swpaul 214450974Swpaul return; 214550974Swpaul} 214650974Swpaul 2147102334Salfredstatic int 2148102334Salfredsis_ioctl(ifp, command, data) 214950974Swpaul struct ifnet *ifp; 215050974Swpaul u_long command; 215150974Swpaul caddr_t data; 215250974Swpaul{ 215350974Swpaul struct sis_softc *sc = ifp->if_softc; 215450974Swpaul struct ifreq *ifr = (struct ifreq *) data; 215550974Swpaul struct mii_data *mii; 215667087Swpaul int error = 0; 215750974Swpaul 215850974Swpaul switch(command) { 215950974Swpaul case SIOCSIFFLAGS: 216050974Swpaul if (ifp->if_flags & IFF_UP) { 216150974Swpaul sis_init(sc); 216250974Swpaul } else { 216350974Swpaul if (ifp->if_flags & IFF_RUNNING) 216450974Swpaul sis_stop(sc); 216550974Swpaul } 216650974Swpaul error = 0; 216750974Swpaul break; 216850974Swpaul case SIOCADDMULTI: 216950974Swpaul case SIOCDELMULTI: 217081713Swpaul SIS_LOCK(sc); 217162672Swpaul if (sc->sis_type == SIS_TYPE_83815) 217262672Swpaul sis_setmulti_ns(sc); 217362672Swpaul else 217462672Swpaul sis_setmulti_sis(sc); 217581713Swpaul SIS_UNLOCK(sc); 217650974Swpaul error = 0; 217750974Swpaul break; 217850974Swpaul case SIOCGIFMEDIA: 217950974Swpaul case SIOCSIFMEDIA: 218050974Swpaul mii = device_get_softc(sc->sis_miibus); 218181713Swpaul SIS_LOCK(sc); 218250974Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 218381713Swpaul SIS_UNLOCK(sc); 218450974Swpaul break; 218550974Swpaul default: 2186106936Ssam error = ether_ioctl(ifp, command, data); 218750974Swpaul break; 218850974Swpaul } 218950974Swpaul 219050974Swpaul return(error); 219150974Swpaul} 219250974Swpaul 2193102334Salfredstatic void 2194102334Salfredsis_watchdog(ifp) 219550974Swpaul struct ifnet *ifp; 219650974Swpaul{ 219750974Swpaul struct sis_softc *sc; 219850974Swpaul 219950974Swpaul sc = ifp->if_softc; 220050974Swpaul 220167087Swpaul SIS_LOCK(sc); 220267087Swpaul 220350974Swpaul ifp->if_oerrors++; 220450974Swpaul printf("sis%d: watchdog timeout\n", sc->sis_unit); 220550974Swpaul 220650974Swpaul sis_stop(sc); 220750974Swpaul sis_reset(sc); 220850974Swpaul sis_init(sc); 220950974Swpaul 221050974Swpaul if (ifp->if_snd.ifq_head != NULL) 221150974Swpaul sis_start(ifp); 221250974Swpaul 221367087Swpaul SIS_UNLOCK(sc); 221467087Swpaul 221550974Swpaul return; 221650974Swpaul} 221750974Swpaul 221850974Swpaul/* 221950974Swpaul * Stop the adapter and free any mbufs allocated to the 222050974Swpaul * RX and TX lists. 222150974Swpaul */ 2222102334Salfredstatic void 2223102334Salfredsis_stop(sc) 222450974Swpaul struct sis_softc *sc; 222550974Swpaul{ 222650974Swpaul register int i; 222750974Swpaul struct ifnet *ifp; 222850974Swpaul 222967087Swpaul SIS_LOCK(sc); 223050974Swpaul ifp = &sc->arpcom.ac_if; 223150974Swpaul ifp->if_timer = 0; 223250974Swpaul 223350974Swpaul untimeout(sis_tick, sc, sc->sis_stat_ch); 223487472Speter 223587472Speter ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 223687902Sluigi#ifdef DEVICE_POLLING 223787902Sluigi ether_poll_deregister(ifp); 223887902Sluigi#endif 223950974Swpaul CSR_WRITE_4(sc, SIS_IER, 0); 224050974Swpaul CSR_WRITE_4(sc, SIS_IMR, 0); 224150974Swpaul SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 224250974Swpaul DELAY(1000); 224350974Swpaul CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 224450974Swpaul CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 224550974Swpaul 224664963Swpaul sc->sis_link = 0; 224764963Swpaul 224850974Swpaul /* 224950974Swpaul * Free data in the RX lists. 225050974Swpaul */ 225150974Swpaul for (i = 0; i < SIS_RX_LIST_CNT; i++) { 225281713Swpaul if (sc->sis_ldata.sis_rx_list[i].sis_mbuf != NULL) { 225381713Swpaul bus_dmamap_unload(sc->sis_tag, 225481713Swpaul sc->sis_ldata.sis_rx_list[i].sis_map); 225581713Swpaul bus_dmamap_destroy(sc->sis_tag, 225681713Swpaul sc->sis_ldata.sis_rx_list[i].sis_map); 225781713Swpaul m_freem(sc->sis_ldata.sis_rx_list[i].sis_mbuf); 225881713Swpaul sc->sis_ldata.sis_rx_list[i].sis_mbuf = NULL; 225950974Swpaul } 226050974Swpaul } 226181713Swpaul bzero(sc->sis_ldata.sis_rx_list, 226281713Swpaul sizeof(sc->sis_ldata.sis_rx_list)); 226350974Swpaul 226450974Swpaul /* 226550974Swpaul * Free the TX list buffers. 226650974Swpaul */ 226750974Swpaul for (i = 0; i < SIS_TX_LIST_CNT; i++) { 226881713Swpaul if (sc->sis_ldata.sis_tx_list[i].sis_mbuf != NULL) { 226981713Swpaul bus_dmamap_unload(sc->sis_tag, 227081713Swpaul sc->sis_ldata.sis_tx_list[i].sis_map); 227181713Swpaul bus_dmamap_destroy(sc->sis_tag, 227281713Swpaul sc->sis_ldata.sis_tx_list[i].sis_map); 227381713Swpaul m_freem(sc->sis_ldata.sis_tx_list[i].sis_mbuf); 227481713Swpaul sc->sis_ldata.sis_tx_list[i].sis_mbuf = NULL; 227550974Swpaul } 227650974Swpaul } 227750974Swpaul 227881713Swpaul bzero(sc->sis_ldata.sis_tx_list, 227981713Swpaul sizeof(sc->sis_ldata.sis_tx_list)); 228050974Swpaul 228167087Swpaul SIS_UNLOCK(sc); 228267087Swpaul 228350974Swpaul return; 228450974Swpaul} 228550974Swpaul 228650974Swpaul/* 228750974Swpaul * Stop all chip I/O so that the kernel's probe routines don't 228850974Swpaul * get confused by errant DMAs when rebooting. 228950974Swpaul */ 2290102334Salfredstatic void 2291102334Salfredsis_shutdown(dev) 229250974Swpaul device_t dev; 229350974Swpaul{ 229450974Swpaul struct sis_softc *sc; 229550974Swpaul 229650974Swpaul sc = device_get_softc(dev); 229767087Swpaul SIS_LOCK(sc); 229850974Swpaul sis_reset(sc); 229950974Swpaul sis_stop(sc); 230067087Swpaul SIS_UNLOCK(sc); 230150974Swpaul 230250974Swpaul return; 230350974Swpaul} 2304