if_sis.c revision 109061
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_sis.c 109061 2003-01-10 08:16:03Z mbr $ 33 */ 34 35/* 36 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 37 * available from http://www.sis.com.tw. 38 * 39 * This driver also supports the NatSemi DP83815. Datasheets are 40 * available from http://www.national.com. 41 * 42 * Written by Bill Paul <wpaul@ee.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47/* 48 * The SiS 900 is a fairly simple chip. It uses bus master DMA with 49 * simple TX and RX descriptors of 3 longwords in size. The receiver 50 * has a single perfect filter entry for the station address and a 51 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 52 * transceiver while the 7016 requires an external transceiver chip. 53 * Both chips offer the standard bit-bang MII interface as well as 54 * an enchanced PHY interface which simplifies accessing MII registers. 55 * 56 * The only downside to this chipset is that RX descriptors must be 57 * longword aligned. 58 */ 59 60#include <sys/param.h> 61#include <sys/systm.h> 62#include <sys/sockio.h> 63#include <sys/mbuf.h> 64#include <sys/malloc.h> 65#include <sys/kernel.h> 66#include <sys/socket.h> 67#include <sys/sysctl.h> 68 69#include <net/if.h> 70#include <net/if_arp.h> 71#include <net/ethernet.h> 72#include <net/if_dl.h> 73#include <net/if_media.h> 74#include <net/if_types.h> 75#include <net/if_vlan_var.h> 76 77#include <net/bpf.h> 78 79#include <machine/bus_pio.h> 80#include <machine/bus_memio.h> 81#include <machine/bus.h> 82#include <machine/resource.h> 83#include <sys/bus.h> 84#include <sys/rman.h> 85 86#include <dev/mii/mii.h> 87#include <dev/mii/miivar.h> 88 89#include <pci/pcireg.h> 90#include <pci/pcivar.h> 91 92#define SIS_USEIOSPACE 93 94#include <pci/if_sisreg.h> 95 96MODULE_DEPEND(sis, miibus, 1, 1, 1); 97 98/* "controller miibus0" required. See GENERIC if you get errors here. */ 99#include "miibus_if.h" 100 101#ifndef lint 102static const char rcsid[] = 103 "$FreeBSD: head/sys/pci/if_sis.c 109061 2003-01-10 08:16:03Z mbr $"; 104#endif 105 106/* 107 * Various supported device vendors/types and their names. 108 */ 109static struct sis_type sis_devs[] = { 110 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 111 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 112 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP83815 10/100BaseTX" }, 113 { 0, 0, NULL } 114}; 115 116static int sis_probe (device_t); 117static int sis_attach (device_t); 118static int sis_detach (device_t); 119 120static int sis_newbuf (struct sis_softc *, 121 struct sis_desc *, struct mbuf *); 122static int sis_encap (struct sis_softc *, 123 struct mbuf *, u_int32_t *); 124static void sis_rxeof (struct sis_softc *); 125static void sis_rxeoc (struct sis_softc *); 126static void sis_txeof (struct sis_softc *); 127static void sis_intr (void *); 128static void sis_tick (void *); 129static void sis_start (struct ifnet *); 130static int sis_ioctl (struct ifnet *, u_long, caddr_t); 131static void sis_init (void *); 132static void sis_stop (struct sis_softc *); 133static void sis_watchdog (struct ifnet *); 134static void sis_shutdown (device_t); 135static int sis_ifmedia_upd (struct ifnet *); 136static void sis_ifmedia_sts (struct ifnet *, struct ifmediareq *); 137 138static u_int16_t sis_reverse (u_int16_t); 139static void sis_delay (struct sis_softc *); 140static void sis_eeprom_idle (struct sis_softc *); 141static void sis_eeprom_putbyte (struct sis_softc *, int); 142static void sis_eeprom_getword (struct sis_softc *, int, u_int16_t *); 143static void sis_read_eeprom (struct sis_softc *, caddr_t, int, int, int); 144#ifdef __i386__ 145static void sis_read_cmos (struct sis_softc *, device_t, caddr_t, 146 int, int); 147static void sis_read_mac (struct sis_softc *, device_t, caddr_t); 148static device_t sis_find_bridge (device_t); 149#endif 150 151static void sis_mii_sync (struct sis_softc *); 152static void sis_mii_send (struct sis_softc *, u_int32_t, int); 153static int sis_mii_readreg (struct sis_softc *, struct sis_mii_frame *); 154static int sis_mii_writereg (struct sis_softc *, struct sis_mii_frame *); 155static int sis_miibus_readreg (device_t, int, int); 156static int sis_miibus_writereg (device_t, int, int, int); 157static void sis_miibus_statchg (device_t); 158 159static void sis_setmulti_sis (struct sis_softc *); 160static void sis_setmulti_ns (struct sis_softc *); 161static u_int32_t sis_crc (struct sis_softc *, caddr_t); 162static void sis_reset (struct sis_softc *); 163static int sis_list_rx_init (struct sis_softc *); 164static int sis_list_tx_init (struct sis_softc *); 165 166static void sis_dma_map_desc_ptr (void *, bus_dma_segment_t *, int, int); 167static void sis_dma_map_desc_next (void *, bus_dma_segment_t *, int, int); 168static void sis_dma_map_ring (void *, bus_dma_segment_t *, int, int); 169#ifdef SIS_USEIOSPACE 170#define SIS_RES SYS_RES_IOPORT 171#define SIS_RID SIS_PCI_LOIO 172#else 173#define SIS_RES SYS_RES_MEMORY 174#define SIS_RID SIS_PCI_LOMEM 175#endif 176 177static device_method_t sis_methods[] = { 178 /* Device interface */ 179 DEVMETHOD(device_probe, sis_probe), 180 DEVMETHOD(device_attach, sis_attach), 181 DEVMETHOD(device_detach, sis_detach), 182 DEVMETHOD(device_shutdown, sis_shutdown), 183 184 /* bus interface */ 185 DEVMETHOD(bus_print_child, bus_generic_print_child), 186 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 187 188 /* MII interface */ 189 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 190 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 191 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 192 193 { 0, 0 } 194}; 195 196static driver_t sis_driver = { 197 "sis", 198 sis_methods, 199 sizeof(struct sis_softc) 200}; 201 202static devclass_t sis_devclass; 203 204DRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, 0, 0); 205DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 206 207#define SIS_SETBIT(sc, reg, x) \ 208 CSR_WRITE_4(sc, reg, \ 209 CSR_READ_4(sc, reg) | (x)) 210 211#define SIS_CLRBIT(sc, reg, x) \ 212 CSR_WRITE_4(sc, reg, \ 213 CSR_READ_4(sc, reg) & ~(x)) 214 215#define SIO_SET(x) \ 216 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 217 218#define SIO_CLR(x) \ 219 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 220 221static void 222sis_dma_map_desc_next(arg, segs, nseg, error) 223 void *arg; 224 bus_dma_segment_t *segs; 225 int nseg, error; 226{ 227 struct sis_desc *r; 228 229 r = arg; 230 r->sis_next = segs->ds_addr; 231 232 return; 233} 234 235static void 236sis_dma_map_desc_ptr(arg, segs, nseg, error) 237 void *arg; 238 bus_dma_segment_t *segs; 239 int nseg, error; 240{ 241 struct sis_desc *r; 242 243 r = arg; 244 r->sis_ptr = segs->ds_addr; 245 246 return; 247} 248 249static void 250sis_dma_map_ring(arg, segs, nseg, error) 251 void *arg; 252 bus_dma_segment_t *segs; 253 int nseg, error; 254{ 255 u_int32_t *p; 256 257 p = arg; 258 *p = segs->ds_addr; 259 260 return; 261} 262 263/* 264 * Routine to reverse the bits in a word. Stolen almost 265 * verbatim from /usr/games/fortune. 266 */ 267static u_int16_t 268sis_reverse(n) 269 u_int16_t n; 270{ 271 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 272 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 273 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 274 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 275 276 return(n); 277} 278 279static void 280sis_delay(sc) 281 struct sis_softc *sc; 282{ 283 int idx; 284 285 for (idx = (300 / 33) + 1; idx > 0; idx--) 286 CSR_READ_4(sc, SIS_CSR); 287 288 return; 289} 290 291static void 292sis_eeprom_idle(sc) 293 struct sis_softc *sc; 294{ 295 register int i; 296 297 SIO_SET(SIS_EECTL_CSEL); 298 sis_delay(sc); 299 SIO_SET(SIS_EECTL_CLK); 300 sis_delay(sc); 301 302 for (i = 0; i < 25; i++) { 303 SIO_CLR(SIS_EECTL_CLK); 304 sis_delay(sc); 305 SIO_SET(SIS_EECTL_CLK); 306 sis_delay(sc); 307 } 308 309 SIO_CLR(SIS_EECTL_CLK); 310 sis_delay(sc); 311 SIO_CLR(SIS_EECTL_CSEL); 312 sis_delay(sc); 313 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 314 315 return; 316} 317 318/* 319 * Send a read command and address to the EEPROM, check for ACK. 320 */ 321static void 322sis_eeprom_putbyte(sc, addr) 323 struct sis_softc *sc; 324 int addr; 325{ 326 register int d, i; 327 328 d = addr | SIS_EECMD_READ; 329 330 /* 331 * Feed in each bit and stobe the clock. 332 */ 333 for (i = 0x400; i; i >>= 1) { 334 if (d & i) { 335 SIO_SET(SIS_EECTL_DIN); 336 } else { 337 SIO_CLR(SIS_EECTL_DIN); 338 } 339 sis_delay(sc); 340 SIO_SET(SIS_EECTL_CLK); 341 sis_delay(sc); 342 SIO_CLR(SIS_EECTL_CLK); 343 sis_delay(sc); 344 } 345 346 return; 347} 348 349/* 350 * Read a word of data stored in the EEPROM at address 'addr.' 351 */ 352static void 353sis_eeprom_getword(sc, addr, dest) 354 struct sis_softc *sc; 355 int addr; 356 u_int16_t *dest; 357{ 358 register int i; 359 u_int16_t word = 0; 360 361 /* Force EEPROM to idle state. */ 362 sis_eeprom_idle(sc); 363 364 /* Enter EEPROM access mode. */ 365 sis_delay(sc); 366 SIO_CLR(SIS_EECTL_CLK); 367 sis_delay(sc); 368 SIO_SET(SIS_EECTL_CSEL); 369 sis_delay(sc); 370 371 /* 372 * Send address of word we want to read. 373 */ 374 sis_eeprom_putbyte(sc, addr); 375 376 /* 377 * Start reading bits from EEPROM. 378 */ 379 for (i = 0x8000; i; i >>= 1) { 380 SIO_SET(SIS_EECTL_CLK); 381 sis_delay(sc); 382 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 383 word |= i; 384 sis_delay(sc); 385 SIO_CLR(SIS_EECTL_CLK); 386 sis_delay(sc); 387 } 388 389 /* Turn off EEPROM access mode. */ 390 sis_eeprom_idle(sc); 391 392 *dest = word; 393 394 return; 395} 396 397/* 398 * Read a sequence of words from the EEPROM. 399 */ 400static void 401sis_read_eeprom(sc, dest, off, cnt, swap) 402 struct sis_softc *sc; 403 caddr_t dest; 404 int off; 405 int cnt; 406 int swap; 407{ 408 int i; 409 u_int16_t word = 0, *ptr; 410 411 for (i = 0; i < cnt; i++) { 412 sis_eeprom_getword(sc, off + i, &word); 413 ptr = (u_int16_t *)(dest + (i * 2)); 414 if (swap) 415 *ptr = ntohs(word); 416 else 417 *ptr = word; 418 } 419 420 return; 421} 422 423#ifdef __i386__ 424static device_t 425sis_find_bridge(dev) 426 device_t dev; 427{ 428 devclass_t pci_devclass; 429 device_t *pci_devices; 430 int pci_count = 0; 431 device_t *pci_children; 432 int pci_childcount = 0; 433 device_t *busp, *childp; 434 device_t child = NULL; 435 int i, j; 436 437 if ((pci_devclass = devclass_find("pci")) == NULL) 438 return(NULL); 439 440 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 441 442 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 443 pci_childcount = 0; 444 device_get_children(*busp, &pci_children, &pci_childcount); 445 for (j = 0, childp = pci_children; 446 j < pci_childcount; j++, childp++) { 447 if (pci_get_vendor(*childp) == SIS_VENDORID && 448 pci_get_device(*childp) == 0x0008) { 449 child = *childp; 450 goto done; 451 } 452 } 453 } 454 455done: 456 free(pci_devices, M_TEMP); 457 free(pci_children, M_TEMP); 458 return(child); 459} 460 461static void 462sis_read_cmos(sc, dev, dest, off, cnt) 463 struct sis_softc *sc; 464 device_t dev; 465 caddr_t dest; 466 int off; 467 int cnt; 468{ 469 device_t bridge; 470 u_int8_t reg; 471 int i; 472 bus_space_tag_t btag; 473 474 bridge = sis_find_bridge(dev); 475 if (bridge == NULL) 476 return; 477 reg = pci_read_config(bridge, 0x48, 1); 478 pci_write_config(bridge, 0x48, reg|0x40, 1); 479 480 /* XXX */ 481 btag = I386_BUS_SPACE_IO; 482 483 for (i = 0; i < cnt; i++) { 484 bus_space_write_1(btag, 0x0, 0x70, i + off); 485 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 486 } 487 488 pci_write_config(bridge, 0x48, reg & ~0x40, 1); 489 return; 490} 491 492static void 493sis_read_mac(sc, dev, dest) 494 struct sis_softc *sc; 495 device_t dev; 496 caddr_t dest; 497{ 498 u_int32_t filtsave, csrsave; 499 500 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 501 csrsave = CSR_READ_4(sc, SIS_CSR); 502 503 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 504 CSR_WRITE_4(sc, SIS_CSR, 0); 505 506 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 507 508 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 509 ((u_int16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 510 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 511 ((u_int16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 512 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 513 ((u_int16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 514 515 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 516 CSR_WRITE_4(sc, SIS_CSR, csrsave); 517 return; 518} 519#endif 520 521/* 522 * Sync the PHYs by setting data bit and strobing the clock 32 times. 523 */ 524static void sis_mii_sync(sc) 525 struct sis_softc *sc; 526{ 527 register int i; 528 529 SIO_SET(SIS_MII_DIR|SIS_MII_DATA); 530 531 for (i = 0; i < 32; i++) { 532 SIO_SET(SIS_MII_CLK); 533 DELAY(1); 534 SIO_CLR(SIS_MII_CLK); 535 DELAY(1); 536 } 537 538 return; 539} 540 541/* 542 * Clock a series of bits through the MII. 543 */ 544static void sis_mii_send(sc, bits, cnt) 545 struct sis_softc *sc; 546 u_int32_t bits; 547 int cnt; 548{ 549 int i; 550 551 SIO_CLR(SIS_MII_CLK); 552 553 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 554 if (bits & i) { 555 SIO_SET(SIS_MII_DATA); 556 } else { 557 SIO_CLR(SIS_MII_DATA); 558 } 559 DELAY(1); 560 SIO_CLR(SIS_MII_CLK); 561 DELAY(1); 562 SIO_SET(SIS_MII_CLK); 563 } 564} 565 566/* 567 * Read an PHY register through the MII. 568 */ 569static int sis_mii_readreg(sc, frame) 570 struct sis_softc *sc; 571 struct sis_mii_frame *frame; 572 573{ 574 int i, ack, s; 575 576 s = splimp(); 577 578 /* 579 * Set up frame for RX. 580 */ 581 frame->mii_stdelim = SIS_MII_STARTDELIM; 582 frame->mii_opcode = SIS_MII_READOP; 583 frame->mii_turnaround = 0; 584 frame->mii_data = 0; 585 586 /* 587 * Turn on data xmit. 588 */ 589 SIO_SET(SIS_MII_DIR); 590 591 sis_mii_sync(sc); 592 593 /* 594 * Send command/address info. 595 */ 596 sis_mii_send(sc, frame->mii_stdelim, 2); 597 sis_mii_send(sc, frame->mii_opcode, 2); 598 sis_mii_send(sc, frame->mii_phyaddr, 5); 599 sis_mii_send(sc, frame->mii_regaddr, 5); 600 601 /* Idle bit */ 602 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA)); 603 DELAY(1); 604 SIO_SET(SIS_MII_CLK); 605 DELAY(1); 606 607 /* Turn off xmit. */ 608 SIO_CLR(SIS_MII_DIR); 609 610 /* Check for ack */ 611 SIO_CLR(SIS_MII_CLK); 612 DELAY(1); 613 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA; 614 SIO_SET(SIS_MII_CLK); 615 DELAY(1); 616 617 /* 618 * Now try reading data bits. If the ack failed, we still 619 * need to clock through 16 cycles to keep the PHY(s) in sync. 620 */ 621 if (ack) { 622 for(i = 0; i < 16; i++) { 623 SIO_CLR(SIS_MII_CLK); 624 DELAY(1); 625 SIO_SET(SIS_MII_CLK); 626 DELAY(1); 627 } 628 goto fail; 629 } 630 631 for (i = 0x8000; i; i >>= 1) { 632 SIO_CLR(SIS_MII_CLK); 633 DELAY(1); 634 if (!ack) { 635 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA) 636 frame->mii_data |= i; 637 DELAY(1); 638 } 639 SIO_SET(SIS_MII_CLK); 640 DELAY(1); 641 } 642 643fail: 644 645 SIO_CLR(SIS_MII_CLK); 646 DELAY(1); 647 SIO_SET(SIS_MII_CLK); 648 DELAY(1); 649 650 splx(s); 651 652 if (ack) 653 return(1); 654 return(0); 655} 656 657/* 658 * Write to a PHY register through the MII. 659 */ 660static int sis_mii_writereg(sc, frame) 661 struct sis_softc *sc; 662 struct sis_mii_frame *frame; 663 664{ 665 int s; 666 667 s = splimp(); 668 /* 669 * Set up frame for TX. 670 */ 671 672 frame->mii_stdelim = SIS_MII_STARTDELIM; 673 frame->mii_opcode = SIS_MII_WRITEOP; 674 frame->mii_turnaround = SIS_MII_TURNAROUND; 675 676 /* 677 * Turn on data output. 678 */ 679 SIO_SET(SIS_MII_DIR); 680 681 sis_mii_sync(sc); 682 683 sis_mii_send(sc, frame->mii_stdelim, 2); 684 sis_mii_send(sc, frame->mii_opcode, 2); 685 sis_mii_send(sc, frame->mii_phyaddr, 5); 686 sis_mii_send(sc, frame->mii_regaddr, 5); 687 sis_mii_send(sc, frame->mii_turnaround, 2); 688 sis_mii_send(sc, frame->mii_data, 16); 689 690 /* Idle bit. */ 691 SIO_SET(SIS_MII_CLK); 692 DELAY(1); 693 SIO_CLR(SIS_MII_CLK); 694 DELAY(1); 695 696 /* 697 * Turn off xmit. 698 */ 699 SIO_CLR(SIS_MII_DIR); 700 701 splx(s); 702 703 return(0); 704} 705 706static int 707sis_miibus_readreg(dev, phy, reg) 708 device_t dev; 709 int phy, reg; 710{ 711 struct sis_softc *sc; 712 struct sis_mii_frame frame; 713 714 sc = device_get_softc(dev); 715 716 if (sc->sis_type == SIS_TYPE_83815) { 717 if (phy != 0) 718 return(0); 719 /* 720 * The NatSemi chip can take a while after 721 * a reset to come ready, during which the BMSR 722 * returns a value of 0. This is *never* supposed 723 * to happen: some of the BMSR bits are meant to 724 * be hardwired in the on position, and this can 725 * confuse the miibus code a bit during the probe 726 * and attach phase. So we make an effort to check 727 * for this condition and wait for it to clear. 728 */ 729 if (!CSR_READ_4(sc, NS_BMSR)) 730 DELAY(1000); 731 return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 732 } 733 734 if (sc->sis_type == SIS_TYPE_900 && 735 sc->sis_rev < SIS_REV_635 && phy != 0) 736 return(0); 737 738 bzero((char *)&frame, sizeof(frame)); 739 740 frame.mii_phyaddr = phy; 741 frame.mii_regaddr = reg; 742 sis_mii_readreg(sc, &frame); 743 744 return(frame.mii_data); 745} 746 747static int 748sis_miibus_writereg(dev, phy, reg, data) 749 device_t dev; 750 int phy, reg, data; 751{ 752 struct sis_softc *sc; 753 struct sis_mii_frame frame; 754 755 sc = device_get_softc(dev); 756 757 if (sc->sis_type == SIS_TYPE_83815) { 758 if (phy != 0) 759 return(0); 760 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 761 return(0); 762 } 763 764 if (sc->sis_type == SIS_TYPE_900 && phy != 0) 765 return(0); 766 767 bzero((char *)&frame, sizeof(frame)); 768 769 frame.mii_phyaddr = phy; 770 frame.mii_regaddr = reg; 771 frame.mii_data = data; 772 773 sis_mii_writereg(sc, &frame); 774 775 return(0); 776} 777 778static void 779sis_miibus_statchg(dev) 780 device_t dev; 781{ 782 struct sis_softc *sc; 783 784 sc = device_get_softc(dev); 785 sis_init(sc); 786 787 return; 788} 789 790static u_int32_t 791sis_crc(sc, addr) 792 struct sis_softc *sc; 793 caddr_t addr; 794{ 795 u_int32_t crc, carry; 796 int i, j; 797 u_int8_t c; 798 799 /* Compute CRC for the address value. */ 800 crc = 0xFFFFFFFF; /* initial value */ 801 802 for (i = 0; i < 6; i++) { 803 c = *(addr + i); 804 for (j = 0; j < 8; j++) { 805 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 806 crc <<= 1; 807 c >>= 1; 808 if (carry) 809 crc = (crc ^ 0x04c11db6) | carry; 810 } 811 } 812 813 /* 814 * return the filter bit position 815 * 816 * The NatSemi chip has a 512-bit filter, which is 817 * different than the SiS, so we special-case it. 818 */ 819 if (sc->sis_type == SIS_TYPE_83815) 820 return (crc >> 23); 821 822 if (sc->sis_rev >= SIS_REV_635) 823 return (crc >> 24); 824 825 return (crc >> 25); 826} 827 828static void 829sis_setmulti_ns(sc) 830 struct sis_softc *sc; 831{ 832 struct ifnet *ifp; 833 struct ifmultiaddr *ifma; 834 u_int32_t h = 0, i, filtsave; 835 int bit, index; 836 837 ifp = &sc->arpcom.ac_if; 838 839 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 840 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 841 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 842 return; 843 } 844 845 /* 846 * We have to explicitly enable the multicast hash table 847 * on the NatSemi chip if we want to use it, which we do. 848 */ 849 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 850 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 851 852 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 853 854 /* first, zot all the existing hash bits */ 855 for (i = 0; i < 32; i++) { 856 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 857 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 858 } 859 860 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 861 if (ifma->ifma_addr->sa_family != AF_LINK) 862 continue; 863 h = sis_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 864 index = h >> 3; 865 bit = h & 0x1F; 866 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 867 if (bit > 0xF) 868 bit -= 0x10; 869 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 870 } 871 872 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 873 874 return; 875} 876 877static void 878sis_setmulti_sis(sc) 879 struct sis_softc *sc; 880{ 881 struct ifnet *ifp; 882 struct ifmultiaddr *ifma; 883 u_int32_t h, i, n, ctl; 884 u_int16_t hashes[16]; 885 886 ifp = &sc->arpcom.ac_if; 887 888 /* hash table size */ 889 n = sc->sis_rev >= SIS_REV_635 ? 16 : 8; 890 891 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE; 892 893 if (ifp->if_flags & IFF_BROADCAST) 894 ctl |= SIS_RXFILTCTL_BROAD; 895 896 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 897 ctl |= SIS_RXFILTCTL_ALLMULTI; 898 if (ifp->if_flags & IFF_PROMISC) 899 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS; 900 for (i = 0; i < n; i++) 901 hashes[i] = ~0; 902 } else { 903 for (i = 0; i < n; i++) 904 hashes[i] = 0; 905 i = 0; 906 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 907 if (ifma->ifma_addr->sa_family != AF_LINK) 908 continue; 909 h = sis_crc(sc, 910 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 911 hashes[h >> 4] |= 1 << (h & 0xf); 912 i++; 913 } 914 if (i > n) { 915 ctl |= SIS_RXFILTCTL_ALLMULTI; 916 for (i = 0; i < n; i++) 917 hashes[i] = ~0; 918 } 919 } 920 921 for (i = 0; i < n; i++) { 922 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); 923 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); 924 } 925 926 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl); 927} 928 929static void 930sis_reset(sc) 931 struct sis_softc *sc; 932{ 933 register int i; 934 935 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 936 937 for (i = 0; i < SIS_TIMEOUT; i++) { 938 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 939 break; 940 } 941 942 if (i == SIS_TIMEOUT) 943 printf("sis%d: reset never completed\n", sc->sis_unit); 944 945 /* Wait a little while for the chip to get its brains in order. */ 946 DELAY(1000); 947 948 /* 949 * If this is a NetSemi chip, make sure to clear 950 * PME mode. 951 */ 952 if (sc->sis_type == SIS_TYPE_83815) { 953 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 954 CSR_WRITE_4(sc, NS_CLKRUN, 0); 955 } 956 957 return; 958} 959 960/* 961 * Probe for an SiS chip. Check the PCI vendor and device 962 * IDs against our list and return a device name if we find a match. 963 */ 964static int 965sis_probe(dev) 966 device_t dev; 967{ 968 struct sis_type *t; 969 970 t = sis_devs; 971 972 while(t->sis_name != NULL) { 973 if ((pci_get_vendor(dev) == t->sis_vid) && 974 (pci_get_device(dev) == t->sis_did)) { 975 device_set_desc(dev, t->sis_name); 976 return(0); 977 } 978 t++; 979 } 980 981 return(ENXIO); 982} 983 984/* 985 * Attach the interface. Allocate softc structures, do ifmedia 986 * setup and ethernet/BPF attach. 987 */ 988static int 989sis_attach(dev) 990 device_t dev; 991{ 992 u_char eaddr[ETHER_ADDR_LEN]; 993 u_int32_t command; 994 struct sis_softc *sc; 995 struct ifnet *ifp; 996 int unit, error = 0, rid, waittime = 0; 997 998 waittime = 0; 999 sc = device_get_softc(dev); 1000 unit = device_get_unit(dev); 1001 bzero(sc, sizeof(struct sis_softc)); 1002 1003 mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1004 MTX_DEF | MTX_RECURSE); 1005 1006 if (pci_get_device(dev) == SIS_DEVICEID_900) 1007 sc->sis_type = SIS_TYPE_900; 1008 if (pci_get_device(dev) == SIS_DEVICEID_7016) 1009 sc->sis_type = SIS_TYPE_7016; 1010 if (pci_get_vendor(dev) == NS_VENDORID) 1011 sc->sis_type = SIS_TYPE_83815; 1012 1013 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 1014 1015 /* 1016 * Handle power management nonsense. 1017 */ 1018 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1019 u_int32_t iobase, membase, irq; 1020 1021 /* Save important PCI config data. */ 1022 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4); 1023 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4); 1024 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4); 1025 1026 /* Reset the power state. */ 1027 printf("sis%d: chip is in D%d power mode " 1028 "-- setting to D0\n", unit, 1029 pci_get_powerstate(dev)); 1030 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1031 1032 /* Restore PCI config data. */ 1033 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4); 1034 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4); 1035 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4); 1036 } 1037 1038 /* 1039 * Map control/status registers. 1040 */ 1041 pci_enable_busmaster(dev); 1042 pci_enable_io(dev, SYS_RES_IOPORT); 1043 pci_enable_io(dev, SYS_RES_MEMORY); 1044 command = pci_read_config(dev, PCIR_COMMAND, 4); 1045 1046#ifdef SIS_USEIOSPACE 1047 if (!(command & PCIM_CMD_PORTEN)) { 1048 printf("sis%d: failed to enable I/O ports!\n", unit); 1049 error = ENXIO;; 1050 goto fail; 1051 } 1052#else 1053 if (!(command & PCIM_CMD_MEMEN)) { 1054 printf("sis%d: failed to enable memory mapping!\n", unit); 1055 error = ENXIO;; 1056 goto fail; 1057 } 1058#endif 1059 1060 rid = SIS_RID; 1061 sc->sis_res = bus_alloc_resource(dev, SIS_RES, &rid, 1062 0, ~0, 1, RF_ACTIVE); 1063 1064 if (sc->sis_res == NULL) { 1065 printf("sis%d: couldn't map ports/memory\n", unit); 1066 error = ENXIO; 1067 goto fail; 1068 } 1069 1070 sc->sis_btag = rman_get_bustag(sc->sis_res); 1071 sc->sis_bhandle = rman_get_bushandle(sc->sis_res); 1072 1073 /* Allocate interrupt */ 1074 rid = 0; 1075 sc->sis_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1076 RF_SHAREABLE | RF_ACTIVE); 1077 1078 if (sc->sis_irq == NULL) { 1079 printf("sis%d: couldn't map interrupt\n", unit); 1080 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1081 error = ENXIO; 1082 goto fail; 1083 } 1084 1085 error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET, 1086 sis_intr, sc, &sc->sis_intrhand); 1087 1088 if (error) { 1089 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1090 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1091 printf("sis%d: couldn't set up irq\n", unit); 1092 goto fail; 1093 } 1094 1095 /* Reset the adapter. */ 1096 sis_reset(sc); 1097 1098 /* 1099 * Get station address from the EEPROM. 1100 */ 1101 switch (pci_get_vendor(dev)) { 1102 case NS_VENDORID: 1103 /* 1104 * Reading the MAC address out of the EEPROM on 1105 * the NatSemi chip takes a bit more work than 1106 * you'd expect. The address spans 4 16-bit words, 1107 * with the first word containing only a single bit. 1108 * You have to shift everything over one bit to 1109 * get it aligned properly. Also, the bits are 1110 * stored backwards (the LSB is really the MSB, 1111 * and so on) so you have to reverse them in order 1112 * to get the MAC address into the form we want. 1113 * Why? Who the hell knows. 1114 */ 1115 { 1116 u_int16_t tmp[4]; 1117 1118 sis_read_eeprom(sc, (caddr_t)&tmp, 1119 NS_EE_NODEADDR, 4, 0); 1120 1121 /* Shift everything over one bit. */ 1122 tmp[3] = tmp[3] >> 1; 1123 tmp[3] |= tmp[2] << 15; 1124 tmp[2] = tmp[2] >> 1; 1125 tmp[2] |= tmp[1] << 15; 1126 tmp[1] = tmp[1] >> 1; 1127 tmp[1] |= tmp[0] << 15; 1128 1129 /* Now reverse all the bits. */ 1130 tmp[3] = sis_reverse(tmp[3]); 1131 tmp[2] = sis_reverse(tmp[2]); 1132 tmp[1] = sis_reverse(tmp[1]); 1133 1134 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); 1135 } 1136 break; 1137 case SIS_VENDORID: 1138 default: 1139#ifdef __i386__ 1140 /* 1141 * If this is a SiS 630E chipset with an embedded 1142 * SiS 900 controller, we have to read the MAC address 1143 * from the APC CMOS RAM. Our method for doing this 1144 * is very ugly since we have to reach out and grab 1145 * ahold of hardware for which we cannot properly 1146 * allocate resources. This code is only compiled on 1147 * the i386 architecture since the SiS 630E chipset 1148 * is for x86 motherboards only. Note that there are 1149 * a lot of magic numbers in this hack. These are 1150 * taken from SiS's Linux driver. I'd like to replace 1151 * them with proper symbolic definitions, but that 1152 * requires some datasheets that I don't have access 1153 * to at the moment. 1154 */ 1155 if (sc->sis_rev == SIS_REV_630S || 1156 sc->sis_rev == SIS_REV_630E || 1157 sc->sis_rev == SIS_REV_630EA1) 1158 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 1159 1160 else if (sc->sis_rev == SIS_REV_635 || 1161 sc->sis_rev == SIS_REV_630ET) 1162 sis_read_mac(sc, dev, (caddr_t)&eaddr); 1163 else if (sc->sis_rev == SIS_REV_96x) { 1164 /* Allow to read EEPROM from LAN. It is shared 1165 * between a 1394 controller and the NIC and each 1166 * time we access it, we need to set SIS_EECMD_REQ. 1167 */ 1168 SIO_SET(SIS_EECMD_REQ); 1169 for (waittime = 0; waittime < SIS_TIMEOUT; 1170 waittime++) { 1171 /* Force EEPROM to idle state. */ 1172 sis_eeprom_idle(sc); 1173 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { 1174 sis_read_eeprom(sc, (caddr_t)&eaddr, 1175 SIS_EE_NODEADDR, 3, 0); 1176 break; 1177 } 1178 DELAY(1); 1179 } 1180 /* 1181 * Set SIS_EECTL_CLK to high, so a other master 1182 * can operate on the i2c bus. 1183 */ 1184 SIO_SET(SIS_EECTL_CLK); 1185 /* Refuse EEPROM access by LAN */ 1186 SIO_SET(SIS_EECMD_DONE); 1187 } else 1188#endif 1189 sis_read_eeprom(sc, (caddr_t)&eaddr, 1190 SIS_EE_NODEADDR, 3, 0); 1191 break; 1192 } 1193 1194 /* 1195 * A SiS chip was detected. Inform the world. 1196 */ 1197 printf("sis%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1198 1199 sc->sis_unit = unit; 1200 callout_handle_init(&sc->sis_stat_ch); 1201 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1202 1203 /* 1204 * Allocate the parent bus DMA tag appropriate for PCI. 1205 */ 1206#define SIS_NSEG_NEW 32 1207 error = bus_dma_tag_create(NULL, /* parent */ 1208 1, 0, /* alignment, boundary */ 1209 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1210 BUS_SPACE_MAXADDR, /* highaddr */ 1211 NULL, NULL, /* filter, filterarg */ 1212 MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */ 1213 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1214 BUS_DMA_ALLOCNOW, /* flags */ 1215 &sc->sis_parent_tag); 1216 1217 /* 1218 * Now allocate a tag for the DMA descriptor lists. 1219 * All of our lists are allocated as a contiguous block 1220 * of memory. 1221 */ 1222 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1223 1, 0, /* alignment, boundary */ 1224 BUS_SPACE_MAXADDR, /* lowaddr */ 1225 BUS_SPACE_MAXADDR, /* highaddr */ 1226 NULL, NULL, /* filter, filterarg */ 1227 SIS_RX_LIST_SZ, 1, /* maxsize,nsegments */ 1228 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1229 0, /* flags */ 1230 &sc->sis_ldata.sis_rx_tag); 1231 1232 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1233 1, 0, /* alignment, boundary */ 1234 BUS_SPACE_MAXADDR, /* lowaddr */ 1235 BUS_SPACE_MAXADDR, /* highaddr */ 1236 NULL, NULL, /* filter, filterarg */ 1237 SIS_TX_LIST_SZ, 1, /* maxsize,nsegments */ 1238 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1239 0, /* flags */ 1240 &sc->sis_ldata.sis_tx_tag); 1241 1242 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1243 1, 0, /* alignment, boundary */ 1244 BUS_SPACE_MAXADDR, /* lowaddr */ 1245 BUS_SPACE_MAXADDR, /* highaddr */ 1246 NULL, NULL, /* filter, filterarg */ 1247 MCLBYTES, 1, /* maxsize,nsegments */ 1248 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1249 0, /* flags */ 1250 &sc->sis_tag); 1251 1252 /* 1253 * Now allocate a chunk of DMA-able memory based on the 1254 * tag we just created. 1255 */ 1256 error = bus_dmamem_alloc(sc->sis_ldata.sis_tx_tag, 1257 (void **)&sc->sis_ldata.sis_tx_list, BUS_DMA_NOWAIT, 1258 &sc->sis_ldata.sis_tx_dmamap); 1259 1260 if (error) { 1261 printf("sis%d: no memory for list buffers!\n", unit); 1262 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1263 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1264 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1265 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1266 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1267 error = ENXIO; 1268 goto fail; 1269 } 1270 1271 error = bus_dmamem_alloc(sc->sis_ldata.sis_rx_tag, 1272 (void **)&sc->sis_ldata.sis_rx_list, BUS_DMA_NOWAIT, 1273 &sc->sis_ldata.sis_rx_dmamap); 1274 1275 if (error) { 1276 printf("sis%d: no memory for list buffers!\n", unit); 1277 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1278 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1279 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1280 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1281 sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 1282 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1283 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1284 error = ENXIO; 1285 goto fail; 1286 } 1287 1288 1289 bzero(sc->sis_ldata.sis_tx_list, SIS_TX_LIST_SZ); 1290 bzero(sc->sis_ldata.sis_rx_list, SIS_RX_LIST_SZ); 1291 1292 /* 1293 * Obtain the physical addresses of the RX and TX 1294 * rings which we'll need later in the init routine. 1295 */ 1296 bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1297 sc->sis_ldata.sis_tx_dmamap, &(sc->sis_ldata.sis_tx_list[0]), 1298 sizeof(struct sis_desc), sis_dma_map_ring, 1299 &sc->sis_cdata.sis_tx_paddr, 0); 1300 bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1301 sc->sis_ldata.sis_rx_dmamap, &(sc->sis_ldata.sis_rx_list[0]), 1302 sizeof(struct sis_desc), sis_dma_map_ring, 1303 &sc->sis_cdata.sis_rx_paddr, 0); 1304 1305 ifp = &sc->arpcom.ac_if; 1306 ifp->if_softc = sc; 1307 ifp->if_unit = unit; 1308 ifp->if_name = "sis"; 1309 ifp->if_mtu = ETHERMTU; 1310 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1311 ifp->if_ioctl = sis_ioctl; 1312 ifp->if_output = ether_output; 1313 ifp->if_start = sis_start; 1314 ifp->if_watchdog = sis_watchdog; 1315 ifp->if_init = sis_init; 1316 ifp->if_baudrate = 10000000; 1317 ifp->if_snd.ifq_maxlen = SIS_TX_LIST_CNT - 1; 1318 1319 /* 1320 * Do MII setup. 1321 */ 1322 if (mii_phy_probe(dev, &sc->sis_miibus, 1323 sis_ifmedia_upd, sis_ifmedia_sts)) { 1324 printf("sis%d: MII without any PHY!\n", sc->sis_unit); 1325 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1326 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1327 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1328 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1329 sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap); 1330 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1331 sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 1332 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1333 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1334 error = ENXIO; 1335 goto fail; 1336 } 1337 1338 /* 1339 * Call MI attach routine. 1340 */ 1341 ether_ifattach(ifp, eaddr); 1342 1343 /* 1344 * Tell the upper layer(s) we support long frames. 1345 */ 1346 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1347 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1348 1349 callout_handle_init(&sc->sis_stat_ch); 1350 return(0); 1351 1352fail: 1353 mtx_destroy(&sc->sis_mtx); 1354 return(error); 1355} 1356 1357static int 1358sis_detach(dev) 1359 device_t dev; 1360{ 1361 struct sis_softc *sc; 1362 struct ifnet *ifp; 1363 1364 1365 sc = device_get_softc(dev); 1366 SIS_LOCK(sc); 1367 ifp = &sc->arpcom.ac_if; 1368 1369 sis_reset(sc); 1370 sis_stop(sc); 1371 ether_ifdetach(ifp); 1372 1373 bus_generic_detach(dev); 1374 device_delete_child(dev, sc->sis_miibus); 1375 1376 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1377 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1378 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1379 1380 bus_dmamap_unload(sc->sis_ldata.sis_rx_tag, 1381 sc->sis_ldata.sis_rx_dmamap); 1382 bus_dmamap_unload(sc->sis_ldata.sis_tx_tag, 1383 sc->sis_ldata.sis_tx_dmamap); 1384 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1385 sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap); 1386 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1387 sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 1388 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1389 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1390 bus_dma_tag_destroy(sc->sis_parent_tag); 1391 1392 SIS_UNLOCK(sc); 1393 mtx_destroy(&sc->sis_mtx); 1394 1395 return(0); 1396} 1397 1398/* 1399 * Initialize the transmit descriptors. 1400 */ 1401static int 1402sis_list_tx_init(sc) 1403 struct sis_softc *sc; 1404{ 1405 struct sis_list_data *ld; 1406 struct sis_ring_data *cd; 1407 int i, nexti; 1408 1409 cd = &sc->sis_cdata; 1410 ld = &sc->sis_ldata; 1411 1412 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1413 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1; 1414 ld->sis_tx_list[i].sis_nextdesc = 1415 &ld->sis_tx_list[nexti]; 1416 bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1417 sc->sis_ldata.sis_tx_dmamap, 1418 &ld->sis_tx_list[nexti], sizeof(struct sis_desc), 1419 sis_dma_map_desc_next, &ld->sis_tx_list[i], 0); 1420 ld->sis_tx_list[i].sis_mbuf = NULL; 1421 ld->sis_tx_list[i].sis_ptr = 0; 1422 ld->sis_tx_list[i].sis_ctl = 0; 1423 } 1424 1425 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0; 1426 1427 bus_dmamap_sync(sc->sis_ldata.sis_tx_tag, 1428 sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 1429 1430 return(0); 1431} 1432 1433/* 1434 * Initialize the RX descriptors and allocate mbufs for them. Note that 1435 * we arrange the descriptors in a closed ring, so that the last descriptor 1436 * points back to the first. 1437 */ 1438static int 1439sis_list_rx_init(sc) 1440 struct sis_softc *sc; 1441{ 1442 struct sis_list_data *ld; 1443 struct sis_ring_data *cd; 1444 int i,nexti; 1445 1446 ld = &sc->sis_ldata; 1447 cd = &sc->sis_cdata; 1448 1449 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1450 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS) 1451 return(ENOBUFS); 1452 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1; 1453 ld->sis_rx_list[i].sis_nextdesc = 1454 &ld->sis_rx_list[nexti]; 1455 bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1456 sc->sis_ldata.sis_rx_dmamap, 1457 &ld->sis_rx_list[nexti], 1458 sizeof(struct sis_desc), sis_dma_map_desc_next, 1459 &ld->sis_rx_list[i], 0); 1460 } 1461 1462 bus_dmamap_sync(sc->sis_ldata.sis_rx_tag, 1463 sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 1464 1465 cd->sis_rx_prod = 0; 1466 1467 return(0); 1468} 1469 1470/* 1471 * Initialize an RX descriptor and attach an MBUF cluster. 1472 */ 1473static int 1474sis_newbuf(sc, c, m) 1475 struct sis_softc *sc; 1476 struct sis_desc *c; 1477 struct mbuf *m; 1478{ 1479 1480 if (c == NULL) 1481 return(EINVAL); 1482 1483 if (m == NULL) { 1484 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1485 if (m == NULL) 1486 return(ENOBUFS); 1487 } else 1488 m->m_data = m->m_ext.ext_buf; 1489 1490 c->sis_mbuf = m; 1491 c->sis_ctl = SIS_RXLEN; 1492 1493 bus_dmamap_create(sc->sis_tag, 0, &c->sis_map); 1494 bus_dmamap_load(sc->sis_tag, c->sis_map, 1495 mtod(m, void *), MCLBYTES, 1496 sis_dma_map_desc_ptr, c, 0); 1497 bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREWRITE); 1498 1499 return(0); 1500} 1501 1502/* 1503 * A frame has been uploaded: pass the resulting mbuf chain up to 1504 * the higher level protocols. 1505 */ 1506static void 1507sis_rxeof(sc) 1508 struct sis_softc *sc; 1509{ 1510 struct mbuf *m; 1511 struct ifnet *ifp; 1512 struct sis_desc *cur_rx; 1513 int i, total_len = 0; 1514 u_int32_t rxstat; 1515 1516 ifp = &sc->arpcom.ac_if; 1517 i = sc->sis_cdata.sis_rx_prod; 1518 1519 while(SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) { 1520 1521#ifdef DEVICE_POLLING 1522 if (ifp->if_flags & IFF_POLLING) { 1523 if (sc->rxcycles <= 0) 1524 break; 1525 sc->rxcycles--; 1526 } 1527#endif /* DEVICE_POLLING */ 1528 cur_rx = &sc->sis_ldata.sis_rx_list[i]; 1529 rxstat = cur_rx->sis_rxstat; 1530 bus_dmamap_sync(sc->sis_tag, 1531 cur_rx->sis_map, BUS_DMASYNC_POSTWRITE); 1532 bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map); 1533 bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map); 1534 m = cur_rx->sis_mbuf; 1535 cur_rx->sis_mbuf = NULL; 1536 total_len = SIS_RXBYTES(cur_rx); 1537 SIS_INC(i, SIS_RX_LIST_CNT); 1538 1539 /* 1540 * If an error occurs, update stats, clear the 1541 * status word and leave the mbuf cluster in place: 1542 * it should simply get re-used next time this descriptor 1543 * comes up in the ring. 1544 */ 1545 if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 1546 ifp->if_ierrors++; 1547 if (rxstat & SIS_RXSTAT_COLL) 1548 ifp->if_collisions++; 1549 sis_newbuf(sc, cur_rx, m); 1550 continue; 1551 } 1552 1553 /* No errors; receive the packet. */ 1554#ifdef __i386__ 1555 /* 1556 * On the x86 we do not have alignment problems, so try to 1557 * allocate a new buffer for the receive ring, and pass up 1558 * the one where the packet is already, saving the expensive 1559 * copy done in m_devget(). 1560 * If we are on an architecture with alignment problems, or 1561 * if the allocation fails, then use m_devget and leave the 1562 * existing buffer in the receive ring. 1563 */ 1564 if (sis_newbuf(sc, cur_rx, NULL) == 0) 1565 m->m_pkthdr.len = m->m_len = total_len; 1566 else 1567#endif 1568 { 1569 struct mbuf *m0; 1570 m0 = m_devget(mtod(m, char *), total_len, 1571 ETHER_ALIGN, ifp, NULL); 1572 sis_newbuf(sc, cur_rx, m); 1573 if (m0 == NULL) { 1574 ifp->if_ierrors++; 1575 continue; 1576 } 1577 m = m0; 1578 } 1579 1580 ifp->if_ipackets++; 1581 m->m_pkthdr.rcvif = ifp; 1582 1583 (*ifp->if_input)(ifp, m); 1584 } 1585 1586 sc->sis_cdata.sis_rx_prod = i; 1587 1588 return; 1589} 1590 1591static void 1592sis_rxeoc(sc) 1593 struct sis_softc *sc; 1594{ 1595 sis_rxeof(sc); 1596 sis_init(sc); 1597 return; 1598} 1599 1600/* 1601 * A frame was downloaded to the chip. It's safe for us to clean up 1602 * the list buffers. 1603 */ 1604 1605static void 1606sis_txeof(sc) 1607 struct sis_softc *sc; 1608{ 1609 struct ifnet *ifp; 1610 u_int32_t idx; 1611 1612 ifp = &sc->arpcom.ac_if; 1613 1614 /* 1615 * Go through our tx list and free mbufs for those 1616 * frames that have been transmitted. 1617 */ 1618 for (idx = sc->sis_cdata.sis_tx_cons; sc->sis_cdata.sis_tx_cnt > 0; 1619 sc->sis_cdata.sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) { 1620 struct sis_desc *cur_tx = &sc->sis_ldata.sis_tx_list[idx]; 1621 1622 if (SIS_OWNDESC(cur_tx)) 1623 break; 1624 1625 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) 1626 continue; 1627 1628 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 1629 ifp->if_oerrors++; 1630 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 1631 ifp->if_collisions++; 1632 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 1633 ifp->if_collisions++; 1634 } 1635 1636 ifp->if_collisions += 1637 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 1638 1639 ifp->if_opackets++; 1640 if (cur_tx->sis_mbuf != NULL) { 1641 m_freem(cur_tx->sis_mbuf); 1642 cur_tx->sis_mbuf = NULL; 1643 bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map); 1644 bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map); 1645 } 1646 } 1647 1648 if (idx != sc->sis_cdata.sis_tx_cons) { 1649 /* we freed up some buffers */ 1650 sc->sis_cdata.sis_tx_cons = idx; 1651 ifp->if_flags &= ~IFF_OACTIVE; 1652 } 1653 1654 ifp->if_timer = (sc->sis_cdata.sis_tx_cnt == 0) ? 0 : 5; 1655 1656 return; 1657} 1658 1659static void 1660sis_tick(xsc) 1661 void *xsc; 1662{ 1663 struct sis_softc *sc; 1664 struct mii_data *mii; 1665 struct ifnet *ifp; 1666 1667 sc = xsc; 1668 SIS_LOCK(sc); 1669 ifp = &sc->arpcom.ac_if; 1670 1671 mii = device_get_softc(sc->sis_miibus); 1672 mii_tick(mii); 1673 1674 if (!sc->sis_link && mii->mii_media_status & IFM_ACTIVE && 1675 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1676 sc->sis_link++; 1677 if (ifp->if_snd.ifq_head != NULL) 1678 sis_start(ifp); 1679 } 1680 1681 sc->sis_stat_ch = timeout(sis_tick, sc, hz); 1682 1683 SIS_UNLOCK(sc); 1684 1685 return; 1686} 1687 1688#ifdef DEVICE_POLLING 1689static poll_handler_t sis_poll; 1690 1691static void 1692sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1693{ 1694 struct sis_softc *sc = ifp->if_softc; 1695 1696 SIS_LOCK(sc); 1697 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1698 CSR_WRITE_4(sc, SIS_IER, 1); 1699 goto done; 1700 } 1701 1702 /* 1703 * On the sis, reading the status register also clears it. 1704 * So before returning to intr mode we must make sure that all 1705 * possible pending sources of interrupts have been served. 1706 * In practice this means run to completion the *eof routines, 1707 * and then call the interrupt routine 1708 */ 1709 sc->rxcycles = count; 1710 sis_rxeof(sc); 1711 sis_txeof(sc); 1712 if (ifp->if_snd.ifq_head != NULL) 1713 sis_start(ifp); 1714 1715 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1716 u_int32_t status; 1717 1718 /* Reading the ISR register clears all interrupts. */ 1719 status = CSR_READ_4(sc, SIS_ISR); 1720 1721 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 1722 sis_rxeoc(sc); 1723 1724 if (status & (SIS_ISR_RX_IDLE)) 1725 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1726 1727 if (status & SIS_ISR_SYSERR) { 1728 sis_reset(sc); 1729 sis_init(sc); 1730 } 1731 } 1732done: 1733 SIS_UNLOCK(sc); 1734 return; 1735} 1736#endif /* DEVICE_POLLING */ 1737 1738static void 1739sis_intr(arg) 1740 void *arg; 1741{ 1742 struct sis_softc *sc; 1743 struct ifnet *ifp; 1744 u_int32_t status; 1745 1746 sc = arg; 1747 ifp = &sc->arpcom.ac_if; 1748 1749 SIS_LOCK(sc); 1750#ifdef DEVICE_POLLING 1751 if (ifp->if_flags & IFF_POLLING) 1752 goto done; 1753 if (ether_poll_register(sis_poll, ifp)) { /* ok, disable interrupts */ 1754 CSR_WRITE_4(sc, SIS_IER, 0); 1755 goto done; 1756 } 1757#endif /* DEVICE_POLLING */ 1758 1759 /* Supress unwanted interrupts */ 1760 if (!(ifp->if_flags & IFF_UP)) { 1761 sis_stop(sc); 1762 goto done; 1763 } 1764 1765 /* Disable interrupts. */ 1766 CSR_WRITE_4(sc, SIS_IER, 0); 1767 1768 for (;;) { 1769 /* Reading the ISR register clears all interrupts. */ 1770 status = CSR_READ_4(sc, SIS_ISR); 1771 1772 if ((status & SIS_INTRS) == 0) 1773 break; 1774 1775 if (status & 1776 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | 1777 SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) ) 1778 sis_txeof(sc); 1779 1780 if (status & (SIS_ISR_RX_DESC_OK|SIS_ISR_RX_OK|SIS_ISR_RX_IDLE)) 1781 sis_rxeof(sc); 1782 1783 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW)) 1784 sis_rxeoc(sc); 1785 1786 if (status & (SIS_ISR_RX_IDLE)) 1787 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1788 1789 if (status & SIS_ISR_SYSERR) { 1790 sis_reset(sc); 1791 sis_init(sc); 1792 } 1793 } 1794 1795 /* Re-enable interrupts. */ 1796 CSR_WRITE_4(sc, SIS_IER, 1); 1797 1798 if (ifp->if_snd.ifq_head != NULL) 1799 sis_start(ifp); 1800done: 1801 SIS_UNLOCK(sc); 1802 1803 return; 1804} 1805 1806/* 1807 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1808 * pointers to the fragment pointers. 1809 */ 1810static int 1811sis_encap(sc, m_head, txidx) 1812 struct sis_softc *sc; 1813 struct mbuf *m_head; 1814 u_int32_t *txidx; 1815{ 1816 struct sis_desc *f = NULL; 1817 struct mbuf *m; 1818 int frag, cur, cnt = 0; 1819 1820 /* 1821 * Start packing the mbufs in this chain into 1822 * the fragment pointers. Stop when we run out 1823 * of fragments or hit the end of the mbuf chain. 1824 */ 1825 m = m_head; 1826 cur = frag = *txidx; 1827 1828 for (m = m_head; m != NULL; m = m->m_next) { 1829 if (m->m_len != 0) { 1830 if ((SIS_TX_LIST_CNT - 1831 (sc->sis_cdata.sis_tx_cnt + cnt)) < 2) 1832 return(ENOBUFS); 1833 f = &sc->sis_ldata.sis_tx_list[frag]; 1834 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; 1835 bus_dmamap_create(sc->sis_tag, 0, &f->sis_map); 1836 bus_dmamap_load(sc->sis_tag, f->sis_map, 1837 mtod(m, void *), m->m_len, 1838 sis_dma_map_desc_ptr, f, 0); 1839 bus_dmamap_sync(sc->sis_tag, 1840 f->sis_map, BUS_DMASYNC_PREREAD); 1841 if (cnt != 0) 1842 f->sis_ctl |= SIS_CMDSTS_OWN; 1843 cur = frag; 1844 SIS_INC(frag, SIS_TX_LIST_CNT); 1845 cnt++; 1846 } 1847 } 1848 1849 if (m != NULL) 1850 return(ENOBUFS); 1851 1852 sc->sis_ldata.sis_tx_list[cur].sis_mbuf = m_head; 1853 sc->sis_ldata.sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1854 sc->sis_ldata.sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1855 sc->sis_cdata.sis_tx_cnt += cnt; 1856 *txidx = frag; 1857 1858 return(0); 1859} 1860 1861/* 1862 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1863 * to the mbuf data regions directly in the transmit lists. We also save a 1864 * copy of the pointers since the transmit list fragment pointers are 1865 * physical addresses. 1866 */ 1867 1868static void 1869sis_start(ifp) 1870 struct ifnet *ifp; 1871{ 1872 struct sis_softc *sc; 1873 struct mbuf *m_head = NULL; 1874 u_int32_t idx; 1875 1876 sc = ifp->if_softc; 1877 SIS_LOCK(sc); 1878 1879 if (!sc->sis_link) { 1880 SIS_UNLOCK(sc); 1881 return; 1882 } 1883 1884 idx = sc->sis_cdata.sis_tx_prod; 1885 1886 if (ifp->if_flags & IFF_OACTIVE) { 1887 SIS_UNLOCK(sc); 1888 return; 1889 } 1890 1891 while(sc->sis_ldata.sis_tx_list[idx].sis_mbuf == NULL) { 1892 IF_DEQUEUE(&ifp->if_snd, m_head); 1893 if (m_head == NULL) 1894 break; 1895 1896 if (sis_encap(sc, m_head, &idx)) { 1897 IF_PREPEND(&ifp->if_snd, m_head); 1898 ifp->if_flags |= IFF_OACTIVE; 1899 break; 1900 } 1901 1902 /* 1903 * If there's a BPF listener, bounce a copy of this frame 1904 * to him. 1905 */ 1906 BPF_MTAP(ifp, m_head); 1907 1908 } 1909 1910 /* Transmit */ 1911 sc->sis_cdata.sis_tx_prod = idx; 1912 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 1913 1914 /* 1915 * Set a timeout in case the chip goes out to lunch. 1916 */ 1917 ifp->if_timer = 5; 1918 1919 SIS_UNLOCK(sc); 1920 1921 return; 1922} 1923 1924static void 1925sis_init(xsc) 1926 void *xsc; 1927{ 1928 struct sis_softc *sc = xsc; 1929 struct ifnet *ifp = &sc->arpcom.ac_if; 1930 struct mii_data *mii; 1931 1932 SIS_LOCK(sc); 1933 1934 /* 1935 * Cancel pending I/O and free all RX/TX buffers. 1936 */ 1937 sis_stop(sc); 1938 1939 mii = device_get_softc(sc->sis_miibus); 1940 1941 /* Set MAC address */ 1942 if (sc->sis_type == SIS_TYPE_83815) { 1943 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 1944 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1945 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1946 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 1947 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1948 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1949 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 1950 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1951 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1952 } else { 1953 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 1954 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1955 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1956 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 1957 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1958 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1959 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 1960 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1961 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1962 } 1963 1964 /* Init circular RX list. */ 1965 if (sis_list_rx_init(sc) == ENOBUFS) { 1966 printf("sis%d: initialization failed: no " 1967 "memory for rx buffers\n", sc->sis_unit); 1968 sis_stop(sc); 1969 SIS_UNLOCK(sc); 1970 return; 1971 } 1972 1973 /* 1974 * Init tx descriptors. 1975 */ 1976 sis_list_tx_init(sc); 1977 1978 /* 1979 * For the NatSemi chip, we have to explicitly enable the 1980 * reception of ARP frames, as well as turn on the 'perfect 1981 * match' filter where we store the station address, otherwise 1982 * we won't receive unicasts meant for this host. 1983 */ 1984 if (sc->sis_type == SIS_TYPE_83815) { 1985 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 1986 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 1987 } 1988 1989 /* If we want promiscuous mode, set the allframes bit. */ 1990 if (ifp->if_flags & IFF_PROMISC) { 1991 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1992 } else { 1993 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1994 } 1995 1996 /* 1997 * Set the capture broadcast bit to capture broadcast frames. 1998 */ 1999 if (ifp->if_flags & IFF_BROADCAST) { 2000 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 2001 } else { 2002 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 2003 } 2004 2005 /* 2006 * Load the multicast filter. 2007 */ 2008 if (sc->sis_type == SIS_TYPE_83815) 2009 sis_setmulti_ns(sc); 2010 else 2011 sis_setmulti_sis(sc); 2012 2013 /* Turn the receive filter on */ 2014 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 2015 2016 /* 2017 * Load the address of the RX and TX lists. 2018 */ 2019 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_cdata.sis_rx_paddr); 2020 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_cdata.sis_tx_paddr); 2021 2022 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of 2023 * the PCI bus. When this bit is set, the Max DMA Burst Size 2024 * for TX/RX DMA should be no larger than 16 double words. 2025 */ 2026 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) { 2027 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); 2028 } else { 2029 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); 2030 } 2031 2032 2033 /* Accept Long Packets for VLAN support */ 2034 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 2035 2036 /* Set TX configuration */ 2037 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 2038 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 2039 } else { 2040 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 2041 } 2042 2043 /* Set full/half duplex mode. */ 2044 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 2045 SIS_SETBIT(sc, SIS_TX_CFG, 2046 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 2047 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 2048 } else { 2049 SIS_CLRBIT(sc, SIS_TX_CFG, 2050 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 2051 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 2052 } 2053 2054 /* 2055 * Enable interrupts. 2056 */ 2057 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 2058#ifdef DEVICE_POLLING 2059 /* 2060 * ... only enable interrupts if we are not polling, make sure 2061 * they are off otherwise. 2062 */ 2063 if (ifp->if_flags & IFF_POLLING) 2064 CSR_WRITE_4(sc, SIS_IER, 0); 2065 else 2066#endif /* DEVICE_POLLING */ 2067 CSR_WRITE_4(sc, SIS_IER, 1); 2068 2069 /* Enable receiver and transmitter. */ 2070 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2071 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 2072 2073#ifdef notdef 2074 mii_mediachg(mii); 2075#endif 2076 2077 /* 2078 * Page 75 of the DP83815 manual recommends the 2079 * following register settings "for optimum 2080 * performance." Note however that at least three 2081 * of the registers are listed as "reserved" in 2082 * the register map, so who knows what they do. 2083 */ 2084 if (sc->sis_type == SIS_TYPE_83815) { 2085 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 2086 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 2087 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 2088 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 2089 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 2090 } 2091 2092 ifp->if_flags |= IFF_RUNNING; 2093 ifp->if_flags &= ~IFF_OACTIVE; 2094 2095 sc->sis_stat_ch = timeout(sis_tick, sc, hz); 2096 2097 SIS_UNLOCK(sc); 2098 2099 return; 2100} 2101 2102/* 2103 * Set media options. 2104 */ 2105static int 2106sis_ifmedia_upd(ifp) 2107 struct ifnet *ifp; 2108{ 2109 struct sis_softc *sc; 2110 struct mii_data *mii; 2111 2112 sc = ifp->if_softc; 2113 2114 mii = device_get_softc(sc->sis_miibus); 2115 sc->sis_link = 0; 2116 if (mii->mii_instance) { 2117 struct mii_softc *miisc; 2118 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2119 mii_phy_reset(miisc); 2120 } 2121 mii_mediachg(mii); 2122 2123 return(0); 2124} 2125 2126/* 2127 * Report current media status. 2128 */ 2129static void 2130sis_ifmedia_sts(ifp, ifmr) 2131 struct ifnet *ifp; 2132 struct ifmediareq *ifmr; 2133{ 2134 struct sis_softc *sc; 2135 struct mii_data *mii; 2136 2137 sc = ifp->if_softc; 2138 2139 mii = device_get_softc(sc->sis_miibus); 2140 mii_pollstat(mii); 2141 ifmr->ifm_active = mii->mii_media_active; 2142 ifmr->ifm_status = mii->mii_media_status; 2143 2144 return; 2145} 2146 2147static int 2148sis_ioctl(ifp, command, data) 2149 struct ifnet *ifp; 2150 u_long command; 2151 caddr_t data; 2152{ 2153 struct sis_softc *sc = ifp->if_softc; 2154 struct ifreq *ifr = (struct ifreq *) data; 2155 struct mii_data *mii; 2156 int error = 0; 2157 2158 switch(command) { 2159 case SIOCSIFFLAGS: 2160 if (ifp->if_flags & IFF_UP) { 2161 sis_init(sc); 2162 } else { 2163 if (ifp->if_flags & IFF_RUNNING) 2164 sis_stop(sc); 2165 } 2166 error = 0; 2167 break; 2168 case SIOCADDMULTI: 2169 case SIOCDELMULTI: 2170 SIS_LOCK(sc); 2171 if (sc->sis_type == SIS_TYPE_83815) 2172 sis_setmulti_ns(sc); 2173 else 2174 sis_setmulti_sis(sc); 2175 SIS_UNLOCK(sc); 2176 error = 0; 2177 break; 2178 case SIOCGIFMEDIA: 2179 case SIOCSIFMEDIA: 2180 mii = device_get_softc(sc->sis_miibus); 2181 SIS_LOCK(sc); 2182 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2183 SIS_UNLOCK(sc); 2184 break; 2185 default: 2186 error = ether_ioctl(ifp, command, data); 2187 break; 2188 } 2189 2190 return(error); 2191} 2192 2193static void 2194sis_watchdog(ifp) 2195 struct ifnet *ifp; 2196{ 2197 struct sis_softc *sc; 2198 2199 sc = ifp->if_softc; 2200 2201 SIS_LOCK(sc); 2202 2203 ifp->if_oerrors++; 2204 printf("sis%d: watchdog timeout\n", sc->sis_unit); 2205 2206 sis_stop(sc); 2207 sis_reset(sc); 2208 sis_init(sc); 2209 2210 if (ifp->if_snd.ifq_head != NULL) 2211 sis_start(ifp); 2212 2213 SIS_UNLOCK(sc); 2214 2215 return; 2216} 2217 2218/* 2219 * Stop the adapter and free any mbufs allocated to the 2220 * RX and TX lists. 2221 */ 2222static void 2223sis_stop(sc) 2224 struct sis_softc *sc; 2225{ 2226 register int i; 2227 struct ifnet *ifp; 2228 2229 SIS_LOCK(sc); 2230 ifp = &sc->arpcom.ac_if; 2231 ifp->if_timer = 0; 2232 2233 untimeout(sis_tick, sc, sc->sis_stat_ch); 2234 2235 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2236#ifdef DEVICE_POLLING 2237 ether_poll_deregister(ifp); 2238#endif 2239 CSR_WRITE_4(sc, SIS_IER, 0); 2240 CSR_WRITE_4(sc, SIS_IMR, 0); 2241 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2242 DELAY(1000); 2243 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 2244 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2245 2246 sc->sis_link = 0; 2247 2248 /* 2249 * Free data in the RX lists. 2250 */ 2251 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 2252 if (sc->sis_ldata.sis_rx_list[i].sis_mbuf != NULL) { 2253 bus_dmamap_unload(sc->sis_tag, 2254 sc->sis_ldata.sis_rx_list[i].sis_map); 2255 bus_dmamap_destroy(sc->sis_tag, 2256 sc->sis_ldata.sis_rx_list[i].sis_map); 2257 m_freem(sc->sis_ldata.sis_rx_list[i].sis_mbuf); 2258 sc->sis_ldata.sis_rx_list[i].sis_mbuf = NULL; 2259 } 2260 } 2261 bzero(sc->sis_ldata.sis_rx_list, 2262 sizeof(sc->sis_ldata.sis_rx_list)); 2263 2264 /* 2265 * Free the TX list buffers. 2266 */ 2267 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 2268 if (sc->sis_ldata.sis_tx_list[i].sis_mbuf != NULL) { 2269 bus_dmamap_unload(sc->sis_tag, 2270 sc->sis_ldata.sis_tx_list[i].sis_map); 2271 bus_dmamap_destroy(sc->sis_tag, 2272 sc->sis_ldata.sis_tx_list[i].sis_map); 2273 m_freem(sc->sis_ldata.sis_tx_list[i].sis_mbuf); 2274 sc->sis_ldata.sis_tx_list[i].sis_mbuf = NULL; 2275 } 2276 } 2277 2278 bzero(sc->sis_ldata.sis_tx_list, 2279 sizeof(sc->sis_ldata.sis_tx_list)); 2280 2281 SIS_UNLOCK(sc); 2282 2283 return; 2284} 2285 2286/* 2287 * Stop all chip I/O so that the kernel's probe routines don't 2288 * get confused by errant DMAs when rebooting. 2289 */ 2290static void 2291sis_shutdown(dev) 2292 device_t dev; 2293{ 2294 struct sis_softc *sc; 2295 2296 sc = device_get_softc(dev); 2297 SIS_LOCK(sc); 2298 sis_reset(sc); 2299 sis_stop(sc); 2300 SIS_UNLOCK(sc); 2301 2302 return; 2303} 2304