if_sis.c revision 109060
155682Smarkm/* 2233294Sstas * Copyright (c) 1997, 1998, 1999 3233294Sstas * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4233294Sstas * 555682Smarkm * Redistribution and use in source and binary forms, with or without 6233294Sstas * modification, are permitted provided that the following conditions 7233294Sstas * are met: 8233294Sstas * 1. Redistributions of source code must retain the above copyright 955682Smarkm * notice, this list of conditions and the following disclaimer. 10233294Sstas * 2. Redistributions in binary form must reproduce the above copyright 11233294Sstas * notice, this list of conditions and the following disclaimer in the 1255682Smarkm * documentation and/or other materials provided with the distribution. 13233294Sstas * 3. All advertising materials mentioning features or use of this software 14233294Sstas * must display the following acknowledgement: 15233294Sstas * This product includes software developed by Bill Paul. 1655682Smarkm * 4. Neither the name of the author nor the names of any co-contributors 17233294Sstas * may be used to endorse or promote products derived from this software 18233294Sstas * without specific prior written permission. 19233294Sstas * 2055682Smarkm * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21233294Sstas * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22233294Sstas * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23233294Sstas * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24233294Sstas * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25233294Sstas * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26233294Sstas * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27233294Sstas * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28233294Sstas * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29233294Sstas * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30233294Sstas * THE POSSIBILITY OF SUCH DAMAGE. 31233294Sstas * 3255682Smarkm * $FreeBSD: head/sys/pci/if_sis.c 109060 2003-01-10 08:14:07Z mbr $ 3355682Smarkm */ 3455682Smarkm 3555682Smarkm/* 3655682Smarkm * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 3755682Smarkm * available from http://www.sis.com.tw. 38233294Sstas * 3955682Smarkm * This driver also supports the NatSemi DP83815. Datasheets are 4055682Smarkm * available from http://www.national.com. 4155682Smarkm * 4255682Smarkm * Written by Bill Paul <wpaul@ee.columbia.edu> 4355682Smarkm * Electrical Engineering Department 4455682Smarkm * Columbia University, New York City 4555682Smarkm */ 4655682Smarkm 4755682Smarkm/* 4855682Smarkm * The SiS 900 is a fairly simple chip. It uses bus master DMA with 4972445Sassar * simple TX and RX descriptors of 3 longwords in size. The receiver 5055682Smarkm * has a single perfect filter entry for the station address and a 5155682Smarkm * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 5255682Smarkm * transceiver while the 7016 requires an external transceiver chip. 5355682Smarkm * Both chips offer the standard bit-bang MII interface as well as 5455682Smarkm * an enchanced PHY interface which simplifies accessing MII registers. 5555682Smarkm * 5655682Smarkm * The only downside to this chipset is that RX descriptors must be 5755682Smarkm * longword aligned. 58178825Sdfr */ 5955682Smarkm 60178825Sdfr#include <sys/param.h> 6155682Smarkm#include <sys/systm.h> 62178825Sdfr#include <sys/sockio.h> 63178825Sdfr#include <sys/mbuf.h> 64178825Sdfr#include <sys/malloc.h> 6555682Smarkm#include <sys/kernel.h> 6655682Smarkm#include <sys/socket.h> 6755682Smarkm#include <sys/sysctl.h> 6855682Smarkm 6955682Smarkm#include <net/if.h> 7055682Smarkm#include <net/if_arp.h> 7155682Smarkm#include <net/ethernet.h> 7255682Smarkm#include <net/if_dl.h> 7355682Smarkm#include <net/if_media.h> 7455682Smarkm#include <net/if_types.h> 7555682Smarkm#include <net/if_vlan_var.h> 7655682Smarkm 7755682Smarkm#include <net/bpf.h> 7855682Smarkm 7955682Smarkm#include <machine/bus_pio.h> 8055682Smarkm#include <machine/bus_memio.h> 8155682Smarkm#include <machine/bus.h> 8255682Smarkm#include <machine/resource.h> 8355682Smarkm#include <sys/bus.h> 8455682Smarkm#include <sys/rman.h> 8555682Smarkm 8655682Smarkm#include <dev/mii/mii.h> 8755682Smarkm#include <dev/mii/miivar.h> 8855682Smarkm 8955682Smarkm#include <pci/pcireg.h> 9055682Smarkm#include <pci/pcivar.h> 9155682Smarkm 9255682Smarkm#define SIS_USEIOSPACE 9355682Smarkm 9455682Smarkm#include <pci/if_sisreg.h> 9555682Smarkm 9655682SmarkmMODULE_DEPEND(sis, miibus, 1, 1, 1); 9755682Smarkm 9855682Smarkm/* "controller miibus0" required. See GENERIC if you get errors here. */ 9955682Smarkm#include "miibus_if.h" 10055682Smarkm 10155682Smarkm#ifndef lint 10255682Smarkmstatic const char rcsid[] = 10355682Smarkm "$FreeBSD: head/sys/pci/if_sis.c 109060 2003-01-10 08:14:07Z mbr $"; 10455682Smarkm#endif 10555682Smarkm 10655682Smarkm/* 10755682Smarkm * Various supported device vendors/types and their names. 10855682Smarkm */ 10955682Smarkmstatic struct sis_type sis_devs[] = { 11055682Smarkm { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 11155682Smarkm { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 11255682Smarkm { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP83815 10/100BaseTX" }, 11355682Smarkm { 0, 0, NULL } 11455682Smarkm}; 11555682Smarkm 11655682Smarkmstatic int sis_probe (device_t); 11755682Smarkmstatic int sis_attach (device_t); 11855682Smarkmstatic int sis_detach (device_t); 11955682Smarkm 12055682Smarkmstatic int sis_newbuf (struct sis_softc *, 12155682Smarkm struct sis_desc *, struct mbuf *); 12255682Smarkmstatic int sis_encap (struct sis_softc *, 12355682Smarkm struct mbuf *, u_int32_t *); 12455682Smarkmstatic void sis_rxeof (struct sis_softc *); 12555682Smarkmstatic void sis_rxeoc (struct sis_softc *); 12655682Smarkmstatic void sis_txeof (struct sis_softc *); 12755682Smarkmstatic void sis_intr (void *); 12855682Smarkmstatic void sis_tick (void *); 12955682Smarkmstatic void sis_start (struct ifnet *); 13055682Smarkmstatic int sis_ioctl (struct ifnet *, u_long, caddr_t); 13155682Smarkmstatic void sis_init (void *); 13255682Smarkmstatic void sis_stop (struct sis_softc *); 13355682Smarkmstatic void sis_watchdog (struct ifnet *); 13455682Smarkmstatic void sis_shutdown (device_t); 13555682Smarkmstatic int sis_ifmedia_upd (struct ifnet *); 13655682Smarkmstatic void sis_ifmedia_sts (struct ifnet *, struct ifmediareq *); 13755682Smarkm 13855682Smarkmstatic u_int16_t sis_reverse (u_int16_t); 13955682Smarkmstatic void sis_delay (struct sis_softc *); 14055682Smarkmstatic void sis_eeprom_idle (struct sis_softc *); 14155682Smarkmstatic void sis_eeprom_putbyte (struct sis_softc *, int); 14255682Smarkmstatic void sis_eeprom_getword (struct sis_softc *, int, u_int16_t *); 14355682Smarkmstatic void sis_read_eeprom (struct sis_softc *, caddr_t, int, int, int); 14455682Smarkm#ifdef __i386__ 14555682Smarkmstatic void sis_read_cmos (struct sis_softc *, device_t, caddr_t, 14655682Smarkm int, int); 14755682Smarkmstatic void sis_read_mac (struct sis_softc *, device_t, caddr_t); 14855682Smarkmstatic device_t sis_find_bridge (device_t); 14955682Smarkm#endif 15055682Smarkm 15155682Smarkmstatic void sis_mii_sync (struct sis_softc *); 15255682Smarkmstatic void sis_mii_send (struct sis_softc *, u_int32_t, int); 15355682Smarkmstatic int sis_mii_readreg (struct sis_softc *, struct sis_mii_frame *); 15455682Smarkmstatic int sis_mii_writereg (struct sis_softc *, struct sis_mii_frame *); 15555682Smarkmstatic int sis_miibus_readreg (device_t, int, int); 15655682Smarkmstatic int sis_miibus_writereg (device_t, int, int, int); 15755682Smarkmstatic void sis_miibus_statchg (device_t); 15855682Smarkm 15955682Smarkmstatic void sis_setmulti_sis (struct sis_softc *); 16055682Smarkmstatic void sis_setmulti_ns (struct sis_softc *); 16155682Smarkmstatic u_int32_t sis_crc (struct sis_softc *, caddr_t); 16255682Smarkmstatic void sis_reset (struct sis_softc *); 16355682Smarkmstatic int sis_list_rx_init (struct sis_softc *); 16455682Smarkmstatic int sis_list_tx_init (struct sis_softc *); 16555682Smarkm 16655682Smarkmstatic void sis_dma_map_desc_ptr (void *, bus_dma_segment_t *, int, int); 16755682Smarkmstatic void sis_dma_map_desc_next (void *, bus_dma_segment_t *, int, int); 168static void sis_dma_map_ring (void *, bus_dma_segment_t *, int, int); 169#ifdef SIS_USEIOSPACE 170#define SIS_RES SYS_RES_IOPORT 171#define SIS_RID SIS_PCI_LOIO 172#else 173#define SIS_RES SYS_RES_MEMORY 174#define SIS_RID SIS_PCI_LOMEM 175#endif 176 177static device_method_t sis_methods[] = { 178 /* Device interface */ 179 DEVMETHOD(device_probe, sis_probe), 180 DEVMETHOD(device_attach, sis_attach), 181 DEVMETHOD(device_detach, sis_detach), 182 DEVMETHOD(device_shutdown, sis_shutdown), 183 184 /* bus interface */ 185 DEVMETHOD(bus_print_child, bus_generic_print_child), 186 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 187 188 /* MII interface */ 189 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 190 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 191 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 192 193 { 0, 0 } 194}; 195 196static driver_t sis_driver = { 197 "sis", 198 sis_methods, 199 sizeof(struct sis_softc) 200}; 201 202static devclass_t sis_devclass; 203 204DRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, 0, 0); 205DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 206 207#define SIS_SETBIT(sc, reg, x) \ 208 CSR_WRITE_4(sc, reg, \ 209 CSR_READ_4(sc, reg) | (x)) 210 211#define SIS_CLRBIT(sc, reg, x) \ 212 CSR_WRITE_4(sc, reg, \ 213 CSR_READ_4(sc, reg) & ~(x)) 214 215#define SIO_SET(x) \ 216 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 217 218#define SIO_CLR(x) \ 219 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 220 221static void 222sis_dma_map_desc_next(arg, segs, nseg, error) 223 void *arg; 224 bus_dma_segment_t *segs; 225 int nseg, error; 226{ 227 struct sis_desc *r; 228 229 r = arg; 230 r->sis_next = segs->ds_addr; 231 232 return; 233} 234 235static void 236sis_dma_map_desc_ptr(arg, segs, nseg, error) 237 void *arg; 238 bus_dma_segment_t *segs; 239 int nseg, error; 240{ 241 struct sis_desc *r; 242 243 r = arg; 244 r->sis_ptr = segs->ds_addr; 245 246 return; 247} 248 249static void 250sis_dma_map_ring(arg, segs, nseg, error) 251 void *arg; 252 bus_dma_segment_t *segs; 253 int nseg, error; 254{ 255 u_int32_t *p; 256 257 p = arg; 258 *p = segs->ds_addr; 259 260 return; 261} 262 263/* 264 * Routine to reverse the bits in a word. Stolen almost 265 * verbatim from /usr/games/fortune. 266 */ 267static u_int16_t 268sis_reverse(n) 269 u_int16_t n; 270{ 271 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 272 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 273 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 274 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 275 276 return(n); 277} 278 279static void 280sis_delay(sc) 281 struct sis_softc *sc; 282{ 283 int idx; 284 285 for (idx = (300 / 33) + 1; idx > 0; idx--) 286 CSR_READ_4(sc, SIS_CSR); 287 288 return; 289} 290 291static void 292sis_eeprom_idle(sc) 293 struct sis_softc *sc; 294{ 295 register int i; 296 297 SIO_SET(SIS_EECTL_CSEL); 298 sis_delay(sc); 299 SIO_SET(SIS_EECTL_CLK); 300 sis_delay(sc); 301 302 for (i = 0; i < 25; i++) { 303 SIO_CLR(SIS_EECTL_CLK); 304 sis_delay(sc); 305 SIO_SET(SIS_EECTL_CLK); 306 sis_delay(sc); 307 } 308 309 SIO_CLR(SIS_EECTL_CLK); 310 sis_delay(sc); 311 SIO_CLR(SIS_EECTL_CSEL); 312 sis_delay(sc); 313 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 314 315 return; 316} 317 318/* 319 * Send a read command and address to the EEPROM, check for ACK. 320 */ 321static void 322sis_eeprom_putbyte(sc, addr) 323 struct sis_softc *sc; 324 int addr; 325{ 326 register int d, i; 327 328 d = addr | SIS_EECMD_READ; 329 330 /* 331 * Feed in each bit and stobe the clock. 332 */ 333 for (i = 0x400; i; i >>= 1) { 334 if (d & i) { 335 SIO_SET(SIS_EECTL_DIN); 336 } else { 337 SIO_CLR(SIS_EECTL_DIN); 338 } 339 sis_delay(sc); 340 SIO_SET(SIS_EECTL_CLK); 341 sis_delay(sc); 342 SIO_CLR(SIS_EECTL_CLK); 343 sis_delay(sc); 344 } 345 346 return; 347} 348 349/* 350 * Read a word of data stored in the EEPROM at address 'addr.' 351 */ 352static void 353sis_eeprom_getword(sc, addr, dest) 354 struct sis_softc *sc; 355 int addr; 356 u_int16_t *dest; 357{ 358 register int i; 359 u_int16_t word = 0; 360 361 /* Force EEPROM to idle state. */ 362 sis_eeprom_idle(sc); 363 364 /* Enter EEPROM access mode. */ 365 sis_delay(sc); 366 SIO_CLR(SIS_EECTL_CLK); 367 sis_delay(sc); 368 SIO_SET(SIS_EECTL_CSEL); 369 sis_delay(sc); 370 371 /* 372 * Send address of word we want to read. 373 */ 374 sis_eeprom_putbyte(sc, addr); 375 376 /* 377 * Start reading bits from EEPROM. 378 */ 379 for (i = 0x8000; i; i >>= 1) { 380 SIO_SET(SIS_EECTL_CLK); 381 sis_delay(sc); 382 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 383 word |= i; 384 sis_delay(sc); 385 SIO_CLR(SIS_EECTL_CLK); 386 sis_delay(sc); 387 } 388 389 /* Turn off EEPROM access mode. */ 390 sis_eeprom_idle(sc); 391 392 *dest = word; 393 394 return; 395} 396 397/* 398 * Read a sequence of words from the EEPROM. 399 */ 400static void 401sis_read_eeprom(sc, dest, off, cnt, swap) 402 struct sis_softc *sc; 403 caddr_t dest; 404 int off; 405 int cnt; 406 int swap; 407{ 408 int i; 409 u_int16_t word = 0, *ptr; 410 411 for (i = 0; i < cnt; i++) { 412 sis_eeprom_getword(sc, off + i, &word); 413 ptr = (u_int16_t *)(dest + (i * 2)); 414 if (swap) 415 *ptr = ntohs(word); 416 else 417 *ptr = word; 418 } 419 420 return; 421} 422 423#ifdef __i386__ 424static device_t 425sis_find_bridge(dev) 426 device_t dev; 427{ 428 devclass_t pci_devclass; 429 device_t *pci_devices; 430 int pci_count = 0; 431 device_t *pci_children; 432 int pci_childcount = 0; 433 device_t *busp, *childp; 434 device_t child = NULL; 435 int i, j; 436 437 if ((pci_devclass = devclass_find("pci")) == NULL) 438 return(NULL); 439 440 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 441 442 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 443 pci_childcount = 0; 444 device_get_children(*busp, &pci_children, &pci_childcount); 445 for (j = 0, childp = pci_children; 446 j < pci_childcount; j++, childp++) { 447 if (pci_get_vendor(*childp) == SIS_VENDORID && 448 pci_get_device(*childp) == 0x0008) { 449 child = *childp; 450 goto done; 451 } 452 } 453 } 454 455done: 456 free(pci_devices, M_TEMP); 457 free(pci_children, M_TEMP); 458 return(child); 459} 460 461static void 462sis_read_cmos(sc, dev, dest, off, cnt) 463 struct sis_softc *sc; 464 device_t dev; 465 caddr_t dest; 466 int off; 467 int cnt; 468{ 469 device_t bridge; 470 u_int8_t reg; 471 int i; 472 bus_space_tag_t btag; 473 474 bridge = sis_find_bridge(dev); 475 if (bridge == NULL) 476 return; 477 reg = pci_read_config(bridge, 0x48, 1); 478 pci_write_config(bridge, 0x48, reg|0x40, 1); 479 480 /* XXX */ 481 btag = I386_BUS_SPACE_IO; 482 483 for (i = 0; i < cnt; i++) { 484 bus_space_write_1(btag, 0x0, 0x70, i + off); 485 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 486 } 487 488 pci_write_config(bridge, 0x48, reg & ~0x40, 1); 489 return; 490} 491 492static void 493sis_read_mac(sc, dev, dest) 494 struct sis_softc *sc; 495 device_t dev; 496 caddr_t dest; 497{ 498 u_int32_t filtsave, csrsave; 499 500 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 501 csrsave = CSR_READ_4(sc, SIS_CSR); 502 503 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 504 CSR_WRITE_4(sc, SIS_CSR, 0); 505 506 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 507 508 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 509 ((u_int16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 510 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 511 ((u_int16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 512 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 513 ((u_int16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 514 515 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 516 CSR_WRITE_4(sc, SIS_CSR, csrsave); 517 return; 518} 519#endif 520 521/* 522 * Sync the PHYs by setting data bit and strobing the clock 32 times. 523 */ 524static void sis_mii_sync(sc) 525 struct sis_softc *sc; 526{ 527 register int i; 528 529 SIO_SET(SIS_MII_DIR|SIS_MII_DATA); 530 531 for (i = 0; i < 32; i++) { 532 SIO_SET(SIS_MII_CLK); 533 DELAY(1); 534 SIO_CLR(SIS_MII_CLK); 535 DELAY(1); 536 } 537 538 return; 539} 540 541/* 542 * Clock a series of bits through the MII. 543 */ 544static void sis_mii_send(sc, bits, cnt) 545 struct sis_softc *sc; 546 u_int32_t bits; 547 int cnt; 548{ 549 int i; 550 551 SIO_CLR(SIS_MII_CLK); 552 553 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 554 if (bits & i) { 555 SIO_SET(SIS_MII_DATA); 556 } else { 557 SIO_CLR(SIS_MII_DATA); 558 } 559 DELAY(1); 560 SIO_CLR(SIS_MII_CLK); 561 DELAY(1); 562 SIO_SET(SIS_MII_CLK); 563 } 564} 565 566/* 567 * Read an PHY register through the MII. 568 */ 569static int sis_mii_readreg(sc, frame) 570 struct sis_softc *sc; 571 struct sis_mii_frame *frame; 572 573{ 574 int i, ack, s; 575 576 s = splimp(); 577 578 /* 579 * Set up frame for RX. 580 */ 581 frame->mii_stdelim = SIS_MII_STARTDELIM; 582 frame->mii_opcode = SIS_MII_READOP; 583 frame->mii_turnaround = 0; 584 frame->mii_data = 0; 585 586 /* 587 * Turn on data xmit. 588 */ 589 SIO_SET(SIS_MII_DIR); 590 591 sis_mii_sync(sc); 592 593 /* 594 * Send command/address info. 595 */ 596 sis_mii_send(sc, frame->mii_stdelim, 2); 597 sis_mii_send(sc, frame->mii_opcode, 2); 598 sis_mii_send(sc, frame->mii_phyaddr, 5); 599 sis_mii_send(sc, frame->mii_regaddr, 5); 600 601 /* Idle bit */ 602 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA)); 603 DELAY(1); 604 SIO_SET(SIS_MII_CLK); 605 DELAY(1); 606 607 /* Turn off xmit. */ 608 SIO_CLR(SIS_MII_DIR); 609 610 /* Check for ack */ 611 SIO_CLR(SIS_MII_CLK); 612 DELAY(1); 613 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA; 614 SIO_SET(SIS_MII_CLK); 615 DELAY(1); 616 617 /* 618 * Now try reading data bits. If the ack failed, we still 619 * need to clock through 16 cycles to keep the PHY(s) in sync. 620 */ 621 if (ack) { 622 for(i = 0; i < 16; i++) { 623 SIO_CLR(SIS_MII_CLK); 624 DELAY(1); 625 SIO_SET(SIS_MII_CLK); 626 DELAY(1); 627 } 628 goto fail; 629 } 630 631 for (i = 0x8000; i; i >>= 1) { 632 SIO_CLR(SIS_MII_CLK); 633 DELAY(1); 634 if (!ack) { 635 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA) 636 frame->mii_data |= i; 637 DELAY(1); 638 } 639 SIO_SET(SIS_MII_CLK); 640 DELAY(1); 641 } 642 643fail: 644 645 SIO_CLR(SIS_MII_CLK); 646 DELAY(1); 647 SIO_SET(SIS_MII_CLK); 648 DELAY(1); 649 650 splx(s); 651 652 if (ack) 653 return(1); 654 return(0); 655} 656 657/* 658 * Write to a PHY register through the MII. 659 */ 660static int sis_mii_writereg(sc, frame) 661 struct sis_softc *sc; 662 struct sis_mii_frame *frame; 663 664{ 665 int s; 666 667 s = splimp(); 668 /* 669 * Set up frame for TX. 670 */ 671 672 frame->mii_stdelim = SIS_MII_STARTDELIM; 673 frame->mii_opcode = SIS_MII_WRITEOP; 674 frame->mii_turnaround = SIS_MII_TURNAROUND; 675 676 /* 677 * Turn on data output. 678 */ 679 SIO_SET(SIS_MII_DIR); 680 681 sis_mii_sync(sc); 682 683 sis_mii_send(sc, frame->mii_stdelim, 2); 684 sis_mii_send(sc, frame->mii_opcode, 2); 685 sis_mii_send(sc, frame->mii_phyaddr, 5); 686 sis_mii_send(sc, frame->mii_regaddr, 5); 687 sis_mii_send(sc, frame->mii_turnaround, 2); 688 sis_mii_send(sc, frame->mii_data, 16); 689 690 /* Idle bit. */ 691 SIO_SET(SIS_MII_CLK); 692 DELAY(1); 693 SIO_CLR(SIS_MII_CLK); 694 DELAY(1); 695 696 /* 697 * Turn off xmit. 698 */ 699 SIO_CLR(SIS_MII_DIR); 700 701 splx(s); 702 703 return(0); 704} 705 706static int 707sis_miibus_readreg(dev, phy, reg) 708 device_t dev; 709 int phy, reg; 710{ 711 struct sis_softc *sc; 712 struct sis_mii_frame frame; 713 714 sc = device_get_softc(dev); 715 716 if (sc->sis_type == SIS_TYPE_83815) { 717 if (phy != 0) 718 return(0); 719 /* 720 * The NatSemi chip can take a while after 721 * a reset to come ready, during which the BMSR 722 * returns a value of 0. This is *never* supposed 723 * to happen: some of the BMSR bits are meant to 724 * be hardwired in the on position, and this can 725 * confuse the miibus code a bit during the probe 726 * and attach phase. So we make an effort to check 727 * for this condition and wait for it to clear. 728 */ 729 if (!CSR_READ_4(sc, NS_BMSR)) 730 DELAY(1000); 731 return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 732 } 733 734 if (sc->sis_type == SIS_TYPE_900 && 735 sc->sis_rev < SIS_REV_635 && phy != 0) 736 return(0); 737 738 bzero((char *)&frame, sizeof(frame)); 739 740 frame.mii_phyaddr = phy; 741 frame.mii_regaddr = reg; 742 sis_mii_readreg(sc, &frame); 743 744 return(frame.mii_data); 745} 746 747static int 748sis_miibus_writereg(dev, phy, reg, data) 749 device_t dev; 750 int phy, reg, data; 751{ 752 struct sis_softc *sc; 753 struct sis_mii_frame frame; 754 755 sc = device_get_softc(dev); 756 757 if (sc->sis_type == SIS_TYPE_83815) { 758 if (phy != 0) 759 return(0); 760 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 761 return(0); 762 } 763 764 if (sc->sis_type == SIS_TYPE_900 && phy != 0) 765 return(0); 766 767 bzero((char *)&frame, sizeof(frame)); 768 769 frame.mii_phyaddr = phy; 770 frame.mii_regaddr = reg; 771 frame.mii_data = data; 772 773 sis_mii_writereg(sc, &frame); 774 775 return(0); 776} 777 778static void 779sis_miibus_statchg(dev) 780 device_t dev; 781{ 782 struct sis_softc *sc; 783 784 sc = device_get_softc(dev); 785 sis_init(sc); 786 787 return; 788} 789 790static u_int32_t 791sis_crc(sc, addr) 792 struct sis_softc *sc; 793 caddr_t addr; 794{ 795 u_int32_t crc, carry; 796 int i, j; 797 u_int8_t c; 798 799 /* Compute CRC for the address value. */ 800 crc = 0xFFFFFFFF; /* initial value */ 801 802 for (i = 0; i < 6; i++) { 803 c = *(addr + i); 804 for (j = 0; j < 8; j++) { 805 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 806 crc <<= 1; 807 c >>= 1; 808 if (carry) 809 crc = (crc ^ 0x04c11db6) | carry; 810 } 811 } 812 813 /* 814 * return the filter bit position 815 * 816 * The NatSemi chip has a 512-bit filter, which is 817 * different than the SiS, so we special-case it. 818 */ 819 if (sc->sis_type == SIS_TYPE_83815) 820 return (crc >> 23); 821 822 if (sc->sis_rev >= SIS_REV_635) 823 return (crc >> 24); 824 825 return (crc >> 25); 826} 827 828static void 829sis_setmulti_ns(sc) 830 struct sis_softc *sc; 831{ 832 struct ifnet *ifp; 833 struct ifmultiaddr *ifma; 834 u_int32_t h = 0, i, filtsave; 835 int bit, index; 836 837 ifp = &sc->arpcom.ac_if; 838 839 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 840 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 841 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 842 return; 843 } 844 845 /* 846 * We have to explicitly enable the multicast hash table 847 * on the NatSemi chip if we want to use it, which we do. 848 */ 849 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 850 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 851 852 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 853 854 /* first, zot all the existing hash bits */ 855 for (i = 0; i < 32; i++) { 856 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 857 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 858 } 859 860 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 861 if (ifma->ifma_addr->sa_family != AF_LINK) 862 continue; 863 h = sis_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 864 index = h >> 3; 865 bit = h & 0x1F; 866 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 867 if (bit > 0xF) 868 bit -= 0x10; 869 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 870 } 871 872 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 873 874 return; 875} 876 877static void 878sis_setmulti_sis(sc) 879 struct sis_softc *sc; 880{ 881 struct ifnet *ifp; 882 struct ifmultiaddr *ifma; 883 u_int32_t h, i, n, ctl; 884 u_int16_t hashes[16]; 885 886 ifp = &sc->arpcom.ac_if; 887 888 /* hash table size */ 889 n = sc->sis_rev >= SIS_REV_635 ? 16 : 8; 890 891 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE; 892 893 if (ifp->if_flags & IFF_BROADCAST) 894 ctl |= SIS_RXFILTCTL_BROAD; 895 896 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 897 ctl |= SIS_RXFILTCTL_ALLMULTI; 898 if (ifp->if_flags & IFF_PROMISC) 899 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS; 900 for (i = 0; i < n; i++) 901 hashes[i] = ~0; 902 } else { 903 for (i = 0; i < n; i++) 904 hashes[i] = 0; 905 i = 0; 906 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 907 if (ifma->ifma_addr->sa_family != AF_LINK) 908 continue; 909 h = sis_crc(sc, 910 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 911 hashes[h >> 4] |= 1 << (h & 0xf); 912 i++; 913 } 914 if (i > n) { 915 ctl |= SIS_RXFILTCTL_ALLMULTI; 916 for (i = 0; i < n; i++) 917 hashes[i] = ~0; 918 } 919 } 920 921 for (i = 0; i < n; i++) { 922 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); 923 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); 924 } 925 926 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl); 927} 928 929static void 930sis_reset(sc) 931 struct sis_softc *sc; 932{ 933 register int i; 934 935 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 936 937 for (i = 0; i < SIS_TIMEOUT; i++) { 938 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 939 break; 940 } 941 942 if (i == SIS_TIMEOUT) 943 printf("sis%d: reset never completed\n", sc->sis_unit); 944 945 /* Wait a little while for the chip to get its brains in order. */ 946 DELAY(1000); 947 948 /* 949 * If this is a NetSemi chip, make sure to clear 950 * PME mode. 951 */ 952 if (sc->sis_type == SIS_TYPE_83815) { 953 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 954 CSR_WRITE_4(sc, NS_CLKRUN, 0); 955 } 956 957 return; 958} 959 960/* 961 * Probe for an SiS chip. Check the PCI vendor and device 962 * IDs against our list and return a device name if we find a match. 963 */ 964static int 965sis_probe(dev) 966 device_t dev; 967{ 968 struct sis_type *t; 969 970 t = sis_devs; 971 972 while(t->sis_name != NULL) { 973 if ((pci_get_vendor(dev) == t->sis_vid) && 974 (pci_get_device(dev) == t->sis_did)) { 975 device_set_desc(dev, t->sis_name); 976 return(0); 977 } 978 t++; 979 } 980 981 return(ENXIO); 982} 983 984/* 985 * Attach the interface. Allocate softc structures, do ifmedia 986 * setup and ethernet/BPF attach. 987 */ 988static int 989sis_attach(dev) 990 device_t dev; 991{ 992 u_char eaddr[ETHER_ADDR_LEN]; 993 u_int32_t command; 994 struct sis_softc *sc; 995 struct ifnet *ifp; 996 int unit, error = 0, rid; 997 998 sc = device_get_softc(dev); 999 unit = device_get_unit(dev); 1000 bzero(sc, sizeof(struct sis_softc)); 1001 1002 mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1003 MTX_DEF | MTX_RECURSE); 1004 1005 if (pci_get_device(dev) == SIS_DEVICEID_900) 1006 sc->sis_type = SIS_TYPE_900; 1007 if (pci_get_device(dev) == SIS_DEVICEID_7016) 1008 sc->sis_type = SIS_TYPE_7016; 1009 if (pci_get_vendor(dev) == NS_VENDORID) 1010 sc->sis_type = SIS_TYPE_83815; 1011 1012 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 1013 1014 /* 1015 * Handle power management nonsense. 1016 */ 1017 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1018 u_int32_t iobase, membase, irq; 1019 1020 /* Save important PCI config data. */ 1021 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4); 1022 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4); 1023 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4); 1024 1025 /* Reset the power state. */ 1026 printf("sis%d: chip is in D%d power mode " 1027 "-- setting to D0\n", unit, 1028 pci_get_powerstate(dev)); 1029 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1030 1031 /* Restore PCI config data. */ 1032 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4); 1033 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4); 1034 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4); 1035 } 1036 1037 /* 1038 * Map control/status registers. 1039 */ 1040 pci_enable_busmaster(dev); 1041 pci_enable_io(dev, SYS_RES_IOPORT); 1042 pci_enable_io(dev, SYS_RES_MEMORY); 1043 command = pci_read_config(dev, PCIR_COMMAND, 4); 1044 1045#ifdef SIS_USEIOSPACE 1046 if (!(command & PCIM_CMD_PORTEN)) { 1047 printf("sis%d: failed to enable I/O ports!\n", unit); 1048 error = ENXIO;; 1049 goto fail; 1050 } 1051#else 1052 if (!(command & PCIM_CMD_MEMEN)) { 1053 printf("sis%d: failed to enable memory mapping!\n", unit); 1054 error = ENXIO;; 1055 goto fail; 1056 } 1057#endif 1058 1059 rid = SIS_RID; 1060 sc->sis_res = bus_alloc_resource(dev, SIS_RES, &rid, 1061 0, ~0, 1, RF_ACTIVE); 1062 1063 if (sc->sis_res == NULL) { 1064 printf("sis%d: couldn't map ports/memory\n", unit); 1065 error = ENXIO; 1066 goto fail; 1067 } 1068 1069 sc->sis_btag = rman_get_bustag(sc->sis_res); 1070 sc->sis_bhandle = rman_get_bushandle(sc->sis_res); 1071 1072 /* Allocate interrupt */ 1073 rid = 0; 1074 sc->sis_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1075 RF_SHAREABLE | RF_ACTIVE); 1076 1077 if (sc->sis_irq == NULL) { 1078 printf("sis%d: couldn't map interrupt\n", unit); 1079 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1080 error = ENXIO; 1081 goto fail; 1082 } 1083 1084 error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET, 1085 sis_intr, sc, &sc->sis_intrhand); 1086 1087 if (error) { 1088 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1089 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1090 printf("sis%d: couldn't set up irq\n", unit); 1091 goto fail; 1092 } 1093 1094 /* Reset the adapter. */ 1095 sis_reset(sc); 1096 1097 /* 1098 * Get station address from the EEPROM. 1099 */ 1100 switch (pci_get_vendor(dev)) { 1101 case NS_VENDORID: 1102 /* 1103 * Reading the MAC address out of the EEPROM on 1104 * the NatSemi chip takes a bit more work than 1105 * you'd expect. The address spans 4 16-bit words, 1106 * with the first word containing only a single bit. 1107 * You have to shift everything over one bit to 1108 * get it aligned properly. Also, the bits are 1109 * stored backwards (the LSB is really the MSB, 1110 * and so on) so you have to reverse them in order 1111 * to get the MAC address into the form we want. 1112 * Why? Who the hell knows. 1113 */ 1114 { 1115 u_int16_t tmp[4]; 1116 1117 sis_read_eeprom(sc, (caddr_t)&tmp, 1118 NS_EE_NODEADDR, 4, 0); 1119 1120 /* Shift everything over one bit. */ 1121 tmp[3] = tmp[3] >> 1; 1122 tmp[3] |= tmp[2] << 15; 1123 tmp[2] = tmp[2] >> 1; 1124 tmp[2] |= tmp[1] << 15; 1125 tmp[1] = tmp[1] >> 1; 1126 tmp[1] |= tmp[0] << 15; 1127 1128 /* Now reverse all the bits. */ 1129 tmp[3] = sis_reverse(tmp[3]); 1130 tmp[2] = sis_reverse(tmp[2]); 1131 tmp[1] = sis_reverse(tmp[1]); 1132 1133 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); 1134 } 1135 break; 1136 case SIS_VENDORID: 1137 default: 1138#ifdef __i386__ 1139 /* 1140 * If this is a SiS 630E chipset with an embedded 1141 * SiS 900 controller, we have to read the MAC address 1142 * from the APC CMOS RAM. Our method for doing this 1143 * is very ugly since we have to reach out and grab 1144 * ahold of hardware for which we cannot properly 1145 * allocate resources. This code is only compiled on 1146 * the i386 architecture since the SiS 630E chipset 1147 * is for x86 motherboards only. Note that there are 1148 * a lot of magic numbers in this hack. These are 1149 * taken from SiS's Linux driver. I'd like to replace 1150 * them with proper symbolic definitions, but that 1151 * requires some datasheets that I don't have access 1152 * to at the moment. 1153 */ 1154 if (sc->sis_rev == SIS_REV_630S || 1155 sc->sis_rev == SIS_REV_630E || 1156 sc->sis_rev == SIS_REV_630EA1) 1157 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 1158 1159 else if (sc->sis_rev == SIS_REV_635 || 1160 sc->sis_rev == SIS_REV_630ET) 1161 sis_read_mac(sc, dev, (caddr_t)&eaddr); 1162 else 1163#endif 1164 sis_read_eeprom(sc, (caddr_t)&eaddr, 1165 SIS_EE_NODEADDR, 3, 0); 1166 break; 1167 } 1168 1169 /* 1170 * A SiS chip was detected. Inform the world. 1171 */ 1172 printf("sis%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1173 1174 sc->sis_unit = unit; 1175 callout_handle_init(&sc->sis_stat_ch); 1176 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1177 1178 /* 1179 * Allocate the parent bus DMA tag appropriate for PCI. 1180 */ 1181#define SIS_NSEG_NEW 32 1182 error = bus_dma_tag_create(NULL, /* parent */ 1183 1, 0, /* alignment, boundary */ 1184 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1185 BUS_SPACE_MAXADDR, /* highaddr */ 1186 NULL, NULL, /* filter, filterarg */ 1187 MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */ 1188 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1189 BUS_DMA_ALLOCNOW, /* flags */ 1190 &sc->sis_parent_tag); 1191 1192 /* 1193 * Now allocate a tag for the DMA descriptor lists. 1194 * All of our lists are allocated as a contiguous block 1195 * of memory. 1196 */ 1197 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1198 1, 0, /* alignment, boundary */ 1199 BUS_SPACE_MAXADDR, /* lowaddr */ 1200 BUS_SPACE_MAXADDR, /* highaddr */ 1201 NULL, NULL, /* filter, filterarg */ 1202 SIS_RX_LIST_SZ, 1, /* maxsize,nsegments */ 1203 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1204 0, /* flags */ 1205 &sc->sis_ldata.sis_rx_tag); 1206 1207 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1208 1, 0, /* alignment, boundary */ 1209 BUS_SPACE_MAXADDR, /* lowaddr */ 1210 BUS_SPACE_MAXADDR, /* highaddr */ 1211 NULL, NULL, /* filter, filterarg */ 1212 SIS_TX_LIST_SZ, 1, /* maxsize,nsegments */ 1213 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1214 0, /* flags */ 1215 &sc->sis_ldata.sis_tx_tag); 1216 1217 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1218 1, 0, /* alignment, boundary */ 1219 BUS_SPACE_MAXADDR, /* lowaddr */ 1220 BUS_SPACE_MAXADDR, /* highaddr */ 1221 NULL, NULL, /* filter, filterarg */ 1222 MCLBYTES, 1, /* maxsize,nsegments */ 1223 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1224 0, /* flags */ 1225 &sc->sis_tag); 1226 1227 /* 1228 * Now allocate a chunk of DMA-able memory based on the 1229 * tag we just created. 1230 */ 1231 error = bus_dmamem_alloc(sc->sis_ldata.sis_tx_tag, 1232 (void **)&sc->sis_ldata.sis_tx_list, BUS_DMA_NOWAIT, 1233 &sc->sis_ldata.sis_tx_dmamap); 1234 1235 if (error) { 1236 printf("sis%d: no memory for list buffers!\n", unit); 1237 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1238 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1239 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1240 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1241 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1242 error = ENXIO; 1243 goto fail; 1244 } 1245 1246 error = bus_dmamem_alloc(sc->sis_ldata.sis_rx_tag, 1247 (void **)&sc->sis_ldata.sis_rx_list, BUS_DMA_NOWAIT, 1248 &sc->sis_ldata.sis_rx_dmamap); 1249 1250 if (error) { 1251 printf("sis%d: no memory for list buffers!\n", unit); 1252 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1253 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1254 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1255 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1256 sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 1257 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1258 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1259 error = ENXIO; 1260 goto fail; 1261 } 1262 1263 1264 bzero(sc->sis_ldata.sis_tx_list, SIS_TX_LIST_SZ); 1265 bzero(sc->sis_ldata.sis_rx_list, SIS_RX_LIST_SZ); 1266 1267 /* 1268 * Obtain the physical addresses of the RX and TX 1269 * rings which we'll need later in the init routine. 1270 */ 1271 bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1272 sc->sis_ldata.sis_tx_dmamap, &(sc->sis_ldata.sis_tx_list[0]), 1273 sizeof(struct sis_desc), sis_dma_map_ring, 1274 &sc->sis_cdata.sis_tx_paddr, 0); 1275 bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1276 sc->sis_ldata.sis_rx_dmamap, &(sc->sis_ldata.sis_rx_list[0]), 1277 sizeof(struct sis_desc), sis_dma_map_ring, 1278 &sc->sis_cdata.sis_rx_paddr, 0); 1279 1280 ifp = &sc->arpcom.ac_if; 1281 ifp->if_softc = sc; 1282 ifp->if_unit = unit; 1283 ifp->if_name = "sis"; 1284 ifp->if_mtu = ETHERMTU; 1285 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1286 ifp->if_ioctl = sis_ioctl; 1287 ifp->if_output = ether_output; 1288 ifp->if_start = sis_start; 1289 ifp->if_watchdog = sis_watchdog; 1290 ifp->if_init = sis_init; 1291 ifp->if_baudrate = 10000000; 1292 ifp->if_snd.ifq_maxlen = SIS_TX_LIST_CNT - 1; 1293 1294 /* 1295 * Do MII setup. 1296 */ 1297 if (mii_phy_probe(dev, &sc->sis_miibus, 1298 sis_ifmedia_upd, sis_ifmedia_sts)) { 1299 printf("sis%d: MII without any PHY!\n", sc->sis_unit); 1300 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1301 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1302 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1303 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1304 sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap); 1305 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1306 sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 1307 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1308 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1309 error = ENXIO; 1310 goto fail; 1311 } 1312 1313 /* 1314 * Call MI attach routine. 1315 */ 1316 ether_ifattach(ifp, eaddr); 1317 1318 /* 1319 * Tell the upper layer(s) we support long frames. 1320 */ 1321 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1322 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1323 1324 callout_handle_init(&sc->sis_stat_ch); 1325 return(0); 1326 1327fail: 1328 mtx_destroy(&sc->sis_mtx); 1329 return(error); 1330} 1331 1332static int 1333sis_detach(dev) 1334 device_t dev; 1335{ 1336 struct sis_softc *sc; 1337 struct ifnet *ifp; 1338 1339 1340 sc = device_get_softc(dev); 1341 SIS_LOCK(sc); 1342 ifp = &sc->arpcom.ac_if; 1343 1344 sis_reset(sc); 1345 sis_stop(sc); 1346 ether_ifdetach(ifp); 1347 1348 bus_generic_detach(dev); 1349 device_delete_child(dev, sc->sis_miibus); 1350 1351 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1352 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1353 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1354 1355 bus_dmamap_unload(sc->sis_ldata.sis_rx_tag, 1356 sc->sis_ldata.sis_rx_dmamap); 1357 bus_dmamap_unload(sc->sis_ldata.sis_tx_tag, 1358 sc->sis_ldata.sis_tx_dmamap); 1359 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1360 sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap); 1361 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1362 sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); 1363 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1364 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1365 bus_dma_tag_destroy(sc->sis_parent_tag); 1366 1367 SIS_UNLOCK(sc); 1368 mtx_destroy(&sc->sis_mtx); 1369 1370 return(0); 1371} 1372 1373/* 1374 * Initialize the transmit descriptors. 1375 */ 1376static int 1377sis_list_tx_init(sc) 1378 struct sis_softc *sc; 1379{ 1380 struct sis_list_data *ld; 1381 struct sis_ring_data *cd; 1382 int i, nexti; 1383 1384 cd = &sc->sis_cdata; 1385 ld = &sc->sis_ldata; 1386 1387 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1388 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1; 1389 ld->sis_tx_list[i].sis_nextdesc = 1390 &ld->sis_tx_list[nexti]; 1391 bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1392 sc->sis_ldata.sis_tx_dmamap, 1393 &ld->sis_tx_list[nexti], sizeof(struct sis_desc), 1394 sis_dma_map_desc_next, &ld->sis_tx_list[i], 0); 1395 ld->sis_tx_list[i].sis_mbuf = NULL; 1396 ld->sis_tx_list[i].sis_ptr = 0; 1397 ld->sis_tx_list[i].sis_ctl = 0; 1398 } 1399 1400 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0; 1401 1402 bus_dmamap_sync(sc->sis_ldata.sis_tx_tag, 1403 sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 1404 1405 return(0); 1406} 1407 1408/* 1409 * Initialize the RX descriptors and allocate mbufs for them. Note that 1410 * we arrange the descriptors in a closed ring, so that the last descriptor 1411 * points back to the first. 1412 */ 1413static int 1414sis_list_rx_init(sc) 1415 struct sis_softc *sc; 1416{ 1417 struct sis_list_data *ld; 1418 struct sis_ring_data *cd; 1419 int i,nexti; 1420 1421 ld = &sc->sis_ldata; 1422 cd = &sc->sis_cdata; 1423 1424 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1425 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS) 1426 return(ENOBUFS); 1427 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1; 1428 ld->sis_rx_list[i].sis_nextdesc = 1429 &ld->sis_rx_list[nexti]; 1430 bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1431 sc->sis_ldata.sis_rx_dmamap, 1432 &ld->sis_rx_list[nexti], 1433 sizeof(struct sis_desc), sis_dma_map_desc_next, 1434 &ld->sis_rx_list[i], 0); 1435 } 1436 1437 bus_dmamap_sync(sc->sis_ldata.sis_rx_tag, 1438 sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE); 1439 1440 cd->sis_rx_prod = 0; 1441 1442 return(0); 1443} 1444 1445/* 1446 * Initialize an RX descriptor and attach an MBUF cluster. 1447 */ 1448static int 1449sis_newbuf(sc, c, m) 1450 struct sis_softc *sc; 1451 struct sis_desc *c; 1452 struct mbuf *m; 1453{ 1454 1455 if (c == NULL) 1456 return(EINVAL); 1457 1458 if (m == NULL) { 1459 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1460 if (m == NULL) 1461 return(ENOBUFS); 1462 } else 1463 m->m_data = m->m_ext.ext_buf; 1464 1465 c->sis_mbuf = m; 1466 c->sis_ctl = SIS_RXLEN; 1467 1468 bus_dmamap_create(sc->sis_tag, 0, &c->sis_map); 1469 bus_dmamap_load(sc->sis_tag, c->sis_map, 1470 mtod(m, void *), MCLBYTES, 1471 sis_dma_map_desc_ptr, c, 0); 1472 bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREWRITE); 1473 1474 return(0); 1475} 1476 1477/* 1478 * A frame has been uploaded: pass the resulting mbuf chain up to 1479 * the higher level protocols. 1480 */ 1481static void 1482sis_rxeof(sc) 1483 struct sis_softc *sc; 1484{ 1485 struct mbuf *m; 1486 struct ifnet *ifp; 1487 struct sis_desc *cur_rx; 1488 int i, total_len = 0; 1489 u_int32_t rxstat; 1490 1491 ifp = &sc->arpcom.ac_if; 1492 i = sc->sis_cdata.sis_rx_prod; 1493 1494 while(SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) { 1495 1496#ifdef DEVICE_POLLING 1497 if (ifp->if_flags & IFF_POLLING) { 1498 if (sc->rxcycles <= 0) 1499 break; 1500 sc->rxcycles--; 1501 } 1502#endif /* DEVICE_POLLING */ 1503 cur_rx = &sc->sis_ldata.sis_rx_list[i]; 1504 rxstat = cur_rx->sis_rxstat; 1505 bus_dmamap_sync(sc->sis_tag, 1506 cur_rx->sis_map, BUS_DMASYNC_POSTWRITE); 1507 bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map); 1508 bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map); 1509 m = cur_rx->sis_mbuf; 1510 cur_rx->sis_mbuf = NULL; 1511 total_len = SIS_RXBYTES(cur_rx); 1512 SIS_INC(i, SIS_RX_LIST_CNT); 1513 1514 /* 1515 * If an error occurs, update stats, clear the 1516 * status word and leave the mbuf cluster in place: 1517 * it should simply get re-used next time this descriptor 1518 * comes up in the ring. 1519 */ 1520 if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 1521 ifp->if_ierrors++; 1522 if (rxstat & SIS_RXSTAT_COLL) 1523 ifp->if_collisions++; 1524 sis_newbuf(sc, cur_rx, m); 1525 continue; 1526 } 1527 1528 /* No errors; receive the packet. */ 1529#ifdef __i386__ 1530 /* 1531 * On the x86 we do not have alignment problems, so try to 1532 * allocate a new buffer for the receive ring, and pass up 1533 * the one where the packet is already, saving the expensive 1534 * copy done in m_devget(). 1535 * If we are on an architecture with alignment problems, or 1536 * if the allocation fails, then use m_devget and leave the 1537 * existing buffer in the receive ring. 1538 */ 1539 if (sis_newbuf(sc, cur_rx, NULL) == 0) 1540 m->m_pkthdr.len = m->m_len = total_len; 1541 else 1542#endif 1543 { 1544 struct mbuf *m0; 1545 m0 = m_devget(mtod(m, char *), total_len, 1546 ETHER_ALIGN, ifp, NULL); 1547 sis_newbuf(sc, cur_rx, m); 1548 if (m0 == NULL) { 1549 ifp->if_ierrors++; 1550 continue; 1551 } 1552 m = m0; 1553 } 1554 1555 ifp->if_ipackets++; 1556 m->m_pkthdr.rcvif = ifp; 1557 1558 (*ifp->if_input)(ifp, m); 1559 } 1560 1561 sc->sis_cdata.sis_rx_prod = i; 1562 1563 return; 1564} 1565 1566static void 1567sis_rxeoc(sc) 1568 struct sis_softc *sc; 1569{ 1570 sis_rxeof(sc); 1571 sis_init(sc); 1572 return; 1573} 1574 1575/* 1576 * A frame was downloaded to the chip. It's safe for us to clean up 1577 * the list buffers. 1578 */ 1579 1580static void 1581sis_txeof(sc) 1582 struct sis_softc *sc; 1583{ 1584 struct ifnet *ifp; 1585 u_int32_t idx; 1586 1587 ifp = &sc->arpcom.ac_if; 1588 1589 /* 1590 * Go through our tx list and free mbufs for those 1591 * frames that have been transmitted. 1592 */ 1593 for (idx = sc->sis_cdata.sis_tx_cons; sc->sis_cdata.sis_tx_cnt > 0; 1594 sc->sis_cdata.sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) { 1595 struct sis_desc *cur_tx = &sc->sis_ldata.sis_tx_list[idx]; 1596 1597 if (SIS_OWNDESC(cur_tx)) 1598 break; 1599 1600 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) 1601 continue; 1602 1603 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 1604 ifp->if_oerrors++; 1605 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 1606 ifp->if_collisions++; 1607 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 1608 ifp->if_collisions++; 1609 } 1610 1611 ifp->if_collisions += 1612 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 1613 1614 ifp->if_opackets++; 1615 if (cur_tx->sis_mbuf != NULL) { 1616 m_freem(cur_tx->sis_mbuf); 1617 cur_tx->sis_mbuf = NULL; 1618 bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map); 1619 bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map); 1620 } 1621 } 1622 1623 if (idx != sc->sis_cdata.sis_tx_cons) { 1624 /* we freed up some buffers */ 1625 sc->sis_cdata.sis_tx_cons = idx; 1626 ifp->if_flags &= ~IFF_OACTIVE; 1627 } 1628 1629 ifp->if_timer = (sc->sis_cdata.sis_tx_cnt == 0) ? 0 : 5; 1630 1631 return; 1632} 1633 1634static void 1635sis_tick(xsc) 1636 void *xsc; 1637{ 1638 struct sis_softc *sc; 1639 struct mii_data *mii; 1640 struct ifnet *ifp; 1641 1642 sc = xsc; 1643 SIS_LOCK(sc); 1644 ifp = &sc->arpcom.ac_if; 1645 1646 mii = device_get_softc(sc->sis_miibus); 1647 mii_tick(mii); 1648 1649 if (!sc->sis_link && mii->mii_media_status & IFM_ACTIVE && 1650 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1651 sc->sis_link++; 1652 if (ifp->if_snd.ifq_head != NULL) 1653 sis_start(ifp); 1654 } 1655 1656 sc->sis_stat_ch = timeout(sis_tick, sc, hz); 1657 1658 SIS_UNLOCK(sc); 1659 1660 return; 1661} 1662 1663#ifdef DEVICE_POLLING 1664static poll_handler_t sis_poll; 1665 1666static void 1667sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1668{ 1669 struct sis_softc *sc = ifp->if_softc; 1670 1671 SIS_LOCK(sc); 1672 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1673 CSR_WRITE_4(sc, SIS_IER, 1); 1674 goto done; 1675 } 1676 1677 /* 1678 * On the sis, reading the status register also clears it. 1679 * So before returning to intr mode we must make sure that all 1680 * possible pending sources of interrupts have been served. 1681 * In practice this means run to completion the *eof routines, 1682 * and then call the interrupt routine 1683 */ 1684 sc->rxcycles = count; 1685 sis_rxeof(sc); 1686 sis_txeof(sc); 1687 if (ifp->if_snd.ifq_head != NULL) 1688 sis_start(ifp); 1689 1690 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1691 u_int32_t status; 1692 1693 /* Reading the ISR register clears all interrupts. */ 1694 status = CSR_READ_4(sc, SIS_ISR); 1695 1696 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 1697 sis_rxeoc(sc); 1698 1699 if (status & (SIS_ISR_RX_IDLE)) 1700 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1701 1702 if (status & SIS_ISR_SYSERR) { 1703 sis_reset(sc); 1704 sis_init(sc); 1705 } 1706 } 1707done: 1708 SIS_UNLOCK(sc); 1709 return; 1710} 1711#endif /* DEVICE_POLLING */ 1712 1713static void 1714sis_intr(arg) 1715 void *arg; 1716{ 1717 struct sis_softc *sc; 1718 struct ifnet *ifp; 1719 u_int32_t status; 1720 1721 sc = arg; 1722 ifp = &sc->arpcom.ac_if; 1723 1724 SIS_LOCK(sc); 1725#ifdef DEVICE_POLLING 1726 if (ifp->if_flags & IFF_POLLING) 1727 goto done; 1728 if (ether_poll_register(sis_poll, ifp)) { /* ok, disable interrupts */ 1729 CSR_WRITE_4(sc, SIS_IER, 0); 1730 goto done; 1731 } 1732#endif /* DEVICE_POLLING */ 1733 1734 /* Supress unwanted interrupts */ 1735 if (!(ifp->if_flags & IFF_UP)) { 1736 sis_stop(sc); 1737 goto done; 1738 } 1739 1740 /* Disable interrupts. */ 1741 CSR_WRITE_4(sc, SIS_IER, 0); 1742 1743 for (;;) { 1744 /* Reading the ISR register clears all interrupts. */ 1745 status = CSR_READ_4(sc, SIS_ISR); 1746 1747 if ((status & SIS_INTRS) == 0) 1748 break; 1749 1750 if (status & 1751 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | 1752 SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) ) 1753 sis_txeof(sc); 1754 1755 if (status & (SIS_ISR_RX_DESC_OK|SIS_ISR_RX_OK|SIS_ISR_RX_IDLE)) 1756 sis_rxeof(sc); 1757 1758 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW)) 1759 sis_rxeoc(sc); 1760 1761 if (status & (SIS_ISR_RX_IDLE)) 1762 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1763 1764 if (status & SIS_ISR_SYSERR) { 1765 sis_reset(sc); 1766 sis_init(sc); 1767 } 1768 } 1769 1770 /* Re-enable interrupts. */ 1771 CSR_WRITE_4(sc, SIS_IER, 1); 1772 1773 if (ifp->if_snd.ifq_head != NULL) 1774 sis_start(ifp); 1775done: 1776 SIS_UNLOCK(sc); 1777 1778 return; 1779} 1780 1781/* 1782 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1783 * pointers to the fragment pointers. 1784 */ 1785static int 1786sis_encap(sc, m_head, txidx) 1787 struct sis_softc *sc; 1788 struct mbuf *m_head; 1789 u_int32_t *txidx; 1790{ 1791 struct sis_desc *f = NULL; 1792 struct mbuf *m; 1793 int frag, cur, cnt = 0; 1794 1795 /* 1796 * Start packing the mbufs in this chain into 1797 * the fragment pointers. Stop when we run out 1798 * of fragments or hit the end of the mbuf chain. 1799 */ 1800 m = m_head; 1801 cur = frag = *txidx; 1802 1803 for (m = m_head; m != NULL; m = m->m_next) { 1804 if (m->m_len != 0) { 1805 if ((SIS_TX_LIST_CNT - 1806 (sc->sis_cdata.sis_tx_cnt + cnt)) < 2) 1807 return(ENOBUFS); 1808 f = &sc->sis_ldata.sis_tx_list[frag]; 1809 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; 1810 bus_dmamap_create(sc->sis_tag, 0, &f->sis_map); 1811 bus_dmamap_load(sc->sis_tag, f->sis_map, 1812 mtod(m, void *), m->m_len, 1813 sis_dma_map_desc_ptr, f, 0); 1814 bus_dmamap_sync(sc->sis_tag, 1815 f->sis_map, BUS_DMASYNC_PREREAD); 1816 if (cnt != 0) 1817 f->sis_ctl |= SIS_CMDSTS_OWN; 1818 cur = frag; 1819 SIS_INC(frag, SIS_TX_LIST_CNT); 1820 cnt++; 1821 } 1822 } 1823 1824 if (m != NULL) 1825 return(ENOBUFS); 1826 1827 sc->sis_ldata.sis_tx_list[cur].sis_mbuf = m_head; 1828 sc->sis_ldata.sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1829 sc->sis_ldata.sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1830 sc->sis_cdata.sis_tx_cnt += cnt; 1831 *txidx = frag; 1832 1833 return(0); 1834} 1835 1836/* 1837 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1838 * to the mbuf data regions directly in the transmit lists. We also save a 1839 * copy of the pointers since the transmit list fragment pointers are 1840 * physical addresses. 1841 */ 1842 1843static void 1844sis_start(ifp) 1845 struct ifnet *ifp; 1846{ 1847 struct sis_softc *sc; 1848 struct mbuf *m_head = NULL; 1849 u_int32_t idx; 1850 1851 sc = ifp->if_softc; 1852 SIS_LOCK(sc); 1853 1854 if (!sc->sis_link) { 1855 SIS_UNLOCK(sc); 1856 return; 1857 } 1858 1859 idx = sc->sis_cdata.sis_tx_prod; 1860 1861 if (ifp->if_flags & IFF_OACTIVE) { 1862 SIS_UNLOCK(sc); 1863 return; 1864 } 1865 1866 while(sc->sis_ldata.sis_tx_list[idx].sis_mbuf == NULL) { 1867 IF_DEQUEUE(&ifp->if_snd, m_head); 1868 if (m_head == NULL) 1869 break; 1870 1871 if (sis_encap(sc, m_head, &idx)) { 1872 IF_PREPEND(&ifp->if_snd, m_head); 1873 ifp->if_flags |= IFF_OACTIVE; 1874 break; 1875 } 1876 1877 /* 1878 * If there's a BPF listener, bounce a copy of this frame 1879 * to him. 1880 */ 1881 BPF_MTAP(ifp, m_head); 1882 1883 } 1884 1885 /* Transmit */ 1886 sc->sis_cdata.sis_tx_prod = idx; 1887 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 1888 1889 /* 1890 * Set a timeout in case the chip goes out to lunch. 1891 */ 1892 ifp->if_timer = 5; 1893 1894 SIS_UNLOCK(sc); 1895 1896 return; 1897} 1898 1899static void 1900sis_init(xsc) 1901 void *xsc; 1902{ 1903 struct sis_softc *sc = xsc; 1904 struct ifnet *ifp = &sc->arpcom.ac_if; 1905 struct mii_data *mii; 1906 1907 SIS_LOCK(sc); 1908 1909 /* 1910 * Cancel pending I/O and free all RX/TX buffers. 1911 */ 1912 sis_stop(sc); 1913 1914 mii = device_get_softc(sc->sis_miibus); 1915 1916 /* Set MAC address */ 1917 if (sc->sis_type == SIS_TYPE_83815) { 1918 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 1919 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1920 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1921 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 1922 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1923 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1924 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 1925 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1926 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1927 } else { 1928 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 1929 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1930 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1931 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 1932 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1933 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1934 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 1935 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1936 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1937 } 1938 1939 /* Init circular RX list. */ 1940 if (sis_list_rx_init(sc) == ENOBUFS) { 1941 printf("sis%d: initialization failed: no " 1942 "memory for rx buffers\n", sc->sis_unit); 1943 sis_stop(sc); 1944 SIS_UNLOCK(sc); 1945 return; 1946 } 1947 1948 /* 1949 * Init tx descriptors. 1950 */ 1951 sis_list_tx_init(sc); 1952 1953 /* 1954 * For the NatSemi chip, we have to explicitly enable the 1955 * reception of ARP frames, as well as turn on the 'perfect 1956 * match' filter where we store the station address, otherwise 1957 * we won't receive unicasts meant for this host. 1958 */ 1959 if (sc->sis_type == SIS_TYPE_83815) { 1960 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 1961 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 1962 } 1963 1964 /* If we want promiscuous mode, set the allframes bit. */ 1965 if (ifp->if_flags & IFF_PROMISC) { 1966 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1967 } else { 1968 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1969 } 1970 1971 /* 1972 * Set the capture broadcast bit to capture broadcast frames. 1973 */ 1974 if (ifp->if_flags & IFF_BROADCAST) { 1975 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1976 } else { 1977 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1978 } 1979 1980 /* 1981 * Load the multicast filter. 1982 */ 1983 if (sc->sis_type == SIS_TYPE_83815) 1984 sis_setmulti_ns(sc); 1985 else 1986 sis_setmulti_sis(sc); 1987 1988 /* Turn the receive filter on */ 1989 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 1990 1991 /* 1992 * Load the address of the RX and TX lists. 1993 */ 1994 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_cdata.sis_rx_paddr); 1995 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_cdata.sis_tx_paddr); 1996 1997 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of 1998 * the PCI bus. When this bit is set, the Max DMA Burst Size 1999 * for TX/RX DMA should be no larger than 16 double words. 2000 */ 2001 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) { 2002 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); 2003 } else { 2004 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); 2005 } 2006 2007 2008 /* Accept Long Packets for VLAN support */ 2009 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 2010 2011 /* Set TX configuration */ 2012 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 2013 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 2014 } else { 2015 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 2016 } 2017 2018 /* Set full/half duplex mode. */ 2019 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 2020 SIS_SETBIT(sc, SIS_TX_CFG, 2021 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 2022 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 2023 } else { 2024 SIS_CLRBIT(sc, SIS_TX_CFG, 2025 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 2026 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 2027 } 2028 2029 /* 2030 * Enable interrupts. 2031 */ 2032 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 2033#ifdef DEVICE_POLLING 2034 /* 2035 * ... only enable interrupts if we are not polling, make sure 2036 * they are off otherwise. 2037 */ 2038 if (ifp->if_flags & IFF_POLLING) 2039 CSR_WRITE_4(sc, SIS_IER, 0); 2040 else 2041#endif /* DEVICE_POLLING */ 2042 CSR_WRITE_4(sc, SIS_IER, 1); 2043 2044 /* Enable receiver and transmitter. */ 2045 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2046 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 2047 2048#ifdef notdef 2049 mii_mediachg(mii); 2050#endif 2051 2052 /* 2053 * Page 75 of the DP83815 manual recommends the 2054 * following register settings "for optimum 2055 * performance." Note however that at least three 2056 * of the registers are listed as "reserved" in 2057 * the register map, so who knows what they do. 2058 */ 2059 if (sc->sis_type == SIS_TYPE_83815) { 2060 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 2061 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 2062 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 2063 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 2064 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 2065 } 2066 2067 ifp->if_flags |= IFF_RUNNING; 2068 ifp->if_flags &= ~IFF_OACTIVE; 2069 2070 sc->sis_stat_ch = timeout(sis_tick, sc, hz); 2071 2072 SIS_UNLOCK(sc); 2073 2074 return; 2075} 2076 2077/* 2078 * Set media options. 2079 */ 2080static int 2081sis_ifmedia_upd(ifp) 2082 struct ifnet *ifp; 2083{ 2084 struct sis_softc *sc; 2085 struct mii_data *mii; 2086 2087 sc = ifp->if_softc; 2088 2089 mii = device_get_softc(sc->sis_miibus); 2090 sc->sis_link = 0; 2091 if (mii->mii_instance) { 2092 struct mii_softc *miisc; 2093 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2094 mii_phy_reset(miisc); 2095 } 2096 mii_mediachg(mii); 2097 2098 return(0); 2099} 2100 2101/* 2102 * Report current media status. 2103 */ 2104static void 2105sis_ifmedia_sts(ifp, ifmr) 2106 struct ifnet *ifp; 2107 struct ifmediareq *ifmr; 2108{ 2109 struct sis_softc *sc; 2110 struct mii_data *mii; 2111 2112 sc = ifp->if_softc; 2113 2114 mii = device_get_softc(sc->sis_miibus); 2115 mii_pollstat(mii); 2116 ifmr->ifm_active = mii->mii_media_active; 2117 ifmr->ifm_status = mii->mii_media_status; 2118 2119 return; 2120} 2121 2122static int 2123sis_ioctl(ifp, command, data) 2124 struct ifnet *ifp; 2125 u_long command; 2126 caddr_t data; 2127{ 2128 struct sis_softc *sc = ifp->if_softc; 2129 struct ifreq *ifr = (struct ifreq *) data; 2130 struct mii_data *mii; 2131 int error = 0; 2132 2133 switch(command) { 2134 case SIOCSIFFLAGS: 2135 if (ifp->if_flags & IFF_UP) { 2136 sis_init(sc); 2137 } else { 2138 if (ifp->if_flags & IFF_RUNNING) 2139 sis_stop(sc); 2140 } 2141 error = 0; 2142 break; 2143 case SIOCADDMULTI: 2144 case SIOCDELMULTI: 2145 SIS_LOCK(sc); 2146 if (sc->sis_type == SIS_TYPE_83815) 2147 sis_setmulti_ns(sc); 2148 else 2149 sis_setmulti_sis(sc); 2150 SIS_UNLOCK(sc); 2151 error = 0; 2152 break; 2153 case SIOCGIFMEDIA: 2154 case SIOCSIFMEDIA: 2155 mii = device_get_softc(sc->sis_miibus); 2156 SIS_LOCK(sc); 2157 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2158 SIS_UNLOCK(sc); 2159 break; 2160 default: 2161 error = ether_ioctl(ifp, command, data); 2162 break; 2163 } 2164 2165 return(error); 2166} 2167 2168static void 2169sis_watchdog(ifp) 2170 struct ifnet *ifp; 2171{ 2172 struct sis_softc *sc; 2173 2174 sc = ifp->if_softc; 2175 2176 SIS_LOCK(sc); 2177 2178 ifp->if_oerrors++; 2179 printf("sis%d: watchdog timeout\n", sc->sis_unit); 2180 2181 sis_stop(sc); 2182 sis_reset(sc); 2183 sis_init(sc); 2184 2185 if (ifp->if_snd.ifq_head != NULL) 2186 sis_start(ifp); 2187 2188 SIS_UNLOCK(sc); 2189 2190 return; 2191} 2192 2193/* 2194 * Stop the adapter and free any mbufs allocated to the 2195 * RX and TX lists. 2196 */ 2197static void 2198sis_stop(sc) 2199 struct sis_softc *sc; 2200{ 2201 register int i; 2202 struct ifnet *ifp; 2203 2204 SIS_LOCK(sc); 2205 ifp = &sc->arpcom.ac_if; 2206 ifp->if_timer = 0; 2207 2208 untimeout(sis_tick, sc, sc->sis_stat_ch); 2209 2210 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2211#ifdef DEVICE_POLLING 2212 ether_poll_deregister(ifp); 2213#endif 2214 CSR_WRITE_4(sc, SIS_IER, 0); 2215 CSR_WRITE_4(sc, SIS_IMR, 0); 2216 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2217 DELAY(1000); 2218 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 2219 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2220 2221 sc->sis_link = 0; 2222 2223 /* 2224 * Free data in the RX lists. 2225 */ 2226 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 2227 if (sc->sis_ldata.sis_rx_list[i].sis_mbuf != NULL) { 2228 bus_dmamap_unload(sc->sis_tag, 2229 sc->sis_ldata.sis_rx_list[i].sis_map); 2230 bus_dmamap_destroy(sc->sis_tag, 2231 sc->sis_ldata.sis_rx_list[i].sis_map); 2232 m_freem(sc->sis_ldata.sis_rx_list[i].sis_mbuf); 2233 sc->sis_ldata.sis_rx_list[i].sis_mbuf = NULL; 2234 } 2235 } 2236 bzero(sc->sis_ldata.sis_rx_list, 2237 sizeof(sc->sis_ldata.sis_rx_list)); 2238 2239 /* 2240 * Free the TX list buffers. 2241 */ 2242 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 2243 if (sc->sis_ldata.sis_tx_list[i].sis_mbuf != NULL) { 2244 bus_dmamap_unload(sc->sis_tag, 2245 sc->sis_ldata.sis_tx_list[i].sis_map); 2246 bus_dmamap_destroy(sc->sis_tag, 2247 sc->sis_ldata.sis_tx_list[i].sis_map); 2248 m_freem(sc->sis_ldata.sis_tx_list[i].sis_mbuf); 2249 sc->sis_ldata.sis_tx_list[i].sis_mbuf = NULL; 2250 } 2251 } 2252 2253 bzero(sc->sis_ldata.sis_tx_list, 2254 sizeof(sc->sis_ldata.sis_tx_list)); 2255 2256 SIS_UNLOCK(sc); 2257 2258 return; 2259} 2260 2261/* 2262 * Stop all chip I/O so that the kernel's probe routines don't 2263 * get confused by errant DMAs when rebooting. 2264 */ 2265static void 2266sis_shutdown(dev) 2267 device_t dev; 2268{ 2269 struct sis_softc *sc; 2270 2271 sc = device_get_softc(dev); 2272 SIS_LOCK(sc); 2273 sis_reset(sc); 2274 sis_stop(sc); 2275 SIS_UNLOCK(sc); 2276 2277 return; 2278} 2279