sio.c revision 91276
1/*-
2 * Copyright (c) 1991 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 *    must display the following acknowledgement:
15 *	This product includes software developed by the University of
16 *	California, Berkeley and its contributors.
17 * 4. Neither the name of the University nor the names of its contributors
18 *    may be used to endorse or promote products derived from this software
19 *    without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
33 * $FreeBSD: head/sys/dev/sio/sio.c 91276 2002-02-26 03:13:30Z imp $
34 *	from: @(#)com.c	7.5 (Berkeley) 5/16/91
35 *	from: i386/isa sio.c,v 1.234
36 */
37
38#include "opt_comconsole.h"
39#include "opt_compat.h"
40#include "opt_ddb.h"
41#include "opt_sio.h"
42
43/*
44 * Serial driver, based on 386BSD-0.1 com driver.
45 * Mostly rewritten to use pseudo-DMA.
46 * Works for National Semiconductor NS8250-NS16550AF UARTs.
47 * COM driver, based on HP dca driver.
48 *
49 * Changes for PC-Card integration:
50 *	- Added PC-Card driver table and handlers
51 */
52#include <sys/param.h>
53#include <sys/systm.h>
54#include <sys/bus.h>
55#include <sys/conf.h>
56#include <sys/dkstat.h>
57#include <sys/fcntl.h>
58#include <sys/interrupt.h>
59#include <sys/kernel.h>
60#include <sys/lock.h>
61#include <sys/malloc.h>
62#include <sys/module.h>
63#include <sys/mutex.h>
64#include <sys/proc.h>
65#include <sys/reboot.h>
66#include <sys/sysctl.h>
67#include <sys/syslog.h>
68#include <sys/tty.h>
69#include <machine/bus_pio.h>
70#include <machine/bus.h>
71#include <sys/rman.h>
72#include <sys/timetc.h>
73#include <sys/timepps.h>
74
75#include <isa/isavar.h>
76
77#include <machine/resource.h>
78
79#include <dev/sio/sioreg.h>
80#include <dev/sio/siovar.h>
81
82#ifdef COM_ESP
83#include <dev/ic/esp.h>
84#endif
85#include <dev/ic/ns16550.h>
86
87#define	LOTS_OF_EVENTS	64	/* helps separate urgent events from input */
88
89#define	CALLOUT_MASK		0x80
90#define	CONTROL_MASK		0x60
91#define	CONTROL_INIT_STATE	0x20
92#define	CONTROL_LOCK_STATE	0x40
93#define	DEV_TO_UNIT(dev)	(MINOR_TO_UNIT(minor(dev)))
94#define	MINOR_MAGIC_MASK	(CALLOUT_MASK | CONTROL_MASK)
95#define	MINOR_TO_UNIT(mynor)	((mynor) & ~MINOR_MAGIC_MASK)
96
97#ifdef COM_MULTIPORT
98/* checks in flags for multiport and which is multiport "master chip"
99 * for a given card
100 */
101#define	COM_ISMULTIPORT(flags)	((flags) & 0x01)
102#define	COM_MPMASTER(flags)	(((flags) >> 8) & 0x0ff)
103#define	COM_NOTAST4(flags)	((flags) & 0x04)
104#endif /* COM_MULTIPORT */
105
106#define	COM_CONSOLE(flags)	((flags) & 0x10)
107#define	COM_FORCECONSOLE(flags)	((flags) & 0x20)
108#define	COM_LLCONSOLE(flags)	((flags) & 0x40)
109#define	COM_DEBUGGER(flags)	((flags) & 0x80)
110#define	COM_LOSESOUTINTS(flags)	((flags) & 0x08)
111#define	COM_NOFIFO(flags)		((flags) & 0x02)
112#define COM_ST16650A(flags)	((flags) & 0x20000)
113#define COM_C_NOPROBE		(0x40000)
114#define COM_NOPROBE(flags)	((flags) & COM_C_NOPROBE)
115#define COM_C_IIR_TXRDYBUG	(0x80000)
116#define COM_IIR_TXRDYBUG(flags)	((flags) & COM_C_IIR_TXRDYBUG)
117#define	COM_FIFOSIZE(flags)	(((flags) & 0xff000000) >> 24)
118
119#define	com_scr		7	/* scratch register for 16450-16550 (R/W) */
120
121#define	sio_getreg(com, off) \
122	(bus_space_read_1((com)->bst, (com)->bsh, (off)))
123#define	sio_setreg(com, off, value) \
124	(bus_space_write_1((com)->bst, (com)->bsh, (off), (value)))
125
126/*
127 * com state bits.
128 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher
129 * than the other bits so that they can be tested as a group without masking
130 * off the low bits.
131 *
132 * The following com and tty flags correspond closely:
133 *	CS_BUSY		= TS_BUSY (maintained by comstart(), siopoll() and
134 *				   comstop())
135 *	CS_TTGO		= ~TS_TTSTOP (maintained by comparam() and comstart())
136 *	CS_CTS_OFLOW	= CCTS_OFLOW (maintained by comparam())
137 *	CS_RTS_IFLOW	= CRTS_IFLOW (maintained by comparam())
138 * TS_FLUSH is not used.
139 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON.
140 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state).
141 */
142#define	CS_BUSY		0x80	/* output in progress */
143#define	CS_TTGO		0x40	/* output not stopped by XOFF */
144#define	CS_ODEVREADY	0x20	/* external device h/w ready (CTS) */
145#define	CS_CHECKMSR	1	/* check of MSR scheduled */
146#define	CS_CTS_OFLOW	2	/* use CTS output flow control */
147#define	CS_DTR_OFF	0x10	/* DTR held off */
148#define	CS_ODONE	4	/* output completed */
149#define	CS_RTS_IFLOW	8	/* use RTS input flow control */
150#define	CSE_BUSYCHECK	1	/* siobusycheck() scheduled */
151
152static	char const * const	error_desc[] = {
153#define	CE_OVERRUN			0
154	"silo overflow",
155#define	CE_INTERRUPT_BUF_OVERFLOW	1
156	"interrupt-level buffer overflow",
157#define	CE_TTY_BUF_OVERFLOW		2
158	"tty-level buffer overflow",
159};
160
161#define	CE_NTYPES			3
162#define	CE_RECORD(com, errnum)		(++(com)->delta_error_counts[errnum])
163
164/* types.  XXX - should be elsewhere */
165typedef u_int	Port_t;		/* hardware port */
166typedef u_char	bool_t;		/* boolean */
167
168/* queue of linear buffers */
169struct lbq {
170	u_char	*l_head;	/* next char to process */
171	u_char	*l_tail;	/* one past the last char to process */
172	struct lbq *l_next;	/* next in queue */
173	bool_t	l_queued;	/* nonzero if queued */
174};
175
176/* com device structure */
177struct com_s {
178	u_int	flags;		/* Copy isa device flags */
179	u_char	state;		/* miscellaneous flag bits */
180	bool_t  active_out;	/* nonzero if the callout device is open */
181	u_char	cfcr_image;	/* copy of value written to CFCR */
182#ifdef COM_ESP
183	bool_t	esp;		/* is this unit a hayes esp board? */
184#endif
185	u_char	extra_state;	/* more flag bits, separate for order trick */
186	u_char	fifo_image;	/* copy of value written to FIFO */
187	bool_t	hasfifo;	/* nonzero for 16550 UARTs */
188	bool_t	st16650a;	/* Is a Startech 16650A or RTS/CTS compat */
189	bool_t	loses_outints;	/* nonzero if device loses output interrupts */
190	u_char	mcr_image;	/* copy of value written to MCR */
191#ifdef COM_MULTIPORT
192	bool_t	multiport;	/* is this unit part of a multiport device? */
193#endif /* COM_MULTIPORT */
194	bool_t	no_irq;		/* nonzero if irq is not attached */
195	bool_t  gone;		/* hardware disappeared */
196	bool_t	poll;		/* nonzero if polling is required */
197	bool_t	poll_output;	/* nonzero if polling for output is required */
198	int	unit;		/* unit	number */
199	int	dtr_wait;	/* time to hold DTR down on close (* 1/hz) */
200	u_int	tx_fifo_size;
201	u_int	wopeners;	/* # processes waiting for DCD in open() */
202
203	/*
204	 * The high level of the driver never reads status registers directly
205	 * because there would be too many side effects to handle conveniently.
206	 * Instead, it reads copies of the registers stored here by the
207	 * interrupt handler.
208	 */
209	u_char	last_modem_status;	/* last MSR read by intr handler */
210	u_char	prev_modem_status;	/* last MSR handled by high level */
211
212	u_char	hotchar;	/* ldisc-specific char to be handled ASAP */
213	u_char	*ibuf;		/* start of input buffer */
214	u_char	*ibufend;	/* end of input buffer */
215	u_char	*ibufold;	/* old input buffer, to be freed */
216	u_char	*ihighwater;	/* threshold in input buffer */
217	u_char	*iptr;		/* next free spot in input buffer */
218	int	ibufsize;	/* size of ibuf (not include error bytes) */
219	int	ierroff;	/* offset of error bytes in ibuf */
220
221	struct lbq	obufq;	/* head of queue of output buffers */
222	struct lbq	obufs[2];	/* output buffers */
223
224	bus_space_tag_t		bst;
225	bus_space_handle_t	bsh;
226
227	Port_t	data_port;	/* i/o ports */
228#ifdef COM_ESP
229	Port_t	esp_port;
230#endif
231	Port_t	int_id_port;
232	Port_t	modem_ctl_port;
233	Port_t	line_status_port;
234	Port_t	modem_status_port;
235	Port_t	intr_ctl_port;	/* Ports of IIR register */
236
237	struct tty	*tp;	/* cross reference */
238
239	/* Initial state. */
240	struct termios	it_in;	/* should be in struct tty */
241	struct termios	it_out;
242
243	/* Lock state. */
244	struct termios	lt_in;	/* should be in struct tty */
245	struct termios	lt_out;
246
247	bool_t	do_timestamp;
248	bool_t	do_dcd_timestamp;
249	struct timeval	timestamp;
250	struct timeval	dcd_timestamp;
251	struct	pps_state pps;
252
253	u_long	bytes_in;	/* statistics */
254	u_long	bytes_out;
255	u_int	delta_error_counts[CE_NTYPES];
256	u_long	error_counts[CE_NTYPES];
257
258	u_long	rclk;
259
260	struct resource *irqres;
261	struct resource *ioportres;
262	void *cookie;
263	dev_t devs[6];
264
265	/*
266	 * Data area for output buffers.  Someday we should build the output
267	 * buffer queue without copying data.
268	 */
269	u_char	obuf1[256];
270	u_char	obuf2[256];
271};
272
273#ifdef COM_ESP
274static	int	espattach	__P((struct com_s *com, Port_t esp_port));
275#endif
276
277static	timeout_t siobusycheck;
278static	u_int	siodivisor	__P((u_long rclk, speed_t speed));
279static	timeout_t siodtrwakeup;
280static	void	comhardclose	__P((struct com_s *com));
281static	void	sioinput	__P((struct com_s *com));
282static	void	siointr1	__P((struct com_s *com));
283static	void	siointr		__P((void *arg));
284static	int	commctl		__P((struct com_s *com, int bits, int how));
285static	int	comparam	__P((struct tty *tp, struct termios *t));
286static	void	siopoll		__P((void *));
287static	void	siosettimeout	__P((void));
288static	int	siosetwater	__P((struct com_s *com, speed_t speed));
289static	void	comstart	__P((struct tty *tp));
290static	void	comstop		__P((struct tty *tp, int rw));
291static	timeout_t comwakeup;
292static	void	disc_optim	__P((struct tty	*tp, struct termios *t,
293				     struct com_s *com));
294
295char		sio_driver_name[] = "sio";
296static struct	mtx sio_lock;
297static int	sio_inited;
298
299/* table and macro for fast conversion from a unit number to its com struct */
300devclass_t	sio_devclass;
301#define	com_addr(unit)	((struct com_s *) \
302			 devclass_get_softc(sio_devclass, unit)) /* XXX */
303
304static	d_open_t	sioopen;
305static	d_close_t	sioclose;
306static	d_read_t	sioread;
307static	d_write_t	siowrite;
308static	d_ioctl_t	sioioctl;
309
310#define	CDEV_MAJOR	28
311static struct cdevsw sio_cdevsw = {
312	/* open */	sioopen,
313	/* close */	sioclose,
314	/* read */	sioread,
315	/* write */	siowrite,
316	/* ioctl */	sioioctl,
317	/* poll */	ttypoll,
318	/* mmap */	nommap,
319	/* strategy */	nostrategy,
320	/* name */	sio_driver_name,
321	/* maj */	CDEV_MAJOR,
322	/* dump */	nodump,
323	/* psize */	nopsize,
324	/* flags */	D_TTY | D_KQFILTER,
325	/* kqfilter */	ttykqfilter,
326};
327
328int	comconsole = -1;
329static	volatile speed_t	comdefaultrate = CONSPEED;
330static	u_long			comdefaultrclk = DEFAULT_RCLK;
331SYSCTL_ULONG(_machdep, OID_AUTO, conrclk, CTLFLAG_RW, &comdefaultrclk, 0, "");
332#ifdef __alpha__
333static	volatile speed_t	gdbdefaultrate = CONSPEED;
334#endif
335static	u_int	com_events;	/* input chars + weighted output completions */
336static	Port_t	siocniobase;
337#ifndef __alpha__
338static	int	siocnunit;
339#endif
340static	Port_t	siogdbiobase;
341static	int	siogdbunit = -1;
342static	void	*sio_slow_ih;
343static	void	*sio_fast_ih;
344static	int	sio_timeout;
345static	int	sio_timeouts_until_log;
346static	struct	callout_handle sio_timeout_handle
347    = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle);
348static	int	sio_numunits;
349
350#ifdef COM_ESP
351/* XXX configure this properly. */
352/* XXX quite broken for new-bus. */
353static	Port_t	likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, };
354static	Port_t	likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 };
355#endif
356
357/*
358 * handle sysctl read/write requests for console speed
359 *
360 * In addition to setting comdefaultrate for I/O through /dev/console,
361 * also set the initial and lock values for the /dev/ttyXX device
362 * if there is one associated with the console.  Finally, if the /dev/tty
363 * device has already been open, change the speed on the open running port
364 * itself.
365 */
366
367static int
368sysctl_machdep_comdefaultrate(SYSCTL_HANDLER_ARGS)
369{
370	int error, s;
371	speed_t newspeed;
372	struct com_s *com;
373	struct tty *tp;
374
375	newspeed = comdefaultrate;
376
377	error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req);
378	if (error || !req->newptr)
379		return (error);
380
381	comdefaultrate = newspeed;
382
383	if (comconsole < 0)		/* serial console not selected? */
384		return (0);
385
386	com = com_addr(comconsole);
387	if (com == NULL)
388		return (ENXIO);
389
390	/*
391	 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX
392	 * (note, the lock rates really are boolean -- if non-zero, disallow
393	 *  speed changes)
394	 */
395	com->it_in.c_ispeed  = com->it_in.c_ospeed =
396	com->lt_in.c_ispeed  = com->lt_in.c_ospeed =
397	com->it_out.c_ispeed = com->it_out.c_ospeed =
398	com->lt_out.c_ispeed = com->lt_out.c_ospeed = comdefaultrate;
399
400	/*
401	 * if we're open, change the running rate too
402	 */
403	tp = com->tp;
404	if (tp && (tp->t_state & TS_ISOPEN)) {
405		tp->t_termios.c_ispeed =
406		tp->t_termios.c_ospeed = comdefaultrate;
407		s = spltty();
408		error = comparam(tp, &tp->t_termios);
409		splx(s);
410	}
411	return error;
412}
413
414SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW,
415	    0, 0, sysctl_machdep_comdefaultrate, "I", "");
416TUNABLE_INT("machdep.conspeed", &comdefaultrate);
417
418#define SET_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) | (bit))
419#define CLR_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) & ~(bit))
420
421/*
422 *	Unload the driver and clear the table.
423 *	XXX this is mostly wrong.
424 *	XXX TODO:
425 *	This is usually called when the card is ejected, but
426 *	can be caused by a modunload of a controller driver.
427 *	The idea is to reset the driver's view of the device
428 *	and ensure that any driver entry points such as
429 *	read and write do not hang.
430 */
431int
432siodetach(dev)
433	device_t	dev;
434{
435	struct com_s	*com;
436	int i;
437
438	com = (struct com_s *) device_get_softc(dev);
439	if (com == NULL) {
440		device_printf(dev, "NULL com in siounload\n");
441		return (0);
442	}
443	com->gone = 1;
444	for (i = 0 ; i < 6; i++)
445		destroy_dev(com->devs[i]);
446	if (com->irqres) {
447		bus_teardown_intr(dev, com->irqres, com->cookie);
448		bus_release_resource(dev, SYS_RES_IRQ, 0, com->irqres);
449	}
450	if (com->ioportres)
451		bus_release_resource(dev, SYS_RES_IOPORT, 0, com->ioportres);
452	if (com->tp && (com->tp->t_state & TS_ISOPEN)) {
453		device_printf(dev, "still open, forcing close\n");
454		(*linesw[com->tp->t_line].l_close)(com->tp, 0);
455		com->tp->t_gen++;
456		ttyclose(com->tp);
457		ttwakeup(com->tp);
458		ttwwakeup(com->tp);
459	} else {
460		if (com->ibuf != NULL)
461			free(com->ibuf, M_DEVBUF);
462		device_set_softc(dev, NULL);
463		free(com, M_DEVBUF);
464	}
465	return (0);
466}
467
468int
469sioprobe(dev, xrid, rclk, noprobe)
470	device_t	dev;
471	int		xrid;
472	u_long		rclk;
473	int		noprobe;
474{
475#if 0
476	static bool_t	already_init;
477	device_t	xdev;
478#endif
479	struct com_s	*com;
480	u_int		divisor;
481	bool_t		failures[10];
482	int		fn;
483	device_t	idev;
484	Port_t		iobase;
485	intrmask_t	irqmap[4];
486	intrmask_t	irqs;
487	u_char		mcr_image;
488	int		result;
489	u_long		xirq;
490	u_int		flags = device_get_flags(dev);
491	int		rid;
492	struct resource *port;
493
494	rid = xrid;
495	port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
496				  0, ~0, IO_COMSIZE, RF_ACTIVE);
497	if (!port)
498		return (ENXIO);
499
500	com = malloc(sizeof(*com), M_DEVBUF, M_NOWAIT | M_ZERO);
501	if (com == NULL)
502		return (ENOMEM);
503	device_set_softc(dev, com);
504	com->bst = rman_get_bustag(port);
505	com->bsh = rman_get_bushandle(port);
506	if (rclk == 0)
507		rclk = DEFAULT_RCLK;
508	com->rclk = rclk;
509
510	while (sio_inited != 2)
511		if (atomic_cmpset_int(&sio_inited, 0, 1)) {
512			mtx_init(&sio_lock, sio_driver_name, (comconsole != -1) ?
513			    MTX_SPIN | MTX_QUIET : MTX_SPIN);
514			atomic_store_rel_int(&sio_inited, 2);
515		}
516
517#if 0
518	/*
519	 * XXX this is broken - when we are first called, there are no
520	 * previously configured IO ports.  We could hard code
521	 * 0x3f8, 0x2f8, 0x3e8, 0x2e8 etc but that's probably worse.
522	 * This code has been doing nothing since the conversion since
523	 * "count" is zero the first time around.
524	 */
525	if (!already_init) {
526		/*
527		 * Turn off MCR_IENABLE for all likely serial ports.  An unused
528		 * port with its MCR_IENABLE gate open will inhibit interrupts
529		 * from any used port that shares the interrupt vector.
530		 * XXX the gate enable is elsewhere for some multiports.
531		 */
532		device_t *devs;
533		int count, i, xioport;
534
535		devclass_get_devices(sio_devclass, &devs, &count);
536		for (i = 0; i < count; i++) {
537			xdev = devs[i];
538			if (device_is_enabled(xdev) &&
539			    bus_get_resource(xdev, SYS_RES_IOPORT, 0, &xioport,
540					     NULL) == 0)
541				outb(xioport + com_mcr, 0);
542		}
543		free(devs, M_TEMP);
544		already_init = TRUE;
545	}
546#endif
547
548	if (COM_LLCONSOLE(flags)) {
549		printf("sio%d: reserved for low-level i/o\n",
550		       device_get_unit(dev));
551		bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
552		device_set_softc(dev, NULL);
553		free(com, M_DEVBUF);
554		return (ENXIO);
555	}
556
557	/*
558	 * If the device is on a multiport card and has an AST/4
559	 * compatible interrupt control register, initialize this
560	 * register and prepare to leave MCR_IENABLE clear in the mcr.
561	 * Otherwise, prepare to set MCR_IENABLE in the mcr.
562	 * Point idev to the device struct giving the correct id_irq.
563	 * This is the struct for the master device if there is one.
564	 */
565	idev = dev;
566	mcr_image = MCR_IENABLE;
567#ifdef COM_MULTIPORT
568	if (COM_ISMULTIPORT(flags)) {
569		Port_t xiobase;
570		u_long io;
571
572		idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags));
573		if (idev == NULL) {
574			printf("sio%d: master device %d not configured\n",
575			       device_get_unit(dev), COM_MPMASTER(flags));
576			idev = dev;
577		}
578		if (!COM_NOTAST4(flags)) {
579			if (bus_get_resource(idev, SYS_RES_IOPORT, 0, &io,
580					     NULL) == 0) {
581				xiobase = io;
582				if (bus_get_resource(idev, SYS_RES_IRQ, 0,
583				    NULL, NULL) == 0)
584					outb(xiobase + com_scr, 0x80);
585				else
586					outb(xiobase + com_scr, 0);
587			}
588			mcr_image = 0;
589		}
590	}
591#endif /* COM_MULTIPORT */
592	if (bus_get_resource(idev, SYS_RES_IRQ, 0, NULL, NULL) != 0)
593		mcr_image = 0;
594
595	bzero(failures, sizeof failures);
596	iobase = rman_get_start(port);
597
598	/*
599	 * We don't want to get actual interrupts, just masked ones.
600	 * Interrupts from this line should already be masked in the ICU,
601	 * but mask them in the processor as well in case there are some
602	 * (misconfigured) shared interrupts.
603	 */
604	mtx_lock_spin(&sio_lock);
605/* EXTRA DELAY? */
606
607	/*
608	 * Initialize the speed and the word size and wait long enough to
609	 * drain the maximum of 16 bytes of junk in device output queues.
610	 * The speed is undefined after a master reset and must be set
611	 * before relying on anything related to output.  There may be
612	 * junk after a (very fast) soft reboot and (apparently) after
613	 * master reset.
614	 * XXX what about the UART bug avoided by waiting in comparam()?
615	 * We don't want to to wait long enough to drain at 2 bps.
616	 */
617	if (iobase == siocniobase)
618		DELAY((16 + 1) * 1000000 / (comdefaultrate / 10));
619	else {
620		sio_setreg(com, com_cfcr, CFCR_DLAB | CFCR_8BITS);
621		divisor = siodivisor(rclk, SIO_TEST_SPEED);
622		sio_setreg(com, com_dlbl, divisor & 0xff);
623		sio_setreg(com, com_dlbh, divisor >> 8);
624		sio_setreg(com, com_cfcr, CFCR_8BITS);
625		DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10));
626	}
627
628	/*
629	 * Enable the interrupt gate and disable device interupts.  This
630	 * should leave the device driving the interrupt line low and
631	 * guarantee an edge trigger if an interrupt can be generated.
632	 */
633/* EXTRA DELAY? */
634	sio_setreg(com, com_mcr, mcr_image);
635	sio_setreg(com, com_ier, 0);
636	DELAY(1000);		/* XXX */
637	irqmap[0] = isa_irq_pending();
638
639	/*
640	 * Attempt to set loopback mode so that we can send a null byte
641	 * without annoying any external device.
642	 */
643/* EXTRA DELAY? */
644	sio_setreg(com, com_mcr, mcr_image | MCR_LOOPBACK);
645
646	/*
647	 * Attempt to generate an output interrupt.  On 8250's, setting
648	 * IER_ETXRDY generates an interrupt independent of the current
649	 * setting and independent of whether the THR is empty.  On 16450's,
650	 * setting IER_ETXRDY generates an interrupt independent of the
651	 * current setting.  On 16550A's, setting IER_ETXRDY only
652	 * generates an interrupt when IER_ETXRDY is not already set.
653	 */
654	sio_setreg(com, com_ier, IER_ETXRDY);
655
656	/*
657	 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate
658	 * an interrupt.  They'd better generate one for actually doing
659	 * output.  Loopback may be broken on the same incompatibles but
660	 * it's unlikely to do more than allow the null byte out.
661	 */
662	sio_setreg(com, com_data, 0);
663	DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10));
664
665	/*
666	 * Turn off loopback mode so that the interrupt gate works again
667	 * (MCR_IENABLE was hidden).  This should leave the device driving
668	 * an interrupt line high.  It doesn't matter if the interrupt
669	 * line oscillates while we are not looking at it, since interrupts
670	 * are disabled.
671	 */
672/* EXTRA DELAY? */
673	sio_setreg(com, com_mcr, mcr_image);
674
675	/*
676	 * Some pcmcia cards have the "TXRDY bug", so we check everyone
677	 * for IIR_TXRDY implementation ( Palido 321s, DC-1S... )
678	 */
679	if (noprobe) {
680		/* Reading IIR register twice */
681		for (fn = 0; fn < 2; fn ++) {
682			DELAY(10000);
683			failures[6] = sio_getreg(com, com_iir);
684		}
685		/* Check IIR_TXRDY clear ? */
686		result = 0;
687		if (failures[6] & IIR_TXRDY) {
688			/* Nop, Double check with clearing IER */
689			sio_setreg(com, com_ier, 0);
690			if (sio_getreg(com, com_iir) & IIR_NOPEND) {
691				/* Ok. we're familia this gang */
692				SET_FLAG(dev, COM_C_IIR_TXRDYBUG);
693			} else {
694				/* Unknown, Just omit this chip.. XXX */
695				result = ENXIO;
696				sio_setreg(com, com_mcr, 0);
697			}
698		} else {
699			/* OK. this is well-known guys */
700			CLR_FLAG(dev, COM_C_IIR_TXRDYBUG);
701		}
702		sio_setreg(com, com_ier, 0);
703		sio_setreg(com, com_cfcr, CFCR_8BITS);
704		mtx_unlock_spin(&sio_lock);
705		bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
706		if (iobase == siocniobase)
707			result = 0;
708		if (result != 0) {
709			device_set_softc(dev, NULL);
710			free(com, M_DEVBUF);
711		}
712		return (result);
713	}
714
715	/*
716	 * Check that
717	 *	o the CFCR, IER and MCR in UART hold the values written to them
718	 *	  (the values happen to be all distinct - this is good for
719	 *	  avoiding false positive tests from bus echoes).
720	 *	o an output interrupt is generated and its vector is correct.
721	 *	o the interrupt goes away when the IIR in the UART is read.
722	 */
723/* EXTRA DELAY? */
724	failures[0] = sio_getreg(com, com_cfcr) - CFCR_8BITS;
725	failures[1] = sio_getreg(com, com_ier) - IER_ETXRDY;
726	failures[2] = sio_getreg(com, com_mcr) - mcr_image;
727	DELAY(10000);		/* Some internal modems need this time */
728	irqmap[1] = isa_irq_pending();
729	failures[4] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_TXRDY;
730	DELAY(1000);		/* XXX */
731	irqmap[2] = isa_irq_pending();
732	failures[6] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND;
733
734	/*
735	 * Turn off all device interrupts and check that they go off properly.
736	 * Leave MCR_IENABLE alone.  For ports without a master port, it gates
737	 * the OUT2 output of the UART to
738	 * the ICU input.  Closing the gate would give a floating ICU input
739	 * (unless there is another device driving it) and spurious interrupts.
740	 * (On the system that this was first tested on, the input floats high
741	 * and gives a (masked) interrupt as soon as the gate is closed.)
742	 */
743	sio_setreg(com, com_ier, 0);
744	sio_setreg(com, com_cfcr, CFCR_8BITS);	/* dummy to avoid bus echo */
745	failures[7] = sio_getreg(com, com_ier);
746	DELAY(1000);		/* XXX */
747	irqmap[3] = isa_irq_pending();
748	failures[9] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND;
749
750	mtx_unlock_spin(&sio_lock);
751
752	irqs = irqmap[1] & ~irqmap[0];
753	if (bus_get_resource(idev, SYS_RES_IRQ, 0, &xirq, NULL) == 0 &&
754	    ((1 << xirq) & irqs) == 0) {
755		printf(
756		"sio%d: configured irq %ld not in bitmap of probed irqs %#x\n",
757		    device_get_unit(dev), xirq, irqs);
758		printf(
759		"sio%d: port may not be enabled\n",
760		    device_get_unit(dev));
761	}
762	if (bootverbose)
763		printf("sio%d: irq maps: %#x %#x %#x %#x\n",
764		    device_get_unit(dev),
765		    irqmap[0], irqmap[1], irqmap[2], irqmap[3]);
766
767	result = 0;
768	for (fn = 0; fn < sizeof failures; ++fn)
769		if (failures[fn]) {
770			sio_setreg(com, com_mcr, 0);
771			result = ENXIO;
772			if (bootverbose) {
773				printf("sio%d: probe failed test(s):",
774				    device_get_unit(dev));
775				for (fn = 0; fn < sizeof failures; ++fn)
776					if (failures[fn])
777						printf(" %d", fn);
778				printf("\n");
779			}
780			break;
781		}
782	bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
783	if (iobase == siocniobase)
784		result = 0;
785	if (result != 0) {
786		device_set_softc(dev, NULL);
787		free(com, M_DEVBUF);
788	}
789	return (result);
790}
791
792#ifdef COM_ESP
793static int
794espattach(com, esp_port)
795	struct com_s		*com;
796	Port_t			esp_port;
797{
798	u_char	dips;
799	u_char	val;
800
801	/*
802	 * Check the ESP-specific I/O port to see if we're an ESP
803	 * card.  If not, return failure immediately.
804	 */
805	if ((inb(esp_port) & 0xf3) == 0) {
806		printf(" port 0x%x is not an ESP board?\n", esp_port);
807		return (0);
808	}
809
810	/*
811	 * We've got something that claims to be a Hayes ESP card.
812	 * Let's hope so.
813	 */
814
815	/* Get the dip-switch configuration */
816	outb(esp_port + ESP_CMD1, ESP_GETDIPS);
817	dips = inb(esp_port + ESP_STATUS1);
818
819	/*
820	 * Bits 0,1 of dips say which COM port we are.
821	 */
822	if (rman_get_start(com->ioportres) == likely_com_ports[dips & 0x03])
823		printf(" : ESP");
824	else {
825		printf(" esp_port has com %d\n", dips & 0x03);
826		return (0);
827	}
828
829	/*
830	 * Check for ESP version 2.0 or later:  bits 4,5,6 = 010.
831	 */
832	outb(esp_port + ESP_CMD1, ESP_GETTEST);
833	val = inb(esp_port + ESP_STATUS1);	/* clear reg 1 */
834	val = inb(esp_port + ESP_STATUS2);
835	if ((val & 0x70) < 0x20) {
836		printf("-old (%o)", val & 0x70);
837		return (0);
838	}
839
840	/*
841	 * Check for ability to emulate 16550:  bit 7 == 1
842	 */
843	if ((dips & 0x80) == 0) {
844		printf(" slave");
845		return (0);
846	}
847
848	/*
849	 * Okay, we seem to be a Hayes ESP card.  Whee.
850	 */
851	com->esp = TRUE;
852	com->esp_port = esp_port;
853	return (1);
854}
855#endif /* COM_ESP */
856
857int
858sioattach(dev, xrid, rclk)
859	device_t	dev;
860	int		xrid;
861	u_long		rclk;
862{
863	struct com_s	*com;
864#ifdef COM_ESP
865	Port_t		*espp;
866#endif
867	Port_t		iobase;
868	int		unit;
869	u_int		flags;
870	int		rid;
871	struct resource *port;
872	int		ret;
873
874	rid = xrid;
875	port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
876				  0, ~0, IO_COMSIZE, RF_ACTIVE);
877	if (!port)
878		return (ENXIO);
879
880	iobase = rman_get_start(port);
881	unit = device_get_unit(dev);
882	com = device_get_softc(dev);
883	flags = device_get_flags(dev);
884
885	if (unit >= sio_numunits)
886		sio_numunits = unit + 1;
887	/*
888	 * sioprobe() has initialized the device registers as follows:
889	 *	o cfcr = CFCR_8BITS.
890	 *	  It is most important that CFCR_DLAB is off, so that the
891	 *	  data port is not hidden when we enable interrupts.
892	 *	o ier = 0.
893	 *	  Interrupts are only enabled when the line is open.
894	 *	o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible
895	 *	  interrupt control register or the config specifies no irq.
896	 *	  Keeping MCR_DTR and MCR_RTS off might stop the external
897	 *	  device from sending before we are ready.
898	 */
899	bzero(com, sizeof *com);
900	com->unit = unit;
901	com->ioportres = port;
902	com->bst = rman_get_bustag(port);
903	com->bsh = rman_get_bushandle(port);
904	com->cfcr_image = CFCR_8BITS;
905	com->dtr_wait = 3 * hz;
906	com->loses_outints = COM_LOSESOUTINTS(flags) != 0;
907	com->no_irq = bus_get_resource(dev, SYS_RES_IRQ, 0, NULL, NULL) != 0;
908	com->tx_fifo_size = 1;
909	com->obufs[0].l_head = com->obuf1;
910	com->obufs[1].l_head = com->obuf2;
911
912	com->data_port = iobase + com_data;
913	com->int_id_port = iobase + com_iir;
914	com->modem_ctl_port = iobase + com_mcr;
915	com->mcr_image = inb(com->modem_ctl_port);
916	com->line_status_port = iobase + com_lsr;
917	com->modem_status_port = iobase + com_msr;
918	com->intr_ctl_port = iobase + com_ier;
919
920	if (rclk == 0)
921		rclk = DEFAULT_RCLK;
922	com->rclk = rclk;
923
924	/*
925	 * We don't use all the flags from <sys/ttydefaults.h> since they
926	 * are only relevant for logins.  It's important to have echo off
927	 * initially so that the line doesn't start blathering before the
928	 * echo flag can be turned off.
929	 */
930	com->it_in.c_iflag = 0;
931	com->it_in.c_oflag = 0;
932	com->it_in.c_cflag = TTYDEF_CFLAG;
933	com->it_in.c_lflag = 0;
934	if (unit == comconsole) {
935		com->it_in.c_iflag = TTYDEF_IFLAG;
936		com->it_in.c_oflag = TTYDEF_OFLAG;
937		com->it_in.c_cflag = TTYDEF_CFLAG | CLOCAL;
938		com->it_in.c_lflag = TTYDEF_LFLAG;
939		com->lt_out.c_cflag = com->lt_in.c_cflag = CLOCAL;
940		com->lt_out.c_ispeed = com->lt_out.c_ospeed =
941		com->lt_in.c_ispeed = com->lt_in.c_ospeed =
942		com->it_in.c_ispeed = com->it_in.c_ospeed = comdefaultrate;
943	} else
944		com->it_in.c_ispeed = com->it_in.c_ospeed = TTYDEF_SPEED;
945	if (siosetwater(com, com->it_in.c_ispeed) != 0) {
946		mtx_unlock_spin(&sio_lock);
947		/*
948		 * Leave i/o resources allocated if this is a `cn'-level
949		 * console, so that other devices can't snarf them.
950		 */
951		if (iobase != siocniobase)
952			bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
953		return (ENOMEM);
954	}
955	mtx_unlock_spin(&sio_lock);
956	termioschars(&com->it_in);
957	com->it_out = com->it_in;
958
959	/* attempt to determine UART type */
960	printf("sio%d: type", unit);
961
962
963#ifdef COM_MULTIPORT
964	if (!COM_ISMULTIPORT(flags) && !COM_IIR_TXRDYBUG(flags))
965#else
966	if (!COM_IIR_TXRDYBUG(flags))
967#endif
968	{
969		u_char	scr;
970		u_char	scr1;
971		u_char	scr2;
972
973		scr = sio_getreg(com, com_scr);
974		sio_setreg(com, com_scr, 0xa5);
975		scr1 = sio_getreg(com, com_scr);
976		sio_setreg(com, com_scr, 0x5a);
977		scr2 = sio_getreg(com, com_scr);
978		sio_setreg(com, com_scr, scr);
979		if (scr1 != 0xa5 || scr2 != 0x5a) {
980			printf(" 8250 or not responding");
981			goto determined_type;
982		}
983	}
984	sio_setreg(com, com_fifo, FIFO_ENABLE | FIFO_RX_HIGH);
985	DELAY(100);
986	com->st16650a = 0;
987	switch (inb(com->int_id_port) & IIR_FIFO_MASK) {
988	case FIFO_RX_LOW:
989		printf(" 16450");
990		break;
991	case FIFO_RX_MEDL:
992		printf(" 16450?");
993		break;
994	case FIFO_RX_MEDH:
995		printf(" 16550?");
996		break;
997	case FIFO_RX_HIGH:
998		if (COM_NOFIFO(flags)) {
999			printf(" 16550A fifo disabled");
1000		} else {
1001			com->hasfifo = TRUE;
1002			if (COM_ST16650A(flags)) {
1003				com->st16650a = 1;
1004				com->tx_fifo_size = 32;
1005				printf(" ST16650A");
1006			} else {
1007				com->tx_fifo_size = COM_FIFOSIZE(flags);
1008				printf(" 16550A");
1009			}
1010		}
1011#ifdef COM_ESP
1012		for (espp = likely_esp_ports; *espp != 0; espp++)
1013			if (espattach(com, *espp)) {
1014				com->tx_fifo_size = 1024;
1015				break;
1016			}
1017#endif
1018		if (!com->st16650a) {
1019			if (!com->tx_fifo_size)
1020				com->tx_fifo_size = 16;
1021			else
1022				printf(" lookalike with %d bytes FIFO",
1023				    com->tx_fifo_size);
1024		}
1025
1026		break;
1027	}
1028
1029#ifdef COM_ESP
1030	if (com->esp) {
1031		/*
1032		 * Set 16550 compatibility mode.
1033		 * We don't use the ESP_MODE_SCALE bit to increase the
1034		 * fifo trigger levels because we can't handle large
1035		 * bursts of input.
1036		 * XXX flow control should be set in comparam(), not here.
1037		 */
1038		outb(com->esp_port + ESP_CMD1, ESP_SETMODE);
1039		outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO);
1040
1041		/* Set RTS/CTS flow control. */
1042		outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE);
1043		outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS);
1044		outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS);
1045
1046		/* Set flow-control levels. */
1047		outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW);
1048		outb(com->esp_port + ESP_CMD2, HIBYTE(768));
1049		outb(com->esp_port + ESP_CMD2, LOBYTE(768));
1050		outb(com->esp_port + ESP_CMD2, HIBYTE(512));
1051		outb(com->esp_port + ESP_CMD2, LOBYTE(512));
1052	}
1053#endif /* COM_ESP */
1054	sio_setreg(com, com_fifo, 0);
1055determined_type: ;
1056
1057#ifdef COM_MULTIPORT
1058	if (COM_ISMULTIPORT(flags)) {
1059		device_t masterdev;
1060
1061		com->multiport = TRUE;
1062		printf(" (multiport");
1063		if (unit == COM_MPMASTER(flags))
1064			printf(" master");
1065		printf(")");
1066		masterdev = devclass_get_device(sio_devclass,
1067		    COM_MPMASTER(flags));
1068		com->no_irq = (masterdev == NULL || bus_get_resource(masterdev,
1069		    SYS_RES_IRQ, 0, NULL, NULL) != 0);
1070	 }
1071#endif /* COM_MULTIPORT */
1072	if (unit == comconsole)
1073		printf(", console");
1074	if (COM_IIR_TXRDYBUG(flags))
1075		printf(" with a bogus IIR_TXRDY register");
1076	printf("\n");
1077
1078	if (sio_fast_ih == NULL) {
1079		swi_add(&tty_ithd, "tty:sio", siopoll, NULL, SWI_TTY, 0,
1080		    &sio_fast_ih);
1081		swi_add(&clk_ithd, "tty:sio", siopoll, NULL, SWI_TTY, 0,
1082		    &sio_slow_ih);
1083	}
1084	com->devs[0] = make_dev(&sio_cdevsw, unit,
1085	    UID_ROOT, GID_WHEEL, 0600, "ttyd%r", unit);
1086	com->devs[1] = make_dev(&sio_cdevsw, unit | CONTROL_INIT_STATE,
1087	    UID_ROOT, GID_WHEEL, 0600, "ttyid%r", unit);
1088	com->devs[2] = make_dev(&sio_cdevsw, unit | CONTROL_LOCK_STATE,
1089	    UID_ROOT, GID_WHEEL, 0600, "ttyld%r", unit);
1090	com->devs[3] = make_dev(&sio_cdevsw, unit | CALLOUT_MASK,
1091	    UID_UUCP, GID_DIALER, 0660, "cuaa%r", unit);
1092	com->devs[4] = make_dev(&sio_cdevsw,
1093	    unit | CALLOUT_MASK | CONTROL_INIT_STATE,
1094	    UID_UUCP, GID_DIALER, 0660, "cuaia%r", unit);
1095	com->devs[5] = make_dev(&sio_cdevsw,
1096	    unit | CALLOUT_MASK | CONTROL_LOCK_STATE,
1097	    UID_UUCP, GID_DIALER, 0660, "cuala%r", unit);
1098	com->flags = flags;
1099	com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR;
1100	pps_init(&com->pps);
1101
1102	rid = 0;
1103	com->irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0ul, ~0ul, 1,
1104	    RF_ACTIVE);
1105	if (com->irqres) {
1106		ret = BUS_SETUP_INTR(device_get_parent(dev), dev, com->irqres,
1107				     INTR_TYPE_TTY | INTR_FAST,
1108				     siointr, com, &com->cookie);
1109		if (ret) {
1110			ret = BUS_SETUP_INTR(device_get_parent(dev), dev,
1111					     com->irqres, INTR_TYPE_TTY,
1112					     siointr, com, &com->cookie);
1113			if (ret == 0)
1114				device_printf(dev, "unable to activate interrupt in fast mode - using normal mode\n");
1115		}
1116		if (ret)
1117			device_printf(dev, "could not activate interrupt\n");
1118#if defined(DDB) && (defined(BREAK_TO_DEBUGGER) || \
1119    defined(ALT_BREAK_TO_DEBUGGER))
1120		/*
1121		 * Enable interrupts for early break-to-debugger support
1122		 * on the console.
1123		 */
1124		if (ret == 0 && unit == comconsole)
1125			outb(siocniobase + com_ier, IER_ERXRDY | IER_ERLS |
1126			    IER_EMSC);
1127#endif
1128	}
1129
1130	return (0);
1131}
1132
1133static int
1134sioopen(dev, flag, mode, td)
1135	dev_t		dev;
1136	int		flag;
1137	int		mode;
1138	struct thread	*td;
1139{
1140	struct com_s	*com;
1141	int		error;
1142	int		mynor;
1143	int		s;
1144	struct tty	*tp;
1145	int		unit;
1146
1147	mynor = minor(dev);
1148	unit = MINOR_TO_UNIT(mynor);
1149	com = com_addr(unit);
1150	if (com == NULL)
1151		return (ENXIO);
1152	if (com->gone)
1153		return (ENXIO);
1154	if (mynor & CONTROL_MASK)
1155		return (0);
1156	tp = dev->si_tty = com->tp = ttymalloc(com->tp);
1157	s = spltty();
1158	/*
1159	 * We jump to this label after all non-interrupted sleeps to pick
1160	 * up any changes of the device state.
1161	 */
1162open_top:
1163	while (com->state & CS_DTR_OFF) {
1164		error = tsleep(&com->dtr_wait, TTIPRI | PCATCH, "siodtr", 0);
1165		if (com_addr(unit) == NULL)
1166			return (ENXIO);
1167		if (error != 0 || com->gone)
1168			goto out;
1169	}
1170	if (tp->t_state & TS_ISOPEN) {
1171		/*
1172		 * The device is open, so everything has been initialized.
1173		 * Handle conflicts.
1174		 */
1175		if (mynor & CALLOUT_MASK) {
1176			if (!com->active_out) {
1177				error = EBUSY;
1178				goto out;
1179			}
1180		} else {
1181			if (com->active_out) {
1182				if (flag & O_NONBLOCK) {
1183					error = EBUSY;
1184					goto out;
1185				}
1186				error =	tsleep(&com->active_out,
1187					       TTIPRI | PCATCH, "siobi", 0);
1188				if (com_addr(unit) == NULL)
1189					return (ENXIO);
1190				if (error != 0 || com->gone)
1191					goto out;
1192				goto open_top;
1193			}
1194		}
1195		if (tp->t_state & TS_XCLUDE &&
1196		    suser_td(td)) {
1197			error = EBUSY;
1198			goto out;
1199		}
1200	} else {
1201		/*
1202		 * The device isn't open, so there are no conflicts.
1203		 * Initialize it.  Initialization is done twice in many
1204		 * cases: to preempt sleeping callin opens if we are
1205		 * callout, and to complete a callin open after DCD rises.
1206		 */
1207		tp->t_oproc = comstart;
1208		tp->t_param = comparam;
1209		tp->t_stop = comstop;
1210		tp->t_dev = dev;
1211		tp->t_termios = mynor & CALLOUT_MASK
1212				? com->it_out : com->it_in;
1213		(void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET);
1214		com->poll = com->no_irq;
1215		com->poll_output = com->loses_outints;
1216		++com->wopeners;
1217		error = comparam(tp, &tp->t_termios);
1218		--com->wopeners;
1219		if (error != 0)
1220			goto out;
1221		/*
1222		 * XXX we should goto open_top if comparam() slept.
1223		 */
1224		if (com->hasfifo) {
1225			/*
1226			 * (Re)enable and drain fifos.
1227			 *
1228			 * Certain SMC chips cause problems if the fifos
1229			 * are enabled while input is ready.  Turn off the
1230			 * fifo if necessary to clear the input.  We test
1231			 * the input ready bit after enabling the fifos
1232			 * since we've already enabled them in comparam()
1233			 * and to handle races between enabling and fresh
1234			 * input.
1235			 */
1236			while (TRUE) {
1237				sio_setreg(com, com_fifo,
1238					   FIFO_RCV_RST | FIFO_XMT_RST
1239					   | com->fifo_image);
1240				/*
1241				 * XXX the delays are for superstitious
1242				 * historical reasons.  It must be less than
1243				 * the character time at the maximum
1244				 * supported speed (87 usec at 115200 bps
1245				 * 8N1).  Otherwise we might loop endlessly
1246				 * if data is streaming in.  We used to use
1247				 * delays of 100.  That usually worked
1248				 * because DELAY(100) used to usually delay
1249				 * for about 85 usec instead of 100.
1250				 */
1251				DELAY(50);
1252				if (!(inb(com->line_status_port) & LSR_RXRDY))
1253					break;
1254				sio_setreg(com, com_fifo, 0);
1255				DELAY(50);
1256				(void) inb(com->data_port);
1257			}
1258		}
1259
1260		mtx_lock_spin(&sio_lock);
1261		(void) inb(com->line_status_port);
1262		(void) inb(com->data_port);
1263		com->prev_modem_status = com->last_modem_status
1264		    = inb(com->modem_status_port);
1265		if (COM_IIR_TXRDYBUG(com->flags)) {
1266			outb(com->intr_ctl_port, IER_ERXRDY | IER_ERLS
1267						| IER_EMSC);
1268		} else {
1269			outb(com->intr_ctl_port, IER_ERXRDY | IER_ETXRDY
1270						| IER_ERLS | IER_EMSC);
1271		}
1272		mtx_unlock_spin(&sio_lock);
1273		/*
1274		 * Handle initial DCD.  Callout devices get a fake initial
1275		 * DCD (trapdoor DCD).  If we are callout, then any sleeping
1276		 * callin opens get woken up and resume sleeping on "siobi"
1277		 * instead of "siodcd".
1278		 */
1279		/*
1280		 * XXX `mynor & CALLOUT_MASK' should be
1281		 * `tp->t_cflag & (SOFT_CARRIER | TRAPDOOR_CARRIER) where
1282		 * TRAPDOOR_CARRIER is the default initial state for callout
1283		 * devices and SOFT_CARRIER is like CLOCAL except it hides
1284		 * the true carrier.
1285		 */
1286		if (com->prev_modem_status & MSR_DCD || mynor & CALLOUT_MASK)
1287			(*linesw[tp->t_line].l_modem)(tp, 1);
1288	}
1289	/*
1290	 * Wait for DCD if necessary.
1291	 */
1292	if (!(tp->t_state & TS_CARR_ON) && !(mynor & CALLOUT_MASK)
1293	    && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) {
1294		++com->wopeners;
1295		error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "siodcd", 0);
1296		if (com_addr(unit) == NULL)
1297			return (ENXIO);
1298		--com->wopeners;
1299		if (error != 0 || com->gone)
1300			goto out;
1301		goto open_top;
1302	}
1303	error =	(*linesw[tp->t_line].l_open)(dev, tp);
1304	disc_optim(tp, &tp->t_termios, com);
1305	if (tp->t_state & TS_ISOPEN && mynor & CALLOUT_MASK)
1306		com->active_out = TRUE;
1307	siosettimeout();
1308out:
1309	splx(s);
1310	if (!(tp->t_state & TS_ISOPEN) && com->wopeners == 0)
1311		comhardclose(com);
1312	return (error);
1313}
1314
1315static int
1316sioclose(dev, flag, mode, td)
1317	dev_t		dev;
1318	int		flag;
1319	int		mode;
1320	struct thread	*td;
1321{
1322	struct com_s	*com;
1323	int		mynor;
1324	int		s;
1325	struct tty	*tp;
1326
1327	mynor = minor(dev);
1328	if (mynor & CONTROL_MASK)
1329		return (0);
1330	com = com_addr(MINOR_TO_UNIT(mynor));
1331	if (com == NULL)
1332		return (ENODEV);
1333	tp = com->tp;
1334	s = spltty();
1335	(*linesw[tp->t_line].l_close)(tp, flag);
1336	disc_optim(tp, &tp->t_termios, com);
1337	comstop(tp, FREAD | FWRITE);
1338	comhardclose(com);
1339	ttyclose(tp);
1340	siosettimeout();
1341	splx(s);
1342	if (com->gone) {
1343		printf("sio%d: gone\n", com->unit);
1344		s = spltty();
1345		if (com->ibuf != NULL)
1346			free(com->ibuf, M_DEVBUF);
1347		bzero(tp, sizeof *tp);
1348		splx(s);
1349	}
1350	return (0);
1351}
1352
1353static void
1354comhardclose(com)
1355	struct com_s	*com;
1356{
1357	int		s;
1358	struct tty	*tp;
1359	int		unit;
1360
1361	unit = com->unit;
1362	s = spltty();
1363	com->poll = FALSE;
1364	com->poll_output = FALSE;
1365	com->do_timestamp = FALSE;
1366	com->do_dcd_timestamp = FALSE;
1367	com->pps.ppsparam.mode = 0;
1368	sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
1369	tp = com->tp;
1370
1371#if defined(DDB) && (defined(BREAK_TO_DEBUGGER) || \
1372    defined(ALT_BREAK_TO_DEBUGGER))
1373	/*
1374	 * Leave interrupts enabled and don't clear DTR if this is the
1375	 * console. This allows us to detect break-to-debugger events
1376	 * while the console device is closed.
1377	 */
1378	if (com->unit != comconsole)
1379#endif
1380	{
1381		sio_setreg(com, com_ier, 0);
1382		if (tp->t_cflag & HUPCL
1383		    /*
1384		     * XXX we will miss any carrier drop between here and the
1385		     * next open.  Perhaps we should watch DCD even when the
1386		     * port is closed; it is not sufficient to check it at
1387		     * the next open because it might go up and down while
1388		     * we're not watching.
1389		     */
1390		    || (!com->active_out
1391		        && !(com->prev_modem_status & MSR_DCD)
1392		        && !(com->it_in.c_cflag & CLOCAL))
1393		    || !(tp->t_state & TS_ISOPEN)) {
1394			(void)commctl(com, TIOCM_DTR, DMBIC);
1395			if (com->dtr_wait != 0 && !(com->state & CS_DTR_OFF)) {
1396				timeout(siodtrwakeup, com, com->dtr_wait);
1397				com->state |= CS_DTR_OFF;
1398			}
1399		}
1400	}
1401	if (com->hasfifo) {
1402		/*
1403		 * Disable fifos so that they are off after controlled
1404		 * reboots.  Some BIOSes fail to detect 16550s when the
1405		 * fifos are enabled.
1406		 */
1407		sio_setreg(com, com_fifo, 0);
1408	}
1409	com->active_out = FALSE;
1410	wakeup(&com->active_out);
1411	wakeup(TSA_CARR_ON(tp));	/* restart any wopeners */
1412	splx(s);
1413}
1414
1415static int
1416sioread(dev, uio, flag)
1417	dev_t		dev;
1418	struct uio	*uio;
1419	int		flag;
1420{
1421	int		mynor;
1422	struct com_s	*com;
1423
1424	mynor = minor(dev);
1425	if (mynor & CONTROL_MASK)
1426		return (ENODEV);
1427	com = com_addr(MINOR_TO_UNIT(mynor));
1428	if (com == NULL || com->gone)
1429		return (ENODEV);
1430	return ((*linesw[com->tp->t_line].l_read)(com->tp, uio, flag));
1431}
1432
1433static int
1434siowrite(dev, uio, flag)
1435	dev_t		dev;
1436	struct uio	*uio;
1437	int		flag;
1438{
1439	int		mynor;
1440	struct com_s	*com;
1441	int		unit;
1442
1443	mynor = minor(dev);
1444	if (mynor & CONTROL_MASK)
1445		return (ENODEV);
1446
1447	unit = MINOR_TO_UNIT(mynor);
1448	com = com_addr(unit);
1449	if (com == NULL || com->gone)
1450		return (ENODEV);
1451	/*
1452	 * (XXX) We disallow virtual consoles if the physical console is
1453	 * a serial port.  This is in case there is a display attached that
1454	 * is not the console.  In that situation we don't need/want the X
1455	 * server taking over the console.
1456	 */
1457	if (constty != NULL && unit == comconsole)
1458		constty = NULL;
1459	return ((*linesw[com->tp->t_line].l_write)(com->tp, uio, flag));
1460}
1461
1462static void
1463siobusycheck(chan)
1464	void	*chan;
1465{
1466	struct com_s	*com;
1467	int		s;
1468
1469	com = (struct com_s *)chan;
1470
1471	/*
1472	 * Clear TS_BUSY if low-level output is complete.
1473	 * spl locking is sufficient because siointr1() does not set CS_BUSY.
1474	 * If siointr1() clears CS_BUSY after we look at it, then we'll get
1475	 * called again.  Reading the line status port outside of siointr1()
1476	 * is safe because CS_BUSY is clear so there are no output interrupts
1477	 * to lose.
1478	 */
1479	s = spltty();
1480	if (com->state & CS_BUSY)
1481		com->extra_state &= ~CSE_BUSYCHECK;	/* False alarm. */
1482	else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY))
1483	    == (LSR_TSRE | LSR_TXRDY)) {
1484		com->tp->t_state &= ~TS_BUSY;
1485		ttwwakeup(com->tp);
1486		com->extra_state &= ~CSE_BUSYCHECK;
1487	} else
1488		timeout(siobusycheck, com, hz / 100);
1489	splx(s);
1490}
1491
1492static u_int
1493siodivisor(rclk, speed)
1494	u_long	rclk;
1495	speed_t	speed;
1496{
1497	long	actual_speed;
1498	u_int	divisor;
1499	int	error;
1500
1501	if (speed == 0 || speed > (ULONG_MAX - 1) / 8)
1502		return (0);
1503	divisor = (rclk / (8UL * speed) + 1) / 2;
1504	if (divisor == 0 || divisor >= 65536)
1505		return (0);
1506	actual_speed = rclk / (16UL * divisor);
1507
1508	/* 10 times error in percent: */
1509	error = ((actual_speed - (long)speed) * 2000 / (long)speed + 1) / 2;
1510
1511	/* 3.0% maximum error tolerance: */
1512	if (error < -30 || error > 30)
1513		return (0);
1514
1515	return (divisor);
1516}
1517
1518static void
1519siodtrwakeup(chan)
1520	void	*chan;
1521{
1522	struct com_s	*com;
1523
1524	com = (struct com_s *)chan;
1525	com->state &= ~CS_DTR_OFF;
1526	wakeup(&com->dtr_wait);
1527}
1528
1529/*
1530 * Call this function with the sio_lock mutex held.  It will return with the
1531 * lock still held.
1532 */
1533static void
1534sioinput(com)
1535	struct com_s	*com;
1536{
1537	u_char		*buf;
1538	int		incc;
1539	u_char		line_status;
1540	int		recv_data;
1541	struct tty	*tp;
1542
1543	buf = com->ibuf;
1544	tp = com->tp;
1545	if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) {
1546		com_events -= (com->iptr - com->ibuf);
1547		com->iptr = com->ibuf;
1548		return;
1549	}
1550	if (tp->t_state & TS_CAN_BYPASS_L_RINT) {
1551		/*
1552		 * Avoid the grotesquely inefficient lineswitch routine
1553		 * (ttyinput) in "raw" mode.  It usually takes about 450
1554		 * instructions (that's without canonical processing or echo!).
1555		 * slinput is reasonably fast (usually 40 instructions plus
1556		 * call overhead).
1557		 */
1558		do {
1559			/*
1560			 * This may look odd, but it is using save-and-enable
1561			 * semantics instead of the save-and-disable semantics
1562			 * that are used everywhere else.
1563			 */
1564			mtx_unlock_spin(&sio_lock);
1565			incc = com->iptr - buf;
1566			if (tp->t_rawq.c_cc + incc > tp->t_ihiwat
1567			    && (com->state & CS_RTS_IFLOW
1568				|| tp->t_iflag & IXOFF)
1569			    && !(tp->t_state & TS_TBLOCK))
1570				ttyblock(tp);
1571			com->delta_error_counts[CE_TTY_BUF_OVERFLOW]
1572				+= b_to_q((char *)buf, incc, &tp->t_rawq);
1573			buf += incc;
1574			tk_nin += incc;
1575			tk_rawcc += incc;
1576			tp->t_rawcc += incc;
1577			ttwakeup(tp);
1578			if (tp->t_state & TS_TTSTOP
1579			    && (tp->t_iflag & IXANY
1580				|| tp->t_cc[VSTART] == tp->t_cc[VSTOP])) {
1581				tp->t_state &= ~TS_TTSTOP;
1582				tp->t_lflag &= ~FLUSHO;
1583				comstart(tp);
1584			}
1585			mtx_lock_spin(&sio_lock);
1586		} while (buf < com->iptr);
1587	} else {
1588		do {
1589			/*
1590			 * This may look odd, but it is using save-and-enable
1591			 * semantics instead of the save-and-disable semantics
1592			 * that are used everywhere else.
1593			 */
1594			mtx_unlock_spin(&sio_lock);
1595			line_status = buf[com->ierroff];
1596			recv_data = *buf++;
1597			if (line_status
1598			    & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) {
1599				if (line_status & LSR_BI)
1600					recv_data |= TTY_BI;
1601				if (line_status & LSR_FE)
1602					recv_data |= TTY_FE;
1603				if (line_status & LSR_OE)
1604					recv_data |= TTY_OE;
1605				if (line_status & LSR_PE)
1606					recv_data |= TTY_PE;
1607			}
1608			(*linesw[tp->t_line].l_rint)(recv_data, tp);
1609			mtx_lock_spin(&sio_lock);
1610		} while (buf < com->iptr);
1611	}
1612	com_events -= (com->iptr - com->ibuf);
1613	com->iptr = com->ibuf;
1614
1615	/*
1616	 * There is now room for another low-level buffer full of input,
1617	 * so enable RTS if it is now disabled and there is room in the
1618	 * high-level buffer.
1619	 */
1620	if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) &&
1621	    !(tp->t_state & TS_TBLOCK))
1622		outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
1623}
1624
1625void
1626siointr(arg)
1627	void		*arg;
1628{
1629	struct com_s	*com;
1630
1631#ifndef COM_MULTIPORT
1632	com = (struct com_s *)arg;
1633
1634	mtx_lock_spin(&sio_lock);
1635	siointr1(com);
1636	mtx_unlock_spin(&sio_lock);
1637#else /* COM_MULTIPORT */
1638	bool_t		possibly_more_intrs;
1639	int		unit;
1640
1641	/*
1642	 * Loop until there is no activity on any port.  This is necessary
1643	 * to get an interrupt edge more than to avoid another interrupt.
1644	 * If the IRQ signal is just an OR of the IRQ signals from several
1645	 * devices, then the edge from one may be lost because another is
1646	 * on.
1647	 */
1648	mtx_lock_spin(&sio_lock);
1649	do {
1650		possibly_more_intrs = FALSE;
1651		for (unit = 0; unit < sio_numunits; ++unit) {
1652			com = com_addr(unit);
1653			/*
1654			 * XXX COM_LOCK();
1655			 * would it work here, or be counter-productive?
1656			 */
1657			if (com != NULL
1658			    && !com->gone
1659			    && (inb(com->int_id_port) & IIR_IMASK)
1660			       != IIR_NOPEND) {
1661				siointr1(com);
1662				possibly_more_intrs = TRUE;
1663			}
1664			/* XXX COM_UNLOCK(); */
1665		}
1666	} while (possibly_more_intrs);
1667	mtx_unlock_spin(&sio_lock);
1668#endif /* COM_MULTIPORT */
1669}
1670
1671static void
1672siointr1(com)
1673	struct com_s	*com;
1674{
1675	u_char	line_status;
1676	u_char	modem_status;
1677	u_char	*ioptr;
1678	u_char	recv_data;
1679	u_char	int_ctl;
1680	u_char	int_ctl_new;
1681	struct	timecounter *tc;
1682	u_int	count;
1683
1684	int_ctl = inb(com->intr_ctl_port);
1685	int_ctl_new = int_ctl;
1686
1687	while (!com->gone) {
1688		if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) {
1689			modem_status = inb(com->modem_status_port);
1690		        if ((modem_status ^ com->last_modem_status) & MSR_DCD) {
1691				tc = timecounter;
1692				count = tc->tc_get_timecount(tc);
1693				pps_event(&com->pps, tc, count,
1694				    (modem_status & MSR_DCD) ?
1695				    PPS_CAPTUREASSERT : PPS_CAPTURECLEAR);
1696			}
1697		}
1698		line_status = inb(com->line_status_port);
1699
1700		/* input event? (check first to help avoid overruns) */
1701		while (line_status & LSR_RCV_MASK) {
1702			/* break/unnattached error bits or real input? */
1703			if (!(line_status & LSR_RXRDY))
1704				recv_data = 0;
1705			else
1706				recv_data = inb(com->data_port);
1707#if defined(DDB) && defined(ALT_BREAK_TO_DEBUGGER)
1708			/*
1709			 * Solaris implements a new BREAK which is initiated
1710			 * by a character sequence CR ~ ^b which is similar
1711			 * to a familiar pattern used on Sun servers by the
1712			 * Remote Console.
1713			 */
1714#define	KEY_CRTLB	2	/* ^B */
1715#define	KEY_CR		13	/* CR '\r' */
1716#define	KEY_TILDE	126	/* ~ */
1717
1718			if (com->unit == comconsole) {
1719				static int brk_state1 = 0, brk_state2 = 0;
1720				if (recv_data == KEY_CR) {
1721					brk_state1 = recv_data;
1722					brk_state2 = 0;
1723				} else if (brk_state1 == KEY_CR
1724					   && (recv_data == KEY_TILDE
1725					       || recv_data == KEY_CRTLB)) {
1726					if (recv_data == KEY_TILDE)
1727						brk_state2 = recv_data;
1728					else if (brk_state2 == KEY_TILDE
1729						 && recv_data == KEY_CRTLB) {
1730							breakpoint();
1731							brk_state1 = 0;
1732							brk_state2 = 0;
1733							goto cont;
1734					} else
1735						brk_state2 = 0;
1736				} else
1737					brk_state1 = 0;
1738			}
1739#endif
1740			if (line_status & (LSR_BI | LSR_FE | LSR_PE)) {
1741				/*
1742				 * Don't store BI if IGNBRK or FE/PE if IGNPAR.
1743				 * Otherwise, push the work to a higher level
1744				 * (to handle PARMRK) if we're bypassing.
1745				 * Otherwise, convert BI/FE and PE+INPCK to 0.
1746				 *
1747				 * This makes bypassing work right in the
1748				 * usual "raw" case (IGNBRK set, and IGNPAR
1749				 * and INPCK clear).
1750				 *
1751				 * Note: BI together with FE/PE means just BI.
1752				 */
1753				if (line_status & LSR_BI) {
1754#if defined(DDB) && defined(BREAK_TO_DEBUGGER)
1755					if (com->unit == comconsole) {
1756						breakpoint();
1757						goto cont;
1758					}
1759#endif
1760					if (com->tp == NULL
1761					    || com->tp->t_iflag & IGNBRK)
1762						goto cont;
1763				} else {
1764					if (com->tp == NULL
1765					    || com->tp->t_iflag & IGNPAR)
1766						goto cont;
1767				}
1768				if (com->tp->t_state & TS_CAN_BYPASS_L_RINT
1769				    && (line_status & (LSR_BI | LSR_FE)
1770					|| com->tp->t_iflag & INPCK))
1771					recv_data = 0;
1772			}
1773			++com->bytes_in;
1774			if (com->hotchar != 0 && recv_data == com->hotchar)
1775				swi_sched(sio_fast_ih, 0);
1776			ioptr = com->iptr;
1777			if (ioptr >= com->ibufend)
1778				CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW);
1779			else {
1780				if (com->do_timestamp)
1781					microtime(&com->timestamp);
1782				++com_events;
1783				swi_sched(sio_slow_ih, SWI_DELAY);
1784#if 0 /* for testing input latency vs efficiency */
1785if (com->iptr - com->ibuf == 8)
1786	swi_sched(sio_fast_ih, 0);
1787#endif
1788				ioptr[0] = recv_data;
1789				ioptr[com->ierroff] = line_status;
1790				com->iptr = ++ioptr;
1791				if (ioptr == com->ihighwater
1792				    && com->state & CS_RTS_IFLOW)
1793					outb(com->modem_ctl_port,
1794					     com->mcr_image &= ~MCR_RTS);
1795				if (line_status & LSR_OE)
1796					CE_RECORD(com, CE_OVERRUN);
1797			}
1798cont:
1799			/*
1800			 * "& 0x7F" is to avoid the gcc-1.40 generating a slow
1801			 * jump from the top of the loop to here
1802			 */
1803			line_status = inb(com->line_status_port) & 0x7F;
1804		}
1805
1806		/* modem status change? (always check before doing output) */
1807		modem_status = inb(com->modem_status_port);
1808		if (modem_status != com->last_modem_status) {
1809			if (com->do_dcd_timestamp
1810			    && !(com->last_modem_status & MSR_DCD)
1811			    && modem_status & MSR_DCD)
1812				microtime(&com->dcd_timestamp);
1813
1814			/*
1815			 * Schedule high level to handle DCD changes.  Note
1816			 * that we don't use the delta bits anywhere.  Some
1817			 * UARTs mess them up, and it's easy to remember the
1818			 * previous bits and calculate the delta.
1819			 */
1820			com->last_modem_status = modem_status;
1821			if (!(com->state & CS_CHECKMSR)) {
1822				com_events += LOTS_OF_EVENTS;
1823				com->state |= CS_CHECKMSR;
1824				swi_sched(sio_fast_ih, 0);
1825			}
1826
1827			/* handle CTS change immediately for crisp flow ctl */
1828			if (com->state & CS_CTS_OFLOW) {
1829				if (modem_status & MSR_CTS)
1830					com->state |= CS_ODEVREADY;
1831				else
1832					com->state &= ~CS_ODEVREADY;
1833			}
1834		}
1835
1836		/* output queued and everything ready? */
1837		if (line_status & LSR_TXRDY
1838		    && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) {
1839			ioptr = com->obufq.l_head;
1840			if (com->tx_fifo_size > 1) {
1841				u_int	ocount;
1842
1843				ocount = com->obufq.l_tail - ioptr;
1844				if (ocount > com->tx_fifo_size)
1845					ocount = com->tx_fifo_size;
1846				com->bytes_out += ocount;
1847				do
1848					outb(com->data_port, *ioptr++);
1849				while (--ocount != 0);
1850			} else {
1851				outb(com->data_port, *ioptr++);
1852				++com->bytes_out;
1853			}
1854			com->obufq.l_head = ioptr;
1855			if (COM_IIR_TXRDYBUG(com->flags)) {
1856				int_ctl_new = int_ctl | IER_ETXRDY;
1857			}
1858			if (ioptr >= com->obufq.l_tail) {
1859				struct lbq	*qp;
1860
1861				qp = com->obufq.l_next;
1862				qp->l_queued = FALSE;
1863				qp = qp->l_next;
1864				if (qp != NULL) {
1865					com->obufq.l_head = qp->l_head;
1866					com->obufq.l_tail = qp->l_tail;
1867					com->obufq.l_next = qp;
1868				} else {
1869					/* output just completed */
1870					if (COM_IIR_TXRDYBUG(com->flags)) {
1871						int_ctl_new = int_ctl & ~IER_ETXRDY;
1872					}
1873					com->state &= ~CS_BUSY;
1874				}
1875				if (!(com->state & CS_ODONE)) {
1876					com_events += LOTS_OF_EVENTS;
1877					com->state |= CS_ODONE;
1878					/* handle at high level ASAP */
1879					swi_sched(sio_fast_ih, 0);
1880				}
1881			}
1882			if (COM_IIR_TXRDYBUG(com->flags) && (int_ctl != int_ctl_new)) {
1883				outb(com->intr_ctl_port, int_ctl_new);
1884			}
1885		}
1886
1887		/* finished? */
1888#ifndef COM_MULTIPORT
1889		if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND)
1890#endif /* COM_MULTIPORT */
1891			return;
1892	}
1893}
1894
1895static int
1896sioioctl(dev, cmd, data, flag, td)
1897	dev_t		dev;
1898	u_long		cmd;
1899	caddr_t		data;
1900	int		flag;
1901	struct thread	*td;
1902{
1903	struct com_s	*com;
1904	int		error;
1905	int		mynor;
1906	int		s;
1907	struct tty	*tp;
1908#if defined(COMPAT_43) || defined(COMPAT_SUNOS)
1909	u_long		oldcmd;
1910	struct termios	term;
1911#endif
1912
1913	mynor = minor(dev);
1914	com = com_addr(MINOR_TO_UNIT(mynor));
1915	if (com == NULL || com->gone)
1916		return (ENODEV);
1917	if (mynor & CONTROL_MASK) {
1918		struct termios	*ct;
1919
1920		switch (mynor & CONTROL_MASK) {
1921		case CONTROL_INIT_STATE:
1922			ct = mynor & CALLOUT_MASK ? &com->it_out : &com->it_in;
1923			break;
1924		case CONTROL_LOCK_STATE:
1925			ct = mynor & CALLOUT_MASK ? &com->lt_out : &com->lt_in;
1926			break;
1927		default:
1928			return (ENODEV);	/* /dev/nodev */
1929		}
1930		switch (cmd) {
1931		case TIOCSETA:
1932			error = suser_td(td);
1933			if (error != 0)
1934				return (error);
1935			*ct = *(struct termios *)data;
1936			return (0);
1937		case TIOCGETA:
1938			*(struct termios *)data = *ct;
1939			return (0);
1940		case TIOCGETD:
1941			*(int *)data = TTYDISC;
1942			return (0);
1943		case TIOCGWINSZ:
1944			bzero(data, sizeof(struct winsize));
1945			return (0);
1946		default:
1947			return (ENOTTY);
1948		}
1949	}
1950	tp = com->tp;
1951#if defined(COMPAT_43) || defined(COMPAT_SUNOS)
1952	term = tp->t_termios;
1953	oldcmd = cmd;
1954	error = ttsetcompat(tp, &cmd, data, &term);
1955	if (error != 0)
1956		return (error);
1957	if (cmd != oldcmd)
1958		data = (caddr_t)&term;
1959#endif
1960	if (cmd == TIOCSETA || cmd == TIOCSETAW || cmd == TIOCSETAF) {
1961		int	cc;
1962		struct termios *dt = (struct termios *)data;
1963		struct termios *lt = mynor & CALLOUT_MASK
1964				     ? &com->lt_out : &com->lt_in;
1965
1966		dt->c_iflag = (tp->t_iflag & lt->c_iflag)
1967			      | (dt->c_iflag & ~lt->c_iflag);
1968		dt->c_oflag = (tp->t_oflag & lt->c_oflag)
1969			      | (dt->c_oflag & ~lt->c_oflag);
1970		dt->c_cflag = (tp->t_cflag & lt->c_cflag)
1971			      | (dt->c_cflag & ~lt->c_cflag);
1972		dt->c_lflag = (tp->t_lflag & lt->c_lflag)
1973			      | (dt->c_lflag & ~lt->c_lflag);
1974		for (cc = 0; cc < NCCS; ++cc)
1975			if (lt->c_cc[cc] != 0)
1976				dt->c_cc[cc] = tp->t_cc[cc];
1977		if (lt->c_ispeed != 0)
1978			dt->c_ispeed = tp->t_ispeed;
1979		if (lt->c_ospeed != 0)
1980			dt->c_ospeed = tp->t_ospeed;
1981	}
1982	error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, td);
1983	if (error != ENOIOCTL)
1984		return (error);
1985	s = spltty();
1986	error = ttioctl(tp, cmd, data, flag);
1987	disc_optim(tp, &tp->t_termios, com);
1988	if (error != ENOIOCTL) {
1989		splx(s);
1990		return (error);
1991	}
1992	switch (cmd) {
1993	case TIOCSBRK:
1994		sio_setreg(com, com_cfcr, com->cfcr_image |= CFCR_SBREAK);
1995		break;
1996	case TIOCCBRK:
1997		sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
1998		break;
1999	case TIOCSDTR:
2000		(void)commctl(com, TIOCM_DTR, DMBIS);
2001		break;
2002	case TIOCCDTR:
2003		(void)commctl(com, TIOCM_DTR, DMBIC);
2004		break;
2005	/*
2006	 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set.  The
2007	 * changes get undone on the next call to comparam().
2008	 */
2009	case TIOCMSET:
2010		(void)commctl(com, *(int *)data, DMSET);
2011		break;
2012	case TIOCMBIS:
2013		(void)commctl(com, *(int *)data, DMBIS);
2014		break;
2015	case TIOCMBIC:
2016		(void)commctl(com, *(int *)data, DMBIC);
2017		break;
2018	case TIOCMGET:
2019		*(int *)data = commctl(com, 0, DMGET);
2020		break;
2021	case TIOCMSDTRWAIT:
2022		/* must be root since the wait applies to following logins */
2023		error = suser_td(td);
2024		if (error != 0) {
2025			splx(s);
2026			return (error);
2027		}
2028		com->dtr_wait = *(int *)data * hz / 100;
2029		break;
2030	case TIOCMGDTRWAIT:
2031		*(int *)data = com->dtr_wait * 100 / hz;
2032		break;
2033	case TIOCTIMESTAMP:
2034		com->do_timestamp = TRUE;
2035		*(struct timeval *)data = com->timestamp;
2036		break;
2037	case TIOCDCDTIMESTAMP:
2038		com->do_dcd_timestamp = TRUE;
2039		*(struct timeval *)data = com->dcd_timestamp;
2040		break;
2041	default:
2042		splx(s);
2043		error = pps_ioctl(cmd, data, &com->pps);
2044		if (error == ENODEV)
2045			error = ENOTTY;
2046		return (error);
2047	}
2048	splx(s);
2049	return (0);
2050}
2051
2052/* software interrupt handler for SWI_TTY */
2053static void
2054siopoll(void *dummy)
2055{
2056	int		unit;
2057
2058	if (com_events == 0)
2059		return;
2060repeat:
2061	for (unit = 0; unit < sio_numunits; ++unit) {
2062		struct com_s	*com;
2063		int		incc;
2064		struct tty	*tp;
2065
2066		com = com_addr(unit);
2067		if (com == NULL)
2068			continue;
2069		tp = com->tp;
2070		if (tp == NULL || com->gone) {
2071			/*
2072			 * Discard any events related to never-opened or
2073			 * going-away devices.
2074			 */
2075			mtx_lock_spin(&sio_lock);
2076			incc = com->iptr - com->ibuf;
2077			com->iptr = com->ibuf;
2078			if (com->state & CS_CHECKMSR) {
2079				incc += LOTS_OF_EVENTS;
2080				com->state &= ~CS_CHECKMSR;
2081			}
2082			com_events -= incc;
2083			mtx_unlock_spin(&sio_lock);
2084			continue;
2085		}
2086		if (com->iptr != com->ibuf) {
2087			mtx_lock_spin(&sio_lock);
2088			sioinput(com);
2089			mtx_unlock_spin(&sio_lock);
2090		}
2091		if (com->state & CS_CHECKMSR) {
2092			u_char	delta_modem_status;
2093
2094			mtx_lock_spin(&sio_lock);
2095			delta_modem_status = com->last_modem_status
2096					     ^ com->prev_modem_status;
2097			com->prev_modem_status = com->last_modem_status;
2098			com_events -= LOTS_OF_EVENTS;
2099			com->state &= ~CS_CHECKMSR;
2100			mtx_unlock_spin(&sio_lock);
2101			if (delta_modem_status & MSR_DCD)
2102				(*linesw[tp->t_line].l_modem)
2103					(tp, com->prev_modem_status & MSR_DCD);
2104		}
2105		if (com->state & CS_ODONE) {
2106			mtx_lock_spin(&sio_lock);
2107			com_events -= LOTS_OF_EVENTS;
2108			com->state &= ~CS_ODONE;
2109			mtx_unlock_spin(&sio_lock);
2110			if (!(com->state & CS_BUSY)
2111			    && !(com->extra_state & CSE_BUSYCHECK)) {
2112				timeout(siobusycheck, com, hz / 100);
2113				com->extra_state |= CSE_BUSYCHECK;
2114			}
2115			(*linesw[tp->t_line].l_start)(tp);
2116		}
2117		if (com_events == 0)
2118			break;
2119	}
2120	if (com_events >= LOTS_OF_EVENTS)
2121		goto repeat;
2122}
2123
2124static int
2125comparam(tp, t)
2126	struct tty	*tp;
2127	struct termios	*t;
2128{
2129	u_int		cfcr;
2130	int		cflag;
2131	struct com_s	*com;
2132	u_int		divisor;
2133	u_char		dlbh;
2134	u_char		dlbl;
2135	int		s;
2136	int		unit;
2137
2138	unit = DEV_TO_UNIT(tp->t_dev);
2139	com = com_addr(unit);
2140	if (com == NULL)
2141		return (ENODEV);
2142
2143	/* do historical conversions */
2144	if (t->c_ispeed == 0)
2145		t->c_ispeed = t->c_ospeed;
2146
2147	/* check requested parameters */
2148	if (t->c_ospeed == 0)
2149		divisor = 0;
2150	else {
2151		if (t->c_ispeed != t->c_ospeed)
2152			return (EINVAL);
2153		divisor = siodivisor(com->rclk, t->c_ispeed);
2154		if (divisor == 0)
2155			return (EINVAL);
2156	}
2157
2158	/* parameters are OK, convert them to the com struct and the device */
2159	s = spltty();
2160	if (divisor == 0)
2161		(void)commctl(com, TIOCM_DTR, DMBIC);	/* hang up line */
2162	else
2163		(void)commctl(com, TIOCM_DTR, DMBIS);
2164	cflag = t->c_cflag;
2165	switch (cflag & CSIZE) {
2166	case CS5:
2167		cfcr = CFCR_5BITS;
2168		break;
2169	case CS6:
2170		cfcr = CFCR_6BITS;
2171		break;
2172	case CS7:
2173		cfcr = CFCR_7BITS;
2174		break;
2175	default:
2176		cfcr = CFCR_8BITS;
2177		break;
2178	}
2179	if (cflag & PARENB) {
2180		cfcr |= CFCR_PENAB;
2181		if (!(cflag & PARODD))
2182			cfcr |= CFCR_PEVEN;
2183	}
2184	if (cflag & CSTOPB)
2185		cfcr |= CFCR_STOPB;
2186
2187	if (com->hasfifo && divisor != 0) {
2188		/*
2189		 * Use a fifo trigger level low enough so that the input
2190		 * latency from the fifo is less than about 16 msec and
2191		 * the total latency is less than about 30 msec.  These
2192		 * latencies are reasonable for humans.  Serial comms
2193		 * protocols shouldn't expect anything better since modem
2194		 * latencies are larger.
2195		 *
2196		 * The fifo trigger level cannot be set at RX_HIGH for high
2197		 * speed connections without further work on reducing
2198		 * interrupt disablement times in other parts of the system,
2199		 * without producing silo overflow errors.
2200		 */
2201		com->fifo_image = t->c_ospeed <= 4800
2202				  ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_MEDH;
2203#ifdef COM_ESP
2204		/*
2205		 * The Hayes ESP card needs the fifo DMA mode bit set
2206		 * in compatibility mode.  If not, it will interrupt
2207		 * for each character received.
2208		 */
2209		if (com->esp)
2210			com->fifo_image |= FIFO_DMA_MODE;
2211#endif
2212		sio_setreg(com, com_fifo, com->fifo_image);
2213	}
2214
2215	/*
2216	 * This returns with interrupts disabled so that we can complete
2217	 * the speed change atomically.  Keeping interrupts disabled is
2218	 * especially important while com_data is hidden.
2219	 */
2220	(void) siosetwater(com, t->c_ispeed);
2221
2222	if (divisor != 0) {
2223		sio_setreg(com, com_cfcr, cfcr | CFCR_DLAB);
2224		/*
2225		 * Only set the divisor registers if they would change,
2226		 * since on some 16550 incompatibles (UMC8669F), setting
2227		 * them while input is arriving them loses sync until
2228		 * data stops arriving.
2229		 */
2230		dlbl = divisor & 0xFF;
2231		if (sio_getreg(com, com_dlbl) != dlbl)
2232			sio_setreg(com, com_dlbl, dlbl);
2233		dlbh = divisor >> 8;
2234		if (sio_getreg(com, com_dlbh) != dlbh)
2235			sio_setreg(com, com_dlbh, dlbh);
2236	}
2237
2238	sio_setreg(com, com_cfcr, com->cfcr_image = cfcr);
2239
2240	if (!(tp->t_state & TS_TTSTOP))
2241		com->state |= CS_TTGO;
2242
2243	if (cflag & CRTS_IFLOW) {
2244		if (com->st16650a) {
2245			sio_setreg(com, com_cfcr, 0xbf);
2246			sio_setreg(com, com_fifo,
2247				   sio_getreg(com, com_fifo) | 0x40);
2248		}
2249		com->state |= CS_RTS_IFLOW;
2250		/*
2251		 * If CS_RTS_IFLOW just changed from off to on, the change
2252		 * needs to be propagated to MCR_RTS.  This isn't urgent,
2253		 * so do it later by calling comstart() instead of repeating
2254		 * a lot of code from comstart() here.
2255		 */
2256	} else if (com->state & CS_RTS_IFLOW) {
2257		com->state &= ~CS_RTS_IFLOW;
2258		/*
2259		 * CS_RTS_IFLOW just changed from on to off.  Force MCR_RTS
2260		 * on here, since comstart() won't do it later.
2261		 */
2262		outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
2263		if (com->st16650a) {
2264			sio_setreg(com, com_cfcr, 0xbf);
2265			sio_setreg(com, com_fifo,
2266				   sio_getreg(com, com_fifo) & ~0x40);
2267		}
2268	}
2269
2270
2271	/*
2272	 * Set up state to handle output flow control.
2273	 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level?
2274	 * Now has 10+ msec latency, while CTS flow has 50- usec latency.
2275	 */
2276	com->state |= CS_ODEVREADY;
2277	com->state &= ~CS_CTS_OFLOW;
2278	if (cflag & CCTS_OFLOW) {
2279		com->state |= CS_CTS_OFLOW;
2280		if (!(com->last_modem_status & MSR_CTS))
2281			com->state &= ~CS_ODEVREADY;
2282		if (com->st16650a) {
2283			sio_setreg(com, com_cfcr, 0xbf);
2284			sio_setreg(com, com_fifo,
2285				   sio_getreg(com, com_fifo) | 0x80);
2286		}
2287	} else {
2288		if (com->st16650a) {
2289			sio_setreg(com, com_cfcr, 0xbf);
2290			sio_setreg(com, com_fifo,
2291				   sio_getreg(com, com_fifo) & ~0x80);
2292		}
2293	}
2294
2295	sio_setreg(com, com_cfcr, com->cfcr_image);
2296
2297	/* XXX shouldn't call functions while intrs are disabled. */
2298	disc_optim(tp, t, com);
2299	/*
2300	 * Recover from fiddling with CS_TTGO.  We used to call siointr1()
2301	 * unconditionally, but that defeated the careful discarding of
2302	 * stale input in sioopen().
2303	 */
2304	if (com->state >= (CS_BUSY | CS_TTGO))
2305		siointr1(com);
2306
2307	mtx_unlock_spin(&sio_lock);
2308	splx(s);
2309	comstart(tp);
2310	if (com->ibufold != NULL) {
2311		free(com->ibufold, M_DEVBUF);
2312		com->ibufold = NULL;
2313	}
2314	return (0);
2315}
2316
2317/*
2318 * This function must be called with the sio_lock mutex released and will
2319 * return with it obtained.
2320 */
2321static int
2322siosetwater(com, speed)
2323	struct com_s	*com;
2324	speed_t		speed;
2325{
2326	int		cp4ticks;
2327	u_char		*ibuf;
2328	int		ibufsize;
2329	struct tty	*tp;
2330
2331	/*
2332	 * Make the buffer size large enough to handle a softtty interrupt
2333	 * latency of about 2 ticks without loss of throughput or data
2334	 * (about 3 ticks if input flow control is not used or not honoured,
2335	 * but a bit less for CS5-CS7 modes).
2336	 */
2337	cp4ticks = speed / 10 / hz * 4;
2338	for (ibufsize = 128; ibufsize < cp4ticks;)
2339		ibufsize <<= 1;
2340	if (ibufsize == com->ibufsize) {
2341		mtx_lock_spin(&sio_lock);
2342		return (0);
2343	}
2344
2345	/*
2346	 * Allocate input buffer.  The extra factor of 2 in the size is
2347	 * to allow for an error byte for each input byte.
2348	 */
2349	ibuf = malloc(2 * ibufsize, M_DEVBUF, M_NOWAIT);
2350	if (ibuf == NULL) {
2351		mtx_lock_spin(&sio_lock);
2352		return (ENOMEM);
2353	}
2354
2355	/* Initialize non-critical variables. */
2356	com->ibufold = com->ibuf;
2357	com->ibufsize = ibufsize;
2358	tp = com->tp;
2359	if (tp != NULL) {
2360		tp->t_ififosize = 2 * ibufsize;
2361		tp->t_ispeedwat = (speed_t)-1;
2362		tp->t_ospeedwat = (speed_t)-1;
2363	}
2364
2365	/*
2366	 * Read current input buffer, if any.  Continue with interrupts
2367	 * disabled.
2368	 */
2369	mtx_lock_spin(&sio_lock);
2370	if (com->iptr != com->ibuf)
2371		sioinput(com);
2372
2373	/*-
2374	 * Initialize critical variables, including input buffer watermarks.
2375	 * The external device is asked to stop sending when the buffer
2376	 * exactly reaches high water, or when the high level requests it.
2377	 * The high level is notified immediately (rather than at a later
2378	 * clock tick) when this watermark is reached.
2379	 * The buffer size is chosen so the watermark should almost never
2380	 * be reached.
2381	 * The low watermark is invisibly 0 since the buffer is always
2382	 * emptied all at once.
2383	 */
2384	com->iptr = com->ibuf = ibuf;
2385	com->ibufend = ibuf + ibufsize;
2386	com->ierroff = ibufsize;
2387	com->ihighwater = ibuf + 3 * ibufsize / 4;
2388	return (0);
2389}
2390
2391static void
2392comstart(tp)
2393	struct tty	*tp;
2394{
2395	struct com_s	*com;
2396	int		s;
2397	int		unit;
2398
2399	unit = DEV_TO_UNIT(tp->t_dev);
2400	com = com_addr(unit);
2401	if (com == NULL)
2402		return;
2403	s = spltty();
2404	mtx_lock_spin(&sio_lock);
2405	if (tp->t_state & TS_TTSTOP)
2406		com->state &= ~CS_TTGO;
2407	else
2408		com->state |= CS_TTGO;
2409	if (tp->t_state & TS_TBLOCK) {
2410		if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW)
2411			outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS);
2412	} else {
2413		if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater
2414		    && com->state & CS_RTS_IFLOW)
2415			outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
2416	}
2417	mtx_unlock_spin(&sio_lock);
2418	if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) {
2419		ttwwakeup(tp);
2420		splx(s);
2421		return;
2422	}
2423	if (tp->t_outq.c_cc != 0) {
2424		struct lbq	*qp;
2425		struct lbq	*next;
2426
2427		if (!com->obufs[0].l_queued) {
2428			com->obufs[0].l_tail
2429			    = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1,
2430						  sizeof com->obuf1);
2431			com->obufs[0].l_next = NULL;
2432			com->obufs[0].l_queued = TRUE;
2433			mtx_lock_spin(&sio_lock);
2434			if (com->state & CS_BUSY) {
2435				qp = com->obufq.l_next;
2436				while ((next = qp->l_next) != NULL)
2437					qp = next;
2438				qp->l_next = &com->obufs[0];
2439			} else {
2440				com->obufq.l_head = com->obufs[0].l_head;
2441				com->obufq.l_tail = com->obufs[0].l_tail;
2442				com->obufq.l_next = &com->obufs[0];
2443				com->state |= CS_BUSY;
2444			}
2445			mtx_unlock_spin(&sio_lock);
2446		}
2447		if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) {
2448			com->obufs[1].l_tail
2449			    = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2,
2450						  sizeof com->obuf2);
2451			com->obufs[1].l_next = NULL;
2452			com->obufs[1].l_queued = TRUE;
2453			mtx_lock_spin(&sio_lock);
2454			if (com->state & CS_BUSY) {
2455				qp = com->obufq.l_next;
2456				while ((next = qp->l_next) != NULL)
2457					qp = next;
2458				qp->l_next = &com->obufs[1];
2459			} else {
2460				com->obufq.l_head = com->obufs[1].l_head;
2461				com->obufq.l_tail = com->obufs[1].l_tail;
2462				com->obufq.l_next = &com->obufs[1];
2463				com->state |= CS_BUSY;
2464			}
2465			mtx_unlock_spin(&sio_lock);
2466		}
2467		tp->t_state |= TS_BUSY;
2468	}
2469	mtx_lock_spin(&sio_lock);
2470	if (com->state >= (CS_BUSY | CS_TTGO))
2471		siointr1(com);	/* fake interrupt to start output */
2472	mtx_unlock_spin(&sio_lock);
2473	ttwwakeup(tp);
2474	splx(s);
2475}
2476
2477static void
2478comstop(tp, rw)
2479	struct tty	*tp;
2480	int		rw;
2481{
2482	struct com_s	*com;
2483
2484	com = com_addr(DEV_TO_UNIT(tp->t_dev));
2485	if (com == NULL || com->gone)
2486		return;
2487	mtx_lock_spin(&sio_lock);
2488	if (rw & FWRITE) {
2489		if (com->hasfifo)
2490#ifdef COM_ESP
2491		    /* XXX avoid h/w bug. */
2492		    if (!com->esp)
2493#endif
2494			sio_setreg(com, com_fifo,
2495				   FIFO_XMT_RST | com->fifo_image);
2496		com->obufs[0].l_queued = FALSE;
2497		com->obufs[1].l_queued = FALSE;
2498		if (com->state & CS_ODONE)
2499			com_events -= LOTS_OF_EVENTS;
2500		com->state &= ~(CS_ODONE | CS_BUSY);
2501		com->tp->t_state &= ~TS_BUSY;
2502	}
2503	if (rw & FREAD) {
2504		if (com->hasfifo)
2505#ifdef COM_ESP
2506		    /* XXX avoid h/w bug. */
2507		    if (!com->esp)
2508#endif
2509			sio_setreg(com, com_fifo,
2510				   FIFO_RCV_RST | com->fifo_image);
2511		com_events -= (com->iptr - com->ibuf);
2512		com->iptr = com->ibuf;
2513	}
2514	mtx_unlock_spin(&sio_lock);
2515	comstart(tp);
2516}
2517
2518static int
2519commctl(com, bits, how)
2520	struct com_s	*com;
2521	int		bits;
2522	int		how;
2523{
2524	int	mcr;
2525	int	msr;
2526
2527	if (how == DMGET) {
2528		bits = TIOCM_LE;	/* XXX - always enabled while open */
2529		mcr = com->mcr_image;
2530		if (mcr & MCR_DTR)
2531			bits |= TIOCM_DTR;
2532		if (mcr & MCR_RTS)
2533			bits |= TIOCM_RTS;
2534		msr = com->prev_modem_status;
2535		if (msr & MSR_CTS)
2536			bits |= TIOCM_CTS;
2537		if (msr & MSR_DCD)
2538			bits |= TIOCM_CD;
2539		if (msr & MSR_DSR)
2540			bits |= TIOCM_DSR;
2541		/*
2542		 * XXX - MSR_RI is naturally volatile, and we make MSR_TERI
2543		 * more volatile by reading the modem status a lot.  Perhaps
2544		 * we should latch both bits until the status is read here.
2545		 */
2546		if (msr & (MSR_RI | MSR_TERI))
2547			bits |= TIOCM_RI;
2548		return (bits);
2549	}
2550	mcr = 0;
2551	if (bits & TIOCM_DTR)
2552		mcr |= MCR_DTR;
2553	if (bits & TIOCM_RTS)
2554		mcr |= MCR_RTS;
2555	if (com->gone)
2556		return(0);
2557	mtx_lock_spin(&sio_lock);
2558	switch (how) {
2559	case DMSET:
2560		outb(com->modem_ctl_port,
2561		     com->mcr_image = mcr | (com->mcr_image & MCR_IENABLE));
2562		break;
2563	case DMBIS:
2564		outb(com->modem_ctl_port, com->mcr_image |= mcr);
2565		break;
2566	case DMBIC:
2567		outb(com->modem_ctl_port, com->mcr_image &= ~mcr);
2568		break;
2569	}
2570	mtx_unlock_spin(&sio_lock);
2571	return (0);
2572}
2573
2574static void
2575siosettimeout()
2576{
2577	struct com_s	*com;
2578	bool_t		someopen;
2579	int		unit;
2580
2581	/*
2582	 * Set our timeout period to 1 second if no polled devices are open.
2583	 * Otherwise set it to max(1/200, 1/hz).
2584	 * Enable timeouts iff some device is open.
2585	 */
2586	untimeout(comwakeup, (void *)NULL, sio_timeout_handle);
2587	sio_timeout = hz;
2588	someopen = FALSE;
2589	for (unit = 0; unit < sio_numunits; ++unit) {
2590		com = com_addr(unit);
2591		if (com != NULL && com->tp != NULL
2592		    && com->tp->t_state & TS_ISOPEN && !com->gone) {
2593			someopen = TRUE;
2594			if (com->poll || com->poll_output) {
2595				sio_timeout = hz > 200 ? hz / 200 : 1;
2596				break;
2597			}
2598		}
2599	}
2600	if (someopen) {
2601		sio_timeouts_until_log = hz / sio_timeout;
2602		sio_timeout_handle = timeout(comwakeup, (void *)NULL,
2603					     sio_timeout);
2604	} else {
2605		/* Flush error messages, if any. */
2606		sio_timeouts_until_log = 1;
2607		comwakeup((void *)NULL);
2608		untimeout(comwakeup, (void *)NULL, sio_timeout_handle);
2609	}
2610}
2611
2612static void
2613comwakeup(chan)
2614	void	*chan;
2615{
2616	struct com_s	*com;
2617	int		unit;
2618
2619	sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout);
2620
2621	/*
2622	 * Recover from lost output interrupts.
2623	 * Poll any lines that don't use interrupts.
2624	 */
2625	for (unit = 0; unit < sio_numunits; ++unit) {
2626		com = com_addr(unit);
2627		if (com != NULL && !com->gone
2628		    && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) {
2629			mtx_lock_spin(&sio_lock);
2630			siointr1(com);
2631			mtx_unlock_spin(&sio_lock);
2632		}
2633	}
2634
2635	/*
2636	 * Check for and log errors, but not too often.
2637	 */
2638	if (--sio_timeouts_until_log > 0)
2639		return;
2640	sio_timeouts_until_log = hz / sio_timeout;
2641	for (unit = 0; unit < sio_numunits; ++unit) {
2642		int	errnum;
2643
2644		com = com_addr(unit);
2645		if (com == NULL)
2646			continue;
2647		if (com->gone)
2648			continue;
2649		for (errnum = 0; errnum < CE_NTYPES; ++errnum) {
2650			u_int	delta;
2651			u_long	total;
2652
2653			mtx_lock_spin(&sio_lock);
2654			delta = com->delta_error_counts[errnum];
2655			com->delta_error_counts[errnum] = 0;
2656			mtx_unlock_spin(&sio_lock);
2657			if (delta == 0)
2658				continue;
2659			total = com->error_counts[errnum] += delta;
2660			log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n",
2661			    unit, delta, error_desc[errnum],
2662			    delta == 1 ? "" : "s", total);
2663		}
2664	}
2665}
2666
2667static void
2668disc_optim(tp, t, com)
2669	struct tty	*tp;
2670	struct termios	*t;
2671	struct com_s	*com;
2672{
2673	if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON))
2674	    && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK))
2675	    && (!(t->c_iflag & PARMRK)
2676		|| (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK))
2677	    && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN))
2678	    && linesw[tp->t_line].l_rint == ttyinput)
2679		tp->t_state |= TS_CAN_BYPASS_L_RINT;
2680	else
2681		tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
2682	com->hotchar = linesw[tp->t_line].l_hotchar;
2683}
2684
2685/*
2686 * Following are all routines needed for SIO to act as console
2687 */
2688#include <sys/cons.h>
2689
2690struct siocnstate {
2691	u_char	dlbl;
2692	u_char	dlbh;
2693	u_char	ier;
2694	u_char	cfcr;
2695	u_char	mcr;
2696};
2697
2698#ifndef __alpha__
2699static speed_t siocngetspeed __P((Port_t, u_long rclk));
2700#endif
2701static void siocnclose	__P((struct siocnstate *sp, Port_t iobase));
2702static void siocnopen	__P((struct siocnstate *sp, Port_t iobase, int speed));
2703static void siocntxwait	__P((Port_t iobase));
2704
2705#ifdef __alpha__
2706int siocnattach __P((int port, int speed));
2707int siogdbattach __P((int port, int speed));
2708int siogdbgetc __P((void));
2709void siogdbputc __P((int c));
2710#else
2711static cn_probe_t siocnprobe;
2712static cn_init_t siocninit;
2713static cn_term_t siocnterm;
2714#endif
2715static cn_checkc_t siocncheckc;
2716static cn_getc_t siocngetc;
2717static cn_putc_t siocnputc;
2718
2719#ifndef __alpha__
2720CONS_DRIVER(sio, siocnprobe, siocninit, siocnterm, siocngetc, siocncheckc,
2721	    siocnputc, NULL);
2722#endif
2723
2724/* To get the GDB related variables */
2725#if DDB > 0
2726#include <ddb/ddb.h>
2727#endif
2728
2729static void
2730siocntxwait(iobase)
2731	Port_t	iobase;
2732{
2733	int	timo;
2734
2735	/*
2736	 * Wait for any pending transmission to finish.  Required to avoid
2737	 * the UART lockup bug when the speed is changed, and for normal
2738	 * transmits.
2739	 */
2740	timo = 100000;
2741	while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY))
2742	       != (LSR_TSRE | LSR_TXRDY) && --timo != 0)
2743		;
2744}
2745
2746#ifndef __alpha__
2747
2748/*
2749 * Read the serial port specified and try to figure out what speed
2750 * it's currently running at.  We're assuming the serial port has
2751 * been initialized and is basicly idle.  This routine is only intended
2752 * to be run at system startup.
2753 *
2754 * If the value read from the serial port doesn't make sense, return 0.
2755 */
2756
2757static speed_t
2758siocngetspeed(iobase, rclk)
2759	Port_t	iobase;
2760	u_long	rclk;
2761{
2762	u_int	divisor;
2763	u_char	dlbh;
2764	u_char	dlbl;
2765	u_char  cfcr;
2766
2767	cfcr = inb(iobase + com_cfcr);
2768	outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
2769
2770	dlbl = inb(iobase + com_dlbl);
2771	dlbh = inb(iobase + com_dlbh);
2772
2773	outb(iobase + com_cfcr, cfcr);
2774
2775	divisor = dlbh << 8 | dlbl;
2776
2777	/* XXX there should be more sanity checking. */
2778	if (divisor == 0)
2779		return (CONSPEED);
2780	return (rclk / (16UL * divisor));
2781}
2782
2783#endif
2784
2785static void
2786siocnopen(sp, iobase, speed)
2787	struct siocnstate	*sp;
2788	Port_t			iobase;
2789	int			speed;
2790{
2791	u_int	divisor;
2792	u_char	dlbh;
2793	u_char	dlbl;
2794
2795	/*
2796	 * Save all the device control registers except the fifo register
2797	 * and set our default ones (cs8 -parenb speed=comdefaultrate).
2798	 * We can't save the fifo register since it is read-only.
2799	 */
2800	sp->ier = inb(iobase + com_ier);
2801	outb(iobase + com_ier, 0);	/* spltty() doesn't stop siointr() */
2802	siocntxwait(iobase);
2803	sp->cfcr = inb(iobase + com_cfcr);
2804	outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
2805	sp->dlbl = inb(iobase + com_dlbl);
2806	sp->dlbh = inb(iobase + com_dlbh);
2807	/*
2808	 * Only set the divisor registers if they would change, since on
2809	 * some 16550 incompatibles (Startech), setting them clears the
2810	 * data input register.  This also reduces the effects of the
2811	 * UMC8669F bug.
2812	 */
2813	divisor = siodivisor(comdefaultrclk, speed);
2814	dlbl = divisor & 0xFF;
2815	if (sp->dlbl != dlbl)
2816		outb(iobase + com_dlbl, dlbl);
2817	dlbh = divisor >> 8;
2818	if (sp->dlbh != dlbh)
2819		outb(iobase + com_dlbh, dlbh);
2820	outb(iobase + com_cfcr, CFCR_8BITS);
2821	sp->mcr = inb(iobase + com_mcr);
2822	/*
2823	 * We don't want interrupts, but must be careful not to "disable"
2824	 * them by clearing the MCR_IENABLE bit, since that might cause
2825	 * an interrupt by floating the IRQ line.
2826	 */
2827	outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS);
2828}
2829
2830static void
2831siocnclose(sp, iobase)
2832	struct siocnstate	*sp;
2833	Port_t			iobase;
2834{
2835	/*
2836	 * Restore the device control registers.
2837	 */
2838	siocntxwait(iobase);
2839	outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
2840	if (sp->dlbl != inb(iobase + com_dlbl))
2841		outb(iobase + com_dlbl, sp->dlbl);
2842	if (sp->dlbh != inb(iobase + com_dlbh))
2843		outb(iobase + com_dlbh, sp->dlbh);
2844	outb(iobase + com_cfcr, sp->cfcr);
2845	/*
2846	 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them.
2847	 */
2848	outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS);
2849	outb(iobase + com_ier, sp->ier);
2850}
2851
2852#ifndef __alpha__
2853
2854static void
2855siocnprobe(cp)
2856	struct consdev	*cp;
2857{
2858	speed_t			boot_speed;
2859	u_char			cfcr;
2860	u_int			divisor;
2861	int			s, unit;
2862	struct siocnstate	sp;
2863
2864	/*
2865	 * Find our first enabled console, if any.  If it is a high-level
2866	 * console device, then initialize it and return successfully.
2867	 * If it is a low-level console device, then initialize it and
2868	 * return unsuccessfully.  It must be initialized in both cases
2869	 * for early use by console drivers and debuggers.  Initializing
2870	 * the hardware is not necessary in all cases, since the i/o
2871	 * routines initialize it on the fly, but it is necessary if
2872	 * input might arrive while the hardware is switched back to an
2873	 * uninitialized state.  We can't handle multiple console devices
2874	 * yet because our low-level routines don't take a device arg.
2875	 * We trust the user to set the console flags properly so that we
2876	 * don't need to probe.
2877	 */
2878	cp->cn_pri = CN_DEAD;
2879
2880	for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */
2881		int flags;
2882		int disabled;
2883		if (resource_int_value("sio", unit, "disabled", &disabled) == 0) {
2884			if (disabled)
2885				continue;
2886		}
2887		if (resource_int_value("sio", unit, "flags", &flags))
2888			continue;
2889		if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) {
2890			int port;
2891			Port_t iobase;
2892
2893			if (resource_int_value("sio", unit, "port", &port))
2894				continue;
2895			iobase = port;
2896			s = spltty();
2897			if (boothowto & RB_SERIAL) {
2898				boot_speed =
2899				    siocngetspeed(iobase, comdefaultrclk);
2900				if (boot_speed)
2901					comdefaultrate = boot_speed;
2902			}
2903
2904			/*
2905			 * Initialize the divisor latch.  We can't rely on
2906			 * siocnopen() to do this the first time, since it
2907			 * avoids writing to the latch if the latch appears
2908			 * to have the correct value.  Also, if we didn't
2909			 * just read the speed from the hardware, then we
2910			 * need to set the speed in hardware so that
2911			 * switching it later is null.
2912			 */
2913			cfcr = inb(iobase + com_cfcr);
2914			outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
2915			divisor = siodivisor(comdefaultrclk, comdefaultrate);
2916			outb(iobase + com_dlbl, divisor & 0xff);
2917			outb(iobase + com_dlbh, divisor >> 8);
2918			outb(iobase + com_cfcr, cfcr);
2919
2920			siocnopen(&sp, iobase, comdefaultrate);
2921
2922			splx(s);
2923			if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) {
2924				cp->cn_dev = makedev(CDEV_MAJOR, unit);
2925				cp->cn_pri = COM_FORCECONSOLE(flags)
2926					     || boothowto & RB_SERIAL
2927					     ? CN_REMOTE : CN_NORMAL;
2928				siocniobase = iobase;
2929				siocnunit = unit;
2930			}
2931			if (COM_DEBUGGER(flags)) {
2932				printf("sio%d: gdb debugging port\n", unit);
2933				siogdbiobase = iobase;
2934				siogdbunit = unit;
2935#if DDB > 0
2936				gdbdev = makedev(CDEV_MAJOR, unit);
2937				gdb_getc = siocngetc;
2938				gdb_putc = siocnputc;
2939#endif
2940			}
2941		}
2942	}
2943#ifdef	__i386__
2944#if DDB > 0
2945	/*
2946	 * XXX Ugly Compatability.
2947	 * If no gdb port has been specified, set it to be the console
2948	 * as some configuration files don't specify the gdb port.
2949	 */
2950	if (gdbdev == NODEV && (boothowto & RB_GDB)) {
2951		printf("Warning: no GDB port specified. Defaulting to sio%d.\n",
2952			siocnunit);
2953		printf("Set flag 0x80 on desired GDB port in your\n");
2954		printf("configuration file (currently sio only).\n");
2955		siogdbiobase = siocniobase;
2956		siogdbunit = siocnunit;
2957		gdbdev = makedev(CDEV_MAJOR, siocnunit);
2958		gdb_getc = siocngetc;
2959		gdb_putc = siocnputc;
2960	}
2961#endif
2962#endif
2963}
2964
2965static void
2966siocninit(cp)
2967	struct consdev	*cp;
2968{
2969	comconsole = DEV_TO_UNIT(cp->cn_dev);
2970}
2971
2972static void
2973siocnterm(cp)
2974	struct consdev	*cp;
2975{
2976	comconsole = -1;
2977}
2978
2979#endif
2980
2981#ifdef __alpha__
2982
2983CONS_DRIVER(sio, NULL, NULL, NULL, siocngetc, siocncheckc, siocnputc, NULL);
2984
2985int
2986siocnattach(port, speed)
2987	int port;
2988	int speed;
2989{
2990	int			s;
2991	u_char			cfcr;
2992	u_int			divisor;
2993	struct siocnstate	sp;
2994
2995	siocniobase = port;
2996	comdefaultrate = speed;
2997	sio_consdev.cn_pri = CN_NORMAL;
2998	sio_consdev.cn_dev = makedev(CDEV_MAJOR, 0);
2999
3000	s = spltty();
3001
3002	/*
3003	 * Initialize the divisor latch.  We can't rely on
3004	 * siocnopen() to do this the first time, since it
3005	 * avoids writing to the latch if the latch appears
3006	 * to have the correct value.  Also, if we didn't
3007	 * just read the speed from the hardware, then we
3008	 * need to set the speed in hardware so that
3009	 * switching it later is null.
3010	 */
3011	cfcr = inb(siocniobase + com_cfcr);
3012	outb(siocniobase + com_cfcr, CFCR_DLAB | cfcr);
3013	divisor = siodivisor(comdefaultrclk, comdefaultrate);
3014	outb(siocniobase + com_dlbl, divisor & 0xff);
3015	outb(siocniobase + com_dlbh, divisor >> 8);
3016	outb(siocniobase + com_cfcr, cfcr);
3017
3018	siocnopen(&sp, siocniobase, comdefaultrate);
3019	splx(s);
3020
3021	cnadd(&sio_consdev);
3022	return (0);
3023}
3024
3025int
3026siogdbattach(port, speed)
3027	int port;
3028	int speed;
3029{
3030	int			s;
3031	u_char			cfcr;
3032	u_int			divisor;
3033	struct siocnstate	sp;
3034	int			unit = 1;	/* XXX !!! */
3035
3036	siogdbiobase = port;
3037	gdbdefaultrate = speed;
3038
3039	printf("sio%d: gdb debugging port\n", unit);
3040	siogdbunit = unit;
3041#if DDB > 0
3042	gdbdev = makedev(CDEV_MAJOR, unit);
3043	gdb_getc = siocngetc;
3044	gdb_putc = siocnputc;
3045#endif
3046
3047	s = spltty();
3048
3049	/*
3050	 * Initialize the divisor latch.  We can't rely on
3051	 * siocnopen() to do this the first time, since it
3052	 * avoids writing to the latch if the latch appears
3053	 * to have the correct value.  Also, if we didn't
3054	 * just read the speed from the hardware, then we
3055	 * need to set the speed in hardware so that
3056	 * switching it later is null.
3057	 */
3058	cfcr = inb(siogdbiobase + com_cfcr);
3059	outb(siogdbiobase + com_cfcr, CFCR_DLAB | cfcr);
3060	divisor = siodivisor(comdefaultrclk, gdbdefaultrate);
3061	outb(siogdbiobase + com_dlbl, divisor & 0xff);
3062	outb(siogdbiobase + com_dlbh, divisor >> 8);
3063	outb(siogdbiobase + com_cfcr, cfcr);
3064
3065	siocnopen(&sp, siogdbiobase, gdbdefaultrate);
3066	splx(s);
3067
3068	return (0);
3069}
3070
3071#endif
3072
3073static int
3074siocncheckc(dev)
3075	dev_t	dev;
3076{
3077	int	c;
3078	Port_t	iobase;
3079	int	s;
3080	struct siocnstate	sp;
3081
3082	if (minor(dev) == siogdbunit)
3083		iobase = siogdbiobase;
3084	else
3085		iobase = siocniobase;
3086	s = spltty();
3087	siocnopen(&sp, iobase, comdefaultrate);
3088	if (inb(iobase + com_lsr) & LSR_RXRDY)
3089		c = inb(iobase + com_data);
3090	else
3091		c = -1;
3092	siocnclose(&sp, iobase);
3093	splx(s);
3094	return (c);
3095}
3096
3097
3098int
3099siocngetc(dev)
3100	dev_t	dev;
3101{
3102	int	c;
3103	Port_t	iobase;
3104	int	s;
3105	struct siocnstate	sp;
3106
3107	if (minor(dev) == siogdbunit)
3108		iobase = siogdbiobase;
3109	else
3110		iobase = siocniobase;
3111	s = spltty();
3112	siocnopen(&sp, iobase, comdefaultrate);
3113	while (!(inb(iobase + com_lsr) & LSR_RXRDY))
3114		;
3115	c = inb(iobase + com_data);
3116	siocnclose(&sp, iobase);
3117	splx(s);
3118	return (c);
3119}
3120
3121void
3122siocnputc(dev, c)
3123	dev_t	dev;
3124	int	c;
3125{
3126	int	need_unlock;
3127	int	s;
3128	struct siocnstate	sp;
3129	Port_t	iobase;
3130
3131	if (minor(dev) == siogdbunit)
3132		iobase = siogdbiobase;
3133	else
3134		iobase = siocniobase;
3135	s = spltty();
3136	need_unlock = 0;
3137	if (sio_inited == 2 && !mtx_owned(&sio_lock)) {
3138		mtx_lock_spin(&sio_lock);
3139		need_unlock = 1;
3140	}
3141	siocnopen(&sp, iobase, comdefaultrate);
3142	siocntxwait(iobase);
3143	outb(iobase + com_data, c);
3144	siocnclose(&sp, iobase);
3145	if (need_unlock)
3146		mtx_unlock_spin(&sio_lock);
3147	splx(s);
3148}
3149
3150#ifdef __alpha__
3151int
3152siogdbgetc()
3153{
3154	int	c;
3155	Port_t	iobase;
3156	int	s;
3157	struct siocnstate	sp;
3158
3159	iobase = siogdbiobase;
3160	s = spltty();
3161	siocnopen(&sp, iobase, gdbdefaultrate);
3162	while (!(inb(iobase + com_lsr) & LSR_RXRDY))
3163		;
3164	c = inb(iobase + com_data);
3165	siocnclose(&sp, iobase);
3166	splx(s);
3167	return (c);
3168}
3169
3170void
3171siogdbputc(c)
3172	int	c;
3173{
3174	int	s;
3175	struct siocnstate	sp;
3176
3177	s = spltty();
3178	siocnopen(&sp, siogdbiobase, gdbdefaultrate);
3179	siocntxwait(siogdbiobase);
3180	outb(siogdbiobase + com_data, c);
3181	siocnclose(&sp, siogdbiobase);
3182	splx(s);
3183}
3184#endif
3185