sio.c revision 54920
1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by the University of 16 * California, Berkeley and its contributors. 17 * 4. Neither the name of the University nor the names of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/dev/sio/sio.c 54920 1999-12-20 20:31:23Z peter $ 34 * from: @(#)com.c 7.5 (Berkeley) 5/16/91 35 * from: i386/isa sio.c,v 1.234 36 */ 37 38#include "opt_comconsole.h" 39#include "opt_compat.h" 40#include "opt_ddb.h" 41#include "opt_sio.h" 42#include "card.h" 43#include "sio.h" 44 45/* 46 * Serial driver, based on 386BSD-0.1 com driver. 47 * Mostly rewritten to use pseudo-DMA. 48 * Works for National Semiconductor NS8250-NS16550AF UARTs. 49 * COM driver, based on HP dca driver. 50 * 51 * Changes for PC-Card integration: 52 * - Added PC-Card driver table and handlers 53 */ 54#include <sys/param.h> 55#include <sys/systm.h> 56#include <sys/reboot.h> 57#include <sys/malloc.h> 58#include <sys/tty.h> 59#include <sys/proc.h> 60#include <sys/module.h> 61#include <sys/conf.h> 62#include <sys/dkstat.h> 63#include <sys/fcntl.h> 64#include <sys/interrupt.h> 65#include <sys/kernel.h> 66#include <sys/syslog.h> 67#include <sys/sysctl.h> 68#include <sys/bus.h> 69#include <machine/bus.h> 70#include <sys/rman.h> 71#include <sys/timepps.h> 72 73#include <isa/isareg.h> 74#include <isa/isavar.h> 75#include <machine/lock.h> 76 77#include <machine/clock.h> 78#include <machine/ipl.h> 79#ifndef SMP 80#include <machine/lock.h> 81#endif 82#include <machine/resource.h> 83 84#include <isa/sioreg.h> 85 86#ifdef COM_ESP 87#include <isa/ic/esp.h> 88#endif 89#include <isa/ic/ns16550.h> 90 91#ifndef __i386__ 92#define disable_intr() 93#define enable_intr() 94#endif 95 96#ifdef SMP 97#define disable_intr() COM_DISABLE_INTR() 98#define enable_intr() COM_ENABLE_INTR() 99#endif /* SMP */ 100 101#define LOTS_OF_EVENTS 64 /* helps separate urgent events from input */ 102 103#define CALLOUT_MASK 0x80 104#define CONTROL_MASK 0x60 105#define CONTROL_INIT_STATE 0x20 106#define CONTROL_LOCK_STATE 0x40 107#define DEV_TO_UNIT(dev) (MINOR_TO_UNIT(minor(dev))) 108#define MINOR_MAGIC_MASK (CALLOUT_MASK | CONTROL_MASK) 109#define MINOR_TO_UNIT(mynor) ((mynor) & ~MINOR_MAGIC_MASK) 110 111#ifdef COM_MULTIPORT 112/* checks in flags for multiport and which is multiport "master chip" 113 * for a given card 114 */ 115#define COM_ISMULTIPORT(flags) ((flags) & 0x01) 116#define COM_MPMASTER(flags) (((flags) >> 8) & 0x0ff) 117#define COM_NOTAST4(flags) ((flags) & 0x04) 118#endif /* COM_MULTIPORT */ 119 120#define COM_CONSOLE(flags) ((flags) & 0x10) 121#define COM_FORCECONSOLE(flags) ((flags) & 0x20) 122#define COM_LLCONSOLE(flags) ((flags) & 0x40) 123#define COM_DEBUGGER(flags) ((flags) & 0x80) 124#define COM_LOSESOUTINTS(flags) ((flags) & 0x08) 125#define COM_NOFIFO(flags) ((flags) & 0x02) 126#define COM_ST16650A(flags) ((flags) & 0x20000) 127#define COM_C_NOPROBE (0x40000) 128#define COM_NOPROBE(flags) ((flags) & COM_C_NOPROBE) 129#define COM_C_IIR_TXRDYBUG (0x80000) 130#define COM_IIR_TXRDYBUG(flags) ((flags) & COM_C_IIR_TXRDYBUG) 131#define COM_FIFOSIZE(flags) (((flags) & 0xff000000) >> 24) 132 133#define com_scr 7 /* scratch register for 16450-16550 (R/W) */ 134 135/* 136 * com state bits. 137 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher 138 * than the other bits so that they can be tested as a group without masking 139 * off the low bits. 140 * 141 * The following com and tty flags correspond closely: 142 * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and 143 * comstop()) 144 * CS_TTGO = ~TS_TTSTOP (maintained by comparam() and comstart()) 145 * CS_CTS_OFLOW = CCTS_OFLOW (maintained by comparam()) 146 * CS_RTS_IFLOW = CRTS_IFLOW (maintained by comparam()) 147 * TS_FLUSH is not used. 148 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON. 149 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state). 150 */ 151#define CS_BUSY 0x80 /* output in progress */ 152#define CS_TTGO 0x40 /* output not stopped by XOFF */ 153#define CS_ODEVREADY 0x20 /* external device h/w ready (CTS) */ 154#define CS_CHECKMSR 1 /* check of MSR scheduled */ 155#define CS_CTS_OFLOW 2 /* use CTS output flow control */ 156#define CS_DTR_OFF 0x10 /* DTR held off */ 157#define CS_ODONE 4 /* output completed */ 158#define CS_RTS_IFLOW 8 /* use RTS input flow control */ 159#define CSE_BUSYCHECK 1 /* siobusycheck() scheduled */ 160 161static char const * const error_desc[] = { 162#define CE_OVERRUN 0 163 "silo overflow", 164#define CE_INTERRUPT_BUF_OVERFLOW 1 165 "interrupt-level buffer overflow", 166#define CE_TTY_BUF_OVERFLOW 2 167 "tty-level buffer overflow", 168}; 169 170#define CE_NTYPES 3 171#define CE_RECORD(com, errnum) (++(com)->delta_error_counts[errnum]) 172 173/* types. XXX - should be elsewhere */ 174typedef u_int Port_t; /* hardware port */ 175typedef u_char bool_t; /* boolean */ 176 177/* queue of linear buffers */ 178struct lbq { 179 u_char *l_head; /* next char to process */ 180 u_char *l_tail; /* one past the last char to process */ 181 struct lbq *l_next; /* next in queue */ 182 bool_t l_queued; /* nonzero if queued */ 183}; 184 185/* com device structure */ 186struct com_s { 187 u_int flags; /* Copy isa device flags */ 188 u_char state; /* miscellaneous flag bits */ 189 bool_t active_out; /* nonzero if the callout device is open */ 190 u_char cfcr_image; /* copy of value written to CFCR */ 191#ifdef COM_ESP 192 bool_t esp; /* is this unit a hayes esp board? */ 193#endif 194 u_char extra_state; /* more flag bits, separate for order trick */ 195 u_char fifo_image; /* copy of value written to FIFO */ 196 bool_t hasfifo; /* nonzero for 16550 UARTs */ 197 bool_t st16650a; /* Is a Startech 16650A or RTS/CTS compat */ 198 bool_t loses_outints; /* nonzero if device loses output interrupts */ 199 u_char mcr_image; /* copy of value written to MCR */ 200#ifdef COM_MULTIPORT 201 bool_t multiport; /* is this unit part of a multiport device? */ 202#endif /* COM_MULTIPORT */ 203 bool_t no_irq; /* nonzero if irq is not attached */ 204 bool_t gone; /* hardware disappeared */ 205 bool_t poll; /* nonzero if polling is required */ 206 bool_t poll_output; /* nonzero if polling for output is required */ 207 int unit; /* unit number */ 208 int dtr_wait; /* time to hold DTR down on close (* 1/hz) */ 209 u_int tx_fifo_size; 210 u_int wopeners; /* # processes waiting for DCD in open() */ 211 212 /* 213 * The high level of the driver never reads status registers directly 214 * because there would be too many side effects to handle conveniently. 215 * Instead, it reads copies of the registers stored here by the 216 * interrupt handler. 217 */ 218 u_char last_modem_status; /* last MSR read by intr handler */ 219 u_char prev_modem_status; /* last MSR handled by high level */ 220 221 u_char hotchar; /* ldisc-specific char to be handled ASAP */ 222 u_char *ibuf; /* start of input buffer */ 223 u_char *ibufend; /* end of input buffer */ 224 u_char *ibufold; /* old input buffer, to be freed */ 225 u_char *ihighwater; /* threshold in input buffer */ 226 u_char *iptr; /* next free spot in input buffer */ 227 int ibufsize; /* size of ibuf (not include error bytes) */ 228 int ierroff; /* offset of error bytes in ibuf */ 229 230 struct lbq obufq; /* head of queue of output buffers */ 231 struct lbq obufs[2]; /* output buffers */ 232 233 Port_t data_port; /* i/o ports */ 234#ifdef COM_ESP 235 Port_t esp_port; 236#endif 237 Port_t int_id_port; 238 Port_t iobase; 239 Port_t modem_ctl_port; 240 Port_t line_status_port; 241 Port_t modem_status_port; 242 Port_t intr_ctl_port; /* Ports of IIR register */ 243 244 struct tty *tp; /* cross reference */ 245 246 /* Initial state. */ 247 struct termios it_in; /* should be in struct tty */ 248 struct termios it_out; 249 250 /* Lock state. */ 251 struct termios lt_in; /* should be in struct tty */ 252 struct termios lt_out; 253 254 bool_t do_timestamp; 255 bool_t do_dcd_timestamp; 256 struct timeval timestamp; 257 struct timeval dcd_timestamp; 258 struct pps_state pps; 259 260 u_long bytes_in; /* statistics */ 261 u_long bytes_out; 262 u_int delta_error_counts[CE_NTYPES]; 263 u_long error_counts[CE_NTYPES]; 264 265 struct resource *irqres; 266 struct resource *ioportres; 267 void *cookie; 268 269 /* 270 * Data area for output buffers. Someday we should build the output 271 * buffer queue without copying data. 272 */ 273 u_char obuf1[256]; 274 u_char obuf2[256]; 275}; 276 277#ifdef COM_ESP 278static int espattach __P((struct com_s *com, Port_t esp_port)); 279#endif 280static int sioattach __P((device_t dev)); 281static int sio_isa_attach __P((device_t dev)); 282 283static timeout_t siobusycheck; 284static timeout_t siodtrwakeup; 285static void comhardclose __P((struct com_s *com)); 286static void sioinput __P((struct com_s *com)); 287static void siointr1 __P((struct com_s *com)); 288static void siointr __P((void *arg)); 289static int commctl __P((struct com_s *com, int bits, int how)); 290static int comparam __P((struct tty *tp, struct termios *t)); 291static swihand_t siopoll; 292static int sioprobe __P((device_t dev)); 293static int sio_isa_probe __P((device_t dev)); 294static void siosettimeout __P((void)); 295static int siosetwater __P((struct com_s *com, speed_t speed)); 296static void comstart __P((struct tty *tp)); 297static void comstop __P((struct tty *tp, int rw)); 298static timeout_t comwakeup; 299static void disc_optim __P((struct tty *tp, struct termios *t, 300 struct com_s *com)); 301 302#if NCARD > 0 303static int sio_pccard_attach __P((device_t dev)); 304static int sio_pccard_detach __P((device_t dev)); 305static int sio_pccard_probe __P((device_t dev)); 306#endif /* NCARD > 0 */ 307 308static char driver_name[] = "sio"; 309 310/* table and macro for fast conversion from a unit number to its com struct */ 311static devclass_t sio_devclass; 312#define com_addr(unit) ((struct com_s *) \ 313 devclass_get_softc(sio_devclass, unit)) 314 315static device_method_t sio_isa_methods[] = { 316 /* Device interface */ 317 DEVMETHOD(device_probe, sio_isa_probe), 318 DEVMETHOD(device_attach, sio_isa_attach), 319 320 { 0, 0 } 321}; 322 323static driver_t sio_isa_driver = { 324 driver_name, 325 sio_isa_methods, 326 sizeof(struct com_s), 327}; 328 329#if NCARD > 0 330static device_method_t sio_pccard_methods[] = { 331 /* Device interface */ 332 DEVMETHOD(device_probe, sio_pccard_probe), 333 DEVMETHOD(device_attach, sio_pccard_attach), 334 DEVMETHOD(device_detach, sio_pccard_detach), 335 336 { 0, 0 } 337}; 338 339static driver_t sio_pccard_driver = { 340 driver_name, 341 sio_pccard_methods, 342 sizeof(struct com_s), 343}; 344#endif (NCARD > 0) 345 346static d_open_t sioopen; 347static d_close_t sioclose; 348static d_read_t sioread; 349static d_write_t siowrite; 350static d_ioctl_t sioioctl; 351 352#define CDEV_MAJOR 28 353static struct cdevsw sio_cdevsw = { 354 /* open */ sioopen, 355 /* close */ sioclose, 356 /* read */ sioread, 357 /* write */ siowrite, 358 /* ioctl */ sioioctl, 359 /* poll */ ttypoll, 360 /* mmap */ nommap, 361 /* strategy */ nostrategy, 362 /* name */ driver_name, 363 /* maj */ CDEV_MAJOR, 364 /* dump */ nodump, 365 /* psize */ nopsize, 366 /* flags */ D_TTY, 367 /* bmaj */ -1 368}; 369 370int comconsole = -1; 371static volatile speed_t comdefaultrate = CONSPEED; 372#ifdef __alpha__ 373static volatile speed_t gdbdefaultrate = CONSPEED; 374#endif 375static u_int com_events; /* input chars + weighted output completions */ 376static Port_t siocniobase; 377static int siocnunit; 378static Port_t siogdbiobase; 379static int siogdbunit = -1; 380static bool_t sio_registered; 381static int sio_timeout; 382static int sio_timeouts_until_log; 383static struct callout_handle sio_timeout_handle 384 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle); 385static int sio_numunits; 386 387static struct speedtab comspeedtab[] = { 388 { 0, 0 }, 389 { 50, COMBRD(50) }, 390 { 75, COMBRD(75) }, 391 { 110, COMBRD(110) }, 392 { 134, COMBRD(134) }, 393 { 150, COMBRD(150) }, 394 { 200, COMBRD(200) }, 395 { 300, COMBRD(300) }, 396 { 600, COMBRD(600) }, 397 { 1200, COMBRD(1200) }, 398 { 1800, COMBRD(1800) }, 399 { 2400, COMBRD(2400) }, 400 { 4800, COMBRD(4800) }, 401 { 9600, COMBRD(9600) }, 402 { 19200, COMBRD(19200) }, 403 { 38400, COMBRD(38400) }, 404 { 57600, COMBRD(57600) }, 405 { 115200, COMBRD(115200) }, 406 { -1, -1 } 407}; 408 409#ifdef COM_ESP 410/* XXX configure this properly. */ 411static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, }; 412static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 }; 413#endif 414 415/* 416 * handle sysctl read/write requests for console speed 417 * 418 * In addition to setting comdefaultrate for I/O through /dev/console, 419 * also set the initial and lock values for the /dev/ttyXX device 420 * if there is one associated with the console. Finally, if the /dev/tty 421 * device has already been open, change the speed on the open running port 422 * itself. 423 */ 424 425static int 426sysctl_machdep_comdefaultrate SYSCTL_HANDLER_ARGS 427{ 428 int error, s; 429 speed_t newspeed; 430 struct com_s *com; 431 struct tty *tp; 432 433 newspeed = comdefaultrate; 434 435 error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req); 436 if (error || !req->newptr) 437 return (error); 438 439 comdefaultrate = newspeed; 440 441 if (comconsole < 0) /* serial console not selected? */ 442 return (0); 443 444 com = com_addr(comconsole); 445 if (!com) 446 return (ENXIO); 447 448 /* 449 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX 450 * (note, the lock rates really are boolean -- if non-zero, disallow 451 * speed changes) 452 */ 453 com->it_in.c_ispeed = com->it_in.c_ospeed = 454 com->lt_in.c_ispeed = com->lt_in.c_ospeed = 455 com->it_out.c_ispeed = com->it_out.c_ospeed = 456 com->lt_out.c_ispeed = com->lt_out.c_ospeed = comdefaultrate; 457 458 /* 459 * if we're open, change the running rate too 460 */ 461 tp = com->tp; 462 if (tp && (tp->t_state & TS_ISOPEN)) { 463 tp->t_termios.c_ispeed = 464 tp->t_termios.c_ospeed = comdefaultrate; 465 s = spltty(); 466 error = comparam(tp, &tp->t_termios); 467 splx(s); 468 } 469 return error; 470} 471 472SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW, 473 0, 0, sysctl_machdep_comdefaultrate, "I", ""); 474 475#define SET_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) | (bit)) 476#define CLR_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) & ~(bit)) 477 478#if NCARD > 0 479static int 480sio_pccard_probe(dev) 481 device_t dev; 482{ 483 /* Do not probe IRQ - pccard doesn't turn on the interrupt line */ 484 /* until bus_setup_intr */ 485 SET_FLAG(dev, COM_C_NOPROBE); 486 487 return (sioprobe(dev)); 488} 489 490static int 491sio_pccard_attach(dev) 492 device_t dev; 493{ 494 return (sioattach(dev)); 495} 496 497/* 498 * sio_detach - unload the driver and clear the table. 499 * XXX TODO: 500 * This is usually called when the card is ejected, but 501 * can be caused by a modunload of a controller driver. 502 * The idea is to reset the driver's view of the device 503 * and ensure that any driver entry points such as 504 * read and write do not hang. 505 */ 506static int 507sio_pccard_detach(dev) 508 device_t dev; 509{ 510 struct com_s *com; 511 512 com = (struct com_s *) device_get_softc(dev); 513 if (!com) { 514 device_printf(dev, "NULL com in siounload\n"); 515 return (0); 516 } 517 if (!com->iobase) { 518 device_printf(dev, "already unloaded!\n"); 519 return (0); 520 } 521 com->gone = 1; 522 if (com->irqres) { 523 bus_teardown_intr(dev, com->irqres, com->cookie); 524 bus_release_resource(dev, SYS_RES_IRQ, 0, com->irqres); 525 } 526 if (com->ioportres) 527 bus_release_resource(dev, SYS_RES_IOPORT, 0, com->ioportres); 528 if (com->tp && (com->tp->t_state & TS_ISOPEN)) { 529 device_printf(dev, "unload\n"); 530 com->tp->t_gen++; 531 ttyclose(com->tp); 532 ttwakeup(com->tp); 533 ttwwakeup(com->tp); 534 device_printf(dev, "Was busy, so crash likely\n"); 535 } else { 536 if (com->ibuf != NULL) 537 free(com->ibuf, M_DEVBUF); 538 device_printf(dev, "unload, gone\n"); 539 } 540 return (0); 541} 542#endif /* NCARD > 0 */ 543 544 545static struct isa_pnp_id sio_ids[] = { 546 {0x0005d041, "Standard PC COM port"}, /* PNP0500 */ 547 {0x0105d041, "16550A-compatible COM port"}, /* PNP0501 */ 548 {0x0205d041, "Multiport serial device (non-intelligent 16550)"}, /* PNP0502 */ 549 {0x1005d041, "Generic IRDA-compatible device"}, /* PNP0510 */ 550 {0x1105d041, "Generic IRDA-compatible device"}, /* PNP0511 */ 551 {0x01017256, NULL}, /* USR0101 */ 552 {0x30207256, NULL}, /* USR2030 */ 553 {0x31307256, NULL}, /* USR3031 */ 554 {0x7420b04e, NULL}, /* SUP2070 */ 555 {0x8020b04e, NULL}, /* SUP2080 */ 556 {0x8024b04e, NULL}, /* SUP2480 */ 557 {0x6045f435, NULL}, /* MOT4560 */ 558 {0} 559}; 560 561static int 562sio_isa_probe(dev) 563 device_t dev; 564{ 565 /* Check isapnp ids */ 566 if (ISA_PNP_PROBE(device_get_parent(dev), dev, sio_ids) == ENXIO) 567 return (ENXIO); 568 return (sioprobe(dev)); 569} 570 571static int 572sioprobe(dev) 573 device_t dev; 574{ 575#if 0 576 static bool_t already_init; 577 device_t xdev; 578#endif 579 bool_t failures[10]; 580 int fn; 581 device_t idev; 582 Port_t iobase; 583 intrmask_t irqmap[4]; 584 intrmask_t irqs; 585 u_char mcr_image; 586 int result; 587 u_long xirq; 588 u_int flags = device_get_flags(dev); 589 int rid; 590 struct resource *port; 591 592 rid = 0; 593 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 594 0, ~0, IO_COMSIZE, RF_ACTIVE); 595 if (!port) 596 return ENXIO; 597 598#if 0 599 /* 600 * XXX this is broken - when we are first called, there are no 601 * previously configured IO ports. We could hard code 602 * 0x3f8, 0x2f8, 0x3e8, 0x2e8 etc but that's probably worse. 603 * This code has been doing nothing since the conversion since 604 * "count" is zero the first time around. 605 */ 606 if (!already_init) { 607 /* 608 * Turn off MCR_IENABLE for all likely serial ports. An unused 609 * port with its MCR_IENABLE gate open will inhibit interrupts 610 * from any used port that shares the interrupt vector. 611 * XXX the gate enable is elsewhere for some multiports. 612 */ 613 device_t *devs; 614 int count, i, xioport; 615 616 devclass_get_devices(sio_devclass, &devs, &count); 617 for (i = 0; i < count; i++) { 618 xdev = devs[i]; 619 if (device_is_enabled(xdev) && 620 bus_get_resource(xdev, SYS_RES_IOPORT, 0, &xioport, 621 NULL) == 0) 622 outb(xioport + com_mcr, 0); 623 } 624 free(devs, M_TEMP); 625 already_init = TRUE; 626 } 627#endif 628 629 if (COM_LLCONSOLE(flags)) { 630 printf("sio%d: reserved for low-level i/o\n", 631 device_get_unit(dev)); 632 return (ENXIO); 633 } 634 635 /* 636 * If the device is on a multiport card and has an AST/4 637 * compatible interrupt control register, initialize this 638 * register and prepare to leave MCR_IENABLE clear in the mcr. 639 * Otherwise, prepare to set MCR_IENABLE in the mcr. 640 * Point idev to the device struct giving the correct id_irq. 641 * This is the struct for the master device if there is one. 642 */ 643 idev = dev; 644 mcr_image = MCR_IENABLE; 645#ifdef COM_MULTIPORT 646 if (COM_ISMULTIPORT(flags) && !COM_NOTAST4(flags)) { 647 Port_t xiobase; 648 u_long io; 649 650 idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags)); 651 if (idev == NULL) { 652 printf("sio%d: master device %d not configured\n", 653 device_get_unit(dev), COM_MPMASTER(flags)); 654 idev = dev; 655 } 656 if (bus_get_resource(idev, SYS_RES_IOPORT, 0, &io, NULL) == 0) { 657 xiobase = io; 658 if (bus_get_resource(idev, SYS_RES_IRQ, 0, NULL, NULL)) 659 outb(xiobase + com_scr, 0x80); /* no irq */ 660 else 661 outb(xiobase + com_scr, 0); 662 } 663 mcr_image = 0; 664 } 665#endif /* COM_MULTIPORT */ 666 if (bus_get_resource(idev, SYS_RES_IRQ, 0, NULL, NULL) != 0) 667 mcr_image = 0; 668 669 bzero(failures, sizeof failures); 670 iobase = rman_get_start(port); 671 672 /* 673 * We don't want to get actual interrupts, just masked ones. 674 * Interrupts from this line should already be masked in the ICU, 675 * but mask them in the processor as well in case there are some 676 * (misconfigured) shared interrupts. 677 */ 678 disable_intr(); 679/* EXTRA DELAY? */ 680 681 /* 682 * Initialize the speed and the word size and wait long enough to 683 * drain the maximum of 16 bytes of junk in device output queues. 684 * The speed is undefined after a master reset and must be set 685 * before relying on anything related to output. There may be 686 * junk after a (very fast) soft reboot and (apparently) after 687 * master reset. 688 * XXX what about the UART bug avoided by waiting in comparam()? 689 * We don't want to to wait long enough to drain at 2 bps. 690 */ 691 if (iobase == siocniobase) 692 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10)); 693 else { 694 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 695 outb(iobase + com_dlbl, COMBRD(SIO_TEST_SPEED) & 0xff); 696 outb(iobase + com_dlbh, (u_int) COMBRD(SIO_TEST_SPEED) >> 8); 697 outb(iobase + com_cfcr, CFCR_8BITS); 698 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10)); 699 } 700 701 /* 702 * Enable the interrupt gate and disable device interupts. This 703 * should leave the device driving the interrupt line low and 704 * guarantee an edge trigger if an interrupt can be generated. 705 */ 706/* EXTRA DELAY? */ 707 outb(iobase + com_mcr, mcr_image); 708 outb(iobase + com_ier, 0); 709 DELAY(1000); /* XXX */ 710 irqmap[0] = isa_irq_pending(); 711 712 /* 713 * Attempt to set loopback mode so that we can send a null byte 714 * without annoying any external device. 715 */ 716/* EXTRA DELAY? */ 717 outb(iobase + com_mcr, mcr_image | MCR_LOOPBACK); 718 719 /* 720 * Attempt to generate an output interrupt. On 8250's, setting 721 * IER_ETXRDY generates an interrupt independent of the current 722 * setting and independent of whether the THR is empty. On 16450's, 723 * setting IER_ETXRDY generates an interrupt independent of the 724 * current setting. On 16550A's, setting IER_ETXRDY only 725 * generates an interrupt when IER_ETXRDY is not already set. 726 */ 727 outb(iobase + com_ier, IER_ETXRDY); 728 729 /* 730 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate 731 * an interrupt. They'd better generate one for actually doing 732 * output. Loopback may be broken on the same incompatibles but 733 * it's unlikely to do more than allow the null byte out. 734 */ 735 outb(iobase + com_data, 0); 736 DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10)); 737 738 /* 739 * Turn off loopback mode so that the interrupt gate works again 740 * (MCR_IENABLE was hidden). This should leave the device driving 741 * an interrupt line high. It doesn't matter if the interrupt 742 * line oscillates while we are not looking at it, since interrupts 743 * are disabled. 744 */ 745/* EXTRA DELAY? */ 746 outb(iobase + com_mcr, mcr_image); 747 748 /* 749 * Some pcmcia cards have the "TXRDY bug", so we check everyone 750 * for IIR_TXRDY implementation ( Palido 321s, DC-1S... ) 751 */ 752 if (COM_NOPROBE(flags)) { 753 /* Reading IIR register twice */ 754 for (fn = 0; fn < 2; fn ++) { 755 DELAY(10000); 756 failures[6] = inb(iobase + com_iir); 757 } 758 /* Check IIR_TXRDY clear ? */ 759 result = 0; 760 if (failures[6] & IIR_TXRDY) { 761 /* Nop, Double check with clearing IER */ 762 outb(iobase + com_ier, 0); 763 if (inb(iobase + com_iir) & IIR_NOPEND) { 764 /* Ok. we're familia this gang */ 765 SET_FLAG(dev, COM_C_IIR_TXRDYBUG); 766 } else { 767 /* Unknown, Just omit this chip.. XXX */ 768 result = ENXIO; 769 } 770 } else { 771 /* OK. this is well-known guys */ 772 CLR_FLAG(dev, COM_C_IIR_TXRDYBUG); 773 } 774 outb(iobase + com_cfcr, CFCR_8BITS); 775 enable_intr(); 776 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 777 return (iobase == siocniobase ? 0 : result); 778 } 779 780 /* 781 * Check that 782 * o the CFCR, IER and MCR in UART hold the values written to them 783 * (the values happen to be all distinct - this is good for 784 * avoiding false positive tests from bus echoes). 785 * o an output interrupt is generated and its vector is correct. 786 * o the interrupt goes away when the IIR in the UART is read. 787 */ 788/* EXTRA DELAY? */ 789 failures[0] = inb(iobase + com_cfcr) - CFCR_8BITS; 790 failures[1] = inb(iobase + com_ier) - IER_ETXRDY; 791 failures[2] = inb(iobase + com_mcr) - mcr_image; 792 DELAY(10000); /* Some internal modems need this time */ 793 irqmap[1] = isa_irq_pending(); 794 failures[4] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_TXRDY; 795 DELAY(1000); /* XXX */ 796 irqmap[2] = isa_irq_pending(); 797 failures[6] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_NOPEND; 798 799 /* 800 * Turn off all device interrupts and check that they go off properly. 801 * Leave MCR_IENABLE alone. For ports without a master port, it gates 802 * the OUT2 output of the UART to 803 * the ICU input. Closing the gate would give a floating ICU input 804 * (unless there is another device driving it) and spurious interrupts. 805 * (On the system that this was first tested on, the input floats high 806 * and gives a (masked) interrupt as soon as the gate is closed.) 807 */ 808 outb(iobase + com_ier, 0); 809 outb(iobase + com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */ 810 failures[7] = inb(iobase + com_ier); 811 DELAY(1000); /* XXX */ 812 irqmap[3] = isa_irq_pending(); 813 failures[9] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_NOPEND; 814 815 enable_intr(); 816 817 irqs = irqmap[1] & ~irqmap[0]; 818 if (bus_get_resource(idev, SYS_RES_IRQ, 0, &xirq, NULL) == 0 && 819 ((1 << xirq) & irqs) == 0) 820 printf( 821 "sio%d: configured irq %ld not in bitmap of probed irqs %#x\n", 822 device_get_unit(dev), xirq, irqs); 823 if (bootverbose) 824 printf("sio%d: irq maps: %#x %#x %#x %#x\n", 825 device_get_unit(dev), 826 irqmap[0], irqmap[1], irqmap[2], irqmap[3]); 827 828 result = 0; 829 for (fn = 0; fn < sizeof failures; ++fn) 830 if (failures[fn]) { 831 outb(iobase + com_mcr, 0); 832 result = ENXIO; 833 if (bootverbose) { 834 printf("sio%d: probe failed test(s):", 835 device_get_unit(dev)); 836 for (fn = 0; fn < sizeof failures; ++fn) 837 if (failures[fn]) 838 printf(" %d", fn); 839 printf("\n"); 840 } 841 break; 842 } 843 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 844 return (iobase == siocniobase ? 0 : result); 845} 846 847#ifdef COM_ESP 848static int 849espattach(com, esp_port) 850 struct com_s *com; 851 Port_t esp_port; 852{ 853 u_char dips; 854 u_char val; 855 856 /* 857 * Check the ESP-specific I/O port to see if we're an ESP 858 * card. If not, return failure immediately. 859 */ 860 if ((inb(esp_port) & 0xf3) == 0) { 861 printf(" port 0x%x is not an ESP board?\n", esp_port); 862 return (0); 863 } 864 865 /* 866 * We've got something that claims to be a Hayes ESP card. 867 * Let's hope so. 868 */ 869 870 /* Get the dip-switch configuration */ 871 outb(esp_port + ESP_CMD1, ESP_GETDIPS); 872 dips = inb(esp_port + ESP_STATUS1); 873 874 /* 875 * Bits 0,1 of dips say which COM port we are. 876 */ 877 if (com->iobase == likely_com_ports[dips & 0x03]) 878 printf(" : ESP"); 879 else { 880 printf(" esp_port has com %d\n", dips & 0x03); 881 return (0); 882 } 883 884 /* 885 * Check for ESP version 2.0 or later: bits 4,5,6 = 010. 886 */ 887 outb(esp_port + ESP_CMD1, ESP_GETTEST); 888 val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */ 889 val = inb(esp_port + ESP_STATUS2); 890 if ((val & 0x70) < 0x20) { 891 printf("-old (%o)", val & 0x70); 892 return (0); 893 } 894 895 /* 896 * Check for ability to emulate 16550: bit 7 == 1 897 */ 898 if ((dips & 0x80) == 0) { 899 printf(" slave"); 900 return (0); 901 } 902 903 /* 904 * Okay, we seem to be a Hayes ESP card. Whee. 905 */ 906 com->esp = TRUE; 907 com->esp_port = esp_port; 908 return (1); 909} 910#endif /* COM_ESP */ 911 912static int 913sio_isa_attach(dev) 914 device_t dev; 915{ 916 return (sioattach(dev)); 917} 918 919static int 920sioattach(dev) 921 device_t dev; 922{ 923 struct com_s *com; 924#ifdef COM_ESP 925 Port_t *espp; 926#endif 927 Port_t iobase; 928 int unit; 929 u_int flags; 930 int rid; 931 struct resource *port; 932 int ret; 933 934 rid = 0; 935 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 936 0, ~0, IO_COMSIZE, RF_ACTIVE); 937 if (!port) 938 return ENXIO; 939 940 iobase = rman_get_start(port); 941 unit = device_get_unit(dev); 942 com = device_get_softc(dev); 943 flags = device_get_flags(dev); 944 945 if (unit >= sio_numunits) 946 sio_numunits = unit + 1; 947 /* 948 * sioprobe() has initialized the device registers as follows: 949 * o cfcr = CFCR_8BITS. 950 * It is most important that CFCR_DLAB is off, so that the 951 * data port is not hidden when we enable interrupts. 952 * o ier = 0. 953 * Interrupts are only enabled when the line is open. 954 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible 955 * interrupt control register or the config specifies no irq. 956 * Keeping MCR_DTR and MCR_RTS off might stop the external 957 * device from sending before we are ready. 958 */ 959 bzero(com, sizeof *com); 960 com->unit = unit; 961 com->ioportres = port; 962 com->cfcr_image = CFCR_8BITS; 963 com->dtr_wait = 3 * hz; 964 com->loses_outints = COM_LOSESOUTINTS(flags) != 0; 965 com->no_irq = bus_get_resource(dev, SYS_RES_IRQ, 0, NULL, NULL); 966 com->tx_fifo_size = 1; 967 com->obufs[0].l_head = com->obuf1; 968 com->obufs[1].l_head = com->obuf2; 969 970 com->iobase = iobase; 971 com->data_port = iobase + com_data; 972 com->int_id_port = iobase + com_iir; 973 com->modem_ctl_port = iobase + com_mcr; 974 com->mcr_image = inb(com->modem_ctl_port); 975 com->line_status_port = iobase + com_lsr; 976 com->modem_status_port = iobase + com_msr; 977 com->intr_ctl_port = iobase + com_ier; 978 979 /* 980 * We don't use all the flags from <sys/ttydefaults.h> since they 981 * are only relevant for logins. It's important to have echo off 982 * initially so that the line doesn't start blathering before the 983 * echo flag can be turned off. 984 */ 985 com->it_in.c_iflag = 0; 986 com->it_in.c_oflag = 0; 987 com->it_in.c_cflag = TTYDEF_CFLAG; 988 com->it_in.c_lflag = 0; 989 if (unit == comconsole) { 990 com->it_in.c_iflag = TTYDEF_IFLAG; 991 com->it_in.c_oflag = TTYDEF_OFLAG; 992 com->it_in.c_cflag = TTYDEF_CFLAG | CLOCAL; 993 com->it_in.c_lflag = TTYDEF_LFLAG; 994 com->lt_out.c_cflag = com->lt_in.c_cflag = CLOCAL; 995 com->lt_out.c_ispeed = com->lt_out.c_ospeed = 996 com->lt_in.c_ispeed = com->lt_in.c_ospeed = 997 com->it_in.c_ispeed = com->it_in.c_ospeed = comdefaultrate; 998 } else 999 com->it_in.c_ispeed = com->it_in.c_ospeed = TTYDEF_SPEED; 1000 if (siosetwater(com, com->it_in.c_ispeed) != 0) { 1001 enable_intr(); 1002 free(com, M_DEVBUF); 1003 return (0); 1004 } 1005 enable_intr(); 1006 termioschars(&com->it_in); 1007 com->it_out = com->it_in; 1008 1009 /* attempt to determine UART type */ 1010 printf("sio%d: type", unit); 1011 1012 1013#ifdef COM_MULTIPORT 1014 if (!COM_ISMULTIPORT(flags) && !COM_IIR_TXRDYBUG(flags)) 1015#else 1016 if (!COM_IIR_TXRDYBUG(flags)) 1017#endif 1018 { 1019 u_char scr; 1020 u_char scr1; 1021 u_char scr2; 1022 1023 scr = inb(iobase + com_scr); 1024 outb(iobase + com_scr, 0xa5); 1025 scr1 = inb(iobase + com_scr); 1026 outb(iobase + com_scr, 0x5a); 1027 scr2 = inb(iobase + com_scr); 1028 outb(iobase + com_scr, scr); 1029 if (scr1 != 0xa5 || scr2 != 0x5a) { 1030 printf(" 8250"); 1031 goto determined_type; 1032 } 1033 } 1034 outb(iobase + com_fifo, FIFO_ENABLE | FIFO_RX_HIGH); 1035 DELAY(100); 1036 com->st16650a = 0; 1037 switch (inb(com->int_id_port) & IIR_FIFO_MASK) { 1038 case FIFO_RX_LOW: 1039 printf(" 16450"); 1040 break; 1041 case FIFO_RX_MEDL: 1042 printf(" 16450?"); 1043 break; 1044 case FIFO_RX_MEDH: 1045 printf(" 16550?"); 1046 break; 1047 case FIFO_RX_HIGH: 1048 if (COM_NOFIFO(flags)) { 1049 printf(" 16550A fifo disabled"); 1050 } else { 1051 com->hasfifo = TRUE; 1052 if (COM_ST16650A(flags)) { 1053 com->st16650a = 1; 1054 com->tx_fifo_size = 32; 1055 printf(" ST16650A"); 1056 } else { 1057 com->tx_fifo_size = COM_FIFOSIZE(flags); 1058 printf(" 16550A"); 1059 } 1060 } 1061#ifdef COM_ESP 1062 for (espp = likely_esp_ports; *espp != 0; espp++) 1063 if (espattach(com, *espp)) { 1064 com->tx_fifo_size = 1024; 1065 break; 1066 } 1067#endif 1068 if (!com->st16650a) { 1069 if (!com->tx_fifo_size) 1070 com->tx_fifo_size = 16; 1071 else 1072 printf(" lookalike with %d bytes FIFO", 1073 com->tx_fifo_size); 1074 } 1075 1076 break; 1077 } 1078 1079#ifdef COM_ESP 1080 if (com->esp) { 1081 /* 1082 * Set 16550 compatibility mode. 1083 * We don't use the ESP_MODE_SCALE bit to increase the 1084 * fifo trigger levels because we can't handle large 1085 * bursts of input. 1086 * XXX flow control should be set in comparam(), not here. 1087 */ 1088 outb(com->esp_port + ESP_CMD1, ESP_SETMODE); 1089 outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO); 1090 1091 /* Set RTS/CTS flow control. */ 1092 outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE); 1093 outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS); 1094 outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS); 1095 1096 /* Set flow-control levels. */ 1097 outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW); 1098 outb(com->esp_port + ESP_CMD2, HIBYTE(768)); 1099 outb(com->esp_port + ESP_CMD2, LOBYTE(768)); 1100 outb(com->esp_port + ESP_CMD2, HIBYTE(512)); 1101 outb(com->esp_port + ESP_CMD2, LOBYTE(512)); 1102 } 1103#endif /* COM_ESP */ 1104 outb(iobase + com_fifo, 0); 1105determined_type: ; 1106 1107#ifdef COM_MULTIPORT 1108 if (COM_ISMULTIPORT(flags)) { 1109 device_t masterdev; 1110 1111 com->multiport = TRUE; 1112 printf(" (multiport"); 1113 if (unit == COM_MPMASTER(flags)) 1114 printf(" master"); 1115 printf(")"); 1116 masterdev = devclass_get_device(sio_devclass, 1117 COM_MPMASTER(flags)); 1118 com->no_irq = bus_get_resource(masterdev, SYS_RES_IRQ, 0, NULL, 1119 NULL); 1120 } 1121#endif /* COM_MULTIPORT */ 1122 if (unit == comconsole) 1123 printf(", console"); 1124 if (COM_IIR_TXRDYBUG(flags)) 1125 printf(" with a bogus IIR_TXRDY register"); 1126 printf("\n"); 1127 1128 if (!sio_registered) { 1129 register_swi(SWI_TTY, siopoll); 1130 sio_registered = TRUE; 1131 } 1132 make_dev(&sio_cdevsw, unit, 1133 UID_ROOT, GID_WHEEL, 0600, "ttyd%r", unit); 1134 make_dev(&sio_cdevsw, unit | CONTROL_INIT_STATE, 1135 UID_ROOT, GID_WHEEL, 0600, "ttyid%r", unit); 1136 make_dev(&sio_cdevsw, unit | CONTROL_LOCK_STATE, 1137 UID_ROOT, GID_WHEEL, 0600, "ttyld%r", unit); 1138 make_dev(&sio_cdevsw, unit | CALLOUT_MASK, 1139 UID_UUCP, GID_DIALER, 0660, "cuaa%r", unit); 1140 make_dev(&sio_cdevsw, unit | CALLOUT_MASK | CONTROL_INIT_STATE, 1141 UID_UUCP, GID_DIALER, 0660, "cuaia%r", unit); 1142 make_dev(&sio_cdevsw, unit | CALLOUT_MASK | CONTROL_LOCK_STATE, 1143 UID_UUCP, GID_DIALER, 0660, "cuala%r", unit); 1144 com->flags = flags; 1145 com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 1146 pps_init(&com->pps); 1147 1148 rid = 0; 1149 com->irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0ul, ~0ul, 1, 1150 RF_ACTIVE); 1151 if (com->irqres) { 1152 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, com->irqres, 1153 INTR_TYPE_TTY | INTR_TYPE_FAST, 1154 siointr, com, &com->cookie); 1155 if (ret) { 1156 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, 1157 com->irqres, INTR_TYPE_TTY, 1158 siointr, com, &com->cookie); 1159 if (ret == 0) 1160 device_printf(dev, "unable to activate interrupt in fast mode - using normal mode"); 1161 } 1162 if (ret) 1163 device_printf(dev, "could not activate interrupt\n"); 1164 } 1165 1166 return (0); 1167} 1168 1169static int 1170sioopen(dev, flag, mode, p) 1171 dev_t dev; 1172 int flag; 1173 int mode; 1174 struct proc *p; 1175{ 1176 struct com_s *com; 1177 int error; 1178 Port_t iobase; 1179 int mynor; 1180 int s; 1181 struct tty *tp; 1182 int unit; 1183 1184 mynor = minor(dev); 1185 unit = MINOR_TO_UNIT(mynor); 1186 com = com_addr(unit); 1187 if (com == NULL) 1188 return (ENXIO); 1189 if (com->gone) 1190 return (ENXIO); 1191 if (mynor & CONTROL_MASK) 1192 return (0); 1193 tp = dev->si_tty = com->tp = ttymalloc(com->tp); 1194 s = spltty(); 1195 /* 1196 * We jump to this label after all non-interrupted sleeps to pick 1197 * up any changes of the device state. 1198 */ 1199open_top: 1200 while (com->state & CS_DTR_OFF) { 1201 error = tsleep(&com->dtr_wait, TTIPRI | PCATCH, "siodtr", 0); 1202 if (com_addr(unit) == NULL) 1203 return (ENXIO); 1204 if (error != 0 || com->gone) 1205 goto out; 1206 } 1207 if (tp->t_state & TS_ISOPEN) { 1208 /* 1209 * The device is open, so everything has been initialized. 1210 * Handle conflicts. 1211 */ 1212 if (mynor & CALLOUT_MASK) { 1213 if (!com->active_out) { 1214 error = EBUSY; 1215 goto out; 1216 } 1217 } else { 1218 if (com->active_out) { 1219 if (flag & O_NONBLOCK) { 1220 error = EBUSY; 1221 goto out; 1222 } 1223 error = tsleep(&com->active_out, 1224 TTIPRI | PCATCH, "siobi", 0); 1225 if (com_addr(unit) == NULL) 1226 return (ENXIO); 1227 if (error != 0 || com->gone) 1228 goto out; 1229 goto open_top; 1230 } 1231 } 1232 if (tp->t_state & TS_XCLUDE && 1233 suser(p)) { 1234 error = EBUSY; 1235 goto out; 1236 } 1237 } else { 1238 /* 1239 * The device isn't open, so there are no conflicts. 1240 * Initialize it. Initialization is done twice in many 1241 * cases: to preempt sleeping callin opens if we are 1242 * callout, and to complete a callin open after DCD rises. 1243 */ 1244 tp->t_oproc = comstart; 1245 tp->t_param = comparam; 1246 tp->t_stop = comstop; 1247 tp->t_dev = dev; 1248 tp->t_termios = mynor & CALLOUT_MASK 1249 ? com->it_out : com->it_in; 1250 (void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET); 1251 com->poll = com->no_irq; 1252 com->poll_output = com->loses_outints; 1253 ++com->wopeners; 1254 error = comparam(tp, &tp->t_termios); 1255 --com->wopeners; 1256 if (error != 0) 1257 goto out; 1258 /* 1259 * XXX we should goto open_top if comparam() slept. 1260 */ 1261 iobase = com->iobase; 1262 if (com->hasfifo) { 1263 /* 1264 * (Re)enable and drain fifos. 1265 * 1266 * Certain SMC chips cause problems if the fifos 1267 * are enabled while input is ready. Turn off the 1268 * fifo if necessary to clear the input. We test 1269 * the input ready bit after enabling the fifos 1270 * since we've already enabled them in comparam() 1271 * and to handle races between enabling and fresh 1272 * input. 1273 */ 1274 while (TRUE) { 1275 outb(iobase + com_fifo, 1276 FIFO_RCV_RST | FIFO_XMT_RST 1277 | com->fifo_image); 1278 /* 1279 * XXX the delays are for superstitious 1280 * historical reasons. It must be less than 1281 * the character time at the maximum 1282 * supported speed (87 usec at 115200 bps 1283 * 8N1). Otherwise we might loop endlessly 1284 * if data is streaming in. We used to use 1285 * delays of 100. That usually worked 1286 * because DELAY(100) used to usually delay 1287 * for about 85 usec instead of 100. 1288 */ 1289 DELAY(50); 1290 if (!(inb(com->line_status_port) & LSR_RXRDY)) 1291 break; 1292 outb(iobase + com_fifo, 0); 1293 DELAY(50); 1294 (void) inb(com->data_port); 1295 } 1296 } 1297 1298 disable_intr(); 1299 (void) inb(com->line_status_port); 1300 (void) inb(com->data_port); 1301 com->prev_modem_status = com->last_modem_status 1302 = inb(com->modem_status_port); 1303 if (COM_IIR_TXRDYBUG(com->flags)) { 1304 outb(com->intr_ctl_port, IER_ERXRDY | IER_ERLS 1305 | IER_EMSC); 1306 } else { 1307 outb(com->intr_ctl_port, IER_ERXRDY | IER_ETXRDY 1308 | IER_ERLS | IER_EMSC); 1309 } 1310 enable_intr(); 1311 /* 1312 * Handle initial DCD. Callout devices get a fake initial 1313 * DCD (trapdoor DCD). If we are callout, then any sleeping 1314 * callin opens get woken up and resume sleeping on "siobi" 1315 * instead of "siodcd". 1316 */ 1317 /* 1318 * XXX `mynor & CALLOUT_MASK' should be 1319 * `tp->t_cflag & (SOFT_CARRIER | TRAPDOOR_CARRIER) where 1320 * TRAPDOOR_CARRIER is the default initial state for callout 1321 * devices and SOFT_CARRIER is like CLOCAL except it hides 1322 * the true carrier. 1323 */ 1324 if (com->prev_modem_status & MSR_DCD || mynor & CALLOUT_MASK) 1325 (*linesw[tp->t_line].l_modem)(tp, 1); 1326 } 1327 /* 1328 * Wait for DCD if necessary. 1329 */ 1330 if (!(tp->t_state & TS_CARR_ON) && !(mynor & CALLOUT_MASK) 1331 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 1332 ++com->wopeners; 1333 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "siodcd", 0); 1334 if (com_addr(unit) == NULL) 1335 return (ENXIO); 1336 --com->wopeners; 1337 if (error != 0 || com->gone) 1338 goto out; 1339 goto open_top; 1340 } 1341 error = (*linesw[tp->t_line].l_open)(dev, tp); 1342 disc_optim(tp, &tp->t_termios, com); 1343 if (tp->t_state & TS_ISOPEN && mynor & CALLOUT_MASK) 1344 com->active_out = TRUE; 1345 siosettimeout(); 1346out: 1347 splx(s); 1348 if (!(tp->t_state & TS_ISOPEN) && com->wopeners == 0) 1349 comhardclose(com); 1350 return (error); 1351} 1352 1353static int 1354sioclose(dev, flag, mode, p) 1355 dev_t dev; 1356 int flag; 1357 int mode; 1358 struct proc *p; 1359{ 1360 struct com_s *com; 1361 int mynor; 1362 int s; 1363 struct tty *tp; 1364 1365 mynor = minor(dev); 1366 if (mynor & CONTROL_MASK) 1367 return (0); 1368 com = com_addr(MINOR_TO_UNIT(mynor)); 1369 tp = com->tp; 1370 s = spltty(); 1371 (*linesw[tp->t_line].l_close)(tp, flag); 1372 disc_optim(tp, &tp->t_termios, com); 1373 comstop(tp, FREAD | FWRITE); 1374 comhardclose(com); 1375 ttyclose(tp); 1376 siosettimeout(); 1377 splx(s); 1378 if (com->gone) { 1379 printf("sio%d: gone\n", com->unit); 1380 s = spltty(); 1381 if (com->ibuf != NULL) 1382 free(com->ibuf, M_DEVBUF); 1383 bzero(tp, sizeof *tp); 1384 free(com, M_DEVBUF); 1385 splx(s); 1386 } 1387 return (0); 1388} 1389 1390static void 1391comhardclose(com) 1392 struct com_s *com; 1393{ 1394 Port_t iobase; 1395 int s; 1396 struct tty *tp; 1397 int unit; 1398 1399 unit = com->unit; 1400 iobase = com->iobase; 1401 s = spltty(); 1402 com->poll = FALSE; 1403 com->poll_output = FALSE; 1404 com->do_timestamp = FALSE; 1405 com->do_dcd_timestamp = FALSE; 1406 com->pps.ppsparam.mode = 0; 1407 outb(iobase + com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 1408 { 1409 outb(iobase + com_ier, 0); 1410 tp = com->tp; 1411 if (tp->t_cflag & HUPCL 1412 /* 1413 * XXX we will miss any carrier drop between here and the 1414 * next open. Perhaps we should watch DCD even when the 1415 * port is closed; it is not sufficient to check it at 1416 * the next open because it might go up and down while 1417 * we're not watching. 1418 */ 1419 || (!com->active_out 1420 && !(com->prev_modem_status & MSR_DCD) 1421 && !(com->it_in.c_cflag & CLOCAL)) 1422 || !(tp->t_state & TS_ISOPEN)) { 1423 (void)commctl(com, TIOCM_DTR, DMBIC); 1424 if (com->dtr_wait != 0 && !(com->state & CS_DTR_OFF)) { 1425 timeout(siodtrwakeup, com, com->dtr_wait); 1426 com->state |= CS_DTR_OFF; 1427 } 1428 } 1429 } 1430 if (com->hasfifo) { 1431 /* 1432 * Disable fifos so that they are off after controlled 1433 * reboots. Some BIOSes fail to detect 16550s when the 1434 * fifos are enabled. 1435 */ 1436 outb(iobase + com_fifo, 0); 1437 } 1438 com->active_out = FALSE; 1439 wakeup(&com->active_out); 1440 wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */ 1441 splx(s); 1442} 1443 1444static int 1445sioread(dev, uio, flag) 1446 dev_t dev; 1447 struct uio *uio; 1448 int flag; 1449{ 1450 int mynor; 1451 struct com_s *com; 1452 1453 mynor = minor(dev); 1454 if (mynor & CONTROL_MASK) 1455 return (ENODEV); 1456 com = com_addr(MINOR_TO_UNIT(mynor)); 1457 if (com->gone) 1458 return (ENODEV); 1459 return ((*linesw[com->tp->t_line].l_read)(com->tp, uio, flag)); 1460} 1461 1462static int 1463siowrite(dev, uio, flag) 1464 dev_t dev; 1465 struct uio *uio; 1466 int flag; 1467{ 1468 int mynor; 1469 struct com_s *com; 1470 int unit; 1471 1472 mynor = minor(dev); 1473 if (mynor & CONTROL_MASK) 1474 return (ENODEV); 1475 1476 unit = MINOR_TO_UNIT(mynor); 1477 com = com_addr(unit); 1478 if (com->gone) 1479 return (ENODEV); 1480 /* 1481 * (XXX) We disallow virtual consoles if the physical console is 1482 * a serial port. This is in case there is a display attached that 1483 * is not the console. In that situation we don't need/want the X 1484 * server taking over the console. 1485 */ 1486 if (constty != NULL && unit == comconsole) 1487 constty = NULL; 1488 return ((*linesw[com->tp->t_line].l_write)(com->tp, uio, flag)); 1489} 1490 1491static void 1492siobusycheck(chan) 1493 void *chan; 1494{ 1495 struct com_s *com; 1496 int s; 1497 1498 com = (struct com_s *)chan; 1499 1500 /* 1501 * Clear TS_BUSY if low-level output is complete. 1502 * spl locking is sufficient because siointr1() does not set CS_BUSY. 1503 * If siointr1() clears CS_BUSY after we look at it, then we'll get 1504 * called again. Reading the line status port outside of siointr1() 1505 * is safe because CS_BUSY is clear so there are no output interrupts 1506 * to lose. 1507 */ 1508 s = spltty(); 1509 if (com->state & CS_BUSY) 1510 com->extra_state &= ~CSE_BUSYCHECK; /* False alarm. */ 1511 else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY)) 1512 == (LSR_TSRE | LSR_TXRDY)) { 1513 com->tp->t_state &= ~TS_BUSY; 1514 ttwwakeup(com->tp); 1515 com->extra_state &= ~CSE_BUSYCHECK; 1516 } else 1517 timeout(siobusycheck, com, hz / 100); 1518 splx(s); 1519} 1520 1521static void 1522siodtrwakeup(chan) 1523 void *chan; 1524{ 1525 struct com_s *com; 1526 1527 com = (struct com_s *)chan; 1528 com->state &= ~CS_DTR_OFF; 1529 wakeup(&com->dtr_wait); 1530} 1531 1532static void 1533sioinput(com) 1534 struct com_s *com; 1535{ 1536 u_char *buf; 1537 int incc; 1538 u_char line_status; 1539 int recv_data; 1540 struct tty *tp; 1541 1542 buf = com->ibuf; 1543 tp = com->tp; 1544 if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) { 1545 com_events -= (com->iptr - com->ibuf); 1546 com->iptr = com->ibuf; 1547 return; 1548 } 1549 if (tp->t_state & TS_CAN_BYPASS_L_RINT) { 1550 /* 1551 * Avoid the grotesquely inefficient lineswitch routine 1552 * (ttyinput) in "raw" mode. It usually takes about 450 1553 * instructions (that's without canonical processing or echo!). 1554 * slinput is reasonably fast (usually 40 instructions plus 1555 * call overhead). 1556 */ 1557 do { 1558 enable_intr(); 1559 incc = com->iptr - buf; 1560 if (tp->t_rawq.c_cc + incc > tp->t_ihiwat 1561 && (com->state & CS_RTS_IFLOW 1562 || tp->t_iflag & IXOFF) 1563 && !(tp->t_state & TS_TBLOCK)) 1564 ttyblock(tp); 1565 com->delta_error_counts[CE_TTY_BUF_OVERFLOW] 1566 += b_to_q((char *)buf, incc, &tp->t_rawq); 1567 buf += incc; 1568 tk_nin += incc; 1569 tk_rawcc += incc; 1570 tp->t_rawcc += incc; 1571 ttwakeup(tp); 1572 if (tp->t_state & TS_TTSTOP 1573 && (tp->t_iflag & IXANY 1574 || tp->t_cc[VSTART] == tp->t_cc[VSTOP])) { 1575 tp->t_state &= ~TS_TTSTOP; 1576 tp->t_lflag &= ~FLUSHO; 1577 comstart(tp); 1578 } 1579 disable_intr(); 1580 } while (buf < com->iptr); 1581 } else { 1582 do { 1583 enable_intr(); 1584 line_status = buf[com->ierroff]; 1585 recv_data = *buf++; 1586 if (line_status 1587 & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) { 1588 if (line_status & LSR_BI) 1589 recv_data |= TTY_BI; 1590 if (line_status & LSR_FE) 1591 recv_data |= TTY_FE; 1592 if (line_status & LSR_OE) 1593 recv_data |= TTY_OE; 1594 if (line_status & LSR_PE) 1595 recv_data |= TTY_PE; 1596 } 1597 (*linesw[tp->t_line].l_rint)(recv_data, tp); 1598 disable_intr(); 1599 } while (buf < com->iptr); 1600 } 1601 com_events -= (com->iptr - com->ibuf); 1602 com->iptr = com->ibuf; 1603 1604 /* 1605 * There is now room for another low-level buffer full of input, 1606 * so enable RTS if it is now disabled and there is room in the 1607 * high-level buffer. 1608 */ 1609 if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) && 1610 !(tp->t_state & TS_TBLOCK)) 1611 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 1612} 1613 1614void 1615siointr(arg) 1616 void *arg; 1617{ 1618#ifndef COM_MULTIPORT 1619 COM_LOCK(); 1620 siointr1((struct com_s *) arg); 1621 COM_UNLOCK(); 1622#else /* COM_MULTIPORT */ 1623 bool_t possibly_more_intrs; 1624 int unit; 1625 struct com_s *com; 1626 1627 /* 1628 * Loop until there is no activity on any port. This is necessary 1629 * to get an interrupt edge more than to avoid another interrupt. 1630 * If the IRQ signal is just an OR of the IRQ signals from several 1631 * devices, then the edge from one may be lost because another is 1632 * on. 1633 */ 1634 COM_LOCK(); 1635 do { 1636 possibly_more_intrs = FALSE; 1637 for (unit = 0; unit < sio_numunits; ++unit) { 1638 com = com_addr(unit); 1639 /* 1640 * XXX COM_LOCK(); 1641 * would it work here, or be counter-productive? 1642 */ 1643 if (com != NULL 1644 && !com->gone 1645 && (inb(com->int_id_port) & IIR_IMASK) 1646 != IIR_NOPEND) { 1647 siointr1(com); 1648 possibly_more_intrs = TRUE; 1649 } 1650 /* XXX COM_UNLOCK(); */ 1651 } 1652 } while (possibly_more_intrs); 1653 COM_UNLOCK(); 1654#endif /* COM_MULTIPORT */ 1655} 1656 1657static void 1658siointr1(com) 1659 struct com_s *com; 1660{ 1661 u_char line_status; 1662 u_char modem_status; 1663 u_char *ioptr; 1664 u_char recv_data; 1665 u_char int_ctl; 1666 u_char int_ctl_new; 1667 struct timecounter *tc; 1668 u_int count; 1669 1670 int_ctl = inb(com->intr_ctl_port); 1671 int_ctl_new = int_ctl; 1672 1673 while (!com->gone) { 1674 if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) { 1675 modem_status = inb(com->modem_status_port); 1676 if ((modem_status ^ com->last_modem_status) & MSR_DCD) { 1677 tc = timecounter; 1678 count = tc->tc_get_timecount(tc); 1679 pps_event(&com->pps, tc, count, 1680 (modem_status & MSR_DCD) ? 1681 PPS_CAPTUREASSERT : PPS_CAPTURECLEAR); 1682 } 1683 } 1684 line_status = inb(com->line_status_port); 1685 1686 /* input event? (check first to help avoid overruns) */ 1687 while (line_status & LSR_RCV_MASK) { 1688 /* break/unnattached error bits or real input? */ 1689 if (!(line_status & LSR_RXRDY)) 1690 recv_data = 0; 1691 else 1692 recv_data = inb(com->data_port); 1693 if (line_status & (LSR_BI | LSR_FE | LSR_PE)) { 1694 /* 1695 * Don't store BI if IGNBRK or FE/PE if IGNPAR. 1696 * Otherwise, push the work to a higher level 1697 * (to handle PARMRK) if we're bypassing. 1698 * Otherwise, convert BI/FE and PE+INPCK to 0. 1699 * 1700 * This makes bypassing work right in the 1701 * usual "raw" case (IGNBRK set, and IGNPAR 1702 * and INPCK clear). 1703 * 1704 * Note: BI together with FE/PE means just BI. 1705 */ 1706 if (line_status & LSR_BI) { 1707#if defined(DDB) && defined(BREAK_TO_DEBUGGER) 1708 if (com->unit == comconsole) { 1709 breakpoint(); 1710 goto cont; 1711 } 1712#endif 1713 if (com->tp == NULL 1714 || com->tp->t_iflag & IGNBRK) 1715 goto cont; 1716 } else { 1717 if (com->tp == NULL 1718 || com->tp->t_iflag & IGNPAR) 1719 goto cont; 1720 } 1721 if (com->tp->t_state & TS_CAN_BYPASS_L_RINT 1722 && (line_status & (LSR_BI | LSR_FE) 1723 || com->tp->t_iflag & INPCK)) 1724 recv_data = 0; 1725 } 1726 ++com->bytes_in; 1727 if (com->hotchar != 0 && recv_data == com->hotchar) 1728 setsofttty(); 1729 ioptr = com->iptr; 1730 if (ioptr >= com->ibufend) 1731 CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW); 1732 else { 1733 if (com->do_timestamp) 1734 microtime(&com->timestamp); 1735 ++com_events; 1736 schedsofttty(); 1737#if 0 /* for testing input latency vs efficiency */ 1738if (com->iptr - com->ibuf == 8) 1739 setsofttty(); 1740#endif 1741 ioptr[0] = recv_data; 1742 ioptr[com->ierroff] = line_status; 1743 com->iptr = ++ioptr; 1744 if (ioptr == com->ihighwater 1745 && com->state & CS_RTS_IFLOW) 1746 outb(com->modem_ctl_port, 1747 com->mcr_image &= ~MCR_RTS); 1748 if (line_status & LSR_OE) 1749 CE_RECORD(com, CE_OVERRUN); 1750 } 1751cont: 1752 /* 1753 * "& 0x7F" is to avoid the gcc-1.40 generating a slow 1754 * jump from the top of the loop to here 1755 */ 1756 line_status = inb(com->line_status_port) & 0x7F; 1757 } 1758 1759 /* modem status change? (always check before doing output) */ 1760 modem_status = inb(com->modem_status_port); 1761 if (modem_status != com->last_modem_status) { 1762 if (com->do_dcd_timestamp 1763 && !(com->last_modem_status & MSR_DCD) 1764 && modem_status & MSR_DCD) 1765 microtime(&com->dcd_timestamp); 1766 1767 /* 1768 * Schedule high level to handle DCD changes. Note 1769 * that we don't use the delta bits anywhere. Some 1770 * UARTs mess them up, and it's easy to remember the 1771 * previous bits and calculate the delta. 1772 */ 1773 com->last_modem_status = modem_status; 1774 if (!(com->state & CS_CHECKMSR)) { 1775 com_events += LOTS_OF_EVENTS; 1776 com->state |= CS_CHECKMSR; 1777 setsofttty(); 1778 } 1779 1780 /* handle CTS change immediately for crisp flow ctl */ 1781 if (com->state & CS_CTS_OFLOW) { 1782 if (modem_status & MSR_CTS) 1783 com->state |= CS_ODEVREADY; 1784 else 1785 com->state &= ~CS_ODEVREADY; 1786 } 1787 } 1788 1789 /* output queued and everything ready? */ 1790 if (line_status & LSR_TXRDY 1791 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) { 1792 ioptr = com->obufq.l_head; 1793 if (com->tx_fifo_size > 1) { 1794 u_int ocount; 1795 1796 ocount = com->obufq.l_tail - ioptr; 1797 if (ocount > com->tx_fifo_size) 1798 ocount = com->tx_fifo_size; 1799 com->bytes_out += ocount; 1800 do 1801 outb(com->data_port, *ioptr++); 1802 while (--ocount != 0); 1803 } else { 1804 outb(com->data_port, *ioptr++); 1805 ++com->bytes_out; 1806 } 1807 com->obufq.l_head = ioptr; 1808 if (COM_IIR_TXRDYBUG(com->flags)) { 1809 int_ctl_new = int_ctl | IER_ETXRDY; 1810 } 1811 if (ioptr >= com->obufq.l_tail) { 1812 struct lbq *qp; 1813 1814 qp = com->obufq.l_next; 1815 qp->l_queued = FALSE; 1816 qp = qp->l_next; 1817 if (qp != NULL) { 1818 com->obufq.l_head = qp->l_head; 1819 com->obufq.l_tail = qp->l_tail; 1820 com->obufq.l_next = qp; 1821 } else { 1822 /* output just completed */ 1823 if (COM_IIR_TXRDYBUG(com->flags)) { 1824 int_ctl_new = int_ctl & ~IER_ETXRDY; 1825 } 1826 com->state &= ~CS_BUSY; 1827 } 1828 if (!(com->state & CS_ODONE)) { 1829 com_events += LOTS_OF_EVENTS; 1830 com->state |= CS_ODONE; 1831 setsofttty(); /* handle at high level ASAP */ 1832 } 1833 } 1834 if (COM_IIR_TXRDYBUG(com->flags) && (int_ctl != int_ctl_new)) { 1835 outb(com->intr_ctl_port, int_ctl_new); 1836 } 1837 } 1838 1839 /* finished? */ 1840#ifndef COM_MULTIPORT 1841 if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND) 1842#endif /* COM_MULTIPORT */ 1843 return; 1844 } 1845} 1846 1847static int 1848sioioctl(dev, cmd, data, flag, p) 1849 dev_t dev; 1850 u_long cmd; 1851 caddr_t data; 1852 int flag; 1853 struct proc *p; 1854{ 1855 struct com_s *com; 1856 int error; 1857 Port_t iobase; 1858 int mynor; 1859 int s; 1860 struct tty *tp; 1861#if defined(COMPAT_43) || defined(COMPAT_SUNOS) 1862 u_long oldcmd; 1863 struct termios term; 1864#endif 1865 1866 mynor = minor(dev); 1867 com = com_addr(MINOR_TO_UNIT(mynor)); 1868 if (com->gone) 1869 return (ENODEV); 1870 iobase = com->iobase; 1871 if (mynor & CONTROL_MASK) { 1872 struct termios *ct; 1873 1874 switch (mynor & CONTROL_MASK) { 1875 case CONTROL_INIT_STATE: 1876 ct = mynor & CALLOUT_MASK ? &com->it_out : &com->it_in; 1877 break; 1878 case CONTROL_LOCK_STATE: 1879 ct = mynor & CALLOUT_MASK ? &com->lt_out : &com->lt_in; 1880 break; 1881 default: 1882 return (ENODEV); /* /dev/nodev */ 1883 } 1884 switch (cmd) { 1885 case TIOCSETA: 1886 error = suser(p); 1887 if (error != 0) 1888 return (error); 1889 *ct = *(struct termios *)data; 1890 return (0); 1891 case TIOCGETA: 1892 *(struct termios *)data = *ct; 1893 return (0); 1894 case TIOCGETD: 1895 *(int *)data = TTYDISC; 1896 return (0); 1897 case TIOCGWINSZ: 1898 bzero(data, sizeof(struct winsize)); 1899 return (0); 1900 default: 1901 return (ENOTTY); 1902 } 1903 } 1904 tp = com->tp; 1905#if defined(COMPAT_43) || defined(COMPAT_SUNOS) 1906 term = tp->t_termios; 1907 oldcmd = cmd; 1908 error = ttsetcompat(tp, &cmd, data, &term); 1909 if (error != 0) 1910 return (error); 1911 if (cmd != oldcmd) 1912 data = (caddr_t)&term; 1913#endif 1914 if (cmd == TIOCSETA || cmd == TIOCSETAW || cmd == TIOCSETAF) { 1915 int cc; 1916 struct termios *dt = (struct termios *)data; 1917 struct termios *lt = mynor & CALLOUT_MASK 1918 ? &com->lt_out : &com->lt_in; 1919 1920 dt->c_iflag = (tp->t_iflag & lt->c_iflag) 1921 | (dt->c_iflag & ~lt->c_iflag); 1922 dt->c_oflag = (tp->t_oflag & lt->c_oflag) 1923 | (dt->c_oflag & ~lt->c_oflag); 1924 dt->c_cflag = (tp->t_cflag & lt->c_cflag) 1925 | (dt->c_cflag & ~lt->c_cflag); 1926 dt->c_lflag = (tp->t_lflag & lt->c_lflag) 1927 | (dt->c_lflag & ~lt->c_lflag); 1928 for (cc = 0; cc < NCCS; ++cc) 1929 if (lt->c_cc[cc] != 0) 1930 dt->c_cc[cc] = tp->t_cc[cc]; 1931 if (lt->c_ispeed != 0) 1932 dt->c_ispeed = tp->t_ispeed; 1933 if (lt->c_ospeed != 0) 1934 dt->c_ospeed = tp->t_ospeed; 1935 } 1936 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 1937 if (error != ENOIOCTL) 1938 return (error); 1939 s = spltty(); 1940 error = ttioctl(tp, cmd, data, flag); 1941 disc_optim(tp, &tp->t_termios, com); 1942 if (error != ENOIOCTL) { 1943 splx(s); 1944 return (error); 1945 } 1946 switch (cmd) { 1947 case TIOCSBRK: 1948 outb(iobase + com_cfcr, com->cfcr_image |= CFCR_SBREAK); 1949 break; 1950 case TIOCCBRK: 1951 outb(iobase + com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 1952 break; 1953 case TIOCSDTR: 1954 (void)commctl(com, TIOCM_DTR, DMBIS); 1955 break; 1956 case TIOCCDTR: 1957 (void)commctl(com, TIOCM_DTR, DMBIC); 1958 break; 1959 /* 1960 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The 1961 * changes get undone on the next call to comparam(). 1962 */ 1963 case TIOCMSET: 1964 (void)commctl(com, *(int *)data, DMSET); 1965 break; 1966 case TIOCMBIS: 1967 (void)commctl(com, *(int *)data, DMBIS); 1968 break; 1969 case TIOCMBIC: 1970 (void)commctl(com, *(int *)data, DMBIC); 1971 break; 1972 case TIOCMGET: 1973 *(int *)data = commctl(com, 0, DMGET); 1974 break; 1975 case TIOCMSDTRWAIT: 1976 /* must be root since the wait applies to following logins */ 1977 error = suser(p); 1978 if (error != 0) { 1979 splx(s); 1980 return (error); 1981 } 1982 com->dtr_wait = *(int *)data * hz / 100; 1983 break; 1984 case TIOCMGDTRWAIT: 1985 *(int *)data = com->dtr_wait * 100 / hz; 1986 break; 1987 case TIOCTIMESTAMP: 1988 com->do_timestamp = TRUE; 1989 *(struct timeval *)data = com->timestamp; 1990 break; 1991 case TIOCDCDTIMESTAMP: 1992 com->do_dcd_timestamp = TRUE; 1993 *(struct timeval *)data = com->dcd_timestamp; 1994 break; 1995 default: 1996 splx(s); 1997 error = pps_ioctl(cmd, data, &com->pps); 1998 if (error == ENODEV) 1999 error = ENOTTY; 2000 return (error); 2001 } 2002 splx(s); 2003 return (0); 2004} 2005 2006static void 2007siopoll() 2008{ 2009 int unit; 2010 2011 if (com_events == 0) 2012 return; 2013repeat: 2014 for (unit = 0; unit < sio_numunits; ++unit) { 2015 struct com_s *com; 2016 int incc; 2017 struct tty *tp; 2018 2019 com = com_addr(unit); 2020 if (com == NULL) 2021 continue; 2022 tp = com->tp; 2023 if (tp == NULL || com->gone) { 2024 /* 2025 * Discard any events related to never-opened or 2026 * going-away devices. 2027 */ 2028 disable_intr(); 2029 incc = com->iptr - com->ibuf; 2030 com->iptr = com->ibuf; 2031 if (com->state & CS_CHECKMSR) { 2032 incc += LOTS_OF_EVENTS; 2033 com->state &= ~CS_CHECKMSR; 2034 } 2035 com_events -= incc; 2036 enable_intr(); 2037 continue; 2038 } 2039 if (com->iptr != com->ibuf) { 2040 disable_intr(); 2041 sioinput(com); 2042 enable_intr(); 2043 } 2044 if (com->state & CS_CHECKMSR) { 2045 u_char delta_modem_status; 2046 2047 disable_intr(); 2048 delta_modem_status = com->last_modem_status 2049 ^ com->prev_modem_status; 2050 com->prev_modem_status = com->last_modem_status; 2051 com_events -= LOTS_OF_EVENTS; 2052 com->state &= ~CS_CHECKMSR; 2053 enable_intr(); 2054 if (delta_modem_status & MSR_DCD) 2055 (*linesw[tp->t_line].l_modem) 2056 (tp, com->prev_modem_status & MSR_DCD); 2057 } 2058 if (com->state & CS_ODONE) { 2059 disable_intr(); 2060 com_events -= LOTS_OF_EVENTS; 2061 com->state &= ~CS_ODONE; 2062 enable_intr(); 2063 if (!(com->state & CS_BUSY) 2064 && !(com->extra_state & CSE_BUSYCHECK)) { 2065 timeout(siobusycheck, com, hz / 100); 2066 com->extra_state |= CSE_BUSYCHECK; 2067 } 2068 (*linesw[tp->t_line].l_start)(tp); 2069 } 2070 if (com_events == 0) 2071 break; 2072 } 2073 if (com_events >= LOTS_OF_EVENTS) 2074 goto repeat; 2075} 2076 2077static int 2078comparam(tp, t) 2079 struct tty *tp; 2080 struct termios *t; 2081{ 2082 u_int cfcr; 2083 int cflag; 2084 struct com_s *com; 2085 int divisor; 2086 u_char dlbh; 2087 u_char dlbl; 2088 Port_t iobase; 2089 int s; 2090 int unit; 2091 2092 /* do historical conversions */ 2093 if (t->c_ispeed == 0) 2094 t->c_ispeed = t->c_ospeed; 2095 2096 /* check requested parameters */ 2097 divisor = ttspeedtab(t->c_ospeed, comspeedtab); 2098 if (divisor < 0 || (divisor > 0 && t->c_ispeed != t->c_ospeed)) 2099 return (EINVAL); 2100 2101 /* parameters are OK, convert them to the com struct and the device */ 2102 unit = DEV_TO_UNIT(tp->t_dev); 2103 com = com_addr(unit); 2104 iobase = com->iobase; 2105 s = spltty(); 2106 if (divisor == 0) 2107 (void)commctl(com, TIOCM_DTR, DMBIC); /* hang up line */ 2108 else 2109 (void)commctl(com, TIOCM_DTR, DMBIS); 2110 cflag = t->c_cflag; 2111 switch (cflag & CSIZE) { 2112 case CS5: 2113 cfcr = CFCR_5BITS; 2114 break; 2115 case CS6: 2116 cfcr = CFCR_6BITS; 2117 break; 2118 case CS7: 2119 cfcr = CFCR_7BITS; 2120 break; 2121 default: 2122 cfcr = CFCR_8BITS; 2123 break; 2124 } 2125 if (cflag & PARENB) { 2126 cfcr |= CFCR_PENAB; 2127 if (!(cflag & PARODD)) 2128 cfcr |= CFCR_PEVEN; 2129 } 2130 if (cflag & CSTOPB) 2131 cfcr |= CFCR_STOPB; 2132 2133 if (com->hasfifo && divisor != 0) { 2134 /* 2135 * Use a fifo trigger level low enough so that the input 2136 * latency from the fifo is less than about 16 msec and 2137 * the total latency is less than about 30 msec. These 2138 * latencies are reasonable for humans. Serial comms 2139 * protocols shouldn't expect anything better since modem 2140 * latencies are larger. 2141 */ 2142 com->fifo_image = t->c_ospeed <= 4800 2143 ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_HIGH; 2144#ifdef COM_ESP 2145 /* 2146 * The Hayes ESP card needs the fifo DMA mode bit set 2147 * in compatibility mode. If not, it will interrupt 2148 * for each character received. 2149 */ 2150 if (com->esp) 2151 com->fifo_image |= FIFO_DMA_MODE; 2152#endif 2153 outb(iobase + com_fifo, com->fifo_image); 2154 } 2155 2156 /* 2157 * This returns with interrupts disabled so that we can complete 2158 * the speed change atomically. Keeping interrupts disabled is 2159 * especially important while com_data is hidden. 2160 */ 2161 (void) siosetwater(com, t->c_ispeed); 2162 2163 if (divisor != 0) { 2164 outb(iobase + com_cfcr, cfcr | CFCR_DLAB); 2165 /* 2166 * Only set the divisor registers if they would change, 2167 * since on some 16550 incompatibles (UMC8669F), setting 2168 * them while input is arriving them loses sync until 2169 * data stops arriving. 2170 */ 2171 dlbl = divisor & 0xFF; 2172 if (inb(iobase + com_dlbl) != dlbl) 2173 outb(iobase + com_dlbl, dlbl); 2174 dlbh = (u_int) divisor >> 8; 2175 if (inb(iobase + com_dlbh) != dlbh) 2176 outb(iobase + com_dlbh, dlbh); 2177 } 2178 2179 2180 outb(iobase + com_cfcr, com->cfcr_image = cfcr); 2181 2182 if (!(tp->t_state & TS_TTSTOP)) 2183 com->state |= CS_TTGO; 2184 2185 if (cflag & CRTS_IFLOW) { 2186 if (com->st16650a) { 2187 outb(iobase + com_cfcr, 0xbf); 2188 outb(iobase + com_fifo, inb(iobase + com_fifo) | 0x40); 2189 } 2190 com->state |= CS_RTS_IFLOW; 2191 /* 2192 * If CS_RTS_IFLOW just changed from off to on, the change 2193 * needs to be propagated to MCR_RTS. This isn't urgent, 2194 * so do it later by calling comstart() instead of repeating 2195 * a lot of code from comstart() here. 2196 */ 2197 } else if (com->state & CS_RTS_IFLOW) { 2198 com->state &= ~CS_RTS_IFLOW; 2199 /* 2200 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS 2201 * on here, since comstart() won't do it later. 2202 */ 2203 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2204 if (com->st16650a) { 2205 outb(iobase + com_cfcr, 0xbf); 2206 outb(iobase + com_fifo, inb(iobase + com_fifo) & ~0x40); 2207 } 2208 } 2209 2210 2211 /* 2212 * Set up state to handle output flow control. 2213 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level? 2214 * Now has 10+ msec latency, while CTS flow has 50- usec latency. 2215 */ 2216 com->state |= CS_ODEVREADY; 2217 com->state &= ~CS_CTS_OFLOW; 2218 if (cflag & CCTS_OFLOW) { 2219 com->state |= CS_CTS_OFLOW; 2220 if (!(com->last_modem_status & MSR_CTS)) 2221 com->state &= ~CS_ODEVREADY; 2222 if (com->st16650a) { 2223 outb(iobase + com_cfcr, 0xbf); 2224 outb(iobase + com_fifo, inb(iobase + com_fifo) | 0x80); 2225 } 2226 } else { 2227 if (com->st16650a) { 2228 outb(iobase + com_cfcr, 0xbf); 2229 outb(iobase + com_fifo, inb(iobase + com_fifo) & ~0x80); 2230 } 2231 } 2232 2233 2234 outb(iobase + com_cfcr, com->cfcr_image); 2235 2236 2237 /* XXX shouldn't call functions while intrs are disabled. */ 2238 disc_optim(tp, t, com); 2239 /* 2240 * Recover from fiddling with CS_TTGO. We used to call siointr1() 2241 * unconditionally, but that defeated the careful discarding of 2242 * stale input in sioopen(). 2243 */ 2244 if (com->state >= (CS_BUSY | CS_TTGO)) 2245 siointr1(com); 2246 2247 enable_intr(); 2248 splx(s); 2249 comstart(tp); 2250 if (com->ibufold != NULL) { 2251 free(com->ibufold, M_DEVBUF); 2252 com->ibufold = NULL; 2253 } 2254 return (0); 2255} 2256 2257static int 2258siosetwater(com, speed) 2259 struct com_s *com; 2260 speed_t speed; 2261{ 2262 int cp4ticks; 2263 u_char *ibuf; 2264 int ibufsize; 2265 struct tty *tp; 2266 2267 /* 2268 * Make the buffer size large enough to handle a softtty interrupt 2269 * latency of about 2 ticks without loss of throughput or data 2270 * (about 3 ticks if input flow control is not used or not honoured, 2271 * but a bit less for CS5-CS7 modes). 2272 */ 2273 cp4ticks = speed / 10 / hz * 4; 2274 for (ibufsize = 128; ibufsize < cp4ticks;) 2275 ibufsize <<= 1; 2276 if (ibufsize == com->ibufsize) { 2277 disable_intr(); 2278 return (0); 2279 } 2280 2281 /* 2282 * Allocate input buffer. The extra factor of 2 in the size is 2283 * to allow for an error byte for each input byte. 2284 */ 2285 ibuf = malloc(2 * ibufsize, M_DEVBUF, M_NOWAIT); 2286 if (ibuf == NULL) { 2287 disable_intr(); 2288 return (ENOMEM); 2289 } 2290 2291 /* Initialize non-critical variables. */ 2292 com->ibufold = com->ibuf; 2293 com->ibufsize = ibufsize; 2294 tp = com->tp; 2295 if (tp != NULL) { 2296 tp->t_ififosize = 2 * ibufsize; 2297 tp->t_ispeedwat = (speed_t)-1; 2298 tp->t_ospeedwat = (speed_t)-1; 2299 } 2300 2301 /* 2302 * Read current input buffer, if any. Continue with interrupts 2303 * disabled. 2304 */ 2305 disable_intr(); 2306 if (com->iptr != com->ibuf) 2307 sioinput(com); 2308 2309 /*- 2310 * Initialize critical variables, including input buffer watermarks. 2311 * The external device is asked to stop sending when the buffer 2312 * exactly reaches high water, or when the high level requests it. 2313 * The high level is notified immediately (rather than at a later 2314 * clock tick) when this watermark is reached. 2315 * The buffer size is chosen so the watermark should almost never 2316 * be reached. 2317 * The low watermark is invisibly 0 since the buffer is always 2318 * emptied all at once. 2319 */ 2320 com->iptr = com->ibuf = ibuf; 2321 com->ibufend = ibuf + ibufsize; 2322 com->ierroff = ibufsize; 2323 com->ihighwater = ibuf + 3 * ibufsize / 4; 2324 return (0); 2325} 2326 2327static void 2328comstart(tp) 2329 struct tty *tp; 2330{ 2331 struct com_s *com; 2332 int s; 2333 int unit; 2334 2335 unit = DEV_TO_UNIT(tp->t_dev); 2336 com = com_addr(unit); 2337 s = spltty(); 2338 disable_intr(); 2339 if (tp->t_state & TS_TTSTOP) 2340 com->state &= ~CS_TTGO; 2341 else 2342 com->state |= CS_TTGO; 2343 if (tp->t_state & TS_TBLOCK) { 2344 if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW) 2345 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS); 2346 } else { 2347 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater 2348 && com->state & CS_RTS_IFLOW) 2349 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2350 } 2351 enable_intr(); 2352 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) { 2353 ttwwakeup(tp); 2354 splx(s); 2355 return; 2356 } 2357 if (tp->t_outq.c_cc != 0) { 2358 struct lbq *qp; 2359 struct lbq *next; 2360 2361 if (!com->obufs[0].l_queued) { 2362 com->obufs[0].l_tail 2363 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1, 2364 sizeof com->obuf1); 2365 com->obufs[0].l_next = NULL; 2366 com->obufs[0].l_queued = TRUE; 2367 disable_intr(); 2368 if (com->state & CS_BUSY) { 2369 qp = com->obufq.l_next; 2370 while ((next = qp->l_next) != NULL) 2371 qp = next; 2372 qp->l_next = &com->obufs[0]; 2373 } else { 2374 com->obufq.l_head = com->obufs[0].l_head; 2375 com->obufq.l_tail = com->obufs[0].l_tail; 2376 com->obufq.l_next = &com->obufs[0]; 2377 com->state |= CS_BUSY; 2378 } 2379 enable_intr(); 2380 } 2381 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) { 2382 com->obufs[1].l_tail 2383 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2, 2384 sizeof com->obuf2); 2385 com->obufs[1].l_next = NULL; 2386 com->obufs[1].l_queued = TRUE; 2387 disable_intr(); 2388 if (com->state & CS_BUSY) { 2389 qp = com->obufq.l_next; 2390 while ((next = qp->l_next) != NULL) 2391 qp = next; 2392 qp->l_next = &com->obufs[1]; 2393 } else { 2394 com->obufq.l_head = com->obufs[1].l_head; 2395 com->obufq.l_tail = com->obufs[1].l_tail; 2396 com->obufq.l_next = &com->obufs[1]; 2397 com->state |= CS_BUSY; 2398 } 2399 enable_intr(); 2400 } 2401 tp->t_state |= TS_BUSY; 2402 } 2403 disable_intr(); 2404 if (com->state >= (CS_BUSY | CS_TTGO)) 2405 siointr1(com); /* fake interrupt to start output */ 2406 enable_intr(); 2407 ttwwakeup(tp); 2408 splx(s); 2409} 2410 2411static void 2412comstop(tp, rw) 2413 struct tty *tp; 2414 int rw; 2415{ 2416 struct com_s *com; 2417 2418 com = com_addr(DEV_TO_UNIT(tp->t_dev)); 2419 if (com->gone) 2420 return; 2421 disable_intr(); 2422 if (rw & FWRITE) { 2423 if (com->hasfifo) 2424#ifdef COM_ESP 2425 /* XXX avoid h/w bug. */ 2426 if (!com->esp) 2427#endif 2428 outb(com->iobase + com_fifo, 2429 FIFO_XMT_RST | com->fifo_image); 2430 com->obufs[0].l_queued = FALSE; 2431 com->obufs[1].l_queued = FALSE; 2432 if (com->state & CS_ODONE) 2433 com_events -= LOTS_OF_EVENTS; 2434 com->state &= ~(CS_ODONE | CS_BUSY); 2435 com->tp->t_state &= ~TS_BUSY; 2436 } 2437 if (rw & FREAD) { 2438 if (com->hasfifo) 2439#ifdef COM_ESP 2440 /* XXX avoid h/w bug. */ 2441 if (!com->esp) 2442#endif 2443 outb(com->iobase + com_fifo, 2444 FIFO_RCV_RST | com->fifo_image); 2445 com_events -= (com->iptr - com->ibuf); 2446 com->iptr = com->ibuf; 2447 } 2448 enable_intr(); 2449 comstart(tp); 2450} 2451 2452static int 2453commctl(com, bits, how) 2454 struct com_s *com; 2455 int bits; 2456 int how; 2457{ 2458 int mcr; 2459 int msr; 2460 2461 if (how == DMGET) { 2462 bits = TIOCM_LE; /* XXX - always enabled while open */ 2463 mcr = com->mcr_image; 2464 if (mcr & MCR_DTR) 2465 bits |= TIOCM_DTR; 2466 if (mcr & MCR_RTS) 2467 bits |= TIOCM_RTS; 2468 msr = com->prev_modem_status; 2469 if (msr & MSR_CTS) 2470 bits |= TIOCM_CTS; 2471 if (msr & MSR_DCD) 2472 bits |= TIOCM_CD; 2473 if (msr & MSR_DSR) 2474 bits |= TIOCM_DSR; 2475 /* 2476 * XXX - MSR_RI is naturally volatile, and we make MSR_TERI 2477 * more volatile by reading the modem status a lot. Perhaps 2478 * we should latch both bits until the status is read here. 2479 */ 2480 if (msr & (MSR_RI | MSR_TERI)) 2481 bits |= TIOCM_RI; 2482 return (bits); 2483 } 2484 mcr = 0; 2485 if (bits & TIOCM_DTR) 2486 mcr |= MCR_DTR; 2487 if (bits & TIOCM_RTS) 2488 mcr |= MCR_RTS; 2489 if (com->gone) 2490 return(0); 2491 disable_intr(); 2492 switch (how) { 2493 case DMSET: 2494 outb(com->modem_ctl_port, 2495 com->mcr_image = mcr | (com->mcr_image & MCR_IENABLE)); 2496 break; 2497 case DMBIS: 2498 outb(com->modem_ctl_port, com->mcr_image |= mcr); 2499 break; 2500 case DMBIC: 2501 outb(com->modem_ctl_port, com->mcr_image &= ~mcr); 2502 break; 2503 } 2504 enable_intr(); 2505 return (0); 2506} 2507 2508static void 2509siosettimeout() 2510{ 2511 struct com_s *com; 2512 bool_t someopen; 2513 int unit; 2514 2515 /* 2516 * Set our timeout period to 1 second if no polled devices are open. 2517 * Otherwise set it to max(1/200, 1/hz). 2518 * Enable timeouts iff some device is open. 2519 */ 2520 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 2521 sio_timeout = hz; 2522 someopen = FALSE; 2523 for (unit = 0; unit < sio_numunits; ++unit) { 2524 com = com_addr(unit); 2525 if (com != NULL && com->tp != NULL 2526 && com->tp->t_state & TS_ISOPEN && !com->gone) { 2527 someopen = TRUE; 2528 if (com->poll || com->poll_output) { 2529 sio_timeout = hz > 200 ? hz / 200 : 1; 2530 break; 2531 } 2532 } 2533 } 2534 if (someopen) { 2535 sio_timeouts_until_log = hz / sio_timeout; 2536 sio_timeout_handle = timeout(comwakeup, (void *)NULL, 2537 sio_timeout); 2538 } else { 2539 /* Flush error messages, if any. */ 2540 sio_timeouts_until_log = 1; 2541 comwakeup((void *)NULL); 2542 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 2543 } 2544} 2545 2546static void 2547comwakeup(chan) 2548 void *chan; 2549{ 2550 struct com_s *com; 2551 int unit; 2552 2553 sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout); 2554 2555 /* 2556 * Recover from lost output interrupts. 2557 * Poll any lines that don't use interrupts. 2558 */ 2559 for (unit = 0; unit < sio_numunits; ++unit) { 2560 com = com_addr(unit); 2561 if (com != NULL && !com->gone 2562 && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) { 2563 disable_intr(); 2564 siointr1(com); 2565 enable_intr(); 2566 } 2567 } 2568 2569 /* 2570 * Check for and log errors, but not too often. 2571 */ 2572 if (--sio_timeouts_until_log > 0) 2573 return; 2574 sio_timeouts_until_log = hz / sio_timeout; 2575 for (unit = 0; unit < sio_numunits; ++unit) { 2576 int errnum; 2577 2578 com = com_addr(unit); 2579 if (com == NULL) 2580 continue; 2581 if (com->gone) 2582 continue; 2583 for (errnum = 0; errnum < CE_NTYPES; ++errnum) { 2584 u_int delta; 2585 u_long total; 2586 2587 disable_intr(); 2588 delta = com->delta_error_counts[errnum]; 2589 com->delta_error_counts[errnum] = 0; 2590 enable_intr(); 2591 if (delta == 0) 2592 continue; 2593 total = com->error_counts[errnum] += delta; 2594 log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n", 2595 unit, delta, error_desc[errnum], 2596 delta == 1 ? "" : "s", total); 2597 } 2598 } 2599} 2600 2601static void 2602disc_optim(tp, t, com) 2603 struct tty *tp; 2604 struct termios *t; 2605 struct com_s *com; 2606{ 2607 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON)) 2608 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK)) 2609 && (!(t->c_iflag & PARMRK) 2610 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK)) 2611 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN)) 2612 && linesw[tp->t_line].l_rint == ttyinput) 2613 tp->t_state |= TS_CAN_BYPASS_L_RINT; 2614 else 2615 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 2616 com->hotchar = linesw[tp->t_line].l_hotchar; 2617} 2618 2619/* 2620 * Following are all routines needed for SIO to act as console 2621 */ 2622#include <sys/cons.h> 2623 2624struct siocnstate { 2625 u_char dlbl; 2626 u_char dlbh; 2627 u_char ier; 2628 u_char cfcr; 2629 u_char mcr; 2630}; 2631 2632static speed_t siocngetspeed __P((Port_t, struct speedtab *)); 2633static void siocnclose __P((struct siocnstate *sp, Port_t iobase)); 2634static void siocnopen __P((struct siocnstate *sp, Port_t iobase, int speed)); 2635static void siocntxwait __P((Port_t iobase)); 2636 2637static cn_probe_t siocnprobe; 2638static cn_init_t siocninit; 2639static cn_checkc_t siocncheckc; 2640static cn_getc_t siocngetc; 2641static cn_putc_t siocnputc; 2642 2643#ifdef __i386__ 2644CONS_DRIVER(sio, siocnprobe, siocninit, NULL, siocngetc, siocncheckc, siocnputc); 2645 2646#endif 2647 2648/* To get the GDB related variables */ 2649#if DDB > 0 2650#include <ddb/ddb.h> 2651#endif 2652 2653static void 2654siocntxwait(iobase) 2655 Port_t iobase; 2656{ 2657 int timo; 2658 2659 /* 2660 * Wait for any pending transmission to finish. Required to avoid 2661 * the UART lockup bug when the speed is changed, and for normal 2662 * transmits. 2663 */ 2664 timo = 100000; 2665 while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY)) 2666 != (LSR_TSRE | LSR_TXRDY) && --timo != 0) 2667 ; 2668} 2669 2670/* 2671 * Read the serial port specified and try to figure out what speed 2672 * it's currently running at. We're assuming the serial port has 2673 * been initialized and is basicly idle. This routine is only intended 2674 * to be run at system startup. 2675 * 2676 * If the value read from the serial port doesn't make sense, return 0. 2677 */ 2678 2679static speed_t 2680siocngetspeed(iobase, table) 2681 Port_t iobase; 2682 struct speedtab *table; 2683{ 2684 int code; 2685 u_char dlbh; 2686 u_char dlbl; 2687 u_char cfcr; 2688 2689 cfcr = inb(iobase + com_cfcr); 2690 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 2691 2692 dlbl = inb(iobase + com_dlbl); 2693 dlbh = inb(iobase + com_dlbh); 2694 2695 outb(iobase + com_cfcr, cfcr); 2696 2697 code = dlbh << 8 | dlbl; 2698 2699 for (; table->sp_speed != -1; table++) 2700 if (table->sp_code == code) 2701 return (table->sp_speed); 2702 2703 return 0; /* didn't match anything sane */ 2704} 2705 2706static void 2707siocnopen(sp, iobase, speed) 2708 struct siocnstate *sp; 2709 Port_t iobase; 2710 int speed; 2711{ 2712 int divisor; 2713 u_char dlbh; 2714 u_char dlbl; 2715 2716 /* 2717 * Save all the device control registers except the fifo register 2718 * and set our default ones (cs8 -parenb speed=comdefaultrate). 2719 * We can't save the fifo register since it is read-only. 2720 */ 2721 sp->ier = inb(iobase + com_ier); 2722 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */ 2723 siocntxwait(iobase); 2724 sp->cfcr = inb(iobase + com_cfcr); 2725 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 2726 sp->dlbl = inb(iobase + com_dlbl); 2727 sp->dlbh = inb(iobase + com_dlbh); 2728 /* 2729 * Only set the divisor registers if they would change, since on 2730 * some 16550 incompatibles (Startech), setting them clears the 2731 * data input register. This also reduces the effects of the 2732 * UMC8669F bug. 2733 */ 2734 divisor = ttspeedtab(speed, comspeedtab); 2735 dlbl = divisor & 0xFF; 2736 if (sp->dlbl != dlbl) 2737 outb(iobase + com_dlbl, dlbl); 2738 dlbh = (u_int) divisor >> 8; 2739 if (sp->dlbh != dlbh) 2740 outb(iobase + com_dlbh, dlbh); 2741 outb(iobase + com_cfcr, CFCR_8BITS); 2742 sp->mcr = inb(iobase + com_mcr); 2743 /* 2744 * We don't want interrupts, but must be careful not to "disable" 2745 * them by clearing the MCR_IENABLE bit, since that might cause 2746 * an interrupt by floating the IRQ line. 2747 */ 2748 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS); 2749} 2750 2751static void 2752siocnclose(sp, iobase) 2753 struct siocnstate *sp; 2754 Port_t iobase; 2755{ 2756 /* 2757 * Restore the device control registers. 2758 */ 2759 siocntxwait(iobase); 2760 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 2761 if (sp->dlbl != inb(iobase + com_dlbl)) 2762 outb(iobase + com_dlbl, sp->dlbl); 2763 if (sp->dlbh != inb(iobase + com_dlbh)) 2764 outb(iobase + com_dlbh, sp->dlbh); 2765 outb(iobase + com_cfcr, sp->cfcr); 2766 /* 2767 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them. 2768 */ 2769 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS); 2770 outb(iobase + com_ier, sp->ier); 2771} 2772 2773static void 2774siocnprobe(cp) 2775 struct consdev *cp; 2776{ 2777 speed_t boot_speed; 2778 u_char cfcr; 2779 int s, unit; 2780 struct siocnstate sp; 2781 2782 /* 2783 * Find our first enabled console, if any. If it is a high-level 2784 * console device, then initialize it and return successfully. 2785 * If it is a low-level console device, then initialize it and 2786 * return unsuccessfully. It must be initialized in both cases 2787 * for early use by console drivers and debuggers. Initializing 2788 * the hardware is not necessary in all cases, since the i/o 2789 * routines initialize it on the fly, but it is necessary if 2790 * input might arrive while the hardware is switched back to an 2791 * uninitialized state. We can't handle multiple console devices 2792 * yet because our low-level routines don't take a device arg. 2793 * We trust the user to set the console flags properly so that we 2794 * don't need to probe. 2795 */ 2796 cp->cn_pri = CN_DEAD; 2797 2798 for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */ 2799 int flags; 2800 int disabled; 2801 if (resource_int_value("sio", unit, "disabled", &disabled) == 0) { 2802 if (disabled) 2803 continue; 2804 } 2805 if (resource_int_value("sio", unit, "flags", &flags)) 2806 continue; 2807 if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) { 2808 int port; 2809 Port_t iobase; 2810 2811 if (resource_int_value("sio", unit, "port", &port)) 2812 continue; 2813 iobase = port; 2814 s = spltty(); 2815 if (boothowto & RB_SERIAL) { 2816 boot_speed = siocngetspeed(iobase, comspeedtab); 2817 if (boot_speed) 2818 comdefaultrate = boot_speed; 2819 } 2820 2821 /* 2822 * Initialize the divisor latch. We can't rely on 2823 * siocnopen() to do this the first time, since it 2824 * avoids writing to the latch if the latch appears 2825 * to have the correct value. Also, if we didn't 2826 * just read the speed from the hardware, then we 2827 * need to set the speed in hardware so that 2828 * switching it later is null. 2829 */ 2830 cfcr = inb(iobase + com_cfcr); 2831 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 2832 outb(iobase + com_dlbl, 2833 COMBRD(comdefaultrate) & 0xff); 2834 outb(iobase + com_dlbh, 2835 (u_int) COMBRD(comdefaultrate) >> 8); 2836 outb(iobase + com_cfcr, cfcr); 2837 2838 siocnopen(&sp, iobase, comdefaultrate); 2839 2840 splx(s); 2841 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) { 2842 cp->cn_dev = makedev(CDEV_MAJOR, unit); 2843 cp->cn_pri = COM_FORCECONSOLE(flags) 2844 || boothowto & RB_SERIAL 2845 ? CN_REMOTE : CN_NORMAL; 2846 siocniobase = iobase; 2847 siocnunit = unit; 2848 } 2849 if (COM_DEBUGGER(flags)) { 2850 printf("sio%d: gdb debugging port\n", unit); 2851 siogdbiobase = iobase; 2852 siogdbunit = unit; 2853#if DDB > 0 2854 gdbdev = makedev(CDEV_MAJOR, unit); 2855 gdb_getc = siocngetc; 2856 gdb_putc = siocnputc; 2857#endif 2858 } 2859 } 2860 } 2861#ifdef __i386__ 2862#if DDB > 0 2863 /* 2864 * XXX Ugly Compatability. 2865 * If no gdb port has been specified, set it to be the console 2866 * as some configuration files don't specify the gdb port. 2867 */ 2868 if (gdbdev == NODEV && (boothowto & RB_GDB)) { 2869 printf("Warning: no GDB port specified. Defaulting to sio%d.\n", 2870 siocnunit); 2871 printf("Set flag 0x80 on desired GDB port in your\n"); 2872 printf("configuration file (currently sio only).\n"); 2873 siogdbiobase = siocniobase; 2874 siogdbunit = siocnunit; 2875 gdbdev = makedev(CDEV_MAJOR, siocnunit); 2876 gdb_getc = siocngetc; 2877 gdb_putc = siocnputc; 2878 } 2879#endif 2880#endif 2881} 2882 2883#ifdef __alpha__ 2884 2885CONS_DRIVER(sio, NULL, NULL, NULL, siocngetc, siocncheckc, siocnputc); 2886 2887int 2888siocnattach(port, speed) 2889 int port; 2890 int speed; 2891{ 2892 int s; 2893 u_char cfcr; 2894 struct siocnstate sp; 2895 2896 siocniobase = port; 2897 comdefaultrate = speed; 2898 sio_consdev.cn_pri = CN_NORMAL; 2899 sio_consdev.cn_dev = makedev(CDEV_MAJOR, 0); 2900 2901 s = spltty(); 2902 2903 /* 2904 * Initialize the divisor latch. We can't rely on 2905 * siocnopen() to do this the first time, since it 2906 * avoids writing to the latch if the latch appears 2907 * to have the correct value. Also, if we didn't 2908 * just read the speed from the hardware, then we 2909 * need to set the speed in hardware so that 2910 * switching it later is null. 2911 */ 2912 cfcr = inb(siocniobase + com_cfcr); 2913 outb(siocniobase + com_cfcr, CFCR_DLAB | cfcr); 2914 outb(siocniobase + com_dlbl, 2915 COMBRD(comdefaultrate) & 0xff); 2916 outb(siocniobase + com_dlbh, 2917 (u_int) COMBRD(comdefaultrate) >> 8); 2918 outb(siocniobase + com_cfcr, cfcr); 2919 2920 siocnopen(&sp, siocniobase, comdefaultrate); 2921 splx(s); 2922 2923 cn_tab = &sio_consdev; 2924 return 0; 2925} 2926 2927int 2928siogdbattach(port, speed) 2929 int port; 2930 int speed; 2931{ 2932 int s; 2933 u_char cfcr; 2934 struct siocnstate sp; 2935 2936 siogdbiobase = port; 2937 gdbdefaultrate = speed; 2938 2939 s = spltty(); 2940 2941 /* 2942 * Initialize the divisor latch. We can't rely on 2943 * siocnopen() to do this the first time, since it 2944 * avoids writing to the latch if the latch appears 2945 * to have the correct value. Also, if we didn't 2946 * just read the speed from the hardware, then we 2947 * need to set the speed in hardware so that 2948 * switching it later is null. 2949 */ 2950 cfcr = inb(siogdbiobase + com_cfcr); 2951 outb(siogdbiobase + com_cfcr, CFCR_DLAB | cfcr); 2952 outb(siogdbiobase + com_dlbl, 2953 COMBRD(gdbdefaultrate) & 0xff); 2954 outb(siogdbiobase + com_dlbh, 2955 (u_int) COMBRD(gdbdefaultrate) >> 8); 2956 outb(siogdbiobase + com_cfcr, cfcr); 2957 2958 siocnopen(&sp, siogdbiobase, gdbdefaultrate); 2959 splx(s); 2960 2961 return 0; 2962} 2963 2964#endif 2965 2966static void 2967siocninit(cp) 2968 struct consdev *cp; 2969{ 2970 comconsole = DEV_TO_UNIT(cp->cn_dev); 2971} 2972 2973static int 2974siocncheckc(dev) 2975 dev_t dev; 2976{ 2977 int c; 2978 Port_t iobase; 2979 int s; 2980 struct siocnstate sp; 2981 2982 if (minor(dev) == siogdbunit) 2983 iobase = siogdbiobase; 2984 else 2985 iobase = siocniobase; 2986 s = spltty(); 2987 siocnopen(&sp, iobase, comdefaultrate); 2988 if (inb(iobase + com_lsr) & LSR_RXRDY) 2989 c = inb(iobase + com_data); 2990 else 2991 c = -1; 2992 siocnclose(&sp, iobase); 2993 splx(s); 2994 return (c); 2995} 2996 2997 2998int 2999siocngetc(dev) 3000 dev_t dev; 3001{ 3002 int c; 3003 Port_t iobase; 3004 int s; 3005 struct siocnstate sp; 3006 3007 if (minor(dev) == siogdbunit) 3008 iobase = siogdbiobase; 3009 else 3010 iobase = siocniobase; 3011 s = spltty(); 3012 siocnopen(&sp, iobase, comdefaultrate); 3013 while (!(inb(iobase + com_lsr) & LSR_RXRDY)) 3014 ; 3015 c = inb(iobase + com_data); 3016 siocnclose(&sp, iobase); 3017 splx(s); 3018 return (c); 3019} 3020 3021void 3022siocnputc(dev, c) 3023 dev_t dev; 3024 int c; 3025{ 3026 int s; 3027 struct siocnstate sp; 3028 Port_t iobase; 3029 3030 if (minor(dev) == siogdbunit) 3031 iobase = siogdbiobase; 3032 else 3033 iobase = siocniobase; 3034 s = spltty(); 3035 siocnopen(&sp, iobase, comdefaultrate); 3036 siocntxwait(iobase); 3037 outb(iobase + com_data, c); 3038 siocnclose(&sp, iobase); 3039 splx(s); 3040} 3041 3042#ifdef __alpha__ 3043int 3044siogdbgetc() 3045{ 3046 int c; 3047 Port_t iobase; 3048 int s; 3049 struct siocnstate sp; 3050 3051 iobase = siogdbiobase; 3052 s = spltty(); 3053 siocnopen(&sp, iobase, gdbdefaultrate); 3054 while (!(inb(iobase + com_lsr) & LSR_RXRDY)) 3055 ; 3056 c = inb(iobase + com_data); 3057 siocnclose(&sp, iobase); 3058 splx(s); 3059 return (c); 3060} 3061 3062void 3063siogdbputc(c) 3064 int c; 3065{ 3066 int s; 3067 struct siocnstate sp; 3068 3069 s = spltty(); 3070 siocnopen(&sp, siogdbiobase, gdbdefaultrate); 3071 siocntxwait(siogdbiobase); 3072 outb(siogdbiobase + com_data, c); 3073 siocnclose(&sp, siogdbiobase); 3074 splx(s); 3075} 3076#endif 3077 3078DRIVER_MODULE(sio, isa, sio_isa_driver, sio_devclass, 0, 0); 3079#if NCARD > 0 3080DRIVER_MODULE(sio, pccard, sio_pccard_driver, sio_devclass, 0, 0); 3081#endif 3082