sio.c revision 53344
1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by the University of 16 * California, Berkeley and its contributors. 17 * 4. Neither the name of the University nor the names of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/dev/sio/sio.c 53344 1999-11-18 07:22:41Z peter $ 34 * from: @(#)com.c 7.5 (Berkeley) 5/16/91 35 * from: i386/isa sio.c,v 1.234 36 */ 37 38#include "opt_comconsole.h" 39#include "opt_compat.h" 40#include "opt_ddb.h" 41#include "opt_sio.h" 42#include "sio.h" 43 44/* 45 * Serial driver, based on 386BSD-0.1 com driver. 46 * Mostly rewritten to use pseudo-DMA. 47 * Works for National Semiconductor NS8250-NS16550AF UARTs. 48 * COM driver, based on HP dca driver. 49 * 50 * Changes for PC-Card integration: 51 * - Added PC-Card driver table and handlers 52 */ 53#include <sys/param.h> 54#include <sys/systm.h> 55#include <sys/reboot.h> 56#include <sys/malloc.h> 57#include <sys/tty.h> 58#include <sys/proc.h> 59#include <sys/module.h> 60#include <sys/conf.h> 61#include <sys/dkstat.h> 62#include <sys/fcntl.h> 63#include <sys/interrupt.h> 64#include <sys/kernel.h> 65#include <sys/syslog.h> 66#include <sys/sysctl.h> 67#include <sys/bus.h> 68#include <machine/bus.h> 69#include <sys/rman.h> 70#include <sys/timepps.h> 71 72#include <isa/isareg.h> 73#include <isa/isavar.h> 74#include <machine/lock.h> 75 76#include <machine/clock.h> 77#include <machine/ipl.h> 78#ifndef SMP 79#include <machine/lock.h> 80#endif 81#include <machine/resource.h> 82 83#include <isa/sioreg.h> 84 85#ifdef COM_ESP 86#include <isa/ic/esp.h> 87#endif 88#include <isa/ic/ns16550.h> 89 90#include "card.h" 91#if NCARD > 0 92/* XXX should die XXX */ 93#include <sys/select.h> 94#include <sys/module.h> 95#include <pccard/cardinfo.h> 96#include <pccard/slot.h> 97#endif 98 99#ifndef __i386__ 100#define disable_intr() 101#define enable_intr() 102#endif 103 104#ifdef SMP 105#define disable_intr() COM_DISABLE_INTR() 106#define enable_intr() COM_ENABLE_INTR() 107#endif /* SMP */ 108 109#define LOTS_OF_EVENTS 64 /* helps separate urgent events from input */ 110 111#define CALLOUT_MASK 0x80 112#define CONTROL_MASK 0x60 113#define CONTROL_INIT_STATE 0x20 114#define CONTROL_LOCK_STATE 0x40 115#define DEV_TO_UNIT(dev) (MINOR_TO_UNIT(minor(dev))) 116#define MINOR_MAGIC_MASK (CALLOUT_MASK | CONTROL_MASK) 117#define MINOR_TO_UNIT(mynor) ((mynor) & ~MINOR_MAGIC_MASK) 118 119#ifdef COM_MULTIPORT 120/* checks in flags for multiport and which is multiport "master chip" 121 * for a given card 122 */ 123#define COM_ISMULTIPORT(flags) ((flags) & 0x01) 124#define COM_MPMASTER(flags) (((flags) >> 8) & 0x0ff) 125#define COM_NOTAST4(flags) ((flags) & 0x04) 126#endif /* COM_MULTIPORT */ 127 128#define COM_CONSOLE(flags) ((flags) & 0x10) 129#define COM_FORCECONSOLE(flags) ((flags) & 0x20) 130#define COM_LLCONSOLE(flags) ((flags) & 0x40) 131#define COM_DEBUGGER(flags) ((flags) & 0x80) 132#define COM_LOSESOUTINTS(flags) ((flags) & 0x08) 133#define COM_NOFIFO(flags) ((flags) & 0x02) 134#define COM_ST16650A(flags) ((flags) & 0x20000) 135#define COM_C_NOPROBE (0x40000) 136#define COM_NOPROBE(flags) ((flags) & COM_C_NOPROBE) 137#define COM_C_IIR_TXRDYBUG (0x80000) 138#define COM_IIR_TXRDYBUG(flags) ((flags) & COM_C_IIR_TXRDYBUG) 139#define COM_FIFOSIZE(flags) (((flags) & 0xff000000) >> 24) 140 141#define com_scr 7 /* scratch register for 16450-16550 (R/W) */ 142 143/* 144 * com state bits. 145 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher 146 * than the other bits so that they can be tested as a group without masking 147 * off the low bits. 148 * 149 * The following com and tty flags correspond closely: 150 * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and 151 * comstop()) 152 * CS_TTGO = ~TS_TTSTOP (maintained by comparam() and comstart()) 153 * CS_CTS_OFLOW = CCTS_OFLOW (maintained by comparam()) 154 * CS_RTS_IFLOW = CRTS_IFLOW (maintained by comparam()) 155 * TS_FLUSH is not used. 156 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON. 157 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state). 158 */ 159#define CS_BUSY 0x80 /* output in progress */ 160#define CS_TTGO 0x40 /* output not stopped by XOFF */ 161#define CS_ODEVREADY 0x20 /* external device h/w ready (CTS) */ 162#define CS_CHECKMSR 1 /* check of MSR scheduled */ 163#define CS_CTS_OFLOW 2 /* use CTS output flow control */ 164#define CS_DTR_OFF 0x10 /* DTR held off */ 165#define CS_ODONE 4 /* output completed */ 166#define CS_RTS_IFLOW 8 /* use RTS input flow control */ 167#define CSE_BUSYCHECK 1 /* siobusycheck() scheduled */ 168 169static char const * const error_desc[] = { 170#define CE_OVERRUN 0 171 "silo overflow", 172#define CE_INTERRUPT_BUF_OVERFLOW 1 173 "interrupt-level buffer overflow", 174#define CE_TTY_BUF_OVERFLOW 2 175 "tty-level buffer overflow", 176}; 177 178#define CE_NTYPES 3 179#define CE_RECORD(com, errnum) (++(com)->delta_error_counts[errnum]) 180 181/* types. XXX - should be elsewhere */ 182typedef u_int Port_t; /* hardware port */ 183typedef u_char bool_t; /* boolean */ 184 185/* queue of linear buffers */ 186struct lbq { 187 u_char *l_head; /* next char to process */ 188 u_char *l_tail; /* one past the last char to process */ 189 struct lbq *l_next; /* next in queue */ 190 bool_t l_queued; /* nonzero if queued */ 191}; 192 193/* com device structure */ 194struct com_s { 195 u_int flags; /* Copy isa device flags */ 196 u_char state; /* miscellaneous flag bits */ 197 bool_t active_out; /* nonzero if the callout device is open */ 198 u_char cfcr_image; /* copy of value written to CFCR */ 199#ifdef COM_ESP 200 bool_t esp; /* is this unit a hayes esp board? */ 201#endif 202 u_char extra_state; /* more flag bits, separate for order trick */ 203 u_char fifo_image; /* copy of value written to FIFO */ 204 bool_t hasfifo; /* nonzero for 16550 UARTs */ 205 bool_t st16650a; /* Is a Startech 16650A or RTS/CTS compat */ 206 bool_t loses_outints; /* nonzero if device loses output interrupts */ 207 u_char mcr_image; /* copy of value written to MCR */ 208#ifdef COM_MULTIPORT 209 bool_t multiport; /* is this unit part of a multiport device? */ 210#endif /* COM_MULTIPORT */ 211 bool_t no_irq; /* nonzero if irq is not attached */ 212 bool_t gone; /* hardware disappeared */ 213 bool_t poll; /* nonzero if polling is required */ 214 bool_t poll_output; /* nonzero if polling for output is required */ 215 int unit; /* unit number */ 216 int dtr_wait; /* time to hold DTR down on close (* 1/hz) */ 217 u_int tx_fifo_size; 218 u_int wopeners; /* # processes waiting for DCD in open() */ 219 220 /* 221 * The high level of the driver never reads status registers directly 222 * because there would be too many side effects to handle conveniently. 223 * Instead, it reads copies of the registers stored here by the 224 * interrupt handler. 225 */ 226 u_char last_modem_status; /* last MSR read by intr handler */ 227 u_char prev_modem_status; /* last MSR handled by high level */ 228 229 u_char hotchar; /* ldisc-specific char to be handled ASAP */ 230 u_char *ibuf; /* start of input buffer */ 231 u_char *ibufend; /* end of input buffer */ 232 u_char *ibufold; /* old input buffer, to be freed */ 233 u_char *ihighwater; /* threshold in input buffer */ 234 u_char *iptr; /* next free spot in input buffer */ 235 int ibufsize; /* size of ibuf (not include error bytes) */ 236 int ierroff; /* offset of error bytes in ibuf */ 237 238 struct lbq obufq; /* head of queue of output buffers */ 239 struct lbq obufs[2]; /* output buffers */ 240 241 Port_t data_port; /* i/o ports */ 242#ifdef COM_ESP 243 Port_t esp_port; 244#endif 245 Port_t int_id_port; 246 Port_t iobase; 247 Port_t modem_ctl_port; 248 Port_t line_status_port; 249 Port_t modem_status_port; 250 Port_t intr_ctl_port; /* Ports of IIR register */ 251 252 struct tty *tp; /* cross reference */ 253 254 /* Initial state. */ 255 struct termios it_in; /* should be in struct tty */ 256 struct termios it_out; 257 258 /* Lock state. */ 259 struct termios lt_in; /* should be in struct tty */ 260 struct termios lt_out; 261 262 bool_t do_timestamp; 263 bool_t do_dcd_timestamp; 264 struct timeval timestamp; 265 struct timeval dcd_timestamp; 266 struct pps_state pps; 267 268 u_long bytes_in; /* statistics */ 269 u_long bytes_out; 270 u_int delta_error_counts[CE_NTYPES]; 271 u_long error_counts[CE_NTYPES]; 272 273 struct resource *irqres; 274 struct resource *ioportres; 275 276 /* 277 * Data area for output buffers. Someday we should build the output 278 * buffer queue without copying data. 279 */ 280 u_char obuf1[256]; 281 u_char obuf2[256]; 282}; 283 284#ifdef COM_ESP 285static int espattach __P((struct com_s *com, Port_t esp_port)); 286#endif 287static int sioattach __P((device_t dev)); 288static int sio_isa_attach __P((device_t dev)); 289 290static timeout_t siobusycheck; 291static timeout_t siodtrwakeup; 292static void comhardclose __P((struct com_s *com)); 293static void sioinput __P((struct com_s *com)); 294static void siointr1 __P((struct com_s *com)); 295static void siointr __P((void *arg)); 296static int commctl __P((struct com_s *com, int bits, int how)); 297static int comparam __P((struct tty *tp, struct termios *t)); 298static swihand_t siopoll; 299static int sioprobe __P((device_t dev)); 300static int sio_isa_probe __P((device_t dev)); 301static void siosettimeout __P((void)); 302static int siosetwater __P((struct com_s *com, speed_t speed)); 303static void comstart __P((struct tty *tp)); 304static void comstop __P((struct tty *tp, int rw)); 305static timeout_t comwakeup; 306static void disc_optim __P((struct tty *tp, struct termios *t, 307 struct com_s *com)); 308 309#if NCARD > 0 310static int sio_pccard_attach __P((device_t dev)); 311static void sio_pccard_detach __P((device_t dev)); 312static int sio_pccard_probe __P((device_t dev)); 313#endif /* NCARD > 0 */ 314 315static char driver_name[] = "sio"; 316 317/* table and macro for fast conversion from a unit number to its com struct */ 318static devclass_t sio_devclass; 319#define com_addr(unit) ((struct com_s *) \ 320 devclass_get_softc(sio_devclass, unit)) 321 322static device_method_t sio_isa_methods[] = { 323 /* Device interface */ 324 DEVMETHOD(device_probe, sio_isa_probe), 325 DEVMETHOD(device_attach, sio_isa_attach), 326 327 { 0, 0 } 328}; 329 330static driver_t sio_isa_driver = { 331 driver_name, 332 sio_isa_methods, 333 sizeof(struct com_s), 334}; 335 336#if NCARD > 0 337static device_method_t sio_pccard_methods[] = { 338 /* Device interface */ 339 DEVMETHOD(device_probe, sio_pccard_probe), 340 DEVMETHOD(device_attach, sio_pccard_attach), 341 DEVMETHOD(device_detach, sio_pccard_detach), 342 343 { 0, 0 } 344}; 345 346static driver_t sio_pccard_driver = { 347 driver_name, 348 sio_pccard_methods, 349 sizeof(struct com_s), 350}; 351#endif (NCARD > 0) 352 353static d_open_t sioopen; 354static d_close_t sioclose; 355static d_read_t sioread; 356static d_write_t siowrite; 357static d_ioctl_t sioioctl; 358 359#define CDEV_MAJOR 28 360static struct cdevsw sio_cdevsw = { 361 /* open */ sioopen, 362 /* close */ sioclose, 363 /* read */ sioread, 364 /* write */ siowrite, 365 /* ioctl */ sioioctl, 366 /* poll */ ttypoll, 367 /* mmap */ nommap, 368 /* strategy */ nostrategy, 369 /* name */ driver_name, 370 /* maj */ CDEV_MAJOR, 371 /* dump */ nodump, 372 /* psize */ nopsize, 373 /* flags */ D_TTY, 374 /* bmaj */ -1 375}; 376 377int comconsole = -1; 378static volatile speed_t comdefaultrate = CONSPEED; 379#ifdef __alpha__ 380static volatile speed_t gdbdefaultrate = CONSPEED; 381#endif 382static u_int com_events; /* input chars + weighted output completions */ 383static Port_t siocniobase; 384static int siocnunit; 385static Port_t siogdbiobase; 386static int siogdbunit = -1; 387static bool_t sio_registered; 388static int sio_timeout; 389static int sio_timeouts_until_log; 390static struct callout_handle sio_timeout_handle 391 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle); 392static int sio_numunits; 393 394static struct speedtab comspeedtab[] = { 395 { 0, 0 }, 396 { 50, COMBRD(50) }, 397 { 75, COMBRD(75) }, 398 { 110, COMBRD(110) }, 399 { 134, COMBRD(134) }, 400 { 150, COMBRD(150) }, 401 { 200, COMBRD(200) }, 402 { 300, COMBRD(300) }, 403 { 600, COMBRD(600) }, 404 { 1200, COMBRD(1200) }, 405 { 1800, COMBRD(1800) }, 406 { 2400, COMBRD(2400) }, 407 { 4800, COMBRD(4800) }, 408 { 9600, COMBRD(9600) }, 409 { 19200, COMBRD(19200) }, 410 { 38400, COMBRD(38400) }, 411 { 57600, COMBRD(57600) }, 412 { 115200, COMBRD(115200) }, 413 { -1, -1 } 414}; 415 416#ifdef COM_ESP 417/* XXX configure this properly. */ 418static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, }; 419static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 }; 420#endif 421 422/* 423 * handle sysctl read/write requests for console speed 424 * 425 * In addition to setting comdefaultrate for I/O through /dev/console, 426 * also set the initial and lock values for the /dev/ttyXX device 427 * if there is one associated with the console. Finally, if the /dev/tty 428 * device has already been open, change the speed on the open running port 429 * itself. 430 */ 431 432static int 433sysctl_machdep_comdefaultrate SYSCTL_HANDLER_ARGS 434{ 435 int error, s; 436 speed_t newspeed; 437 struct com_s *com; 438 struct tty *tp; 439 440 newspeed = comdefaultrate; 441 442 error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req); 443 if (error || !req->newptr) 444 return (error); 445 446 comdefaultrate = newspeed; 447 448 if (comconsole < 0) /* serial console not selected? */ 449 return (0); 450 451 com = com_addr(comconsole); 452 if (!com) 453 return (ENXIO); 454 455 /* 456 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX 457 * (note, the lock rates really are boolean -- if non-zero, disallow 458 * speed changes) 459 */ 460 com->it_in.c_ispeed = com->it_in.c_ospeed = 461 com->lt_in.c_ispeed = com->lt_in.c_ospeed = 462 com->it_out.c_ispeed = com->it_out.c_ospeed = 463 com->lt_out.c_ispeed = com->lt_out.c_ospeed = comdefaultrate; 464 465 /* 466 * if we're open, change the running rate too 467 */ 468 tp = com->tp; 469 if (tp && (tp->t_state & TS_ISOPEN)) { 470 tp->t_termios.c_ispeed = 471 tp->t_termios.c_ospeed = comdefaultrate; 472 s = spltty(); 473 error = comparam(tp, &tp->t_termios); 474 splx(s); 475 } 476 return error; 477} 478 479SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW, 480 0, 0, sysctl_machdep_comdefaultrate, "I", ""); 481 482#define SET_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) | (bit)) 483#define CLR_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) & ~(bit)) 484 485#if NCARD > 0 486static int 487sio_pccard_probe(dev) 488 device_t dev; 489{ 490 const char *name; 491 492 name = pccard_get_name(dev); 493 if (strcmp(name, "sio")) 494 return ENXIO; 495 496 /* Do not probe IRQ - pccardd has not arranged for it yet */ 497 SET_FLAG(dev, COM_C_NOPROBE); 498 499 return (sioprobe(dev)); 500} 501 502static int 503sio_pccard_attach(dev) 504 device_t dev; 505{ 506 return (sioattach(dev)); 507} 508 509/* 510 * sio_detach - unload the driver and clear the table. 511 * XXX TODO: 512 * This is usually called when the card is ejected, but 513 * can be caused by a modunload of a controller driver. 514 * The idea is to reset the driver's view of the device 515 * and ensure that any driver entry points such as 516 * read and write do not hang. 517 */ 518static void 519sio_pccard_detach(dev) 520 device_t dev; 521{ 522 struct com_s *com; 523 524 com = (struct com_s *) device_get_softc(dev); 525 if (!com) { 526 device_printf(dev, "NULL com in siounload\n"); 527 return; 528 } 529 if (!com->iobase) { 530 device_printf(dev, "already unloaded!\n"); 531 return; 532 } 533 if (com->tp && (com->tp->t_state & TS_ISOPEN)) { 534 com->gone = 1; 535 device_printf(dev, "unload\n"); 536 com->tp->t_gen++; 537 ttyclose(com->tp); 538 ttwakeup(com->tp); 539 ttwwakeup(com->tp); 540 } else { 541 if (com->ibuf != NULL) 542 free(com->ibuf, M_DEVBUF); 543 free(com, M_DEVBUF); 544 device_printf(dev, "unload,gone\n"); 545 } 546} 547#endif /* NCARD > 0 */ 548 549 550static struct isa_pnp_id sio_ids[] = { 551 {0x0005d041, "Standard PC COM port"}, /* PNP0500 */ 552 {0x0105d041, "16550A-compatible COM port"}, /* PNP0501 */ 553 {0x0205d041, "Multiport serial device (non-intelligent 16550)"}, /* PNP0502 */ 554 {0x1005d041, "Generic IRDA-compatible device"}, /* PNP0510 */ 555 {0x1105d041, "Generic IRDA-compatible device"}, /* PNP0511 */ 556 {0x01017256, NULL}, /* USR0101 */ 557 {0x30207256, NULL}, /* USR2030 */ 558 {0x31307256, NULL}, /* USR3031 */ 559 {0x8020b04e, NULL}, /* SUP2080 */ 560 {0x8024b04e, NULL}, /* SUP2480 */ 561 {0} 562}; 563 564static int 565sio_isa_probe(dev) 566 device_t dev; 567{ 568 /* Check isapnp ids */ 569 if (ISA_PNP_PROBE(device_get_parent(dev), dev, sio_ids) == ENXIO) 570 return (ENXIO); 571 return (sioprobe(dev)); 572} 573 574static int 575sioprobe(dev) 576 device_t dev; 577{ 578#if 0 579 static bool_t already_init; 580 device_t xdev; 581#endif 582 bool_t failures[10]; 583 int fn; 584 device_t idev; 585 Port_t iobase; 586 intrmask_t irqmap[4]; 587 intrmask_t irqs; 588 u_char mcr_image; 589 int result; 590#ifdef COM_MULTIPORT 591 Port_t xiobase; 592#endif 593 int xirq; 594 u_int flags = device_get_flags(dev); 595 int rid; 596 struct resource *port; 597 598 rid = 0; 599 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 600 0, ~0, IO_COMSIZE, RF_ACTIVE); 601 if (!port) 602 return ENXIO; 603 604#if 0 605 /* 606 * XXX this is broken - when we are first called, there are no 607 * previously configured IO ports. We could hard code 608 * 0x3f8, 0x2f8, 0x3e8, 0x2e8 etc but that's probably worse. 609 * This code has been doing nothing since the conversion since 610 * "count" is zero the first time around. 611 */ 612 if (!already_init) { 613 /* 614 * Turn off MCR_IENABLE for all likely serial ports. An unused 615 * port with its MCR_IENABLE gate open will inhibit interrupts 616 * from any used port that shares the interrupt vector. 617 * XXX the gate enable is elsewhere for some multiports. 618 */ 619 device_t *devs; 620 int count, i, xioport; 621 622 devclass_get_devices(sio_devclass, &devs, &count); 623 for (i = 0; i < count; i++) { 624 xdev = devs[i]; 625 xioport = bus_get_resource_start(xdev, SYS_RES_IOPORT, 0); 626 if (device_is_enabled(xdev) && xioport > 0) 627 outb(xioport + com_mcr, 0); 628 } 629 free(devs, M_TEMP); 630 already_init = TRUE; 631 } 632#endif 633 634 if (COM_LLCONSOLE(flags)) { 635 printf("sio%d: reserved for low-level i/o\n", 636 device_get_unit(dev)); 637 return (ENXIO); 638 } 639 640 /* 641 * If the device is on a multiport card and has an AST/4 642 * compatible interrupt control register, initialize this 643 * register and prepare to leave MCR_IENABLE clear in the mcr. 644 * Otherwise, prepare to set MCR_IENABLE in the mcr. 645 * Point idev to the device struct giving the correct id_irq. 646 * This is the struct for the master device if there is one. 647 */ 648 idev = dev; 649 mcr_image = MCR_IENABLE; 650#ifdef COM_MULTIPORT 651 if (COM_ISMULTIPORT(flags) && !COM_NOTAST4(flags)) { 652 idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags)); 653 if (idev == NULL) { 654 printf("sio%d: master device %d not configured\n", 655 device_get_unit(dev), COM_MPMASTER(flags)); 656 idev = dev; 657 } 658 xiobase = bus_get_resource_start(idev, SYS_RES_IOPORT, 0); 659 if (xiobase > 0) { 660 xirq = bus_get_resource_start(idev, SYS_RES_IRQ, 0); 661 outb(xiobase + com_scr, xirq >= 0 ? 0x80 : 0); 662 } 663 mcr_image = 0; 664 } 665#endif /* COM_MULTIPORT */ 666 if (bus_get_resource_start(idev, SYS_RES_IRQ, 0) <= 0) 667 mcr_image = 0; 668 669 bzero(failures, sizeof failures); 670 iobase = rman_get_start(port); 671 672 /* 673 * We don't want to get actual interrupts, just masked ones. 674 * Interrupts from this line should already be masked in the ICU, 675 * but mask them in the processor as well in case there are some 676 * (misconfigured) shared interrupts. 677 */ 678 disable_intr(); 679/* EXTRA DELAY? */ 680 681 /* 682 * Initialize the speed and the word size and wait long enough to 683 * drain the maximum of 16 bytes of junk in device output queues. 684 * The speed is undefined after a master reset and must be set 685 * before relying on anything related to output. There may be 686 * junk after a (very fast) soft reboot and (apparently) after 687 * master reset. 688 * XXX what about the UART bug avoided by waiting in comparam()? 689 * We don't want to to wait long enough to drain at 2 bps. 690 */ 691 if (iobase == siocniobase) 692 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10)); 693 else { 694 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 695 outb(iobase + com_dlbl, COMBRD(SIO_TEST_SPEED) & 0xff); 696 outb(iobase + com_dlbh, (u_int) COMBRD(SIO_TEST_SPEED) >> 8); 697 outb(iobase + com_cfcr, CFCR_8BITS); 698 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10)); 699 } 700 701 /* 702 * Enable the interrupt gate and disable device interupts. This 703 * should leave the device driving the interrupt line low and 704 * guarantee an edge trigger if an interrupt can be generated. 705 */ 706/* EXTRA DELAY? */ 707 outb(iobase + com_mcr, mcr_image); 708 outb(iobase + com_ier, 0); 709 DELAY(1000); /* XXX */ 710 irqmap[0] = isa_irq_pending(); 711 712 /* 713 * Attempt to set loopback mode so that we can send a null byte 714 * without annoying any external device. 715 */ 716/* EXTRA DELAY? */ 717 outb(iobase + com_mcr, mcr_image | MCR_LOOPBACK); 718 719 /* 720 * Attempt to generate an output interrupt. On 8250's, setting 721 * IER_ETXRDY generates an interrupt independent of the current 722 * setting and independent of whether the THR is empty. On 16450's, 723 * setting IER_ETXRDY generates an interrupt independent of the 724 * current setting. On 16550A's, setting IER_ETXRDY only 725 * generates an interrupt when IER_ETXRDY is not already set. 726 */ 727 outb(iobase + com_ier, IER_ETXRDY); 728 729 /* 730 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate 731 * an interrupt. They'd better generate one for actually doing 732 * output. Loopback may be broken on the same incompatibles but 733 * it's unlikely to do more than allow the null byte out. 734 */ 735 outb(iobase + com_data, 0); 736 DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10)); 737 738 /* 739 * Turn off loopback mode so that the interrupt gate works again 740 * (MCR_IENABLE was hidden). This should leave the device driving 741 * an interrupt line high. It doesn't matter if the interrupt 742 * line oscillates while we are not looking at it, since interrupts 743 * are disabled. 744 */ 745/* EXTRA DELAY? */ 746 outb(iobase + com_mcr, mcr_image); 747 748 /* 749 * Some pcmcia cards have the "TXRDY bug", so we check everyone 750 * for IIR_TXRDY implementation ( Palido 321s, DC-1S... ) 751 */ 752#if 1 753 /* Reading IIR register twice */ 754 for (fn = 0; fn < 2; fn ++) { 755 DELAY(10000); 756 failures[6] = inb(iobase + com_iir); 757 } 758 /* Check IIR_TXRDY clear ? */ 759 result = 0; 760 if (failures[6] & IIR_TXRDY) { 761 /* Nop, Double check with clearing IER */ 762 outb(iobase + com_ier, 0); 763 if (inb(iobase + com_iir) & IIR_NOPEND) { 764 /* Ok. we're familia this gang */ 765 SET_FLAG(dev, COM_C_IIR_TXRDYBUG); 766 } else { 767 /* Unknown, Just omit this chip.. XXX */ 768 result = ENXIO; 769 } 770 } else { 771 /* OK. this is well-known guys */ 772 CLR_FLAG(dev, COM_C_IIR_TXRDYBUG); 773 } 774#else 775 result = 0; 776#endif 777 if (COM_NOPROBE(flags)) { 778 outb(iobase + com_cfcr, CFCR_8BITS); 779 enable_intr(); 780 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 781 return (iobase == siocniobase ? 0 : result); 782 } 783 784 /* 785 * Check that 786 * o the CFCR, IER and MCR in UART hold the values written to them 787 * (the values happen to be all distinct - this is good for 788 * avoiding false positive tests from bus echoes). 789 * o an output interrupt is generated and its vector is correct. 790 * o the interrupt goes away when the IIR in the UART is read. 791 */ 792/* EXTRA DELAY? */ 793 failures[0] = inb(iobase + com_cfcr) - CFCR_8BITS; 794 failures[1] = inb(iobase + com_ier) - IER_ETXRDY; 795 failures[2] = inb(iobase + com_mcr) - mcr_image; 796 DELAY(10000); /* Some internal modems need this time */ 797 irqmap[1] = isa_irq_pending(); 798 failures[4] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_TXRDY; 799 DELAY(1000); /* XXX */ 800 irqmap[2] = isa_irq_pending(); 801 failures[6] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_NOPEND; 802 803 /* 804 * Turn off all device interrupts and check that they go off properly. 805 * Leave MCR_IENABLE alone. For ports without a master port, it gates 806 * the OUT2 output of the UART to 807 * the ICU input. Closing the gate would give a floating ICU input 808 * (unless there is another device driving it) and spurious interrupts. 809 * (On the system that this was first tested on, the input floats high 810 * and gives a (masked) interrupt as soon as the gate is closed.) 811 */ 812 outb(iobase + com_ier, 0); 813 outb(iobase + com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */ 814 failures[7] = inb(iobase + com_ier); 815 DELAY(1000); /* XXX */ 816 irqmap[3] = isa_irq_pending(); 817 failures[9] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_NOPEND; 818 819 enable_intr(); 820 821 irqs = irqmap[1] & ~irqmap[0]; 822 xirq = bus_get_resource_start(idev, SYS_RES_IRQ, 0); 823 if (xirq >= 0 && ((1 << xirq) & irqs) == 0) 824 printf( 825 "sio%d: configured irq %d not in bitmap of probed irqs %#x\n", 826 device_get_unit(dev), xirq, irqs); 827 if (bootverbose) 828 printf("sio%d: irq maps: %#x %#x %#x %#x\n", 829 device_get_unit(dev), 830 irqmap[0], irqmap[1], irqmap[2], irqmap[3]); 831 832 result = 0; 833 for (fn = 0; fn < sizeof failures; ++fn) 834 if (failures[fn]) { 835 outb(iobase + com_mcr, 0); 836 result = ENXIO; 837 if (bootverbose) { 838 printf("sio%d: probe failed test(s):", 839 device_get_unit(dev)); 840 for (fn = 0; fn < sizeof failures; ++fn) 841 if (failures[fn]) 842 printf(" %d", fn); 843 printf("\n"); 844 } 845 break; 846 } 847 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 848 return (iobase == siocniobase ? 0 : result); 849} 850 851#ifdef COM_ESP 852static int 853espattach(com, esp_port) 854 struct com_s *com; 855 Port_t esp_port; 856{ 857 u_char dips; 858 u_char val; 859 860 /* 861 * Check the ESP-specific I/O port to see if we're an ESP 862 * card. If not, return failure immediately. 863 */ 864 if ((inb(esp_port) & 0xf3) == 0) { 865 printf(" port 0x%x is not an ESP board?\n", esp_port); 866 return (0); 867 } 868 869 /* 870 * We've got something that claims to be a Hayes ESP card. 871 * Let's hope so. 872 */ 873 874 /* Get the dip-switch configuration */ 875 outb(esp_port + ESP_CMD1, ESP_GETDIPS); 876 dips = inb(esp_port + ESP_STATUS1); 877 878 /* 879 * Bits 0,1 of dips say which COM port we are. 880 */ 881 if (com->iobase == likely_com_ports[dips & 0x03]) 882 printf(" : ESP"); 883 else { 884 printf(" esp_port has com %d\n", dips & 0x03); 885 return (0); 886 } 887 888 /* 889 * Check for ESP version 2.0 or later: bits 4,5,6 = 010. 890 */ 891 outb(esp_port + ESP_CMD1, ESP_GETTEST); 892 val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */ 893 val = inb(esp_port + ESP_STATUS2); 894 if ((val & 0x70) < 0x20) { 895 printf("-old (%o)", val & 0x70); 896 return (0); 897 } 898 899 /* 900 * Check for ability to emulate 16550: bit 7 == 1 901 */ 902 if ((dips & 0x80) == 0) { 903 printf(" slave"); 904 return (0); 905 } 906 907 /* 908 * Okay, we seem to be a Hayes ESP card. Whee. 909 */ 910 com->esp = TRUE; 911 com->esp_port = esp_port; 912 return (1); 913} 914#endif /* COM_ESP */ 915 916static int 917sio_isa_attach(dev) 918 device_t dev; 919{ 920 return (sioattach(dev)); 921} 922 923static int 924sioattach(dev) 925 device_t dev; 926{ 927 struct com_s *com; 928#ifdef COM_ESP 929 Port_t *espp; 930#endif 931 Port_t iobase; 932 int irq; 933 int unit; 934 void *ih; 935 u_int flags; 936 int rid; 937 struct resource *port; 938 int ret; 939 940 rid = 0; 941 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 942 0, ~0, IO_COMSIZE, RF_ACTIVE); 943 if (!port) 944 return ENXIO; 945 946 iobase = rman_get_start(port); 947 irq = bus_get_resource_start(dev, SYS_RES_IRQ, 0); 948 unit = device_get_unit(dev); 949 com = device_get_softc(dev); 950 flags = device_get_flags(dev); 951 952 if (unit >= sio_numunits) 953 sio_numunits = unit + 1; 954 /* 955 * sioprobe() has initialized the device registers as follows: 956 * o cfcr = CFCR_8BITS. 957 * It is most important that CFCR_DLAB is off, so that the 958 * data port is not hidden when we enable interrupts. 959 * o ier = 0. 960 * Interrupts are only enabled when the line is open. 961 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible 962 * interrupt control register or the config specifies no irq. 963 * Keeping MCR_DTR and MCR_RTS off might stop the external 964 * device from sending before we are ready. 965 */ 966 bzero(com, sizeof *com); 967 com->unit = unit; 968 com->ioportres = port; 969 com->cfcr_image = CFCR_8BITS; 970 com->dtr_wait = 3 * hz; 971 com->loses_outints = COM_LOSESOUTINTS(flags) != 0; 972 com->no_irq = irq < 0; 973 com->tx_fifo_size = 1; 974 com->obufs[0].l_head = com->obuf1; 975 com->obufs[1].l_head = com->obuf2; 976 977 com->iobase = iobase; 978 com->data_port = iobase + com_data; 979 com->int_id_port = iobase + com_iir; 980 com->modem_ctl_port = iobase + com_mcr; 981 com->mcr_image = inb(com->modem_ctl_port); 982 com->line_status_port = iobase + com_lsr; 983 com->modem_status_port = iobase + com_msr; 984 com->intr_ctl_port = iobase + com_ier; 985 986 /* 987 * We don't use all the flags from <sys/ttydefaults.h> since they 988 * are only relevant for logins. It's important to have echo off 989 * initially so that the line doesn't start blathering before the 990 * echo flag can be turned off. 991 */ 992 com->it_in.c_iflag = 0; 993 com->it_in.c_oflag = 0; 994 com->it_in.c_cflag = TTYDEF_CFLAG; 995 com->it_in.c_lflag = 0; 996 if (unit == comconsole) { 997 com->it_in.c_iflag = TTYDEF_IFLAG; 998 com->it_in.c_oflag = TTYDEF_OFLAG; 999 com->it_in.c_cflag = TTYDEF_CFLAG | CLOCAL; 1000 com->it_in.c_lflag = TTYDEF_LFLAG; 1001 com->lt_out.c_cflag = com->lt_in.c_cflag = CLOCAL; 1002 com->lt_out.c_ispeed = com->lt_out.c_ospeed = 1003 com->lt_in.c_ispeed = com->lt_in.c_ospeed = 1004 com->it_in.c_ispeed = com->it_in.c_ospeed = comdefaultrate; 1005 } else 1006 com->it_in.c_ispeed = com->it_in.c_ospeed = TTYDEF_SPEED; 1007 if (siosetwater(com, com->it_in.c_ispeed) != 0) { 1008 enable_intr(); 1009 free(com, M_DEVBUF); 1010 return (0); 1011 } 1012 enable_intr(); 1013 termioschars(&com->it_in); 1014 com->it_out = com->it_in; 1015 1016 /* attempt to determine UART type */ 1017 printf("sio%d: type", unit); 1018 1019 1020#ifdef COM_MULTIPORT 1021 if (!COM_ISMULTIPORT(flags) && !COM_IIR_TXRDYBUG(flags)) 1022#else 1023 if (!COM_IIR_TXRDYBUG(flags)) 1024#endif 1025 { 1026 u_char scr; 1027 u_char scr1; 1028 u_char scr2; 1029 1030 scr = inb(iobase + com_scr); 1031 outb(iobase + com_scr, 0xa5); 1032 scr1 = inb(iobase + com_scr); 1033 outb(iobase + com_scr, 0x5a); 1034 scr2 = inb(iobase + com_scr); 1035 outb(iobase + com_scr, scr); 1036 if (scr1 != 0xa5 || scr2 != 0x5a) { 1037 printf(" 8250"); 1038 goto determined_type; 1039 } 1040 } 1041 outb(iobase + com_fifo, FIFO_ENABLE | FIFO_RX_HIGH); 1042 DELAY(100); 1043 com->st16650a = 0; 1044 switch (inb(com->int_id_port) & IIR_FIFO_MASK) { 1045 case FIFO_RX_LOW: 1046 printf(" 16450"); 1047 break; 1048 case FIFO_RX_MEDL: 1049 printf(" 16450?"); 1050 break; 1051 case FIFO_RX_MEDH: 1052 printf(" 16550?"); 1053 break; 1054 case FIFO_RX_HIGH: 1055 if (COM_NOFIFO(flags)) { 1056 printf(" 16550A fifo disabled"); 1057 } else { 1058 com->hasfifo = TRUE; 1059 if (COM_ST16650A(flags)) { 1060 com->st16650a = 1; 1061 com->tx_fifo_size = 32; 1062 printf(" ST16650A"); 1063 } else { 1064 com->tx_fifo_size = COM_FIFOSIZE(flags); 1065 printf(" 16550A"); 1066 } 1067 } 1068#ifdef COM_ESP 1069 for (espp = likely_esp_ports; *espp != 0; espp++) 1070 if (espattach(com, *espp)) { 1071 com->tx_fifo_size = 1024; 1072 break; 1073 } 1074#endif 1075 if (!com->st16650a) { 1076 if (!com->tx_fifo_size) 1077 com->tx_fifo_size = 16; 1078 else 1079 printf(" lookalike with %d bytes FIFO", 1080 com->tx_fifo_size); 1081 } 1082 1083 break; 1084 } 1085 1086#ifdef COM_ESP 1087 if (com->esp) { 1088 /* 1089 * Set 16550 compatibility mode. 1090 * We don't use the ESP_MODE_SCALE bit to increase the 1091 * fifo trigger levels because we can't handle large 1092 * bursts of input. 1093 * XXX flow control should be set in comparam(), not here. 1094 */ 1095 outb(com->esp_port + ESP_CMD1, ESP_SETMODE); 1096 outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO); 1097 1098 /* Set RTS/CTS flow control. */ 1099 outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE); 1100 outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS); 1101 outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS); 1102 1103 /* Set flow-control levels. */ 1104 outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW); 1105 outb(com->esp_port + ESP_CMD2, HIBYTE(768)); 1106 outb(com->esp_port + ESP_CMD2, LOBYTE(768)); 1107 outb(com->esp_port + ESP_CMD2, HIBYTE(512)); 1108 outb(com->esp_port + ESP_CMD2, LOBYTE(512)); 1109 } 1110#endif /* COM_ESP */ 1111 outb(iobase + com_fifo, 0); 1112determined_type: ; 1113 1114#ifdef COM_MULTIPORT 1115 if (COM_ISMULTIPORT(flags)) { 1116 device_t masterdev; 1117 int irq; 1118 1119 com->multiport = TRUE; 1120 printf(" (multiport"); 1121 if (unit == COM_MPMASTER(flags)) 1122 printf(" master"); 1123 printf(")"); 1124 masterdev = devclass_get_device(sio_devclass, 1125 COM_MPMASTER(flags)); 1126 irq = bus_get_resource_start(masterdev, SYS_RES_IRQ, 0); 1127 com->no_irq = irq < 0; 1128 } 1129#endif /* COM_MULTIPORT */ 1130 if (unit == comconsole) 1131 printf(", console"); 1132 if (COM_IIR_TXRDYBUG(flags)) 1133 printf(" with a bogus IIR_TXRDY register"); 1134 printf("\n"); 1135 1136 if (!sio_registered) { 1137 register_swi(SWI_TTY, siopoll); 1138 sio_registered = TRUE; 1139 } 1140 make_dev(&sio_cdevsw, unit, 1141 UID_ROOT, GID_WHEEL, 0600, "ttyd%r", unit); 1142 make_dev(&sio_cdevsw, unit | CONTROL_INIT_STATE, 1143 UID_ROOT, GID_WHEEL, 0600, "ttyid%r", unit); 1144 make_dev(&sio_cdevsw, unit | CONTROL_LOCK_STATE, 1145 UID_ROOT, GID_WHEEL, 0600, "ttyld%r", unit); 1146 make_dev(&sio_cdevsw, unit | CALLOUT_MASK, 1147 UID_UUCP, GID_DIALER, 0660, "cuaa%r", unit); 1148 make_dev(&sio_cdevsw, unit | CALLOUT_MASK | CONTROL_INIT_STATE, 1149 UID_UUCP, GID_DIALER, 0660, "cuaia%r", unit); 1150 make_dev(&sio_cdevsw, unit | CALLOUT_MASK | CONTROL_LOCK_STATE, 1151 UID_UUCP, GID_DIALER, 0660, "cuala%r", unit); 1152 com->flags = flags; 1153 com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 1154 pps_init(&com->pps); 1155 1156 rid = 0; 1157 com->irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0ul, ~0ul, 1, 1158 RF_ACTIVE); 1159 if (com->irqres) { 1160 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, com->irqres, 1161 INTR_TYPE_TTY | INTR_TYPE_FAST, 1162 siointr, com, &ih); 1163 if (ret) 1164 device_printf(dev, "could not activate interrupt\n"); 1165 } 1166 1167 return (0); 1168} 1169 1170static int 1171sioopen(dev, flag, mode, p) 1172 dev_t dev; 1173 int flag; 1174 int mode; 1175 struct proc *p; 1176{ 1177 struct com_s *com; 1178 int error; 1179 Port_t iobase; 1180 int mynor; 1181 int s; 1182 struct tty *tp; 1183 int unit; 1184 1185 mynor = minor(dev); 1186 unit = MINOR_TO_UNIT(mynor); 1187 com = com_addr(unit); 1188 if (com == NULL) 1189 return (ENXIO); 1190 if (com->gone) 1191 return (ENXIO); 1192 if (mynor & CONTROL_MASK) 1193 return (0); 1194 tp = dev->si_tty = com->tp = ttymalloc(com->tp); 1195 s = spltty(); 1196 /* 1197 * We jump to this label after all non-interrupted sleeps to pick 1198 * up any changes of the device state. 1199 */ 1200open_top: 1201 while (com->state & CS_DTR_OFF) { 1202 error = tsleep(&com->dtr_wait, TTIPRI | PCATCH, "siodtr", 0); 1203 if (com_addr(unit) == NULL) 1204 return (ENXIO); 1205 if (error != 0 || com->gone) 1206 goto out; 1207 } 1208 if (tp->t_state & TS_ISOPEN) { 1209 /* 1210 * The device is open, so everything has been initialized. 1211 * Handle conflicts. 1212 */ 1213 if (mynor & CALLOUT_MASK) { 1214 if (!com->active_out) { 1215 error = EBUSY; 1216 goto out; 1217 } 1218 } else { 1219 if (com->active_out) { 1220 if (flag & O_NONBLOCK) { 1221 error = EBUSY; 1222 goto out; 1223 } 1224 error = tsleep(&com->active_out, 1225 TTIPRI | PCATCH, "siobi", 0); 1226 if (com_addr(unit) == NULL) 1227 return (ENXIO); 1228 if (error != 0 || com->gone) 1229 goto out; 1230 goto open_top; 1231 } 1232 } 1233 if (tp->t_state & TS_XCLUDE && 1234 suser(p)) { 1235 error = EBUSY; 1236 goto out; 1237 } 1238 } else { 1239 /* 1240 * The device isn't open, so there are no conflicts. 1241 * Initialize it. Initialization is done twice in many 1242 * cases: to preempt sleeping callin opens if we are 1243 * callout, and to complete a callin open after DCD rises. 1244 */ 1245 tp->t_oproc = comstart; 1246 tp->t_param = comparam; 1247 tp->t_stop = comstop; 1248 tp->t_dev = dev; 1249 tp->t_termios = mynor & CALLOUT_MASK 1250 ? com->it_out : com->it_in; 1251 (void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET); 1252 com->poll = com->no_irq; 1253 com->poll_output = com->loses_outints; 1254 ++com->wopeners; 1255 error = comparam(tp, &tp->t_termios); 1256 --com->wopeners; 1257 if (error != 0) 1258 goto out; 1259 /* 1260 * XXX we should goto open_top if comparam() slept. 1261 */ 1262 iobase = com->iobase; 1263 if (com->hasfifo) { 1264 /* 1265 * (Re)enable and drain fifos. 1266 * 1267 * Certain SMC chips cause problems if the fifos 1268 * are enabled while input is ready. Turn off the 1269 * fifo if necessary to clear the input. We test 1270 * the input ready bit after enabling the fifos 1271 * since we've already enabled them in comparam() 1272 * and to handle races between enabling and fresh 1273 * input. 1274 */ 1275 while (TRUE) { 1276 outb(iobase + com_fifo, 1277 FIFO_RCV_RST | FIFO_XMT_RST 1278 | com->fifo_image); 1279 /* 1280 * XXX the delays are for superstitious 1281 * historical reasons. It must be less than 1282 * the character time at the maximum 1283 * supported speed (87 usec at 115200 bps 1284 * 8N1). Otherwise we might loop endlessly 1285 * if data is streaming in. We used to use 1286 * delays of 100. That usually worked 1287 * because DELAY(100) used to usually delay 1288 * for about 85 usec instead of 100. 1289 */ 1290 DELAY(50); 1291 if (!(inb(com->line_status_port) & LSR_RXRDY)) 1292 break; 1293 outb(iobase + com_fifo, 0); 1294 DELAY(50); 1295 (void) inb(com->data_port); 1296 } 1297 } 1298 1299 disable_intr(); 1300 (void) inb(com->line_status_port); 1301 (void) inb(com->data_port); 1302 com->prev_modem_status = com->last_modem_status 1303 = inb(com->modem_status_port); 1304 if (COM_IIR_TXRDYBUG(com->flags)) { 1305 outb(com->intr_ctl_port, IER_ERXRDY | IER_ERLS 1306 | IER_EMSC); 1307 } else { 1308 outb(com->intr_ctl_port, IER_ERXRDY | IER_ETXRDY 1309 | IER_ERLS | IER_EMSC); 1310 } 1311 enable_intr(); 1312 /* 1313 * Handle initial DCD. Callout devices get a fake initial 1314 * DCD (trapdoor DCD). If we are callout, then any sleeping 1315 * callin opens get woken up and resume sleeping on "siobi" 1316 * instead of "siodcd". 1317 */ 1318 /* 1319 * XXX `mynor & CALLOUT_MASK' should be 1320 * `tp->t_cflag & (SOFT_CARRIER | TRAPDOOR_CARRIER) where 1321 * TRAPDOOR_CARRIER is the default initial state for callout 1322 * devices and SOFT_CARRIER is like CLOCAL except it hides 1323 * the true carrier. 1324 */ 1325 if (com->prev_modem_status & MSR_DCD || mynor & CALLOUT_MASK) 1326 (*linesw[tp->t_line].l_modem)(tp, 1); 1327 } 1328 /* 1329 * Wait for DCD if necessary. 1330 */ 1331 if (!(tp->t_state & TS_CARR_ON) && !(mynor & CALLOUT_MASK) 1332 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 1333 ++com->wopeners; 1334 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "siodcd", 0); 1335 if (com_addr(unit) == NULL) 1336 return (ENXIO); 1337 --com->wopeners; 1338 if (error != 0 || com->gone) 1339 goto out; 1340 goto open_top; 1341 } 1342 error = (*linesw[tp->t_line].l_open)(dev, tp); 1343 disc_optim(tp, &tp->t_termios, com); 1344 if (tp->t_state & TS_ISOPEN && mynor & CALLOUT_MASK) 1345 com->active_out = TRUE; 1346 siosettimeout(); 1347out: 1348 splx(s); 1349 if (!(tp->t_state & TS_ISOPEN) && com->wopeners == 0) 1350 comhardclose(com); 1351 return (error); 1352} 1353 1354static int 1355sioclose(dev, flag, mode, p) 1356 dev_t dev; 1357 int flag; 1358 int mode; 1359 struct proc *p; 1360{ 1361 struct com_s *com; 1362 int mynor; 1363 int s; 1364 struct tty *tp; 1365 1366 mynor = minor(dev); 1367 if (mynor & CONTROL_MASK) 1368 return (0); 1369 com = com_addr(MINOR_TO_UNIT(mynor)); 1370 tp = com->tp; 1371 s = spltty(); 1372 (*linesw[tp->t_line].l_close)(tp, flag); 1373 disc_optim(tp, &tp->t_termios, com); 1374 comstop(tp, FREAD | FWRITE); 1375 comhardclose(com); 1376 ttyclose(tp); 1377 siosettimeout(); 1378 splx(s); 1379 if (com->gone) { 1380 printf("sio%d: gone\n", com->unit); 1381 s = spltty(); 1382 if (com->ibuf != NULL) 1383 free(com->ibuf, M_DEVBUF); 1384 bzero(tp, sizeof *tp); 1385 free(com, M_DEVBUF); 1386 splx(s); 1387 } 1388 return (0); 1389} 1390 1391static void 1392comhardclose(com) 1393 struct com_s *com; 1394{ 1395 Port_t iobase; 1396 int s; 1397 struct tty *tp; 1398 int unit; 1399 1400 unit = com->unit; 1401 iobase = com->iobase; 1402 s = spltty(); 1403 com->poll = FALSE; 1404 com->poll_output = FALSE; 1405 com->do_timestamp = FALSE; 1406 com->do_dcd_timestamp = FALSE; 1407 com->pps.ppsparam.mode = 0; 1408 outb(iobase + com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 1409 { 1410 outb(iobase + com_ier, 0); 1411 tp = com->tp; 1412 if (tp->t_cflag & HUPCL 1413 /* 1414 * XXX we will miss any carrier drop between here and the 1415 * next open. Perhaps we should watch DCD even when the 1416 * port is closed; it is not sufficient to check it at 1417 * the next open because it might go up and down while 1418 * we're not watching. 1419 */ 1420 || (!com->active_out 1421 && !(com->prev_modem_status & MSR_DCD) 1422 && !(com->it_in.c_cflag & CLOCAL)) 1423 || !(tp->t_state & TS_ISOPEN)) { 1424 (void)commctl(com, TIOCM_DTR, DMBIC); 1425 if (com->dtr_wait != 0 && !(com->state & CS_DTR_OFF)) { 1426 timeout(siodtrwakeup, com, com->dtr_wait); 1427 com->state |= CS_DTR_OFF; 1428 } 1429 } 1430 } 1431 if (com->hasfifo) { 1432 /* 1433 * Disable fifos so that they are off after controlled 1434 * reboots. Some BIOSes fail to detect 16550s when the 1435 * fifos are enabled. 1436 */ 1437 outb(iobase + com_fifo, 0); 1438 } 1439 com->active_out = FALSE; 1440 wakeup(&com->active_out); 1441 wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */ 1442 splx(s); 1443} 1444 1445static int 1446sioread(dev, uio, flag) 1447 dev_t dev; 1448 struct uio *uio; 1449 int flag; 1450{ 1451 int mynor; 1452 struct com_s *com; 1453 1454 mynor = minor(dev); 1455 if (mynor & CONTROL_MASK) 1456 return (ENODEV); 1457 com = com_addr(MINOR_TO_UNIT(mynor)); 1458 if (com->gone) 1459 return (ENODEV); 1460 return ((*linesw[com->tp->t_line].l_read)(com->tp, uio, flag)); 1461} 1462 1463static int 1464siowrite(dev, uio, flag) 1465 dev_t dev; 1466 struct uio *uio; 1467 int flag; 1468{ 1469 int mynor; 1470 struct com_s *com; 1471 int unit; 1472 1473 mynor = minor(dev); 1474 if (mynor & CONTROL_MASK) 1475 return (ENODEV); 1476 1477 unit = MINOR_TO_UNIT(mynor); 1478 com = com_addr(unit); 1479 if (com->gone) 1480 return (ENODEV); 1481 /* 1482 * (XXX) We disallow virtual consoles if the physical console is 1483 * a serial port. This is in case there is a display attached that 1484 * is not the console. In that situation we don't need/want the X 1485 * server taking over the console. 1486 */ 1487 if (constty != NULL && unit == comconsole) 1488 constty = NULL; 1489 return ((*linesw[com->tp->t_line].l_write)(com->tp, uio, flag)); 1490} 1491 1492static void 1493siobusycheck(chan) 1494 void *chan; 1495{ 1496 struct com_s *com; 1497 int s; 1498 1499 com = (struct com_s *)chan; 1500 1501 /* 1502 * Clear TS_BUSY if low-level output is complete. 1503 * spl locking is sufficient because siointr1() does not set CS_BUSY. 1504 * If siointr1() clears CS_BUSY after we look at it, then we'll get 1505 * called again. Reading the line status port outside of siointr1() 1506 * is safe because CS_BUSY is clear so there are no output interrupts 1507 * to lose. 1508 */ 1509 s = spltty(); 1510 if (com->state & CS_BUSY) 1511 com->extra_state &= ~CSE_BUSYCHECK; /* False alarm. */ 1512 else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY)) 1513 == (LSR_TSRE | LSR_TXRDY)) { 1514 com->tp->t_state &= ~TS_BUSY; 1515 ttwwakeup(com->tp); 1516 com->extra_state &= ~CSE_BUSYCHECK; 1517 } else 1518 timeout(siobusycheck, com, hz / 100); 1519 splx(s); 1520} 1521 1522static void 1523siodtrwakeup(chan) 1524 void *chan; 1525{ 1526 struct com_s *com; 1527 1528 com = (struct com_s *)chan; 1529 com->state &= ~CS_DTR_OFF; 1530 wakeup(&com->dtr_wait); 1531} 1532 1533static void 1534sioinput(com) 1535 struct com_s *com; 1536{ 1537 u_char *buf; 1538 int incc; 1539 u_char line_status; 1540 int recv_data; 1541 struct tty *tp; 1542 1543 buf = com->ibuf; 1544 tp = com->tp; 1545 if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) { 1546 com_events -= (com->iptr - com->ibuf); 1547 com->iptr = com->ibuf; 1548 return; 1549 } 1550 if (tp->t_state & TS_CAN_BYPASS_L_RINT) { 1551 /* 1552 * Avoid the grotesquely inefficient lineswitch routine 1553 * (ttyinput) in "raw" mode. It usually takes about 450 1554 * instructions (that's without canonical processing or echo!). 1555 * slinput is reasonably fast (usually 40 instructions plus 1556 * call overhead). 1557 */ 1558 do { 1559 enable_intr(); 1560 incc = com->iptr - buf; 1561 if (tp->t_rawq.c_cc + incc > tp->t_ihiwat 1562 && (com->state & CS_RTS_IFLOW 1563 || tp->t_iflag & IXOFF) 1564 && !(tp->t_state & TS_TBLOCK)) 1565 ttyblock(tp); 1566 com->delta_error_counts[CE_TTY_BUF_OVERFLOW] 1567 += b_to_q((char *)buf, incc, &tp->t_rawq); 1568 buf += incc; 1569 tk_nin += incc; 1570 tk_rawcc += incc; 1571 tp->t_rawcc += incc; 1572 ttwakeup(tp); 1573 if (tp->t_state & TS_TTSTOP 1574 && (tp->t_iflag & IXANY 1575 || tp->t_cc[VSTART] == tp->t_cc[VSTOP])) { 1576 tp->t_state &= ~TS_TTSTOP; 1577 tp->t_lflag &= ~FLUSHO; 1578 comstart(tp); 1579 } 1580 disable_intr(); 1581 } while (buf < com->iptr); 1582 } else { 1583 do { 1584 enable_intr(); 1585 line_status = buf[com->ierroff]; 1586 recv_data = *buf++; 1587 if (line_status 1588 & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) { 1589 if (line_status & LSR_BI) 1590 recv_data |= TTY_BI; 1591 if (line_status & LSR_FE) 1592 recv_data |= TTY_FE; 1593 if (line_status & LSR_OE) 1594 recv_data |= TTY_OE; 1595 if (line_status & LSR_PE) 1596 recv_data |= TTY_PE; 1597 } 1598 (*linesw[tp->t_line].l_rint)(recv_data, tp); 1599 disable_intr(); 1600 } while (buf < com->iptr); 1601 } 1602 com_events -= (com->iptr - com->ibuf); 1603 com->iptr = com->ibuf; 1604 1605 /* 1606 * There is now room for another low-level buffer full of input, 1607 * so enable RTS if it is now disabled and there is room in the 1608 * high-level buffer. 1609 */ 1610 if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) && 1611 !(tp->t_state & TS_TBLOCK)) 1612 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 1613} 1614 1615void 1616siointr(arg) 1617 void *arg; 1618{ 1619#ifndef COM_MULTIPORT 1620 COM_LOCK(); 1621 siointr1((struct com_s *) arg); 1622 COM_UNLOCK(); 1623#else /* COM_MULTIPORT */ 1624 bool_t possibly_more_intrs; 1625 int unit; 1626 struct com_s *com; 1627 1628 /* 1629 * Loop until there is no activity on any port. This is necessary 1630 * to get an interrupt edge more than to avoid another interrupt. 1631 * If the IRQ signal is just an OR of the IRQ signals from several 1632 * devices, then the edge from one may be lost because another is 1633 * on. 1634 */ 1635 COM_LOCK(); 1636 do { 1637 possibly_more_intrs = FALSE; 1638 for (unit = 0; unit < sio_numunits; ++unit) { 1639 com = com_addr(unit); 1640 /* 1641 * XXX COM_LOCK(); 1642 * would it work here, or be counter-productive? 1643 */ 1644 if (com != NULL 1645 && !com->gone 1646 && (inb(com->int_id_port) & IIR_IMASK) 1647 != IIR_NOPEND) { 1648 siointr1(com); 1649 possibly_more_intrs = TRUE; 1650 } 1651 /* XXX COM_UNLOCK(); */ 1652 } 1653 } while (possibly_more_intrs); 1654 COM_UNLOCK(); 1655#endif /* COM_MULTIPORT */ 1656} 1657 1658static void 1659siointr1(com) 1660 struct com_s *com; 1661{ 1662 u_char line_status; 1663 u_char modem_status; 1664 u_char *ioptr; 1665 u_char recv_data; 1666 u_char int_ctl; 1667 u_char int_ctl_new; 1668 struct timecounter *tc; 1669 u_int count; 1670 1671 int_ctl = inb(com->intr_ctl_port); 1672 int_ctl_new = int_ctl; 1673 1674 while (!com->gone) { 1675 if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) { 1676 modem_status = inb(com->modem_status_port); 1677 if ((modem_status ^ com->last_modem_status) & MSR_DCD) { 1678 tc = timecounter; 1679 count = tc->tc_get_timecount(tc); 1680 pps_event(&com->pps, tc, count, 1681 (modem_status & MSR_DCD) ? 1682 PPS_CAPTUREASSERT : PPS_CAPTURECLEAR); 1683 } 1684 } 1685 line_status = inb(com->line_status_port); 1686 1687 /* input event? (check first to help avoid overruns) */ 1688 while (line_status & LSR_RCV_MASK) { 1689 /* break/unnattached error bits or real input? */ 1690 if (!(line_status & LSR_RXRDY)) 1691 recv_data = 0; 1692 else 1693 recv_data = inb(com->data_port); 1694 if (line_status & (LSR_BI | LSR_FE | LSR_PE)) { 1695 /* 1696 * Don't store BI if IGNBRK or FE/PE if IGNPAR. 1697 * Otherwise, push the work to a higher level 1698 * (to handle PARMRK) if we're bypassing. 1699 * Otherwise, convert BI/FE and PE+INPCK to 0. 1700 * 1701 * This makes bypassing work right in the 1702 * usual "raw" case (IGNBRK set, and IGNPAR 1703 * and INPCK clear). 1704 * 1705 * Note: BI together with FE/PE means just BI. 1706 */ 1707 if (line_status & LSR_BI) { 1708#if defined(DDB) && defined(BREAK_TO_DEBUGGER) 1709 if (com->unit == comconsole) { 1710 breakpoint(); 1711 goto cont; 1712 } 1713#endif 1714 if (com->tp == NULL 1715 || com->tp->t_iflag & IGNBRK) 1716 goto cont; 1717 } else { 1718 if (com->tp == NULL 1719 || com->tp->t_iflag & IGNPAR) 1720 goto cont; 1721 } 1722 if (com->tp->t_state & TS_CAN_BYPASS_L_RINT 1723 && (line_status & (LSR_BI | LSR_FE) 1724 || com->tp->t_iflag & INPCK)) 1725 recv_data = 0; 1726 } 1727 ++com->bytes_in; 1728 if (com->hotchar != 0 && recv_data == com->hotchar) 1729 setsofttty(); 1730 ioptr = com->iptr; 1731 if (ioptr >= com->ibufend) 1732 CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW); 1733 else { 1734 if (com->do_timestamp) 1735 microtime(&com->timestamp); 1736 ++com_events; 1737 schedsofttty(); 1738#if 0 /* for testing input latency vs efficiency */ 1739if (com->iptr - com->ibuf == 8) 1740 setsofttty(); 1741#endif 1742 ioptr[0] = recv_data; 1743 ioptr[com->ierroff] = line_status; 1744 com->iptr = ++ioptr; 1745 if (ioptr == com->ihighwater 1746 && com->state & CS_RTS_IFLOW) 1747 outb(com->modem_ctl_port, 1748 com->mcr_image &= ~MCR_RTS); 1749 if (line_status & LSR_OE) 1750 CE_RECORD(com, CE_OVERRUN); 1751 } 1752cont: 1753 /* 1754 * "& 0x7F" is to avoid the gcc-1.40 generating a slow 1755 * jump from the top of the loop to here 1756 */ 1757 line_status = inb(com->line_status_port) & 0x7F; 1758 } 1759 1760 /* modem status change? (always check before doing output) */ 1761 modem_status = inb(com->modem_status_port); 1762 if (modem_status != com->last_modem_status) { 1763 if (com->do_dcd_timestamp 1764 && !(com->last_modem_status & MSR_DCD) 1765 && modem_status & MSR_DCD) 1766 microtime(&com->dcd_timestamp); 1767 1768 /* 1769 * Schedule high level to handle DCD changes. Note 1770 * that we don't use the delta bits anywhere. Some 1771 * UARTs mess them up, and it's easy to remember the 1772 * previous bits and calculate the delta. 1773 */ 1774 com->last_modem_status = modem_status; 1775 if (!(com->state & CS_CHECKMSR)) { 1776 com_events += LOTS_OF_EVENTS; 1777 com->state |= CS_CHECKMSR; 1778 setsofttty(); 1779 } 1780 1781 /* handle CTS change immediately for crisp flow ctl */ 1782 if (com->state & CS_CTS_OFLOW) { 1783 if (modem_status & MSR_CTS) 1784 com->state |= CS_ODEVREADY; 1785 else 1786 com->state &= ~CS_ODEVREADY; 1787 } 1788 } 1789 1790 /* output queued and everything ready? */ 1791 if (line_status & LSR_TXRDY 1792 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) { 1793 ioptr = com->obufq.l_head; 1794 if (com->tx_fifo_size > 1) { 1795 u_int ocount; 1796 1797 ocount = com->obufq.l_tail - ioptr; 1798 if (ocount > com->tx_fifo_size) 1799 ocount = com->tx_fifo_size; 1800 com->bytes_out += ocount; 1801 do 1802 outb(com->data_port, *ioptr++); 1803 while (--ocount != 0); 1804 } else { 1805 outb(com->data_port, *ioptr++); 1806 ++com->bytes_out; 1807 } 1808 com->obufq.l_head = ioptr; 1809 if (COM_IIR_TXRDYBUG(com->flags)) { 1810 int_ctl_new = int_ctl | IER_ETXRDY; 1811 } 1812 if (ioptr >= com->obufq.l_tail) { 1813 struct lbq *qp; 1814 1815 qp = com->obufq.l_next; 1816 qp->l_queued = FALSE; 1817 qp = qp->l_next; 1818 if (qp != NULL) { 1819 com->obufq.l_head = qp->l_head; 1820 com->obufq.l_tail = qp->l_tail; 1821 com->obufq.l_next = qp; 1822 } else { 1823 /* output just completed */ 1824 if (COM_IIR_TXRDYBUG(com->flags)) { 1825 int_ctl_new = int_ctl & ~IER_ETXRDY; 1826 } 1827 com->state &= ~CS_BUSY; 1828 } 1829 if (!(com->state & CS_ODONE)) { 1830 com_events += LOTS_OF_EVENTS; 1831 com->state |= CS_ODONE; 1832 setsofttty(); /* handle at high level ASAP */ 1833 } 1834 } 1835 if (COM_IIR_TXRDYBUG(com->flags) && (int_ctl != int_ctl_new)) { 1836 outb(com->intr_ctl_port, int_ctl_new); 1837 } 1838 } 1839 1840 /* finished? */ 1841#ifndef COM_MULTIPORT 1842 if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND) 1843#endif /* COM_MULTIPORT */ 1844 return; 1845 } 1846} 1847 1848static int 1849sioioctl(dev, cmd, data, flag, p) 1850 dev_t dev; 1851 u_long cmd; 1852 caddr_t data; 1853 int flag; 1854 struct proc *p; 1855{ 1856 struct com_s *com; 1857 int error; 1858 Port_t iobase; 1859 int mynor; 1860 int s; 1861 struct tty *tp; 1862#if defined(COMPAT_43) || defined(COMPAT_SUNOS) 1863 u_long oldcmd; 1864 struct termios term; 1865#endif 1866 1867 mynor = minor(dev); 1868 com = com_addr(MINOR_TO_UNIT(mynor)); 1869 if (com->gone) 1870 return (ENODEV); 1871 iobase = com->iobase; 1872 if (mynor & CONTROL_MASK) { 1873 struct termios *ct; 1874 1875 switch (mynor & CONTROL_MASK) { 1876 case CONTROL_INIT_STATE: 1877 ct = mynor & CALLOUT_MASK ? &com->it_out : &com->it_in; 1878 break; 1879 case CONTROL_LOCK_STATE: 1880 ct = mynor & CALLOUT_MASK ? &com->lt_out : &com->lt_in; 1881 break; 1882 default: 1883 return (ENODEV); /* /dev/nodev */ 1884 } 1885 switch (cmd) { 1886 case TIOCSETA: 1887 error = suser(p); 1888 if (error != 0) 1889 return (error); 1890 *ct = *(struct termios *)data; 1891 return (0); 1892 case TIOCGETA: 1893 *(struct termios *)data = *ct; 1894 return (0); 1895 case TIOCGETD: 1896 *(int *)data = TTYDISC; 1897 return (0); 1898 case TIOCGWINSZ: 1899 bzero(data, sizeof(struct winsize)); 1900 return (0); 1901 default: 1902 return (ENOTTY); 1903 } 1904 } 1905 tp = com->tp; 1906#if defined(COMPAT_43) || defined(COMPAT_SUNOS) 1907 term = tp->t_termios; 1908 oldcmd = cmd; 1909 error = ttsetcompat(tp, &cmd, data, &term); 1910 if (error != 0) 1911 return (error); 1912 if (cmd != oldcmd) 1913 data = (caddr_t)&term; 1914#endif 1915 if (cmd == TIOCSETA || cmd == TIOCSETAW || cmd == TIOCSETAF) { 1916 int cc; 1917 struct termios *dt = (struct termios *)data; 1918 struct termios *lt = mynor & CALLOUT_MASK 1919 ? &com->lt_out : &com->lt_in; 1920 1921 dt->c_iflag = (tp->t_iflag & lt->c_iflag) 1922 | (dt->c_iflag & ~lt->c_iflag); 1923 dt->c_oflag = (tp->t_oflag & lt->c_oflag) 1924 | (dt->c_oflag & ~lt->c_oflag); 1925 dt->c_cflag = (tp->t_cflag & lt->c_cflag) 1926 | (dt->c_cflag & ~lt->c_cflag); 1927 dt->c_lflag = (tp->t_lflag & lt->c_lflag) 1928 | (dt->c_lflag & ~lt->c_lflag); 1929 for (cc = 0; cc < NCCS; ++cc) 1930 if (lt->c_cc[cc] != 0) 1931 dt->c_cc[cc] = tp->t_cc[cc]; 1932 if (lt->c_ispeed != 0) 1933 dt->c_ispeed = tp->t_ispeed; 1934 if (lt->c_ospeed != 0) 1935 dt->c_ospeed = tp->t_ospeed; 1936 } 1937 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 1938 if (error != ENOIOCTL) 1939 return (error); 1940 s = spltty(); 1941 error = ttioctl(tp, cmd, data, flag); 1942 disc_optim(tp, &tp->t_termios, com); 1943 if (error != ENOIOCTL) { 1944 splx(s); 1945 return (error); 1946 } 1947 switch (cmd) { 1948 case TIOCSBRK: 1949 outb(iobase + com_cfcr, com->cfcr_image |= CFCR_SBREAK); 1950 break; 1951 case TIOCCBRK: 1952 outb(iobase + com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 1953 break; 1954 case TIOCSDTR: 1955 (void)commctl(com, TIOCM_DTR, DMBIS); 1956 break; 1957 case TIOCCDTR: 1958 (void)commctl(com, TIOCM_DTR, DMBIC); 1959 break; 1960 /* 1961 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The 1962 * changes get undone on the next call to comparam(). 1963 */ 1964 case TIOCMSET: 1965 (void)commctl(com, *(int *)data, DMSET); 1966 break; 1967 case TIOCMBIS: 1968 (void)commctl(com, *(int *)data, DMBIS); 1969 break; 1970 case TIOCMBIC: 1971 (void)commctl(com, *(int *)data, DMBIC); 1972 break; 1973 case TIOCMGET: 1974 *(int *)data = commctl(com, 0, DMGET); 1975 break; 1976 case TIOCMSDTRWAIT: 1977 /* must be root since the wait applies to following logins */ 1978 error = suser(p); 1979 if (error != 0) { 1980 splx(s); 1981 return (error); 1982 } 1983 com->dtr_wait = *(int *)data * hz / 100; 1984 break; 1985 case TIOCMGDTRWAIT: 1986 *(int *)data = com->dtr_wait * 100 / hz; 1987 break; 1988 case TIOCTIMESTAMP: 1989 com->do_timestamp = TRUE; 1990 *(struct timeval *)data = com->timestamp; 1991 break; 1992 case TIOCDCDTIMESTAMP: 1993 com->do_dcd_timestamp = TRUE; 1994 *(struct timeval *)data = com->dcd_timestamp; 1995 break; 1996 default: 1997 splx(s); 1998 error = pps_ioctl(cmd, data, &com->pps); 1999 if (error == ENODEV) 2000 error = ENOTTY; 2001 return (error); 2002 } 2003 splx(s); 2004 return (0); 2005} 2006 2007static void 2008siopoll() 2009{ 2010 int unit; 2011 2012 if (com_events == 0) 2013 return; 2014repeat: 2015 for (unit = 0; unit < sio_numunits; ++unit) { 2016 struct com_s *com; 2017 int incc; 2018 struct tty *tp; 2019 2020 com = com_addr(unit); 2021 if (com == NULL) 2022 continue; 2023 tp = com->tp; 2024 if (tp == NULL || com->gone) { 2025 /* 2026 * Discard any events related to never-opened or 2027 * going-away devices. 2028 */ 2029 disable_intr(); 2030 incc = com->iptr - com->ibuf; 2031 com->iptr = com->ibuf; 2032 if (com->state & CS_CHECKMSR) { 2033 incc += LOTS_OF_EVENTS; 2034 com->state &= ~CS_CHECKMSR; 2035 } 2036 com_events -= incc; 2037 enable_intr(); 2038 continue; 2039 } 2040 if (com->iptr != com->ibuf) { 2041 disable_intr(); 2042 sioinput(com); 2043 enable_intr(); 2044 } 2045 if (com->state & CS_CHECKMSR) { 2046 u_char delta_modem_status; 2047 2048 disable_intr(); 2049 delta_modem_status = com->last_modem_status 2050 ^ com->prev_modem_status; 2051 com->prev_modem_status = com->last_modem_status; 2052 com_events -= LOTS_OF_EVENTS; 2053 com->state &= ~CS_CHECKMSR; 2054 enable_intr(); 2055 if (delta_modem_status & MSR_DCD) 2056 (*linesw[tp->t_line].l_modem) 2057 (tp, com->prev_modem_status & MSR_DCD); 2058 } 2059 if (com->state & CS_ODONE) { 2060 disable_intr(); 2061 com_events -= LOTS_OF_EVENTS; 2062 com->state &= ~CS_ODONE; 2063 enable_intr(); 2064 if (!(com->state & CS_BUSY) 2065 && !(com->extra_state & CSE_BUSYCHECK)) { 2066 timeout(siobusycheck, com, hz / 100); 2067 com->extra_state |= CSE_BUSYCHECK; 2068 } 2069 (*linesw[tp->t_line].l_start)(tp); 2070 } 2071 if (com_events == 0) 2072 break; 2073 } 2074 if (com_events >= LOTS_OF_EVENTS) 2075 goto repeat; 2076} 2077 2078static int 2079comparam(tp, t) 2080 struct tty *tp; 2081 struct termios *t; 2082{ 2083 u_int cfcr; 2084 int cflag; 2085 struct com_s *com; 2086 int divisor; 2087 u_char dlbh; 2088 u_char dlbl; 2089 Port_t iobase; 2090 int s; 2091 int unit; 2092 2093 /* do historical conversions */ 2094 if (t->c_ispeed == 0) 2095 t->c_ispeed = t->c_ospeed; 2096 2097 /* check requested parameters */ 2098 divisor = ttspeedtab(t->c_ospeed, comspeedtab); 2099 if (divisor < 0 || (divisor > 0 && t->c_ispeed != t->c_ospeed)) 2100 return (EINVAL); 2101 2102 /* parameters are OK, convert them to the com struct and the device */ 2103 unit = DEV_TO_UNIT(tp->t_dev); 2104 com = com_addr(unit); 2105 iobase = com->iobase; 2106 s = spltty(); 2107 if (divisor == 0) 2108 (void)commctl(com, TIOCM_DTR, DMBIC); /* hang up line */ 2109 else 2110 (void)commctl(com, TIOCM_DTR, DMBIS); 2111 cflag = t->c_cflag; 2112 switch (cflag & CSIZE) { 2113 case CS5: 2114 cfcr = CFCR_5BITS; 2115 break; 2116 case CS6: 2117 cfcr = CFCR_6BITS; 2118 break; 2119 case CS7: 2120 cfcr = CFCR_7BITS; 2121 break; 2122 default: 2123 cfcr = CFCR_8BITS; 2124 break; 2125 } 2126 if (cflag & PARENB) { 2127 cfcr |= CFCR_PENAB; 2128 if (!(cflag & PARODD)) 2129 cfcr |= CFCR_PEVEN; 2130 } 2131 if (cflag & CSTOPB) 2132 cfcr |= CFCR_STOPB; 2133 2134 if (com->hasfifo && divisor != 0) { 2135 /* 2136 * Use a fifo trigger level low enough so that the input 2137 * latency from the fifo is less than about 16 msec and 2138 * the total latency is less than about 30 msec. These 2139 * latencies are reasonable for humans. Serial comms 2140 * protocols shouldn't expect anything better since modem 2141 * latencies are larger. 2142 */ 2143 com->fifo_image = t->c_ospeed <= 4800 2144 ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_HIGH; 2145#ifdef COM_ESP 2146 /* 2147 * The Hayes ESP card needs the fifo DMA mode bit set 2148 * in compatibility mode. If not, it will interrupt 2149 * for each character received. 2150 */ 2151 if (com->esp) 2152 com->fifo_image |= FIFO_DMA_MODE; 2153#endif 2154 outb(iobase + com_fifo, com->fifo_image); 2155 } 2156 2157 /* 2158 * This returns with interrupts disabled so that we can complete 2159 * the speed change atomically. Keeping interrupts disabled is 2160 * especially important while com_data is hidden. 2161 */ 2162 (void) siosetwater(com, t->c_ispeed); 2163 2164 if (divisor != 0) { 2165 outb(iobase + com_cfcr, cfcr | CFCR_DLAB); 2166 /* 2167 * Only set the divisor registers if they would change, 2168 * since on some 16550 incompatibles (UMC8669F), setting 2169 * them while input is arriving them loses sync until 2170 * data stops arriving. 2171 */ 2172 dlbl = divisor & 0xFF; 2173 if (inb(iobase + com_dlbl) != dlbl) 2174 outb(iobase + com_dlbl, dlbl); 2175 dlbh = (u_int) divisor >> 8; 2176 if (inb(iobase + com_dlbh) != dlbh) 2177 outb(iobase + com_dlbh, dlbh); 2178 } 2179 2180 2181 outb(iobase + com_cfcr, com->cfcr_image = cfcr); 2182 2183 if (!(tp->t_state & TS_TTSTOP)) 2184 com->state |= CS_TTGO; 2185 2186 if (cflag & CRTS_IFLOW) { 2187 if (com->st16650a) { 2188 outb(iobase + com_cfcr, 0xbf); 2189 outb(iobase + com_fifo, inb(iobase + com_fifo) | 0x40); 2190 } 2191 com->state |= CS_RTS_IFLOW; 2192 /* 2193 * If CS_RTS_IFLOW just changed from off to on, the change 2194 * needs to be propagated to MCR_RTS. This isn't urgent, 2195 * so do it later by calling comstart() instead of repeating 2196 * a lot of code from comstart() here. 2197 */ 2198 } else if (com->state & CS_RTS_IFLOW) { 2199 com->state &= ~CS_RTS_IFLOW; 2200 /* 2201 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS 2202 * on here, since comstart() won't do it later. 2203 */ 2204 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2205 if (com->st16650a) { 2206 outb(iobase + com_cfcr, 0xbf); 2207 outb(iobase + com_fifo, inb(iobase + com_fifo) & ~0x40); 2208 } 2209 } 2210 2211 2212 /* 2213 * Set up state to handle output flow control. 2214 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level? 2215 * Now has 10+ msec latency, while CTS flow has 50- usec latency. 2216 */ 2217 com->state |= CS_ODEVREADY; 2218 com->state &= ~CS_CTS_OFLOW; 2219 if (cflag & CCTS_OFLOW) { 2220 com->state |= CS_CTS_OFLOW; 2221 if (!(com->last_modem_status & MSR_CTS)) 2222 com->state &= ~CS_ODEVREADY; 2223 if (com->st16650a) { 2224 outb(iobase + com_cfcr, 0xbf); 2225 outb(iobase + com_fifo, inb(iobase + com_fifo) | 0x80); 2226 } 2227 } else { 2228 if (com->st16650a) { 2229 outb(iobase + com_cfcr, 0xbf); 2230 outb(iobase + com_fifo, inb(iobase + com_fifo) & ~0x80); 2231 } 2232 } 2233 2234 2235 outb(iobase + com_cfcr, com->cfcr_image); 2236 2237 2238 /* XXX shouldn't call functions while intrs are disabled. */ 2239 disc_optim(tp, t, com); 2240 /* 2241 * Recover from fiddling with CS_TTGO. We used to call siointr1() 2242 * unconditionally, but that defeated the careful discarding of 2243 * stale input in sioopen(). 2244 */ 2245 if (com->state >= (CS_BUSY | CS_TTGO)) 2246 siointr1(com); 2247 2248 enable_intr(); 2249 splx(s); 2250 comstart(tp); 2251 if (com->ibufold != NULL) { 2252 free(com->ibufold, M_DEVBUF); 2253 com->ibufold = NULL; 2254 } 2255 return (0); 2256} 2257 2258static int 2259siosetwater(com, speed) 2260 struct com_s *com; 2261 speed_t speed; 2262{ 2263 int cp4ticks; 2264 u_char *ibuf; 2265 int ibufsize; 2266 struct tty *tp; 2267 2268 /* 2269 * Make the buffer size large enough to handle a softtty interrupt 2270 * latency of about 2 ticks without loss of throughput or data 2271 * (about 3 ticks if input flow control is not used or not honoured, 2272 * but a bit less for CS5-CS7 modes). 2273 */ 2274 cp4ticks = speed / 10 / hz * 4; 2275 for (ibufsize = 128; ibufsize < cp4ticks;) 2276 ibufsize <<= 1; 2277 if (ibufsize == com->ibufsize) { 2278 disable_intr(); 2279 return (0); 2280 } 2281 2282 /* 2283 * Allocate input buffer. The extra factor of 2 in the size is 2284 * to allow for an error byte for each input byte. 2285 */ 2286 ibuf = malloc(2 * ibufsize, M_DEVBUF, M_NOWAIT); 2287 if (ibuf == NULL) { 2288 disable_intr(); 2289 return (ENOMEM); 2290 } 2291 2292 /* Initialize non-critical variables. */ 2293 com->ibufold = com->ibuf; 2294 com->ibufsize = ibufsize; 2295 tp = com->tp; 2296 if (tp != NULL) { 2297 tp->t_ififosize = 2 * ibufsize; 2298 tp->t_ispeedwat = (speed_t)-1; 2299 tp->t_ospeedwat = (speed_t)-1; 2300 } 2301 2302 /* 2303 * Read current input buffer, if any. Continue with interrupts 2304 * disabled. 2305 */ 2306 disable_intr(); 2307 if (com->iptr != com->ibuf) 2308 sioinput(com); 2309 2310 /*- 2311 * Initialize critical variables, including input buffer watermarks. 2312 * The external device is asked to stop sending when the buffer 2313 * exactly reaches high water, or when the high level requests it. 2314 * The high level is notified immediately (rather than at a later 2315 * clock tick) when this watermark is reached. 2316 * The buffer size is chosen so the watermark should almost never 2317 * be reached. 2318 * The low watermark is invisibly 0 since the buffer is always 2319 * emptied all at once. 2320 */ 2321 com->iptr = com->ibuf = ibuf; 2322 com->ibufend = ibuf + ibufsize; 2323 com->ierroff = ibufsize; 2324 com->ihighwater = ibuf + 3 * ibufsize / 4; 2325 return (0); 2326} 2327 2328static void 2329comstart(tp) 2330 struct tty *tp; 2331{ 2332 struct com_s *com; 2333 int s; 2334 int unit; 2335 2336 unit = DEV_TO_UNIT(tp->t_dev); 2337 com = com_addr(unit); 2338 s = spltty(); 2339 disable_intr(); 2340 if (tp->t_state & TS_TTSTOP) 2341 com->state &= ~CS_TTGO; 2342 else 2343 com->state |= CS_TTGO; 2344 if (tp->t_state & TS_TBLOCK) { 2345 if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW) 2346 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS); 2347 } else { 2348 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater 2349 && com->state & CS_RTS_IFLOW) 2350 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2351 } 2352 enable_intr(); 2353 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) { 2354 ttwwakeup(tp); 2355 splx(s); 2356 return; 2357 } 2358 if (tp->t_outq.c_cc != 0) { 2359 struct lbq *qp; 2360 struct lbq *next; 2361 2362 if (!com->obufs[0].l_queued) { 2363 com->obufs[0].l_tail 2364 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1, 2365 sizeof com->obuf1); 2366 com->obufs[0].l_next = NULL; 2367 com->obufs[0].l_queued = TRUE; 2368 disable_intr(); 2369 if (com->state & CS_BUSY) { 2370 qp = com->obufq.l_next; 2371 while ((next = qp->l_next) != NULL) 2372 qp = next; 2373 qp->l_next = &com->obufs[0]; 2374 } else { 2375 com->obufq.l_head = com->obufs[0].l_head; 2376 com->obufq.l_tail = com->obufs[0].l_tail; 2377 com->obufq.l_next = &com->obufs[0]; 2378 com->state |= CS_BUSY; 2379 } 2380 enable_intr(); 2381 } 2382 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) { 2383 com->obufs[1].l_tail 2384 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2, 2385 sizeof com->obuf2); 2386 com->obufs[1].l_next = NULL; 2387 com->obufs[1].l_queued = TRUE; 2388 disable_intr(); 2389 if (com->state & CS_BUSY) { 2390 qp = com->obufq.l_next; 2391 while ((next = qp->l_next) != NULL) 2392 qp = next; 2393 qp->l_next = &com->obufs[1]; 2394 } else { 2395 com->obufq.l_head = com->obufs[1].l_head; 2396 com->obufq.l_tail = com->obufs[1].l_tail; 2397 com->obufq.l_next = &com->obufs[1]; 2398 com->state |= CS_BUSY; 2399 } 2400 enable_intr(); 2401 } 2402 tp->t_state |= TS_BUSY; 2403 } 2404 disable_intr(); 2405 if (com->state >= (CS_BUSY | CS_TTGO)) 2406 siointr1(com); /* fake interrupt to start output */ 2407 enable_intr(); 2408 ttwwakeup(tp); 2409 splx(s); 2410} 2411 2412static void 2413comstop(tp, rw) 2414 struct tty *tp; 2415 int rw; 2416{ 2417 struct com_s *com; 2418 2419 com = com_addr(DEV_TO_UNIT(tp->t_dev)); 2420 if (com->gone) 2421 return; 2422 disable_intr(); 2423 if (rw & FWRITE) { 2424 if (com->hasfifo) 2425#ifdef COM_ESP 2426 /* XXX avoid h/w bug. */ 2427 if (!com->esp) 2428#endif 2429 outb(com->iobase + com_fifo, 2430 FIFO_XMT_RST | com->fifo_image); 2431 com->obufs[0].l_queued = FALSE; 2432 com->obufs[1].l_queued = FALSE; 2433 if (com->state & CS_ODONE) 2434 com_events -= LOTS_OF_EVENTS; 2435 com->state &= ~(CS_ODONE | CS_BUSY); 2436 com->tp->t_state &= ~TS_BUSY; 2437 } 2438 if (rw & FREAD) { 2439 if (com->hasfifo) 2440#ifdef COM_ESP 2441 /* XXX avoid h/w bug. */ 2442 if (!com->esp) 2443#endif 2444 outb(com->iobase + com_fifo, 2445 FIFO_RCV_RST | com->fifo_image); 2446 com_events -= (com->iptr - com->ibuf); 2447 com->iptr = com->ibuf; 2448 } 2449 enable_intr(); 2450 comstart(tp); 2451} 2452 2453static int 2454commctl(com, bits, how) 2455 struct com_s *com; 2456 int bits; 2457 int how; 2458{ 2459 int mcr; 2460 int msr; 2461 2462 if (how == DMGET) { 2463 bits = TIOCM_LE; /* XXX - always enabled while open */ 2464 mcr = com->mcr_image; 2465 if (mcr & MCR_DTR) 2466 bits |= TIOCM_DTR; 2467 if (mcr & MCR_RTS) 2468 bits |= TIOCM_RTS; 2469 msr = com->prev_modem_status; 2470 if (msr & MSR_CTS) 2471 bits |= TIOCM_CTS; 2472 if (msr & MSR_DCD) 2473 bits |= TIOCM_CD; 2474 if (msr & MSR_DSR) 2475 bits |= TIOCM_DSR; 2476 /* 2477 * XXX - MSR_RI is naturally volatile, and we make MSR_TERI 2478 * more volatile by reading the modem status a lot. Perhaps 2479 * we should latch both bits until the status is read here. 2480 */ 2481 if (msr & (MSR_RI | MSR_TERI)) 2482 bits |= TIOCM_RI; 2483 return (bits); 2484 } 2485 mcr = 0; 2486 if (bits & TIOCM_DTR) 2487 mcr |= MCR_DTR; 2488 if (bits & TIOCM_RTS) 2489 mcr |= MCR_RTS; 2490 if (com->gone) 2491 return(0); 2492 disable_intr(); 2493 switch (how) { 2494 case DMSET: 2495 outb(com->modem_ctl_port, 2496 com->mcr_image = mcr | (com->mcr_image & MCR_IENABLE)); 2497 break; 2498 case DMBIS: 2499 outb(com->modem_ctl_port, com->mcr_image |= mcr); 2500 break; 2501 case DMBIC: 2502 outb(com->modem_ctl_port, com->mcr_image &= ~mcr); 2503 break; 2504 } 2505 enable_intr(); 2506 return (0); 2507} 2508 2509static void 2510siosettimeout() 2511{ 2512 struct com_s *com; 2513 bool_t someopen; 2514 int unit; 2515 2516 /* 2517 * Set our timeout period to 1 second if no polled devices are open. 2518 * Otherwise set it to max(1/200, 1/hz). 2519 * Enable timeouts iff some device is open. 2520 */ 2521 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 2522 sio_timeout = hz; 2523 someopen = FALSE; 2524 for (unit = 0; unit < sio_numunits; ++unit) { 2525 com = com_addr(unit); 2526 if (com != NULL && com->tp != NULL 2527 && com->tp->t_state & TS_ISOPEN && !com->gone) { 2528 someopen = TRUE; 2529 if (com->poll || com->poll_output) { 2530 sio_timeout = hz > 200 ? hz / 200 : 1; 2531 break; 2532 } 2533 } 2534 } 2535 if (someopen) { 2536 sio_timeouts_until_log = hz / sio_timeout; 2537 sio_timeout_handle = timeout(comwakeup, (void *)NULL, 2538 sio_timeout); 2539 } else { 2540 /* Flush error messages, if any. */ 2541 sio_timeouts_until_log = 1; 2542 comwakeup((void *)NULL); 2543 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 2544 } 2545} 2546 2547static void 2548comwakeup(chan) 2549 void *chan; 2550{ 2551 struct com_s *com; 2552 int unit; 2553 2554 sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout); 2555 2556 /* 2557 * Recover from lost output interrupts. 2558 * Poll any lines that don't use interrupts. 2559 */ 2560 for (unit = 0; unit < sio_numunits; ++unit) { 2561 com = com_addr(unit); 2562 if (com != NULL && !com->gone 2563 && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) { 2564 disable_intr(); 2565 siointr1(com); 2566 enable_intr(); 2567 } 2568 } 2569 2570 /* 2571 * Check for and log errors, but not too often. 2572 */ 2573 if (--sio_timeouts_until_log > 0) 2574 return; 2575 sio_timeouts_until_log = hz / sio_timeout; 2576 for (unit = 0; unit < sio_numunits; ++unit) { 2577 int errnum; 2578 2579 com = com_addr(unit); 2580 if (com == NULL) 2581 continue; 2582 if (com->gone) 2583 continue; 2584 for (errnum = 0; errnum < CE_NTYPES; ++errnum) { 2585 u_int delta; 2586 u_long total; 2587 2588 disable_intr(); 2589 delta = com->delta_error_counts[errnum]; 2590 com->delta_error_counts[errnum] = 0; 2591 enable_intr(); 2592 if (delta == 0) 2593 continue; 2594 total = com->error_counts[errnum] += delta; 2595 log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n", 2596 unit, delta, error_desc[errnum], 2597 delta == 1 ? "" : "s", total); 2598 } 2599 } 2600} 2601 2602static void 2603disc_optim(tp, t, com) 2604 struct tty *tp; 2605 struct termios *t; 2606 struct com_s *com; 2607{ 2608 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON)) 2609 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK)) 2610 && (!(t->c_iflag & PARMRK) 2611 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK)) 2612 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN)) 2613 && linesw[tp->t_line].l_rint == ttyinput) 2614 tp->t_state |= TS_CAN_BYPASS_L_RINT; 2615 else 2616 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 2617 com->hotchar = linesw[tp->t_line].l_hotchar; 2618} 2619 2620/* 2621 * Following are all routines needed for SIO to act as console 2622 */ 2623#include <sys/cons.h> 2624 2625struct siocnstate { 2626 u_char dlbl; 2627 u_char dlbh; 2628 u_char ier; 2629 u_char cfcr; 2630 u_char mcr; 2631}; 2632 2633static speed_t siocngetspeed __P((Port_t, struct speedtab *)); 2634static void siocnclose __P((struct siocnstate *sp, Port_t iobase)); 2635static void siocnopen __P((struct siocnstate *sp, Port_t iobase, int speed)); 2636static void siocntxwait __P((Port_t iobase)); 2637 2638static cn_probe_t siocnprobe; 2639static cn_init_t siocninit; 2640static cn_checkc_t siocncheckc; 2641static cn_getc_t siocngetc; 2642static cn_putc_t siocnputc; 2643 2644#ifdef __i386__ 2645CONS_DRIVER(sio, siocnprobe, siocninit, NULL, siocngetc, siocncheckc, siocnputc); 2646 2647#endif 2648 2649/* To get the GDB related variables */ 2650#if DDB > 0 2651#include <ddb/ddb.h> 2652#endif 2653 2654static void 2655siocntxwait(iobase) 2656 Port_t iobase; 2657{ 2658 int timo; 2659 2660 /* 2661 * Wait for any pending transmission to finish. Required to avoid 2662 * the UART lockup bug when the speed is changed, and for normal 2663 * transmits. 2664 */ 2665 timo = 100000; 2666 while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY)) 2667 != (LSR_TSRE | LSR_TXRDY) && --timo != 0) 2668 ; 2669} 2670 2671/* 2672 * Read the serial port specified and try to figure out what speed 2673 * it's currently running at. We're assuming the serial port has 2674 * been initialized and is basicly idle. This routine is only intended 2675 * to be run at system startup. 2676 * 2677 * If the value read from the serial port doesn't make sense, return 0. 2678 */ 2679 2680static speed_t 2681siocngetspeed(iobase, table) 2682 Port_t iobase; 2683 struct speedtab *table; 2684{ 2685 int code; 2686 u_char dlbh; 2687 u_char dlbl; 2688 u_char cfcr; 2689 2690 cfcr = inb(iobase + com_cfcr); 2691 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 2692 2693 dlbl = inb(iobase + com_dlbl); 2694 dlbh = inb(iobase + com_dlbh); 2695 2696 outb(iobase + com_cfcr, cfcr); 2697 2698 code = dlbh << 8 | dlbl; 2699 2700 for (; table->sp_speed != -1; table++) 2701 if (table->sp_code == code) 2702 return (table->sp_speed); 2703 2704 return 0; /* didn't match anything sane */ 2705} 2706 2707static void 2708siocnopen(sp, iobase, speed) 2709 struct siocnstate *sp; 2710 Port_t iobase; 2711 int speed; 2712{ 2713 int divisor; 2714 u_char dlbh; 2715 u_char dlbl; 2716 2717 /* 2718 * Save all the device control registers except the fifo register 2719 * and set our default ones (cs8 -parenb speed=comdefaultrate). 2720 * We can't save the fifo register since it is read-only. 2721 */ 2722 sp->ier = inb(iobase + com_ier); 2723 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */ 2724 siocntxwait(iobase); 2725 sp->cfcr = inb(iobase + com_cfcr); 2726 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 2727 sp->dlbl = inb(iobase + com_dlbl); 2728 sp->dlbh = inb(iobase + com_dlbh); 2729 /* 2730 * Only set the divisor registers if they would change, since on 2731 * some 16550 incompatibles (Startech), setting them clears the 2732 * data input register. This also reduces the effects of the 2733 * UMC8669F bug. 2734 */ 2735 divisor = ttspeedtab(speed, comspeedtab); 2736 dlbl = divisor & 0xFF; 2737 if (sp->dlbl != dlbl) 2738 outb(iobase + com_dlbl, dlbl); 2739 dlbh = (u_int) divisor >> 8; 2740 if (sp->dlbh != dlbh) 2741 outb(iobase + com_dlbh, dlbh); 2742 outb(iobase + com_cfcr, CFCR_8BITS); 2743 sp->mcr = inb(iobase + com_mcr); 2744 /* 2745 * We don't want interrupts, but must be careful not to "disable" 2746 * them by clearing the MCR_IENABLE bit, since that might cause 2747 * an interrupt by floating the IRQ line. 2748 */ 2749 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS); 2750} 2751 2752static void 2753siocnclose(sp, iobase) 2754 struct siocnstate *sp; 2755 Port_t iobase; 2756{ 2757 /* 2758 * Restore the device control registers. 2759 */ 2760 siocntxwait(iobase); 2761 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 2762 if (sp->dlbl != inb(iobase + com_dlbl)) 2763 outb(iobase + com_dlbl, sp->dlbl); 2764 if (sp->dlbh != inb(iobase + com_dlbh)) 2765 outb(iobase + com_dlbh, sp->dlbh); 2766 outb(iobase + com_cfcr, sp->cfcr); 2767 /* 2768 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them. 2769 */ 2770 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS); 2771 outb(iobase + com_ier, sp->ier); 2772} 2773 2774static void 2775siocnprobe(cp) 2776 struct consdev *cp; 2777{ 2778 speed_t boot_speed; 2779 u_char cfcr; 2780 int s, unit; 2781 struct siocnstate sp; 2782 2783 /* 2784 * Find our first enabled console, if any. If it is a high-level 2785 * console device, then initialize it and return successfully. 2786 * If it is a low-level console device, then initialize it and 2787 * return unsuccessfully. It must be initialized in both cases 2788 * for early use by console drivers and debuggers. Initializing 2789 * the hardware is not necessary in all cases, since the i/o 2790 * routines initialize it on the fly, but it is necessary if 2791 * input might arrive while the hardware is switched back to an 2792 * uninitialized state. We can't handle multiple console devices 2793 * yet because our low-level routines don't take a device arg. 2794 * We trust the user to set the console flags properly so that we 2795 * don't need to probe. 2796 */ 2797 cp->cn_pri = CN_DEAD; 2798 2799 for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */ 2800 int flags; 2801 int disabled; 2802 if (resource_int_value("sio", unit, "disabled", &disabled) == 0) { 2803 if (disabled) 2804 continue; 2805 } 2806 if (resource_int_value("sio", unit, "flags", &flags)) 2807 continue; 2808 if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) { 2809 int port; 2810 Port_t iobase; 2811 2812 if (resource_int_value("sio", unit, "port", &port)) 2813 continue; 2814 iobase = port; 2815 s = spltty(); 2816 if (boothowto & RB_SERIAL) { 2817 boot_speed = siocngetspeed(iobase, comspeedtab); 2818 if (boot_speed) 2819 comdefaultrate = boot_speed; 2820 } 2821 2822 /* 2823 * Initialize the divisor latch. We can't rely on 2824 * siocnopen() to do this the first time, since it 2825 * avoids writing to the latch if the latch appears 2826 * to have the correct value. Also, if we didn't 2827 * just read the speed from the hardware, then we 2828 * need to set the speed in hardware so that 2829 * switching it later is null. 2830 */ 2831 cfcr = inb(iobase + com_cfcr); 2832 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 2833 outb(iobase + com_dlbl, 2834 COMBRD(comdefaultrate) & 0xff); 2835 outb(iobase + com_dlbh, 2836 (u_int) COMBRD(comdefaultrate) >> 8); 2837 outb(iobase + com_cfcr, cfcr); 2838 2839 siocnopen(&sp, iobase, comdefaultrate); 2840 2841 splx(s); 2842 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) { 2843 cp->cn_dev = makedev(CDEV_MAJOR, unit); 2844 cp->cn_pri = COM_FORCECONSOLE(flags) 2845 || boothowto & RB_SERIAL 2846 ? CN_REMOTE : CN_NORMAL; 2847 siocniobase = iobase; 2848 siocnunit = unit; 2849 } 2850 if (COM_DEBUGGER(flags)) { 2851 printf("sio%d: gdb debugging port\n", unit); 2852 siogdbiobase = iobase; 2853 siogdbunit = unit; 2854#if DDB > 0 2855 gdbdev = makedev(CDEV_MAJOR, unit); 2856 gdb_getc = siocngetc; 2857 gdb_putc = siocnputc; 2858#endif 2859 } 2860 } 2861 } 2862#ifdef __i386__ 2863#if DDB > 0 2864 /* 2865 * XXX Ugly Compatability. 2866 * If no gdb port has been specified, set it to be the console 2867 * as some configuration files don't specify the gdb port. 2868 */ 2869 if (gdbdev == NODEV && (boothowto & RB_GDB)) { 2870 printf("Warning: no GDB port specified. Defaulting to sio%d.\n", 2871 siocnunit); 2872 printf("Set flag 0x80 on desired GDB port in your\n"); 2873 printf("configuration file (currently sio only).\n"); 2874 siogdbiobase = siocniobase; 2875 siogdbunit = siocnunit; 2876 gdbdev = makedev(CDEV_MAJOR, siocnunit); 2877 gdb_getc = siocngetc; 2878 gdb_putc = siocnputc; 2879 } 2880#endif 2881#endif 2882} 2883 2884#ifdef __alpha__ 2885 2886CONS_DRIVER(sio, NULL, NULL, NULL, siocngetc, siocncheckc, siocnputc); 2887 2888int 2889siocnattach(port, speed) 2890 int port; 2891 int speed; 2892{ 2893 int s; 2894 u_char cfcr; 2895 struct siocnstate sp; 2896 2897 siocniobase = port; 2898 comdefaultrate = speed; 2899 sio_consdev.cn_pri = CN_NORMAL; 2900 sio_consdev.cn_dev = makedev(CDEV_MAJOR, 0); 2901 2902 s = spltty(); 2903 2904 /* 2905 * Initialize the divisor latch. We can't rely on 2906 * siocnopen() to do this the first time, since it 2907 * avoids writing to the latch if the latch appears 2908 * to have the correct value. Also, if we didn't 2909 * just read the speed from the hardware, then we 2910 * need to set the speed in hardware so that 2911 * switching it later is null. 2912 */ 2913 cfcr = inb(siocniobase + com_cfcr); 2914 outb(siocniobase + com_cfcr, CFCR_DLAB | cfcr); 2915 outb(siocniobase + com_dlbl, 2916 COMBRD(comdefaultrate) & 0xff); 2917 outb(siocniobase + com_dlbh, 2918 (u_int) COMBRD(comdefaultrate) >> 8); 2919 outb(siocniobase + com_cfcr, cfcr); 2920 2921 siocnopen(&sp, siocniobase, comdefaultrate); 2922 splx(s); 2923 2924 cn_tab = &sio_consdev; 2925 return 0; 2926} 2927 2928int 2929siogdbattach(port, speed) 2930 int port; 2931 int speed; 2932{ 2933 int s; 2934 u_char cfcr; 2935 struct siocnstate sp; 2936 2937 siogdbiobase = port; 2938 gdbdefaultrate = speed; 2939 2940 s = spltty(); 2941 2942 /* 2943 * Initialize the divisor latch. We can't rely on 2944 * siocnopen() to do this the first time, since it 2945 * avoids writing to the latch if the latch appears 2946 * to have the correct value. Also, if we didn't 2947 * just read the speed from the hardware, then we 2948 * need to set the speed in hardware so that 2949 * switching it later is null. 2950 */ 2951 cfcr = inb(siogdbiobase + com_cfcr); 2952 outb(siogdbiobase + com_cfcr, CFCR_DLAB | cfcr); 2953 outb(siogdbiobase + com_dlbl, 2954 COMBRD(gdbdefaultrate) & 0xff); 2955 outb(siogdbiobase + com_dlbh, 2956 (u_int) COMBRD(gdbdefaultrate) >> 8); 2957 outb(siogdbiobase + com_cfcr, cfcr); 2958 2959 siocnopen(&sp, siogdbiobase, gdbdefaultrate); 2960 splx(s); 2961 2962 return 0; 2963} 2964 2965#endif 2966 2967static void 2968siocninit(cp) 2969 struct consdev *cp; 2970{ 2971 comconsole = DEV_TO_UNIT(cp->cn_dev); 2972} 2973 2974static int 2975siocncheckc(dev) 2976 dev_t dev; 2977{ 2978 int c; 2979 Port_t iobase; 2980 int s; 2981 struct siocnstate sp; 2982 2983 if (minor(dev) == siogdbunit) 2984 iobase = siogdbiobase; 2985 else 2986 iobase = siocniobase; 2987 s = spltty(); 2988 siocnopen(&sp, iobase, comdefaultrate); 2989 if (inb(iobase + com_lsr) & LSR_RXRDY) 2990 c = inb(iobase + com_data); 2991 else 2992 c = -1; 2993 siocnclose(&sp, iobase); 2994 splx(s); 2995 return (c); 2996} 2997 2998 2999int 3000siocngetc(dev) 3001 dev_t dev; 3002{ 3003 int c; 3004 Port_t iobase; 3005 int s; 3006 struct siocnstate sp; 3007 3008 if (minor(dev) == siogdbunit) 3009 iobase = siogdbiobase; 3010 else 3011 iobase = siocniobase; 3012 s = spltty(); 3013 siocnopen(&sp, iobase, comdefaultrate); 3014 while (!(inb(iobase + com_lsr) & LSR_RXRDY)) 3015 ; 3016 c = inb(iobase + com_data); 3017 siocnclose(&sp, iobase); 3018 splx(s); 3019 return (c); 3020} 3021 3022void 3023siocnputc(dev, c) 3024 dev_t dev; 3025 int c; 3026{ 3027 int s; 3028 struct siocnstate sp; 3029 Port_t iobase; 3030 3031 if (minor(dev) == siogdbunit) 3032 iobase = siogdbiobase; 3033 else 3034 iobase = siocniobase; 3035 s = spltty(); 3036 siocnopen(&sp, iobase, comdefaultrate); 3037 siocntxwait(iobase); 3038 outb(iobase + com_data, c); 3039 siocnclose(&sp, iobase); 3040 splx(s); 3041} 3042 3043#ifdef __alpha__ 3044int 3045siogdbgetc() 3046{ 3047 int c; 3048 Port_t iobase; 3049 int s; 3050 struct siocnstate sp; 3051 3052 iobase = siogdbiobase; 3053 s = spltty(); 3054 siocnopen(&sp, iobase, gdbdefaultrate); 3055 while (!(inb(iobase + com_lsr) & LSR_RXRDY)) 3056 ; 3057 c = inb(iobase + com_data); 3058 siocnclose(&sp, iobase); 3059 splx(s); 3060 return (c); 3061} 3062 3063void 3064siogdbputc(c) 3065 int c; 3066{ 3067 int s; 3068 struct siocnstate sp; 3069 3070 s = spltty(); 3071 siocnopen(&sp, siogdbiobase, gdbdefaultrate); 3072 siocntxwait(siogdbiobase); 3073 outb(siogdbiobase + com_data, c); 3074 siocnclose(&sp, siogdbiobase); 3075 splx(s); 3076} 3077#endif 3078 3079DRIVER_MODULE(sio, isa, sio_isa_driver, sio_devclass, 0, 0); 3080#if NCARD > 0 3081DRIVER_MODULE(sio, pccard, sio_pccard_driver, sio_devclass, 0, 0); 3082#endif 3083