sio.c revision 218424
1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 4. Neither the name of the University nor the names of its contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: @(#)com.c 7.5 (Berkeley) 5/16/91 30 * from: i386/isa sio.c,v 1.234 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/sio/sio.c 218424 2011-02-08 00:16:36Z mdf $"); 35 36#include "opt_comconsole.h" 37#include "opt_compat.h" 38#include "opt_gdb.h" 39#include "opt_kdb.h" 40#include "opt_sio.h" 41 42/* 43 * Serial driver, based on 386BSD-0.1 com driver. 44 * Mostly rewritten to use pseudo-DMA. 45 * Works for National Semiconductor NS8250-NS16550AF UARTs. 46 * COM driver, based on HP dca driver. 47 * 48 * Changes for PC Card integration: 49 * - Added PC Card driver table and handlers 50 */ 51#include <sys/param.h> 52#include <sys/systm.h> 53#include <sys/bus.h> 54#include <sys/conf.h> 55#include <sys/fcntl.h> 56#include <sys/interrupt.h> 57#include <sys/kdb.h> 58#include <sys/kernel.h> 59#include <sys/limits.h> 60#include <sys/lock.h> 61#include <sys/malloc.h> 62#include <sys/module.h> 63#include <sys/mutex.h> 64#include <sys/proc.h> 65#include <sys/reboot.h> 66#include <sys/serial.h> 67#include <sys/sysctl.h> 68#include <sys/syslog.h> 69#include <sys/tty.h> 70#include <machine/bus.h> 71#include <sys/rman.h> 72#include <sys/timepps.h> 73#include <sys/uio.h> 74#include <sys/cons.h> 75 76#include <isa/isavar.h> 77 78#include <machine/resource.h> 79 80#include <dev/sio/sioreg.h> 81#include <dev/sio/siovar.h> 82 83#ifdef COM_ESP 84#include <dev/ic/esp.h> 85#endif 86#include <dev/ic/ns16550.h> 87 88#define LOTS_OF_EVENTS 64 /* helps separate urgent events from input */ 89 90#ifdef COM_MULTIPORT 91/* checks in flags for multiport and which is multiport "master chip" 92 * for a given card 93 */ 94#define COM_ISMULTIPORT(flags) ((flags) & 0x01) 95#define COM_MPMASTER(flags) (((flags) >> 8) & 0x0ff) 96#define COM_NOTAST4(flags) ((flags) & 0x04) 97#else 98#define COM_ISMULTIPORT(flags) (0) 99#endif /* COM_MULTIPORT */ 100 101#define COM_C_IIR_TXRDYBUG 0x80000 102#define COM_CONSOLE(flags) ((flags) & 0x10) 103#define COM_DEBUGGER(flags) ((flags) & 0x80) 104#define COM_FIFOSIZE(flags) (((flags) & 0xff000000) >> 24) 105#define COM_FORCECONSOLE(flags) ((flags) & 0x20) 106#define COM_IIR_TXRDYBUG(flags) ((flags) & COM_C_IIR_TXRDYBUG) 107#define COM_LLCONSOLE(flags) ((flags) & 0x40) 108#define COM_LOSESOUTINTS(flags) ((flags) & 0x08) 109#define COM_NOFIFO(flags) ((flags) & 0x02) 110#define COM_NOPROBE(flags) ((flags) & 0x40000) 111#define COM_NOSCR(flags) ((flags) & 0x100000) 112#define COM_PPSCTS(flags) ((flags) & 0x10000) 113#define COM_ST16650A(flags) ((flags) & 0x20000) 114#define COM_TI16754(flags) ((flags) & 0x200000) 115 116#define sio_getreg(com, off) \ 117 (bus_space_read_1((com)->bst, (com)->bsh, (off))) 118#define sio_setreg(com, off, value) \ 119 (bus_space_write_1((com)->bst, (com)->bsh, (off), (value))) 120 121/* 122 * com state bits. 123 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher 124 * than the other bits so that they can be tested as a group without masking 125 * off the low bits. 126 * 127 * The following com and tty flags correspond closely: 128 * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and 129 * comstop()) 130 * CS_TTGO = ~TS_TTSTOP (maintained by comparam() and comstart()) 131 * CS_CTS_OFLOW = CCTS_OFLOW (maintained by comparam()) 132 * CS_RTS_IFLOW = CRTS_IFLOW (maintained by comparam()) 133 * TS_FLUSH is not used. 134 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON. 135 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state). 136 */ 137#define CS_BUSY 0x80 /* output in progress */ 138#define CS_TTGO 0x40 /* output not stopped by XOFF */ 139#define CS_ODEVREADY 0x20 /* external device h/w ready (CTS) */ 140#define CS_CHECKMSR 1 /* check of MSR scheduled */ 141#define CS_CTS_OFLOW 2 /* use CTS output flow control */ 142#define CS_ODONE 4 /* output completed */ 143#define CS_RTS_IFLOW 8 /* use RTS input flow control */ 144#define CSE_BUSYCHECK 1 /* siobusycheck() scheduled */ 145 146static char const * const error_desc[] = { 147#define CE_OVERRUN 0 148 "silo overflow", 149#define CE_INTERRUPT_BUF_OVERFLOW 1 150 "interrupt-level buffer overflow", 151#define CE_TTY_BUF_OVERFLOW 2 152 "tty-level buffer overflow", 153}; 154 155#define CE_NTYPES 3 156#define CE_RECORD(com, errnum) (++(com)->delta_error_counts[errnum]) 157 158/* types. XXX - should be elsewhere */ 159typedef u_int Port_t; /* hardware port */ 160typedef u_char bool_t; /* boolean */ 161 162/* queue of linear buffers */ 163struct lbq { 164 u_char *l_head; /* next char to process */ 165 u_char *l_tail; /* one past the last char to process */ 166 struct lbq *l_next; /* next in queue */ 167 bool_t l_queued; /* nonzero if queued */ 168}; 169 170/* com device structure */ 171struct com_s { 172 u_char state; /* miscellaneous flag bits */ 173 u_char cfcr_image; /* copy of value written to CFCR */ 174#ifdef COM_ESP 175 bool_t esp; /* is this unit a hayes esp board? */ 176#endif 177 u_char extra_state; /* more flag bits, separate for order trick */ 178 u_char fifo_image; /* copy of value written to FIFO */ 179 bool_t hasfifo; /* nonzero for 16550 UARTs */ 180 bool_t loses_outints; /* nonzero if device loses output interrupts */ 181 u_char mcr_image; /* copy of value written to MCR */ 182#ifdef COM_MULTIPORT 183 bool_t multiport; /* is this unit part of a multiport device? */ 184#endif /* COM_MULTIPORT */ 185 bool_t no_irq; /* nonzero if irq is not attached */ 186 bool_t gone; /* hardware disappeared */ 187 bool_t poll; /* nonzero if polling is required */ 188 bool_t poll_output; /* nonzero if polling for output is required */ 189 bool_t st16650a; /* nonzero if Startech 16650A compatible */ 190 int unit; /* unit number */ 191 u_int flags; /* copy of device flags */ 192 u_int tx_fifo_size; 193 194 /* 195 * The high level of the driver never reads status registers directly 196 * because there would be too many side effects to handle conveniently. 197 * Instead, it reads copies of the registers stored here by the 198 * interrupt handler. 199 */ 200 u_char last_modem_status; /* last MSR read by intr handler */ 201 u_char prev_modem_status; /* last MSR handled by high level */ 202 203 u_char *ibuf; /* start of input buffer */ 204 u_char *ibufend; /* end of input buffer */ 205 u_char *ibufold; /* old input buffer, to be freed */ 206 u_char *ihighwater; /* threshold in input buffer */ 207 u_char *iptr; /* next free spot in input buffer */ 208 int ibufsize; /* size of ibuf (not include error bytes) */ 209 int ierroff; /* offset of error bytes in ibuf */ 210 211 struct lbq obufq; /* head of queue of output buffers */ 212 struct lbq obufs[2]; /* output buffers */ 213 214 bus_space_tag_t bst; 215 bus_space_handle_t bsh; 216 217 Port_t data_port; /* i/o ports */ 218#ifdef COM_ESP 219 Port_t esp_port; 220#endif 221 Port_t int_ctl_port; 222 Port_t int_id_port; 223 Port_t modem_ctl_port; 224 Port_t line_status_port; 225 Port_t modem_status_port; 226 227 struct tty *tp; /* cross reference */ 228 229 struct pps_state pps; 230 int pps_bit; 231#ifdef ALT_BREAK_TO_DEBUGGER 232 int alt_brk_state; 233#endif 234 235 u_long bytes_in; /* statistics */ 236 u_long bytes_out; 237 u_int delta_error_counts[CE_NTYPES]; 238 u_long error_counts[CE_NTYPES]; 239 240 u_long rclk; 241 242 struct resource *irqres; 243 struct resource *ioportres; 244 int ioportrid; 245 void *cookie; 246 247 /* 248 * Data area for output buffers. Someday we should build the output 249 * buffer queue without copying data. 250 */ 251 u_char obuf1[256]; 252 u_char obuf2[256]; 253}; 254 255#ifdef COM_ESP 256static int espattach(struct com_s *com, Port_t esp_port); 257#endif 258 259static void combreak(struct tty *tp, int sig); 260static timeout_t siobusycheck; 261static u_int siodivisor(u_long rclk, speed_t speed); 262static void comclose(struct tty *tp); 263static int comopen(struct tty *tp, struct cdev *dev); 264static void sioinput(struct com_s *com); 265static void siointr1(struct com_s *com); 266static int siointr(void *arg); 267static int commodem(struct tty *tp, int sigon, int sigoff); 268static int comparam(struct tty *tp, struct termios *t); 269static void siopoll(void *); 270static void siosettimeout(void); 271static int siosetwater(struct com_s *com, speed_t speed); 272static void comstart(struct tty *tp); 273static void comstop(struct tty *tp, int rw); 274static timeout_t comwakeup; 275 276char sio_driver_name[] = "sio"; 277static struct mtx sio_lock; 278static int sio_inited; 279 280/* table and macro for fast conversion from a unit number to its com struct */ 281devclass_t sio_devclass; 282#define com_addr(unit) ((struct com_s *) \ 283 devclass_get_softc(sio_devclass, unit)) /* XXX */ 284 285int comconsole = -1; 286static volatile speed_t comdefaultrate = CONSPEED; 287static u_long comdefaultrclk = DEFAULT_RCLK; 288SYSCTL_ULONG(_machdep, OID_AUTO, conrclk, CTLFLAG_RW, &comdefaultrclk, 0, ""); 289static speed_t gdbdefaultrate = GDBSPEED; 290SYSCTL_UINT(_machdep, OID_AUTO, gdbspeed, CTLFLAG_RW, 291 &gdbdefaultrate, GDBSPEED, ""); 292static u_int com_events; /* input chars + weighted output completions */ 293static Port_t siocniobase; 294static int siocnunit = -1; 295static void *sio_slow_ih; 296static void *sio_fast_ih; 297static int sio_timeout; 298static int sio_timeouts_until_log; 299static struct callout_handle sio_timeout_handle 300 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle); 301static int sio_numunits; 302 303#ifdef GDB 304static Port_t siogdbiobase = 0; 305#endif 306 307#ifdef COM_ESP 308/* XXX configure this properly. */ 309/* XXX quite broken for new-bus. */ 310static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, }; 311static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 }; 312#endif 313 314/* 315 * handle sysctl read/write requests for console speed 316 * 317 * In addition to setting comdefaultrate for I/O through /dev/console, 318 * also set the initial and lock values for the /dev/ttyXX device 319 * if there is one associated with the console. Finally, if the /dev/tty 320 * device has already been open, change the speed on the open running port 321 * itself. 322 */ 323 324static int 325sysctl_machdep_comdefaultrate(SYSCTL_HANDLER_ARGS) 326{ 327 int error, s; 328 speed_t newspeed; 329 struct com_s *com; 330 struct tty *tp; 331 332 newspeed = comdefaultrate; 333 334 error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req); 335 if (error || !req->newptr) 336 return (error); 337 338 comdefaultrate = newspeed; 339 340 if (comconsole < 0) /* serial console not selected? */ 341 return (0); 342 343 com = com_addr(comconsole); 344 if (com == NULL) 345 return (ENXIO); 346 347 tp = com->tp; 348 if (tp == NULL) 349 return (ENXIO); 350 351 /* 352 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX 353 * (note, the lock rates really are boolean -- if non-zero, disallow 354 * speed changes) 355 */ 356 tp->t_init_in.c_ispeed = tp->t_init_in.c_ospeed = 357 tp->t_lock_in.c_ispeed = tp->t_lock_in.c_ospeed = 358 tp->t_init_out.c_ispeed = tp->t_init_out.c_ospeed = 359 tp->t_lock_out.c_ispeed = tp->t_lock_out.c_ospeed = comdefaultrate; 360 361 if (tp->t_state & TS_ISOPEN) { 362 tp->t_termios.c_ispeed = 363 tp->t_termios.c_ospeed = comdefaultrate; 364 s = spltty(); 365 error = comparam(tp, &tp->t_termios); 366 splx(s); 367 } 368 return error; 369} 370 371SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW, 372 0, 0, sysctl_machdep_comdefaultrate, "I", ""); 373TUNABLE_INT("machdep.conspeed", __DEVOLATILE(int *, &comdefaultrate)); 374 375#define SET_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) | (bit)) 376#define CLR_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) & ~(bit)) 377 378/* 379 * Unload the driver and clear the table. 380 * XXX this is mostly wrong. 381 * XXX TODO: 382 * This is usually called when the card is ejected, but 383 * can be caused by a kldunload of a controller driver. 384 * The idea is to reset the driver's view of the device 385 * and ensure that any driver entry points such as 386 * read and write do not hang. 387 */ 388int 389siodetach(device_t dev) 390{ 391 struct com_s *com; 392 393 com = (struct com_s *) device_get_softc(dev); 394 if (com == NULL) { 395 device_printf(dev, "NULL com in siounload\n"); 396 return (0); 397 } 398 com->gone = TRUE; 399 if (com->tp) 400 ttyfree(com->tp); 401 if (com->irqres) { 402 bus_teardown_intr(dev, com->irqres, com->cookie); 403 bus_release_resource(dev, SYS_RES_IRQ, 0, com->irqres); 404 } 405 if (com->ioportres) 406 bus_release_resource(dev, SYS_RES_IOPORT, com->ioportrid, 407 com->ioportres); 408 if (com->ibuf != NULL) 409 free(com->ibuf, M_DEVBUF); 410 411 device_set_softc(dev, NULL); 412 free(com, M_DEVBUF); 413 return (0); 414} 415 416int 417sioprobe(dev, xrid, rclk, noprobe) 418 device_t dev; 419 int xrid; 420 u_long rclk; 421 int noprobe; 422{ 423#if 0 424 static bool_t already_init; 425 device_t xdev; 426#endif 427 struct com_s *com; 428 u_int divisor; 429 bool_t failures[10]; 430 int fn; 431 device_t idev; 432 Port_t iobase; 433 intrmask_t irqmap[4]; 434 intrmask_t irqs; 435 u_char mcr_image; 436 int result; 437 u_long xirq; 438 u_int flags = device_get_flags(dev); 439 int rid; 440 struct resource *port; 441 442 rid = xrid; 443 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 444 0, ~0, IO_COMSIZE, RF_ACTIVE); 445 if (!port) 446 return (ENXIO); 447 448 com = malloc(sizeof(*com), M_DEVBUF, M_NOWAIT | M_ZERO); 449 if (com == NULL) { 450 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 451 return (ENOMEM); 452 } 453 device_set_softc(dev, com); 454 com->bst = rman_get_bustag(port); 455 com->bsh = rman_get_bushandle(port); 456 if (rclk == 0) 457 rclk = DEFAULT_RCLK; 458 com->rclk = rclk; 459 460 while (sio_inited != 2) 461 if (atomic_cmpset_int(&sio_inited, 0, 1)) { 462 mtx_init(&sio_lock, sio_driver_name, NULL, 463 (comconsole != -1) ? 464 MTX_SPIN | MTX_QUIET : MTX_SPIN); 465 atomic_store_rel_int(&sio_inited, 2); 466 } 467 468#if 0 469 /* 470 * XXX this is broken - when we are first called, there are no 471 * previously configured IO ports. We could hard code 472 * 0x3f8, 0x2f8, 0x3e8, 0x2e8 etc but that's probably worse. 473 * This code has been doing nothing since the conversion since 474 * "count" is zero the first time around. 475 */ 476 if (!already_init) { 477 /* 478 * Turn off MCR_IENABLE for all likely serial ports. An unused 479 * port with its MCR_IENABLE gate open will inhibit interrupts 480 * from any used port that shares the interrupt vector. 481 * XXX the gate enable is elsewhere for some multiports. 482 */ 483 device_t *devs; 484 int count, i, xioport; 485 486 devclass_get_devices(sio_devclass, &devs, &count); 487 for (i = 0; i < count; i++) { 488 xdev = devs[i]; 489 if (device_is_enabled(xdev) && 490 bus_get_resource(xdev, SYS_RES_IOPORT, 0, &xioport, 491 NULL) == 0) 492 outb(xioport + com_mcr, 0); 493 } 494 free(devs, M_TEMP); 495 already_init = TRUE; 496 } 497#endif 498 499 if (COM_LLCONSOLE(flags)) { 500 printf("sio%d: reserved for low-level i/o\n", 501 device_get_unit(dev)); 502 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 503 device_set_softc(dev, NULL); 504 free(com, M_DEVBUF); 505 return (ENXIO); 506 } 507 508 /* 509 * If the device is on a multiport card and has an AST/4 510 * compatible interrupt control register, initialize this 511 * register and prepare to leave MCR_IENABLE clear in the mcr. 512 * Otherwise, prepare to set MCR_IENABLE in the mcr. 513 * Point idev to the device struct giving the correct id_irq. 514 * This is the struct for the master device if there is one. 515 */ 516 idev = dev; 517 mcr_image = MCR_IENABLE; 518#ifdef COM_MULTIPORT 519 if (COM_ISMULTIPORT(flags)) { 520 Port_t xiobase; 521 u_long io; 522 523 idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags)); 524 if (idev == NULL) { 525 printf("sio%d: master device %d not configured\n", 526 device_get_unit(dev), COM_MPMASTER(flags)); 527 idev = dev; 528 } 529 if (!COM_NOTAST4(flags)) { 530 if (bus_get_resource(idev, SYS_RES_IOPORT, 0, &io, 531 NULL) == 0) { 532 xiobase = io; 533 if (bus_get_resource(idev, SYS_RES_IRQ, 0, 534 NULL, NULL) == 0) 535 outb(xiobase + com_scr, 0x80); 536 else 537 outb(xiobase + com_scr, 0); 538 } 539 mcr_image = 0; 540 } 541 } 542#endif /* COM_MULTIPORT */ 543 if (bus_get_resource(idev, SYS_RES_IRQ, 0, NULL, NULL) != 0) 544 mcr_image = 0; 545 546 bzero(failures, sizeof failures); 547 iobase = rman_get_start(port); 548 549 /* 550 * We don't want to get actual interrupts, just masked ones. 551 * Interrupts from this line should already be masked in the ICU, 552 * but mask them in the processor as well in case there are some 553 * (misconfigured) shared interrupts. 554 */ 555 mtx_lock_spin(&sio_lock); 556/* EXTRA DELAY? */ 557 558 /* 559 * For the TI16754 chips, set prescaler to 1 (4 is often the 560 * default after-reset value) as otherwise it's impossible to 561 * get highest baudrates. 562 */ 563 if (COM_TI16754(flags)) { 564 u_char cfcr, efr; 565 566 cfcr = sio_getreg(com, com_cfcr); 567 sio_setreg(com, com_cfcr, CFCR_EFR_ENABLE); 568 efr = sio_getreg(com, com_efr); 569 /* Unlock extended features to turn off prescaler. */ 570 sio_setreg(com, com_efr, efr | EFR_EFE); 571 /* Disable EFR. */ 572 sio_setreg(com, com_cfcr, (cfcr != CFCR_EFR_ENABLE) ? cfcr : 0); 573 /* Turn off prescaler. */ 574 sio_setreg(com, com_mcr, 575 sio_getreg(com, com_mcr) & ~MCR_PRESCALE); 576 sio_setreg(com, com_cfcr, CFCR_EFR_ENABLE); 577 sio_setreg(com, com_efr, efr); 578 sio_setreg(com, com_cfcr, cfcr); 579 } 580 581 /* 582 * Initialize the speed and the word size and wait long enough to 583 * drain the maximum of 16 bytes of junk in device output queues. 584 * The speed is undefined after a master reset and must be set 585 * before relying on anything related to output. There may be 586 * junk after a (very fast) soft reboot and (apparently) after 587 * master reset. 588 * XXX what about the UART bug avoided by waiting in comparam()? 589 * We don't want to to wait long enough to drain at 2 bps. 590 */ 591 if (iobase == siocniobase) 592 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10)); 593 else { 594 sio_setreg(com, com_cfcr, CFCR_DLAB | CFCR_8BITS); 595 divisor = siodivisor(rclk, SIO_TEST_SPEED); 596 sio_setreg(com, com_dlbl, divisor & 0xff); 597 sio_setreg(com, com_dlbh, divisor >> 8); 598 sio_setreg(com, com_cfcr, CFCR_8BITS); 599 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10)); 600 } 601 602 /* 603 * Enable the interrupt gate and disable device interrupts. This 604 * should leave the device driving the interrupt line low and 605 * guarantee an edge trigger if an interrupt can be generated. 606 */ 607/* EXTRA DELAY? */ 608 sio_setreg(com, com_mcr, mcr_image); 609 sio_setreg(com, com_ier, 0); 610 DELAY(1000); /* XXX */ 611 irqmap[0] = isa_irq_pending(); 612 613 /* 614 * Attempt to set loopback mode so that we can send a null byte 615 * without annoying any external device. 616 */ 617/* EXTRA DELAY? */ 618 sio_setreg(com, com_mcr, mcr_image | MCR_LOOPBACK); 619 620 /* 621 * Attempt to generate an output interrupt. On 8250's, setting 622 * IER_ETXRDY generates an interrupt independent of the current 623 * setting and independent of whether the THR is empty. On 16450's, 624 * setting IER_ETXRDY generates an interrupt independent of the 625 * current setting. On 16550A's, setting IER_ETXRDY only 626 * generates an interrupt when IER_ETXRDY is not already set. 627 */ 628 sio_setreg(com, com_ier, IER_ETXRDY); 629 630 /* 631 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate 632 * an interrupt. They'd better generate one for actually doing 633 * output. Loopback may be broken on the same incompatibles but 634 * it's unlikely to do more than allow the null byte out. 635 */ 636 sio_setreg(com, com_data, 0); 637 if (iobase == siocniobase) 638 DELAY((1 + 2) * 1000000 / (comdefaultrate / 10)); 639 else 640 DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10)); 641 642 /* 643 * Turn off loopback mode so that the interrupt gate works again 644 * (MCR_IENABLE was hidden). This should leave the device driving 645 * an interrupt line high. It doesn't matter if the interrupt 646 * line oscillates while we are not looking at it, since interrupts 647 * are disabled. 648 */ 649/* EXTRA DELAY? */ 650 sio_setreg(com, com_mcr, mcr_image); 651 652 /* 653 * It seems my Xircom CBEM56G Cardbus modem wants to be reset 654 * to 8 bits *again*, or else probe test 0 will fail. 655 * gwk@sgi.com, 4/19/2001 656 */ 657 sio_setreg(com, com_cfcr, CFCR_8BITS); 658 659 /* 660 * Some PCMCIA cards (Palido 321s, DC-1S, ...) have the "TXRDY bug", 661 * so we probe for a buggy IIR_TXRDY implementation even in the 662 * noprobe case. We don't probe for it in the !noprobe case because 663 * noprobe is always set for PCMCIA cards and the problem is not 664 * known to affect any other cards. 665 */ 666 if (noprobe) { 667 /* Read IIR a few times. */ 668 for (fn = 0; fn < 2; fn ++) { 669 DELAY(10000); 670 failures[6] = sio_getreg(com, com_iir); 671 } 672 673 /* IIR_TXRDY should be clear. Is it? */ 674 result = 0; 675 if (failures[6] & IIR_TXRDY) { 676 /* 677 * No. We seem to have the bug. Does our fix for 678 * it work? 679 */ 680 sio_setreg(com, com_ier, 0); 681 if (sio_getreg(com, com_iir) & IIR_NOPEND) { 682 /* Yes. We discovered the TXRDY bug! */ 683 SET_FLAG(dev, COM_C_IIR_TXRDYBUG); 684 } else { 685 /* No. Just fail. XXX */ 686 result = ENXIO; 687 sio_setreg(com, com_mcr, 0); 688 } 689 } else { 690 /* Yes. No bug. */ 691 CLR_FLAG(dev, COM_C_IIR_TXRDYBUG); 692 } 693 sio_setreg(com, com_ier, 0); 694 sio_setreg(com, com_cfcr, CFCR_8BITS); 695 mtx_unlock_spin(&sio_lock); 696 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 697 if (iobase == siocniobase) 698 result = 0; 699 /* 700 * XXX: Since we don't return 0, we shouldn't be relying on 701 * the softc that we set to persist to the call to attach 702 * since other probe routines may be called, and the malloc 703 * here causes subr_bus to not allocate anything for the 704 * other probes. Instead, this softc is preserved and other 705 * probe routines can corrupt it. 706 */ 707 if (result != 0) { 708 device_set_softc(dev, NULL); 709 free(com, M_DEVBUF); 710 } 711 return (result == 0 ? BUS_PROBE_DEFAULT + 1 : result); 712 } 713 714 /* 715 * Check that 716 * o the CFCR, IER and MCR in UART hold the values written to them 717 * (the values happen to be all distinct - this is good for 718 * avoiding false positive tests from bus echoes). 719 * o an output interrupt is generated and its vector is correct. 720 * o the interrupt goes away when the IIR in the UART is read. 721 */ 722/* EXTRA DELAY? */ 723 failures[0] = sio_getreg(com, com_cfcr) - CFCR_8BITS; 724 failures[1] = sio_getreg(com, com_ier) - IER_ETXRDY; 725 failures[2] = sio_getreg(com, com_mcr) - mcr_image; 726 DELAY(10000); /* Some internal modems need this time */ 727 irqmap[1] = isa_irq_pending(); 728 failures[4] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_TXRDY; 729 DELAY(1000); /* XXX */ 730 irqmap[2] = isa_irq_pending(); 731 failures[6] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND; 732 733 /* 734 * Turn off all device interrupts and check that they go off properly. 735 * Leave MCR_IENABLE alone. For ports without a master port, it gates 736 * the OUT2 output of the UART to 737 * the ICU input. Closing the gate would give a floating ICU input 738 * (unless there is another device driving it) and spurious interrupts. 739 * (On the system that this was first tested on, the input floats high 740 * and gives a (masked) interrupt as soon as the gate is closed.) 741 */ 742 sio_setreg(com, com_ier, 0); 743 sio_setreg(com, com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */ 744 failures[7] = sio_getreg(com, com_ier); 745 DELAY(1000); /* XXX */ 746 irqmap[3] = isa_irq_pending(); 747 failures[9] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND; 748 749 mtx_unlock_spin(&sio_lock); 750 751 irqs = irqmap[1] & ~irqmap[0]; 752 if (bus_get_resource(idev, SYS_RES_IRQ, 0, &xirq, NULL) == 0 && 753 ((1 << xirq) & irqs) == 0) { 754 printf( 755 "sio%d: configured irq %ld not in bitmap of probed irqs %#x\n", 756 device_get_unit(dev), xirq, irqs); 757 printf( 758 "sio%d: port may not be enabled\n", 759 device_get_unit(dev)); 760 } 761 if (bootverbose) 762 printf("sio%d: irq maps: %#x %#x %#x %#x\n", 763 device_get_unit(dev), 764 irqmap[0], irqmap[1], irqmap[2], irqmap[3]); 765 766 result = 0; 767 for (fn = 0; fn < sizeof failures; ++fn) 768 if (failures[fn]) { 769 sio_setreg(com, com_mcr, 0); 770 result = ENXIO; 771 if (bootverbose) { 772 printf("sio%d: probe failed test(s):", 773 device_get_unit(dev)); 774 for (fn = 0; fn < sizeof failures; ++fn) 775 if (failures[fn]) 776 printf(" %d", fn); 777 printf("\n"); 778 } 779 break; 780 } 781 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 782 if (iobase == siocniobase) 783 result = 0; 784 /* 785 * XXX: Since we don't return 0, we shouldn't be relying on the softc 786 * that we set to persist to the call to attach since other probe 787 * routines may be called, and the malloc here causes subr_bus to not 788 * allocate anything for the other probes. Instead, this softc is 789 * preserved and other probe routines can corrupt it. 790 */ 791 if (result != 0) { 792 device_set_softc(dev, NULL); 793 free(com, M_DEVBUF); 794 } 795 return (result == 0 ? BUS_PROBE_DEFAULT + 1 : result); 796} 797 798#ifdef COM_ESP 799static int 800espattach(com, esp_port) 801 struct com_s *com; 802 Port_t esp_port; 803{ 804 u_char dips; 805 u_char val; 806 807 /* 808 * Check the ESP-specific I/O port to see if we're an ESP 809 * card. If not, return failure immediately. 810 */ 811 if ((inb(esp_port) & 0xf3) == 0) { 812 printf(" port 0x%x is not an ESP board?\n", esp_port); 813 return (0); 814 } 815 816 /* 817 * We've got something that claims to be a Hayes ESP card. 818 * Let's hope so. 819 */ 820 821 /* Get the dip-switch configuration */ 822 outb(esp_port + ESP_CMD1, ESP_GETDIPS); 823 dips = inb(esp_port + ESP_STATUS1); 824 825 /* 826 * Bits 0,1 of dips say which COM port we are. 827 */ 828 if (rman_get_start(com->ioportres) == likely_com_ports[dips & 0x03]) 829 printf(" : ESP"); 830 else { 831 printf(" esp_port has com %d\n", dips & 0x03); 832 return (0); 833 } 834 835 /* 836 * Check for ESP version 2.0 or later: bits 4,5,6 = 010. 837 */ 838 outb(esp_port + ESP_CMD1, ESP_GETTEST); 839 val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */ 840 val = inb(esp_port + ESP_STATUS2); 841 if ((val & 0x70) < 0x20) { 842 printf("-old (%o)", val & 0x70); 843 return (0); 844 } 845 846 /* 847 * Check for ability to emulate 16550: bit 7 == 1 848 */ 849 if ((dips & 0x80) == 0) { 850 printf(" slave"); 851 return (0); 852 } 853 854 /* 855 * Okay, we seem to be a Hayes ESP card. Whee. 856 */ 857 com->esp = TRUE; 858 com->esp_port = esp_port; 859 return (1); 860} 861#endif /* COM_ESP */ 862 863int 864sioattach(dev, xrid, rclk) 865 device_t dev; 866 int xrid; 867 u_long rclk; 868{ 869 struct com_s *com; 870#ifdef COM_ESP 871 Port_t *espp; 872#endif 873 Port_t iobase; 874 int unit; 875 u_int flags; 876 int rid; 877 struct resource *port; 878 int ret; 879 int error; 880 struct tty *tp; 881 882 rid = xrid; 883 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 884 0, ~0, IO_COMSIZE, RF_ACTIVE); 885 if (!port) 886 return (ENXIO); 887 888 iobase = rman_get_start(port); 889 unit = device_get_unit(dev); 890 com = device_get_softc(dev); 891 flags = device_get_flags(dev); 892 893 if (unit >= sio_numunits) 894 sio_numunits = unit + 1; 895 /* 896 * sioprobe() has initialized the device registers as follows: 897 * o cfcr = CFCR_8BITS. 898 * It is most important that CFCR_DLAB is off, so that the 899 * data port is not hidden when we enable interrupts. 900 * o ier = 0. 901 * Interrupts are only enabled when the line is open. 902 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible 903 * interrupt control register or the config specifies no irq. 904 * Keeping MCR_DTR and MCR_RTS off might stop the external 905 * device from sending before we are ready. 906 */ 907 bzero(com, sizeof *com); 908 com->unit = unit; 909 com->ioportres = port; 910 com->ioportrid = rid; 911 com->bst = rman_get_bustag(port); 912 com->bsh = rman_get_bushandle(port); 913 com->cfcr_image = CFCR_8BITS; 914 com->loses_outints = COM_LOSESOUTINTS(flags) != 0; 915 com->no_irq = bus_get_resource(dev, SYS_RES_IRQ, 0, NULL, NULL) != 0; 916 com->tx_fifo_size = 1; 917 com->obufs[0].l_head = com->obuf1; 918 com->obufs[1].l_head = com->obuf2; 919 920 com->data_port = iobase + com_data; 921 com->int_ctl_port = iobase + com_ier; 922 com->int_id_port = iobase + com_iir; 923 com->modem_ctl_port = iobase + com_mcr; 924 com->mcr_image = inb(com->modem_ctl_port); 925 com->line_status_port = iobase + com_lsr; 926 com->modem_status_port = iobase + com_msr; 927 928 tp = com->tp = ttyalloc(); 929 tp->t_oproc = comstart; 930 tp->t_param = comparam; 931 tp->t_stop = comstop; 932 tp->t_modem = commodem; 933 tp->t_break = combreak; 934 tp->t_close = comclose; 935 tp->t_open = comopen; 936 tp->t_sc = com; 937 938 if (rclk == 0) 939 rclk = DEFAULT_RCLK; 940 com->rclk = rclk; 941 942 if (unit == comconsole) 943 ttyconsolemode(tp, comdefaultrate); 944 error = siosetwater(com, tp->t_init_in.c_ispeed); 945 mtx_unlock_spin(&sio_lock); 946 if (error) { 947 /* 948 * Leave i/o resources allocated if this is a `cn'-level 949 * console, so that other devices can't snarf them. 950 */ 951 if (iobase != siocniobase) 952 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 953 return (ENOMEM); 954 } 955 956 /* attempt to determine UART type */ 957 printf("sio%d: type", unit); 958 959 if (!COM_ISMULTIPORT(flags) && 960 !COM_IIR_TXRDYBUG(flags) && !COM_NOSCR(flags)) { 961 u_char scr; 962 u_char scr1; 963 u_char scr2; 964 965 scr = sio_getreg(com, com_scr); 966 sio_setreg(com, com_scr, 0xa5); 967 scr1 = sio_getreg(com, com_scr); 968 sio_setreg(com, com_scr, 0x5a); 969 scr2 = sio_getreg(com, com_scr); 970 sio_setreg(com, com_scr, scr); 971 if (scr1 != 0xa5 || scr2 != 0x5a) { 972 printf(" 8250 or not responding"); 973 goto determined_type; 974 } 975 } 976 sio_setreg(com, com_fifo, FIFO_ENABLE | FIFO_RX_HIGH); 977 DELAY(100); 978 switch (inb(com->int_id_port) & IIR_FIFO_MASK) { 979 case FIFO_RX_LOW: 980 printf(" 16450"); 981 break; 982 case FIFO_RX_MEDL: 983 printf(" 16450?"); 984 break; 985 case FIFO_RX_MEDH: 986 printf(" 16550?"); 987 break; 988 case FIFO_RX_HIGH: 989 if (COM_NOFIFO(flags)) { 990 printf(" 16550A fifo disabled"); 991 break; 992 } 993 com->hasfifo = TRUE; 994 if (COM_ST16650A(flags)) { 995 printf(" ST16650A"); 996 com->st16650a = TRUE; 997 com->tx_fifo_size = 32; 998 break; 999 } 1000 if (COM_TI16754(flags)) { 1001 printf(" TI16754"); 1002 com->tx_fifo_size = 64; 1003 break; 1004 } 1005 printf(" 16550A"); 1006#ifdef COM_ESP 1007 for (espp = likely_esp_ports; *espp != 0; espp++) 1008 if (espattach(com, *espp)) { 1009 com->tx_fifo_size = 1024; 1010 break; 1011 } 1012 if (com->esp) 1013 break; 1014#endif 1015 com->tx_fifo_size = COM_FIFOSIZE(flags); 1016 if (com->tx_fifo_size == 0) 1017 com->tx_fifo_size = 16; 1018 else 1019 printf(" lookalike with %u bytes FIFO", 1020 com->tx_fifo_size); 1021 break; 1022 } 1023#ifdef COM_ESP 1024 if (com->esp) { 1025 /* 1026 * Set 16550 compatibility mode. 1027 * We don't use the ESP_MODE_SCALE bit to increase the 1028 * fifo trigger levels because we can't handle large 1029 * bursts of input. 1030 * XXX flow control should be set in comparam(), not here. 1031 */ 1032 outb(com->esp_port + ESP_CMD1, ESP_SETMODE); 1033 outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO); 1034 1035 /* Set RTS/CTS flow control. */ 1036 outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE); 1037 outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS); 1038 outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS); 1039 1040 /* Set flow-control levels. */ 1041 outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW); 1042 outb(com->esp_port + ESP_CMD2, HIBYTE(768)); 1043 outb(com->esp_port + ESP_CMD2, LOBYTE(768)); 1044 outb(com->esp_port + ESP_CMD2, HIBYTE(512)); 1045 outb(com->esp_port + ESP_CMD2, LOBYTE(512)); 1046 } 1047#endif /* COM_ESP */ 1048 sio_setreg(com, com_fifo, 0); 1049determined_type: ; 1050 1051#ifdef COM_MULTIPORT 1052 if (COM_ISMULTIPORT(flags)) { 1053 device_t masterdev; 1054 1055 com->multiport = TRUE; 1056 printf(" (multiport"); 1057 if (unit == COM_MPMASTER(flags)) 1058 printf(" master"); 1059 printf(")"); 1060 masterdev = devclass_get_device(sio_devclass, 1061 COM_MPMASTER(flags)); 1062 com->no_irq = (masterdev == NULL || bus_get_resource(masterdev, 1063 SYS_RES_IRQ, 0, NULL, NULL) != 0); 1064 } 1065#endif /* COM_MULTIPORT */ 1066 if (unit == comconsole) 1067 printf(", console"); 1068 if (COM_IIR_TXRDYBUG(flags)) 1069 printf(" with a buggy IIR_TXRDY implementation"); 1070 printf("\n"); 1071 1072 if (sio_fast_ih == NULL) { 1073 swi_add(&tty_intr_event, "sio", siopoll, NULL, SWI_TTY, 0, 1074 &sio_fast_ih); 1075 swi_add(&clk_intr_event, "sio", siopoll, NULL, SWI_CLOCK, 0, 1076 &sio_slow_ih); 1077 } 1078 1079 com->flags = flags; 1080 com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 1081 tp->t_pps = &com->pps; 1082 1083 if (COM_PPSCTS(flags)) 1084 com->pps_bit = MSR_CTS; 1085 else 1086 com->pps_bit = MSR_DCD; 1087 pps_init(&com->pps); 1088 1089 rid = 0; 1090 com->irqres = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); 1091 if (com->irqres) { 1092 ret = bus_setup_intr(dev, com->irqres, 1093 INTR_TYPE_TTY, 1094 siointr, NULL, com, 1095 &com->cookie); 1096 if (ret) { 1097 ret = bus_setup_intr(dev, 1098 com->irqres, INTR_TYPE_TTY, 1099 NULL, (driver_intr_t *)siointr, com, &com->cookie); 1100 if (ret == 0) 1101 device_printf(dev, "unable to activate interrupt in fast mode - using normal mode\n"); 1102 } 1103 if (ret) 1104 device_printf(dev, "could not activate interrupt\n"); 1105#if defined(KDB) && (defined(BREAK_TO_DEBUGGER) || \ 1106 defined(ALT_BREAK_TO_DEBUGGER)) 1107 /* 1108 * Enable interrupts for early break-to-debugger support 1109 * on the console. 1110 */ 1111 if (ret == 0 && unit == comconsole) 1112 outb(siocniobase + com_ier, IER_ERXRDY | IER_ERLS | 1113 IER_EMSC); 1114#endif 1115 } 1116 1117 /* We're ready, open the doors... */ 1118 ttycreate(tp, TS_CALLOUT, "d%r", unit); 1119 1120 return (0); 1121} 1122 1123static int 1124comopen(struct tty *tp, struct cdev *dev) 1125{ 1126 struct com_s *com; 1127 int i; 1128 1129 com = tp->t_sc; 1130 com->poll = com->no_irq; 1131 com->poll_output = com->loses_outints; 1132 if (com->hasfifo) { 1133 /* 1134 * (Re)enable and drain fifos. 1135 * 1136 * Certain SMC chips cause problems if the fifos 1137 * are enabled while input is ready. Turn off the 1138 * fifo if necessary to clear the input. We test 1139 * the input ready bit after enabling the fifos 1140 * since we've already enabled them in comparam() 1141 * and to handle races between enabling and fresh 1142 * input. 1143 */ 1144 for (i = 0; i < 500; i++) { 1145 sio_setreg(com, com_fifo, 1146 FIFO_RCV_RST | FIFO_XMT_RST 1147 | com->fifo_image); 1148 /* 1149 * XXX the delays are for superstitious 1150 * historical reasons. It must be less than 1151 * the character time at the maximum 1152 * supported speed (87 usec at 115200 bps 1153 * 8N1). Otherwise we might loop endlessly 1154 * if data is streaming in. We used to use 1155 * delays of 100. That usually worked 1156 * because DELAY(100) used to usually delay 1157 * for about 85 usec instead of 100. 1158 */ 1159 DELAY(50); 1160 if (!(inb(com->line_status_port) & LSR_RXRDY)) 1161 break; 1162 sio_setreg(com, com_fifo, 0); 1163 DELAY(50); 1164 (void) inb(com->data_port); 1165 } 1166 if (i == 500) 1167 return (EIO); 1168 } 1169 1170 mtx_lock_spin(&sio_lock); 1171 (void) inb(com->line_status_port); 1172 (void) inb(com->data_port); 1173 com->prev_modem_status = com->last_modem_status 1174 = inb(com->modem_status_port); 1175 outb(com->int_ctl_port, 1176 IER_ERXRDY | IER_ERLS | IER_EMSC 1177 | (COM_IIR_TXRDYBUG(com->flags) ? 0 : IER_ETXRDY)); 1178 mtx_unlock_spin(&sio_lock); 1179 siosettimeout(); 1180 /* XXX: should be generic ? */ 1181 if (com->prev_modem_status & MSR_DCD || ISCALLOUT(dev)) 1182 ttyld_modem(tp, 1); 1183 return (0); 1184} 1185 1186static void 1187comclose(tp) 1188 struct tty *tp; 1189{ 1190 int s; 1191 struct com_s *com; 1192 1193 s = spltty(); 1194 com = tp->t_sc; 1195 com->poll = FALSE; 1196 com->poll_output = FALSE; 1197 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 1198 1199#if defined(KDB) && (defined(BREAK_TO_DEBUGGER) || \ 1200 defined(ALT_BREAK_TO_DEBUGGER)) 1201 /* 1202 * Leave interrupts enabled and don't clear DTR if this is the 1203 * console. This allows us to detect break-to-debugger events 1204 * while the console device is closed. 1205 */ 1206 if (com->unit != comconsole) 1207#endif 1208 { 1209 sio_setreg(com, com_ier, 0); 1210 if (tp->t_cflag & HUPCL 1211 /* 1212 * XXX we will miss any carrier drop between here and the 1213 * next open. Perhaps we should watch DCD even when the 1214 * port is closed; it is not sufficient to check it at 1215 * the next open because it might go up and down while 1216 * we're not watching. 1217 */ 1218 || (!tp->t_actout 1219 && !(com->prev_modem_status & MSR_DCD) 1220 && !(tp->t_init_in.c_cflag & CLOCAL)) 1221 || !(tp->t_state & TS_ISOPEN)) { 1222 (void)commodem(tp, 0, SER_DTR); 1223 ttydtrwaitstart(tp); 1224 } 1225 } 1226 if (com->hasfifo) { 1227 /* 1228 * Disable fifos so that they are off after controlled 1229 * reboots. Some BIOSes fail to detect 16550s when the 1230 * fifos are enabled. 1231 */ 1232 sio_setreg(com, com_fifo, 0); 1233 } 1234 tp->t_actout = FALSE; 1235 wakeup(&tp->t_actout); 1236 wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */ 1237 siosettimeout(); 1238 splx(s); 1239} 1240 1241static void 1242siobusycheck(chan) 1243 void *chan; 1244{ 1245 struct com_s *com; 1246 int s; 1247 1248 com = (struct com_s *)chan; 1249 1250 /* 1251 * Clear TS_BUSY if low-level output is complete. 1252 * spl locking is sufficient because siointr1() does not set CS_BUSY. 1253 * If siointr1() clears CS_BUSY after we look at it, then we'll get 1254 * called again. Reading the line status port outside of siointr1() 1255 * is safe because CS_BUSY is clear so there are no output interrupts 1256 * to lose. 1257 */ 1258 s = spltty(); 1259 if (com->state & CS_BUSY) 1260 com->extra_state &= ~CSE_BUSYCHECK; /* False alarm. */ 1261 else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY)) 1262 == (LSR_TSRE | LSR_TXRDY)) { 1263 com->tp->t_state &= ~TS_BUSY; 1264 ttwwakeup(com->tp); 1265 com->extra_state &= ~CSE_BUSYCHECK; 1266 } else 1267 timeout(siobusycheck, com, hz / 100); 1268 splx(s); 1269} 1270 1271static u_int 1272siodivisor(rclk, speed) 1273 u_long rclk; 1274 speed_t speed; 1275{ 1276 long actual_speed; 1277 u_int divisor; 1278 int error; 1279 1280 if (speed == 0) 1281 return (0); 1282#if UINT_MAX > (ULONG_MAX - 1) / 8 1283 if (speed > (ULONG_MAX - 1) / 8) 1284 return (0); 1285#endif 1286 divisor = (rclk / (8UL * speed) + 1) / 2; 1287 if (divisor == 0 || divisor >= 65536) 1288 return (0); 1289 actual_speed = rclk / (16UL * divisor); 1290 1291 /* 10 times error in percent: */ 1292 error = ((actual_speed - (long)speed) * 2000 / (long)speed + 1) / 2; 1293 1294 /* 3.0% maximum error tolerance: */ 1295 if (error < -30 || error > 30) 1296 return (0); 1297 1298 return (divisor); 1299} 1300 1301/* 1302 * Call this function with the sio_lock mutex held. It will return with the 1303 * lock still held. 1304 */ 1305static void 1306sioinput(com) 1307 struct com_s *com; 1308{ 1309 u_char *buf; 1310 int incc; 1311 u_char line_status; 1312 int recv_data; 1313 struct tty *tp; 1314 1315 buf = com->ibuf; 1316 tp = com->tp; 1317 if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) { 1318 com_events -= (com->iptr - com->ibuf); 1319 com->iptr = com->ibuf; 1320 return; 1321 } 1322 if (tp->t_state & TS_CAN_BYPASS_L_RINT) { 1323 /* 1324 * Avoid the grotesquely inefficient lineswitch routine 1325 * (ttyinput) in "raw" mode. It usually takes about 450 1326 * instructions (that's without canonical processing or echo!). 1327 * slinput is reasonably fast (usually 40 instructions plus 1328 * call overhead). 1329 */ 1330 do { 1331 /* 1332 * This may look odd, but it is using save-and-enable 1333 * semantics instead of the save-and-disable semantics 1334 * that are used everywhere else. 1335 */ 1336 mtx_unlock_spin(&sio_lock); 1337 incc = com->iptr - buf; 1338 if (tp->t_rawq.c_cc + incc > tp->t_ihiwat 1339 && (com->state & CS_RTS_IFLOW 1340 || tp->t_iflag & IXOFF) 1341 && !(tp->t_state & TS_TBLOCK)) 1342 ttyblock(tp); 1343 com->delta_error_counts[CE_TTY_BUF_OVERFLOW] 1344 += b_to_q((char *)buf, incc, &tp->t_rawq); 1345 buf += incc; 1346 tk_nin += incc; 1347 tk_rawcc += incc; 1348 tp->t_rawcc += incc; 1349 ttwakeup(tp); 1350 if (tp->t_state & TS_TTSTOP 1351 && (tp->t_iflag & IXANY 1352 || tp->t_cc[VSTART] == tp->t_cc[VSTOP])) { 1353 tp->t_state &= ~TS_TTSTOP; 1354 tp->t_lflag &= ~FLUSHO; 1355 comstart(tp); 1356 } 1357 mtx_lock_spin(&sio_lock); 1358 } while (buf < com->iptr); 1359 } else { 1360 do { 1361 /* 1362 * This may look odd, but it is using save-and-enable 1363 * semantics instead of the save-and-disable semantics 1364 * that are used everywhere else. 1365 */ 1366 mtx_unlock_spin(&sio_lock); 1367 line_status = buf[com->ierroff]; 1368 recv_data = *buf++; 1369 if (line_status 1370 & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) { 1371 if (line_status & LSR_BI) 1372 recv_data |= TTY_BI; 1373 if (line_status & LSR_FE) 1374 recv_data |= TTY_FE; 1375 if (line_status & LSR_OE) 1376 recv_data |= TTY_OE; 1377 if (line_status & LSR_PE) 1378 recv_data |= TTY_PE; 1379 } 1380 ttyld_rint(tp, recv_data); 1381 mtx_lock_spin(&sio_lock); 1382 } while (buf < com->iptr); 1383 } 1384 com_events -= (com->iptr - com->ibuf); 1385 com->iptr = com->ibuf; 1386 1387 /* 1388 * There is now room for another low-level buffer full of input, 1389 * so enable RTS if it is now disabled and there is room in the 1390 * high-level buffer. 1391 */ 1392 if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) && 1393 !(tp->t_state & TS_TBLOCK)) 1394 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 1395} 1396 1397static int 1398siointr(arg) 1399 void *arg; 1400{ 1401 struct com_s *com; 1402 1403#ifndef COM_MULTIPORT 1404 com = (struct com_s *)arg; 1405 1406 mtx_lock_spin(&sio_lock); 1407 siointr1(com); 1408 mtx_unlock_spin(&sio_lock); 1409#else /* COM_MULTIPORT */ 1410 bool_t possibly_more_intrs; 1411 int unit; 1412 1413 /* 1414 * Loop until there is no activity on any port. This is necessary 1415 * to get an interrupt edge more than to avoid another interrupt. 1416 * If the IRQ signal is just an OR of the IRQ signals from several 1417 * devices, then the edge from one may be lost because another is 1418 * on. 1419 */ 1420 mtx_lock_spin(&sio_lock); 1421 do { 1422 possibly_more_intrs = FALSE; 1423 for (unit = 0; unit < sio_numunits; ++unit) { 1424 com = com_addr(unit); 1425 /* 1426 * XXX COM_LOCK(); 1427 * would it work here, or be counter-productive? 1428 */ 1429 if (com != NULL 1430 && !com->gone 1431 && (inb(com->int_id_port) & IIR_IMASK) 1432 != IIR_NOPEND) { 1433 siointr1(com); 1434 possibly_more_intrs = TRUE; 1435 } 1436 /* XXX COM_UNLOCK(); */ 1437 } 1438 } while (possibly_more_intrs); 1439 mtx_unlock_spin(&sio_lock); 1440#endif /* COM_MULTIPORT */ 1441 return(FILTER_HANDLED); 1442} 1443 1444static struct timespec siots[8]; 1445static int siotso; 1446static int volatile siotsunit = -1; 1447 1448static int 1449sysctl_siots(SYSCTL_HANDLER_ARGS) 1450{ 1451 char buf[128]; 1452 long long delta; 1453 size_t len; 1454 int error, i, tso; 1455 1456 for (i = 1, tso = siotso; i < tso; i++) { 1457 delta = (long long)(siots[i].tv_sec - siots[i - 1].tv_sec) * 1458 1000000000 + 1459 (siots[i].tv_nsec - siots[i - 1].tv_nsec); 1460 len = sprintf(buf, "%lld\n", delta); 1461 if (delta >= 110000) 1462 len += sprintf(buf + len - 1, ": *** %ld.%09ld\n", 1463 (long)siots[i].tv_sec, siots[i].tv_nsec) - 1; 1464 if (i == tso - 1) 1465 buf[len - 1] = '\0'; 1466 error = SYSCTL_OUT(req, buf, len); 1467 if (error != 0) 1468 return (error); 1469 } 1470 return (0); 1471} 1472 1473SYSCTL_PROC(_machdep, OID_AUTO, siots, CTLTYPE_STRING | CTLFLAG_RD, 1474 0, 0, sysctl_siots, "A", "sio timestamps"); 1475 1476static void 1477siointr1(com) 1478 struct com_s *com; 1479{ 1480 u_char int_ctl; 1481 u_char int_ctl_new; 1482 u_char line_status; 1483 u_char modem_status; 1484 u_char *ioptr; 1485 u_char recv_data; 1486#if defined(KDB) && defined(ALT_BREAK_TO_DEBUGGER) 1487 int kdb_brk; 1488 1489again: 1490#endif 1491 1492 if (COM_IIR_TXRDYBUG(com->flags)) { 1493 int_ctl = inb(com->int_ctl_port); 1494 int_ctl_new = int_ctl; 1495 } else { 1496 int_ctl = 0; 1497 int_ctl_new = 0; 1498 } 1499 1500 while (!com->gone) { 1501 if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) { 1502 modem_status = inb(com->modem_status_port); 1503 if ((modem_status ^ com->last_modem_status) & 1504 com->pps_bit) { 1505 pps_capture(&com->pps); 1506 pps_event(&com->pps, 1507 (modem_status & com->pps_bit) ? 1508 PPS_CAPTUREASSERT : PPS_CAPTURECLEAR); 1509 } 1510 } 1511 line_status = inb(com->line_status_port); 1512 1513 /* input event? (check first to help avoid overruns) */ 1514 while (line_status & LSR_RCV_MASK) { 1515 /* break/unnattached error bits or real input? */ 1516 if (!(line_status & LSR_RXRDY)) 1517 recv_data = 0; 1518 else 1519 recv_data = inb(com->data_port); 1520#ifdef KDB 1521#ifdef ALT_BREAK_TO_DEBUGGER 1522 if (com->unit == comconsole && 1523 (kdb_brk = kdb_alt_break(recv_data, 1524 &com->alt_brk_state)) != 0) { 1525 mtx_unlock_spin(&sio_lock); 1526 switch (kdb_brk) { 1527 case KDB_REQ_DEBUGGER: 1528 kdb_enter(KDB_WHY_BREAK, 1529 "Break sequence on console"); 1530 break; 1531 case KDB_REQ_PANIC: 1532 kdb_panic("panic on console"); 1533 break; 1534 case KDB_REQ_REBOOT: 1535 kdb_reboot(); 1536 break; 1537 } 1538 mtx_lock_spin(&sio_lock); 1539 goto again; 1540 } 1541#endif /* ALT_BREAK_TO_DEBUGGER */ 1542#endif /* KDB */ 1543 if (line_status & (LSR_BI | LSR_FE | LSR_PE)) { 1544 /* 1545 * Don't store BI if IGNBRK or FE/PE if IGNPAR. 1546 * Otherwise, push the work to a higher level 1547 * (to handle PARMRK) if we're bypassing. 1548 * Otherwise, convert BI/FE and PE+INPCK to 0. 1549 * 1550 * This makes bypassing work right in the 1551 * usual "raw" case (IGNBRK set, and IGNPAR 1552 * and INPCK clear). 1553 * 1554 * Note: BI together with FE/PE means just BI. 1555 */ 1556 if (line_status & LSR_BI) { 1557#if defined(KDB) && defined(BREAK_TO_DEBUGGER) 1558 if (com->unit == comconsole) { 1559 kdb_enter(KDB_WHY_BREAK, 1560 "Line break on console"); 1561 goto cont; 1562 } 1563#endif 1564 if (com->tp == NULL 1565 || com->tp->t_iflag & IGNBRK) 1566 goto cont; 1567 } else { 1568 if (com->tp == NULL 1569 || com->tp->t_iflag & IGNPAR) 1570 goto cont; 1571 } 1572 if (com->tp->t_state & TS_CAN_BYPASS_L_RINT 1573 && (line_status & (LSR_BI | LSR_FE) 1574 || com->tp->t_iflag & INPCK)) 1575 recv_data = 0; 1576 } 1577 ++com->bytes_in; 1578 if (com->tp != NULL && 1579 com->tp->t_hotchar != 0 && recv_data == com->tp->t_hotchar) 1580 swi_sched(sio_fast_ih, 0); 1581 ioptr = com->iptr; 1582 if (ioptr >= com->ibufend) 1583 CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW); 1584 else { 1585 if (com->tp != NULL && com->tp->t_do_timestamp) 1586 microtime(&com->tp->t_timestamp); 1587 ++com_events; 1588 swi_sched(sio_slow_ih, SWI_DELAY); 1589#if 0 /* for testing input latency vs efficiency */ 1590if (com->iptr - com->ibuf == 8) 1591 swi_sched(sio_fast_ih, 0); 1592#endif 1593 ioptr[0] = recv_data; 1594 ioptr[com->ierroff] = line_status; 1595 com->iptr = ++ioptr; 1596 if (ioptr == com->ihighwater 1597 && com->state & CS_RTS_IFLOW) 1598 outb(com->modem_ctl_port, 1599 com->mcr_image &= ~MCR_RTS); 1600 if (line_status & LSR_OE) 1601 CE_RECORD(com, CE_OVERRUN); 1602 } 1603cont: 1604 if (line_status & LSR_TXRDY 1605 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) 1606 goto txrdy; 1607 1608 /* 1609 * "& 0x7F" is to avoid the gcc-1.40 generating a slow 1610 * jump from the top of the loop to here 1611 */ 1612 line_status = inb(com->line_status_port) & 0x7F; 1613 } 1614 1615 /* modem status change? (always check before doing output) */ 1616 modem_status = inb(com->modem_status_port); 1617 if (modem_status != com->last_modem_status) { 1618 /* 1619 * Schedule high level to handle DCD changes. Note 1620 * that we don't use the delta bits anywhere. Some 1621 * UARTs mess them up, and it's easy to remember the 1622 * previous bits and calculate the delta. 1623 */ 1624 com->last_modem_status = modem_status; 1625 if (!(com->state & CS_CHECKMSR)) { 1626 com_events += LOTS_OF_EVENTS; 1627 com->state |= CS_CHECKMSR; 1628 swi_sched(sio_fast_ih, 0); 1629 } 1630 1631 /* handle CTS change immediately for crisp flow ctl */ 1632 if (com->state & CS_CTS_OFLOW) { 1633 if (modem_status & MSR_CTS) 1634 com->state |= CS_ODEVREADY; 1635 else 1636 com->state &= ~CS_ODEVREADY; 1637 } 1638 } 1639 1640txrdy: 1641 /* output queued and everything ready? */ 1642 if (line_status & LSR_TXRDY 1643 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) { 1644 ioptr = com->obufq.l_head; 1645 if (com->tx_fifo_size > 1 && com->unit != siotsunit) { 1646 u_int ocount; 1647 1648 ocount = com->obufq.l_tail - ioptr; 1649 if (ocount > com->tx_fifo_size) 1650 ocount = com->tx_fifo_size; 1651 com->bytes_out += ocount; 1652 do 1653 outb(com->data_port, *ioptr++); 1654 while (--ocount != 0); 1655 } else { 1656 outb(com->data_port, *ioptr++); 1657 ++com->bytes_out; 1658 if (com->unit == siotsunit 1659 && siotso < sizeof siots / sizeof siots[0]) 1660 nanouptime(&siots[siotso++]); 1661 } 1662 com->obufq.l_head = ioptr; 1663 if (COM_IIR_TXRDYBUG(com->flags)) 1664 int_ctl_new = int_ctl | IER_ETXRDY; 1665 if (ioptr >= com->obufq.l_tail) { 1666 struct lbq *qp; 1667 1668 qp = com->obufq.l_next; 1669 qp->l_queued = FALSE; 1670 qp = qp->l_next; 1671 if (qp != NULL) { 1672 com->obufq.l_head = qp->l_head; 1673 com->obufq.l_tail = qp->l_tail; 1674 com->obufq.l_next = qp; 1675 } else { 1676 /* output just completed */ 1677 if (COM_IIR_TXRDYBUG(com->flags)) 1678 int_ctl_new = int_ctl 1679 & ~IER_ETXRDY; 1680 com->state &= ~CS_BUSY; 1681 } 1682 if (!(com->state & CS_ODONE)) { 1683 com_events += LOTS_OF_EVENTS; 1684 com->state |= CS_ODONE; 1685 /* handle at high level ASAP */ 1686 swi_sched(sio_fast_ih, 0); 1687 } 1688 } 1689 if (COM_IIR_TXRDYBUG(com->flags) 1690 && int_ctl != int_ctl_new) 1691 outb(com->int_ctl_port, int_ctl_new); 1692 } 1693 1694 /* finished? */ 1695#ifndef COM_MULTIPORT 1696 if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND) 1697#endif /* COM_MULTIPORT */ 1698 return; 1699 } 1700} 1701 1702/* software interrupt handler for SWI_TTY */ 1703static void 1704siopoll(void *dummy) 1705{ 1706 int unit; 1707 1708 if (com_events == 0) 1709 return; 1710repeat: 1711 for (unit = 0; unit < sio_numunits; ++unit) { 1712 struct com_s *com; 1713 int incc; 1714 struct tty *tp; 1715 1716 com = com_addr(unit); 1717 if (com == NULL) 1718 continue; 1719 tp = com->tp; 1720 if (tp == NULL || com->gone) { 1721 /* 1722 * Discard any events related to never-opened or 1723 * going-away devices. 1724 */ 1725 mtx_lock_spin(&sio_lock); 1726 incc = com->iptr - com->ibuf; 1727 com->iptr = com->ibuf; 1728 if (com->state & CS_CHECKMSR) { 1729 incc += LOTS_OF_EVENTS; 1730 com->state &= ~CS_CHECKMSR; 1731 } 1732 com_events -= incc; 1733 mtx_unlock_spin(&sio_lock); 1734 continue; 1735 } 1736 if (com->iptr != com->ibuf) { 1737 mtx_lock_spin(&sio_lock); 1738 sioinput(com); 1739 mtx_unlock_spin(&sio_lock); 1740 } 1741 if (com->state & CS_CHECKMSR) { 1742 u_char delta_modem_status; 1743 1744 mtx_lock_spin(&sio_lock); 1745 delta_modem_status = com->last_modem_status 1746 ^ com->prev_modem_status; 1747 com->prev_modem_status = com->last_modem_status; 1748 com_events -= LOTS_OF_EVENTS; 1749 com->state &= ~CS_CHECKMSR; 1750 mtx_unlock_spin(&sio_lock); 1751 if (delta_modem_status & MSR_DCD) 1752 ttyld_modem(tp, 1753 com->prev_modem_status & MSR_DCD); 1754 } 1755 if (com->state & CS_ODONE) { 1756 mtx_lock_spin(&sio_lock); 1757 com_events -= LOTS_OF_EVENTS; 1758 com->state &= ~CS_ODONE; 1759 mtx_unlock_spin(&sio_lock); 1760 if (!(com->state & CS_BUSY) 1761 && !(com->extra_state & CSE_BUSYCHECK)) { 1762 timeout(siobusycheck, com, hz / 100); 1763 com->extra_state |= CSE_BUSYCHECK; 1764 } 1765 ttyld_start(tp); 1766 } 1767 if (com_events == 0) 1768 break; 1769 } 1770 if (com_events >= LOTS_OF_EVENTS) 1771 goto repeat; 1772} 1773 1774static void 1775combreak(tp, sig) 1776 struct tty *tp; 1777 int sig; 1778{ 1779 struct com_s *com; 1780 1781 com = tp->t_sc; 1782 1783 if (sig) 1784 sio_setreg(com, com_cfcr, com->cfcr_image |= CFCR_SBREAK); 1785 else 1786 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 1787} 1788 1789static int 1790comparam(tp, t) 1791 struct tty *tp; 1792 struct termios *t; 1793{ 1794 u_int cfcr; 1795 int cflag; 1796 struct com_s *com; 1797 u_int divisor; 1798 u_char dlbh; 1799 u_char dlbl; 1800 u_char efr_flowbits; 1801 int s; 1802 1803 com = tp->t_sc; 1804 if (com == NULL) 1805 return (ENODEV); 1806 1807 /* check requested parameters */ 1808 if (t->c_ispeed != (t->c_ospeed != 0 ? t->c_ospeed : tp->t_ospeed)) 1809 return (EINVAL); 1810 divisor = siodivisor(com->rclk, t->c_ispeed); 1811 if (divisor == 0) 1812 return (EINVAL); 1813 1814 /* parameters are OK, convert them to the com struct and the device */ 1815 s = spltty(); 1816 if (t->c_ospeed == 0) 1817 (void)commodem(tp, 0, SER_DTR); /* hang up line */ 1818 else 1819 (void)commodem(tp, SER_DTR, 0); 1820 cflag = t->c_cflag; 1821 switch (cflag & CSIZE) { 1822 case CS5: 1823 cfcr = CFCR_5BITS; 1824 break; 1825 case CS6: 1826 cfcr = CFCR_6BITS; 1827 break; 1828 case CS7: 1829 cfcr = CFCR_7BITS; 1830 break; 1831 default: 1832 cfcr = CFCR_8BITS; 1833 break; 1834 } 1835 if (cflag & PARENB) { 1836 cfcr |= CFCR_PENAB; 1837 if (!(cflag & PARODD)) 1838 cfcr |= CFCR_PEVEN; 1839 } 1840 if (cflag & CSTOPB) 1841 cfcr |= CFCR_STOPB; 1842 1843 if (com->hasfifo) { 1844 /* 1845 * Use a fifo trigger level low enough so that the input 1846 * latency from the fifo is less than about 16 msec and 1847 * the total latency is less than about 30 msec. These 1848 * latencies are reasonable for humans. Serial comms 1849 * protocols shouldn't expect anything better since modem 1850 * latencies are larger. 1851 * 1852 * The fifo trigger level cannot be set at RX_HIGH for high 1853 * speed connections without further work on reducing 1854 * interrupt disablement times in other parts of the system, 1855 * without producing silo overflow errors. 1856 */ 1857 com->fifo_image = com->unit == siotsunit ? 0 1858 : t->c_ispeed <= 4800 1859 ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_MEDH; 1860#ifdef COM_ESP 1861 /* 1862 * The Hayes ESP card needs the fifo DMA mode bit set 1863 * in compatibility mode. If not, it will interrupt 1864 * for each character received. 1865 */ 1866 if (com->esp) 1867 com->fifo_image |= FIFO_DMA_MODE; 1868#endif 1869 sio_setreg(com, com_fifo, com->fifo_image); 1870 } 1871 1872 /* 1873 * This returns with interrupts disabled so that we can complete 1874 * the speed change atomically. Keeping interrupts disabled is 1875 * especially important while com_data is hidden. 1876 */ 1877 (void) siosetwater(com, t->c_ispeed); 1878 1879 sio_setreg(com, com_cfcr, cfcr | CFCR_DLAB); 1880 /* 1881 * Only set the divisor registers if they would change, since on 1882 * some 16550 incompatibles (UMC8669F), setting them while input 1883 * is arriving loses sync until data stops arriving. 1884 */ 1885 dlbl = divisor & 0xFF; 1886 if (sio_getreg(com, com_dlbl) != dlbl) 1887 sio_setreg(com, com_dlbl, dlbl); 1888 dlbh = divisor >> 8; 1889 if (sio_getreg(com, com_dlbh) != dlbh) 1890 sio_setreg(com, com_dlbh, dlbh); 1891 1892 efr_flowbits = 0; 1893 1894 if (cflag & CRTS_IFLOW) { 1895 com->state |= CS_RTS_IFLOW; 1896 efr_flowbits |= EFR_AUTORTS; 1897 /* 1898 * If CS_RTS_IFLOW just changed from off to on, the change 1899 * needs to be propagated to MCR_RTS. This isn't urgent, 1900 * so do it later by calling comstart() instead of repeating 1901 * a lot of code from comstart() here. 1902 */ 1903 } else if (com->state & CS_RTS_IFLOW) { 1904 com->state &= ~CS_RTS_IFLOW; 1905 /* 1906 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS 1907 * on here, since comstart() won't do it later. 1908 */ 1909 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 1910 } 1911 1912 /* 1913 * Set up state to handle output flow control. 1914 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level? 1915 * Now has 10+ msec latency, while CTS flow has 50- usec latency. 1916 */ 1917 com->state |= CS_ODEVREADY; 1918 com->state &= ~CS_CTS_OFLOW; 1919 if (cflag & CCTS_OFLOW) { 1920 com->state |= CS_CTS_OFLOW; 1921 efr_flowbits |= EFR_AUTOCTS; 1922 if (!(com->last_modem_status & MSR_CTS)) 1923 com->state &= ~CS_ODEVREADY; 1924 } 1925 1926 if (com->st16650a) { 1927 sio_setreg(com, com_lcr, LCR_EFR_ENABLE); 1928 sio_setreg(com, com_efr, 1929 (sio_getreg(com, com_efr) 1930 & ~(EFR_AUTOCTS | EFR_AUTORTS)) | efr_flowbits); 1931 } 1932 sio_setreg(com, com_cfcr, com->cfcr_image = cfcr); 1933 1934 /* XXX shouldn't call functions while intrs are disabled. */ 1935 ttyldoptim(tp); 1936 1937 mtx_unlock_spin(&sio_lock); 1938 splx(s); 1939 comstart(tp); 1940 if (com->ibufold != NULL) { 1941 free(com->ibufold, M_DEVBUF); 1942 com->ibufold = NULL; 1943 } 1944 return (0); 1945} 1946 1947/* 1948 * This function must be called with the sio_lock mutex released and will 1949 * return with it obtained. 1950 */ 1951static int 1952siosetwater(com, speed) 1953 struct com_s *com; 1954 speed_t speed; 1955{ 1956 int cp4ticks; 1957 u_char *ibuf; 1958 int ibufsize; 1959 struct tty *tp; 1960 1961 /* 1962 * Make the buffer size large enough to handle a softtty interrupt 1963 * latency of about 2 ticks without loss of throughput or data 1964 * (about 3 ticks if input flow control is not used or not honoured, 1965 * but a bit less for CS5-CS7 modes). 1966 */ 1967 cp4ticks = speed / 10 / hz * 4; 1968 for (ibufsize = 128; ibufsize < cp4ticks;) 1969 ibufsize <<= 1; 1970 if (ibufsize == com->ibufsize) { 1971 mtx_lock_spin(&sio_lock); 1972 return (0); 1973 } 1974 1975 /* 1976 * Allocate input buffer. The extra factor of 2 in the size is 1977 * to allow for an error byte for each input byte. 1978 */ 1979 ibuf = malloc(2 * ibufsize, M_DEVBUF, M_NOWAIT); 1980 if (ibuf == NULL) { 1981 mtx_lock_spin(&sio_lock); 1982 return (ENOMEM); 1983 } 1984 1985 /* Initialize non-critical variables. */ 1986 com->ibufold = com->ibuf; 1987 com->ibufsize = ibufsize; 1988 tp = com->tp; 1989 if (tp != NULL) { 1990 tp->t_ififosize = 2 * ibufsize; 1991 tp->t_ispeedwat = (speed_t)-1; 1992 tp->t_ospeedwat = (speed_t)-1; 1993 } 1994 1995 /* 1996 * Read current input buffer, if any. Continue with interrupts 1997 * disabled. 1998 */ 1999 mtx_lock_spin(&sio_lock); 2000 if (com->iptr != com->ibuf) 2001 sioinput(com); 2002 2003 /*- 2004 * Initialize critical variables, including input buffer watermarks. 2005 * The external device is asked to stop sending when the buffer 2006 * exactly reaches high water, or when the high level requests it. 2007 * The high level is notified immediately (rather than at a later 2008 * clock tick) when this watermark is reached. 2009 * The buffer size is chosen so the watermark should almost never 2010 * be reached. 2011 * The low watermark is invisibly 0 since the buffer is always 2012 * emptied all at once. 2013 */ 2014 com->iptr = com->ibuf = ibuf; 2015 com->ibufend = ibuf + ibufsize; 2016 com->ierroff = ibufsize; 2017 com->ihighwater = ibuf + 3 * ibufsize / 4; 2018 return (0); 2019} 2020 2021static void 2022comstart(tp) 2023 struct tty *tp; 2024{ 2025 struct com_s *com; 2026 int s; 2027 2028 com = tp->t_sc; 2029 if (com == NULL) 2030 return; 2031 s = spltty(); 2032 mtx_lock_spin(&sio_lock); 2033 if (tp->t_state & TS_TTSTOP) 2034 com->state &= ~CS_TTGO; 2035 else 2036 com->state |= CS_TTGO; 2037 if (tp->t_state & TS_TBLOCK) { 2038 if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW) 2039 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS); 2040 } else { 2041 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater 2042 && com->state & CS_RTS_IFLOW) 2043 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2044 } 2045 mtx_unlock_spin(&sio_lock); 2046 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) { 2047 ttwwakeup(tp); 2048 splx(s); 2049 return; 2050 } 2051 if (tp->t_outq.c_cc != 0) { 2052 struct lbq *qp; 2053 struct lbq *next; 2054 2055 if (!com->obufs[0].l_queued) { 2056 com->obufs[0].l_tail 2057 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1, 2058 sizeof com->obuf1); 2059 com->obufs[0].l_next = NULL; 2060 com->obufs[0].l_queued = TRUE; 2061 mtx_lock_spin(&sio_lock); 2062 if (com->state & CS_BUSY) { 2063 qp = com->obufq.l_next; 2064 while ((next = qp->l_next) != NULL) 2065 qp = next; 2066 qp->l_next = &com->obufs[0]; 2067 } else { 2068 com->obufq.l_head = com->obufs[0].l_head; 2069 com->obufq.l_tail = com->obufs[0].l_tail; 2070 com->obufq.l_next = &com->obufs[0]; 2071 com->state |= CS_BUSY; 2072 } 2073 mtx_unlock_spin(&sio_lock); 2074 } 2075 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) { 2076 com->obufs[1].l_tail 2077 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2, 2078 sizeof com->obuf2); 2079 com->obufs[1].l_next = NULL; 2080 com->obufs[1].l_queued = TRUE; 2081 mtx_lock_spin(&sio_lock); 2082 if (com->state & CS_BUSY) { 2083 qp = com->obufq.l_next; 2084 while ((next = qp->l_next) != NULL) 2085 qp = next; 2086 qp->l_next = &com->obufs[1]; 2087 } else { 2088 com->obufq.l_head = com->obufs[1].l_head; 2089 com->obufq.l_tail = com->obufs[1].l_tail; 2090 com->obufq.l_next = &com->obufs[1]; 2091 com->state |= CS_BUSY; 2092 } 2093 mtx_unlock_spin(&sio_lock); 2094 } 2095 tp->t_state |= TS_BUSY; 2096 } 2097 mtx_lock_spin(&sio_lock); 2098 if (com->state >= (CS_BUSY | CS_TTGO)) 2099 siointr1(com); /* fake interrupt to start output */ 2100 mtx_unlock_spin(&sio_lock); 2101 ttwwakeup(tp); 2102 splx(s); 2103} 2104 2105static void 2106comstop(tp, rw) 2107 struct tty *tp; 2108 int rw; 2109{ 2110 struct com_s *com; 2111 2112 com = tp->t_sc; 2113 if (com == NULL || com->gone) 2114 return; 2115 mtx_lock_spin(&sio_lock); 2116 if (rw & FWRITE) { 2117 if (com->hasfifo) 2118#ifdef COM_ESP 2119 /* XXX avoid h/w bug. */ 2120 if (!com->esp) 2121#endif 2122 sio_setreg(com, com_fifo, 2123 FIFO_XMT_RST | com->fifo_image); 2124 com->obufs[0].l_queued = FALSE; 2125 com->obufs[1].l_queued = FALSE; 2126 if (com->state & CS_ODONE) 2127 com_events -= LOTS_OF_EVENTS; 2128 com->state &= ~(CS_ODONE | CS_BUSY); 2129 com->tp->t_state &= ~TS_BUSY; 2130 } 2131 if (rw & FREAD) { 2132 if (com->hasfifo) 2133#ifdef COM_ESP 2134 /* XXX avoid h/w bug. */ 2135 if (!com->esp) 2136#endif 2137 sio_setreg(com, com_fifo, 2138 FIFO_RCV_RST | com->fifo_image); 2139 com_events -= (com->iptr - com->ibuf); 2140 com->iptr = com->ibuf; 2141 } 2142 mtx_unlock_spin(&sio_lock); 2143 comstart(tp); 2144} 2145 2146static int 2147commodem(struct tty *tp, int sigon, int sigoff) 2148{ 2149 struct com_s *com; 2150 int bitand, bitor, msr; 2151 2152 com = tp->t_sc; 2153 if (com->gone) 2154 return(0); 2155 if (sigon != 0 || sigoff != 0) { 2156 bitand = bitor = 0; 2157 if (sigoff & SER_DTR) 2158 bitand |= MCR_DTR; 2159 if (sigoff & SER_RTS) 2160 bitand |= MCR_RTS; 2161 if (sigon & SER_DTR) 2162 bitor |= MCR_DTR; 2163 if (sigon & SER_RTS) 2164 bitor |= MCR_RTS; 2165 bitand = ~bitand; 2166 mtx_lock_spin(&sio_lock); 2167 com->mcr_image &= bitand; 2168 com->mcr_image |= bitor; 2169 outb(com->modem_ctl_port, com->mcr_image); 2170 mtx_unlock_spin(&sio_lock); 2171 return (0); 2172 } else { 2173 bitor = 0; 2174 if (com->mcr_image & MCR_DTR) 2175 bitor |= SER_DTR; 2176 if (com->mcr_image & MCR_RTS) 2177 bitor |= SER_RTS; 2178 msr = com->prev_modem_status; 2179 if (msr & MSR_CTS) 2180 bitor |= SER_CTS; 2181 if (msr & MSR_DCD) 2182 bitor |= SER_DCD; 2183 if (msr & MSR_DSR) 2184 bitor |= SER_DSR; 2185 if (msr & MSR_DSR) 2186 bitor |= SER_DSR; 2187 if (msr & (MSR_RI | MSR_TERI)) 2188 bitor |= SER_RI; 2189 return (bitor); 2190 } 2191} 2192 2193static void 2194siosettimeout() 2195{ 2196 struct com_s *com; 2197 bool_t someopen; 2198 int unit; 2199 2200 /* 2201 * Set our timeout period to 1 second if no polled devices are open. 2202 * Otherwise set it to max(1/200, 1/hz). 2203 * Enable timeouts iff some device is open. 2204 */ 2205 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 2206 sio_timeout = hz; 2207 someopen = FALSE; 2208 for (unit = 0; unit < sio_numunits; ++unit) { 2209 com = com_addr(unit); 2210 if (com != NULL && com->tp != NULL 2211 && com->tp->t_state & TS_ISOPEN && !com->gone) { 2212 someopen = TRUE; 2213 if (com->poll || com->poll_output) { 2214 sio_timeout = hz > 200 ? hz / 200 : 1; 2215 break; 2216 } 2217 } 2218 } 2219 if (someopen) { 2220 sio_timeouts_until_log = hz / sio_timeout; 2221 sio_timeout_handle = timeout(comwakeup, (void *)NULL, 2222 sio_timeout); 2223 } else { 2224 /* Flush error messages, if any. */ 2225 sio_timeouts_until_log = 1; 2226 comwakeup((void *)NULL); 2227 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 2228 } 2229} 2230 2231static void 2232comwakeup(chan) 2233 void *chan; 2234{ 2235 struct com_s *com; 2236 int unit; 2237 2238 sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout); 2239 2240 /* 2241 * Recover from lost output interrupts. 2242 * Poll any lines that don't use interrupts. 2243 */ 2244 for (unit = 0; unit < sio_numunits; ++unit) { 2245 com = com_addr(unit); 2246 if (com != NULL && !com->gone 2247 && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) { 2248 mtx_lock_spin(&sio_lock); 2249 siointr1(com); 2250 mtx_unlock_spin(&sio_lock); 2251 } 2252 } 2253 2254 /* 2255 * Check for and log errors, but not too often. 2256 */ 2257 if (--sio_timeouts_until_log > 0) 2258 return; 2259 sio_timeouts_until_log = hz / sio_timeout; 2260 for (unit = 0; unit < sio_numunits; ++unit) { 2261 int errnum; 2262 2263 com = com_addr(unit); 2264 if (com == NULL) 2265 continue; 2266 if (com->gone) 2267 continue; 2268 for (errnum = 0; errnum < CE_NTYPES; ++errnum) { 2269 u_int delta; 2270 u_long total; 2271 2272 mtx_lock_spin(&sio_lock); 2273 delta = com->delta_error_counts[errnum]; 2274 com->delta_error_counts[errnum] = 0; 2275 mtx_unlock_spin(&sio_lock); 2276 if (delta == 0) 2277 continue; 2278 total = com->error_counts[errnum] += delta; 2279 log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n", 2280 unit, delta, error_desc[errnum], 2281 delta == 1 ? "" : "s", total); 2282 } 2283 } 2284} 2285 2286/* 2287 * Following are all routines needed for SIO to act as console 2288 */ 2289struct siocnstate { 2290 u_char dlbl; 2291 u_char dlbh; 2292 u_char ier; 2293 u_char cfcr; 2294 u_char mcr; 2295}; 2296 2297/* 2298 * This is a function in order to not replicate "ttyd%d" more 2299 * places than absolutely necessary. 2300 */ 2301static void 2302siocnset(struct consdev *cd, int unit) 2303{ 2304 2305 cd->cn_unit = unit; 2306 sprintf(cd->cn_name, "ttyd%d", unit); 2307} 2308 2309static speed_t siocngetspeed(Port_t, u_long rclk); 2310static void siocnclose(struct siocnstate *sp, Port_t iobase); 2311static void siocnopen(struct siocnstate *sp, Port_t iobase, int speed); 2312static void siocntxwait(Port_t iobase); 2313 2314static cn_probe_t sio_cnprobe; 2315static cn_init_t sio_cninit; 2316static cn_term_t sio_cnterm; 2317static cn_getc_t sio_cngetc; 2318static cn_putc_t sio_cnputc; 2319 2320CONSOLE_DRIVER(sio); 2321 2322static void 2323siocntxwait(iobase) 2324 Port_t iobase; 2325{ 2326 int timo; 2327 2328 /* 2329 * Wait for any pending transmission to finish. Required to avoid 2330 * the UART lockup bug when the speed is changed, and for normal 2331 * transmits. 2332 */ 2333 timo = 100000; 2334 while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY)) 2335 != (LSR_TSRE | LSR_TXRDY) && --timo != 0) 2336 ; 2337} 2338 2339/* 2340 * Read the serial port specified and try to figure out what speed 2341 * it's currently running at. We're assuming the serial port has 2342 * been initialized and is basicly idle. This routine is only intended 2343 * to be run at system startup. 2344 * 2345 * If the value read from the serial port doesn't make sense, return 0. 2346 */ 2347 2348static speed_t 2349siocngetspeed(iobase, rclk) 2350 Port_t iobase; 2351 u_long rclk; 2352{ 2353 u_int divisor; 2354 u_char dlbh; 2355 u_char dlbl; 2356 u_char cfcr; 2357 2358 cfcr = inb(iobase + com_cfcr); 2359 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 2360 2361 dlbl = inb(iobase + com_dlbl); 2362 dlbh = inb(iobase + com_dlbh); 2363 2364 outb(iobase + com_cfcr, cfcr); 2365 2366 divisor = dlbh << 8 | dlbl; 2367 2368 /* XXX there should be more sanity checking. */ 2369 if (divisor == 0) 2370 return (CONSPEED); 2371 return (rclk / (16UL * divisor)); 2372} 2373 2374static void 2375siocnopen(sp, iobase, speed) 2376 struct siocnstate *sp; 2377 Port_t iobase; 2378 int speed; 2379{ 2380 u_int divisor; 2381 u_char dlbh; 2382 u_char dlbl; 2383 2384 /* 2385 * Save all the device control registers except the fifo register 2386 * and set our default ones (cs8 -parenb speed=comdefaultrate). 2387 * We can't save the fifo register since it is read-only. 2388 */ 2389 sp->ier = inb(iobase + com_ier); 2390 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */ 2391 siocntxwait(iobase); 2392 sp->cfcr = inb(iobase + com_cfcr); 2393 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 2394 sp->dlbl = inb(iobase + com_dlbl); 2395 sp->dlbh = inb(iobase + com_dlbh); 2396 /* 2397 * Only set the divisor registers if they would change, since on 2398 * some 16550 incompatibles (Startech), setting them clears the 2399 * data input register. This also reduces the effects of the 2400 * UMC8669F bug. 2401 */ 2402 divisor = siodivisor(comdefaultrclk, speed); 2403 dlbl = divisor & 0xFF; 2404 if (sp->dlbl != dlbl) 2405 outb(iobase + com_dlbl, dlbl); 2406 dlbh = divisor >> 8; 2407 if (sp->dlbh != dlbh) 2408 outb(iobase + com_dlbh, dlbh); 2409 outb(iobase + com_cfcr, CFCR_8BITS); 2410 sp->mcr = inb(iobase + com_mcr); 2411 /* 2412 * We don't want interrupts, but must be careful not to "disable" 2413 * them by clearing the MCR_IENABLE bit, since that might cause 2414 * an interrupt by floating the IRQ line. 2415 */ 2416 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS); 2417} 2418 2419static void 2420siocnclose(sp, iobase) 2421 struct siocnstate *sp; 2422 Port_t iobase; 2423{ 2424 /* 2425 * Restore the device control registers. 2426 */ 2427 siocntxwait(iobase); 2428 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 2429 if (sp->dlbl != inb(iobase + com_dlbl)) 2430 outb(iobase + com_dlbl, sp->dlbl); 2431 if (sp->dlbh != inb(iobase + com_dlbh)) 2432 outb(iobase + com_dlbh, sp->dlbh); 2433 outb(iobase + com_cfcr, sp->cfcr); 2434 /* 2435 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them. 2436 */ 2437 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS); 2438 outb(iobase + com_ier, sp->ier); 2439} 2440 2441static void 2442sio_cnprobe(cp) 2443 struct consdev *cp; 2444{ 2445 speed_t boot_speed; 2446 u_char cfcr; 2447 u_int divisor; 2448 int s, unit; 2449 struct siocnstate sp; 2450 2451 /* 2452 * Find our first enabled console, if any. If it is a high-level 2453 * console device, then initialize it and return successfully. 2454 * If it is a low-level console device, then initialize it and 2455 * return unsuccessfully. It must be initialized in both cases 2456 * for early use by console drivers and debuggers. Initializing 2457 * the hardware is not necessary in all cases, since the i/o 2458 * routines initialize it on the fly, but it is necessary if 2459 * input might arrive while the hardware is switched back to an 2460 * uninitialized state. We can't handle multiple console devices 2461 * yet because our low-level routines don't take a device arg. 2462 * We trust the user to set the console flags properly so that we 2463 * don't need to probe. 2464 */ 2465 cp->cn_pri = CN_DEAD; 2466 2467 for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */ 2468 int flags; 2469 2470 if (resource_disabled("sio", unit)) 2471 continue; 2472 if (resource_int_value("sio", unit, "flags", &flags)) 2473 continue; 2474 if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) { 2475 int port; 2476 Port_t iobase; 2477 2478 if (resource_int_value("sio", unit, "port", &port)) 2479 continue; 2480 iobase = port; 2481 s = spltty(); 2482 if ((boothowto & RB_SERIAL) && COM_CONSOLE(flags)) { 2483 boot_speed = 2484 siocngetspeed(iobase, comdefaultrclk); 2485 if (boot_speed) 2486 comdefaultrate = boot_speed; 2487 } 2488 2489 /* 2490 * Initialize the divisor latch. We can't rely on 2491 * siocnopen() to do this the first time, since it 2492 * avoids writing to the latch if the latch appears 2493 * to have the correct value. Also, if we didn't 2494 * just read the speed from the hardware, then we 2495 * need to set the speed in hardware so that 2496 * switching it later is null. 2497 */ 2498 cfcr = inb(iobase + com_cfcr); 2499 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 2500 divisor = siodivisor(comdefaultrclk, comdefaultrate); 2501 outb(iobase + com_dlbl, divisor & 0xff); 2502 outb(iobase + com_dlbh, divisor >> 8); 2503 outb(iobase + com_cfcr, cfcr); 2504 2505 siocnopen(&sp, iobase, comdefaultrate); 2506 2507 splx(s); 2508 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) { 2509 siocnset(cp, unit); 2510 cp->cn_pri = COM_FORCECONSOLE(flags) 2511 || boothowto & RB_SERIAL 2512 ? CN_REMOTE : CN_NORMAL; 2513 siocniobase = iobase; 2514 siocnunit = unit; 2515 } 2516#ifdef GDB 2517 if (COM_DEBUGGER(flags)) 2518 siogdbiobase = iobase; 2519#endif 2520 } 2521 } 2522} 2523 2524static void 2525sio_cninit(cp) 2526 struct consdev *cp; 2527{ 2528 comconsole = cp->cn_unit; 2529} 2530 2531static void 2532sio_cnterm(cp) 2533 struct consdev *cp; 2534{ 2535 comconsole = -1; 2536} 2537 2538static int 2539sio_cngetc(struct consdev *cd) 2540{ 2541 int c; 2542 Port_t iobase; 2543 int s; 2544 struct siocnstate sp; 2545 speed_t speed; 2546 2547 if (cd != NULL && cd->cn_unit == siocnunit) { 2548 iobase = siocniobase; 2549 speed = comdefaultrate; 2550 } else { 2551#ifdef GDB 2552 iobase = siogdbiobase; 2553 speed = gdbdefaultrate; 2554#else 2555 return (-1); 2556#endif 2557 } 2558 s = spltty(); 2559 siocnopen(&sp, iobase, speed); 2560 if (inb(iobase + com_lsr) & LSR_RXRDY) 2561 c = inb(iobase + com_data); 2562 else 2563 c = -1; 2564 siocnclose(&sp, iobase); 2565 splx(s); 2566 return (c); 2567} 2568 2569static void 2570sio_cnputc(struct consdev *cd, int c) 2571{ 2572 int need_unlock; 2573 int s; 2574 struct siocnstate sp; 2575 Port_t iobase; 2576 speed_t speed; 2577 2578 if (cd != NULL && cd->cn_unit == siocnunit) { 2579 iobase = siocniobase; 2580 speed = comdefaultrate; 2581 } else { 2582#ifdef GDB 2583 iobase = siogdbiobase; 2584 speed = gdbdefaultrate; 2585#else 2586 return; 2587#endif 2588 } 2589 s = spltty(); 2590 need_unlock = 0; 2591 if (!kdb_active && sio_inited == 2 && !mtx_owned(&sio_lock)) { 2592 mtx_lock_spin(&sio_lock); 2593 need_unlock = 1; 2594 } 2595 siocnopen(&sp, iobase, speed); 2596 siocntxwait(iobase); 2597 outb(iobase + com_data, c); 2598 siocnclose(&sp, iobase); 2599 if (need_unlock) 2600 mtx_unlock_spin(&sio_lock); 2601 splx(s); 2602} 2603 2604/* 2605 * Remote gdb(1) support. 2606 */ 2607 2608#if defined(GDB) 2609 2610#include <gdb/gdb.h> 2611 2612static gdb_probe_f siogdbprobe; 2613static gdb_init_f siogdbinit; 2614static gdb_term_f siogdbterm; 2615static gdb_getc_f siogdbgetc; 2616static gdb_putc_f siogdbputc; 2617 2618GDB_DBGPORT(sio, siogdbprobe, siogdbinit, siogdbterm, siogdbgetc, siogdbputc); 2619 2620static int 2621siogdbprobe(void) 2622{ 2623 return ((siogdbiobase != 0) ? 0 : -1); 2624} 2625 2626static void 2627siogdbinit(void) 2628{ 2629} 2630 2631static void 2632siogdbterm(void) 2633{ 2634} 2635 2636static void 2637siogdbputc(int c) 2638{ 2639 sio_cnputc(NULL, c); 2640} 2641 2642static int 2643siogdbgetc(void) 2644{ 2645 return (sio_cngetc(NULL)); 2646} 2647 2648#endif 2649