sio.c revision 131373
1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 4. Neither the name of the University nor the names of its contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: @(#)com.c 7.5 (Berkeley) 5/16/91 30 * from: i386/isa sio.c,v 1.234 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/sio/sio.c 131373 2004-06-30 21:38:08Z phk $"); 35 36#include "opt_comconsole.h" 37#include "opt_compat.h" 38#include "opt_ddb.h" 39#include "opt_sio.h" 40 41/* 42 * Serial driver, based on 386BSD-0.1 com driver. 43 * Mostly rewritten to use pseudo-DMA. 44 * Works for National Semiconductor NS8250-NS16550AF UARTs. 45 * COM driver, based on HP dca driver. 46 * 47 * Changes for PC-Card integration: 48 * - Added PC-Card driver table and handlers 49 */ 50#include <sys/param.h> 51#include <sys/systm.h> 52#include <sys/bus.h> 53#include <sys/conf.h> 54#include <sys/fcntl.h> 55#include <sys/interrupt.h> 56#include <sys/kernel.h> 57#include <sys/limits.h> 58#include <sys/lock.h> 59#include <sys/malloc.h> 60#include <sys/module.h> 61#include <sys/mutex.h> 62#include <sys/proc.h> 63#include <sys/reboot.h> 64#include <sys/serial.h> 65#include <sys/sysctl.h> 66#include <sys/syslog.h> 67#include <sys/tty.h> 68#include <machine/bus_pio.h> 69#include <machine/bus.h> 70#include <sys/rman.h> 71#include <sys/timepps.h> 72#include <sys/uio.h> 73#include <sys/cons.h> 74#if DDB > 0 75#include <ddb/ddb.h> 76#endif 77 78#include <isa/isavar.h> 79 80#include <machine/resource.h> 81 82#include <dev/sio/sioreg.h> 83#include <dev/sio/siovar.h> 84 85#ifdef COM_ESP 86#include <dev/ic/esp.h> 87#endif 88#include <dev/ic/ns16550.h> 89 90#define LOTS_OF_EVENTS 64 /* helps separate urgent events from input */ 91 92#define CALLOUT_MASK 0x80 93#define CONTROL_MASK 0x60 94#define CONTROL_INIT_STATE 0x20 95#define CONTROL_LOCK_STATE 0x40 96#define DEV_TO_UNIT(dev) (MINOR_TO_UNIT(minor(dev))) 97#define MINOR_TO_UNIT(mynor) ((((mynor) & ~0xffffU) >> (8 + 3)) \ 98 | ((mynor) & 0x1f)) 99#define UNIT_TO_MINOR(unit) ((((unit) & ~0x1fU) << (8 + 3)) \ 100 | ((unit) & 0x1f)) 101 102#ifdef COM_MULTIPORT 103/* checks in flags for multiport and which is multiport "master chip" 104 * for a given card 105 */ 106#define COM_ISMULTIPORT(flags) ((flags) & 0x01) 107#define COM_MPMASTER(flags) (((flags) >> 8) & 0x0ff) 108#define COM_NOTAST4(flags) ((flags) & 0x04) 109#else 110#define COM_ISMULTIPORT(flags) (0) 111#endif /* COM_MULTIPORT */ 112 113#define COM_C_IIR_TXRDYBUG 0x80000 114#define COM_CONSOLE(flags) ((flags) & 0x10) 115#define COM_DEBUGGER(flags) ((flags) & 0x80) 116#define COM_FIFOSIZE(flags) (((flags) & 0xff000000) >> 24) 117#define COM_FORCECONSOLE(flags) ((flags) & 0x20) 118#define COM_IIR_TXRDYBUG(flags) ((flags) & COM_C_IIR_TXRDYBUG) 119#define COM_LLCONSOLE(flags) ((flags) & 0x40) 120#define COM_LOSESOUTINTS(flags) ((flags) & 0x08) 121#define COM_NOFIFO(flags) ((flags) & 0x02) 122#define COM_NOPROBE(flags) ((flags) & 0x40000) 123#define COM_NOSCR(flags) ((flags) & 0x100000) 124#define COM_PPSCTS(flags) ((flags) & 0x10000) 125#define COM_ST16650A(flags) ((flags) & 0x20000) 126#define COM_TI16754(flags) ((flags) & 0x200000) 127 128#define sio_getreg(com, off) \ 129 (bus_space_read_1((com)->bst, (com)->bsh, (off))) 130#define sio_setreg(com, off, value) \ 131 (bus_space_write_1((com)->bst, (com)->bsh, (off), (value))) 132 133/* 134 * com state bits. 135 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher 136 * than the other bits so that they can be tested as a group without masking 137 * off the low bits. 138 * 139 * The following com and tty flags correspond closely: 140 * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and 141 * comstop()) 142 * CS_TTGO = ~TS_TTSTOP (maintained by comparam() and comstart()) 143 * CS_CTS_OFLOW = CCTS_OFLOW (maintained by comparam()) 144 * CS_RTS_IFLOW = CRTS_IFLOW (maintained by comparam()) 145 * TS_FLUSH is not used. 146 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON. 147 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state). 148 */ 149#define CS_BUSY 0x80 /* output in progress */ 150#define CS_TTGO 0x40 /* output not stopped by XOFF */ 151#define CS_ODEVREADY 0x20 /* external device h/w ready (CTS) */ 152#define CS_CHECKMSR 1 /* check of MSR scheduled */ 153#define CS_CTS_OFLOW 2 /* use CTS output flow control */ 154#define CS_DTR_OFF 0x10 /* DTR held off */ 155#define CS_ODONE 4 /* output completed */ 156#define CS_RTS_IFLOW 8 /* use RTS input flow control */ 157#define CSE_BUSYCHECK 1 /* siobusycheck() scheduled */ 158 159static char const * const error_desc[] = { 160#define CE_OVERRUN 0 161 "silo overflow", 162#define CE_INTERRUPT_BUF_OVERFLOW 1 163 "interrupt-level buffer overflow", 164#define CE_TTY_BUF_OVERFLOW 2 165 "tty-level buffer overflow", 166}; 167 168#define CE_NTYPES 3 169#define CE_RECORD(com, errnum) (++(com)->delta_error_counts[errnum]) 170 171/* types. XXX - should be elsewhere */ 172typedef u_int Port_t; /* hardware port */ 173typedef u_char bool_t; /* boolean */ 174 175/* queue of linear buffers */ 176struct lbq { 177 u_char *l_head; /* next char to process */ 178 u_char *l_tail; /* one past the last char to process */ 179 struct lbq *l_next; /* next in queue */ 180 bool_t l_queued; /* nonzero if queued */ 181}; 182 183/* com device structure */ 184struct com_s { 185 u_char state; /* miscellaneous flag bits */ 186 bool_t active_out; /* nonzero if the callout device is open */ 187 u_char cfcr_image; /* copy of value written to CFCR */ 188#ifdef COM_ESP 189 bool_t esp; /* is this unit a hayes esp board? */ 190#endif 191 u_char extra_state; /* more flag bits, separate for order trick */ 192 u_char fifo_image; /* copy of value written to FIFO */ 193 bool_t hasfifo; /* nonzero for 16550 UARTs */ 194 bool_t loses_outints; /* nonzero if device loses output interrupts */ 195 u_char mcr_image; /* copy of value written to MCR */ 196#ifdef COM_MULTIPORT 197 bool_t multiport; /* is this unit part of a multiport device? */ 198#endif /* COM_MULTIPORT */ 199 bool_t no_irq; /* nonzero if irq is not attached */ 200 bool_t gone; /* hardware disappeared */ 201 bool_t poll; /* nonzero if polling is required */ 202 bool_t poll_output; /* nonzero if polling for output is required */ 203 bool_t st16650a; /* nonzero if Startech 16650A compatible */ 204 int unit; /* unit number */ 205 int dtr_wait; /* time to hold DTR down on close (* 1/hz) */ 206 u_int flags; /* copy of device flags */ 207 u_int tx_fifo_size; 208 u_int wopeners; /* # processes waiting for DCD in open() */ 209 210 /* 211 * The high level of the driver never reads status registers directly 212 * because there would be too many side effects to handle conveniently. 213 * Instead, it reads copies of the registers stored here by the 214 * interrupt handler. 215 */ 216 u_char last_modem_status; /* last MSR read by intr handler */ 217 u_char prev_modem_status; /* last MSR handled by high level */ 218 219 u_char *ibuf; /* start of input buffer */ 220 u_char *ibufend; /* end of input buffer */ 221 u_char *ibufold; /* old input buffer, to be freed */ 222 u_char *ihighwater; /* threshold in input buffer */ 223 u_char *iptr; /* next free spot in input buffer */ 224 int ibufsize; /* size of ibuf (not include error bytes) */ 225 int ierroff; /* offset of error bytes in ibuf */ 226 227 struct lbq obufq; /* head of queue of output buffers */ 228 struct lbq obufs[2]; /* output buffers */ 229 230 bus_space_tag_t bst; 231 bus_space_handle_t bsh; 232 233 Port_t data_port; /* i/o ports */ 234#ifdef COM_ESP 235 Port_t esp_port; 236#endif 237 Port_t int_ctl_port; 238 Port_t int_id_port; 239 Port_t modem_ctl_port; 240 Port_t line_status_port; 241 Port_t modem_status_port; 242 243 struct tty *tp; /* cross reference */ 244 245 /* Initial state. */ 246 struct termios it_in; /* should be in struct tty */ 247 struct termios it_out; 248 249 /* Lock state. */ 250 struct termios lt_in; /* should be in struct tty */ 251 struct termios lt_out; 252 253 bool_t do_timestamp; 254 struct timeval timestamp; 255 struct pps_state pps; 256 int pps_bit; 257#ifdef ALT_BREAK_TO_DEBUGGER 258 int alt_brk_state; 259#endif 260 261 u_long bytes_in; /* statistics */ 262 u_long bytes_out; 263 u_int delta_error_counts[CE_NTYPES]; 264 u_long error_counts[CE_NTYPES]; 265 266 u_long rclk; 267 268 struct resource *irqres; 269 struct resource *ioportres; 270 int ioportrid; 271 void *cookie; 272 struct cdev *devs[6]; 273 274 /* 275 * Data area for output buffers. Someday we should build the output 276 * buffer queue without copying data. 277 */ 278 u_char obuf1[256]; 279 u_char obuf2[256]; 280}; 281 282#ifdef COM_ESP 283static int espattach(struct com_s *com, Port_t esp_port); 284#endif 285 286static void combreak(struct tty *tp, int sig); 287static timeout_t siobusycheck; 288static u_int siodivisor(u_long rclk, speed_t speed); 289static timeout_t siodtrwakeup; 290static void comhardclose(struct com_s *com); 291static void sioinput(struct com_s *com); 292static void siointr1(struct com_s *com); 293static void siointr(void *arg); 294static int commodem(struct tty *tp, int sigon, int sigoff); 295static int comparam(struct tty *tp, struct termios *t); 296static void siopoll(void *); 297static void siosettimeout(void); 298static int siosetwater(struct com_s *com, speed_t speed); 299static void comstart(struct tty *tp); 300static void comstop(struct tty *tp, int rw); 301static timeout_t comwakeup; 302 303char sio_driver_name[] = "sio"; 304static struct mtx sio_lock; 305static int sio_inited; 306 307/* table and macro for fast conversion from a unit number to its com struct */ 308devclass_t sio_devclass; 309#define com_addr(unit) ((struct com_s *) \ 310 devclass_get_softc(sio_devclass, unit)) /* XXX */ 311 312static d_open_t sioopen; 313static d_close_t sioclose; 314static d_read_t sioread; 315static d_write_t siowrite; 316static d_ioctl_t sioioctl; 317 318static struct cdevsw sio_cdevsw = { 319 .d_version = D_VERSION, 320 .d_open = sioopen, 321 .d_close = sioclose, 322 .d_read = sioread, 323 .d_write = siowrite, 324 .d_ioctl = sioioctl, 325 .d_name = sio_driver_name, 326 .d_flags = D_TTY | D_NEEDGIANT, 327}; 328 329static d_open_t siocopen; 330static d_close_t siocclose; 331static d_read_t siocrdwr; 332static d_ioctl_t siocioctl; 333 334static struct cdevsw sioc_cdevsw = { 335 .d_version = D_VERSION, 336 .d_open = siocopen, 337 .d_close = siocclose, 338 .d_read = siocrdwr, 339 .d_write = siocrdwr, 340 .d_ioctl = siocioctl, 341 .d_name = sio_driver_name, 342 .d_flags = D_TTY | D_NEEDGIANT, 343}; 344 345int comconsole = -1; 346static volatile speed_t comdefaultrate = CONSPEED; 347static u_long comdefaultrclk = DEFAULT_RCLK; 348SYSCTL_ULONG(_machdep, OID_AUTO, conrclk, CTLFLAG_RW, &comdefaultrclk, 0, ""); 349static speed_t gdbdefaultrate = GDBSPEED; 350SYSCTL_UINT(_machdep, OID_AUTO, gdbspeed, CTLFLAG_RW, 351 &gdbdefaultrate, GDBSPEED, ""); 352static u_int com_events; /* input chars + weighted output completions */ 353static Port_t siocniobase; 354static int siocnunit = -1; 355static Port_t siogdbiobase; 356static int siogdbunit = -1; 357static void *sio_slow_ih; 358static void *sio_fast_ih; 359static int sio_timeout; 360static int sio_timeouts_until_log; 361static struct callout_handle sio_timeout_handle 362 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle); 363static int sio_numunits; 364 365#ifdef COM_ESP 366/* XXX configure this properly. */ 367/* XXX quite broken for new-bus. */ 368static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, }; 369static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 }; 370#endif 371 372/* 373 * handle sysctl read/write requests for console speed 374 * 375 * In addition to setting comdefaultrate for I/O through /dev/console, 376 * also set the initial and lock values for the /dev/ttyXX device 377 * if there is one associated with the console. Finally, if the /dev/tty 378 * device has already been open, change the speed on the open running port 379 * itself. 380 */ 381 382static int 383sysctl_machdep_comdefaultrate(SYSCTL_HANDLER_ARGS) 384{ 385 int error, s; 386 speed_t newspeed; 387 struct com_s *com; 388 struct tty *tp; 389 390 newspeed = comdefaultrate; 391 392 error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req); 393 if (error || !req->newptr) 394 return (error); 395 396 comdefaultrate = newspeed; 397 398 if (comconsole < 0) /* serial console not selected? */ 399 return (0); 400 401 com = com_addr(comconsole); 402 if (com == NULL) 403 return (ENXIO); 404 405 /* 406 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX 407 * (note, the lock rates really are boolean -- if non-zero, disallow 408 * speed changes) 409 */ 410 com->it_in.c_ispeed = com->it_in.c_ospeed = 411 com->lt_in.c_ispeed = com->lt_in.c_ospeed = 412 com->it_out.c_ispeed = com->it_out.c_ospeed = 413 com->lt_out.c_ispeed = com->lt_out.c_ospeed = comdefaultrate; 414 415 /* 416 * if we're open, change the running rate too 417 */ 418 tp = com->tp; 419 if (tp && (tp->t_state & TS_ISOPEN)) { 420 tp->t_termios.c_ispeed = 421 tp->t_termios.c_ospeed = comdefaultrate; 422 s = spltty(); 423 error = comparam(tp, &tp->t_termios); 424 splx(s); 425 } 426 return error; 427} 428 429SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW, 430 0, 0, sysctl_machdep_comdefaultrate, "I", ""); 431/* TUNABLE_INT("machdep.conspeed", &comdefaultrate); */ 432 433#define SET_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) | (bit)) 434#define CLR_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) & ~(bit)) 435 436/* 437 * Unload the driver and clear the table. 438 * XXX this is mostly wrong. 439 * XXX TODO: 440 * This is usually called when the card is ejected, but 441 * can be caused by a kldunload of a controller driver. 442 * The idea is to reset the driver's view of the device 443 * and ensure that any driver entry points such as 444 * read and write do not hang. 445 */ 446int 447siodetach(dev) 448 device_t dev; 449{ 450 struct com_s *com; 451 int i; 452 453 com = (struct com_s *) device_get_softc(dev); 454 if (com == NULL) { 455 device_printf(dev, "NULL com in siounload\n"); 456 return (0); 457 } 458 com->gone = TRUE; 459 for (i = 0 ; i < 6; i++) 460 destroy_dev(com->devs[i]); 461 if (com->irqres) { 462 bus_teardown_intr(dev, com->irqres, com->cookie); 463 bus_release_resource(dev, SYS_RES_IRQ, 0, com->irqres); 464 } 465 if (com->ioportres) 466 bus_release_resource(dev, SYS_RES_IOPORT, com->ioportrid, 467 com->ioportres); 468 if (com->tp && (com->tp->t_state & TS_ISOPEN)) { 469 device_printf(dev, "still open, forcing close\n"); 470 ttyld_close(com->tp, 0); 471 ttyclose(com->tp); 472 } else { 473 if (com->ibuf != NULL) 474 free(com->ibuf, M_DEVBUF); 475 device_set_softc(dev, NULL); 476 free(com, M_DEVBUF); 477 } 478 return (0); 479} 480 481int 482sioprobe(dev, xrid, rclk, noprobe) 483 device_t dev; 484 int xrid; 485 u_long rclk; 486 int noprobe; 487{ 488#if 0 489 static bool_t already_init; 490 device_t xdev; 491#endif 492 struct com_s *com; 493 u_int divisor; 494 bool_t failures[10]; 495 int fn; 496 device_t idev; 497 Port_t iobase; 498 intrmask_t irqmap[4]; 499 intrmask_t irqs; 500 u_char mcr_image; 501 int result; 502 u_long xirq; 503 u_int flags = device_get_flags(dev); 504 int rid; 505 struct resource *port; 506 507 rid = xrid; 508 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 509 0, ~0, IO_COMSIZE, RF_ACTIVE); 510 if (!port) 511 return (ENXIO); 512 513 com = malloc(sizeof(*com), M_DEVBUF, M_NOWAIT | M_ZERO); 514 if (com == NULL) { 515 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 516 return (ENOMEM); 517 } 518 device_set_softc(dev, com); 519 com->bst = rman_get_bustag(port); 520 com->bsh = rman_get_bushandle(port); 521 if (rclk == 0) 522 rclk = DEFAULT_RCLK; 523 com->rclk = rclk; 524 525 while (sio_inited != 2) 526 if (atomic_cmpset_int(&sio_inited, 0, 1)) { 527 mtx_init(&sio_lock, sio_driver_name, NULL, 528 (comconsole != -1) ? 529 MTX_SPIN | MTX_QUIET : MTX_SPIN); 530 atomic_store_rel_int(&sio_inited, 2); 531 } 532 533#if 0 534 /* 535 * XXX this is broken - when we are first called, there are no 536 * previously configured IO ports. We could hard code 537 * 0x3f8, 0x2f8, 0x3e8, 0x2e8 etc but that's probably worse. 538 * This code has been doing nothing since the conversion since 539 * "count" is zero the first time around. 540 */ 541 if (!already_init) { 542 /* 543 * Turn off MCR_IENABLE for all likely serial ports. An unused 544 * port with its MCR_IENABLE gate open will inhibit interrupts 545 * from any used port that shares the interrupt vector. 546 * XXX the gate enable is elsewhere for some multiports. 547 */ 548 device_t *devs; 549 int count, i, xioport; 550 551 devclass_get_devices(sio_devclass, &devs, &count); 552 for (i = 0; i < count; i++) { 553 xdev = devs[i]; 554 if (device_is_enabled(xdev) && 555 bus_get_resource(xdev, SYS_RES_IOPORT, 0, &xioport, 556 NULL) == 0) 557 outb(xioport + com_mcr, 0); 558 } 559 free(devs, M_TEMP); 560 already_init = TRUE; 561 } 562#endif 563 564 if (COM_LLCONSOLE(flags)) { 565 printf("sio%d: reserved for low-level i/o\n", 566 device_get_unit(dev)); 567 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 568 device_set_softc(dev, NULL); 569 free(com, M_DEVBUF); 570 return (ENXIO); 571 } 572 573 /* 574 * If the device is on a multiport card and has an AST/4 575 * compatible interrupt control register, initialize this 576 * register and prepare to leave MCR_IENABLE clear in the mcr. 577 * Otherwise, prepare to set MCR_IENABLE in the mcr. 578 * Point idev to the device struct giving the correct id_irq. 579 * This is the struct for the master device if there is one. 580 */ 581 idev = dev; 582 mcr_image = MCR_IENABLE; 583#ifdef COM_MULTIPORT 584 if (COM_ISMULTIPORT(flags)) { 585 Port_t xiobase; 586 u_long io; 587 588 idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags)); 589 if (idev == NULL) { 590 printf("sio%d: master device %d not configured\n", 591 device_get_unit(dev), COM_MPMASTER(flags)); 592 idev = dev; 593 } 594 if (!COM_NOTAST4(flags)) { 595 if (bus_get_resource(idev, SYS_RES_IOPORT, 0, &io, 596 NULL) == 0) { 597 xiobase = io; 598 if (bus_get_resource(idev, SYS_RES_IRQ, 0, 599 NULL, NULL) == 0) 600 outb(xiobase + com_scr, 0x80); 601 else 602 outb(xiobase + com_scr, 0); 603 } 604 mcr_image = 0; 605 } 606 } 607#endif /* COM_MULTIPORT */ 608 if (bus_get_resource(idev, SYS_RES_IRQ, 0, NULL, NULL) != 0) 609 mcr_image = 0; 610 611 bzero(failures, sizeof failures); 612 iobase = rman_get_start(port); 613 614 /* 615 * We don't want to get actual interrupts, just masked ones. 616 * Interrupts from this line should already be masked in the ICU, 617 * but mask them in the processor as well in case there are some 618 * (misconfigured) shared interrupts. 619 */ 620 mtx_lock_spin(&sio_lock); 621/* EXTRA DELAY? */ 622 623 /* 624 * For the TI16754 chips, set prescaler to 1 (4 is often the 625 * default after-reset value) as otherwise it's impossible to 626 * get highest baudrates. 627 */ 628 if (COM_TI16754(flags)) { 629 u_char cfcr, efr; 630 631 cfcr = sio_getreg(com, com_cfcr); 632 sio_setreg(com, com_cfcr, CFCR_EFR_ENABLE); 633 efr = sio_getreg(com, com_efr); 634 /* Unlock extended features to turn off prescaler. */ 635 sio_setreg(com, com_efr, efr | EFR_EFE); 636 /* Disable EFR. */ 637 sio_setreg(com, com_cfcr, (cfcr != CFCR_EFR_ENABLE) ? cfcr : 0); 638 /* Turn off prescaler. */ 639 sio_setreg(com, com_mcr, 640 sio_getreg(com, com_mcr) & ~MCR_PRESCALE); 641 sio_setreg(com, com_cfcr, CFCR_EFR_ENABLE); 642 sio_setreg(com, com_efr, efr); 643 sio_setreg(com, com_cfcr, cfcr); 644 } 645 646 /* 647 * Initialize the speed and the word size and wait long enough to 648 * drain the maximum of 16 bytes of junk in device output queues. 649 * The speed is undefined after a master reset and must be set 650 * before relying on anything related to output. There may be 651 * junk after a (very fast) soft reboot and (apparently) after 652 * master reset. 653 * XXX what about the UART bug avoided by waiting in comparam()? 654 * We don't want to to wait long enough to drain at 2 bps. 655 */ 656 if (iobase == siocniobase) 657 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10)); 658 else { 659 sio_setreg(com, com_cfcr, CFCR_DLAB | CFCR_8BITS); 660 divisor = siodivisor(rclk, SIO_TEST_SPEED); 661 sio_setreg(com, com_dlbl, divisor & 0xff); 662 sio_setreg(com, com_dlbh, divisor >> 8); 663 sio_setreg(com, com_cfcr, CFCR_8BITS); 664 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10)); 665 } 666 667 /* 668 * Enable the interrupt gate and disable device interupts. This 669 * should leave the device driving the interrupt line low and 670 * guarantee an edge trigger if an interrupt can be generated. 671 */ 672/* EXTRA DELAY? */ 673 sio_setreg(com, com_mcr, mcr_image); 674 sio_setreg(com, com_ier, 0); 675 DELAY(1000); /* XXX */ 676 irqmap[0] = isa_irq_pending(); 677 678 /* 679 * Attempt to set loopback mode so that we can send a null byte 680 * without annoying any external device. 681 */ 682/* EXTRA DELAY? */ 683 sio_setreg(com, com_mcr, mcr_image | MCR_LOOPBACK); 684 685 /* 686 * Attempt to generate an output interrupt. On 8250's, setting 687 * IER_ETXRDY generates an interrupt independent of the current 688 * setting and independent of whether the THR is empty. On 16450's, 689 * setting IER_ETXRDY generates an interrupt independent of the 690 * current setting. On 16550A's, setting IER_ETXRDY only 691 * generates an interrupt when IER_ETXRDY is not already set. 692 */ 693 sio_setreg(com, com_ier, IER_ETXRDY); 694 695 /* 696 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate 697 * an interrupt. They'd better generate one for actually doing 698 * output. Loopback may be broken on the same incompatibles but 699 * it's unlikely to do more than allow the null byte out. 700 */ 701 sio_setreg(com, com_data, 0); 702 if (iobase == siocniobase) 703 DELAY((1 + 2) * 1000000 / (comdefaultrate / 10)); 704 else 705 DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10)); 706 707 /* 708 * Turn off loopback mode so that the interrupt gate works again 709 * (MCR_IENABLE was hidden). This should leave the device driving 710 * an interrupt line high. It doesn't matter if the interrupt 711 * line oscillates while we are not looking at it, since interrupts 712 * are disabled. 713 */ 714/* EXTRA DELAY? */ 715 sio_setreg(com, com_mcr, mcr_image); 716 717 /* 718 * It seems my Xircom CBEM56G Cardbus modem wants to be reset 719 * to 8 bits *again*, or else probe test 0 will fail. 720 * gwk@sgi.com, 4/19/2001 721 */ 722 sio_setreg(com, com_cfcr, CFCR_8BITS); 723 724 /* 725 * Some PCMCIA cards (Palido 321s, DC-1S, ...) have the "TXRDY bug", 726 * so we probe for a buggy IIR_TXRDY implementation even in the 727 * noprobe case. We don't probe for it in the !noprobe case because 728 * noprobe is always set for PCMCIA cards and the problem is not 729 * known to affect any other cards. 730 */ 731 if (noprobe) { 732 /* Read IIR a few times. */ 733 for (fn = 0; fn < 2; fn ++) { 734 DELAY(10000); 735 failures[6] = sio_getreg(com, com_iir); 736 } 737 738 /* IIR_TXRDY should be clear. Is it? */ 739 result = 0; 740 if (failures[6] & IIR_TXRDY) { 741 /* 742 * No. We seem to have the bug. Does our fix for 743 * it work? 744 */ 745 sio_setreg(com, com_ier, 0); 746 if (sio_getreg(com, com_iir) & IIR_NOPEND) { 747 /* Yes. We discovered the TXRDY bug! */ 748 SET_FLAG(dev, COM_C_IIR_TXRDYBUG); 749 } else { 750 /* No. Just fail. XXX */ 751 result = ENXIO; 752 sio_setreg(com, com_mcr, 0); 753 } 754 } else { 755 /* Yes. No bug. */ 756 CLR_FLAG(dev, COM_C_IIR_TXRDYBUG); 757 } 758 sio_setreg(com, com_ier, 0); 759 sio_setreg(com, com_cfcr, CFCR_8BITS); 760 mtx_unlock_spin(&sio_lock); 761 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 762 if (iobase == siocniobase) 763 result = 0; 764 if (result != 0) { 765 device_set_softc(dev, NULL); 766 free(com, M_DEVBUF); 767 } 768 return (result); 769 } 770 771 /* 772 * Check that 773 * o the CFCR, IER and MCR in UART hold the values written to them 774 * (the values happen to be all distinct - this is good for 775 * avoiding false positive tests from bus echoes). 776 * o an output interrupt is generated and its vector is correct. 777 * o the interrupt goes away when the IIR in the UART is read. 778 */ 779/* EXTRA DELAY? */ 780 failures[0] = sio_getreg(com, com_cfcr) - CFCR_8BITS; 781 failures[1] = sio_getreg(com, com_ier) - IER_ETXRDY; 782 failures[2] = sio_getreg(com, com_mcr) - mcr_image; 783 DELAY(10000); /* Some internal modems need this time */ 784 irqmap[1] = isa_irq_pending(); 785 failures[4] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_TXRDY; 786 DELAY(1000); /* XXX */ 787 irqmap[2] = isa_irq_pending(); 788 failures[6] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND; 789 790 /* 791 * Turn off all device interrupts and check that they go off properly. 792 * Leave MCR_IENABLE alone. For ports without a master port, it gates 793 * the OUT2 output of the UART to 794 * the ICU input. Closing the gate would give a floating ICU input 795 * (unless there is another device driving it) and spurious interrupts. 796 * (On the system that this was first tested on, the input floats high 797 * and gives a (masked) interrupt as soon as the gate is closed.) 798 */ 799 sio_setreg(com, com_ier, 0); 800 sio_setreg(com, com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */ 801 failures[7] = sio_getreg(com, com_ier); 802 DELAY(1000); /* XXX */ 803 irqmap[3] = isa_irq_pending(); 804 failures[9] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND; 805 806 mtx_unlock_spin(&sio_lock); 807 808 irqs = irqmap[1] & ~irqmap[0]; 809 if (bus_get_resource(idev, SYS_RES_IRQ, 0, &xirq, NULL) == 0 && 810 ((1 << xirq) & irqs) == 0) { 811 printf( 812 "sio%d: configured irq %ld not in bitmap of probed irqs %#x\n", 813 device_get_unit(dev), xirq, irqs); 814 printf( 815 "sio%d: port may not be enabled\n", 816 device_get_unit(dev)); 817 } 818 if (bootverbose) 819 printf("sio%d: irq maps: %#x %#x %#x %#x\n", 820 device_get_unit(dev), 821 irqmap[0], irqmap[1], irqmap[2], irqmap[3]); 822 823 result = 0; 824 for (fn = 0; fn < sizeof failures; ++fn) 825 if (failures[fn]) { 826 sio_setreg(com, com_mcr, 0); 827 result = ENXIO; 828 if (bootverbose) { 829 printf("sio%d: probe failed test(s):", 830 device_get_unit(dev)); 831 for (fn = 0; fn < sizeof failures; ++fn) 832 if (failures[fn]) 833 printf(" %d", fn); 834 printf("\n"); 835 } 836 break; 837 } 838 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 839 if (iobase == siocniobase) 840 result = 0; 841 if (result != 0) { 842 device_set_softc(dev, NULL); 843 free(com, M_DEVBUF); 844 } 845 return (result); 846} 847 848#ifdef COM_ESP 849static int 850espattach(com, esp_port) 851 struct com_s *com; 852 Port_t esp_port; 853{ 854 u_char dips; 855 u_char val; 856 857 /* 858 * Check the ESP-specific I/O port to see if we're an ESP 859 * card. If not, return failure immediately. 860 */ 861 if ((inb(esp_port) & 0xf3) == 0) { 862 printf(" port 0x%x is not an ESP board?\n", esp_port); 863 return (0); 864 } 865 866 /* 867 * We've got something that claims to be a Hayes ESP card. 868 * Let's hope so. 869 */ 870 871 /* Get the dip-switch configuration */ 872 outb(esp_port + ESP_CMD1, ESP_GETDIPS); 873 dips = inb(esp_port + ESP_STATUS1); 874 875 /* 876 * Bits 0,1 of dips say which COM port we are. 877 */ 878 if (rman_get_start(com->ioportres) == likely_com_ports[dips & 0x03]) 879 printf(" : ESP"); 880 else { 881 printf(" esp_port has com %d\n", dips & 0x03); 882 return (0); 883 } 884 885 /* 886 * Check for ESP version 2.0 or later: bits 4,5,6 = 010. 887 */ 888 outb(esp_port + ESP_CMD1, ESP_GETTEST); 889 val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */ 890 val = inb(esp_port + ESP_STATUS2); 891 if ((val & 0x70) < 0x20) { 892 printf("-old (%o)", val & 0x70); 893 return (0); 894 } 895 896 /* 897 * Check for ability to emulate 16550: bit 7 == 1 898 */ 899 if ((dips & 0x80) == 0) { 900 printf(" slave"); 901 return (0); 902 } 903 904 /* 905 * Okay, we seem to be a Hayes ESP card. Whee. 906 */ 907 com->esp = TRUE; 908 com->esp_port = esp_port; 909 return (1); 910} 911#endif /* COM_ESP */ 912 913int 914sioattach(dev, xrid, rclk) 915 device_t dev; 916 int xrid; 917 u_long rclk; 918{ 919 struct com_s *com; 920#ifdef COM_ESP 921 Port_t *espp; 922#endif 923 Port_t iobase; 924 int minorbase; 925 int unit; 926 u_int flags; 927 int rid; 928 struct resource *port; 929 int ret; 930 931 rid = xrid; 932 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 933 0, ~0, IO_COMSIZE, RF_ACTIVE); 934 if (!port) 935 return (ENXIO); 936 937 iobase = rman_get_start(port); 938 unit = device_get_unit(dev); 939 com = device_get_softc(dev); 940 flags = device_get_flags(dev); 941 942 if (unit >= sio_numunits) 943 sio_numunits = unit + 1; 944 /* 945 * sioprobe() has initialized the device registers as follows: 946 * o cfcr = CFCR_8BITS. 947 * It is most important that CFCR_DLAB is off, so that the 948 * data port is not hidden when we enable interrupts. 949 * o ier = 0. 950 * Interrupts are only enabled when the line is open. 951 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible 952 * interrupt control register or the config specifies no irq. 953 * Keeping MCR_DTR and MCR_RTS off might stop the external 954 * device from sending before we are ready. 955 */ 956 bzero(com, sizeof *com); 957 com->unit = unit; 958 com->ioportres = port; 959 com->ioportrid = rid; 960 com->bst = rman_get_bustag(port); 961 com->bsh = rman_get_bushandle(port); 962 com->cfcr_image = CFCR_8BITS; 963 com->dtr_wait = 3 * hz; 964 com->loses_outints = COM_LOSESOUTINTS(flags) != 0; 965 com->no_irq = bus_get_resource(dev, SYS_RES_IRQ, 0, NULL, NULL) != 0; 966 com->tx_fifo_size = 1; 967 com->obufs[0].l_head = com->obuf1; 968 com->obufs[1].l_head = com->obuf2; 969 970 com->data_port = iobase + com_data; 971 com->int_ctl_port = iobase + com_ier; 972 com->int_id_port = iobase + com_iir; 973 com->modem_ctl_port = iobase + com_mcr; 974 com->mcr_image = inb(com->modem_ctl_port); 975 com->line_status_port = iobase + com_lsr; 976 com->modem_status_port = iobase + com_msr; 977 978 if (rclk == 0) 979 rclk = DEFAULT_RCLK; 980 com->rclk = rclk; 981 982 /* 983 * We don't use all the flags from <sys/ttydefaults.h> since they 984 * are only relevant for logins. It's important to have echo off 985 * initially so that the line doesn't start blathering before the 986 * echo flag can be turned off. 987 */ 988 com->it_in.c_iflag = 0; 989 com->it_in.c_oflag = 0; 990 com->it_in.c_cflag = TTYDEF_CFLAG; 991 com->it_in.c_lflag = 0; 992 if (unit == comconsole) { 993 com->it_in.c_iflag = TTYDEF_IFLAG; 994 com->it_in.c_oflag = TTYDEF_OFLAG; 995 com->it_in.c_cflag = TTYDEF_CFLAG | CLOCAL; 996 com->it_in.c_lflag = TTYDEF_LFLAG; 997 com->lt_out.c_cflag = com->lt_in.c_cflag = CLOCAL; 998 com->lt_out.c_ispeed = com->lt_out.c_ospeed = 999 com->lt_in.c_ispeed = com->lt_in.c_ospeed = 1000 com->it_in.c_ispeed = com->it_in.c_ospeed = comdefaultrate; 1001 } else 1002 com->it_in.c_ispeed = com->it_in.c_ospeed = TTYDEF_SPEED; 1003 if (siosetwater(com, com->it_in.c_ispeed) != 0) { 1004 mtx_unlock_spin(&sio_lock); 1005 /* 1006 * Leave i/o resources allocated if this is a `cn'-level 1007 * console, so that other devices can't snarf them. 1008 */ 1009 if (iobase != siocniobase) 1010 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1011 return (ENOMEM); 1012 } 1013 mtx_unlock_spin(&sio_lock); 1014 termioschars(&com->it_in); 1015 com->it_out = com->it_in; 1016 1017 /* attempt to determine UART type */ 1018 printf("sio%d: type", unit); 1019 1020 1021 if (!COM_ISMULTIPORT(flags) && 1022 !COM_IIR_TXRDYBUG(flags) && !COM_NOSCR(flags)) { 1023 u_char scr; 1024 u_char scr1; 1025 u_char scr2; 1026 1027 scr = sio_getreg(com, com_scr); 1028 sio_setreg(com, com_scr, 0xa5); 1029 scr1 = sio_getreg(com, com_scr); 1030 sio_setreg(com, com_scr, 0x5a); 1031 scr2 = sio_getreg(com, com_scr); 1032 sio_setreg(com, com_scr, scr); 1033 if (scr1 != 0xa5 || scr2 != 0x5a) { 1034 printf(" 8250 or not responding"); 1035 goto determined_type; 1036 } 1037 } 1038 sio_setreg(com, com_fifo, FIFO_ENABLE | FIFO_RX_HIGH); 1039 DELAY(100); 1040 switch (inb(com->int_id_port) & IIR_FIFO_MASK) { 1041 case FIFO_RX_LOW: 1042 printf(" 16450"); 1043 break; 1044 case FIFO_RX_MEDL: 1045 printf(" 16450?"); 1046 break; 1047 case FIFO_RX_MEDH: 1048 printf(" 16550?"); 1049 break; 1050 case FIFO_RX_HIGH: 1051 if (COM_NOFIFO(flags)) { 1052 printf(" 16550A fifo disabled"); 1053 break; 1054 } 1055 com->hasfifo = TRUE; 1056 if (COM_ST16650A(flags)) { 1057 printf(" ST16650A"); 1058 com->st16650a = TRUE; 1059 com->tx_fifo_size = 32; 1060 break; 1061 } 1062 if (COM_TI16754(flags)) { 1063 printf(" TI16754"); 1064 com->tx_fifo_size = 64; 1065 break; 1066 } 1067 printf(" 16550A"); 1068#ifdef COM_ESP 1069 for (espp = likely_esp_ports; *espp != 0; espp++) 1070 if (espattach(com, *espp)) { 1071 com->tx_fifo_size = 1024; 1072 break; 1073 } 1074 if (com->esp) 1075 break; 1076#endif 1077 com->tx_fifo_size = COM_FIFOSIZE(flags); 1078 if (com->tx_fifo_size == 0) 1079 com->tx_fifo_size = 16; 1080 else 1081 printf(" lookalike with %u bytes FIFO", 1082 com->tx_fifo_size); 1083 break; 1084 } 1085#ifdef COM_ESP 1086 if (com->esp) { 1087 /* 1088 * Set 16550 compatibility mode. 1089 * We don't use the ESP_MODE_SCALE bit to increase the 1090 * fifo trigger levels because we can't handle large 1091 * bursts of input. 1092 * XXX flow control should be set in comparam(), not here. 1093 */ 1094 outb(com->esp_port + ESP_CMD1, ESP_SETMODE); 1095 outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO); 1096 1097 /* Set RTS/CTS flow control. */ 1098 outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE); 1099 outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS); 1100 outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS); 1101 1102 /* Set flow-control levels. */ 1103 outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW); 1104 outb(com->esp_port + ESP_CMD2, HIBYTE(768)); 1105 outb(com->esp_port + ESP_CMD2, LOBYTE(768)); 1106 outb(com->esp_port + ESP_CMD2, HIBYTE(512)); 1107 outb(com->esp_port + ESP_CMD2, LOBYTE(512)); 1108 } 1109#endif /* COM_ESP */ 1110 sio_setreg(com, com_fifo, 0); 1111determined_type: ; 1112 1113#ifdef COM_MULTIPORT 1114 if (COM_ISMULTIPORT(flags)) { 1115 device_t masterdev; 1116 1117 com->multiport = TRUE; 1118 printf(" (multiport"); 1119 if (unit == COM_MPMASTER(flags)) 1120 printf(" master"); 1121 printf(")"); 1122 masterdev = devclass_get_device(sio_devclass, 1123 COM_MPMASTER(flags)); 1124 com->no_irq = (masterdev == NULL || bus_get_resource(masterdev, 1125 SYS_RES_IRQ, 0, NULL, NULL) != 0); 1126 } 1127#endif /* COM_MULTIPORT */ 1128 if (unit == comconsole) 1129 printf(", console"); 1130 if (COM_IIR_TXRDYBUG(flags)) 1131 printf(" with a buggy IIR_TXRDY implementation"); 1132 printf("\n"); 1133 1134 if (sio_fast_ih == NULL) { 1135 swi_add(&tty_ithd, "sio", siopoll, NULL, SWI_TTY, 0, 1136 &sio_fast_ih); 1137 swi_add(&clk_ithd, "sio", siopoll, NULL, SWI_CLOCK, 0, 1138 &sio_slow_ih); 1139 } 1140 minorbase = UNIT_TO_MINOR(unit); 1141 com->devs[0] = make_dev(&sio_cdevsw, minorbase, 1142 UID_ROOT, GID_WHEEL, 0600, "ttyd%r", unit); 1143 com->devs[1] = make_dev(&sioc_cdevsw, minorbase | CONTROL_INIT_STATE, 1144 UID_ROOT, GID_WHEEL, 0600, "ttyid%r", unit); 1145 com->devs[2] = make_dev(&sioc_cdevsw, minorbase | CONTROL_LOCK_STATE, 1146 UID_ROOT, GID_WHEEL, 0600, "ttyld%r", unit); 1147 com->devs[3] = make_dev(&sio_cdevsw, minorbase | CALLOUT_MASK, 1148 UID_UUCP, GID_DIALER, 0660, "cuaa%r", unit); 1149 com->devs[4] = make_dev(&sioc_cdevsw, 1150 minorbase | CALLOUT_MASK | CONTROL_INIT_STATE, 1151 UID_UUCP, GID_DIALER, 0660, "cuaia%r", unit); 1152 com->devs[5] = make_dev(&sioc_cdevsw, 1153 minorbase | CALLOUT_MASK | CONTROL_LOCK_STATE, 1154 UID_UUCP, GID_DIALER, 0660, "cuala%r", unit); 1155 for (rid = 0; rid < 6; rid++) 1156 com->devs[rid]->si_drv1 = com; 1157 com->flags = flags; 1158 com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 1159 1160 if (COM_PPSCTS(flags)) 1161 com->pps_bit = MSR_CTS; 1162 else 1163 com->pps_bit = MSR_DCD; 1164 pps_init(&com->pps); 1165 1166 rid = 0; 1167 com->irqres = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); 1168 if (com->irqres) { 1169 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, com->irqres, 1170 INTR_TYPE_TTY | INTR_FAST, 1171 siointr, com, &com->cookie); 1172 if (ret) { 1173 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, 1174 com->irqres, INTR_TYPE_TTY, 1175 siointr, com, &com->cookie); 1176 if (ret == 0) 1177 device_printf(dev, "unable to activate interrupt in fast mode - using normal mode\n"); 1178 } 1179 if (ret) 1180 device_printf(dev, "could not activate interrupt\n"); 1181#if defined(DDB) && (defined(BREAK_TO_DEBUGGER) || \ 1182 defined(ALT_BREAK_TO_DEBUGGER)) 1183 /* 1184 * Enable interrupts for early break-to-debugger support 1185 * on the console. 1186 */ 1187 if (ret == 0 && unit == comconsole) 1188 outb(siocniobase + com_ier, IER_ERXRDY | IER_ERLS | 1189 IER_EMSC); 1190#endif 1191 } 1192 1193 return (0); 1194} 1195 1196static int 1197siocopen(dev, flag, mode, td) 1198 struct cdev *dev; 1199 int flag; 1200 int mode; 1201 struct thread *td; 1202{ 1203 struct com_s *com; 1204 1205 com = dev->si_drv1; 1206 if (com == NULL) 1207 return (ENXIO); 1208 if (com->gone) 1209 return (ENXIO); 1210 return (0); 1211} 1212 1213static int 1214sioopen(dev, flag, mode, td) 1215 struct cdev *dev; 1216 int flag; 1217 int mode; 1218 struct thread *td; 1219{ 1220 struct com_s *com; 1221 int error; 1222 int mynor; 1223 int s; 1224 struct tty *tp; 1225 int unit; 1226 1227 mynor = minor(dev); 1228 unit = MINOR_TO_UNIT(mynor); 1229 com = dev->si_drv1; 1230 if (com == NULL) 1231 return (ENXIO); 1232 if (com->gone) 1233 return (ENXIO); 1234 tp = dev->si_tty = com->tp = ttymalloc(com->tp); 1235 s = spltty(); 1236 /* 1237 * We jump to this label after all non-interrupted sleeps to pick 1238 * up any changes of the device state. 1239 */ 1240open_top: 1241 while (com->state & CS_DTR_OFF) { 1242 error = tsleep(&com->dtr_wait, TTIPRI | PCATCH, "siodtr", 0); 1243 if (com_addr(unit) == NULL) 1244 return (ENXIO); 1245 if (error != 0 || com->gone) 1246 goto out; 1247 } 1248 if (tp->t_state & TS_ISOPEN) { 1249 /* 1250 * The device is open, so everything has been initialized. 1251 * Handle conflicts. 1252 */ 1253 if (mynor & CALLOUT_MASK) { 1254 if (!com->active_out) { 1255 error = EBUSY; 1256 goto out; 1257 } 1258 } else { 1259 if (com->active_out) { 1260 if (flag & O_NONBLOCK) { 1261 error = EBUSY; 1262 goto out; 1263 } 1264 error = tsleep(&com->active_out, 1265 TTIPRI | PCATCH, "siobi", 0); 1266 if (com_addr(unit) == NULL) 1267 return (ENXIO); 1268 if (error != 0 || com->gone) 1269 goto out; 1270 goto open_top; 1271 } 1272 } 1273 if (tp->t_state & TS_XCLUDE && 1274 suser(td)) { 1275 error = EBUSY; 1276 goto out; 1277 } 1278 } else { 1279 /* 1280 * The device isn't open, so there are no conflicts. 1281 * Initialize it. Initialization is done twice in many 1282 * cases: to preempt sleeping callin opens if we are 1283 * callout, and to complete a callin open after DCD rises. 1284 */ 1285 tp->t_oproc = comstart; 1286 tp->t_param = comparam; 1287 tp->t_stop = comstop; 1288 tp->t_modem = commodem; 1289 tp->t_break = combreak; 1290 tp->t_dev = dev; 1291 tp->t_termios = mynor & CALLOUT_MASK 1292 ? com->it_out : com->it_in; 1293 (void)commodem(tp, SER_DTR | SER_RTS, 0); 1294 com->poll = com->no_irq; 1295 com->poll_output = com->loses_outints; 1296 ++com->wopeners; 1297 error = comparam(tp, &tp->t_termios); 1298 --com->wopeners; 1299 if (error != 0) 1300 goto out; 1301 /* 1302 * XXX we should goto open_top if comparam() slept. 1303 */ 1304 if (com->hasfifo) { 1305 int i; 1306 /* 1307 * (Re)enable and drain fifos. 1308 * 1309 * Certain SMC chips cause problems if the fifos 1310 * are enabled while input is ready. Turn off the 1311 * fifo if necessary to clear the input. We test 1312 * the input ready bit after enabling the fifos 1313 * since we've already enabled them in comparam() 1314 * and to handle races between enabling and fresh 1315 * input. 1316 */ 1317 for (i = 0; i < 500; i++) { 1318 sio_setreg(com, com_fifo, 1319 FIFO_RCV_RST | FIFO_XMT_RST 1320 | com->fifo_image); 1321 /* 1322 * XXX the delays are for superstitious 1323 * historical reasons. It must be less than 1324 * the character time at the maximum 1325 * supported speed (87 usec at 115200 bps 1326 * 8N1). Otherwise we might loop endlessly 1327 * if data is streaming in. We used to use 1328 * delays of 100. That usually worked 1329 * because DELAY(100) used to usually delay 1330 * for about 85 usec instead of 100. 1331 */ 1332 DELAY(50); 1333 if (!(inb(com->line_status_port) & LSR_RXRDY)) 1334 break; 1335 sio_setreg(com, com_fifo, 0); 1336 DELAY(50); 1337 (void) inb(com->data_port); 1338 } 1339 if (i == 500) { 1340 error = EIO; 1341 goto out; 1342 } 1343 } 1344 1345 mtx_lock_spin(&sio_lock); 1346 (void) inb(com->line_status_port); 1347 (void) inb(com->data_port); 1348 com->prev_modem_status = com->last_modem_status 1349 = inb(com->modem_status_port); 1350 outb(com->int_ctl_port, 1351 IER_ERXRDY | IER_ERLS | IER_EMSC 1352 | (COM_IIR_TXRDYBUG(com->flags) ? 0 : IER_ETXRDY)); 1353 mtx_unlock_spin(&sio_lock); 1354 /* 1355 * Handle initial DCD. Callout devices get a fake initial 1356 * DCD (trapdoor DCD). If we are callout, then any sleeping 1357 * callin opens get woken up and resume sleeping on "siobi" 1358 * instead of "siodcd". 1359 */ 1360 /* 1361 * XXX `mynor & CALLOUT_MASK' should be 1362 * `tp->t_cflag & (SOFT_CARRIER | TRAPDOOR_CARRIER) where 1363 * TRAPDOOR_CARRIER is the default initial state for callout 1364 * devices and SOFT_CARRIER is like CLOCAL except it hides 1365 * the true carrier. 1366 */ 1367 if (com->prev_modem_status & MSR_DCD || mynor & CALLOUT_MASK) 1368 ttyld_modem(tp, 1); 1369 } 1370 /* 1371 * Wait for DCD if necessary. 1372 */ 1373 if (!(tp->t_state & TS_CARR_ON) && !(mynor & CALLOUT_MASK) 1374 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 1375 ++com->wopeners; 1376 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "siodcd", 0); 1377 if (com_addr(unit) == NULL) 1378 return (ENXIO); 1379 --com->wopeners; 1380 if (error != 0 || com->gone) 1381 goto out; 1382 goto open_top; 1383 } 1384 error = ttyld_open(tp, dev); 1385 ttyldoptim(tp); 1386 if (tp->t_state & TS_ISOPEN && mynor & CALLOUT_MASK) 1387 com->active_out = TRUE; 1388 siosettimeout(); 1389out: 1390 splx(s); 1391 if (!(tp->t_state & TS_ISOPEN) && com->wopeners == 0) 1392 comhardclose(com); 1393 return (error); 1394} 1395 1396static int 1397siocclose(dev, flag, mode, td) 1398 struct cdev *dev; 1399 int flag; 1400 int mode; 1401 struct thread *td; 1402{ 1403 1404 return (0); 1405} 1406 1407static int 1408sioclose(dev, flag, mode, td) 1409 struct cdev *dev; 1410 int flag; 1411 int mode; 1412 struct thread *td; 1413{ 1414 struct com_s *com; 1415 int mynor; 1416 int s; 1417 struct tty *tp; 1418 1419 mynor = minor(dev); 1420 com = dev->si_drv1; 1421 if (com == NULL) 1422 return (ENODEV); 1423 tp = com->tp; 1424 s = spltty(); 1425 ttyld_close(tp, flag); 1426 ttyldoptim(tp); 1427 comhardclose(com); 1428 ttyclose(tp); 1429 siosettimeout(); 1430 splx(s); 1431 if (com->gone) { 1432 printf("sio%d: gone\n", com->unit); 1433 s = spltty(); 1434 if (com->ibuf != NULL) 1435 free(com->ibuf, M_DEVBUF); 1436 bzero(tp, sizeof *tp); 1437 splx(s); 1438 } 1439 return (0); 1440} 1441 1442static void 1443comhardclose(com) 1444 struct com_s *com; 1445{ 1446 int s; 1447 struct tty *tp; 1448 1449 s = spltty(); 1450 com->poll = FALSE; 1451 com->poll_output = FALSE; 1452 com->do_timestamp = FALSE; 1453 com->pps.ppsparam.mode = 0; 1454 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 1455 tp = com->tp; 1456 1457#if defined(DDB) && (defined(BREAK_TO_DEBUGGER) || \ 1458 defined(ALT_BREAK_TO_DEBUGGER)) 1459 /* 1460 * Leave interrupts enabled and don't clear DTR if this is the 1461 * console. This allows us to detect break-to-debugger events 1462 * while the console device is closed. 1463 */ 1464 if (com->unit != comconsole) 1465#endif 1466 { 1467 sio_setreg(com, com_ier, 0); 1468 if (tp->t_cflag & HUPCL 1469 /* 1470 * XXX we will miss any carrier drop between here and the 1471 * next open. Perhaps we should watch DCD even when the 1472 * port is closed; it is not sufficient to check it at 1473 * the next open because it might go up and down while 1474 * we're not watching. 1475 */ 1476 || (!com->active_out 1477 && !(com->prev_modem_status & MSR_DCD) 1478 && !(com->it_in.c_cflag & CLOCAL)) 1479 || !(tp->t_state & TS_ISOPEN)) { 1480 (void)commodem(tp, 0, SER_DTR); 1481 if (com->dtr_wait != 0 && !(com->state & CS_DTR_OFF)) { 1482 timeout(siodtrwakeup, com, com->dtr_wait); 1483 com->state |= CS_DTR_OFF; 1484 } 1485 } 1486 } 1487 if (com->hasfifo) { 1488 /* 1489 * Disable fifos so that they are off after controlled 1490 * reboots. Some BIOSes fail to detect 16550s when the 1491 * fifos are enabled. 1492 */ 1493 sio_setreg(com, com_fifo, 0); 1494 } 1495 com->active_out = FALSE; 1496 wakeup(&com->active_out); 1497 wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */ 1498 splx(s); 1499} 1500 1501static int 1502siocrdwr(dev, uio, flag) 1503 struct cdev *dev; 1504 struct uio *uio; 1505 int flag; 1506{ 1507 1508 return (ENODEV); 1509} 1510 1511static int 1512sioread(dev, uio, flag) 1513 struct cdev *dev; 1514 struct uio *uio; 1515 int flag; 1516{ 1517 struct com_s *com; 1518 1519 com = dev->si_drv1; 1520 if (com == NULL || com->gone) 1521 return (ENODEV); 1522 return (ttyld_read(com->tp, uio, flag)); 1523} 1524 1525static int 1526siowrite(dev, uio, flag) 1527 struct cdev *dev; 1528 struct uio *uio; 1529 int flag; 1530{ 1531 int mynor; 1532 struct com_s *com; 1533 int unit; 1534 1535 mynor = minor(dev); 1536 1537 unit = MINOR_TO_UNIT(mynor); 1538 com = com_addr(unit); 1539 if (com == NULL || com->gone) 1540 return (ENODEV); 1541 /* 1542 * (XXX) We disallow virtual consoles if the physical console is 1543 * a serial port. This is in case there is a display attached that 1544 * is not the console. In that situation we don't need/want the X 1545 * server taking over the console. 1546 */ 1547 if (constty != NULL && unit == comconsole) 1548 constty = NULL; 1549 return (ttyld_write(com->tp, uio, flag)); 1550} 1551 1552static void 1553siobusycheck(chan) 1554 void *chan; 1555{ 1556 struct com_s *com; 1557 int s; 1558 1559 com = (struct com_s *)chan; 1560 1561 /* 1562 * Clear TS_BUSY if low-level output is complete. 1563 * spl locking is sufficient because siointr1() does not set CS_BUSY. 1564 * If siointr1() clears CS_BUSY after we look at it, then we'll get 1565 * called again. Reading the line status port outside of siointr1() 1566 * is safe because CS_BUSY is clear so there are no output interrupts 1567 * to lose. 1568 */ 1569 s = spltty(); 1570 if (com->state & CS_BUSY) 1571 com->extra_state &= ~CSE_BUSYCHECK; /* False alarm. */ 1572 else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY)) 1573 == (LSR_TSRE | LSR_TXRDY)) { 1574 com->tp->t_state &= ~TS_BUSY; 1575 ttwwakeup(com->tp); 1576 com->extra_state &= ~CSE_BUSYCHECK; 1577 } else 1578 timeout(siobusycheck, com, hz / 100); 1579 splx(s); 1580} 1581 1582static u_int 1583siodivisor(rclk, speed) 1584 u_long rclk; 1585 speed_t speed; 1586{ 1587 long actual_speed; 1588 u_int divisor; 1589 int error; 1590 1591 if (speed == 0) 1592 return (0); 1593#if UINT_MAX > (ULONG_MAX - 1) / 8 1594 if (speed > (ULONG_MAX - 1) / 8) 1595 return (0); 1596#endif 1597 divisor = (rclk / (8UL * speed) + 1) / 2; 1598 if (divisor == 0 || divisor >= 65536) 1599 return (0); 1600 actual_speed = rclk / (16UL * divisor); 1601 1602 /* 10 times error in percent: */ 1603 error = ((actual_speed - (long)speed) * 2000 / (long)speed + 1) / 2; 1604 1605 /* 3.0% maximum error tolerance: */ 1606 if (error < -30 || error > 30) 1607 return (0); 1608 1609 return (divisor); 1610} 1611 1612static void 1613siodtrwakeup(chan) 1614 void *chan; 1615{ 1616 struct com_s *com; 1617 1618 com = (struct com_s *)chan; 1619 com->state &= ~CS_DTR_OFF; 1620 wakeup(&com->dtr_wait); 1621} 1622 1623/* 1624 * Call this function with the sio_lock mutex held. It will return with the 1625 * lock still held. 1626 */ 1627static void 1628sioinput(com) 1629 struct com_s *com; 1630{ 1631 u_char *buf; 1632 int incc; 1633 u_char line_status; 1634 int recv_data; 1635 struct tty *tp; 1636 1637 buf = com->ibuf; 1638 tp = com->tp; 1639 if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) { 1640 com_events -= (com->iptr - com->ibuf); 1641 com->iptr = com->ibuf; 1642 return; 1643 } 1644 if (tp->t_state & TS_CAN_BYPASS_L_RINT) { 1645 /* 1646 * Avoid the grotesquely inefficient lineswitch routine 1647 * (ttyinput) in "raw" mode. It usually takes about 450 1648 * instructions (that's without canonical processing or echo!). 1649 * slinput is reasonably fast (usually 40 instructions plus 1650 * call overhead). 1651 */ 1652 do { 1653 /* 1654 * This may look odd, but it is using save-and-enable 1655 * semantics instead of the save-and-disable semantics 1656 * that are used everywhere else. 1657 */ 1658 mtx_unlock_spin(&sio_lock); 1659 incc = com->iptr - buf; 1660 if (tp->t_rawq.c_cc + incc > tp->t_ihiwat 1661 && (com->state & CS_RTS_IFLOW 1662 || tp->t_iflag & IXOFF) 1663 && !(tp->t_state & TS_TBLOCK)) 1664 ttyblock(tp); 1665 com->delta_error_counts[CE_TTY_BUF_OVERFLOW] 1666 += b_to_q((char *)buf, incc, &tp->t_rawq); 1667 buf += incc; 1668 tk_nin += incc; 1669 tk_rawcc += incc; 1670 tp->t_rawcc += incc; 1671 ttwakeup(tp); 1672 if (tp->t_state & TS_TTSTOP 1673 && (tp->t_iflag & IXANY 1674 || tp->t_cc[VSTART] == tp->t_cc[VSTOP])) { 1675 tp->t_state &= ~TS_TTSTOP; 1676 tp->t_lflag &= ~FLUSHO; 1677 comstart(tp); 1678 } 1679 mtx_lock_spin(&sio_lock); 1680 } while (buf < com->iptr); 1681 } else { 1682 do { 1683 /* 1684 * This may look odd, but it is using save-and-enable 1685 * semantics instead of the save-and-disable semantics 1686 * that are used everywhere else. 1687 */ 1688 mtx_unlock_spin(&sio_lock); 1689 line_status = buf[com->ierroff]; 1690 recv_data = *buf++; 1691 if (line_status 1692 & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) { 1693 if (line_status & LSR_BI) 1694 recv_data |= TTY_BI; 1695 if (line_status & LSR_FE) 1696 recv_data |= TTY_FE; 1697 if (line_status & LSR_OE) 1698 recv_data |= TTY_OE; 1699 if (line_status & LSR_PE) 1700 recv_data |= TTY_PE; 1701 } 1702 ttyld_rint(tp, recv_data); 1703 mtx_lock_spin(&sio_lock); 1704 } while (buf < com->iptr); 1705 } 1706 com_events -= (com->iptr - com->ibuf); 1707 com->iptr = com->ibuf; 1708 1709 /* 1710 * There is now room for another low-level buffer full of input, 1711 * so enable RTS if it is now disabled and there is room in the 1712 * high-level buffer. 1713 */ 1714 if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) && 1715 !(tp->t_state & TS_TBLOCK)) 1716 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 1717} 1718 1719static void 1720siointr(arg) 1721 void *arg; 1722{ 1723 struct com_s *com; 1724 1725#ifndef COM_MULTIPORT 1726 com = (struct com_s *)arg; 1727 1728 mtx_lock_spin(&sio_lock); 1729 siointr1(com); 1730 mtx_unlock_spin(&sio_lock); 1731#else /* COM_MULTIPORT */ 1732 bool_t possibly_more_intrs; 1733 int unit; 1734 1735 /* 1736 * Loop until there is no activity on any port. This is necessary 1737 * to get an interrupt edge more than to avoid another interrupt. 1738 * If the IRQ signal is just an OR of the IRQ signals from several 1739 * devices, then the edge from one may be lost because another is 1740 * on. 1741 */ 1742 mtx_lock_spin(&sio_lock); 1743 do { 1744 possibly_more_intrs = FALSE; 1745 for (unit = 0; unit < sio_numunits; ++unit) { 1746 com = com_addr(unit); 1747 /* 1748 * XXX COM_LOCK(); 1749 * would it work here, or be counter-productive? 1750 */ 1751 if (com != NULL 1752 && !com->gone 1753 && (inb(com->int_id_port) & IIR_IMASK) 1754 != IIR_NOPEND) { 1755 siointr1(com); 1756 possibly_more_intrs = TRUE; 1757 } 1758 /* XXX COM_UNLOCK(); */ 1759 } 1760 } while (possibly_more_intrs); 1761 mtx_unlock_spin(&sio_lock); 1762#endif /* COM_MULTIPORT */ 1763} 1764 1765static struct timespec siots[8]; 1766static int siotso; 1767static int volatile siotsunit = -1; 1768 1769static int 1770sysctl_siots(SYSCTL_HANDLER_ARGS) 1771{ 1772 char buf[128]; 1773 long long delta; 1774 size_t len; 1775 int error, i, tso; 1776 1777 for (i = 1, tso = siotso; i < tso; i++) { 1778 delta = (long long)(siots[i].tv_sec - siots[i - 1].tv_sec) * 1779 1000000000 + 1780 (siots[i].tv_nsec - siots[i - 1].tv_nsec); 1781 len = sprintf(buf, "%lld\n", delta); 1782 if (delta >= 110000) 1783 len += sprintf(buf + len - 1, ": *** %ld.%09ld\n", 1784 (long)siots[i].tv_sec, siots[i].tv_nsec) - 1; 1785 if (i == tso - 1) 1786 buf[len - 1] = '\0'; 1787 error = SYSCTL_OUT(req, buf, len); 1788 if (error != 0) 1789 return (error); 1790 uio_yield(); 1791 } 1792 return (0); 1793} 1794 1795SYSCTL_PROC(_machdep, OID_AUTO, siots, CTLTYPE_STRING | CTLFLAG_RD, 1796 0, 0, sysctl_siots, "A", "sio timestamps"); 1797 1798static void 1799siointr1(com) 1800 struct com_s *com; 1801{ 1802 u_char int_ctl; 1803 u_char int_ctl_new; 1804 u_char line_status; 1805 u_char modem_status; 1806 u_char *ioptr; 1807 u_char recv_data; 1808 1809 if (COM_IIR_TXRDYBUG(com->flags)) { 1810 int_ctl = inb(com->int_ctl_port); 1811 int_ctl_new = int_ctl; 1812 } else { 1813 int_ctl = 0; 1814 int_ctl_new = 0; 1815 } 1816 1817 while (!com->gone) { 1818 if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) { 1819 modem_status = inb(com->modem_status_port); 1820 if ((modem_status ^ com->last_modem_status) & 1821 com->pps_bit) { 1822 pps_capture(&com->pps); 1823 pps_event(&com->pps, 1824 (modem_status & com->pps_bit) ? 1825 PPS_CAPTUREASSERT : PPS_CAPTURECLEAR); 1826 } 1827 } 1828 line_status = inb(com->line_status_port); 1829 1830 /* input event? (check first to help avoid overruns) */ 1831 while (line_status & LSR_RCV_MASK) { 1832 /* break/unnattached error bits or real input? */ 1833 if (!(line_status & LSR_RXRDY)) 1834 recv_data = 0; 1835 else 1836 recv_data = inb(com->data_port); 1837#ifdef DDB 1838#ifdef ALT_BREAK_TO_DEBUGGER 1839 if (com->unit == comconsole && 1840 db_alt_break(recv_data, &com->alt_brk_state) != 0) 1841 breakpoint(); 1842#endif /* ALT_BREAK_TO_DEBUGGER */ 1843#endif /* DDB */ 1844 if (line_status & (LSR_BI | LSR_FE | LSR_PE)) { 1845 /* 1846 * Don't store BI if IGNBRK or FE/PE if IGNPAR. 1847 * Otherwise, push the work to a higher level 1848 * (to handle PARMRK) if we're bypassing. 1849 * Otherwise, convert BI/FE and PE+INPCK to 0. 1850 * 1851 * This makes bypassing work right in the 1852 * usual "raw" case (IGNBRK set, and IGNPAR 1853 * and INPCK clear). 1854 * 1855 * Note: BI together with FE/PE means just BI. 1856 */ 1857 if (line_status & LSR_BI) { 1858#if defined(DDB) && defined(BREAK_TO_DEBUGGER) 1859 if (com->unit == comconsole) { 1860 breakpoint(); 1861 goto cont; 1862 } 1863#endif 1864 if (com->tp == NULL 1865 || com->tp->t_iflag & IGNBRK) 1866 goto cont; 1867 } else { 1868 if (com->tp == NULL 1869 || com->tp->t_iflag & IGNPAR) 1870 goto cont; 1871 } 1872 if (com->tp->t_state & TS_CAN_BYPASS_L_RINT 1873 && (line_status & (LSR_BI | LSR_FE) 1874 || com->tp->t_iflag & INPCK)) 1875 recv_data = 0; 1876 } 1877 ++com->bytes_in; 1878 if (com->tp != NULL && 1879 com->tp->t_hotchar != 0 && recv_data == com->tp->t_hotchar) 1880 swi_sched(sio_fast_ih, 0); 1881 ioptr = com->iptr; 1882 if (ioptr >= com->ibufend) 1883 CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW); 1884 else { 1885 if (com->do_timestamp) 1886 microtime(&com->timestamp); 1887 ++com_events; 1888 swi_sched(sio_slow_ih, SWI_DELAY); 1889#if 0 /* for testing input latency vs efficiency */ 1890if (com->iptr - com->ibuf == 8) 1891 swi_sched(sio_fast_ih, 0); 1892#endif 1893 ioptr[0] = recv_data; 1894 ioptr[com->ierroff] = line_status; 1895 com->iptr = ++ioptr; 1896 if (ioptr == com->ihighwater 1897 && com->state & CS_RTS_IFLOW) 1898 outb(com->modem_ctl_port, 1899 com->mcr_image &= ~MCR_RTS); 1900 if (line_status & LSR_OE) 1901 CE_RECORD(com, CE_OVERRUN); 1902 } 1903cont: 1904 if (line_status & LSR_TXRDY 1905 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) 1906 goto txrdy; 1907 1908 /* 1909 * "& 0x7F" is to avoid the gcc-1.40 generating a slow 1910 * jump from the top of the loop to here 1911 */ 1912 line_status = inb(com->line_status_port) & 0x7F; 1913 } 1914 1915 /* modem status change? (always check before doing output) */ 1916 modem_status = inb(com->modem_status_port); 1917 if (modem_status != com->last_modem_status) { 1918 /* 1919 * Schedule high level to handle DCD changes. Note 1920 * that we don't use the delta bits anywhere. Some 1921 * UARTs mess them up, and it's easy to remember the 1922 * previous bits and calculate the delta. 1923 */ 1924 com->last_modem_status = modem_status; 1925 if (!(com->state & CS_CHECKMSR)) { 1926 com_events += LOTS_OF_EVENTS; 1927 com->state |= CS_CHECKMSR; 1928 swi_sched(sio_fast_ih, 0); 1929 } 1930 1931 /* handle CTS change immediately for crisp flow ctl */ 1932 if (com->state & CS_CTS_OFLOW) { 1933 if (modem_status & MSR_CTS) 1934 com->state |= CS_ODEVREADY; 1935 else 1936 com->state &= ~CS_ODEVREADY; 1937 } 1938 } 1939 1940txrdy: 1941 /* output queued and everything ready? */ 1942 if (line_status & LSR_TXRDY 1943 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) { 1944 ioptr = com->obufq.l_head; 1945 if (com->tx_fifo_size > 1 && com->unit != siotsunit) { 1946 u_int ocount; 1947 1948 ocount = com->obufq.l_tail - ioptr; 1949 if (ocount > com->tx_fifo_size) 1950 ocount = com->tx_fifo_size; 1951 com->bytes_out += ocount; 1952 do 1953 outb(com->data_port, *ioptr++); 1954 while (--ocount != 0); 1955 } else { 1956 outb(com->data_port, *ioptr++); 1957 ++com->bytes_out; 1958 if (com->unit == siotsunit 1959 && siotso < sizeof siots / sizeof siots[0]) 1960 nanouptime(&siots[siotso++]); 1961 } 1962 com->obufq.l_head = ioptr; 1963 if (COM_IIR_TXRDYBUG(com->flags)) 1964 int_ctl_new = int_ctl | IER_ETXRDY; 1965 if (ioptr >= com->obufq.l_tail) { 1966 struct lbq *qp; 1967 1968 qp = com->obufq.l_next; 1969 qp->l_queued = FALSE; 1970 qp = qp->l_next; 1971 if (qp != NULL) { 1972 com->obufq.l_head = qp->l_head; 1973 com->obufq.l_tail = qp->l_tail; 1974 com->obufq.l_next = qp; 1975 } else { 1976 /* output just completed */ 1977 if (COM_IIR_TXRDYBUG(com->flags)) 1978 int_ctl_new = int_ctl 1979 & ~IER_ETXRDY; 1980 com->state &= ~CS_BUSY; 1981 } 1982 if (!(com->state & CS_ODONE)) { 1983 com_events += LOTS_OF_EVENTS; 1984 com->state |= CS_ODONE; 1985 /* handle at high level ASAP */ 1986 swi_sched(sio_fast_ih, 0); 1987 } 1988 } 1989 if (COM_IIR_TXRDYBUG(com->flags) 1990 && int_ctl != int_ctl_new) 1991 outb(com->int_ctl_port, int_ctl_new); 1992 } 1993 1994 /* finished? */ 1995#ifndef COM_MULTIPORT 1996 if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND) 1997#endif /* COM_MULTIPORT */ 1998 return; 1999 } 2000} 2001 2002static int 2003siocioctl(dev, cmd, data, flag, td) 2004 struct cdev *dev; 2005 u_long cmd; 2006 caddr_t data; 2007 int flag; 2008 struct thread *td; 2009{ 2010 struct com_s *com; 2011 int error; 2012 int mynor; 2013 struct termios *ct; 2014 2015 mynor = minor(dev); 2016 com = com_addr(MINOR_TO_UNIT(mynor)); 2017 if (com == NULL || com->gone) 2018 return (ENODEV); 2019 2020 switch (mynor & CONTROL_MASK) { 2021 case CONTROL_INIT_STATE: 2022 ct = mynor & CALLOUT_MASK ? &com->it_out : &com->it_in; 2023 break; 2024 case CONTROL_LOCK_STATE: 2025 ct = mynor & CALLOUT_MASK ? &com->lt_out : &com->lt_in; 2026 break; 2027 default: 2028 return (ENODEV); /* /dev/nodev */ 2029 } 2030 switch (cmd) { 2031 case TIOCSETA: 2032 error = suser(td); 2033 if (error != 0) 2034 return (error); 2035 *ct = *(struct termios *)data; 2036 return (0); 2037 case TIOCGETA: 2038 *(struct termios *)data = *ct; 2039 return (0); 2040 case TIOCGETD: 2041 *(int *)data = TTYDISC; 2042 return (0); 2043 case TIOCGWINSZ: 2044 bzero(data, sizeof(struct winsize)); 2045 return (0); 2046 default: 2047 return (ENOTTY); 2048 } 2049} 2050 2051static int 2052sioioctl(dev, cmd, data, flag, td) 2053 struct cdev *dev; 2054 u_long cmd; 2055 caddr_t data; 2056 int flag; 2057 struct thread *td; 2058{ 2059 struct com_s *com; 2060 int error; 2061 int mynor; 2062 int s; 2063 struct tty *tp; 2064#ifndef BURN_BRIDGES 2065#if defined(COMPAT_43) 2066 u_long oldcmd; 2067 struct termios term; 2068#endif 2069#endif 2070 2071 mynor = minor(dev); 2072 com = dev->si_drv1; 2073 if (com == NULL || com->gone) 2074 return (ENODEV); 2075 tp = com->tp; 2076#ifndef BURN_BRIDGES 2077#if defined(COMPAT_43) 2078 term = tp->t_termios; 2079 oldcmd = cmd; 2080 error = ttsetcompat(tp, &cmd, data, &term); 2081 if (error != 0) 2082 return (error); 2083 if (cmd != oldcmd) 2084 data = (caddr_t)&term; 2085#endif 2086#endif 2087 if (cmd == TIOCSETA || cmd == TIOCSETAW || cmd == TIOCSETAF) { 2088 int cc; 2089 struct termios *dt = (struct termios *)data; 2090 struct termios *lt = mynor & CALLOUT_MASK 2091 ? &com->lt_out : &com->lt_in; 2092 2093 dt->c_iflag = (tp->t_iflag & lt->c_iflag) 2094 | (dt->c_iflag & ~lt->c_iflag); 2095 dt->c_oflag = (tp->t_oflag & lt->c_oflag) 2096 | (dt->c_oflag & ~lt->c_oflag); 2097 dt->c_cflag = (tp->t_cflag & lt->c_cflag) 2098 | (dt->c_cflag & ~lt->c_cflag); 2099 dt->c_lflag = (tp->t_lflag & lt->c_lflag) 2100 | (dt->c_lflag & ~lt->c_lflag); 2101 for (cc = 0; cc < NCCS; ++cc) 2102 if (lt->c_cc[cc] != 0) 2103 dt->c_cc[cc] = tp->t_cc[cc]; 2104 if (lt->c_ispeed != 0) 2105 dt->c_ispeed = tp->t_ispeed; 2106 if (lt->c_ospeed != 0) 2107 dt->c_ospeed = tp->t_ospeed; 2108 } 2109 error = ttyioctl(dev, cmd, data, flag, td); 2110 ttyldoptim(tp); 2111 if (error != ENOTTY) 2112 return (error); 2113 s = spltty(); 2114 switch (cmd) { 2115 case TIOCMSDTRWAIT: 2116 /* must be root since the wait applies to following logins */ 2117 error = suser(td); 2118 if (error != 0) { 2119 splx(s); 2120 return (error); 2121 } 2122 com->dtr_wait = *(int *)data * hz / 100; 2123 break; 2124 case TIOCMGDTRWAIT: 2125 *(int *)data = com->dtr_wait * 100 / hz; 2126 break; 2127 case TIOCTIMESTAMP: 2128 com->do_timestamp = TRUE; 2129 *(struct timeval *)data = com->timestamp; 2130 break; 2131 default: 2132 splx(s); 2133 error = pps_ioctl(cmd, data, &com->pps); 2134 if (error == ENODEV) 2135 error = ENOTTY; 2136 return (error); 2137 } 2138 splx(s); 2139 return (0); 2140} 2141 2142/* software interrupt handler for SWI_TTY */ 2143static void 2144siopoll(void *dummy) 2145{ 2146 int unit; 2147 2148 if (com_events == 0) 2149 return; 2150repeat: 2151 for (unit = 0; unit < sio_numunits; ++unit) { 2152 struct com_s *com; 2153 int incc; 2154 struct tty *tp; 2155 2156 com = com_addr(unit); 2157 if (com == NULL) 2158 continue; 2159 tp = com->tp; 2160 if (tp == NULL || com->gone) { 2161 /* 2162 * Discard any events related to never-opened or 2163 * going-away devices. 2164 */ 2165 mtx_lock_spin(&sio_lock); 2166 incc = com->iptr - com->ibuf; 2167 com->iptr = com->ibuf; 2168 if (com->state & CS_CHECKMSR) { 2169 incc += LOTS_OF_EVENTS; 2170 com->state &= ~CS_CHECKMSR; 2171 } 2172 com_events -= incc; 2173 mtx_unlock_spin(&sio_lock); 2174 continue; 2175 } 2176 if (com->iptr != com->ibuf) { 2177 mtx_lock_spin(&sio_lock); 2178 sioinput(com); 2179 mtx_unlock_spin(&sio_lock); 2180 } 2181 if (com->state & CS_CHECKMSR) { 2182 u_char delta_modem_status; 2183 2184 mtx_lock_spin(&sio_lock); 2185 delta_modem_status = com->last_modem_status 2186 ^ com->prev_modem_status; 2187 com->prev_modem_status = com->last_modem_status; 2188 com_events -= LOTS_OF_EVENTS; 2189 com->state &= ~CS_CHECKMSR; 2190 mtx_unlock_spin(&sio_lock); 2191 if (delta_modem_status & MSR_DCD) 2192 ttyld_modem(tp, 2193 com->prev_modem_status & MSR_DCD); 2194 } 2195 if (com->state & CS_ODONE) { 2196 mtx_lock_spin(&sio_lock); 2197 com_events -= LOTS_OF_EVENTS; 2198 com->state &= ~CS_ODONE; 2199 mtx_unlock_spin(&sio_lock); 2200 if (!(com->state & CS_BUSY) 2201 && !(com->extra_state & CSE_BUSYCHECK)) { 2202 timeout(siobusycheck, com, hz / 100); 2203 com->extra_state |= CSE_BUSYCHECK; 2204 } 2205 ttyld_start(tp); 2206 } 2207 if (com_events == 0) 2208 break; 2209 } 2210 if (com_events >= LOTS_OF_EVENTS) 2211 goto repeat; 2212} 2213 2214static void 2215combreak(tp, sig) 2216 struct tty *tp; 2217 int sig; 2218{ 2219 struct com_s *com; 2220 2221 com = tp->t_dev->si_drv1; 2222 2223 if (sig) 2224 sio_setreg(com, com_cfcr, com->cfcr_image |= CFCR_SBREAK); 2225 else 2226 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 2227} 2228 2229static int 2230comparam(tp, t) 2231 struct tty *tp; 2232 struct termios *t; 2233{ 2234 u_int cfcr; 2235 int cflag; 2236 struct com_s *com; 2237 u_int divisor; 2238 u_char dlbh; 2239 u_char dlbl; 2240 u_char efr_flowbits; 2241 int s; 2242 int unit; 2243 2244 unit = DEV_TO_UNIT(tp->t_dev); 2245 com = com_addr(unit); 2246 if (com == NULL) 2247 return (ENODEV); 2248 2249 /* check requested parameters */ 2250 if (t->c_ispeed != (t->c_ospeed != 0 ? t->c_ospeed : tp->t_ospeed)) 2251 return (EINVAL); 2252 divisor = siodivisor(com->rclk, t->c_ispeed); 2253 if (divisor == 0) 2254 return (EINVAL); 2255 2256 /* parameters are OK, convert them to the com struct and the device */ 2257 s = spltty(); 2258 if (t->c_ospeed == 0) 2259 (void)commodem(tp, 0, SER_DTR); /* hang up line */ 2260 else 2261 (void)commodem(tp, SER_DTR, 0); 2262 cflag = t->c_cflag; 2263 switch (cflag & CSIZE) { 2264 case CS5: 2265 cfcr = CFCR_5BITS; 2266 break; 2267 case CS6: 2268 cfcr = CFCR_6BITS; 2269 break; 2270 case CS7: 2271 cfcr = CFCR_7BITS; 2272 break; 2273 default: 2274 cfcr = CFCR_8BITS; 2275 break; 2276 } 2277 if (cflag & PARENB) { 2278 cfcr |= CFCR_PENAB; 2279 if (!(cflag & PARODD)) 2280 cfcr |= CFCR_PEVEN; 2281 } 2282 if (cflag & CSTOPB) 2283 cfcr |= CFCR_STOPB; 2284 2285 if (com->hasfifo) { 2286 /* 2287 * Use a fifo trigger level low enough so that the input 2288 * latency from the fifo is less than about 16 msec and 2289 * the total latency is less than about 30 msec. These 2290 * latencies are reasonable for humans. Serial comms 2291 * protocols shouldn't expect anything better since modem 2292 * latencies are larger. 2293 * 2294 * The fifo trigger level cannot be set at RX_HIGH for high 2295 * speed connections without further work on reducing 2296 * interrupt disablement times in other parts of the system, 2297 * without producing silo overflow errors. 2298 */ 2299 com->fifo_image = com->unit == siotsunit ? 0 2300 : t->c_ispeed <= 4800 2301 ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_MEDH; 2302#ifdef COM_ESP 2303 /* 2304 * The Hayes ESP card needs the fifo DMA mode bit set 2305 * in compatibility mode. If not, it will interrupt 2306 * for each character received. 2307 */ 2308 if (com->esp) 2309 com->fifo_image |= FIFO_DMA_MODE; 2310#endif 2311 sio_setreg(com, com_fifo, com->fifo_image); 2312 } 2313 2314 /* 2315 * This returns with interrupts disabled so that we can complete 2316 * the speed change atomically. Keeping interrupts disabled is 2317 * especially important while com_data is hidden. 2318 */ 2319 (void) siosetwater(com, t->c_ispeed); 2320 2321 sio_setreg(com, com_cfcr, cfcr | CFCR_DLAB); 2322 /* 2323 * Only set the divisor registers if they would change, since on 2324 * some 16550 incompatibles (UMC8669F), setting them while input 2325 * is arriving loses sync until data stops arriving. 2326 */ 2327 dlbl = divisor & 0xFF; 2328 if (sio_getreg(com, com_dlbl) != dlbl) 2329 sio_setreg(com, com_dlbl, dlbl); 2330 dlbh = divisor >> 8; 2331 if (sio_getreg(com, com_dlbh) != dlbh) 2332 sio_setreg(com, com_dlbh, dlbh); 2333 2334 efr_flowbits = 0; 2335 2336 if (cflag & CRTS_IFLOW) { 2337 com->state |= CS_RTS_IFLOW; 2338 efr_flowbits |= EFR_AUTORTS; 2339 /* 2340 * If CS_RTS_IFLOW just changed from off to on, the change 2341 * needs to be propagated to MCR_RTS. This isn't urgent, 2342 * so do it later by calling comstart() instead of repeating 2343 * a lot of code from comstart() here. 2344 */ 2345 } else if (com->state & CS_RTS_IFLOW) { 2346 com->state &= ~CS_RTS_IFLOW; 2347 /* 2348 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS 2349 * on here, since comstart() won't do it later. 2350 */ 2351 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2352 } 2353 2354 /* 2355 * Set up state to handle output flow control. 2356 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level? 2357 * Now has 10+ msec latency, while CTS flow has 50- usec latency. 2358 */ 2359 com->state |= CS_ODEVREADY; 2360 com->state &= ~CS_CTS_OFLOW; 2361 if (cflag & CCTS_OFLOW) { 2362 com->state |= CS_CTS_OFLOW; 2363 efr_flowbits |= EFR_AUTOCTS; 2364 if (!(com->last_modem_status & MSR_CTS)) 2365 com->state &= ~CS_ODEVREADY; 2366 } 2367 2368 if (com->st16650a) { 2369 sio_setreg(com, com_lcr, LCR_EFR_ENABLE); 2370 sio_setreg(com, com_efr, 2371 (sio_getreg(com, com_efr) 2372 & ~(EFR_AUTOCTS | EFR_AUTORTS)) | efr_flowbits); 2373 } 2374 sio_setreg(com, com_cfcr, com->cfcr_image = cfcr); 2375 2376 /* XXX shouldn't call functions while intrs are disabled. */ 2377 ttyldoptim(tp); 2378 2379 mtx_unlock_spin(&sio_lock); 2380 splx(s); 2381 comstart(tp); 2382 if (com->ibufold != NULL) { 2383 free(com->ibufold, M_DEVBUF); 2384 com->ibufold = NULL; 2385 } 2386 return (0); 2387} 2388 2389/* 2390 * This function must be called with the sio_lock mutex released and will 2391 * return with it obtained. 2392 */ 2393static int 2394siosetwater(com, speed) 2395 struct com_s *com; 2396 speed_t speed; 2397{ 2398 int cp4ticks; 2399 u_char *ibuf; 2400 int ibufsize; 2401 struct tty *tp; 2402 2403 /* 2404 * Make the buffer size large enough to handle a softtty interrupt 2405 * latency of about 2 ticks without loss of throughput or data 2406 * (about 3 ticks if input flow control is not used or not honoured, 2407 * but a bit less for CS5-CS7 modes). 2408 */ 2409 cp4ticks = speed / 10 / hz * 4; 2410 for (ibufsize = 128; ibufsize < cp4ticks;) 2411 ibufsize <<= 1; 2412 if (ibufsize == com->ibufsize) { 2413 mtx_lock_spin(&sio_lock); 2414 return (0); 2415 } 2416 2417 /* 2418 * Allocate input buffer. The extra factor of 2 in the size is 2419 * to allow for an error byte for each input byte. 2420 */ 2421 ibuf = malloc(2 * ibufsize, M_DEVBUF, M_NOWAIT); 2422 if (ibuf == NULL) { 2423 mtx_lock_spin(&sio_lock); 2424 return (ENOMEM); 2425 } 2426 2427 /* Initialize non-critical variables. */ 2428 com->ibufold = com->ibuf; 2429 com->ibufsize = ibufsize; 2430 tp = com->tp; 2431 if (tp != NULL) { 2432 tp->t_ififosize = 2 * ibufsize; 2433 tp->t_ispeedwat = (speed_t)-1; 2434 tp->t_ospeedwat = (speed_t)-1; 2435 } 2436 2437 /* 2438 * Read current input buffer, if any. Continue with interrupts 2439 * disabled. 2440 */ 2441 mtx_lock_spin(&sio_lock); 2442 if (com->iptr != com->ibuf) 2443 sioinput(com); 2444 2445 /*- 2446 * Initialize critical variables, including input buffer watermarks. 2447 * The external device is asked to stop sending when the buffer 2448 * exactly reaches high water, or when the high level requests it. 2449 * The high level is notified immediately (rather than at a later 2450 * clock tick) when this watermark is reached. 2451 * The buffer size is chosen so the watermark should almost never 2452 * be reached. 2453 * The low watermark is invisibly 0 since the buffer is always 2454 * emptied all at once. 2455 */ 2456 com->iptr = com->ibuf = ibuf; 2457 com->ibufend = ibuf + ibufsize; 2458 com->ierroff = ibufsize; 2459 com->ihighwater = ibuf + 3 * ibufsize / 4; 2460 return (0); 2461} 2462 2463static void 2464comstart(tp) 2465 struct tty *tp; 2466{ 2467 struct com_s *com; 2468 int s; 2469 int unit; 2470 2471 unit = DEV_TO_UNIT(tp->t_dev); 2472 com = com_addr(unit); 2473 if (com == NULL) 2474 return; 2475 s = spltty(); 2476 mtx_lock_spin(&sio_lock); 2477 if (tp->t_state & TS_TTSTOP) 2478 com->state &= ~CS_TTGO; 2479 else 2480 com->state |= CS_TTGO; 2481 if (tp->t_state & TS_TBLOCK) { 2482 if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW) 2483 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS); 2484 } else { 2485 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater 2486 && com->state & CS_RTS_IFLOW) 2487 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2488 } 2489 mtx_unlock_spin(&sio_lock); 2490 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) { 2491 ttwwakeup(tp); 2492 splx(s); 2493 return; 2494 } 2495 if (tp->t_outq.c_cc != 0) { 2496 struct lbq *qp; 2497 struct lbq *next; 2498 2499 if (!com->obufs[0].l_queued) { 2500 com->obufs[0].l_tail 2501 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1, 2502 sizeof com->obuf1); 2503 com->obufs[0].l_next = NULL; 2504 com->obufs[0].l_queued = TRUE; 2505 mtx_lock_spin(&sio_lock); 2506 if (com->state & CS_BUSY) { 2507 qp = com->obufq.l_next; 2508 while ((next = qp->l_next) != NULL) 2509 qp = next; 2510 qp->l_next = &com->obufs[0]; 2511 } else { 2512 com->obufq.l_head = com->obufs[0].l_head; 2513 com->obufq.l_tail = com->obufs[0].l_tail; 2514 com->obufq.l_next = &com->obufs[0]; 2515 com->state |= CS_BUSY; 2516 } 2517 mtx_unlock_spin(&sio_lock); 2518 } 2519 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) { 2520 com->obufs[1].l_tail 2521 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2, 2522 sizeof com->obuf2); 2523 com->obufs[1].l_next = NULL; 2524 com->obufs[1].l_queued = TRUE; 2525 mtx_lock_spin(&sio_lock); 2526 if (com->state & CS_BUSY) { 2527 qp = com->obufq.l_next; 2528 while ((next = qp->l_next) != NULL) 2529 qp = next; 2530 qp->l_next = &com->obufs[1]; 2531 } else { 2532 com->obufq.l_head = com->obufs[1].l_head; 2533 com->obufq.l_tail = com->obufs[1].l_tail; 2534 com->obufq.l_next = &com->obufs[1]; 2535 com->state |= CS_BUSY; 2536 } 2537 mtx_unlock_spin(&sio_lock); 2538 } 2539 tp->t_state |= TS_BUSY; 2540 } 2541 mtx_lock_spin(&sio_lock); 2542 if (com->state >= (CS_BUSY | CS_TTGO)) 2543 siointr1(com); /* fake interrupt to start output */ 2544 mtx_unlock_spin(&sio_lock); 2545 ttwwakeup(tp); 2546 splx(s); 2547} 2548 2549static void 2550comstop(tp, rw) 2551 struct tty *tp; 2552 int rw; 2553{ 2554 struct com_s *com; 2555 2556 com = com_addr(DEV_TO_UNIT(tp->t_dev)); 2557 if (com == NULL || com->gone) 2558 return; 2559 mtx_lock_spin(&sio_lock); 2560 if (rw & FWRITE) { 2561 if (com->hasfifo) 2562#ifdef COM_ESP 2563 /* XXX avoid h/w bug. */ 2564 if (!com->esp) 2565#endif 2566 sio_setreg(com, com_fifo, 2567 FIFO_XMT_RST | com->fifo_image); 2568 com->obufs[0].l_queued = FALSE; 2569 com->obufs[1].l_queued = FALSE; 2570 if (com->state & CS_ODONE) 2571 com_events -= LOTS_OF_EVENTS; 2572 com->state &= ~(CS_ODONE | CS_BUSY); 2573 com->tp->t_state &= ~TS_BUSY; 2574 } 2575 if (rw & FREAD) { 2576 if (com->hasfifo) 2577#ifdef COM_ESP 2578 /* XXX avoid h/w bug. */ 2579 if (!com->esp) 2580#endif 2581 sio_setreg(com, com_fifo, 2582 FIFO_RCV_RST | com->fifo_image); 2583 com_events -= (com->iptr - com->ibuf); 2584 com->iptr = com->ibuf; 2585 } 2586 mtx_unlock_spin(&sio_lock); 2587 comstart(tp); 2588} 2589 2590static int 2591commodem(tp, sigon, sigoff) 2592 struct tty *tp; 2593 int sigon, sigoff; 2594{ 2595 struct com_s *com; 2596 int bitand, bitor, msr; 2597 2598 com = tp->t_dev->si_drv1; 2599 if (com->gone) 2600 return(0); 2601 if (sigon != 0 || sigoff != 0) { 2602 bitand = bitor = 0; 2603 if (sigoff & SER_DTR) 2604 bitand |= MCR_DTR; 2605 if (sigoff & SER_RTS) 2606 bitand |= MCR_RTS; 2607 if (sigon & SER_DTR) 2608 bitor |= MCR_DTR; 2609 if (sigon & SER_RTS) 2610 bitor |= MCR_RTS; 2611 bitand = ~bitand; 2612 mtx_lock_spin(&sio_lock); 2613 com->mcr_image &= bitand; 2614 com->mcr_image |= bitor; 2615 outb(com->modem_ctl_port, com->mcr_image); 2616 mtx_unlock_spin(&sio_lock); 2617 return (0); 2618 } else { 2619 bitor = 0; 2620 if (com->mcr_image & MCR_DTR) 2621 bitor |= SER_DTR; 2622 if (com->mcr_image & MCR_RTS) 2623 bitor |= SER_RTS; 2624 msr = com->prev_modem_status; 2625 if (msr & MSR_CTS) 2626 bitor |= SER_CTS; 2627 if (msr & MSR_DCD) 2628 bitor |= SER_DCD; 2629 if (msr & MSR_DSR) 2630 bitor |= SER_DSR; 2631 if (msr & MSR_DSR) 2632 bitor |= SER_DSR; 2633 if (msr & (MSR_RI | MSR_TERI)) 2634 bitor |= SER_RI; 2635 return (bitor); 2636 } 2637} 2638 2639static void 2640siosettimeout() 2641{ 2642 struct com_s *com; 2643 bool_t someopen; 2644 int unit; 2645 2646 /* 2647 * Set our timeout period to 1 second if no polled devices are open. 2648 * Otherwise set it to max(1/200, 1/hz). 2649 * Enable timeouts iff some device is open. 2650 */ 2651 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 2652 sio_timeout = hz; 2653 someopen = FALSE; 2654 for (unit = 0; unit < sio_numunits; ++unit) { 2655 com = com_addr(unit); 2656 if (com != NULL && com->tp != NULL 2657 && com->tp->t_state & TS_ISOPEN && !com->gone) { 2658 someopen = TRUE; 2659 if (com->poll || com->poll_output) { 2660 sio_timeout = hz > 200 ? hz / 200 : 1; 2661 break; 2662 } 2663 } 2664 } 2665 if (someopen) { 2666 sio_timeouts_until_log = hz / sio_timeout; 2667 sio_timeout_handle = timeout(comwakeup, (void *)NULL, 2668 sio_timeout); 2669 } else { 2670 /* Flush error messages, if any. */ 2671 sio_timeouts_until_log = 1; 2672 comwakeup((void *)NULL); 2673 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 2674 } 2675} 2676 2677static void 2678comwakeup(chan) 2679 void *chan; 2680{ 2681 struct com_s *com; 2682 int unit; 2683 2684 sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout); 2685 2686 /* 2687 * Recover from lost output interrupts. 2688 * Poll any lines that don't use interrupts. 2689 */ 2690 for (unit = 0; unit < sio_numunits; ++unit) { 2691 com = com_addr(unit); 2692 if (com != NULL && !com->gone 2693 && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) { 2694 mtx_lock_spin(&sio_lock); 2695 siointr1(com); 2696 mtx_unlock_spin(&sio_lock); 2697 } 2698 } 2699 2700 /* 2701 * Check for and log errors, but not too often. 2702 */ 2703 if (--sio_timeouts_until_log > 0) 2704 return; 2705 sio_timeouts_until_log = hz / sio_timeout; 2706 for (unit = 0; unit < sio_numunits; ++unit) { 2707 int errnum; 2708 2709 com = com_addr(unit); 2710 if (com == NULL) 2711 continue; 2712 if (com->gone) 2713 continue; 2714 for (errnum = 0; errnum < CE_NTYPES; ++errnum) { 2715 u_int delta; 2716 u_long total; 2717 2718 mtx_lock_spin(&sio_lock); 2719 delta = com->delta_error_counts[errnum]; 2720 com->delta_error_counts[errnum] = 0; 2721 mtx_unlock_spin(&sio_lock); 2722 if (delta == 0) 2723 continue; 2724 total = com->error_counts[errnum] += delta; 2725 log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n", 2726 unit, delta, error_desc[errnum], 2727 delta == 1 ? "" : "s", total); 2728 } 2729 } 2730} 2731 2732/* 2733 * Following are all routines needed for SIO to act as console 2734 */ 2735struct siocnstate { 2736 u_char dlbl; 2737 u_char dlbh; 2738 u_char ier; 2739 u_char cfcr; 2740 u_char mcr; 2741}; 2742 2743/* 2744 * This is a function in order to not replicate "ttyd%d" more 2745 * places than absolutely necessary. 2746 */ 2747static void 2748siocnset(struct consdev *cd, int unit) 2749{ 2750 2751 cd->cn_unit = unit; 2752 sprintf(cd->cn_name, "ttyd%d", unit); 2753} 2754 2755#ifndef __alpha__ 2756static speed_t siocngetspeed(Port_t, u_long rclk); 2757#endif 2758static void siocnclose(struct siocnstate *sp, Port_t iobase); 2759static void siocnopen(struct siocnstate *sp, Port_t iobase, int speed); 2760static void siocntxwait(Port_t iobase); 2761 2762#ifdef __alpha__ 2763int siocnattach(int port, int speed); 2764int siogdbattach(int port, int speed); 2765int siogdbgetc(void); 2766void siogdbputc(int c); 2767#else 2768static cn_probe_t siocnprobe; 2769static cn_init_t siocninit; 2770static cn_term_t siocnterm; 2771#endif 2772static cn_checkc_t siocncheckc; 2773static cn_getc_t siocngetc; 2774static cn_putc_t siocnputc; 2775 2776#ifndef __alpha__ 2777CONS_DRIVER(sio, siocnprobe, siocninit, siocnterm, siocngetc, siocncheckc, 2778 siocnputc, NULL); 2779#endif 2780 2781#if DDB > 0 2782static struct consdev gdbconsdev; 2783#endif 2784 2785static void 2786siocntxwait(iobase) 2787 Port_t iobase; 2788{ 2789 int timo; 2790 2791 /* 2792 * Wait for any pending transmission to finish. Required to avoid 2793 * the UART lockup bug when the speed is changed, and for normal 2794 * transmits. 2795 */ 2796 timo = 100000; 2797 while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY)) 2798 != (LSR_TSRE | LSR_TXRDY) && --timo != 0) 2799 ; 2800} 2801 2802#ifndef __alpha__ 2803 2804/* 2805 * Read the serial port specified and try to figure out what speed 2806 * it's currently running at. We're assuming the serial port has 2807 * been initialized and is basicly idle. This routine is only intended 2808 * to be run at system startup. 2809 * 2810 * If the value read from the serial port doesn't make sense, return 0. 2811 */ 2812 2813static speed_t 2814siocngetspeed(iobase, rclk) 2815 Port_t iobase; 2816 u_long rclk; 2817{ 2818 u_int divisor; 2819 u_char dlbh; 2820 u_char dlbl; 2821 u_char cfcr; 2822 2823 cfcr = inb(iobase + com_cfcr); 2824 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 2825 2826 dlbl = inb(iobase + com_dlbl); 2827 dlbh = inb(iobase + com_dlbh); 2828 2829 outb(iobase + com_cfcr, cfcr); 2830 2831 divisor = dlbh << 8 | dlbl; 2832 2833 /* XXX there should be more sanity checking. */ 2834 if (divisor == 0) 2835 return (CONSPEED); 2836 return (rclk / (16UL * divisor)); 2837} 2838 2839#endif 2840 2841static void 2842siocnopen(sp, iobase, speed) 2843 struct siocnstate *sp; 2844 Port_t iobase; 2845 int speed; 2846{ 2847 u_int divisor; 2848 u_char dlbh; 2849 u_char dlbl; 2850 2851 /* 2852 * Save all the device control registers except the fifo register 2853 * and set our default ones (cs8 -parenb speed=comdefaultrate). 2854 * We can't save the fifo register since it is read-only. 2855 */ 2856 sp->ier = inb(iobase + com_ier); 2857 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */ 2858 siocntxwait(iobase); 2859 sp->cfcr = inb(iobase + com_cfcr); 2860 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 2861 sp->dlbl = inb(iobase + com_dlbl); 2862 sp->dlbh = inb(iobase + com_dlbh); 2863 /* 2864 * Only set the divisor registers if they would change, since on 2865 * some 16550 incompatibles (Startech), setting them clears the 2866 * data input register. This also reduces the effects of the 2867 * UMC8669F bug. 2868 */ 2869 divisor = siodivisor(comdefaultrclk, speed); 2870 dlbl = divisor & 0xFF; 2871 if (sp->dlbl != dlbl) 2872 outb(iobase + com_dlbl, dlbl); 2873 dlbh = divisor >> 8; 2874 if (sp->dlbh != dlbh) 2875 outb(iobase + com_dlbh, dlbh); 2876 outb(iobase + com_cfcr, CFCR_8BITS); 2877 sp->mcr = inb(iobase + com_mcr); 2878 /* 2879 * We don't want interrupts, but must be careful not to "disable" 2880 * them by clearing the MCR_IENABLE bit, since that might cause 2881 * an interrupt by floating the IRQ line. 2882 */ 2883 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS); 2884} 2885 2886static void 2887siocnclose(sp, iobase) 2888 struct siocnstate *sp; 2889 Port_t iobase; 2890{ 2891 /* 2892 * Restore the device control registers. 2893 */ 2894 siocntxwait(iobase); 2895 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 2896 if (sp->dlbl != inb(iobase + com_dlbl)) 2897 outb(iobase + com_dlbl, sp->dlbl); 2898 if (sp->dlbh != inb(iobase + com_dlbh)) 2899 outb(iobase + com_dlbh, sp->dlbh); 2900 outb(iobase + com_cfcr, sp->cfcr); 2901 /* 2902 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them. 2903 */ 2904 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS); 2905 outb(iobase + com_ier, sp->ier); 2906} 2907 2908#ifndef __alpha__ 2909 2910static void 2911siocnprobe(cp) 2912 struct consdev *cp; 2913{ 2914 speed_t boot_speed; 2915 u_char cfcr; 2916 u_int divisor; 2917 int s, unit; 2918 struct siocnstate sp; 2919 2920 /* 2921 * Find our first enabled console, if any. If it is a high-level 2922 * console device, then initialize it and return successfully. 2923 * If it is a low-level console device, then initialize it and 2924 * return unsuccessfully. It must be initialized in both cases 2925 * for early use by console drivers and debuggers. Initializing 2926 * the hardware is not necessary in all cases, since the i/o 2927 * routines initialize it on the fly, but it is necessary if 2928 * input might arrive while the hardware is switched back to an 2929 * uninitialized state. We can't handle multiple console devices 2930 * yet because our low-level routines don't take a device arg. 2931 * We trust the user to set the console flags properly so that we 2932 * don't need to probe. 2933 */ 2934 cp->cn_pri = CN_DEAD; 2935 2936 for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */ 2937 int flags; 2938 2939 if (resource_disabled("sio", unit)) 2940 continue; 2941 if (resource_int_value("sio", unit, "flags", &flags)) 2942 continue; 2943 if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) { 2944 int port; 2945 Port_t iobase; 2946 2947 if (resource_int_value("sio", unit, "port", &port)) 2948 continue; 2949 iobase = port; 2950 s = spltty(); 2951 if (boothowto & RB_SERIAL) { 2952 boot_speed = 2953 siocngetspeed(iobase, comdefaultrclk); 2954 if (boot_speed) 2955 comdefaultrate = boot_speed; 2956 } 2957 2958 /* 2959 * Initialize the divisor latch. We can't rely on 2960 * siocnopen() to do this the first time, since it 2961 * avoids writing to the latch if the latch appears 2962 * to have the correct value. Also, if we didn't 2963 * just read the speed from the hardware, then we 2964 * need to set the speed in hardware so that 2965 * switching it later is null. 2966 */ 2967 cfcr = inb(iobase + com_cfcr); 2968 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 2969 divisor = siodivisor(comdefaultrclk, comdefaultrate); 2970 outb(iobase + com_dlbl, divisor & 0xff); 2971 outb(iobase + com_dlbh, divisor >> 8); 2972 outb(iobase + com_cfcr, cfcr); 2973 2974 siocnopen(&sp, iobase, comdefaultrate); 2975 2976 splx(s); 2977 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) { 2978 siocnset(cp, unit); 2979 cp->cn_pri = COM_FORCECONSOLE(flags) 2980 || boothowto & RB_SERIAL 2981 ? CN_REMOTE : CN_NORMAL; 2982 siocniobase = iobase; 2983 siocnunit = unit; 2984 } 2985 if (COM_DEBUGGER(flags)) { 2986 printf("sio%d: gdb debugging port\n", unit); 2987 siogdbiobase = iobase; 2988 siogdbunit = unit; 2989#if DDB > 0 2990 siocnset(&gdbconsdev, unit); 2991 gdb_arg = &gdbconsdev; 2992 gdb_getc = siocngetc; 2993 gdb_putc = siocnputc; 2994#endif 2995 } 2996 } 2997 } 2998#ifdef __i386__ 2999#if DDB > 0 3000 /* 3001 * XXX Ugly Compatability. 3002 * If no gdb port has been specified, set it to be the console 3003 * as some configuration files don't specify the gdb port. 3004 */ 3005 if (gdb_arg == NULL && (boothowto & RB_GDB)) { 3006 printf("Warning: no GDB port specified. Defaulting to sio%d.\n", 3007 siocnunit); 3008 printf("Set flag 0x80 on desired GDB port in your\n"); 3009 printf("configuration file (currently sio only).\n"); 3010 siogdbiobase = siocniobase; 3011 siogdbunit = siocnunit; 3012 siocnset(&gdbconsdev, siocnunit); 3013 gdb_arg = &gdbconsdev; 3014 gdb_getc = siocngetc; 3015 gdb_putc = siocnputc; 3016 } 3017#endif 3018#endif 3019} 3020 3021static void 3022siocninit(cp) 3023 struct consdev *cp; 3024{ 3025 comconsole = cp->cn_unit; 3026} 3027 3028static void 3029siocnterm(cp) 3030 struct consdev *cp; 3031{ 3032 comconsole = -1; 3033} 3034 3035#endif 3036 3037#ifdef __alpha__ 3038 3039CONS_DRIVER(sio, NULL, NULL, NULL, siocngetc, siocncheckc, siocnputc, NULL); 3040 3041int 3042siocnattach(port, speed) 3043 int port; 3044 int speed; 3045{ 3046 int s; 3047 u_char cfcr; 3048 u_int divisor; 3049 struct siocnstate sp; 3050 int unit = 0; /* XXX random value! */ 3051 3052 siocniobase = port; 3053 siocnunit = unit; 3054 comdefaultrate = speed; 3055 sio_consdev.cn_pri = CN_NORMAL; 3056 siocnset(&sio_consdev, unit); 3057 3058 s = spltty(); 3059 3060 /* 3061 * Initialize the divisor latch. We can't rely on 3062 * siocnopen() to do this the first time, since it 3063 * avoids writing to the latch if the latch appears 3064 * to have the correct value. Also, if we didn't 3065 * just read the speed from the hardware, then we 3066 * need to set the speed in hardware so that 3067 * switching it later is null. 3068 */ 3069 cfcr = inb(siocniobase + com_cfcr); 3070 outb(siocniobase + com_cfcr, CFCR_DLAB | cfcr); 3071 divisor = siodivisor(comdefaultrclk, comdefaultrate); 3072 outb(siocniobase + com_dlbl, divisor & 0xff); 3073 outb(siocniobase + com_dlbh, divisor >> 8); 3074 outb(siocniobase + com_cfcr, cfcr); 3075 3076 siocnopen(&sp, siocniobase, comdefaultrate); 3077 splx(s); 3078 3079 cnadd(&sio_consdev); 3080 return (0); 3081} 3082 3083int 3084siogdbattach(port, speed) 3085 int port; 3086 int speed; 3087{ 3088 int s; 3089 u_char cfcr; 3090 u_int divisor; 3091 struct siocnstate sp; 3092 int unit = 1; /* XXX random value! */ 3093 3094 siogdbiobase = port; 3095 gdbdefaultrate = speed; 3096 3097 printf("sio%d: gdb debugging port\n", unit); 3098 siogdbunit = unit; 3099#if DDB > 0 3100 siocnset(&gdbconsdev, unit); 3101 gdb_arg = &gdbconsdev; 3102 gdb_getc = siocngetc; 3103 gdb_putc = siocnputc; 3104#endif 3105 3106 s = spltty(); 3107 3108 /* 3109 * Initialize the divisor latch. We can't rely on 3110 * siocnopen() to do this the first time, since it 3111 * avoids writing to the latch if the latch appears 3112 * to have the correct value. Also, if we didn't 3113 * just read the speed from the hardware, then we 3114 * need to set the speed in hardware so that 3115 * switching it later is null. 3116 */ 3117 cfcr = inb(siogdbiobase + com_cfcr); 3118 outb(siogdbiobase + com_cfcr, CFCR_DLAB | cfcr); 3119 divisor = siodivisor(comdefaultrclk, gdbdefaultrate); 3120 outb(siogdbiobase + com_dlbl, divisor & 0xff); 3121 outb(siogdbiobase + com_dlbh, divisor >> 8); 3122 outb(siogdbiobase + com_cfcr, cfcr); 3123 3124 siocnopen(&sp, siogdbiobase, gdbdefaultrate); 3125 splx(s); 3126 3127 return (0); 3128} 3129 3130#endif 3131 3132static int 3133siocncheckc(struct consdev *cd) 3134{ 3135 int c; 3136 Port_t iobase; 3137 int s; 3138 struct siocnstate sp; 3139 speed_t speed; 3140 3141 if (cd->cn_unit == siocnunit) { 3142 iobase = siocniobase; 3143 speed = comdefaultrate; 3144 } else { 3145 iobase = siogdbiobase; 3146 speed = gdbdefaultrate; 3147 } 3148 s = spltty(); 3149 siocnopen(&sp, iobase, speed); 3150 if (inb(iobase + com_lsr) & LSR_RXRDY) 3151 c = inb(iobase + com_data); 3152 else 3153 c = -1; 3154 siocnclose(&sp, iobase); 3155 splx(s); 3156 return (c); 3157} 3158 3159static int 3160siocngetc(struct consdev *cd) 3161{ 3162 int c; 3163 Port_t iobase; 3164 int s; 3165 struct siocnstate sp; 3166 speed_t speed; 3167 3168 if (cd->cn_unit == siocnunit) { 3169 iobase = siocniobase; 3170 speed = comdefaultrate; 3171 } else { 3172 iobase = siogdbiobase; 3173 speed = gdbdefaultrate; 3174 } 3175 s = spltty(); 3176 siocnopen(&sp, iobase, speed); 3177 while (!(inb(iobase + com_lsr) & LSR_RXRDY)) 3178 ; 3179 c = inb(iobase + com_data); 3180 siocnclose(&sp, iobase); 3181 splx(s); 3182 return (c); 3183} 3184 3185static void 3186siocnputc(struct consdev *cd, int c) 3187{ 3188 int need_unlock; 3189 int s; 3190 struct siocnstate sp; 3191 Port_t iobase; 3192 speed_t speed; 3193 3194 if (cd->cn_unit == siocnunit) { 3195 iobase = siocniobase; 3196 speed = comdefaultrate; 3197 } else { 3198 iobase = siogdbiobase; 3199 speed = gdbdefaultrate; 3200 } 3201 s = spltty(); 3202 need_unlock = 0; 3203 if (sio_inited == 2 && !mtx_owned(&sio_lock)) { 3204 mtx_lock_spin(&sio_lock); 3205 need_unlock = 1; 3206 } 3207 siocnopen(&sp, iobase, speed); 3208 siocntxwait(iobase); 3209 outb(iobase + com_data, c); 3210 siocnclose(&sp, iobase); 3211 if (need_unlock) 3212 mtx_unlock_spin(&sio_lock); 3213 splx(s); 3214} 3215 3216#ifdef __alpha__ 3217int 3218siogdbgetc() 3219{ 3220 int c; 3221 Port_t iobase; 3222 speed_t speed; 3223 int s; 3224 struct siocnstate sp; 3225 3226 if (siogdbunit == siocnunit) { 3227 iobase = siocniobase; 3228 speed = comdefaultrate; 3229 } else { 3230 iobase = siogdbiobase; 3231 speed = gdbdefaultrate; 3232 } 3233 3234 s = spltty(); 3235 siocnopen(&sp, iobase, speed); 3236 while (!(inb(iobase + com_lsr) & LSR_RXRDY)) 3237 ; 3238 c = inb(iobase + com_data); 3239 siocnclose(&sp, iobase); 3240 splx(s); 3241 return (c); 3242} 3243 3244void 3245siogdbputc(c) 3246 int c; 3247{ 3248 Port_t iobase; 3249 speed_t speed; 3250 int s; 3251 struct siocnstate sp; 3252 3253 if (siogdbunit == siocnunit) { 3254 iobase = siocniobase; 3255 speed = comdefaultrate; 3256 } else { 3257 iobase = siogdbiobase; 3258 speed = gdbdefaultrate; 3259 } 3260 3261 s = spltty(); 3262 siocnopen(&sp, iobase, speed); 3263 siocntxwait(siogdbiobase); 3264 outb(siogdbiobase + com_data, c); 3265 siocnclose(&sp, siogdbiobase); 3266 splx(s); 3267} 3268#endif 3269