sio.c revision 130872
1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 4. Neither the name of the University nor the names of its contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: @(#)com.c 7.5 (Berkeley) 5/16/91 30 * from: i386/isa sio.c,v 1.234 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/sio/sio.c 130872 2004-06-21 20:09:23Z phk $"); 35 36#include "opt_comconsole.h" 37#include "opt_compat.h" 38#include "opt_ddb.h" 39#include "opt_sio.h" 40 41/* 42 * Serial driver, based on 386BSD-0.1 com driver. 43 * Mostly rewritten to use pseudo-DMA. 44 * Works for National Semiconductor NS8250-NS16550AF UARTs. 45 * COM driver, based on HP dca driver. 46 * 47 * Changes for PC-Card integration: 48 * - Added PC-Card driver table and handlers 49 */ 50#include <sys/param.h> 51#include <sys/systm.h> 52#include <sys/bus.h> 53#include <sys/conf.h> 54#include <sys/fcntl.h> 55#include <sys/interrupt.h> 56#include <sys/kernel.h> 57#include <sys/limits.h> 58#include <sys/lock.h> 59#include <sys/malloc.h> 60#include <sys/module.h> 61#include <sys/mutex.h> 62#include <sys/proc.h> 63#include <sys/reboot.h> 64#include <sys/sysctl.h> 65#include <sys/syslog.h> 66#include <sys/tty.h> 67#include <machine/bus_pio.h> 68#include <machine/bus.h> 69#include <sys/rman.h> 70#include <sys/timepps.h> 71#include <sys/uio.h> 72#include <sys/cons.h> 73#if DDB > 0 74#include <ddb/ddb.h> 75#endif 76 77#include <isa/isavar.h> 78 79#include <machine/resource.h> 80 81#include <dev/sio/sioreg.h> 82#include <dev/sio/siovar.h> 83 84#ifdef COM_ESP 85#include <dev/ic/esp.h> 86#endif 87#include <dev/ic/ns16550.h> 88 89#define LOTS_OF_EVENTS 64 /* helps separate urgent events from input */ 90 91#define CALLOUT_MASK 0x80 92#define CONTROL_MASK 0x60 93#define CONTROL_INIT_STATE 0x20 94#define CONTROL_LOCK_STATE 0x40 95#define DEV_TO_UNIT(dev) (MINOR_TO_UNIT(minor(dev))) 96#define MINOR_TO_UNIT(mynor) ((((mynor) & ~0xffffU) >> (8 + 3)) \ 97 | ((mynor) & 0x1f)) 98#define UNIT_TO_MINOR(unit) ((((unit) & ~0x1fU) << (8 + 3)) \ 99 | ((unit) & 0x1f)) 100 101#ifdef COM_MULTIPORT 102/* checks in flags for multiport and which is multiport "master chip" 103 * for a given card 104 */ 105#define COM_ISMULTIPORT(flags) ((flags) & 0x01) 106#define COM_MPMASTER(flags) (((flags) >> 8) & 0x0ff) 107#define COM_NOTAST4(flags) ((flags) & 0x04) 108#else 109#define COM_ISMULTIPORT(flags) (0) 110#endif /* COM_MULTIPORT */ 111 112#define COM_C_IIR_TXRDYBUG 0x80000 113#define COM_CONSOLE(flags) ((flags) & 0x10) 114#define COM_DEBUGGER(flags) ((flags) & 0x80) 115#define COM_FIFOSIZE(flags) (((flags) & 0xff000000) >> 24) 116#define COM_FORCECONSOLE(flags) ((flags) & 0x20) 117#define COM_IIR_TXRDYBUG(flags) ((flags) & COM_C_IIR_TXRDYBUG) 118#define COM_LLCONSOLE(flags) ((flags) & 0x40) 119#define COM_LOSESOUTINTS(flags) ((flags) & 0x08) 120#define COM_NOFIFO(flags) ((flags) & 0x02) 121#define COM_NOPROBE(flags) ((flags) & 0x40000) 122#define COM_NOSCR(flags) ((flags) & 0x100000) 123#define COM_PPSCTS(flags) ((flags) & 0x10000) 124#define COM_ST16650A(flags) ((flags) & 0x20000) 125#define COM_TI16754(flags) ((flags) & 0x200000) 126 127#define sio_getreg(com, off) \ 128 (bus_space_read_1((com)->bst, (com)->bsh, (off))) 129#define sio_setreg(com, off, value) \ 130 (bus_space_write_1((com)->bst, (com)->bsh, (off), (value))) 131 132/* 133 * com state bits. 134 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher 135 * than the other bits so that they can be tested as a group without masking 136 * off the low bits. 137 * 138 * The following com and tty flags correspond closely: 139 * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and 140 * comstop()) 141 * CS_TTGO = ~TS_TTSTOP (maintained by comparam() and comstart()) 142 * CS_CTS_OFLOW = CCTS_OFLOW (maintained by comparam()) 143 * CS_RTS_IFLOW = CRTS_IFLOW (maintained by comparam()) 144 * TS_FLUSH is not used. 145 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON. 146 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state). 147 */ 148#define CS_BUSY 0x80 /* output in progress */ 149#define CS_TTGO 0x40 /* output not stopped by XOFF */ 150#define CS_ODEVREADY 0x20 /* external device h/w ready (CTS) */ 151#define CS_CHECKMSR 1 /* check of MSR scheduled */ 152#define CS_CTS_OFLOW 2 /* use CTS output flow control */ 153#define CS_DTR_OFF 0x10 /* DTR held off */ 154#define CS_ODONE 4 /* output completed */ 155#define CS_RTS_IFLOW 8 /* use RTS input flow control */ 156#define CSE_BUSYCHECK 1 /* siobusycheck() scheduled */ 157 158static char const * const error_desc[] = { 159#define CE_OVERRUN 0 160 "silo overflow", 161#define CE_INTERRUPT_BUF_OVERFLOW 1 162 "interrupt-level buffer overflow", 163#define CE_TTY_BUF_OVERFLOW 2 164 "tty-level buffer overflow", 165}; 166 167#define CE_NTYPES 3 168#define CE_RECORD(com, errnum) (++(com)->delta_error_counts[errnum]) 169 170/* types. XXX - should be elsewhere */ 171typedef u_int Port_t; /* hardware port */ 172typedef u_char bool_t; /* boolean */ 173 174/* queue of linear buffers */ 175struct lbq { 176 u_char *l_head; /* next char to process */ 177 u_char *l_tail; /* one past the last char to process */ 178 struct lbq *l_next; /* next in queue */ 179 bool_t l_queued; /* nonzero if queued */ 180}; 181 182/* com device structure */ 183struct com_s { 184 u_char state; /* miscellaneous flag bits */ 185 bool_t active_out; /* nonzero if the callout device is open */ 186 u_char cfcr_image; /* copy of value written to CFCR */ 187#ifdef COM_ESP 188 bool_t esp; /* is this unit a hayes esp board? */ 189#endif 190 u_char extra_state; /* more flag bits, separate for order trick */ 191 u_char fifo_image; /* copy of value written to FIFO */ 192 bool_t hasfifo; /* nonzero for 16550 UARTs */ 193 bool_t loses_outints; /* nonzero if device loses output interrupts */ 194 u_char mcr_image; /* copy of value written to MCR */ 195#ifdef COM_MULTIPORT 196 bool_t multiport; /* is this unit part of a multiport device? */ 197#endif /* COM_MULTIPORT */ 198 bool_t no_irq; /* nonzero if irq is not attached */ 199 bool_t gone; /* hardware disappeared */ 200 bool_t poll; /* nonzero if polling is required */ 201 bool_t poll_output; /* nonzero if polling for output is required */ 202 bool_t st16650a; /* nonzero if Startech 16650A compatible */ 203 int unit; /* unit number */ 204 int dtr_wait; /* time to hold DTR down on close (* 1/hz) */ 205 u_int flags; /* copy of device flags */ 206 u_int tx_fifo_size; 207 u_int wopeners; /* # processes waiting for DCD in open() */ 208 209 /* 210 * The high level of the driver never reads status registers directly 211 * because there would be too many side effects to handle conveniently. 212 * Instead, it reads copies of the registers stored here by the 213 * interrupt handler. 214 */ 215 u_char last_modem_status; /* last MSR read by intr handler */ 216 u_char prev_modem_status; /* last MSR handled by high level */ 217 218 u_char hotchar; /* ldisc-specific char to be handled ASAP */ 219 u_char *ibuf; /* start of input buffer */ 220 u_char *ibufend; /* end of input buffer */ 221 u_char *ibufold; /* old input buffer, to be freed */ 222 u_char *ihighwater; /* threshold in input buffer */ 223 u_char *iptr; /* next free spot in input buffer */ 224 int ibufsize; /* size of ibuf (not include error bytes) */ 225 int ierroff; /* offset of error bytes in ibuf */ 226 227 struct lbq obufq; /* head of queue of output buffers */ 228 struct lbq obufs[2]; /* output buffers */ 229 230 bus_space_tag_t bst; 231 bus_space_handle_t bsh; 232 233 Port_t data_port; /* i/o ports */ 234#ifdef COM_ESP 235 Port_t esp_port; 236#endif 237 Port_t int_ctl_port; 238 Port_t int_id_port; 239 Port_t modem_ctl_port; 240 Port_t line_status_port; 241 Port_t modem_status_port; 242 243 struct tty *tp; /* cross reference */ 244 245 /* Initial state. */ 246 struct termios it_in; /* should be in struct tty */ 247 struct termios it_out; 248 249 /* Lock state. */ 250 struct termios lt_in; /* should be in struct tty */ 251 struct termios lt_out; 252 253 bool_t do_timestamp; 254 bool_t do_dcd_timestamp; 255 struct timeval timestamp; 256 struct timeval dcd_timestamp; 257 struct pps_state pps; 258 int pps_bit; 259#ifdef ALT_BREAK_TO_DEBUGGER 260 int alt_brk_state; 261#endif 262 263 u_long bytes_in; /* statistics */ 264 u_long bytes_out; 265 u_int delta_error_counts[CE_NTYPES]; 266 u_long error_counts[CE_NTYPES]; 267 268 u_long rclk; 269 270 struct resource *irqres; 271 struct resource *ioportres; 272 int ioportrid; 273 void *cookie; 274 struct cdev *devs[6]; 275 276 /* 277 * Data area for output buffers. Someday we should build the output 278 * buffer queue without copying data. 279 */ 280 u_char obuf1[256]; 281 u_char obuf2[256]; 282}; 283 284#ifdef COM_ESP 285static int espattach(struct com_s *com, Port_t esp_port); 286#endif 287 288static timeout_t siobusycheck; 289static u_int siodivisor(u_long rclk, speed_t speed); 290static timeout_t siodtrwakeup; 291static void comhardclose(struct com_s *com); 292static void sioinput(struct com_s *com); 293static void siointr1(struct com_s *com); 294static void siointr(void *arg); 295static int commctl(struct com_s *com, int bits, int how); 296static int comparam(struct tty *tp, struct termios *t); 297static void siopoll(void *); 298static void siosettimeout(void); 299static int siosetwater(struct com_s *com, speed_t speed); 300static void comstart(struct tty *tp); 301static void comstop(struct tty *tp, int rw); 302static timeout_t comwakeup; 303 304char sio_driver_name[] = "sio"; 305static struct mtx sio_lock; 306static int sio_inited; 307 308/* table and macro for fast conversion from a unit number to its com struct */ 309devclass_t sio_devclass; 310#define com_addr(unit) ((struct com_s *) \ 311 devclass_get_softc(sio_devclass, unit)) /* XXX */ 312 313static d_open_t sioopen; 314static d_close_t sioclose; 315static d_read_t sioread; 316static d_write_t siowrite; 317static d_ioctl_t sioioctl; 318 319static struct cdevsw sio_cdevsw = { 320 .d_version = D_VERSION, 321 .d_open = sioopen, 322 .d_close = sioclose, 323 .d_read = sioread, 324 .d_write = siowrite, 325 .d_ioctl = sioioctl, 326 .d_name = sio_driver_name, 327 .d_flags = D_TTY | D_NEEDGIANT, 328}; 329 330static d_open_t siocopen; 331static d_close_t siocclose; 332static d_read_t siocrdwr; 333static d_ioctl_t siocioctl; 334 335static struct cdevsw sioc_cdevsw = { 336 .d_version = D_VERSION, 337 .d_open = siocopen, 338 .d_close = siocclose, 339 .d_read = siocrdwr, 340 .d_write = siocrdwr, 341 .d_ioctl = siocioctl, 342 .d_name = sio_driver_name, 343 .d_flags = D_TTY | D_NEEDGIANT, 344}; 345 346int comconsole = -1; 347static volatile speed_t comdefaultrate = CONSPEED; 348static u_long comdefaultrclk = DEFAULT_RCLK; 349SYSCTL_ULONG(_machdep, OID_AUTO, conrclk, CTLFLAG_RW, &comdefaultrclk, 0, ""); 350static speed_t gdbdefaultrate = GDBSPEED; 351SYSCTL_UINT(_machdep, OID_AUTO, gdbspeed, CTLFLAG_RW, 352 &gdbdefaultrate, GDBSPEED, ""); 353static u_int com_events; /* input chars + weighted output completions */ 354static Port_t siocniobase; 355static int siocnunit = -1; 356static Port_t siogdbiobase; 357static int siogdbunit = -1; 358static void *sio_slow_ih; 359static void *sio_fast_ih; 360static int sio_timeout; 361static int sio_timeouts_until_log; 362static struct callout_handle sio_timeout_handle 363 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle); 364static int sio_numunits; 365 366#ifdef COM_ESP 367/* XXX configure this properly. */ 368/* XXX quite broken for new-bus. */ 369static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, }; 370static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 }; 371#endif 372 373/* 374 * handle sysctl read/write requests for console speed 375 * 376 * In addition to setting comdefaultrate for I/O through /dev/console, 377 * also set the initial and lock values for the /dev/ttyXX device 378 * if there is one associated with the console. Finally, if the /dev/tty 379 * device has already been open, change the speed on the open running port 380 * itself. 381 */ 382 383static int 384sysctl_machdep_comdefaultrate(SYSCTL_HANDLER_ARGS) 385{ 386 int error, s; 387 speed_t newspeed; 388 struct com_s *com; 389 struct tty *tp; 390 391 newspeed = comdefaultrate; 392 393 error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req); 394 if (error || !req->newptr) 395 return (error); 396 397 comdefaultrate = newspeed; 398 399 if (comconsole < 0) /* serial console not selected? */ 400 return (0); 401 402 com = com_addr(comconsole); 403 if (com == NULL) 404 return (ENXIO); 405 406 /* 407 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX 408 * (note, the lock rates really are boolean -- if non-zero, disallow 409 * speed changes) 410 */ 411 com->it_in.c_ispeed = com->it_in.c_ospeed = 412 com->lt_in.c_ispeed = com->lt_in.c_ospeed = 413 com->it_out.c_ispeed = com->it_out.c_ospeed = 414 com->lt_out.c_ispeed = com->lt_out.c_ospeed = comdefaultrate; 415 416 /* 417 * if we're open, change the running rate too 418 */ 419 tp = com->tp; 420 if (tp && (tp->t_state & TS_ISOPEN)) { 421 tp->t_termios.c_ispeed = 422 tp->t_termios.c_ospeed = comdefaultrate; 423 s = spltty(); 424 error = comparam(tp, &tp->t_termios); 425 splx(s); 426 } 427 return error; 428} 429 430SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW, 431 0, 0, sysctl_machdep_comdefaultrate, "I", ""); 432/* TUNABLE_INT("machdep.conspeed", &comdefaultrate); */ 433 434#define SET_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) | (bit)) 435#define CLR_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) & ~(bit)) 436 437/* 438 * Unload the driver and clear the table. 439 * XXX this is mostly wrong. 440 * XXX TODO: 441 * This is usually called when the card is ejected, but 442 * can be caused by a kldunload of a controller driver. 443 * The idea is to reset the driver's view of the device 444 * and ensure that any driver entry points such as 445 * read and write do not hang. 446 */ 447int 448siodetach(dev) 449 device_t dev; 450{ 451 struct com_s *com; 452 int i; 453 454 com = (struct com_s *) device_get_softc(dev); 455 if (com == NULL) { 456 device_printf(dev, "NULL com in siounload\n"); 457 return (0); 458 } 459 com->gone = TRUE; 460 for (i = 0 ; i < 6; i++) 461 destroy_dev(com->devs[i]); 462 if (com->irqres) { 463 bus_teardown_intr(dev, com->irqres, com->cookie); 464 bus_release_resource(dev, SYS_RES_IRQ, 0, com->irqres); 465 } 466 if (com->ioportres) 467 bus_release_resource(dev, SYS_RES_IOPORT, com->ioportrid, 468 com->ioportres); 469 if (com->tp && (com->tp->t_state & TS_ISOPEN)) { 470 device_printf(dev, "still open, forcing close\n"); 471 ttyld_close(com->tp, 0); 472 ttyclose(com->tp); 473 } else { 474 if (com->ibuf != NULL) 475 free(com->ibuf, M_DEVBUF); 476 device_set_softc(dev, NULL); 477 free(com, M_DEVBUF); 478 } 479 return (0); 480} 481 482int 483sioprobe(dev, xrid, rclk, noprobe) 484 device_t dev; 485 int xrid; 486 u_long rclk; 487 int noprobe; 488{ 489#if 0 490 static bool_t already_init; 491 device_t xdev; 492#endif 493 struct com_s *com; 494 u_int divisor; 495 bool_t failures[10]; 496 int fn; 497 device_t idev; 498 Port_t iobase; 499 intrmask_t irqmap[4]; 500 intrmask_t irqs; 501 u_char mcr_image; 502 int result; 503 u_long xirq; 504 u_int flags = device_get_flags(dev); 505 int rid; 506 struct resource *port; 507 508 rid = xrid; 509 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 510 0, ~0, IO_COMSIZE, RF_ACTIVE); 511 if (!port) 512 return (ENXIO); 513 514 com = malloc(sizeof(*com), M_DEVBUF, M_NOWAIT | M_ZERO); 515 if (com == NULL) { 516 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 517 return (ENOMEM); 518 } 519 device_set_softc(dev, com); 520 com->bst = rman_get_bustag(port); 521 com->bsh = rman_get_bushandle(port); 522 if (rclk == 0) 523 rclk = DEFAULT_RCLK; 524 com->rclk = rclk; 525 526 while (sio_inited != 2) 527 if (atomic_cmpset_int(&sio_inited, 0, 1)) { 528 mtx_init(&sio_lock, sio_driver_name, NULL, 529 (comconsole != -1) ? 530 MTX_SPIN | MTX_QUIET : MTX_SPIN); 531 atomic_store_rel_int(&sio_inited, 2); 532 } 533 534#if 0 535 /* 536 * XXX this is broken - when we are first called, there are no 537 * previously configured IO ports. We could hard code 538 * 0x3f8, 0x2f8, 0x3e8, 0x2e8 etc but that's probably worse. 539 * This code has been doing nothing since the conversion since 540 * "count" is zero the first time around. 541 */ 542 if (!already_init) { 543 /* 544 * Turn off MCR_IENABLE for all likely serial ports. An unused 545 * port with its MCR_IENABLE gate open will inhibit interrupts 546 * from any used port that shares the interrupt vector. 547 * XXX the gate enable is elsewhere for some multiports. 548 */ 549 device_t *devs; 550 int count, i, xioport; 551 552 devclass_get_devices(sio_devclass, &devs, &count); 553 for (i = 0; i < count; i++) { 554 xdev = devs[i]; 555 if (device_is_enabled(xdev) && 556 bus_get_resource(xdev, SYS_RES_IOPORT, 0, &xioport, 557 NULL) == 0) 558 outb(xioport + com_mcr, 0); 559 } 560 free(devs, M_TEMP); 561 already_init = TRUE; 562 } 563#endif 564 565 if (COM_LLCONSOLE(flags)) { 566 printf("sio%d: reserved for low-level i/o\n", 567 device_get_unit(dev)); 568 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 569 device_set_softc(dev, NULL); 570 free(com, M_DEVBUF); 571 return (ENXIO); 572 } 573 574 /* 575 * If the device is on a multiport card and has an AST/4 576 * compatible interrupt control register, initialize this 577 * register and prepare to leave MCR_IENABLE clear in the mcr. 578 * Otherwise, prepare to set MCR_IENABLE in the mcr. 579 * Point idev to the device struct giving the correct id_irq. 580 * This is the struct for the master device if there is one. 581 */ 582 idev = dev; 583 mcr_image = MCR_IENABLE; 584#ifdef COM_MULTIPORT 585 if (COM_ISMULTIPORT(flags)) { 586 Port_t xiobase; 587 u_long io; 588 589 idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags)); 590 if (idev == NULL) { 591 printf("sio%d: master device %d not configured\n", 592 device_get_unit(dev), COM_MPMASTER(flags)); 593 idev = dev; 594 } 595 if (!COM_NOTAST4(flags)) { 596 if (bus_get_resource(idev, SYS_RES_IOPORT, 0, &io, 597 NULL) == 0) { 598 xiobase = io; 599 if (bus_get_resource(idev, SYS_RES_IRQ, 0, 600 NULL, NULL) == 0) 601 outb(xiobase + com_scr, 0x80); 602 else 603 outb(xiobase + com_scr, 0); 604 } 605 mcr_image = 0; 606 } 607 } 608#endif /* COM_MULTIPORT */ 609 if (bus_get_resource(idev, SYS_RES_IRQ, 0, NULL, NULL) != 0) 610 mcr_image = 0; 611 612 bzero(failures, sizeof failures); 613 iobase = rman_get_start(port); 614 615 /* 616 * We don't want to get actual interrupts, just masked ones. 617 * Interrupts from this line should already be masked in the ICU, 618 * but mask them in the processor as well in case there are some 619 * (misconfigured) shared interrupts. 620 */ 621 mtx_lock_spin(&sio_lock); 622/* EXTRA DELAY? */ 623 624 /* 625 * For the TI16754 chips, set prescaler to 1 (4 is often the 626 * default after-reset value) as otherwise it's impossible to 627 * get highest baudrates. 628 */ 629 if (COM_TI16754(flags)) { 630 u_char cfcr, efr; 631 632 cfcr = sio_getreg(com, com_cfcr); 633 sio_setreg(com, com_cfcr, CFCR_EFR_ENABLE); 634 efr = sio_getreg(com, com_efr); 635 /* Unlock extended features to turn off prescaler. */ 636 sio_setreg(com, com_efr, efr | EFR_EFE); 637 /* Disable EFR. */ 638 sio_setreg(com, com_cfcr, (cfcr != CFCR_EFR_ENABLE) ? cfcr : 0); 639 /* Turn off prescaler. */ 640 sio_setreg(com, com_mcr, 641 sio_getreg(com, com_mcr) & ~MCR_PRESCALE); 642 sio_setreg(com, com_cfcr, CFCR_EFR_ENABLE); 643 sio_setreg(com, com_efr, efr); 644 sio_setreg(com, com_cfcr, cfcr); 645 } 646 647 /* 648 * Initialize the speed and the word size and wait long enough to 649 * drain the maximum of 16 bytes of junk in device output queues. 650 * The speed is undefined after a master reset and must be set 651 * before relying on anything related to output. There may be 652 * junk after a (very fast) soft reboot and (apparently) after 653 * master reset. 654 * XXX what about the UART bug avoided by waiting in comparam()? 655 * We don't want to to wait long enough to drain at 2 bps. 656 */ 657 if (iobase == siocniobase) 658 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10)); 659 else { 660 sio_setreg(com, com_cfcr, CFCR_DLAB | CFCR_8BITS); 661 divisor = siodivisor(rclk, SIO_TEST_SPEED); 662 sio_setreg(com, com_dlbl, divisor & 0xff); 663 sio_setreg(com, com_dlbh, divisor >> 8); 664 sio_setreg(com, com_cfcr, CFCR_8BITS); 665 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10)); 666 } 667 668 /* 669 * Enable the interrupt gate and disable device interupts. This 670 * should leave the device driving the interrupt line low and 671 * guarantee an edge trigger if an interrupt can be generated. 672 */ 673/* EXTRA DELAY? */ 674 sio_setreg(com, com_mcr, mcr_image); 675 sio_setreg(com, com_ier, 0); 676 DELAY(1000); /* XXX */ 677 irqmap[0] = isa_irq_pending(); 678 679 /* 680 * Attempt to set loopback mode so that we can send a null byte 681 * without annoying any external device. 682 */ 683/* EXTRA DELAY? */ 684 sio_setreg(com, com_mcr, mcr_image | MCR_LOOPBACK); 685 686 /* 687 * Attempt to generate an output interrupt. On 8250's, setting 688 * IER_ETXRDY generates an interrupt independent of the current 689 * setting and independent of whether the THR is empty. On 16450's, 690 * setting IER_ETXRDY generates an interrupt independent of the 691 * current setting. On 16550A's, setting IER_ETXRDY only 692 * generates an interrupt when IER_ETXRDY is not already set. 693 */ 694 sio_setreg(com, com_ier, IER_ETXRDY); 695 696 /* 697 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate 698 * an interrupt. They'd better generate one for actually doing 699 * output. Loopback may be broken on the same incompatibles but 700 * it's unlikely to do more than allow the null byte out. 701 */ 702 sio_setreg(com, com_data, 0); 703 if (iobase == siocniobase) 704 DELAY((1 + 2) * 1000000 / (comdefaultrate / 10)); 705 else 706 DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10)); 707 708 /* 709 * Turn off loopback mode so that the interrupt gate works again 710 * (MCR_IENABLE was hidden). This should leave the device driving 711 * an interrupt line high. It doesn't matter if the interrupt 712 * line oscillates while we are not looking at it, since interrupts 713 * are disabled. 714 */ 715/* EXTRA DELAY? */ 716 sio_setreg(com, com_mcr, mcr_image); 717 718 /* 719 * It seems my Xircom CBEM56G Cardbus modem wants to be reset 720 * to 8 bits *again*, or else probe test 0 will fail. 721 * gwk@sgi.com, 4/19/2001 722 */ 723 sio_setreg(com, com_cfcr, CFCR_8BITS); 724 725 /* 726 * Some PCMCIA cards (Palido 321s, DC-1S, ...) have the "TXRDY bug", 727 * so we probe for a buggy IIR_TXRDY implementation even in the 728 * noprobe case. We don't probe for it in the !noprobe case because 729 * noprobe is always set for PCMCIA cards and the problem is not 730 * known to affect any other cards. 731 */ 732 if (noprobe) { 733 /* Read IIR a few times. */ 734 for (fn = 0; fn < 2; fn ++) { 735 DELAY(10000); 736 failures[6] = sio_getreg(com, com_iir); 737 } 738 739 /* IIR_TXRDY should be clear. Is it? */ 740 result = 0; 741 if (failures[6] & IIR_TXRDY) { 742 /* 743 * No. We seem to have the bug. Does our fix for 744 * it work? 745 */ 746 sio_setreg(com, com_ier, 0); 747 if (sio_getreg(com, com_iir) & IIR_NOPEND) { 748 /* Yes. We discovered the TXRDY bug! */ 749 SET_FLAG(dev, COM_C_IIR_TXRDYBUG); 750 } else { 751 /* No. Just fail. XXX */ 752 result = ENXIO; 753 sio_setreg(com, com_mcr, 0); 754 } 755 } else { 756 /* Yes. No bug. */ 757 CLR_FLAG(dev, COM_C_IIR_TXRDYBUG); 758 } 759 sio_setreg(com, com_ier, 0); 760 sio_setreg(com, com_cfcr, CFCR_8BITS); 761 mtx_unlock_spin(&sio_lock); 762 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 763 if (iobase == siocniobase) 764 result = 0; 765 if (result != 0) { 766 device_set_softc(dev, NULL); 767 free(com, M_DEVBUF); 768 } 769 return (result); 770 } 771 772 /* 773 * Check that 774 * o the CFCR, IER and MCR in UART hold the values written to them 775 * (the values happen to be all distinct - this is good for 776 * avoiding false positive tests from bus echoes). 777 * o an output interrupt is generated and its vector is correct. 778 * o the interrupt goes away when the IIR in the UART is read. 779 */ 780/* EXTRA DELAY? */ 781 failures[0] = sio_getreg(com, com_cfcr) - CFCR_8BITS; 782 failures[1] = sio_getreg(com, com_ier) - IER_ETXRDY; 783 failures[2] = sio_getreg(com, com_mcr) - mcr_image; 784 DELAY(10000); /* Some internal modems need this time */ 785 irqmap[1] = isa_irq_pending(); 786 failures[4] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_TXRDY; 787 DELAY(1000); /* XXX */ 788 irqmap[2] = isa_irq_pending(); 789 failures[6] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND; 790 791 /* 792 * Turn off all device interrupts and check that they go off properly. 793 * Leave MCR_IENABLE alone. For ports without a master port, it gates 794 * the OUT2 output of the UART to 795 * the ICU input. Closing the gate would give a floating ICU input 796 * (unless there is another device driving it) and spurious interrupts. 797 * (On the system that this was first tested on, the input floats high 798 * and gives a (masked) interrupt as soon as the gate is closed.) 799 */ 800 sio_setreg(com, com_ier, 0); 801 sio_setreg(com, com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */ 802 failures[7] = sio_getreg(com, com_ier); 803 DELAY(1000); /* XXX */ 804 irqmap[3] = isa_irq_pending(); 805 failures[9] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND; 806 807 mtx_unlock_spin(&sio_lock); 808 809 irqs = irqmap[1] & ~irqmap[0]; 810 if (bus_get_resource(idev, SYS_RES_IRQ, 0, &xirq, NULL) == 0 && 811 ((1 << xirq) & irqs) == 0) { 812 printf( 813 "sio%d: configured irq %ld not in bitmap of probed irqs %#x\n", 814 device_get_unit(dev), xirq, irqs); 815 printf( 816 "sio%d: port may not be enabled\n", 817 device_get_unit(dev)); 818 } 819 if (bootverbose) 820 printf("sio%d: irq maps: %#x %#x %#x %#x\n", 821 device_get_unit(dev), 822 irqmap[0], irqmap[1], irqmap[2], irqmap[3]); 823 824 result = 0; 825 for (fn = 0; fn < sizeof failures; ++fn) 826 if (failures[fn]) { 827 sio_setreg(com, com_mcr, 0); 828 result = ENXIO; 829 if (bootverbose) { 830 printf("sio%d: probe failed test(s):", 831 device_get_unit(dev)); 832 for (fn = 0; fn < sizeof failures; ++fn) 833 if (failures[fn]) 834 printf(" %d", fn); 835 printf("\n"); 836 } 837 break; 838 } 839 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 840 if (iobase == siocniobase) 841 result = 0; 842 if (result != 0) { 843 device_set_softc(dev, NULL); 844 free(com, M_DEVBUF); 845 } 846 return (result); 847} 848 849#ifdef COM_ESP 850static int 851espattach(com, esp_port) 852 struct com_s *com; 853 Port_t esp_port; 854{ 855 u_char dips; 856 u_char val; 857 858 /* 859 * Check the ESP-specific I/O port to see if we're an ESP 860 * card. If not, return failure immediately. 861 */ 862 if ((inb(esp_port) & 0xf3) == 0) { 863 printf(" port 0x%x is not an ESP board?\n", esp_port); 864 return (0); 865 } 866 867 /* 868 * We've got something that claims to be a Hayes ESP card. 869 * Let's hope so. 870 */ 871 872 /* Get the dip-switch configuration */ 873 outb(esp_port + ESP_CMD1, ESP_GETDIPS); 874 dips = inb(esp_port + ESP_STATUS1); 875 876 /* 877 * Bits 0,1 of dips say which COM port we are. 878 */ 879 if (rman_get_start(com->ioportres) == likely_com_ports[dips & 0x03]) 880 printf(" : ESP"); 881 else { 882 printf(" esp_port has com %d\n", dips & 0x03); 883 return (0); 884 } 885 886 /* 887 * Check for ESP version 2.0 or later: bits 4,5,6 = 010. 888 */ 889 outb(esp_port + ESP_CMD1, ESP_GETTEST); 890 val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */ 891 val = inb(esp_port + ESP_STATUS2); 892 if ((val & 0x70) < 0x20) { 893 printf("-old (%o)", val & 0x70); 894 return (0); 895 } 896 897 /* 898 * Check for ability to emulate 16550: bit 7 == 1 899 */ 900 if ((dips & 0x80) == 0) { 901 printf(" slave"); 902 return (0); 903 } 904 905 /* 906 * Okay, we seem to be a Hayes ESP card. Whee. 907 */ 908 com->esp = TRUE; 909 com->esp_port = esp_port; 910 return (1); 911} 912#endif /* COM_ESP */ 913 914int 915sioattach(dev, xrid, rclk) 916 device_t dev; 917 int xrid; 918 u_long rclk; 919{ 920 struct com_s *com; 921#ifdef COM_ESP 922 Port_t *espp; 923#endif 924 Port_t iobase; 925 int minorbase; 926 int unit; 927 u_int flags; 928 int rid; 929 struct resource *port; 930 int ret; 931 932 rid = xrid; 933 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 934 0, ~0, IO_COMSIZE, RF_ACTIVE); 935 if (!port) 936 return (ENXIO); 937 938 iobase = rman_get_start(port); 939 unit = device_get_unit(dev); 940 com = device_get_softc(dev); 941 flags = device_get_flags(dev); 942 943 if (unit >= sio_numunits) 944 sio_numunits = unit + 1; 945 /* 946 * sioprobe() has initialized the device registers as follows: 947 * o cfcr = CFCR_8BITS. 948 * It is most important that CFCR_DLAB is off, so that the 949 * data port is not hidden when we enable interrupts. 950 * o ier = 0. 951 * Interrupts are only enabled when the line is open. 952 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible 953 * interrupt control register or the config specifies no irq. 954 * Keeping MCR_DTR and MCR_RTS off might stop the external 955 * device from sending before we are ready. 956 */ 957 bzero(com, sizeof *com); 958 com->unit = unit; 959 com->ioportres = port; 960 com->ioportrid = rid; 961 com->bst = rman_get_bustag(port); 962 com->bsh = rman_get_bushandle(port); 963 com->cfcr_image = CFCR_8BITS; 964 com->dtr_wait = 3 * hz; 965 com->loses_outints = COM_LOSESOUTINTS(flags) != 0; 966 com->no_irq = bus_get_resource(dev, SYS_RES_IRQ, 0, NULL, NULL) != 0; 967 com->tx_fifo_size = 1; 968 com->obufs[0].l_head = com->obuf1; 969 com->obufs[1].l_head = com->obuf2; 970 971 com->data_port = iobase + com_data; 972 com->int_ctl_port = iobase + com_ier; 973 com->int_id_port = iobase + com_iir; 974 com->modem_ctl_port = iobase + com_mcr; 975 com->mcr_image = inb(com->modem_ctl_port); 976 com->line_status_port = iobase + com_lsr; 977 com->modem_status_port = iobase + com_msr; 978 979 if (rclk == 0) 980 rclk = DEFAULT_RCLK; 981 com->rclk = rclk; 982 983 /* 984 * We don't use all the flags from <sys/ttydefaults.h> since they 985 * are only relevant for logins. It's important to have echo off 986 * initially so that the line doesn't start blathering before the 987 * echo flag can be turned off. 988 */ 989 com->it_in.c_iflag = 0; 990 com->it_in.c_oflag = 0; 991 com->it_in.c_cflag = TTYDEF_CFLAG; 992 com->it_in.c_lflag = 0; 993 if (unit == comconsole) { 994 com->it_in.c_iflag = TTYDEF_IFLAG; 995 com->it_in.c_oflag = TTYDEF_OFLAG; 996 com->it_in.c_cflag = TTYDEF_CFLAG | CLOCAL; 997 com->it_in.c_lflag = TTYDEF_LFLAG; 998 com->lt_out.c_cflag = com->lt_in.c_cflag = CLOCAL; 999 com->lt_out.c_ispeed = com->lt_out.c_ospeed = 1000 com->lt_in.c_ispeed = com->lt_in.c_ospeed = 1001 com->it_in.c_ispeed = com->it_in.c_ospeed = comdefaultrate; 1002 } else 1003 com->it_in.c_ispeed = com->it_in.c_ospeed = TTYDEF_SPEED; 1004 if (siosetwater(com, com->it_in.c_ispeed) != 0) { 1005 mtx_unlock_spin(&sio_lock); 1006 /* 1007 * Leave i/o resources allocated if this is a `cn'-level 1008 * console, so that other devices can't snarf them. 1009 */ 1010 if (iobase != siocniobase) 1011 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1012 return (ENOMEM); 1013 } 1014 mtx_unlock_spin(&sio_lock); 1015 termioschars(&com->it_in); 1016 com->it_out = com->it_in; 1017 1018 /* attempt to determine UART type */ 1019 printf("sio%d: type", unit); 1020 1021 1022 if (!COM_ISMULTIPORT(flags) && 1023 !COM_IIR_TXRDYBUG(flags) && !COM_NOSCR(flags)) { 1024 u_char scr; 1025 u_char scr1; 1026 u_char scr2; 1027 1028 scr = sio_getreg(com, com_scr); 1029 sio_setreg(com, com_scr, 0xa5); 1030 scr1 = sio_getreg(com, com_scr); 1031 sio_setreg(com, com_scr, 0x5a); 1032 scr2 = sio_getreg(com, com_scr); 1033 sio_setreg(com, com_scr, scr); 1034 if (scr1 != 0xa5 || scr2 != 0x5a) { 1035 printf(" 8250 or not responding"); 1036 goto determined_type; 1037 } 1038 } 1039 sio_setreg(com, com_fifo, FIFO_ENABLE | FIFO_RX_HIGH); 1040 DELAY(100); 1041 switch (inb(com->int_id_port) & IIR_FIFO_MASK) { 1042 case FIFO_RX_LOW: 1043 printf(" 16450"); 1044 break; 1045 case FIFO_RX_MEDL: 1046 printf(" 16450?"); 1047 break; 1048 case FIFO_RX_MEDH: 1049 printf(" 16550?"); 1050 break; 1051 case FIFO_RX_HIGH: 1052 if (COM_NOFIFO(flags)) { 1053 printf(" 16550A fifo disabled"); 1054 break; 1055 } 1056 com->hasfifo = TRUE; 1057 if (COM_ST16650A(flags)) { 1058 printf(" ST16650A"); 1059 com->st16650a = TRUE; 1060 com->tx_fifo_size = 32; 1061 break; 1062 } 1063 if (COM_TI16754(flags)) { 1064 printf(" TI16754"); 1065 com->tx_fifo_size = 64; 1066 break; 1067 } 1068 printf(" 16550A"); 1069#ifdef COM_ESP 1070 for (espp = likely_esp_ports; *espp != 0; espp++) 1071 if (espattach(com, *espp)) { 1072 com->tx_fifo_size = 1024; 1073 break; 1074 } 1075 if (com->esp) 1076 break; 1077#endif 1078 com->tx_fifo_size = COM_FIFOSIZE(flags); 1079 if (com->tx_fifo_size == 0) 1080 com->tx_fifo_size = 16; 1081 else 1082 printf(" lookalike with %u bytes FIFO", 1083 com->tx_fifo_size); 1084 break; 1085 } 1086#ifdef COM_ESP 1087 if (com->esp) { 1088 /* 1089 * Set 16550 compatibility mode. 1090 * We don't use the ESP_MODE_SCALE bit to increase the 1091 * fifo trigger levels because we can't handle large 1092 * bursts of input. 1093 * XXX flow control should be set in comparam(), not here. 1094 */ 1095 outb(com->esp_port + ESP_CMD1, ESP_SETMODE); 1096 outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO); 1097 1098 /* Set RTS/CTS flow control. */ 1099 outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE); 1100 outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS); 1101 outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS); 1102 1103 /* Set flow-control levels. */ 1104 outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW); 1105 outb(com->esp_port + ESP_CMD2, HIBYTE(768)); 1106 outb(com->esp_port + ESP_CMD2, LOBYTE(768)); 1107 outb(com->esp_port + ESP_CMD2, HIBYTE(512)); 1108 outb(com->esp_port + ESP_CMD2, LOBYTE(512)); 1109 } 1110#endif /* COM_ESP */ 1111 sio_setreg(com, com_fifo, 0); 1112determined_type: ; 1113 1114#ifdef COM_MULTIPORT 1115 if (COM_ISMULTIPORT(flags)) { 1116 device_t masterdev; 1117 1118 com->multiport = TRUE; 1119 printf(" (multiport"); 1120 if (unit == COM_MPMASTER(flags)) 1121 printf(" master"); 1122 printf(")"); 1123 masterdev = devclass_get_device(sio_devclass, 1124 COM_MPMASTER(flags)); 1125 com->no_irq = (masterdev == NULL || bus_get_resource(masterdev, 1126 SYS_RES_IRQ, 0, NULL, NULL) != 0); 1127 } 1128#endif /* COM_MULTIPORT */ 1129 if (unit == comconsole) 1130 printf(", console"); 1131 if (COM_IIR_TXRDYBUG(flags)) 1132 printf(" with a buggy IIR_TXRDY implementation"); 1133 printf("\n"); 1134 1135 if (sio_fast_ih == NULL) { 1136 swi_add(&tty_ithd, "tty:sio", siopoll, NULL, SWI_TTY, 0, 1137 &sio_fast_ih); 1138 swi_add(&clk_ithd, "tty:sio", siopoll, NULL, SWI_TTY, 0, 1139 &sio_slow_ih); 1140 } 1141 minorbase = UNIT_TO_MINOR(unit); 1142 com->devs[0] = make_dev(&sio_cdevsw, minorbase, 1143 UID_ROOT, GID_WHEEL, 0600, "ttyd%r", unit); 1144 com->devs[1] = make_dev(&sioc_cdevsw, minorbase | CONTROL_INIT_STATE, 1145 UID_ROOT, GID_WHEEL, 0600, "ttyid%r", unit); 1146 com->devs[2] = make_dev(&sioc_cdevsw, minorbase | CONTROL_LOCK_STATE, 1147 UID_ROOT, GID_WHEEL, 0600, "ttyld%r", unit); 1148 com->devs[3] = make_dev(&sio_cdevsw, minorbase | CALLOUT_MASK, 1149 UID_UUCP, GID_DIALER, 0660, "cuaa%r", unit); 1150 com->devs[4] = make_dev(&sioc_cdevsw, 1151 minorbase | CALLOUT_MASK | CONTROL_INIT_STATE, 1152 UID_UUCP, GID_DIALER, 0660, "cuaia%r", unit); 1153 com->devs[5] = make_dev(&sioc_cdevsw, 1154 minorbase | CALLOUT_MASK | CONTROL_LOCK_STATE, 1155 UID_UUCP, GID_DIALER, 0660, "cuala%r", unit); 1156 for (rid = 0; rid < 6; rid++) 1157 com->devs[rid]->si_drv1 = com; 1158 com->flags = flags; 1159 com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 1160 1161 if (COM_PPSCTS(flags)) 1162 com->pps_bit = MSR_CTS; 1163 else 1164 com->pps_bit = MSR_DCD; 1165 pps_init(&com->pps); 1166 1167 rid = 0; 1168 com->irqres = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); 1169 if (com->irqres) { 1170 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, com->irqres, 1171 INTR_TYPE_TTY | INTR_FAST, 1172 siointr, com, &com->cookie); 1173 if (ret) { 1174 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, 1175 com->irqres, INTR_TYPE_TTY, 1176 siointr, com, &com->cookie); 1177 if (ret == 0) 1178 device_printf(dev, "unable to activate interrupt in fast mode - using normal mode\n"); 1179 } 1180 if (ret) 1181 device_printf(dev, "could not activate interrupt\n"); 1182#if defined(DDB) && (defined(BREAK_TO_DEBUGGER) || \ 1183 defined(ALT_BREAK_TO_DEBUGGER)) 1184 /* 1185 * Enable interrupts for early break-to-debugger support 1186 * on the console. 1187 */ 1188 if (ret == 0 && unit == comconsole) 1189 outb(siocniobase + com_ier, IER_ERXRDY | IER_ERLS | 1190 IER_EMSC); 1191#endif 1192 } 1193 1194 return (0); 1195} 1196 1197static int 1198siocopen(dev, flag, mode, td) 1199 struct cdev *dev; 1200 int flag; 1201 int mode; 1202 struct thread *td; 1203{ 1204 struct com_s *com; 1205 1206 com = dev->si_drv1; 1207 if (com == NULL) 1208 return (ENXIO); 1209 if (com->gone) 1210 return (ENXIO); 1211 return (0); 1212} 1213 1214static int 1215sioopen(dev, flag, mode, td) 1216 struct cdev *dev; 1217 int flag; 1218 int mode; 1219 struct thread *td; 1220{ 1221 struct com_s *com; 1222 int error; 1223 int mynor; 1224 int s; 1225 struct tty *tp; 1226 int unit; 1227 1228 mynor = minor(dev); 1229 unit = MINOR_TO_UNIT(mynor); 1230 com = dev->si_drv1; 1231 if (com == NULL) 1232 return (ENXIO); 1233 if (com->gone) 1234 return (ENXIO); 1235 tp = dev->si_tty = com->tp = ttymalloc(com->tp); 1236 s = spltty(); 1237 /* 1238 * We jump to this label after all non-interrupted sleeps to pick 1239 * up any changes of the device state. 1240 */ 1241open_top: 1242 while (com->state & CS_DTR_OFF) { 1243 error = tsleep(&com->dtr_wait, TTIPRI | PCATCH, "siodtr", 0); 1244 if (com_addr(unit) == NULL) 1245 return (ENXIO); 1246 if (error != 0 || com->gone) 1247 goto out; 1248 } 1249 if (tp->t_state & TS_ISOPEN) { 1250 /* 1251 * The device is open, so everything has been initialized. 1252 * Handle conflicts. 1253 */ 1254 if (mynor & CALLOUT_MASK) { 1255 if (!com->active_out) { 1256 error = EBUSY; 1257 goto out; 1258 } 1259 } else { 1260 if (com->active_out) { 1261 if (flag & O_NONBLOCK) { 1262 error = EBUSY; 1263 goto out; 1264 } 1265 error = tsleep(&com->active_out, 1266 TTIPRI | PCATCH, "siobi", 0); 1267 if (com_addr(unit) == NULL) 1268 return (ENXIO); 1269 if (error != 0 || com->gone) 1270 goto out; 1271 goto open_top; 1272 } 1273 } 1274 if (tp->t_state & TS_XCLUDE && 1275 suser(td)) { 1276 error = EBUSY; 1277 goto out; 1278 } 1279 } else { 1280 /* 1281 * The device isn't open, so there are no conflicts. 1282 * Initialize it. Initialization is done twice in many 1283 * cases: to preempt sleeping callin opens if we are 1284 * callout, and to complete a callin open after DCD rises. 1285 */ 1286 tp->t_oproc = comstart; 1287 tp->t_param = comparam; 1288 tp->t_stop = comstop; 1289 tp->t_dev = dev; 1290 tp->t_termios = mynor & CALLOUT_MASK 1291 ? com->it_out : com->it_in; 1292 (void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET); 1293 com->poll = com->no_irq; 1294 com->poll_output = com->loses_outints; 1295 ++com->wopeners; 1296 error = comparam(tp, &tp->t_termios); 1297 --com->wopeners; 1298 if (error != 0) 1299 goto out; 1300 /* 1301 * XXX we should goto open_top if comparam() slept. 1302 */ 1303 if (com->hasfifo) { 1304 int i; 1305 /* 1306 * (Re)enable and drain fifos. 1307 * 1308 * Certain SMC chips cause problems if the fifos 1309 * are enabled while input is ready. Turn off the 1310 * fifo if necessary to clear the input. We test 1311 * the input ready bit after enabling the fifos 1312 * since we've already enabled them in comparam() 1313 * and to handle races between enabling and fresh 1314 * input. 1315 */ 1316 for (i = 0; i < 500; i++) { 1317 sio_setreg(com, com_fifo, 1318 FIFO_RCV_RST | FIFO_XMT_RST 1319 | com->fifo_image); 1320 /* 1321 * XXX the delays are for superstitious 1322 * historical reasons. It must be less than 1323 * the character time at the maximum 1324 * supported speed (87 usec at 115200 bps 1325 * 8N1). Otherwise we might loop endlessly 1326 * if data is streaming in. We used to use 1327 * delays of 100. That usually worked 1328 * because DELAY(100) used to usually delay 1329 * for about 85 usec instead of 100. 1330 */ 1331 DELAY(50); 1332 if (!(inb(com->line_status_port) & LSR_RXRDY)) 1333 break; 1334 sio_setreg(com, com_fifo, 0); 1335 DELAY(50); 1336 (void) inb(com->data_port); 1337 } 1338 if (i == 500) { 1339 error = EIO; 1340 goto out; 1341 } 1342 } 1343 1344 mtx_lock_spin(&sio_lock); 1345 (void) inb(com->line_status_port); 1346 (void) inb(com->data_port); 1347 com->prev_modem_status = com->last_modem_status 1348 = inb(com->modem_status_port); 1349 outb(com->int_ctl_port, 1350 IER_ERXRDY | IER_ERLS | IER_EMSC 1351 | (COM_IIR_TXRDYBUG(com->flags) ? 0 : IER_ETXRDY)); 1352 mtx_unlock_spin(&sio_lock); 1353 /* 1354 * Handle initial DCD. Callout devices get a fake initial 1355 * DCD (trapdoor DCD). If we are callout, then any sleeping 1356 * callin opens get woken up and resume sleeping on "siobi" 1357 * instead of "siodcd". 1358 */ 1359 /* 1360 * XXX `mynor & CALLOUT_MASK' should be 1361 * `tp->t_cflag & (SOFT_CARRIER | TRAPDOOR_CARRIER) where 1362 * TRAPDOOR_CARRIER is the default initial state for callout 1363 * devices and SOFT_CARRIER is like CLOCAL except it hides 1364 * the true carrier. 1365 */ 1366 if (com->prev_modem_status & MSR_DCD || mynor & CALLOUT_MASK) 1367 ttyld_modem(tp, 1); 1368 } 1369 /* 1370 * Wait for DCD if necessary. 1371 */ 1372 if (!(tp->t_state & TS_CARR_ON) && !(mynor & CALLOUT_MASK) 1373 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 1374 ++com->wopeners; 1375 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "siodcd", 0); 1376 if (com_addr(unit) == NULL) 1377 return (ENXIO); 1378 --com->wopeners; 1379 if (error != 0 || com->gone) 1380 goto out; 1381 goto open_top; 1382 } 1383 error = ttyld_open(tp, dev); 1384 com->hotchar = ttyldoptim(tp); 1385 if (tp->t_state & TS_ISOPEN && mynor & CALLOUT_MASK) 1386 com->active_out = TRUE; 1387 siosettimeout(); 1388out: 1389 splx(s); 1390 if (!(tp->t_state & TS_ISOPEN) && com->wopeners == 0) 1391 comhardclose(com); 1392 return (error); 1393} 1394 1395static int 1396siocclose(dev, flag, mode, td) 1397 struct cdev *dev; 1398 int flag; 1399 int mode; 1400 struct thread *td; 1401{ 1402 1403 return (0); 1404} 1405 1406static int 1407sioclose(dev, flag, mode, td) 1408 struct cdev *dev; 1409 int flag; 1410 int mode; 1411 struct thread *td; 1412{ 1413 struct com_s *com; 1414 int mynor; 1415 int s; 1416 struct tty *tp; 1417 1418 mynor = minor(dev); 1419 com = dev->si_drv1; 1420 if (com == NULL) 1421 return (ENODEV); 1422 tp = com->tp; 1423 s = spltty(); 1424 ttyld_close(tp, flag); 1425 com->hotchar = ttyldoptim(tp); 1426 comhardclose(com); 1427 ttyclose(tp); 1428 siosettimeout(); 1429 splx(s); 1430 if (com->gone) { 1431 printf("sio%d: gone\n", com->unit); 1432 s = spltty(); 1433 if (com->ibuf != NULL) 1434 free(com->ibuf, M_DEVBUF); 1435 bzero(tp, sizeof *tp); 1436 splx(s); 1437 } 1438 return (0); 1439} 1440 1441static void 1442comhardclose(com) 1443 struct com_s *com; 1444{ 1445 int s; 1446 struct tty *tp; 1447 1448 s = spltty(); 1449 com->poll = FALSE; 1450 com->poll_output = FALSE; 1451 com->do_timestamp = FALSE; 1452 com->do_dcd_timestamp = FALSE; 1453 com->pps.ppsparam.mode = 0; 1454 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 1455 tp = com->tp; 1456 1457#if defined(DDB) && (defined(BREAK_TO_DEBUGGER) || \ 1458 defined(ALT_BREAK_TO_DEBUGGER)) 1459 /* 1460 * Leave interrupts enabled and don't clear DTR if this is the 1461 * console. This allows us to detect break-to-debugger events 1462 * while the console device is closed. 1463 */ 1464 if (com->unit != comconsole) 1465#endif 1466 { 1467 sio_setreg(com, com_ier, 0); 1468 if (tp->t_cflag & HUPCL 1469 /* 1470 * XXX we will miss any carrier drop between here and the 1471 * next open. Perhaps we should watch DCD even when the 1472 * port is closed; it is not sufficient to check it at 1473 * the next open because it might go up and down while 1474 * we're not watching. 1475 */ 1476 || (!com->active_out 1477 && !(com->prev_modem_status & MSR_DCD) 1478 && !(com->it_in.c_cflag & CLOCAL)) 1479 || !(tp->t_state & TS_ISOPEN)) { 1480 (void)commctl(com, TIOCM_DTR, DMBIC); 1481 if (com->dtr_wait != 0 && !(com->state & CS_DTR_OFF)) { 1482 timeout(siodtrwakeup, com, com->dtr_wait); 1483 com->state |= CS_DTR_OFF; 1484 } 1485 } 1486 } 1487 if (com->hasfifo) { 1488 /* 1489 * Disable fifos so that they are off after controlled 1490 * reboots. Some BIOSes fail to detect 16550s when the 1491 * fifos are enabled. 1492 */ 1493 sio_setreg(com, com_fifo, 0); 1494 } 1495 com->active_out = FALSE; 1496 wakeup(&com->active_out); 1497 wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */ 1498 splx(s); 1499} 1500 1501static int 1502siocrdwr(dev, uio, flag) 1503 struct cdev *dev; 1504 struct uio *uio; 1505 int flag; 1506{ 1507 1508 return (ENODEV); 1509} 1510 1511static int 1512sioread(dev, uio, flag) 1513 struct cdev *dev; 1514 struct uio *uio; 1515 int flag; 1516{ 1517 struct com_s *com; 1518 1519 com = dev->si_drv1; 1520 if (com == NULL || com->gone) 1521 return (ENODEV); 1522 return (ttyld_read(com->tp, uio, flag)); 1523} 1524 1525static int 1526siowrite(dev, uio, flag) 1527 struct cdev *dev; 1528 struct uio *uio; 1529 int flag; 1530{ 1531 int mynor; 1532 struct com_s *com; 1533 int unit; 1534 1535 mynor = minor(dev); 1536 1537 unit = MINOR_TO_UNIT(mynor); 1538 com = com_addr(unit); 1539 if (com == NULL || com->gone) 1540 return (ENODEV); 1541 /* 1542 * (XXX) We disallow virtual consoles if the physical console is 1543 * a serial port. This is in case there is a display attached that 1544 * is not the console. In that situation we don't need/want the X 1545 * server taking over the console. 1546 */ 1547 if (constty != NULL && unit == comconsole) 1548 constty = NULL; 1549 return (ttyld_write(com->tp, uio, flag)); 1550} 1551 1552static void 1553siobusycheck(chan) 1554 void *chan; 1555{ 1556 struct com_s *com; 1557 int s; 1558 1559 com = (struct com_s *)chan; 1560 1561 /* 1562 * Clear TS_BUSY if low-level output is complete. 1563 * spl locking is sufficient because siointr1() does not set CS_BUSY. 1564 * If siointr1() clears CS_BUSY after we look at it, then we'll get 1565 * called again. Reading the line status port outside of siointr1() 1566 * is safe because CS_BUSY is clear so there are no output interrupts 1567 * to lose. 1568 */ 1569 s = spltty(); 1570 if (com->state & CS_BUSY) 1571 com->extra_state &= ~CSE_BUSYCHECK; /* False alarm. */ 1572 else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY)) 1573 == (LSR_TSRE | LSR_TXRDY)) { 1574 com->tp->t_state &= ~TS_BUSY; 1575 ttwwakeup(com->tp); 1576 com->extra_state &= ~CSE_BUSYCHECK; 1577 } else 1578 timeout(siobusycheck, com, hz / 100); 1579 splx(s); 1580} 1581 1582static u_int 1583siodivisor(rclk, speed) 1584 u_long rclk; 1585 speed_t speed; 1586{ 1587 long actual_speed; 1588 u_int divisor; 1589 int error; 1590 1591 if (speed == 0) 1592 return (0); 1593#if UINT_MAX > (ULONG_MAX - 1) / 8 1594 if (speed > (ULONG_MAX - 1) / 8) 1595 return (0); 1596#endif 1597 divisor = (rclk / (8UL * speed) + 1) / 2; 1598 if (divisor == 0 || divisor >= 65536) 1599 return (0); 1600 actual_speed = rclk / (16UL * divisor); 1601 1602 /* 10 times error in percent: */ 1603 error = ((actual_speed - (long)speed) * 2000 / (long)speed + 1) / 2; 1604 1605 /* 3.0% maximum error tolerance: */ 1606 if (error < -30 || error > 30) 1607 return (0); 1608 1609 return (divisor); 1610} 1611 1612static void 1613siodtrwakeup(chan) 1614 void *chan; 1615{ 1616 struct com_s *com; 1617 1618 com = (struct com_s *)chan; 1619 com->state &= ~CS_DTR_OFF; 1620 wakeup(&com->dtr_wait); 1621} 1622 1623/* 1624 * Call this function with the sio_lock mutex held. It will return with the 1625 * lock still held. 1626 */ 1627static void 1628sioinput(com) 1629 struct com_s *com; 1630{ 1631 u_char *buf; 1632 int incc; 1633 u_char line_status; 1634 int recv_data; 1635 struct tty *tp; 1636 1637 buf = com->ibuf; 1638 tp = com->tp; 1639 if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) { 1640 com_events -= (com->iptr - com->ibuf); 1641 com->iptr = com->ibuf; 1642 return; 1643 } 1644 if (tp->t_state & TS_CAN_BYPASS_L_RINT) { 1645 /* 1646 * Avoid the grotesquely inefficient lineswitch routine 1647 * (ttyinput) in "raw" mode. It usually takes about 450 1648 * instructions (that's without canonical processing or echo!). 1649 * slinput is reasonably fast (usually 40 instructions plus 1650 * call overhead). 1651 */ 1652 do { 1653 /* 1654 * This may look odd, but it is using save-and-enable 1655 * semantics instead of the save-and-disable semantics 1656 * that are used everywhere else. 1657 */ 1658 mtx_unlock_spin(&sio_lock); 1659 incc = com->iptr - buf; 1660 if (tp->t_rawq.c_cc + incc > tp->t_ihiwat 1661 && (com->state & CS_RTS_IFLOW 1662 || tp->t_iflag & IXOFF) 1663 && !(tp->t_state & TS_TBLOCK)) 1664 ttyblock(tp); 1665 com->delta_error_counts[CE_TTY_BUF_OVERFLOW] 1666 += b_to_q((char *)buf, incc, &tp->t_rawq); 1667 buf += incc; 1668 tk_nin += incc; 1669 tk_rawcc += incc; 1670 tp->t_rawcc += incc; 1671 ttwakeup(tp); 1672 if (tp->t_state & TS_TTSTOP 1673 && (tp->t_iflag & IXANY 1674 || tp->t_cc[VSTART] == tp->t_cc[VSTOP])) { 1675 tp->t_state &= ~TS_TTSTOP; 1676 tp->t_lflag &= ~FLUSHO; 1677 comstart(tp); 1678 } 1679 mtx_lock_spin(&sio_lock); 1680 } while (buf < com->iptr); 1681 } else { 1682 do { 1683 /* 1684 * This may look odd, but it is using save-and-enable 1685 * semantics instead of the save-and-disable semantics 1686 * that are used everywhere else. 1687 */ 1688 mtx_unlock_spin(&sio_lock); 1689 line_status = buf[com->ierroff]; 1690 recv_data = *buf++; 1691 if (line_status 1692 & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) { 1693 if (line_status & LSR_BI) 1694 recv_data |= TTY_BI; 1695 if (line_status & LSR_FE) 1696 recv_data |= TTY_FE; 1697 if (line_status & LSR_OE) 1698 recv_data |= TTY_OE; 1699 if (line_status & LSR_PE) 1700 recv_data |= TTY_PE; 1701 } 1702 ttyld_rint(tp, recv_data); 1703 mtx_lock_spin(&sio_lock); 1704 } while (buf < com->iptr); 1705 } 1706 com_events -= (com->iptr - com->ibuf); 1707 com->iptr = com->ibuf; 1708 1709 /* 1710 * There is now room for another low-level buffer full of input, 1711 * so enable RTS if it is now disabled and there is room in the 1712 * high-level buffer. 1713 */ 1714 if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) && 1715 !(tp->t_state & TS_TBLOCK)) 1716 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 1717} 1718 1719static void 1720siointr(arg) 1721 void *arg; 1722{ 1723 struct com_s *com; 1724 1725#ifndef COM_MULTIPORT 1726 com = (struct com_s *)arg; 1727 1728 mtx_lock_spin(&sio_lock); 1729 siointr1(com); 1730 mtx_unlock_spin(&sio_lock); 1731#else /* COM_MULTIPORT */ 1732 bool_t possibly_more_intrs; 1733 int unit; 1734 1735 /* 1736 * Loop until there is no activity on any port. This is necessary 1737 * to get an interrupt edge more than to avoid another interrupt. 1738 * If the IRQ signal is just an OR of the IRQ signals from several 1739 * devices, then the edge from one may be lost because another is 1740 * on. 1741 */ 1742 mtx_lock_spin(&sio_lock); 1743 do { 1744 possibly_more_intrs = FALSE; 1745 for (unit = 0; unit < sio_numunits; ++unit) { 1746 com = com_addr(unit); 1747 /* 1748 * XXX COM_LOCK(); 1749 * would it work here, or be counter-productive? 1750 */ 1751 if (com != NULL 1752 && !com->gone 1753 && (inb(com->int_id_port) & IIR_IMASK) 1754 != IIR_NOPEND) { 1755 siointr1(com); 1756 possibly_more_intrs = TRUE; 1757 } 1758 /* XXX COM_UNLOCK(); */ 1759 } 1760 } while (possibly_more_intrs); 1761 mtx_unlock_spin(&sio_lock); 1762#endif /* COM_MULTIPORT */ 1763} 1764 1765static struct timespec siots[8]; 1766static int siotso; 1767static int volatile siotsunit = -1; 1768 1769static int 1770sysctl_siots(SYSCTL_HANDLER_ARGS) 1771{ 1772 char buf[128]; 1773 long long delta; 1774 size_t len; 1775 int error, i, tso; 1776 1777 for (i = 1, tso = siotso; i < tso; i++) { 1778 delta = (long long)(siots[i].tv_sec - siots[i - 1].tv_sec) * 1779 1000000000 + 1780 (siots[i].tv_nsec - siots[i - 1].tv_nsec); 1781 len = sprintf(buf, "%lld\n", delta); 1782 if (delta >= 110000) 1783 len += sprintf(buf + len - 1, ": *** %ld.%09ld\n", 1784 (long)siots[i].tv_sec, siots[i].tv_nsec) - 1; 1785 if (i == tso - 1) 1786 buf[len - 1] = '\0'; 1787 error = SYSCTL_OUT(req, buf, len); 1788 if (error != 0) 1789 return (error); 1790 uio_yield(); 1791 } 1792 return (0); 1793} 1794 1795SYSCTL_PROC(_machdep, OID_AUTO, siots, CTLTYPE_STRING | CTLFLAG_RD, 1796 0, 0, sysctl_siots, "A", "sio timestamps"); 1797 1798static void 1799siointr1(com) 1800 struct com_s *com; 1801{ 1802 u_char int_ctl; 1803 u_char int_ctl_new; 1804 u_char line_status; 1805 u_char modem_status; 1806 u_char *ioptr; 1807 u_char recv_data; 1808 1809 if (COM_IIR_TXRDYBUG(com->flags)) { 1810 int_ctl = inb(com->int_ctl_port); 1811 int_ctl_new = int_ctl; 1812 } else { 1813 int_ctl = 0; 1814 int_ctl_new = 0; 1815 } 1816 1817 while (!com->gone) { 1818 if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) { 1819 modem_status = inb(com->modem_status_port); 1820 if ((modem_status ^ com->last_modem_status) & 1821 com->pps_bit) { 1822 pps_capture(&com->pps); 1823 pps_event(&com->pps, 1824 (modem_status & com->pps_bit) ? 1825 PPS_CAPTUREASSERT : PPS_CAPTURECLEAR); 1826 } 1827 } 1828 line_status = inb(com->line_status_port); 1829 1830 /* input event? (check first to help avoid overruns) */ 1831 while (line_status & LSR_RCV_MASK) { 1832 /* break/unnattached error bits or real input? */ 1833 if (!(line_status & LSR_RXRDY)) 1834 recv_data = 0; 1835 else 1836 recv_data = inb(com->data_port); 1837#ifdef DDB 1838#ifdef ALT_BREAK_TO_DEBUGGER 1839 if (com->unit == comconsole && 1840 db_alt_break(recv_data, &com->alt_brk_state) != 0) 1841 breakpoint(); 1842#endif /* ALT_BREAK_TO_DEBUGGER */ 1843#endif /* DDB */ 1844 if (line_status & (LSR_BI | LSR_FE | LSR_PE)) { 1845 /* 1846 * Don't store BI if IGNBRK or FE/PE if IGNPAR. 1847 * Otherwise, push the work to a higher level 1848 * (to handle PARMRK) if we're bypassing. 1849 * Otherwise, convert BI/FE and PE+INPCK to 0. 1850 * 1851 * This makes bypassing work right in the 1852 * usual "raw" case (IGNBRK set, and IGNPAR 1853 * and INPCK clear). 1854 * 1855 * Note: BI together with FE/PE means just BI. 1856 */ 1857 if (line_status & LSR_BI) { 1858#if defined(DDB) && defined(BREAK_TO_DEBUGGER) 1859 if (com->unit == comconsole) { 1860 breakpoint(); 1861 goto cont; 1862 } 1863#endif 1864 if (com->tp == NULL 1865 || com->tp->t_iflag & IGNBRK) 1866 goto cont; 1867 } else { 1868 if (com->tp == NULL 1869 || com->tp->t_iflag & IGNPAR) 1870 goto cont; 1871 } 1872 if (com->tp->t_state & TS_CAN_BYPASS_L_RINT 1873 && (line_status & (LSR_BI | LSR_FE) 1874 || com->tp->t_iflag & INPCK)) 1875 recv_data = 0; 1876 } 1877 ++com->bytes_in; 1878 if (com->hotchar != 0 && recv_data == com->hotchar) 1879 swi_sched(sio_fast_ih, 0); 1880 ioptr = com->iptr; 1881 if (ioptr >= com->ibufend) 1882 CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW); 1883 else { 1884 if (com->do_timestamp) 1885 microtime(&com->timestamp); 1886 ++com_events; 1887 swi_sched(sio_slow_ih, SWI_DELAY); 1888#if 0 /* for testing input latency vs efficiency */ 1889if (com->iptr - com->ibuf == 8) 1890 swi_sched(sio_fast_ih, 0); 1891#endif 1892 ioptr[0] = recv_data; 1893 ioptr[com->ierroff] = line_status; 1894 com->iptr = ++ioptr; 1895 if (ioptr == com->ihighwater 1896 && com->state & CS_RTS_IFLOW) 1897 outb(com->modem_ctl_port, 1898 com->mcr_image &= ~MCR_RTS); 1899 if (line_status & LSR_OE) 1900 CE_RECORD(com, CE_OVERRUN); 1901 } 1902cont: 1903 if (line_status & LSR_TXRDY 1904 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) 1905 goto txrdy; 1906 1907 /* 1908 * "& 0x7F" is to avoid the gcc-1.40 generating a slow 1909 * jump from the top of the loop to here 1910 */ 1911 line_status = inb(com->line_status_port) & 0x7F; 1912 } 1913 1914 /* modem status change? (always check before doing output) */ 1915 modem_status = inb(com->modem_status_port); 1916 if (modem_status != com->last_modem_status) { 1917 if (com->do_dcd_timestamp 1918 && !(com->last_modem_status & MSR_DCD) 1919 && modem_status & MSR_DCD) 1920 microtime(&com->dcd_timestamp); 1921 1922 /* 1923 * Schedule high level to handle DCD changes. Note 1924 * that we don't use the delta bits anywhere. Some 1925 * UARTs mess them up, and it's easy to remember the 1926 * previous bits and calculate the delta. 1927 */ 1928 com->last_modem_status = modem_status; 1929 if (!(com->state & CS_CHECKMSR)) { 1930 com_events += LOTS_OF_EVENTS; 1931 com->state |= CS_CHECKMSR; 1932 swi_sched(sio_fast_ih, 0); 1933 } 1934 1935 /* handle CTS change immediately for crisp flow ctl */ 1936 if (com->state & CS_CTS_OFLOW) { 1937 if (modem_status & MSR_CTS) 1938 com->state |= CS_ODEVREADY; 1939 else 1940 com->state &= ~CS_ODEVREADY; 1941 } 1942 } 1943 1944txrdy: 1945 /* output queued and everything ready? */ 1946 if (line_status & LSR_TXRDY 1947 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) { 1948 ioptr = com->obufq.l_head; 1949 if (com->tx_fifo_size > 1 && com->unit != siotsunit) { 1950 u_int ocount; 1951 1952 ocount = com->obufq.l_tail - ioptr; 1953 if (ocount > com->tx_fifo_size) 1954 ocount = com->tx_fifo_size; 1955 com->bytes_out += ocount; 1956 do 1957 outb(com->data_port, *ioptr++); 1958 while (--ocount != 0); 1959 } else { 1960 outb(com->data_port, *ioptr++); 1961 ++com->bytes_out; 1962 if (com->unit == siotsunit 1963 && siotso < sizeof siots / sizeof siots[0]) 1964 nanouptime(&siots[siotso++]); 1965 } 1966 com->obufq.l_head = ioptr; 1967 if (COM_IIR_TXRDYBUG(com->flags)) 1968 int_ctl_new = int_ctl | IER_ETXRDY; 1969 if (ioptr >= com->obufq.l_tail) { 1970 struct lbq *qp; 1971 1972 qp = com->obufq.l_next; 1973 qp->l_queued = FALSE; 1974 qp = qp->l_next; 1975 if (qp != NULL) { 1976 com->obufq.l_head = qp->l_head; 1977 com->obufq.l_tail = qp->l_tail; 1978 com->obufq.l_next = qp; 1979 } else { 1980 /* output just completed */ 1981 if (COM_IIR_TXRDYBUG(com->flags)) 1982 int_ctl_new = int_ctl 1983 & ~IER_ETXRDY; 1984 com->state &= ~CS_BUSY; 1985 } 1986 if (!(com->state & CS_ODONE)) { 1987 com_events += LOTS_OF_EVENTS; 1988 com->state |= CS_ODONE; 1989 /* handle at high level ASAP */ 1990 swi_sched(sio_fast_ih, 0); 1991 } 1992 } 1993 if (COM_IIR_TXRDYBUG(com->flags) 1994 && int_ctl != int_ctl_new) 1995 outb(com->int_ctl_port, int_ctl_new); 1996 } 1997 1998 /* finished? */ 1999#ifndef COM_MULTIPORT 2000 if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND) 2001#endif /* COM_MULTIPORT */ 2002 return; 2003 } 2004} 2005 2006static int 2007siocioctl(dev, cmd, data, flag, td) 2008 struct cdev *dev; 2009 u_long cmd; 2010 caddr_t data; 2011 int flag; 2012 struct thread *td; 2013{ 2014 struct com_s *com; 2015 int error; 2016 int mynor; 2017 struct termios *ct; 2018 2019 mynor = minor(dev); 2020 com = com_addr(MINOR_TO_UNIT(mynor)); 2021 if (com == NULL || com->gone) 2022 return (ENODEV); 2023 2024 switch (mynor & CONTROL_MASK) { 2025 case CONTROL_INIT_STATE: 2026 ct = mynor & CALLOUT_MASK ? &com->it_out : &com->it_in; 2027 break; 2028 case CONTROL_LOCK_STATE: 2029 ct = mynor & CALLOUT_MASK ? &com->lt_out : &com->lt_in; 2030 break; 2031 default: 2032 return (ENODEV); /* /dev/nodev */ 2033 } 2034 switch (cmd) { 2035 case TIOCSETA: 2036 error = suser(td); 2037 if (error != 0) 2038 return (error); 2039 *ct = *(struct termios *)data; 2040 return (0); 2041 case TIOCGETA: 2042 *(struct termios *)data = *ct; 2043 return (0); 2044 case TIOCGETD: 2045 *(int *)data = TTYDISC; 2046 return (0); 2047 case TIOCGWINSZ: 2048 bzero(data, sizeof(struct winsize)); 2049 return (0); 2050 default: 2051 return (ENOTTY); 2052 } 2053} 2054 2055static int 2056sioioctl(dev, cmd, data, flag, td) 2057 struct cdev *dev; 2058 u_long cmd; 2059 caddr_t data; 2060 int flag; 2061 struct thread *td; 2062{ 2063 struct com_s *com; 2064 int error; 2065 int mynor; 2066 int s; 2067 struct tty *tp; 2068#if defined(COMPAT_43) 2069 u_long oldcmd; 2070 struct termios term; 2071#endif 2072 2073 mynor = minor(dev); 2074 com = dev->si_drv1; 2075 if (com == NULL || com->gone) 2076 return (ENODEV); 2077 tp = com->tp; 2078#if defined(COMPAT_43) 2079 term = tp->t_termios; 2080 oldcmd = cmd; 2081 error = ttsetcompat(tp, &cmd, data, &term); 2082 if (error != 0) 2083 return (error); 2084 if (cmd != oldcmd) 2085 data = (caddr_t)&term; 2086#endif 2087 if (cmd == TIOCSETA || cmd == TIOCSETAW || cmd == TIOCSETAF) { 2088 int cc; 2089 struct termios *dt = (struct termios *)data; 2090 struct termios *lt = mynor & CALLOUT_MASK 2091 ? &com->lt_out : &com->lt_in; 2092 2093 dt->c_iflag = (tp->t_iflag & lt->c_iflag) 2094 | (dt->c_iflag & ~lt->c_iflag); 2095 dt->c_oflag = (tp->t_oflag & lt->c_oflag) 2096 | (dt->c_oflag & ~lt->c_oflag); 2097 dt->c_cflag = (tp->t_cflag & lt->c_cflag) 2098 | (dt->c_cflag & ~lt->c_cflag); 2099 dt->c_lflag = (tp->t_lflag & lt->c_lflag) 2100 | (dt->c_lflag & ~lt->c_lflag); 2101 for (cc = 0; cc < NCCS; ++cc) 2102 if (lt->c_cc[cc] != 0) 2103 dt->c_cc[cc] = tp->t_cc[cc]; 2104 if (lt->c_ispeed != 0) 2105 dt->c_ispeed = tp->t_ispeed; 2106 if (lt->c_ospeed != 0) 2107 dt->c_ospeed = tp->t_ospeed; 2108 } 2109 error = ttyioctl(dev, cmd, data, flag, td); 2110 com->hotchar = ttyldoptim(tp); 2111 if (error != ENOTTY) 2112 return (error); 2113 s = spltty(); 2114 switch (cmd) { 2115 case TIOCSBRK: 2116 sio_setreg(com, com_cfcr, com->cfcr_image |= CFCR_SBREAK); 2117 break; 2118 case TIOCCBRK: 2119 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 2120 break; 2121 case TIOCSDTR: 2122 (void)commctl(com, TIOCM_DTR, DMBIS); 2123 break; 2124 case TIOCCDTR: 2125 (void)commctl(com, TIOCM_DTR, DMBIC); 2126 break; 2127 /* 2128 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The 2129 * changes get undone on the next call to comparam(). 2130 */ 2131 case TIOCMSET: 2132 (void)commctl(com, *(int *)data, DMSET); 2133 break; 2134 case TIOCMBIS: 2135 (void)commctl(com, *(int *)data, DMBIS); 2136 break; 2137 case TIOCMBIC: 2138 (void)commctl(com, *(int *)data, DMBIC); 2139 break; 2140 case TIOCMGET: 2141 *(int *)data = commctl(com, 0, DMGET); 2142 break; 2143 case TIOCMSDTRWAIT: 2144 /* must be root since the wait applies to following logins */ 2145 error = suser(td); 2146 if (error != 0) { 2147 splx(s); 2148 return (error); 2149 } 2150 com->dtr_wait = *(int *)data * hz / 100; 2151 break; 2152 case TIOCMGDTRWAIT: 2153 *(int *)data = com->dtr_wait * 100 / hz; 2154 break; 2155 case TIOCTIMESTAMP: 2156 com->do_timestamp = TRUE; 2157 *(struct timeval *)data = com->timestamp; 2158 break; 2159 case TIOCDCDTIMESTAMP: 2160 com->do_dcd_timestamp = TRUE; 2161 *(struct timeval *)data = com->dcd_timestamp; 2162 break; 2163 default: 2164 splx(s); 2165 error = pps_ioctl(cmd, data, &com->pps); 2166 if (error == ENODEV) 2167 error = ENOTTY; 2168 return (error); 2169 } 2170 splx(s); 2171 return (0); 2172} 2173 2174/* software interrupt handler for SWI_TTY */ 2175static void 2176siopoll(void *dummy) 2177{ 2178 int unit; 2179 2180 if (com_events == 0) 2181 return; 2182repeat: 2183 for (unit = 0; unit < sio_numunits; ++unit) { 2184 struct com_s *com; 2185 int incc; 2186 struct tty *tp; 2187 2188 com = com_addr(unit); 2189 if (com == NULL) 2190 continue; 2191 tp = com->tp; 2192 if (tp == NULL || com->gone) { 2193 /* 2194 * Discard any events related to never-opened or 2195 * going-away devices. 2196 */ 2197 mtx_lock_spin(&sio_lock); 2198 incc = com->iptr - com->ibuf; 2199 com->iptr = com->ibuf; 2200 if (com->state & CS_CHECKMSR) { 2201 incc += LOTS_OF_EVENTS; 2202 com->state &= ~CS_CHECKMSR; 2203 } 2204 com_events -= incc; 2205 mtx_unlock_spin(&sio_lock); 2206 continue; 2207 } 2208 if (com->iptr != com->ibuf) { 2209 mtx_lock_spin(&sio_lock); 2210 sioinput(com); 2211 mtx_unlock_spin(&sio_lock); 2212 } 2213 if (com->state & CS_CHECKMSR) { 2214 u_char delta_modem_status; 2215 2216 mtx_lock_spin(&sio_lock); 2217 delta_modem_status = com->last_modem_status 2218 ^ com->prev_modem_status; 2219 com->prev_modem_status = com->last_modem_status; 2220 com_events -= LOTS_OF_EVENTS; 2221 com->state &= ~CS_CHECKMSR; 2222 mtx_unlock_spin(&sio_lock); 2223 if (delta_modem_status & MSR_DCD) 2224 ttyld_modem(tp, 2225 com->prev_modem_status & MSR_DCD); 2226 } 2227 if (com->state & CS_ODONE) { 2228 mtx_lock_spin(&sio_lock); 2229 com_events -= LOTS_OF_EVENTS; 2230 com->state &= ~CS_ODONE; 2231 mtx_unlock_spin(&sio_lock); 2232 if (!(com->state & CS_BUSY) 2233 && !(com->extra_state & CSE_BUSYCHECK)) { 2234 timeout(siobusycheck, com, hz / 100); 2235 com->extra_state |= CSE_BUSYCHECK; 2236 } 2237 ttyld_start(tp); 2238 } 2239 if (com_events == 0) 2240 break; 2241 } 2242 if (com_events >= LOTS_OF_EVENTS) 2243 goto repeat; 2244} 2245 2246static int 2247comparam(tp, t) 2248 struct tty *tp; 2249 struct termios *t; 2250{ 2251 u_int cfcr; 2252 int cflag; 2253 struct com_s *com; 2254 u_int divisor; 2255 u_char dlbh; 2256 u_char dlbl; 2257 u_char efr_flowbits; 2258 int s; 2259 int unit; 2260 2261 unit = DEV_TO_UNIT(tp->t_dev); 2262 com = com_addr(unit); 2263 if (com == NULL) 2264 return (ENODEV); 2265 2266 /* check requested parameters */ 2267 if (t->c_ispeed != (t->c_ospeed != 0 ? t->c_ospeed : tp->t_ospeed)) 2268 return (EINVAL); 2269 divisor = siodivisor(com->rclk, t->c_ispeed); 2270 if (divisor == 0) 2271 return (EINVAL); 2272 2273 /* parameters are OK, convert them to the com struct and the device */ 2274 s = spltty(); 2275 if (t->c_ospeed == 0) 2276 (void)commctl(com, TIOCM_DTR, DMBIC); /* hang up line */ 2277 else 2278 (void)commctl(com, TIOCM_DTR, DMBIS); 2279 cflag = t->c_cflag; 2280 switch (cflag & CSIZE) { 2281 case CS5: 2282 cfcr = CFCR_5BITS; 2283 break; 2284 case CS6: 2285 cfcr = CFCR_6BITS; 2286 break; 2287 case CS7: 2288 cfcr = CFCR_7BITS; 2289 break; 2290 default: 2291 cfcr = CFCR_8BITS; 2292 break; 2293 } 2294 if (cflag & PARENB) { 2295 cfcr |= CFCR_PENAB; 2296 if (!(cflag & PARODD)) 2297 cfcr |= CFCR_PEVEN; 2298 } 2299 if (cflag & CSTOPB) 2300 cfcr |= CFCR_STOPB; 2301 2302 if (com->hasfifo) { 2303 /* 2304 * Use a fifo trigger level low enough so that the input 2305 * latency from the fifo is less than about 16 msec and 2306 * the total latency is less than about 30 msec. These 2307 * latencies are reasonable for humans. Serial comms 2308 * protocols shouldn't expect anything better since modem 2309 * latencies are larger. 2310 * 2311 * The fifo trigger level cannot be set at RX_HIGH for high 2312 * speed connections without further work on reducing 2313 * interrupt disablement times in other parts of the system, 2314 * without producing silo overflow errors. 2315 */ 2316 com->fifo_image = com->unit == siotsunit ? 0 2317 : t->c_ispeed <= 4800 2318 ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_MEDH; 2319#ifdef COM_ESP 2320 /* 2321 * The Hayes ESP card needs the fifo DMA mode bit set 2322 * in compatibility mode. If not, it will interrupt 2323 * for each character received. 2324 */ 2325 if (com->esp) 2326 com->fifo_image |= FIFO_DMA_MODE; 2327#endif 2328 sio_setreg(com, com_fifo, com->fifo_image); 2329 } 2330 2331 /* 2332 * This returns with interrupts disabled so that we can complete 2333 * the speed change atomically. Keeping interrupts disabled is 2334 * especially important while com_data is hidden. 2335 */ 2336 (void) siosetwater(com, t->c_ispeed); 2337 2338 sio_setreg(com, com_cfcr, cfcr | CFCR_DLAB); 2339 /* 2340 * Only set the divisor registers if they would change, since on 2341 * some 16550 incompatibles (UMC8669F), setting them while input 2342 * is arriving loses sync until data stops arriving. 2343 */ 2344 dlbl = divisor & 0xFF; 2345 if (sio_getreg(com, com_dlbl) != dlbl) 2346 sio_setreg(com, com_dlbl, dlbl); 2347 dlbh = divisor >> 8; 2348 if (sio_getreg(com, com_dlbh) != dlbh) 2349 sio_setreg(com, com_dlbh, dlbh); 2350 2351 efr_flowbits = 0; 2352 2353 if (cflag & CRTS_IFLOW) { 2354 com->state |= CS_RTS_IFLOW; 2355 efr_flowbits |= EFR_AUTORTS; 2356 /* 2357 * If CS_RTS_IFLOW just changed from off to on, the change 2358 * needs to be propagated to MCR_RTS. This isn't urgent, 2359 * so do it later by calling comstart() instead of repeating 2360 * a lot of code from comstart() here. 2361 */ 2362 } else if (com->state & CS_RTS_IFLOW) { 2363 com->state &= ~CS_RTS_IFLOW; 2364 /* 2365 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS 2366 * on here, since comstart() won't do it later. 2367 */ 2368 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2369 } 2370 2371 /* 2372 * Set up state to handle output flow control. 2373 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level? 2374 * Now has 10+ msec latency, while CTS flow has 50- usec latency. 2375 */ 2376 com->state |= CS_ODEVREADY; 2377 com->state &= ~CS_CTS_OFLOW; 2378 if (cflag & CCTS_OFLOW) { 2379 com->state |= CS_CTS_OFLOW; 2380 efr_flowbits |= EFR_AUTOCTS; 2381 if (!(com->last_modem_status & MSR_CTS)) 2382 com->state &= ~CS_ODEVREADY; 2383 } 2384 2385 if (com->st16650a) { 2386 sio_setreg(com, com_lcr, LCR_EFR_ENABLE); 2387 sio_setreg(com, com_efr, 2388 (sio_getreg(com, com_efr) 2389 & ~(EFR_AUTOCTS | EFR_AUTORTS)) | efr_flowbits); 2390 } 2391 sio_setreg(com, com_cfcr, com->cfcr_image = cfcr); 2392 2393 /* XXX shouldn't call functions while intrs are disabled. */ 2394 com->hotchar = ttyldoptim(tp); 2395 2396 mtx_unlock_spin(&sio_lock); 2397 splx(s); 2398 comstart(tp); 2399 if (com->ibufold != NULL) { 2400 free(com->ibufold, M_DEVBUF); 2401 com->ibufold = NULL; 2402 } 2403 return (0); 2404} 2405 2406/* 2407 * This function must be called with the sio_lock mutex released and will 2408 * return with it obtained. 2409 */ 2410static int 2411siosetwater(com, speed) 2412 struct com_s *com; 2413 speed_t speed; 2414{ 2415 int cp4ticks; 2416 u_char *ibuf; 2417 int ibufsize; 2418 struct tty *tp; 2419 2420 /* 2421 * Make the buffer size large enough to handle a softtty interrupt 2422 * latency of about 2 ticks without loss of throughput or data 2423 * (about 3 ticks if input flow control is not used or not honoured, 2424 * but a bit less for CS5-CS7 modes). 2425 */ 2426 cp4ticks = speed / 10 / hz * 4; 2427 for (ibufsize = 128; ibufsize < cp4ticks;) 2428 ibufsize <<= 1; 2429 if (ibufsize == com->ibufsize) { 2430 mtx_lock_spin(&sio_lock); 2431 return (0); 2432 } 2433 2434 /* 2435 * Allocate input buffer. The extra factor of 2 in the size is 2436 * to allow for an error byte for each input byte. 2437 */ 2438 ibuf = malloc(2 * ibufsize, M_DEVBUF, M_NOWAIT); 2439 if (ibuf == NULL) { 2440 mtx_lock_spin(&sio_lock); 2441 return (ENOMEM); 2442 } 2443 2444 /* Initialize non-critical variables. */ 2445 com->ibufold = com->ibuf; 2446 com->ibufsize = ibufsize; 2447 tp = com->tp; 2448 if (tp != NULL) { 2449 tp->t_ififosize = 2 * ibufsize; 2450 tp->t_ispeedwat = (speed_t)-1; 2451 tp->t_ospeedwat = (speed_t)-1; 2452 } 2453 2454 /* 2455 * Read current input buffer, if any. Continue with interrupts 2456 * disabled. 2457 */ 2458 mtx_lock_spin(&sio_lock); 2459 if (com->iptr != com->ibuf) 2460 sioinput(com); 2461 2462 /*- 2463 * Initialize critical variables, including input buffer watermarks. 2464 * The external device is asked to stop sending when the buffer 2465 * exactly reaches high water, or when the high level requests it. 2466 * The high level is notified immediately (rather than at a later 2467 * clock tick) when this watermark is reached. 2468 * The buffer size is chosen so the watermark should almost never 2469 * be reached. 2470 * The low watermark is invisibly 0 since the buffer is always 2471 * emptied all at once. 2472 */ 2473 com->iptr = com->ibuf = ibuf; 2474 com->ibufend = ibuf + ibufsize; 2475 com->ierroff = ibufsize; 2476 com->ihighwater = ibuf + 3 * ibufsize / 4; 2477 return (0); 2478} 2479 2480static void 2481comstart(tp) 2482 struct tty *tp; 2483{ 2484 struct com_s *com; 2485 int s; 2486 int unit; 2487 2488 unit = DEV_TO_UNIT(tp->t_dev); 2489 com = com_addr(unit); 2490 if (com == NULL) 2491 return; 2492 s = spltty(); 2493 mtx_lock_spin(&sio_lock); 2494 if (tp->t_state & TS_TTSTOP) 2495 com->state &= ~CS_TTGO; 2496 else 2497 com->state |= CS_TTGO; 2498 if (tp->t_state & TS_TBLOCK) { 2499 if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW) 2500 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS); 2501 } else { 2502 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater 2503 && com->state & CS_RTS_IFLOW) 2504 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2505 } 2506 mtx_unlock_spin(&sio_lock); 2507 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) { 2508 ttwwakeup(tp); 2509 splx(s); 2510 return; 2511 } 2512 if (tp->t_outq.c_cc != 0) { 2513 struct lbq *qp; 2514 struct lbq *next; 2515 2516 if (!com->obufs[0].l_queued) { 2517 com->obufs[0].l_tail 2518 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1, 2519 sizeof com->obuf1); 2520 com->obufs[0].l_next = NULL; 2521 com->obufs[0].l_queued = TRUE; 2522 mtx_lock_spin(&sio_lock); 2523 if (com->state & CS_BUSY) { 2524 qp = com->obufq.l_next; 2525 while ((next = qp->l_next) != NULL) 2526 qp = next; 2527 qp->l_next = &com->obufs[0]; 2528 } else { 2529 com->obufq.l_head = com->obufs[0].l_head; 2530 com->obufq.l_tail = com->obufs[0].l_tail; 2531 com->obufq.l_next = &com->obufs[0]; 2532 com->state |= CS_BUSY; 2533 } 2534 mtx_unlock_spin(&sio_lock); 2535 } 2536 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) { 2537 com->obufs[1].l_tail 2538 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2, 2539 sizeof com->obuf2); 2540 com->obufs[1].l_next = NULL; 2541 com->obufs[1].l_queued = TRUE; 2542 mtx_lock_spin(&sio_lock); 2543 if (com->state & CS_BUSY) { 2544 qp = com->obufq.l_next; 2545 while ((next = qp->l_next) != NULL) 2546 qp = next; 2547 qp->l_next = &com->obufs[1]; 2548 } else { 2549 com->obufq.l_head = com->obufs[1].l_head; 2550 com->obufq.l_tail = com->obufs[1].l_tail; 2551 com->obufq.l_next = &com->obufs[1]; 2552 com->state |= CS_BUSY; 2553 } 2554 mtx_unlock_spin(&sio_lock); 2555 } 2556 tp->t_state |= TS_BUSY; 2557 } 2558 mtx_lock_spin(&sio_lock); 2559 if (com->state >= (CS_BUSY | CS_TTGO)) 2560 siointr1(com); /* fake interrupt to start output */ 2561 mtx_unlock_spin(&sio_lock); 2562 ttwwakeup(tp); 2563 splx(s); 2564} 2565 2566static void 2567comstop(tp, rw) 2568 struct tty *tp; 2569 int rw; 2570{ 2571 struct com_s *com; 2572 2573 com = com_addr(DEV_TO_UNIT(tp->t_dev)); 2574 if (com == NULL || com->gone) 2575 return; 2576 mtx_lock_spin(&sio_lock); 2577 if (rw & FWRITE) { 2578 if (com->hasfifo) 2579#ifdef COM_ESP 2580 /* XXX avoid h/w bug. */ 2581 if (!com->esp) 2582#endif 2583 sio_setreg(com, com_fifo, 2584 FIFO_XMT_RST | com->fifo_image); 2585 com->obufs[0].l_queued = FALSE; 2586 com->obufs[1].l_queued = FALSE; 2587 if (com->state & CS_ODONE) 2588 com_events -= LOTS_OF_EVENTS; 2589 com->state &= ~(CS_ODONE | CS_BUSY); 2590 com->tp->t_state &= ~TS_BUSY; 2591 } 2592 if (rw & FREAD) { 2593 if (com->hasfifo) 2594#ifdef COM_ESP 2595 /* XXX avoid h/w bug. */ 2596 if (!com->esp) 2597#endif 2598 sio_setreg(com, com_fifo, 2599 FIFO_RCV_RST | com->fifo_image); 2600 com_events -= (com->iptr - com->ibuf); 2601 com->iptr = com->ibuf; 2602 } 2603 mtx_unlock_spin(&sio_lock); 2604 comstart(tp); 2605} 2606 2607static int 2608commctl(com, bits, how) 2609 struct com_s *com; 2610 int bits; 2611 int how; 2612{ 2613 int mcr; 2614 int msr; 2615 2616 if (how == DMGET) { 2617 bits = TIOCM_LE; /* XXX - always enabled while open */ 2618 mcr = com->mcr_image; 2619 if (mcr & MCR_DTR) 2620 bits |= TIOCM_DTR; 2621 if (mcr & MCR_RTS) 2622 bits |= TIOCM_RTS; 2623 msr = com->prev_modem_status; 2624 if (msr & MSR_CTS) 2625 bits |= TIOCM_CTS; 2626 if (msr & MSR_DCD) 2627 bits |= TIOCM_CD; 2628 if (msr & MSR_DSR) 2629 bits |= TIOCM_DSR; 2630 /* 2631 * XXX - MSR_RI is naturally volatile, and we make MSR_TERI 2632 * more volatile by reading the modem status a lot. Perhaps 2633 * we should latch both bits until the status is read here. 2634 */ 2635 if (msr & (MSR_RI | MSR_TERI)) 2636 bits |= TIOCM_RI; 2637 return (bits); 2638 } 2639 mcr = 0; 2640 if (bits & TIOCM_DTR) 2641 mcr |= MCR_DTR; 2642 if (bits & TIOCM_RTS) 2643 mcr |= MCR_RTS; 2644 if (com->gone) 2645 return(0); 2646 mtx_lock_spin(&sio_lock); 2647 switch (how) { 2648 case DMSET: 2649 outb(com->modem_ctl_port, 2650 com->mcr_image = mcr | (com->mcr_image & MCR_IENABLE)); 2651 break; 2652 case DMBIS: 2653 outb(com->modem_ctl_port, com->mcr_image |= mcr); 2654 break; 2655 case DMBIC: 2656 outb(com->modem_ctl_port, com->mcr_image &= ~mcr); 2657 break; 2658 } 2659 mtx_unlock_spin(&sio_lock); 2660 return (0); 2661} 2662 2663static void 2664siosettimeout() 2665{ 2666 struct com_s *com; 2667 bool_t someopen; 2668 int unit; 2669 2670 /* 2671 * Set our timeout period to 1 second if no polled devices are open. 2672 * Otherwise set it to max(1/200, 1/hz). 2673 * Enable timeouts iff some device is open. 2674 */ 2675 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 2676 sio_timeout = hz; 2677 someopen = FALSE; 2678 for (unit = 0; unit < sio_numunits; ++unit) { 2679 com = com_addr(unit); 2680 if (com != NULL && com->tp != NULL 2681 && com->tp->t_state & TS_ISOPEN && !com->gone) { 2682 someopen = TRUE; 2683 if (com->poll || com->poll_output) { 2684 sio_timeout = hz > 200 ? hz / 200 : 1; 2685 break; 2686 } 2687 } 2688 } 2689 if (someopen) { 2690 sio_timeouts_until_log = hz / sio_timeout; 2691 sio_timeout_handle = timeout(comwakeup, (void *)NULL, 2692 sio_timeout); 2693 } else { 2694 /* Flush error messages, if any. */ 2695 sio_timeouts_until_log = 1; 2696 comwakeup((void *)NULL); 2697 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 2698 } 2699} 2700 2701static void 2702comwakeup(chan) 2703 void *chan; 2704{ 2705 struct com_s *com; 2706 int unit; 2707 2708 sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout); 2709 2710 /* 2711 * Recover from lost output interrupts. 2712 * Poll any lines that don't use interrupts. 2713 */ 2714 for (unit = 0; unit < sio_numunits; ++unit) { 2715 com = com_addr(unit); 2716 if (com != NULL && !com->gone 2717 && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) { 2718 mtx_lock_spin(&sio_lock); 2719 siointr1(com); 2720 mtx_unlock_spin(&sio_lock); 2721 } 2722 } 2723 2724 /* 2725 * Check for and log errors, but not too often. 2726 */ 2727 if (--sio_timeouts_until_log > 0) 2728 return; 2729 sio_timeouts_until_log = hz / sio_timeout; 2730 for (unit = 0; unit < sio_numunits; ++unit) { 2731 int errnum; 2732 2733 com = com_addr(unit); 2734 if (com == NULL) 2735 continue; 2736 if (com->gone) 2737 continue; 2738 for (errnum = 0; errnum < CE_NTYPES; ++errnum) { 2739 u_int delta; 2740 u_long total; 2741 2742 mtx_lock_spin(&sio_lock); 2743 delta = com->delta_error_counts[errnum]; 2744 com->delta_error_counts[errnum] = 0; 2745 mtx_unlock_spin(&sio_lock); 2746 if (delta == 0) 2747 continue; 2748 total = com->error_counts[errnum] += delta; 2749 log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n", 2750 unit, delta, error_desc[errnum], 2751 delta == 1 ? "" : "s", total); 2752 } 2753 } 2754} 2755 2756/* 2757 * Following are all routines needed for SIO to act as console 2758 */ 2759struct siocnstate { 2760 u_char dlbl; 2761 u_char dlbh; 2762 u_char ier; 2763 u_char cfcr; 2764 u_char mcr; 2765}; 2766 2767/* 2768 * This is a function in order to not replicate "ttyd%d" more 2769 * places than absolutely necessary. 2770 */ 2771static void 2772siocnset(struct consdev *cd, int unit) 2773{ 2774 2775 cd->cn_unit = unit; 2776 sprintf(cd->cn_name, "ttyd%d", unit); 2777} 2778 2779#ifndef __alpha__ 2780static speed_t siocngetspeed(Port_t, u_long rclk); 2781#endif 2782static void siocnclose(struct siocnstate *sp, Port_t iobase); 2783static void siocnopen(struct siocnstate *sp, Port_t iobase, int speed); 2784static void siocntxwait(Port_t iobase); 2785 2786#ifdef __alpha__ 2787int siocnattach(int port, int speed); 2788int siogdbattach(int port, int speed); 2789int siogdbgetc(void); 2790void siogdbputc(int c); 2791#else 2792static cn_probe_t siocnprobe; 2793static cn_init_t siocninit; 2794static cn_term_t siocnterm; 2795#endif 2796static cn_checkc_t siocncheckc; 2797static cn_getc_t siocngetc; 2798static cn_putc_t siocnputc; 2799 2800#ifndef __alpha__ 2801CONS_DRIVER(sio, siocnprobe, siocninit, siocnterm, siocngetc, siocncheckc, 2802 siocnputc, NULL); 2803#endif 2804 2805#if DDB > 0 2806static struct consdev gdbconsdev; 2807#endif 2808 2809static void 2810siocntxwait(iobase) 2811 Port_t iobase; 2812{ 2813 int timo; 2814 2815 /* 2816 * Wait for any pending transmission to finish. Required to avoid 2817 * the UART lockup bug when the speed is changed, and for normal 2818 * transmits. 2819 */ 2820 timo = 100000; 2821 while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY)) 2822 != (LSR_TSRE | LSR_TXRDY) && --timo != 0) 2823 ; 2824} 2825 2826#ifndef __alpha__ 2827 2828/* 2829 * Read the serial port specified and try to figure out what speed 2830 * it's currently running at. We're assuming the serial port has 2831 * been initialized and is basicly idle. This routine is only intended 2832 * to be run at system startup. 2833 * 2834 * If the value read from the serial port doesn't make sense, return 0. 2835 */ 2836 2837static speed_t 2838siocngetspeed(iobase, rclk) 2839 Port_t iobase; 2840 u_long rclk; 2841{ 2842 u_int divisor; 2843 u_char dlbh; 2844 u_char dlbl; 2845 u_char cfcr; 2846 2847 cfcr = inb(iobase + com_cfcr); 2848 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 2849 2850 dlbl = inb(iobase + com_dlbl); 2851 dlbh = inb(iobase + com_dlbh); 2852 2853 outb(iobase + com_cfcr, cfcr); 2854 2855 divisor = dlbh << 8 | dlbl; 2856 2857 /* XXX there should be more sanity checking. */ 2858 if (divisor == 0) 2859 return (CONSPEED); 2860 return (rclk / (16UL * divisor)); 2861} 2862 2863#endif 2864 2865static void 2866siocnopen(sp, iobase, speed) 2867 struct siocnstate *sp; 2868 Port_t iobase; 2869 int speed; 2870{ 2871 u_int divisor; 2872 u_char dlbh; 2873 u_char dlbl; 2874 2875 /* 2876 * Save all the device control registers except the fifo register 2877 * and set our default ones (cs8 -parenb speed=comdefaultrate). 2878 * We can't save the fifo register since it is read-only. 2879 */ 2880 sp->ier = inb(iobase + com_ier); 2881 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */ 2882 siocntxwait(iobase); 2883 sp->cfcr = inb(iobase + com_cfcr); 2884 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 2885 sp->dlbl = inb(iobase + com_dlbl); 2886 sp->dlbh = inb(iobase + com_dlbh); 2887 /* 2888 * Only set the divisor registers if they would change, since on 2889 * some 16550 incompatibles (Startech), setting them clears the 2890 * data input register. This also reduces the effects of the 2891 * UMC8669F bug. 2892 */ 2893 divisor = siodivisor(comdefaultrclk, speed); 2894 dlbl = divisor & 0xFF; 2895 if (sp->dlbl != dlbl) 2896 outb(iobase + com_dlbl, dlbl); 2897 dlbh = divisor >> 8; 2898 if (sp->dlbh != dlbh) 2899 outb(iobase + com_dlbh, dlbh); 2900 outb(iobase + com_cfcr, CFCR_8BITS); 2901 sp->mcr = inb(iobase + com_mcr); 2902 /* 2903 * We don't want interrupts, but must be careful not to "disable" 2904 * them by clearing the MCR_IENABLE bit, since that might cause 2905 * an interrupt by floating the IRQ line. 2906 */ 2907 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS); 2908} 2909 2910static void 2911siocnclose(sp, iobase) 2912 struct siocnstate *sp; 2913 Port_t iobase; 2914{ 2915 /* 2916 * Restore the device control registers. 2917 */ 2918 siocntxwait(iobase); 2919 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 2920 if (sp->dlbl != inb(iobase + com_dlbl)) 2921 outb(iobase + com_dlbl, sp->dlbl); 2922 if (sp->dlbh != inb(iobase + com_dlbh)) 2923 outb(iobase + com_dlbh, sp->dlbh); 2924 outb(iobase + com_cfcr, sp->cfcr); 2925 /* 2926 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them. 2927 */ 2928 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS); 2929 outb(iobase + com_ier, sp->ier); 2930} 2931 2932#ifndef __alpha__ 2933 2934static void 2935siocnprobe(cp) 2936 struct consdev *cp; 2937{ 2938 speed_t boot_speed; 2939 u_char cfcr; 2940 u_int divisor; 2941 int s, unit; 2942 struct siocnstate sp; 2943 2944 /* 2945 * Find our first enabled console, if any. If it is a high-level 2946 * console device, then initialize it and return successfully. 2947 * If it is a low-level console device, then initialize it and 2948 * return unsuccessfully. It must be initialized in both cases 2949 * for early use by console drivers and debuggers. Initializing 2950 * the hardware is not necessary in all cases, since the i/o 2951 * routines initialize it on the fly, but it is necessary if 2952 * input might arrive while the hardware is switched back to an 2953 * uninitialized state. We can't handle multiple console devices 2954 * yet because our low-level routines don't take a device arg. 2955 * We trust the user to set the console flags properly so that we 2956 * don't need to probe. 2957 */ 2958 cp->cn_pri = CN_DEAD; 2959 2960 for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */ 2961 int flags; 2962 2963 if (resource_disabled("sio", unit)) 2964 continue; 2965 if (resource_int_value("sio", unit, "flags", &flags)) 2966 continue; 2967 if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) { 2968 int port; 2969 Port_t iobase; 2970 2971 if (resource_int_value("sio", unit, "port", &port)) 2972 continue; 2973 iobase = port; 2974 s = spltty(); 2975 if (boothowto & RB_SERIAL) { 2976 boot_speed = 2977 siocngetspeed(iobase, comdefaultrclk); 2978 if (boot_speed) 2979 comdefaultrate = boot_speed; 2980 } 2981 2982 /* 2983 * Initialize the divisor latch. We can't rely on 2984 * siocnopen() to do this the first time, since it 2985 * avoids writing to the latch if the latch appears 2986 * to have the correct value. Also, if we didn't 2987 * just read the speed from the hardware, then we 2988 * need to set the speed in hardware so that 2989 * switching it later is null. 2990 */ 2991 cfcr = inb(iobase + com_cfcr); 2992 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 2993 divisor = siodivisor(comdefaultrclk, comdefaultrate); 2994 outb(iobase + com_dlbl, divisor & 0xff); 2995 outb(iobase + com_dlbh, divisor >> 8); 2996 outb(iobase + com_cfcr, cfcr); 2997 2998 siocnopen(&sp, iobase, comdefaultrate); 2999 3000 splx(s); 3001 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) { 3002 siocnset(cp, unit); 3003 cp->cn_pri = COM_FORCECONSOLE(flags) 3004 || boothowto & RB_SERIAL 3005 ? CN_REMOTE : CN_NORMAL; 3006 siocniobase = iobase; 3007 siocnunit = unit; 3008 } 3009 if (COM_DEBUGGER(flags)) { 3010 printf("sio%d: gdb debugging port\n", unit); 3011 siogdbiobase = iobase; 3012 siogdbunit = unit; 3013#if DDB > 0 3014 siocnset(&gdbconsdev, unit); 3015 gdb_arg = &gdbconsdev; 3016 gdb_getc = siocngetc; 3017 gdb_putc = siocnputc; 3018#endif 3019 } 3020 } 3021 } 3022#ifdef __i386__ 3023#if DDB > 0 3024 /* 3025 * XXX Ugly Compatability. 3026 * If no gdb port has been specified, set it to be the console 3027 * as some configuration files don't specify the gdb port. 3028 */ 3029 if (gdb_arg == NULL && (boothowto & RB_GDB)) { 3030 printf("Warning: no GDB port specified. Defaulting to sio%d.\n", 3031 siocnunit); 3032 printf("Set flag 0x80 on desired GDB port in your\n"); 3033 printf("configuration file (currently sio only).\n"); 3034 siogdbiobase = siocniobase; 3035 siogdbunit = siocnunit; 3036 siocnset(&gdbconsdev, siocnunit); 3037 gdb_arg = &gdbconsdev; 3038 gdb_getc = siocngetc; 3039 gdb_putc = siocnputc; 3040 } 3041#endif 3042#endif 3043} 3044 3045static void 3046siocninit(cp) 3047 struct consdev *cp; 3048{ 3049 comconsole = cp->cn_unit; 3050} 3051 3052static void 3053siocnterm(cp) 3054 struct consdev *cp; 3055{ 3056 comconsole = -1; 3057} 3058 3059#endif 3060 3061#ifdef __alpha__ 3062 3063CONS_DRIVER(sio, NULL, NULL, NULL, siocngetc, siocncheckc, siocnputc, NULL); 3064 3065int 3066siocnattach(port, speed) 3067 int port; 3068 int speed; 3069{ 3070 int s; 3071 u_char cfcr; 3072 u_int divisor; 3073 struct siocnstate sp; 3074 int unit = 0; /* XXX random value! */ 3075 3076 siocniobase = port; 3077 siocnunit = unit; 3078 comdefaultrate = speed; 3079 sio_consdev.cn_pri = CN_NORMAL; 3080 siocnset(&sio_consdev, unit); 3081 3082 s = spltty(); 3083 3084 /* 3085 * Initialize the divisor latch. We can't rely on 3086 * siocnopen() to do this the first time, since it 3087 * avoids writing to the latch if the latch appears 3088 * to have the correct value. Also, if we didn't 3089 * just read the speed from the hardware, then we 3090 * need to set the speed in hardware so that 3091 * switching it later is null. 3092 */ 3093 cfcr = inb(siocniobase + com_cfcr); 3094 outb(siocniobase + com_cfcr, CFCR_DLAB | cfcr); 3095 divisor = siodivisor(comdefaultrclk, comdefaultrate); 3096 outb(siocniobase + com_dlbl, divisor & 0xff); 3097 outb(siocniobase + com_dlbh, divisor >> 8); 3098 outb(siocniobase + com_cfcr, cfcr); 3099 3100 siocnopen(&sp, siocniobase, comdefaultrate); 3101 splx(s); 3102 3103 cnadd(&sio_consdev); 3104 return (0); 3105} 3106 3107int 3108siogdbattach(port, speed) 3109 int port; 3110 int speed; 3111{ 3112 int s; 3113 u_char cfcr; 3114 u_int divisor; 3115 struct siocnstate sp; 3116 int unit = 1; /* XXX random value! */ 3117 3118 siogdbiobase = port; 3119 gdbdefaultrate = speed; 3120 3121 printf("sio%d: gdb debugging port\n", unit); 3122 siogdbunit = unit; 3123#if DDB > 0 3124 siocnset(&gdbconsdev, unit); 3125 gdb_arg = &gdbconsdev; 3126 gdb_getc = siocngetc; 3127 gdb_putc = siocnputc; 3128#endif 3129 3130 s = spltty(); 3131 3132 /* 3133 * Initialize the divisor latch. We can't rely on 3134 * siocnopen() to do this the first time, since it 3135 * avoids writing to the latch if the latch appears 3136 * to have the correct value. Also, if we didn't 3137 * just read the speed from the hardware, then we 3138 * need to set the speed in hardware so that 3139 * switching it later is null. 3140 */ 3141 cfcr = inb(siogdbiobase + com_cfcr); 3142 outb(siogdbiobase + com_cfcr, CFCR_DLAB | cfcr); 3143 divisor = siodivisor(comdefaultrclk, gdbdefaultrate); 3144 outb(siogdbiobase + com_dlbl, divisor & 0xff); 3145 outb(siogdbiobase + com_dlbh, divisor >> 8); 3146 outb(siogdbiobase + com_cfcr, cfcr); 3147 3148 siocnopen(&sp, siogdbiobase, gdbdefaultrate); 3149 splx(s); 3150 3151 return (0); 3152} 3153 3154#endif 3155 3156static int 3157siocncheckc(struct consdev *cd) 3158{ 3159 int c; 3160 Port_t iobase; 3161 int s; 3162 struct siocnstate sp; 3163 speed_t speed; 3164 3165 if (cd->cn_unit == siocnunit) { 3166 iobase = siocniobase; 3167 speed = comdefaultrate; 3168 } else { 3169 iobase = siogdbiobase; 3170 speed = gdbdefaultrate; 3171 } 3172 s = spltty(); 3173 siocnopen(&sp, iobase, speed); 3174 if (inb(iobase + com_lsr) & LSR_RXRDY) 3175 c = inb(iobase + com_data); 3176 else 3177 c = -1; 3178 siocnclose(&sp, iobase); 3179 splx(s); 3180 return (c); 3181} 3182 3183static int 3184siocngetc(struct consdev *cd) 3185{ 3186 int c; 3187 Port_t iobase; 3188 int s; 3189 struct siocnstate sp; 3190 speed_t speed; 3191 3192 if (cd->cn_unit == siocnunit) { 3193 iobase = siocniobase; 3194 speed = comdefaultrate; 3195 } else { 3196 iobase = siogdbiobase; 3197 speed = gdbdefaultrate; 3198 } 3199 s = spltty(); 3200 siocnopen(&sp, iobase, speed); 3201 while (!(inb(iobase + com_lsr) & LSR_RXRDY)) 3202 ; 3203 c = inb(iobase + com_data); 3204 siocnclose(&sp, iobase); 3205 splx(s); 3206 return (c); 3207} 3208 3209static void 3210siocnputc(struct consdev *cd, int c) 3211{ 3212 int need_unlock; 3213 int s; 3214 struct siocnstate sp; 3215 Port_t iobase; 3216 speed_t speed; 3217 3218 if (cd->cn_unit == siocnunit) { 3219 iobase = siocniobase; 3220 speed = comdefaultrate; 3221 } else { 3222 iobase = siogdbiobase; 3223 speed = gdbdefaultrate; 3224 } 3225 s = spltty(); 3226 need_unlock = 0; 3227 if (sio_inited == 2 && !mtx_owned(&sio_lock)) { 3228 mtx_lock_spin(&sio_lock); 3229 need_unlock = 1; 3230 } 3231 siocnopen(&sp, iobase, speed); 3232 siocntxwait(iobase); 3233 outb(iobase + com_data, c); 3234 siocnclose(&sp, iobase); 3235 if (need_unlock) 3236 mtx_unlock_spin(&sio_lock); 3237 splx(s); 3238} 3239 3240#ifdef __alpha__ 3241int 3242siogdbgetc() 3243{ 3244 int c; 3245 Port_t iobase; 3246 speed_t speed; 3247 int s; 3248 struct siocnstate sp; 3249 3250 if (siogdbunit == siocnunit) { 3251 iobase = siocniobase; 3252 speed = comdefaultrate; 3253 } else { 3254 iobase = siogdbiobase; 3255 speed = gdbdefaultrate; 3256 } 3257 3258 s = spltty(); 3259 siocnopen(&sp, iobase, speed); 3260 while (!(inb(iobase + com_lsr) & LSR_RXRDY)) 3261 ; 3262 c = inb(iobase + com_data); 3263 siocnclose(&sp, iobase); 3264 splx(s); 3265 return (c); 3266} 3267 3268void 3269siogdbputc(c) 3270 int c; 3271{ 3272 Port_t iobase; 3273 speed_t speed; 3274 int s; 3275 struct siocnstate sp; 3276 3277 if (siogdbunit == siocnunit) { 3278 iobase = siocniobase; 3279 speed = comdefaultrate; 3280 } else { 3281 iobase = siogdbiobase; 3282 speed = gdbdefaultrate; 3283 } 3284 3285 s = spltty(); 3286 siocnopen(&sp, iobase, speed); 3287 siocntxwait(siogdbiobase); 3288 outb(siogdbiobase + com_data, c); 3289 siocnclose(&sp, siogdbiobase); 3290 splx(s); 3291} 3292#endif 3293