sio.c revision 114216
1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by the University of 16 * California, Berkeley and its contributors. 17 * 4. Neither the name of the University nor the names of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/dev/sio/sio.c 114216 2003-04-29 13:36:06Z kan $ 34 * from: @(#)com.c 7.5 (Berkeley) 5/16/91 35 * from: i386/isa sio.c,v 1.234 36 */ 37 38#include "opt_comconsole.h" 39#include "opt_compat.h" 40#include "opt_ddb.h" 41#include "opt_sio.h" 42 43/* 44 * Serial driver, based on 386BSD-0.1 com driver. 45 * Mostly rewritten to use pseudo-DMA. 46 * Works for National Semiconductor NS8250-NS16550AF UARTs. 47 * COM driver, based on HP dca driver. 48 * 49 * Changes for PC-Card integration: 50 * - Added PC-Card driver table and handlers 51 */ 52#include <sys/param.h> 53#include <sys/systm.h> 54#include <sys/bus.h> 55#include <sys/conf.h> 56#include <sys/fcntl.h> 57#include <sys/interrupt.h> 58#include <sys/kernel.h> 59#include <sys/limits.h> 60#include <sys/lock.h> 61#include <sys/malloc.h> 62#include <sys/module.h> 63#include <sys/mutex.h> 64#include <sys/proc.h> 65#include <sys/reboot.h> 66#include <sys/sysctl.h> 67#include <sys/syslog.h> 68#include <sys/tty.h> 69#include <machine/bus_pio.h> 70#include <machine/bus.h> 71#include <sys/rman.h> 72#include <sys/timepps.h> 73#include <sys/uio.h> 74 75#include <isa/isavar.h> 76 77#include <machine/resource.h> 78 79#include <dev/sio/sioreg.h> 80#include <dev/sio/siovar.h> 81 82#ifdef COM_ESP 83#include <dev/ic/esp.h> 84#endif 85#include <dev/ic/ns16550.h> 86 87#define LOTS_OF_EVENTS 64 /* helps separate urgent events from input */ 88 89#define CALLOUT_MASK 0x80 90#define CONTROL_MASK 0x60 91#define CONTROL_INIT_STATE 0x20 92#define CONTROL_LOCK_STATE 0x40 93#define DEV_TO_UNIT(dev) (MINOR_TO_UNIT(minor(dev))) 94#define MINOR_TO_UNIT(mynor) ((((mynor) & ~0xffffU) >> (8 + 3)) \ 95 | ((mynor) & 0x1f)) 96#define UNIT_TO_MINOR(unit) ((((unit) & ~0x1fU) << (8 + 3)) \ 97 | ((unit) & 0x1f)) 98 99#ifdef COM_MULTIPORT 100/* checks in flags for multiport and which is multiport "master chip" 101 * for a given card 102 */ 103#define COM_ISMULTIPORT(flags) ((flags) & 0x01) 104#define COM_MPMASTER(flags) (((flags) >> 8) & 0x0ff) 105#define COM_NOTAST4(flags) ((flags) & 0x04) 106#else 107#define COM_ISMULTIPORT(flags) (0) 108#endif /* COM_MULTIPORT */ 109 110#define COM_CONSOLE(flags) ((flags) & 0x10) 111#define COM_FORCECONSOLE(flags) ((flags) & 0x20) 112#define COM_LLCONSOLE(flags) ((flags) & 0x40) 113#define COM_DEBUGGER(flags) ((flags) & 0x80) 114#define COM_LOSESOUTINTS(flags) ((flags) & 0x08) 115#define COM_NOFIFO(flags) ((flags) & 0x02) 116#define COM_PPSCTS(flags) ((flags) & 0x10000) 117#define COM_ST16650A(flags) ((flags) & 0x20000) 118#define COM_C_NOPROBE (0x40000) 119#define COM_NOPROBE(flags) ((flags) & COM_C_NOPROBE) 120#define COM_C_IIR_TXRDYBUG (0x80000) 121#define COM_IIR_TXRDYBUG(flags) ((flags) & COM_C_IIR_TXRDYBUG) 122#define COM_NOSCR(flags) ((flags) & 0x100000) 123#define COM_TI16754(flags) ((flags) & 0x200000) 124#define COM_FIFOSIZE(flags) (((flags) & 0xff000000) >> 24) 125 126#define sio_getreg(com, off) \ 127 (bus_space_read_1((com)->bst, (com)->bsh, (off))) 128#define sio_setreg(com, off, value) \ 129 (bus_space_write_1((com)->bst, (com)->bsh, (off), (value))) 130 131/* 132 * com state bits. 133 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher 134 * than the other bits so that they can be tested as a group without masking 135 * off the low bits. 136 * 137 * The following com and tty flags correspond closely: 138 * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and 139 * comstop()) 140 * CS_TTGO = ~TS_TTSTOP (maintained by comparam() and comstart()) 141 * CS_CTS_OFLOW = CCTS_OFLOW (maintained by comparam()) 142 * CS_RTS_IFLOW = CRTS_IFLOW (maintained by comparam()) 143 * TS_FLUSH is not used. 144 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON. 145 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state). 146 */ 147#define CS_BUSY 0x80 /* output in progress */ 148#define CS_TTGO 0x40 /* output not stopped by XOFF */ 149#define CS_ODEVREADY 0x20 /* external device h/w ready (CTS) */ 150#define CS_CHECKMSR 1 /* check of MSR scheduled */ 151#define CS_CTS_OFLOW 2 /* use CTS output flow control */ 152#define CS_DTR_OFF 0x10 /* DTR held off */ 153#define CS_ODONE 4 /* output completed */ 154#define CS_RTS_IFLOW 8 /* use RTS input flow control */ 155#define CSE_BUSYCHECK 1 /* siobusycheck() scheduled */ 156 157static char const * const error_desc[] = { 158#define CE_OVERRUN 0 159 "silo overflow", 160#define CE_INTERRUPT_BUF_OVERFLOW 1 161 "interrupt-level buffer overflow", 162#define CE_TTY_BUF_OVERFLOW 2 163 "tty-level buffer overflow", 164}; 165 166#define CE_NTYPES 3 167#define CE_RECORD(com, errnum) (++(com)->delta_error_counts[errnum]) 168 169/* types. XXX - should be elsewhere */ 170typedef u_int Port_t; /* hardware port */ 171typedef u_char bool_t; /* boolean */ 172 173/* queue of linear buffers */ 174struct lbq { 175 u_char *l_head; /* next char to process */ 176 u_char *l_tail; /* one past the last char to process */ 177 struct lbq *l_next; /* next in queue */ 178 bool_t l_queued; /* nonzero if queued */ 179}; 180 181/* com device structure */ 182struct com_s { 183 u_int flags; /* Copy isa device flags */ 184 u_char state; /* miscellaneous flag bits */ 185 bool_t active_out; /* nonzero if the callout device is open */ 186 u_char cfcr_image; /* copy of value written to CFCR */ 187#ifdef COM_ESP 188 bool_t esp; /* is this unit a hayes esp board? */ 189#endif 190 u_char extra_state; /* more flag bits, separate for order trick */ 191 u_char fifo_image; /* copy of value written to FIFO */ 192 bool_t hasfifo; /* nonzero for 16550 UARTs */ 193 bool_t st16650a; /* Is a Startech 16650A or RTS/CTS compat */ 194 bool_t loses_outints; /* nonzero if device loses output interrupts */ 195 u_char mcr_image; /* copy of value written to MCR */ 196#ifdef COM_MULTIPORT 197 bool_t multiport; /* is this unit part of a multiport device? */ 198#endif /* COM_MULTIPORT */ 199 bool_t no_irq; /* nonzero if irq is not attached */ 200 bool_t gone; /* hardware disappeared */ 201 bool_t poll; /* nonzero if polling is required */ 202 bool_t poll_output; /* nonzero if polling for output is required */ 203 int unit; /* unit number */ 204 int dtr_wait; /* time to hold DTR down on close (* 1/hz) */ 205 u_int tx_fifo_size; 206 u_int wopeners; /* # processes waiting for DCD in open() */ 207 208 /* 209 * The high level of the driver never reads status registers directly 210 * because there would be too many side effects to handle conveniently. 211 * Instead, it reads copies of the registers stored here by the 212 * interrupt handler. 213 */ 214 u_char last_modem_status; /* last MSR read by intr handler */ 215 u_char prev_modem_status; /* last MSR handled by high level */ 216 217 u_char hotchar; /* ldisc-specific char to be handled ASAP */ 218 u_char *ibuf; /* start of input buffer */ 219 u_char *ibufend; /* end of input buffer */ 220 u_char *ibufold; /* old input buffer, to be freed */ 221 u_char *ihighwater; /* threshold in input buffer */ 222 u_char *iptr; /* next free spot in input buffer */ 223 int ibufsize; /* size of ibuf (not include error bytes) */ 224 int ierroff; /* offset of error bytes in ibuf */ 225 226 struct lbq obufq; /* head of queue of output buffers */ 227 struct lbq obufs[2]; /* output buffers */ 228 229 bus_space_tag_t bst; 230 bus_space_handle_t bsh; 231 232 Port_t data_port; /* i/o ports */ 233#ifdef COM_ESP 234 Port_t esp_port; 235#endif 236 Port_t int_id_port; 237 Port_t modem_ctl_port; 238 Port_t line_status_port; 239 Port_t modem_status_port; 240 Port_t intr_ctl_port; /* Ports of IIR register */ 241 242 struct tty *tp; /* cross reference */ 243 244 /* Initial state. */ 245 struct termios it_in; /* should be in struct tty */ 246 struct termios it_out; 247 248 /* Lock state. */ 249 struct termios lt_in; /* should be in struct tty */ 250 struct termios lt_out; 251 252 bool_t do_timestamp; 253 bool_t do_dcd_timestamp; 254 struct timeval timestamp; 255 struct timeval dcd_timestamp; 256 struct pps_state pps; 257 int pps_bit; 258 259 u_long bytes_in; /* statistics */ 260 u_long bytes_out; 261 u_int delta_error_counts[CE_NTYPES]; 262 u_long error_counts[CE_NTYPES]; 263 264 u_long rclk; 265 266 struct resource *irqres; 267 struct resource *ioportres; 268 void *cookie; 269 dev_t devs[6]; 270 271 /* 272 * Data area for output buffers. Someday we should build the output 273 * buffer queue without copying data. 274 */ 275 u_char obuf1[256]; 276 u_char obuf2[256]; 277}; 278 279#ifdef COM_ESP 280static int espattach(struct com_s *com, Port_t esp_port); 281#endif 282 283static timeout_t siobusycheck; 284static u_int siodivisor(u_long rclk, speed_t speed); 285static timeout_t siodtrwakeup; 286static void comhardclose(struct com_s *com); 287static void sioinput(struct com_s *com); 288static void siointr1(struct com_s *com); 289static void siointr(void *arg); 290static int commctl(struct com_s *com, int bits, int how); 291static int comparam(struct tty *tp, struct termios *t); 292static void siopoll(void *); 293static void siosettimeout(void); 294static int siosetwater(struct com_s *com, speed_t speed); 295static void comstart(struct tty *tp); 296static void comstop(struct tty *tp, int rw); 297static timeout_t comwakeup; 298static void disc_optim(struct tty *tp, struct termios *t, 299 struct com_s *com); 300 301char sio_driver_name[] = "sio"; 302static struct mtx sio_lock; 303static int sio_inited; 304 305/* table and macro for fast conversion from a unit number to its com struct */ 306devclass_t sio_devclass; 307#define com_addr(unit) ((struct com_s *) \ 308 devclass_get_softc(sio_devclass, unit)) /* XXX */ 309 310static d_open_t sioopen; 311static d_close_t sioclose; 312static d_read_t sioread; 313static d_write_t siowrite; 314static d_ioctl_t sioioctl; 315 316#define CDEV_MAJOR 28 317static struct cdevsw sio_cdevsw = { 318 .d_open = sioopen, 319 .d_close = sioclose, 320 .d_read = sioread, 321 .d_write = siowrite, 322 .d_ioctl = sioioctl, 323 .d_poll = ttypoll, 324 .d_name = sio_driver_name, 325 .d_maj = CDEV_MAJOR, 326 .d_flags = D_TTY, 327 .d_kqfilter = ttykqfilter, 328}; 329 330int comconsole = -1; 331static volatile speed_t comdefaultrate = CONSPEED; 332static u_long comdefaultrclk = DEFAULT_RCLK; 333SYSCTL_ULONG(_machdep, OID_AUTO, conrclk, CTLFLAG_RW, &comdefaultrclk, 0, ""); 334static speed_t gdbdefaultrate = GDBSPEED; 335SYSCTL_UINT(_machdep, OID_AUTO, gdbspeed, CTLFLAG_RW, 336 &gdbdefaultrate, GDBSPEED, ""); 337static u_int com_events; /* input chars + weighted output completions */ 338static Port_t siocniobase; 339static int siocnunit = -1; 340static Port_t siogdbiobase; 341static int siogdbunit = -1; 342static void *sio_slow_ih; 343static void *sio_fast_ih; 344static int sio_timeout; 345static int sio_timeouts_until_log; 346static struct callout_handle sio_timeout_handle 347 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle); 348static int sio_numunits; 349 350#ifdef COM_ESP 351/* XXX configure this properly. */ 352/* XXX quite broken for new-bus. */ 353static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, }; 354static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 }; 355#endif 356 357/* 358 * handle sysctl read/write requests for console speed 359 * 360 * In addition to setting comdefaultrate for I/O through /dev/console, 361 * also set the initial and lock values for the /dev/ttyXX device 362 * if there is one associated with the console. Finally, if the /dev/tty 363 * device has already been open, change the speed on the open running port 364 * itself. 365 */ 366 367static int 368sysctl_machdep_comdefaultrate(SYSCTL_HANDLER_ARGS) 369{ 370 int error, s; 371 speed_t newspeed; 372 struct com_s *com; 373 struct tty *tp; 374 375 newspeed = comdefaultrate; 376 377 error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req); 378 if (error || !req->newptr) 379 return (error); 380 381 comdefaultrate = newspeed; 382 383 if (comconsole < 0) /* serial console not selected? */ 384 return (0); 385 386 com = com_addr(comconsole); 387 if (com == NULL) 388 return (ENXIO); 389 390 /* 391 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX 392 * (note, the lock rates really are boolean -- if non-zero, disallow 393 * speed changes) 394 */ 395 com->it_in.c_ispeed = com->it_in.c_ospeed = 396 com->lt_in.c_ispeed = com->lt_in.c_ospeed = 397 com->it_out.c_ispeed = com->it_out.c_ospeed = 398 com->lt_out.c_ispeed = com->lt_out.c_ospeed = comdefaultrate; 399 400 /* 401 * if we're open, change the running rate too 402 */ 403 tp = com->tp; 404 if (tp && (tp->t_state & TS_ISOPEN)) { 405 tp->t_termios.c_ispeed = 406 tp->t_termios.c_ospeed = comdefaultrate; 407 s = spltty(); 408 error = comparam(tp, &tp->t_termios); 409 splx(s); 410 } 411 return error; 412} 413 414SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW, 415 0, 0, sysctl_machdep_comdefaultrate, "I", ""); 416/* TUNABLE_INT("machdep.conspeed", &comdefaultrate); */ 417 418#define SET_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) | (bit)) 419#define CLR_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) & ~(bit)) 420 421/* 422 * Unload the driver and clear the table. 423 * XXX this is mostly wrong. 424 * XXX TODO: 425 * This is usually called when the card is ejected, but 426 * can be caused by a kldunload of a controller driver. 427 * The idea is to reset the driver's view of the device 428 * and ensure that any driver entry points such as 429 * read and write do not hang. 430 */ 431int 432siodetach(dev) 433 device_t dev; 434{ 435 struct com_s *com; 436 int i; 437 438 com = (struct com_s *) device_get_softc(dev); 439 if (com == NULL) { 440 device_printf(dev, "NULL com in siounload\n"); 441 return (0); 442 } 443 com->gone = 1; 444 for (i = 0 ; i < 6; i++) 445 destroy_dev(com->devs[i]); 446 if (com->irqres) { 447 bus_teardown_intr(dev, com->irqres, com->cookie); 448 bus_release_resource(dev, SYS_RES_IRQ, 0, com->irqres); 449 } 450 if (com->ioportres) 451 bus_release_resource(dev, SYS_RES_IOPORT, 0, com->ioportres); 452 if (com->tp && (com->tp->t_state & TS_ISOPEN)) { 453 device_printf(dev, "still open, forcing close\n"); 454 (*linesw[com->tp->t_line].l_close)(com->tp, 0); 455 com->tp->t_gen++; 456 ttyclose(com->tp); 457 ttwakeup(com->tp); 458 ttwwakeup(com->tp); 459 } else { 460 if (com->ibuf != NULL) 461 free(com->ibuf, M_DEVBUF); 462 device_set_softc(dev, NULL); 463 free(com, M_DEVBUF); 464 } 465 return (0); 466} 467 468int 469sioprobe(dev, xrid, rclk, noprobe) 470 device_t dev; 471 int xrid; 472 u_long rclk; 473 int noprobe; 474{ 475#if 0 476 static bool_t already_init; 477 device_t xdev; 478#endif 479 struct com_s *com; 480 u_int divisor; 481 bool_t failures[10]; 482 int fn; 483 device_t idev; 484 Port_t iobase; 485 intrmask_t irqmap[4]; 486 intrmask_t irqs; 487 u_char mcr_image; 488 int result; 489 u_long xirq; 490 u_int flags = device_get_flags(dev); 491 int rid; 492 struct resource *port; 493 494 rid = xrid; 495 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 496 0, ~0, IO_COMSIZE, RF_ACTIVE); 497 if (!port) 498 return (ENXIO); 499 500 com = malloc(sizeof(*com), M_DEVBUF, M_NOWAIT | M_ZERO); 501 if (com == NULL) 502 return (ENOMEM); 503 device_set_softc(dev, com); 504 com->bst = rman_get_bustag(port); 505 com->bsh = rman_get_bushandle(port); 506 if (rclk == 0) 507 rclk = DEFAULT_RCLK; 508 com->rclk = rclk; 509 510 while (sio_inited != 2) 511 if (atomic_cmpset_int(&sio_inited, 0, 1)) { 512 mtx_init(&sio_lock, sio_driver_name, NULL, 513 (comconsole != -1) ? 514 MTX_SPIN | MTX_QUIET : MTX_SPIN); 515 atomic_store_rel_int(&sio_inited, 2); 516 } 517 518#if 0 519 /* 520 * XXX this is broken - when we are first called, there are no 521 * previously configured IO ports. We could hard code 522 * 0x3f8, 0x2f8, 0x3e8, 0x2e8 etc but that's probably worse. 523 * This code has been doing nothing since the conversion since 524 * "count" is zero the first time around. 525 */ 526 if (!already_init) { 527 /* 528 * Turn off MCR_IENABLE for all likely serial ports. An unused 529 * port with its MCR_IENABLE gate open will inhibit interrupts 530 * from any used port that shares the interrupt vector. 531 * XXX the gate enable is elsewhere for some multiports. 532 */ 533 device_t *devs; 534 int count, i, xioport; 535 536 devclass_get_devices(sio_devclass, &devs, &count); 537 for (i = 0; i < count; i++) { 538 xdev = devs[i]; 539 if (device_is_enabled(xdev) && 540 bus_get_resource(xdev, SYS_RES_IOPORT, 0, &xioport, 541 NULL) == 0) 542 outb(xioport + com_mcr, 0); 543 } 544 free(devs, M_TEMP); 545 already_init = TRUE; 546 } 547#endif 548 549 if (COM_LLCONSOLE(flags)) { 550 printf("sio%d: reserved for low-level i/o\n", 551 device_get_unit(dev)); 552 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 553 device_set_softc(dev, NULL); 554 free(com, M_DEVBUF); 555 return (ENXIO); 556 } 557 558 /* 559 * If the device is on a multiport card and has an AST/4 560 * compatible interrupt control register, initialize this 561 * register and prepare to leave MCR_IENABLE clear in the mcr. 562 * Otherwise, prepare to set MCR_IENABLE in the mcr. 563 * Point idev to the device struct giving the correct id_irq. 564 * This is the struct for the master device if there is one. 565 */ 566 idev = dev; 567 mcr_image = MCR_IENABLE; 568#ifdef COM_MULTIPORT 569 if (COM_ISMULTIPORT(flags)) { 570 Port_t xiobase; 571 u_long io; 572 573 idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags)); 574 if (idev == NULL) { 575 printf("sio%d: master device %d not configured\n", 576 device_get_unit(dev), COM_MPMASTER(flags)); 577 idev = dev; 578 } 579 if (!COM_NOTAST4(flags)) { 580 if (bus_get_resource(idev, SYS_RES_IOPORT, 0, &io, 581 NULL) == 0) { 582 xiobase = io; 583 if (bus_get_resource(idev, SYS_RES_IRQ, 0, 584 NULL, NULL) == 0) 585 outb(xiobase + com_scr, 0x80); 586 else 587 outb(xiobase + com_scr, 0); 588 } 589 mcr_image = 0; 590 } 591 } 592#endif /* COM_MULTIPORT */ 593 if (bus_get_resource(idev, SYS_RES_IRQ, 0, NULL, NULL) != 0) 594 mcr_image = 0; 595 596 bzero(failures, sizeof failures); 597 iobase = rman_get_start(port); 598 599 /* 600 * We don't want to get actual interrupts, just masked ones. 601 * Interrupts from this line should already be masked in the ICU, 602 * but mask them in the processor as well in case there are some 603 * (misconfigured) shared interrupts. 604 */ 605 mtx_lock_spin(&sio_lock); 606/* EXTRA DELAY? */ 607 608 /* 609 * For the TI16754 chips, set prescaler to 1 (4 is often the 610 * default after-reset value) as otherwise it's impossible to 611 * get highest baudrates. 612 */ 613 if (COM_TI16754(flags)) { 614 u_char cfcr, efr; 615 616 cfcr = sio_getreg(com, com_cfcr); 617 sio_setreg(com, com_cfcr, CFCR_EFR_ENABLE); 618 efr = sio_getreg(com, com_efr); 619 /* Unlock extended features to turn off prescaler. */ 620 sio_setreg(com, com_efr, efr | EFR_EFE); 621 /* Disable EFR. */ 622 sio_setreg(com, com_cfcr, (cfcr != CFCR_EFR_ENABLE) ? cfcr : 0); 623 /* Turn off prescaler. */ 624 sio_setreg(com, com_mcr, 625 sio_getreg(com, com_mcr) & ~MCR_PRESCALE); 626 sio_setreg(com, com_cfcr, CFCR_EFR_ENABLE); 627 sio_setreg(com, com_efr, efr); 628 sio_setreg(com, com_cfcr, cfcr); 629 } 630 631 /* 632 * Initialize the speed and the word size and wait long enough to 633 * drain the maximum of 16 bytes of junk in device output queues. 634 * The speed is undefined after a master reset and must be set 635 * before relying on anything related to output. There may be 636 * junk after a (very fast) soft reboot and (apparently) after 637 * master reset. 638 * XXX what about the UART bug avoided by waiting in comparam()? 639 * We don't want to to wait long enough to drain at 2 bps. 640 */ 641 if (iobase == siocniobase) 642 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10)); 643 else { 644 sio_setreg(com, com_cfcr, CFCR_DLAB | CFCR_8BITS); 645 divisor = siodivisor(rclk, SIO_TEST_SPEED); 646 sio_setreg(com, com_dlbl, divisor & 0xff); 647 sio_setreg(com, com_dlbh, divisor >> 8); 648 sio_setreg(com, com_cfcr, CFCR_8BITS); 649 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10)); 650 } 651 652 /* 653 * Enable the interrupt gate and disable device interupts. This 654 * should leave the device driving the interrupt line low and 655 * guarantee an edge trigger if an interrupt can be generated. 656 */ 657/* EXTRA DELAY? */ 658 sio_setreg(com, com_mcr, mcr_image); 659 sio_setreg(com, com_ier, 0); 660 DELAY(1000); /* XXX */ 661 irqmap[0] = isa_irq_pending(); 662 663 /* 664 * Attempt to set loopback mode so that we can send a null byte 665 * without annoying any external device. 666 */ 667/* EXTRA DELAY? */ 668 sio_setreg(com, com_mcr, mcr_image | MCR_LOOPBACK); 669 670 /* 671 * Attempt to generate an output interrupt. On 8250's, setting 672 * IER_ETXRDY generates an interrupt independent of the current 673 * setting and independent of whether the THR is empty. On 16450's, 674 * setting IER_ETXRDY generates an interrupt independent of the 675 * current setting. On 16550A's, setting IER_ETXRDY only 676 * generates an interrupt when IER_ETXRDY is not already set. 677 */ 678 sio_setreg(com, com_ier, IER_ETXRDY); 679 680 /* 681 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate 682 * an interrupt. They'd better generate one for actually doing 683 * output. Loopback may be broken on the same incompatibles but 684 * it's unlikely to do more than allow the null byte out. 685 */ 686 sio_setreg(com, com_data, 0); 687 DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10)); 688 689 /* 690 * Turn off loopback mode so that the interrupt gate works again 691 * (MCR_IENABLE was hidden). This should leave the device driving 692 * an interrupt line high. It doesn't matter if the interrupt 693 * line oscillates while we are not looking at it, since interrupts 694 * are disabled. 695 */ 696/* EXTRA DELAY? */ 697 sio_setreg(com, com_mcr, mcr_image); 698 699 /* 700 * It seems my Xircom CBEM56G Cardbus modem wants to be reset 701 * to 8 bits *again*, or else probe test 0 will fail. 702 * gwk@sgi.com, 4/19/2001 703 */ 704 sio_setreg(com, com_cfcr, CFCR_8BITS); 705 706 /* 707 * Some pcmcia cards have the "TXRDY bug", so we check everyone 708 * for IIR_TXRDY implementation ( Palido 321s, DC-1S... ) 709 */ 710 if (noprobe) { 711 /* Reading IIR register twice */ 712 for (fn = 0; fn < 2; fn ++) { 713 DELAY(10000); 714 failures[6] = sio_getreg(com, com_iir); 715 } 716 /* Check IIR_TXRDY clear ? */ 717 result = 0; 718 if (failures[6] & IIR_TXRDY) { 719 /* No, Double check with clearing IER */ 720 sio_setreg(com, com_ier, 0); 721 if (sio_getreg(com, com_iir) & IIR_NOPEND) { 722 /* Ok. We discovered TXRDY bug! */ 723 SET_FLAG(dev, COM_C_IIR_TXRDYBUG); 724 } else { 725 /* Unknown, Just omit this chip.. XXX */ 726 result = ENXIO; 727 sio_setreg(com, com_mcr, 0); 728 } 729 } else { 730 /* OK. this is well-known guys */ 731 CLR_FLAG(dev, COM_C_IIR_TXRDYBUG); 732 } 733 sio_setreg(com, com_ier, 0); 734 sio_setreg(com, com_cfcr, CFCR_8BITS); 735 mtx_unlock_spin(&sio_lock); 736 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 737 if (iobase == siocniobase) 738 result = 0; 739 if (result != 0) { 740 device_set_softc(dev, NULL); 741 free(com, M_DEVBUF); 742 } 743 return (result); 744 } 745 746 /* 747 * Check that 748 * o the CFCR, IER and MCR in UART hold the values written to them 749 * (the values happen to be all distinct - this is good for 750 * avoiding false positive tests from bus echoes). 751 * o an output interrupt is generated and its vector is correct. 752 * o the interrupt goes away when the IIR in the UART is read. 753 */ 754/* EXTRA DELAY? */ 755 failures[0] = sio_getreg(com, com_cfcr) - CFCR_8BITS; 756 failures[1] = sio_getreg(com, com_ier) - IER_ETXRDY; 757 failures[2] = sio_getreg(com, com_mcr) - mcr_image; 758 DELAY(10000); /* Some internal modems need this time */ 759 irqmap[1] = isa_irq_pending(); 760 failures[4] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_TXRDY; 761 DELAY(1000); /* XXX */ 762 irqmap[2] = isa_irq_pending(); 763 failures[6] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND; 764 765 /* 766 * Turn off all device interrupts and check that they go off properly. 767 * Leave MCR_IENABLE alone. For ports without a master port, it gates 768 * the OUT2 output of the UART to 769 * the ICU input. Closing the gate would give a floating ICU input 770 * (unless there is another device driving it) and spurious interrupts. 771 * (On the system that this was first tested on, the input floats high 772 * and gives a (masked) interrupt as soon as the gate is closed.) 773 */ 774 sio_setreg(com, com_ier, 0); 775 sio_setreg(com, com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */ 776 failures[7] = sio_getreg(com, com_ier); 777 DELAY(1000); /* XXX */ 778 irqmap[3] = isa_irq_pending(); 779 failures[9] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND; 780 781 mtx_unlock_spin(&sio_lock); 782 783 irqs = irqmap[1] & ~irqmap[0]; 784 if (bus_get_resource(idev, SYS_RES_IRQ, 0, &xirq, NULL) == 0 && 785 ((1 << xirq) & irqs) == 0) { 786 printf( 787 "sio%d: configured irq %ld not in bitmap of probed irqs %#x\n", 788 device_get_unit(dev), xirq, irqs); 789 printf( 790 "sio%d: port may not be enabled\n", 791 device_get_unit(dev)); 792 } 793 if (bootverbose) 794 printf("sio%d: irq maps: %#x %#x %#x %#x\n", 795 device_get_unit(dev), 796 irqmap[0], irqmap[1], irqmap[2], irqmap[3]); 797 798 result = 0; 799 for (fn = 0; fn < sizeof failures; ++fn) 800 if (failures[fn]) { 801 sio_setreg(com, com_mcr, 0); 802 result = ENXIO; 803 if (bootverbose) { 804 printf("sio%d: probe failed test(s):", 805 device_get_unit(dev)); 806 for (fn = 0; fn < sizeof failures; ++fn) 807 if (failures[fn]) 808 printf(" %d", fn); 809 printf("\n"); 810 } 811 break; 812 } 813 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 814 if (iobase == siocniobase) 815 result = 0; 816 if (result != 0) { 817 device_set_softc(dev, NULL); 818 free(com, M_DEVBUF); 819 } 820 return (result); 821} 822 823#ifdef COM_ESP 824static int 825espattach(com, esp_port) 826 struct com_s *com; 827 Port_t esp_port; 828{ 829 u_char dips; 830 u_char val; 831 832 /* 833 * Check the ESP-specific I/O port to see if we're an ESP 834 * card. If not, return failure immediately. 835 */ 836 if ((inb(esp_port) & 0xf3) == 0) { 837 printf(" port 0x%x is not an ESP board?\n", esp_port); 838 return (0); 839 } 840 841 /* 842 * We've got something that claims to be a Hayes ESP card. 843 * Let's hope so. 844 */ 845 846 /* Get the dip-switch configuration */ 847 outb(esp_port + ESP_CMD1, ESP_GETDIPS); 848 dips = inb(esp_port + ESP_STATUS1); 849 850 /* 851 * Bits 0,1 of dips say which COM port we are. 852 */ 853 if (rman_get_start(com->ioportres) == likely_com_ports[dips & 0x03]) 854 printf(" : ESP"); 855 else { 856 printf(" esp_port has com %d\n", dips & 0x03); 857 return (0); 858 } 859 860 /* 861 * Check for ESP version 2.0 or later: bits 4,5,6 = 010. 862 */ 863 outb(esp_port + ESP_CMD1, ESP_GETTEST); 864 val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */ 865 val = inb(esp_port + ESP_STATUS2); 866 if ((val & 0x70) < 0x20) { 867 printf("-old (%o)", val & 0x70); 868 return (0); 869 } 870 871 /* 872 * Check for ability to emulate 16550: bit 7 == 1 873 */ 874 if ((dips & 0x80) == 0) { 875 printf(" slave"); 876 return (0); 877 } 878 879 /* 880 * Okay, we seem to be a Hayes ESP card. Whee. 881 */ 882 com->esp = TRUE; 883 com->esp_port = esp_port; 884 return (1); 885} 886#endif /* COM_ESP */ 887 888int 889sioattach(dev, xrid, rclk) 890 device_t dev; 891 int xrid; 892 u_long rclk; 893{ 894 struct com_s *com; 895#ifdef COM_ESP 896 Port_t *espp; 897#endif 898 Port_t iobase; 899 int minorbase; 900 int unit; 901 u_int flags; 902 int rid; 903 struct resource *port; 904 int ret; 905 906 rid = xrid; 907 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 908 0, ~0, IO_COMSIZE, RF_ACTIVE); 909 if (!port) 910 return (ENXIO); 911 912 iobase = rman_get_start(port); 913 unit = device_get_unit(dev); 914 com = device_get_softc(dev); 915 flags = device_get_flags(dev); 916 917 if (unit >= sio_numunits) 918 sio_numunits = unit + 1; 919 /* 920 * sioprobe() has initialized the device registers as follows: 921 * o cfcr = CFCR_8BITS. 922 * It is most important that CFCR_DLAB is off, so that the 923 * data port is not hidden when we enable interrupts. 924 * o ier = 0. 925 * Interrupts are only enabled when the line is open. 926 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible 927 * interrupt control register or the config specifies no irq. 928 * Keeping MCR_DTR and MCR_RTS off might stop the external 929 * device from sending before we are ready. 930 */ 931 bzero(com, sizeof *com); 932 com->unit = unit; 933 com->ioportres = port; 934 com->bst = rman_get_bustag(port); 935 com->bsh = rman_get_bushandle(port); 936 com->cfcr_image = CFCR_8BITS; 937 com->dtr_wait = 3 * hz; 938 com->loses_outints = COM_LOSESOUTINTS(flags) != 0; 939 com->no_irq = bus_get_resource(dev, SYS_RES_IRQ, 0, NULL, NULL) != 0; 940 com->tx_fifo_size = 1; 941 com->obufs[0].l_head = com->obuf1; 942 com->obufs[1].l_head = com->obuf2; 943 944 com->data_port = iobase + com_data; 945 com->int_id_port = iobase + com_iir; 946 com->modem_ctl_port = iobase + com_mcr; 947 com->mcr_image = inb(com->modem_ctl_port); 948 com->line_status_port = iobase + com_lsr; 949 com->modem_status_port = iobase + com_msr; 950 com->intr_ctl_port = iobase + com_ier; 951 952 if (rclk == 0) 953 rclk = DEFAULT_RCLK; 954 com->rclk = rclk; 955 956 /* 957 * We don't use all the flags from <sys/ttydefaults.h> since they 958 * are only relevant for logins. It's important to have echo off 959 * initially so that the line doesn't start blathering before the 960 * echo flag can be turned off. 961 */ 962 com->it_in.c_iflag = 0; 963 com->it_in.c_oflag = 0; 964 com->it_in.c_cflag = TTYDEF_CFLAG; 965 com->it_in.c_lflag = 0; 966 if (unit == comconsole) { 967 com->it_in.c_iflag = TTYDEF_IFLAG; 968 com->it_in.c_oflag = TTYDEF_OFLAG; 969 com->it_in.c_cflag = TTYDEF_CFLAG | CLOCAL; 970 com->it_in.c_lflag = TTYDEF_LFLAG; 971 com->lt_out.c_cflag = com->lt_in.c_cflag = CLOCAL; 972 com->lt_out.c_ispeed = com->lt_out.c_ospeed = 973 com->lt_in.c_ispeed = com->lt_in.c_ospeed = 974 com->it_in.c_ispeed = com->it_in.c_ospeed = comdefaultrate; 975 } else 976 com->it_in.c_ispeed = com->it_in.c_ospeed = TTYDEF_SPEED; 977 if (siosetwater(com, com->it_in.c_ispeed) != 0) { 978 mtx_unlock_spin(&sio_lock); 979 /* 980 * Leave i/o resources allocated if this is a `cn'-level 981 * console, so that other devices can't snarf them. 982 */ 983 if (iobase != siocniobase) 984 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 985 return (ENOMEM); 986 } 987 mtx_unlock_spin(&sio_lock); 988 termioschars(&com->it_in); 989 com->it_out = com->it_in; 990 991 /* attempt to determine UART type */ 992 printf("sio%d: type", unit); 993 994 995 if (!COM_ISMULTIPORT(flags) && 996 !COM_IIR_TXRDYBUG(flags) && !COM_NOSCR(flags)) { 997 u_char scr; 998 u_char scr1; 999 u_char scr2; 1000 1001 scr = sio_getreg(com, com_scr); 1002 sio_setreg(com, com_scr, 0xa5); 1003 scr1 = sio_getreg(com, com_scr); 1004 sio_setreg(com, com_scr, 0x5a); 1005 scr2 = sio_getreg(com, com_scr); 1006 sio_setreg(com, com_scr, scr); 1007 if (scr1 != 0xa5 || scr2 != 0x5a) { 1008 printf(" 8250 or not responding"); 1009 goto determined_type; 1010 } 1011 } 1012 sio_setreg(com, com_fifo, FIFO_ENABLE | FIFO_RX_HIGH); 1013 DELAY(100); 1014 com->st16650a = 0; 1015 switch (inb(com->int_id_port) & IIR_FIFO_MASK) { 1016 case FIFO_RX_LOW: 1017 printf(" 16450"); 1018 break; 1019 case FIFO_RX_MEDL: 1020 printf(" 16450?"); 1021 break; 1022 case FIFO_RX_MEDH: 1023 printf(" 16550?"); 1024 break; 1025 case FIFO_RX_HIGH: 1026 if (COM_NOFIFO(flags)) { 1027 printf(" 16550A fifo disabled"); 1028 } else { 1029 com->hasfifo = TRUE; 1030 if (COM_ST16650A(flags)) { 1031 com->st16650a = 1; 1032 com->tx_fifo_size = 32; 1033 printf(" ST16650A"); 1034 } else if (COM_TI16754(flags)) { 1035 com->tx_fifo_size = 64; 1036 printf(" TI16754"); 1037 } else { 1038 com->tx_fifo_size = COM_FIFOSIZE(flags); 1039 printf(" 16550A"); 1040 } 1041 } 1042#ifdef COM_ESP 1043 for (espp = likely_esp_ports; *espp != 0; espp++) 1044 if (espattach(com, *espp)) { 1045 com->tx_fifo_size = 1024; 1046 break; 1047 } 1048#endif 1049 if (!com->st16650a && !COM_TI16754(flags)) { 1050 if (!com->tx_fifo_size) 1051 com->tx_fifo_size = 16; 1052 else 1053 printf(" lookalike with %d bytes FIFO", 1054 com->tx_fifo_size); 1055 } 1056 1057 break; 1058 } 1059 1060#ifdef COM_ESP 1061 if (com->esp) { 1062 /* 1063 * Set 16550 compatibility mode. 1064 * We don't use the ESP_MODE_SCALE bit to increase the 1065 * fifo trigger levels because we can't handle large 1066 * bursts of input. 1067 * XXX flow control should be set in comparam(), not here. 1068 */ 1069 outb(com->esp_port + ESP_CMD1, ESP_SETMODE); 1070 outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO); 1071 1072 /* Set RTS/CTS flow control. */ 1073 outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE); 1074 outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS); 1075 outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS); 1076 1077 /* Set flow-control levels. */ 1078 outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW); 1079 outb(com->esp_port + ESP_CMD2, HIBYTE(768)); 1080 outb(com->esp_port + ESP_CMD2, LOBYTE(768)); 1081 outb(com->esp_port + ESP_CMD2, HIBYTE(512)); 1082 outb(com->esp_port + ESP_CMD2, LOBYTE(512)); 1083 } 1084#endif /* COM_ESP */ 1085 sio_setreg(com, com_fifo, 0); 1086determined_type: ; 1087 1088#ifdef COM_MULTIPORT 1089 if (COM_ISMULTIPORT(flags)) { 1090 device_t masterdev; 1091 1092 com->multiport = TRUE; 1093 printf(" (multiport"); 1094 if (unit == COM_MPMASTER(flags)) 1095 printf(" master"); 1096 printf(")"); 1097 masterdev = devclass_get_device(sio_devclass, 1098 COM_MPMASTER(flags)); 1099 com->no_irq = (masterdev == NULL || bus_get_resource(masterdev, 1100 SYS_RES_IRQ, 0, NULL, NULL) != 0); 1101 } 1102#endif /* COM_MULTIPORT */ 1103 if (unit == comconsole) 1104 printf(", console"); 1105 if (COM_IIR_TXRDYBUG(flags)) 1106 printf(" with a bogus IIR_TXRDY register"); 1107 printf("\n"); 1108 1109 if (sio_fast_ih == NULL) { 1110 swi_add(&tty_ithd, "tty:sio", siopoll, NULL, SWI_TTY, 0, 1111 &sio_fast_ih); 1112 swi_add(&clk_ithd, "tty:sio", siopoll, NULL, SWI_TTY, 0, 1113 &sio_slow_ih); 1114 } 1115 minorbase = UNIT_TO_MINOR(unit); 1116 com->devs[0] = make_dev(&sio_cdevsw, minorbase, 1117 UID_ROOT, GID_WHEEL, 0600, "ttyd%r", unit); 1118 com->devs[1] = make_dev(&sio_cdevsw, minorbase | CONTROL_INIT_STATE, 1119 UID_ROOT, GID_WHEEL, 0600, "ttyid%r", unit); 1120 com->devs[2] = make_dev(&sio_cdevsw, minorbase | CONTROL_LOCK_STATE, 1121 UID_ROOT, GID_WHEEL, 0600, "ttyld%r", unit); 1122 com->devs[3] = make_dev(&sio_cdevsw, minorbase | CALLOUT_MASK, 1123 UID_UUCP, GID_DIALER, 0660, "cuaa%r", unit); 1124 com->devs[4] = make_dev(&sio_cdevsw, 1125 minorbase | CALLOUT_MASK | CONTROL_INIT_STATE, 1126 UID_UUCP, GID_DIALER, 0660, "cuaia%r", unit); 1127 com->devs[5] = make_dev(&sio_cdevsw, 1128 minorbase | CALLOUT_MASK | CONTROL_LOCK_STATE, 1129 UID_UUCP, GID_DIALER, 0660, "cuala%r", unit); 1130 for (rid = 0; rid < 6; rid++) 1131 com->devs[rid]->si_drv1 = com; 1132 com->flags = flags; 1133 com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 1134 1135 if (COM_PPSCTS(flags)) 1136 com->pps_bit = MSR_CTS; 1137 else 1138 com->pps_bit = MSR_DCD; 1139 pps_init(&com->pps); 1140 1141 rid = 0; 1142 com->irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0ul, ~0ul, 1, 1143 RF_ACTIVE); 1144 if (com->irqres) { 1145 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, com->irqres, 1146 INTR_TYPE_TTY | INTR_FAST, 1147 siointr, com, &com->cookie); 1148 if (ret) { 1149 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, 1150 com->irqres, INTR_TYPE_TTY, 1151 siointr, com, &com->cookie); 1152 if (ret == 0) 1153 device_printf(dev, "unable to activate interrupt in fast mode - using normal mode\n"); 1154 } 1155 if (ret) 1156 device_printf(dev, "could not activate interrupt\n"); 1157#if defined(DDB) && (defined(BREAK_TO_DEBUGGER) || \ 1158 defined(ALT_BREAK_TO_DEBUGGER)) 1159 /* 1160 * Enable interrupts for early break-to-debugger support 1161 * on the console. 1162 */ 1163 if (ret == 0 && unit == comconsole) 1164 outb(siocniobase + com_ier, IER_ERXRDY | IER_ERLS | 1165 IER_EMSC); 1166#endif 1167 } 1168 1169 return (0); 1170} 1171 1172static int 1173sioopen(dev, flag, mode, td) 1174 dev_t dev; 1175 int flag; 1176 int mode; 1177 struct thread *td; 1178{ 1179 struct com_s *com; 1180 int error; 1181 int mynor; 1182 int s; 1183 struct tty *tp; 1184 int unit; 1185 1186 mynor = minor(dev); 1187 unit = MINOR_TO_UNIT(mynor); 1188 com = com_addr(unit); 1189 if (com == NULL) 1190 return (ENXIO); 1191 if (com->gone) 1192 return (ENXIO); 1193 if (mynor & CONTROL_MASK) 1194 return (0); 1195 tp = dev->si_tty = com->tp = ttymalloc(com->tp); 1196 s = spltty(); 1197 /* 1198 * We jump to this label after all non-interrupted sleeps to pick 1199 * up any changes of the device state. 1200 */ 1201open_top: 1202 while (com->state & CS_DTR_OFF) { 1203 error = tsleep(&com->dtr_wait, TTIPRI | PCATCH, "siodtr", 0); 1204 if (com_addr(unit) == NULL) 1205 return (ENXIO); 1206 if (error != 0 || com->gone) 1207 goto out; 1208 } 1209 if (tp->t_state & TS_ISOPEN) { 1210 /* 1211 * The device is open, so everything has been initialized. 1212 * Handle conflicts. 1213 */ 1214 if (mynor & CALLOUT_MASK) { 1215 if (!com->active_out) { 1216 error = EBUSY; 1217 goto out; 1218 } 1219 } else { 1220 if (com->active_out) { 1221 if (flag & O_NONBLOCK) { 1222 error = EBUSY; 1223 goto out; 1224 } 1225 error = tsleep(&com->active_out, 1226 TTIPRI | PCATCH, "siobi", 0); 1227 if (com_addr(unit) == NULL) 1228 return (ENXIO); 1229 if (error != 0 || com->gone) 1230 goto out; 1231 goto open_top; 1232 } 1233 } 1234 if (tp->t_state & TS_XCLUDE && 1235 suser(td)) { 1236 error = EBUSY; 1237 goto out; 1238 } 1239 } else { 1240 /* 1241 * The device isn't open, so there are no conflicts. 1242 * Initialize it. Initialization is done twice in many 1243 * cases: to preempt sleeping callin opens if we are 1244 * callout, and to complete a callin open after DCD rises. 1245 */ 1246 tp->t_oproc = comstart; 1247 tp->t_param = comparam; 1248 tp->t_stop = comstop; 1249 tp->t_dev = dev; 1250 tp->t_termios = mynor & CALLOUT_MASK 1251 ? com->it_out : com->it_in; 1252 (void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET); 1253 com->poll = com->no_irq; 1254 com->poll_output = com->loses_outints; 1255 ++com->wopeners; 1256 error = comparam(tp, &tp->t_termios); 1257 --com->wopeners; 1258 if (error != 0) 1259 goto out; 1260 /* 1261 * XXX we should goto open_top if comparam() slept. 1262 */ 1263 if (com->hasfifo) { 1264 int i; 1265 /* 1266 * (Re)enable and drain fifos. 1267 * 1268 * Certain SMC chips cause problems if the fifos 1269 * are enabled while input is ready. Turn off the 1270 * fifo if necessary to clear the input. We test 1271 * the input ready bit after enabling the fifos 1272 * since we've already enabled them in comparam() 1273 * and to handle races between enabling and fresh 1274 * input. 1275 */ 1276 for (i = 0; i < 500; i++) { 1277 sio_setreg(com, com_fifo, 1278 FIFO_RCV_RST | FIFO_XMT_RST 1279 | com->fifo_image); 1280 /* 1281 * XXX the delays are for superstitious 1282 * historical reasons. It must be less than 1283 * the character time at the maximum 1284 * supported speed (87 usec at 115200 bps 1285 * 8N1). Otherwise we might loop endlessly 1286 * if data is streaming in. We used to use 1287 * delays of 100. That usually worked 1288 * because DELAY(100) used to usually delay 1289 * for about 85 usec instead of 100. 1290 */ 1291 DELAY(50); 1292 if (!(inb(com->line_status_port) & LSR_RXRDY)) 1293 break; 1294 sio_setreg(com, com_fifo, 0); 1295 DELAY(50); 1296 (void) inb(com->data_port); 1297 } 1298 if (i == 500) { 1299 error = EIO; 1300 goto out; 1301 } 1302 } 1303 1304 mtx_lock_spin(&sio_lock); 1305 (void) inb(com->line_status_port); 1306 (void) inb(com->data_port); 1307 com->prev_modem_status = com->last_modem_status 1308 = inb(com->modem_status_port); 1309 if (COM_IIR_TXRDYBUG(com->flags)) { 1310 outb(com->intr_ctl_port, IER_ERXRDY | IER_ERLS 1311 | IER_EMSC); 1312 } else { 1313 outb(com->intr_ctl_port, IER_ERXRDY | IER_ETXRDY 1314 | IER_ERLS | IER_EMSC); 1315 } 1316 mtx_unlock_spin(&sio_lock); 1317 /* 1318 * Handle initial DCD. Callout devices get a fake initial 1319 * DCD (trapdoor DCD). If we are callout, then any sleeping 1320 * callin opens get woken up and resume sleeping on "siobi" 1321 * instead of "siodcd". 1322 */ 1323 /* 1324 * XXX `mynor & CALLOUT_MASK' should be 1325 * `tp->t_cflag & (SOFT_CARRIER | TRAPDOOR_CARRIER) where 1326 * TRAPDOOR_CARRIER is the default initial state for callout 1327 * devices and SOFT_CARRIER is like CLOCAL except it hides 1328 * the true carrier. 1329 */ 1330 if (com->prev_modem_status & MSR_DCD || mynor & CALLOUT_MASK) 1331 (*linesw[tp->t_line].l_modem)(tp, 1); 1332 } 1333 /* 1334 * Wait for DCD if necessary. 1335 */ 1336 if (!(tp->t_state & TS_CARR_ON) && !(mynor & CALLOUT_MASK) 1337 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 1338 ++com->wopeners; 1339 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "siodcd", 0); 1340 if (com_addr(unit) == NULL) 1341 return (ENXIO); 1342 --com->wopeners; 1343 if (error != 0 || com->gone) 1344 goto out; 1345 goto open_top; 1346 } 1347 error = (*linesw[tp->t_line].l_open)(dev, tp); 1348 disc_optim(tp, &tp->t_termios, com); 1349 if (tp->t_state & TS_ISOPEN && mynor & CALLOUT_MASK) 1350 com->active_out = TRUE; 1351 siosettimeout(); 1352out: 1353 splx(s); 1354 if (!(tp->t_state & TS_ISOPEN) && com->wopeners == 0) 1355 comhardclose(com); 1356 return (error); 1357} 1358 1359static int 1360sioclose(dev, flag, mode, td) 1361 dev_t dev; 1362 int flag; 1363 int mode; 1364 struct thread *td; 1365{ 1366 struct com_s *com; 1367 int mynor; 1368 int s; 1369 struct tty *tp; 1370 1371 mynor = minor(dev); 1372 if (mynor & CONTROL_MASK) 1373 return (0); 1374 com = com_addr(MINOR_TO_UNIT(mynor)); 1375 if (com == NULL) 1376 return (ENODEV); 1377 tp = com->tp; 1378 s = spltty(); 1379 (*linesw[tp->t_line].l_close)(tp, flag); 1380 disc_optim(tp, &tp->t_termios, com); 1381 comstop(tp, FREAD | FWRITE); 1382 comhardclose(com); 1383 ttyclose(tp); 1384 siosettimeout(); 1385 splx(s); 1386 if (com->gone) { 1387 printf("sio%d: gone\n", com->unit); 1388 s = spltty(); 1389 if (com->ibuf != NULL) 1390 free(com->ibuf, M_DEVBUF); 1391 bzero(tp, sizeof *tp); 1392 splx(s); 1393 } 1394 return (0); 1395} 1396 1397static void 1398comhardclose(com) 1399 struct com_s *com; 1400{ 1401 int s; 1402 struct tty *tp; 1403 int unit; 1404 1405 unit = com->unit; 1406 s = spltty(); 1407 com->poll = FALSE; 1408 com->poll_output = FALSE; 1409 com->do_timestamp = FALSE; 1410 com->do_dcd_timestamp = FALSE; 1411 com->pps.ppsparam.mode = 0; 1412 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 1413 tp = com->tp; 1414 1415#if defined(DDB) && (defined(BREAK_TO_DEBUGGER) || \ 1416 defined(ALT_BREAK_TO_DEBUGGER)) 1417 /* 1418 * Leave interrupts enabled and don't clear DTR if this is the 1419 * console. This allows us to detect break-to-debugger events 1420 * while the console device is closed. 1421 */ 1422 if (com->unit != comconsole) 1423#endif 1424 { 1425 sio_setreg(com, com_ier, 0); 1426 if (tp->t_cflag & HUPCL 1427 /* 1428 * XXX we will miss any carrier drop between here and the 1429 * next open. Perhaps we should watch DCD even when the 1430 * port is closed; it is not sufficient to check it at 1431 * the next open because it might go up and down while 1432 * we're not watching. 1433 */ 1434 || (!com->active_out 1435 && !(com->prev_modem_status & MSR_DCD) 1436 && !(com->it_in.c_cflag & CLOCAL)) 1437 || !(tp->t_state & TS_ISOPEN)) { 1438 (void)commctl(com, TIOCM_DTR, DMBIC); 1439 if (com->dtr_wait != 0 && !(com->state & CS_DTR_OFF)) { 1440 timeout(siodtrwakeup, com, com->dtr_wait); 1441 com->state |= CS_DTR_OFF; 1442 } 1443 } 1444 } 1445 if (com->hasfifo) { 1446 /* 1447 * Disable fifos so that they are off after controlled 1448 * reboots. Some BIOSes fail to detect 16550s when the 1449 * fifos are enabled. 1450 */ 1451 sio_setreg(com, com_fifo, 0); 1452 } 1453 com->active_out = FALSE; 1454 wakeup(&com->active_out); 1455 wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */ 1456 splx(s); 1457} 1458 1459static int 1460sioread(dev, uio, flag) 1461 dev_t dev; 1462 struct uio *uio; 1463 int flag; 1464{ 1465 int mynor; 1466 struct com_s *com; 1467 1468 mynor = minor(dev); 1469 if (mynor & CONTROL_MASK) 1470 return (ENODEV); 1471 com = com_addr(MINOR_TO_UNIT(mynor)); 1472 if (com == NULL || com->gone) 1473 return (ENODEV); 1474 return ((*linesw[com->tp->t_line].l_read)(com->tp, uio, flag)); 1475} 1476 1477static int 1478siowrite(dev, uio, flag) 1479 dev_t dev; 1480 struct uio *uio; 1481 int flag; 1482{ 1483 int mynor; 1484 struct com_s *com; 1485 int unit; 1486 1487 mynor = minor(dev); 1488 if (mynor & CONTROL_MASK) 1489 return (ENODEV); 1490 1491 unit = MINOR_TO_UNIT(mynor); 1492 com = com_addr(unit); 1493 if (com == NULL || com->gone) 1494 return (ENODEV); 1495 /* 1496 * (XXX) We disallow virtual consoles if the physical console is 1497 * a serial port. This is in case there is a display attached that 1498 * is not the console. In that situation we don't need/want the X 1499 * server taking over the console. 1500 */ 1501 if (constty != NULL && unit == comconsole) 1502 constty = NULL; 1503 return ((*linesw[com->tp->t_line].l_write)(com->tp, uio, flag)); 1504} 1505 1506static void 1507siobusycheck(chan) 1508 void *chan; 1509{ 1510 struct com_s *com; 1511 int s; 1512 1513 com = (struct com_s *)chan; 1514 1515 /* 1516 * Clear TS_BUSY if low-level output is complete. 1517 * spl locking is sufficient because siointr1() does not set CS_BUSY. 1518 * If siointr1() clears CS_BUSY after we look at it, then we'll get 1519 * called again. Reading the line status port outside of siointr1() 1520 * is safe because CS_BUSY is clear so there are no output interrupts 1521 * to lose. 1522 */ 1523 s = spltty(); 1524 if (com->state & CS_BUSY) 1525 com->extra_state &= ~CSE_BUSYCHECK; /* False alarm. */ 1526 else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY)) 1527 == (LSR_TSRE | LSR_TXRDY)) { 1528 com->tp->t_state &= ~TS_BUSY; 1529 ttwwakeup(com->tp); 1530 com->extra_state &= ~CSE_BUSYCHECK; 1531 } else 1532 timeout(siobusycheck, com, hz / 100); 1533 splx(s); 1534} 1535 1536static u_int 1537siodivisor(rclk, speed) 1538 u_long rclk; 1539 speed_t speed; 1540{ 1541 long actual_speed; 1542 u_int divisor; 1543 int error; 1544 1545 if (speed == 0 || speed > (ULONG_MAX - 1) / 8) 1546 return (0); 1547 divisor = (rclk / (8UL * speed) + 1) / 2; 1548 if (divisor == 0 || divisor >= 65536) 1549 return (0); 1550 actual_speed = rclk / (16UL * divisor); 1551 1552 /* 10 times error in percent: */ 1553 error = ((actual_speed - (long)speed) * 2000 / (long)speed + 1) / 2; 1554 1555 /* 3.0% maximum error tolerance: */ 1556 if (error < -30 || error > 30) 1557 return (0); 1558 1559 return (divisor); 1560} 1561 1562static void 1563siodtrwakeup(chan) 1564 void *chan; 1565{ 1566 struct com_s *com; 1567 1568 com = (struct com_s *)chan; 1569 com->state &= ~CS_DTR_OFF; 1570 wakeup(&com->dtr_wait); 1571} 1572 1573/* 1574 * Call this function with the sio_lock mutex held. It will return with the 1575 * lock still held. 1576 */ 1577static void 1578sioinput(com) 1579 struct com_s *com; 1580{ 1581 u_char *buf; 1582 int incc; 1583 u_char line_status; 1584 int recv_data; 1585 struct tty *tp; 1586 1587 buf = com->ibuf; 1588 tp = com->tp; 1589 if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) { 1590 com_events -= (com->iptr - com->ibuf); 1591 com->iptr = com->ibuf; 1592 return; 1593 } 1594 if (tp->t_state & TS_CAN_BYPASS_L_RINT) { 1595 /* 1596 * Avoid the grotesquely inefficient lineswitch routine 1597 * (ttyinput) in "raw" mode. It usually takes about 450 1598 * instructions (that's without canonical processing or echo!). 1599 * slinput is reasonably fast (usually 40 instructions plus 1600 * call overhead). 1601 */ 1602 do { 1603 /* 1604 * This may look odd, but it is using save-and-enable 1605 * semantics instead of the save-and-disable semantics 1606 * that are used everywhere else. 1607 */ 1608 mtx_unlock_spin(&sio_lock); 1609 incc = com->iptr - buf; 1610 if (tp->t_rawq.c_cc + incc > tp->t_ihiwat 1611 && (com->state & CS_RTS_IFLOW 1612 || tp->t_iflag & IXOFF) 1613 && !(tp->t_state & TS_TBLOCK)) 1614 ttyblock(tp); 1615 com->delta_error_counts[CE_TTY_BUF_OVERFLOW] 1616 += b_to_q((char *)buf, incc, &tp->t_rawq); 1617 buf += incc; 1618 tk_nin += incc; 1619 tk_rawcc += incc; 1620 tp->t_rawcc += incc; 1621 ttwakeup(tp); 1622 if (tp->t_state & TS_TTSTOP 1623 && (tp->t_iflag & IXANY 1624 || tp->t_cc[VSTART] == tp->t_cc[VSTOP])) { 1625 tp->t_state &= ~TS_TTSTOP; 1626 tp->t_lflag &= ~FLUSHO; 1627 comstart(tp); 1628 } 1629 mtx_lock_spin(&sio_lock); 1630 } while (buf < com->iptr); 1631 } else { 1632 do { 1633 /* 1634 * This may look odd, but it is using save-and-enable 1635 * semantics instead of the save-and-disable semantics 1636 * that are used everywhere else. 1637 */ 1638 mtx_unlock_spin(&sio_lock); 1639 line_status = buf[com->ierroff]; 1640 recv_data = *buf++; 1641 if (line_status 1642 & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) { 1643 if (line_status & LSR_BI) 1644 recv_data |= TTY_BI; 1645 if (line_status & LSR_FE) 1646 recv_data |= TTY_FE; 1647 if (line_status & LSR_OE) 1648 recv_data |= TTY_OE; 1649 if (line_status & LSR_PE) 1650 recv_data |= TTY_PE; 1651 } 1652 (*linesw[tp->t_line].l_rint)(recv_data, tp); 1653 mtx_lock_spin(&sio_lock); 1654 } while (buf < com->iptr); 1655 } 1656 com_events -= (com->iptr - com->ibuf); 1657 com->iptr = com->ibuf; 1658 1659 /* 1660 * There is now room for another low-level buffer full of input, 1661 * so enable RTS if it is now disabled and there is room in the 1662 * high-level buffer. 1663 */ 1664 if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) && 1665 !(tp->t_state & TS_TBLOCK)) 1666 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 1667} 1668 1669static void 1670siointr(arg) 1671 void *arg; 1672{ 1673 struct com_s *com; 1674 1675#ifndef COM_MULTIPORT 1676 com = (struct com_s *)arg; 1677 1678 mtx_lock_spin(&sio_lock); 1679 siointr1(com); 1680 mtx_unlock_spin(&sio_lock); 1681#else /* COM_MULTIPORT */ 1682 bool_t possibly_more_intrs; 1683 int unit; 1684 1685 /* 1686 * Loop until there is no activity on any port. This is necessary 1687 * to get an interrupt edge more than to avoid another interrupt. 1688 * If the IRQ signal is just an OR of the IRQ signals from several 1689 * devices, then the edge from one may be lost because another is 1690 * on. 1691 */ 1692 mtx_lock_spin(&sio_lock); 1693 do { 1694 possibly_more_intrs = FALSE; 1695 for (unit = 0; unit < sio_numunits; ++unit) { 1696 com = com_addr(unit); 1697 /* 1698 * XXX COM_LOCK(); 1699 * would it work here, or be counter-productive? 1700 */ 1701 if (com != NULL 1702 && !com->gone 1703 && (inb(com->int_id_port) & IIR_IMASK) 1704 != IIR_NOPEND) { 1705 siointr1(com); 1706 possibly_more_intrs = TRUE; 1707 } 1708 /* XXX COM_UNLOCK(); */ 1709 } 1710 } while (possibly_more_intrs); 1711 mtx_unlock_spin(&sio_lock); 1712#endif /* COM_MULTIPORT */ 1713} 1714 1715static struct timespec siots[8192]; 1716static int siotso; 1717static int volatile siotsunit = -1; 1718 1719static int 1720sysctl_siots(SYSCTL_HANDLER_ARGS) 1721{ 1722 char buf[128]; 1723 long long delta; 1724 size_t len; 1725 int error, i; 1726 1727 for (i = 1; i < siotso; i++) { 1728 delta = (long long)(siots[i].tv_sec - siots[i - 1].tv_sec) * 1729 1000000000 + 1730 (siots[i].tv_nsec - siots[i - 1].tv_nsec); 1731 len = sprintf(buf, "%lld\n", delta); 1732 if (delta >= 110000) 1733 len += sprintf(buf + len - 1, ": *** %ld.%09ld\n", 1734 (long)siots[i].tv_sec, siots[i].tv_nsec); 1735 if (i == siotso - 1) 1736 buf[len - 1] = '\0'; 1737 error = SYSCTL_OUT(req, buf, len); 1738 if (error != 0) 1739 return (error); 1740 uio_yield(); 1741 } 1742 return (0); 1743} 1744 1745SYSCTL_PROC(_machdep, OID_AUTO, siots, CTLTYPE_STRING | CTLFLAG_RD, 1746 0, 0, sysctl_siots, "A", "sio timestamps"); 1747 1748static void 1749siointr1(com) 1750 struct com_s *com; 1751{ 1752 u_char line_status; 1753 u_char modem_status; 1754 u_char *ioptr; 1755 u_char recv_data; 1756 u_char int_ctl; 1757 u_char int_ctl_new; 1758 1759 int_ctl = inb(com->intr_ctl_port); 1760 int_ctl_new = int_ctl; 1761 1762 while (!com->gone) { 1763 if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) { 1764 modem_status = inb(com->modem_status_port); 1765 if ((modem_status ^ com->last_modem_status) & 1766 com->pps_bit) { 1767 pps_capture(&com->pps); 1768 pps_event(&com->pps, 1769 (modem_status & com->pps_bit) ? 1770 PPS_CAPTUREASSERT : PPS_CAPTURECLEAR); 1771 } 1772 } 1773 line_status = inb(com->line_status_port); 1774 1775 /* input event? (check first to help avoid overruns) */ 1776 while (line_status & LSR_RCV_MASK) { 1777 /* break/unnattached error bits or real input? */ 1778 if (!(line_status & LSR_RXRDY)) 1779 recv_data = 0; 1780 else 1781 recv_data = inb(com->data_port); 1782#if defined(DDB) && defined(ALT_BREAK_TO_DEBUGGER) 1783 /* 1784 * Solaris implements a new BREAK which is initiated 1785 * by a character sequence CR ~ ^b which is similar 1786 * to a familiar pattern used on Sun servers by the 1787 * Remote Console. 1788 */ 1789#define KEY_CRTLB 2 /* ^B */ 1790#define KEY_CR 13 /* CR '\r' */ 1791#define KEY_TILDE 126 /* ~ */ 1792 1793 if (com->unit == comconsole) { 1794 static int brk_state1 = 0, brk_state2 = 0; 1795 if (recv_data == KEY_CR) { 1796 brk_state1 = recv_data; 1797 brk_state2 = 0; 1798 } else if (brk_state1 == KEY_CR 1799 && (recv_data == KEY_TILDE 1800 || recv_data == KEY_CRTLB)) { 1801 if (recv_data == KEY_TILDE) 1802 brk_state2 = recv_data; 1803 else if (brk_state2 == KEY_TILDE 1804 && recv_data == KEY_CRTLB) { 1805 breakpoint(); 1806 brk_state1 = 0; 1807 brk_state2 = 0; 1808 goto cont; 1809 } else 1810 brk_state2 = 0; 1811 } else 1812 brk_state1 = 0; 1813 } 1814#endif 1815 if (line_status & (LSR_BI | LSR_FE | LSR_PE)) { 1816 /* 1817 * Don't store BI if IGNBRK or FE/PE if IGNPAR. 1818 * Otherwise, push the work to a higher level 1819 * (to handle PARMRK) if we're bypassing. 1820 * Otherwise, convert BI/FE and PE+INPCK to 0. 1821 * 1822 * This makes bypassing work right in the 1823 * usual "raw" case (IGNBRK set, and IGNPAR 1824 * and INPCK clear). 1825 * 1826 * Note: BI together with FE/PE means just BI. 1827 */ 1828 if (line_status & LSR_BI) { 1829#if defined(DDB) && defined(BREAK_TO_DEBUGGER) 1830 if (com->unit == comconsole) { 1831 breakpoint(); 1832 goto cont; 1833 } 1834#endif 1835 if (com->tp == NULL 1836 || com->tp->t_iflag & IGNBRK) 1837 goto cont; 1838 } else { 1839 if (com->tp == NULL 1840 || com->tp->t_iflag & IGNPAR) 1841 goto cont; 1842 } 1843 if (com->tp->t_state & TS_CAN_BYPASS_L_RINT 1844 && (line_status & (LSR_BI | LSR_FE) 1845 || com->tp->t_iflag & INPCK)) 1846 recv_data = 0; 1847 } 1848 ++com->bytes_in; 1849 if (com->hotchar != 0 && recv_data == com->hotchar) 1850 swi_sched(sio_fast_ih, 0); 1851 ioptr = com->iptr; 1852 if (ioptr >= com->ibufend) 1853 CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW); 1854 else { 1855 if (com->do_timestamp) 1856 microtime(&com->timestamp); 1857 ++com_events; 1858 swi_sched(sio_slow_ih, SWI_DELAY); 1859#if 0 /* for testing input latency vs efficiency */ 1860if (com->iptr - com->ibuf == 8) 1861 swi_sched(sio_fast_ih, 0); 1862#endif 1863 ioptr[0] = recv_data; 1864 ioptr[com->ierroff] = line_status; 1865 com->iptr = ++ioptr; 1866 if (ioptr == com->ihighwater 1867 && com->state & CS_RTS_IFLOW) 1868 outb(com->modem_ctl_port, 1869 com->mcr_image &= ~MCR_RTS); 1870 if (line_status & LSR_OE) 1871 CE_RECORD(com, CE_OVERRUN); 1872 } 1873cont: 1874 /* 1875 * "& 0x7F" is to avoid the gcc-1.40 generating a slow 1876 * jump from the top of the loop to here 1877 */ 1878 line_status = inb(com->line_status_port) & 0x7F; 1879 } 1880 1881 /* modem status change? (always check before doing output) */ 1882 modem_status = inb(com->modem_status_port); 1883 if (modem_status != com->last_modem_status) { 1884 if (com->do_dcd_timestamp 1885 && !(com->last_modem_status & MSR_DCD) 1886 && modem_status & MSR_DCD) 1887 microtime(&com->dcd_timestamp); 1888 1889 /* 1890 * Schedule high level to handle DCD changes. Note 1891 * that we don't use the delta bits anywhere. Some 1892 * UARTs mess them up, and it's easy to remember the 1893 * previous bits and calculate the delta. 1894 */ 1895 com->last_modem_status = modem_status; 1896 if (!(com->state & CS_CHECKMSR)) { 1897 com_events += LOTS_OF_EVENTS; 1898 com->state |= CS_CHECKMSR; 1899 swi_sched(sio_fast_ih, 0); 1900 } 1901 1902 /* handle CTS change immediately for crisp flow ctl */ 1903 if (com->state & CS_CTS_OFLOW) { 1904 if (modem_status & MSR_CTS) 1905 com->state |= CS_ODEVREADY; 1906 else 1907 com->state &= ~CS_ODEVREADY; 1908 } 1909 } 1910 1911 /* output queued and everything ready? */ 1912 if (line_status & LSR_TXRDY 1913 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) { 1914 ioptr = com->obufq.l_head; 1915 if (com->tx_fifo_size > 1 && com->unit != siotsunit) { 1916 u_int ocount; 1917 1918 ocount = com->obufq.l_tail - ioptr; 1919 if (ocount > com->tx_fifo_size) 1920 ocount = com->tx_fifo_size; 1921 com->bytes_out += ocount; 1922 do 1923 outb(com->data_port, *ioptr++); 1924 while (--ocount != 0); 1925 } else { 1926 outb(com->data_port, *ioptr++); 1927 ++com->bytes_out; 1928 if (com->unit == siotsunit) { 1929 nanouptime(&siots[siotso]); 1930 siotso = (siotso + 1) % 1931 (sizeof siots / sizeof siots[0]); 1932 } 1933 } 1934 com->obufq.l_head = ioptr; 1935 if (COM_IIR_TXRDYBUG(com->flags)) { 1936 int_ctl_new = int_ctl | IER_ETXRDY; 1937 } 1938 if (ioptr >= com->obufq.l_tail) { 1939 struct lbq *qp; 1940 1941 qp = com->obufq.l_next; 1942 qp->l_queued = FALSE; 1943 qp = qp->l_next; 1944 if (qp != NULL) { 1945 com->obufq.l_head = qp->l_head; 1946 com->obufq.l_tail = qp->l_tail; 1947 com->obufq.l_next = qp; 1948 } else { 1949 /* output just completed */ 1950 if (COM_IIR_TXRDYBUG(com->flags)) { 1951 int_ctl_new = int_ctl & ~IER_ETXRDY; 1952 } 1953 com->state &= ~CS_BUSY; 1954 } 1955 if (!(com->state & CS_ODONE)) { 1956 com_events += LOTS_OF_EVENTS; 1957 com->state |= CS_ODONE; 1958 /* handle at high level ASAP */ 1959 swi_sched(sio_fast_ih, 0); 1960 } 1961 } 1962 if (COM_IIR_TXRDYBUG(com->flags) && (int_ctl != int_ctl_new)) { 1963 outb(com->intr_ctl_port, int_ctl_new); 1964 } 1965 } 1966 1967 /* finished? */ 1968#ifndef COM_MULTIPORT 1969 if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND) 1970#endif /* COM_MULTIPORT */ 1971 return; 1972 } 1973} 1974 1975static int 1976sioioctl(dev, cmd, data, flag, td) 1977 dev_t dev; 1978 u_long cmd; 1979 caddr_t data; 1980 int flag; 1981 struct thread *td; 1982{ 1983 struct com_s *com; 1984 int error; 1985 int mynor; 1986 int s; 1987 struct tty *tp; 1988#if defined(COMPAT_43) || defined(COMPAT_SUNOS) 1989 u_long oldcmd; 1990 struct termios term; 1991#endif 1992 1993 mynor = minor(dev); 1994 com = com_addr(MINOR_TO_UNIT(mynor)); 1995 if (com == NULL || com->gone) 1996 return (ENODEV); 1997 if (mynor & CONTROL_MASK) { 1998 struct termios *ct; 1999 2000 switch (mynor & CONTROL_MASK) { 2001 case CONTROL_INIT_STATE: 2002 ct = mynor & CALLOUT_MASK ? &com->it_out : &com->it_in; 2003 break; 2004 case CONTROL_LOCK_STATE: 2005 ct = mynor & CALLOUT_MASK ? &com->lt_out : &com->lt_in; 2006 break; 2007 default: 2008 return (ENODEV); /* /dev/nodev */ 2009 } 2010 switch (cmd) { 2011 case TIOCSETA: 2012 error = suser(td); 2013 if (error != 0) 2014 return (error); 2015 *ct = *(struct termios *)data; 2016 return (0); 2017 case TIOCGETA: 2018 *(struct termios *)data = *ct; 2019 return (0); 2020 case TIOCGETD: 2021 *(int *)data = TTYDISC; 2022 return (0); 2023 case TIOCGWINSZ: 2024 bzero(data, sizeof(struct winsize)); 2025 return (0); 2026 default: 2027 return (ENOTTY); 2028 } 2029 } 2030 tp = com->tp; 2031#if defined(COMPAT_43) || defined(COMPAT_SUNOS) 2032 term = tp->t_termios; 2033 oldcmd = cmd; 2034 error = ttsetcompat(tp, &cmd, data, &term); 2035 if (error != 0) 2036 return (error); 2037 if (cmd != oldcmd) 2038 data = (caddr_t)&term; 2039#endif 2040 if (cmd == TIOCSETA || cmd == TIOCSETAW || cmd == TIOCSETAF) { 2041 int cc; 2042 struct termios *dt = (struct termios *)data; 2043 struct termios *lt = mynor & CALLOUT_MASK 2044 ? &com->lt_out : &com->lt_in; 2045 2046 dt->c_iflag = (tp->t_iflag & lt->c_iflag) 2047 | (dt->c_iflag & ~lt->c_iflag); 2048 dt->c_oflag = (tp->t_oflag & lt->c_oflag) 2049 | (dt->c_oflag & ~lt->c_oflag); 2050 dt->c_cflag = (tp->t_cflag & lt->c_cflag) 2051 | (dt->c_cflag & ~lt->c_cflag); 2052 dt->c_lflag = (tp->t_lflag & lt->c_lflag) 2053 | (dt->c_lflag & ~lt->c_lflag); 2054 for (cc = 0; cc < NCCS; ++cc) 2055 if (lt->c_cc[cc] != 0) 2056 dt->c_cc[cc] = tp->t_cc[cc]; 2057 if (lt->c_ispeed != 0) 2058 dt->c_ispeed = tp->t_ispeed; 2059 if (lt->c_ospeed != 0) 2060 dt->c_ospeed = tp->t_ospeed; 2061 } 2062 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, td); 2063 if (error != ENOIOCTL) 2064 return (error); 2065 s = spltty(); 2066 error = ttioctl(tp, cmd, data, flag); 2067 disc_optim(tp, &tp->t_termios, com); 2068 if (error != ENOIOCTL) { 2069 splx(s); 2070 return (error); 2071 } 2072 switch (cmd) { 2073 case TIOCSBRK: 2074 sio_setreg(com, com_cfcr, com->cfcr_image |= CFCR_SBREAK); 2075 break; 2076 case TIOCCBRK: 2077 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 2078 break; 2079 case TIOCSDTR: 2080 (void)commctl(com, TIOCM_DTR, DMBIS); 2081 break; 2082 case TIOCCDTR: 2083 (void)commctl(com, TIOCM_DTR, DMBIC); 2084 break; 2085 /* 2086 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The 2087 * changes get undone on the next call to comparam(). 2088 */ 2089 case TIOCMSET: 2090 (void)commctl(com, *(int *)data, DMSET); 2091 break; 2092 case TIOCMBIS: 2093 (void)commctl(com, *(int *)data, DMBIS); 2094 break; 2095 case TIOCMBIC: 2096 (void)commctl(com, *(int *)data, DMBIC); 2097 break; 2098 case TIOCMGET: 2099 *(int *)data = commctl(com, 0, DMGET); 2100 break; 2101 case TIOCMSDTRWAIT: 2102 /* must be root since the wait applies to following logins */ 2103 error = suser(td); 2104 if (error != 0) { 2105 splx(s); 2106 return (error); 2107 } 2108 com->dtr_wait = *(int *)data * hz / 100; 2109 break; 2110 case TIOCMGDTRWAIT: 2111 *(int *)data = com->dtr_wait * 100 / hz; 2112 break; 2113 case TIOCTIMESTAMP: 2114 com->do_timestamp = TRUE; 2115 *(struct timeval *)data = com->timestamp; 2116 break; 2117 case TIOCDCDTIMESTAMP: 2118 com->do_dcd_timestamp = TRUE; 2119 *(struct timeval *)data = com->dcd_timestamp; 2120 break; 2121 default: 2122 splx(s); 2123 error = pps_ioctl(cmd, data, &com->pps); 2124 if (error == ENODEV) 2125 error = ENOTTY; 2126 return (error); 2127 } 2128 splx(s); 2129 return (0); 2130} 2131 2132/* software interrupt handler for SWI_TTY */ 2133static void 2134siopoll(void *dummy) 2135{ 2136 int unit; 2137 2138 if (com_events == 0) 2139 return; 2140repeat: 2141 for (unit = 0; unit < sio_numunits; ++unit) { 2142 struct com_s *com; 2143 int incc; 2144 struct tty *tp; 2145 2146 com = com_addr(unit); 2147 if (com == NULL) 2148 continue; 2149 tp = com->tp; 2150 if (tp == NULL || com->gone) { 2151 /* 2152 * Discard any events related to never-opened or 2153 * going-away devices. 2154 */ 2155 mtx_lock_spin(&sio_lock); 2156 incc = com->iptr - com->ibuf; 2157 com->iptr = com->ibuf; 2158 if (com->state & CS_CHECKMSR) { 2159 incc += LOTS_OF_EVENTS; 2160 com->state &= ~CS_CHECKMSR; 2161 } 2162 com_events -= incc; 2163 mtx_unlock_spin(&sio_lock); 2164 continue; 2165 } 2166 if (com->iptr != com->ibuf) { 2167 mtx_lock_spin(&sio_lock); 2168 sioinput(com); 2169 mtx_unlock_spin(&sio_lock); 2170 } 2171 if (com->state & CS_CHECKMSR) { 2172 u_char delta_modem_status; 2173 2174 mtx_lock_spin(&sio_lock); 2175 delta_modem_status = com->last_modem_status 2176 ^ com->prev_modem_status; 2177 com->prev_modem_status = com->last_modem_status; 2178 com_events -= LOTS_OF_EVENTS; 2179 com->state &= ~CS_CHECKMSR; 2180 mtx_unlock_spin(&sio_lock); 2181 if (delta_modem_status & MSR_DCD) 2182 (*linesw[tp->t_line].l_modem) 2183 (tp, com->prev_modem_status & MSR_DCD); 2184 } 2185 if (com->state & CS_ODONE) { 2186 mtx_lock_spin(&sio_lock); 2187 com_events -= LOTS_OF_EVENTS; 2188 com->state &= ~CS_ODONE; 2189 mtx_unlock_spin(&sio_lock); 2190 if (!(com->state & CS_BUSY) 2191 && !(com->extra_state & CSE_BUSYCHECK)) { 2192 timeout(siobusycheck, com, hz / 100); 2193 com->extra_state |= CSE_BUSYCHECK; 2194 } 2195 (*linesw[tp->t_line].l_start)(tp); 2196 } 2197 if (com_events == 0) 2198 break; 2199 } 2200 if (com_events >= LOTS_OF_EVENTS) 2201 goto repeat; 2202} 2203 2204static int 2205comparam(tp, t) 2206 struct tty *tp; 2207 struct termios *t; 2208{ 2209 u_int cfcr; 2210 int cflag; 2211 struct com_s *com; 2212 u_int divisor; 2213 u_char dlbh; 2214 u_char dlbl; 2215 int s; 2216 int unit; 2217 2218 unit = DEV_TO_UNIT(tp->t_dev); 2219 com = com_addr(unit); 2220 if (com == NULL) 2221 return (ENODEV); 2222 2223 /* do historical conversions */ 2224 if (t->c_ispeed == 0) 2225 t->c_ispeed = t->c_ospeed; 2226 2227 /* check requested parameters */ 2228 if (t->c_ospeed == 0) 2229 divisor = 0; 2230 else { 2231 if (t->c_ispeed != t->c_ospeed) 2232 return (EINVAL); 2233 divisor = siodivisor(com->rclk, t->c_ispeed); 2234 if (divisor == 0) 2235 return (EINVAL); 2236 } 2237 2238 /* parameters are OK, convert them to the com struct and the device */ 2239 s = spltty(); 2240 if (divisor == 0) 2241 (void)commctl(com, TIOCM_DTR, DMBIC); /* hang up line */ 2242 else 2243 (void)commctl(com, TIOCM_DTR, DMBIS); 2244 cflag = t->c_cflag; 2245 switch (cflag & CSIZE) { 2246 case CS5: 2247 cfcr = CFCR_5BITS; 2248 break; 2249 case CS6: 2250 cfcr = CFCR_6BITS; 2251 break; 2252 case CS7: 2253 cfcr = CFCR_7BITS; 2254 break; 2255 default: 2256 cfcr = CFCR_8BITS; 2257 break; 2258 } 2259 if (cflag & PARENB) { 2260 cfcr |= CFCR_PENAB; 2261 if (!(cflag & PARODD)) 2262 cfcr |= CFCR_PEVEN; 2263 } 2264 if (cflag & CSTOPB) 2265 cfcr |= CFCR_STOPB; 2266 2267 if (com->hasfifo && divisor != 0) { 2268 /* 2269 * Use a fifo trigger level low enough so that the input 2270 * latency from the fifo is less than about 16 msec and 2271 * the total latency is less than about 30 msec. These 2272 * latencies are reasonable for humans. Serial comms 2273 * protocols shouldn't expect anything better since modem 2274 * latencies are larger. 2275 * 2276 * The fifo trigger level cannot be set at RX_HIGH for high 2277 * speed connections without further work on reducing 2278 * interrupt disablement times in other parts of the system, 2279 * without producing silo overflow errors. 2280 */ 2281 com->fifo_image = com->unit == siotsunit ? 0 2282 : t->c_ospeed <= 4800 2283 ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_MEDH; 2284#ifdef COM_ESP 2285 /* 2286 * The Hayes ESP card needs the fifo DMA mode bit set 2287 * in compatibility mode. If not, it will interrupt 2288 * for each character received. 2289 */ 2290 if (com->esp) 2291 com->fifo_image |= FIFO_DMA_MODE; 2292#endif 2293 sio_setreg(com, com_fifo, com->fifo_image); 2294 } 2295 2296 /* 2297 * This returns with interrupts disabled so that we can complete 2298 * the speed change atomically. Keeping interrupts disabled is 2299 * especially important while com_data is hidden. 2300 */ 2301 (void) siosetwater(com, t->c_ispeed); 2302 2303 if (divisor != 0) { 2304 sio_setreg(com, com_cfcr, cfcr | CFCR_DLAB); 2305 /* 2306 * Only set the divisor registers if they would change, 2307 * since on some 16550 incompatibles (UMC8669F), setting 2308 * them while input is arriving them loses sync until 2309 * data stops arriving. 2310 */ 2311 dlbl = divisor & 0xFF; 2312 if (sio_getreg(com, com_dlbl) != dlbl) 2313 sio_setreg(com, com_dlbl, dlbl); 2314 dlbh = divisor >> 8; 2315 if (sio_getreg(com, com_dlbh) != dlbh) 2316 sio_setreg(com, com_dlbh, dlbh); 2317 } 2318 2319 sio_setreg(com, com_cfcr, com->cfcr_image = cfcr); 2320 2321 if (!(tp->t_state & TS_TTSTOP)) 2322 com->state |= CS_TTGO; 2323 2324 if (cflag & CRTS_IFLOW) { 2325 if (com->st16650a) { 2326 sio_setreg(com, com_cfcr, 0xbf); 2327 sio_setreg(com, com_fifo, 2328 sio_getreg(com, com_fifo) | 0x40); 2329 } 2330 com->state |= CS_RTS_IFLOW; 2331 /* 2332 * If CS_RTS_IFLOW just changed from off to on, the change 2333 * needs to be propagated to MCR_RTS. This isn't urgent, 2334 * so do it later by calling comstart() instead of repeating 2335 * a lot of code from comstart() here. 2336 */ 2337 } else if (com->state & CS_RTS_IFLOW) { 2338 com->state &= ~CS_RTS_IFLOW; 2339 /* 2340 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS 2341 * on here, since comstart() won't do it later. 2342 */ 2343 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2344 if (com->st16650a) { 2345 sio_setreg(com, com_cfcr, 0xbf); 2346 sio_setreg(com, com_fifo, 2347 sio_getreg(com, com_fifo) & ~0x40); 2348 } 2349 } 2350 2351 2352 /* 2353 * Set up state to handle output flow control. 2354 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level? 2355 * Now has 10+ msec latency, while CTS flow has 50- usec latency. 2356 */ 2357 com->state |= CS_ODEVREADY; 2358 com->state &= ~CS_CTS_OFLOW; 2359 if (cflag & CCTS_OFLOW) { 2360 com->state |= CS_CTS_OFLOW; 2361 if (!(com->last_modem_status & MSR_CTS)) 2362 com->state &= ~CS_ODEVREADY; 2363 if (com->st16650a) { 2364 sio_setreg(com, com_cfcr, 0xbf); 2365 sio_setreg(com, com_fifo, 2366 sio_getreg(com, com_fifo) | 0x80); 2367 } 2368 } else { 2369 if (com->st16650a) { 2370 sio_setreg(com, com_cfcr, 0xbf); 2371 sio_setreg(com, com_fifo, 2372 sio_getreg(com, com_fifo) & ~0x80); 2373 } 2374 } 2375 2376 sio_setreg(com, com_cfcr, com->cfcr_image); 2377 2378 /* XXX shouldn't call functions while intrs are disabled. */ 2379 disc_optim(tp, t, com); 2380 /* 2381 * Recover from fiddling with CS_TTGO. We used to call siointr1() 2382 * unconditionally, but that defeated the careful discarding of 2383 * stale input in sioopen(). 2384 */ 2385 if (com->state >= (CS_BUSY | CS_TTGO)) 2386 siointr1(com); 2387 2388 mtx_unlock_spin(&sio_lock); 2389 splx(s); 2390 comstart(tp); 2391 if (com->ibufold != NULL) { 2392 free(com->ibufold, M_DEVBUF); 2393 com->ibufold = NULL; 2394 } 2395 return (0); 2396} 2397 2398/* 2399 * This function must be called with the sio_lock mutex released and will 2400 * return with it obtained. 2401 */ 2402static int 2403siosetwater(com, speed) 2404 struct com_s *com; 2405 speed_t speed; 2406{ 2407 int cp4ticks; 2408 u_char *ibuf; 2409 int ibufsize; 2410 struct tty *tp; 2411 2412 /* 2413 * Make the buffer size large enough to handle a softtty interrupt 2414 * latency of about 2 ticks without loss of throughput or data 2415 * (about 3 ticks if input flow control is not used or not honoured, 2416 * but a bit less for CS5-CS7 modes). 2417 */ 2418 cp4ticks = speed / 10 / hz * 4; 2419 for (ibufsize = 128; ibufsize < cp4ticks;) 2420 ibufsize <<= 1; 2421 if (ibufsize == com->ibufsize) { 2422 mtx_lock_spin(&sio_lock); 2423 return (0); 2424 } 2425 2426 /* 2427 * Allocate input buffer. The extra factor of 2 in the size is 2428 * to allow for an error byte for each input byte. 2429 */ 2430 ibuf = malloc(2 * ibufsize, M_DEVBUF, M_NOWAIT); 2431 if (ibuf == NULL) { 2432 mtx_lock_spin(&sio_lock); 2433 return (ENOMEM); 2434 } 2435 2436 /* Initialize non-critical variables. */ 2437 com->ibufold = com->ibuf; 2438 com->ibufsize = ibufsize; 2439 tp = com->tp; 2440 if (tp != NULL) { 2441 tp->t_ififosize = 2 * ibufsize; 2442 tp->t_ispeedwat = (speed_t)-1; 2443 tp->t_ospeedwat = (speed_t)-1; 2444 } 2445 2446 /* 2447 * Read current input buffer, if any. Continue with interrupts 2448 * disabled. 2449 */ 2450 mtx_lock_spin(&sio_lock); 2451 if (com->iptr != com->ibuf) 2452 sioinput(com); 2453 2454 /*- 2455 * Initialize critical variables, including input buffer watermarks. 2456 * The external device is asked to stop sending when the buffer 2457 * exactly reaches high water, or when the high level requests it. 2458 * The high level is notified immediately (rather than at a later 2459 * clock tick) when this watermark is reached. 2460 * The buffer size is chosen so the watermark should almost never 2461 * be reached. 2462 * The low watermark is invisibly 0 since the buffer is always 2463 * emptied all at once. 2464 */ 2465 com->iptr = com->ibuf = ibuf; 2466 com->ibufend = ibuf + ibufsize; 2467 com->ierroff = ibufsize; 2468 com->ihighwater = ibuf + 3 * ibufsize / 4; 2469 return (0); 2470} 2471 2472static void 2473comstart(tp) 2474 struct tty *tp; 2475{ 2476 struct com_s *com; 2477 int s; 2478 int unit; 2479 2480 unit = DEV_TO_UNIT(tp->t_dev); 2481 com = com_addr(unit); 2482 if (com == NULL) 2483 return; 2484 s = spltty(); 2485 mtx_lock_spin(&sio_lock); 2486 if (tp->t_state & TS_TTSTOP) 2487 com->state &= ~CS_TTGO; 2488 else 2489 com->state |= CS_TTGO; 2490 if (tp->t_state & TS_TBLOCK) { 2491 if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW) 2492 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS); 2493 } else { 2494 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater 2495 && com->state & CS_RTS_IFLOW) 2496 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2497 } 2498 mtx_unlock_spin(&sio_lock); 2499 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) { 2500 ttwwakeup(tp); 2501 splx(s); 2502 return; 2503 } 2504 if (tp->t_outq.c_cc != 0) { 2505 struct lbq *qp; 2506 struct lbq *next; 2507 2508 if (!com->obufs[0].l_queued) { 2509 com->obufs[0].l_tail 2510 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1, 2511 sizeof com->obuf1); 2512 com->obufs[0].l_next = NULL; 2513 com->obufs[0].l_queued = TRUE; 2514 mtx_lock_spin(&sio_lock); 2515 if (com->state & CS_BUSY) { 2516 qp = com->obufq.l_next; 2517 while ((next = qp->l_next) != NULL) 2518 qp = next; 2519 qp->l_next = &com->obufs[0]; 2520 } else { 2521 com->obufq.l_head = com->obufs[0].l_head; 2522 com->obufq.l_tail = com->obufs[0].l_tail; 2523 com->obufq.l_next = &com->obufs[0]; 2524 com->state |= CS_BUSY; 2525 } 2526 mtx_unlock_spin(&sio_lock); 2527 } 2528 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) { 2529 com->obufs[1].l_tail 2530 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2, 2531 sizeof com->obuf2); 2532 com->obufs[1].l_next = NULL; 2533 com->obufs[1].l_queued = TRUE; 2534 mtx_lock_spin(&sio_lock); 2535 if (com->state & CS_BUSY) { 2536 qp = com->obufq.l_next; 2537 while ((next = qp->l_next) != NULL) 2538 qp = next; 2539 qp->l_next = &com->obufs[1]; 2540 } else { 2541 com->obufq.l_head = com->obufs[1].l_head; 2542 com->obufq.l_tail = com->obufs[1].l_tail; 2543 com->obufq.l_next = &com->obufs[1]; 2544 com->state |= CS_BUSY; 2545 } 2546 mtx_unlock_spin(&sio_lock); 2547 } 2548 tp->t_state |= TS_BUSY; 2549 } 2550 mtx_lock_spin(&sio_lock); 2551 if (com->state >= (CS_BUSY | CS_TTGO)) 2552 siointr1(com); /* fake interrupt to start output */ 2553 mtx_unlock_spin(&sio_lock); 2554 ttwwakeup(tp); 2555 splx(s); 2556} 2557 2558static void 2559comstop(tp, rw) 2560 struct tty *tp; 2561 int rw; 2562{ 2563 struct com_s *com; 2564 2565 com = com_addr(DEV_TO_UNIT(tp->t_dev)); 2566 if (com == NULL || com->gone) 2567 return; 2568 mtx_lock_spin(&sio_lock); 2569 if (rw & FWRITE) { 2570 if (com->hasfifo) 2571#ifdef COM_ESP 2572 /* XXX avoid h/w bug. */ 2573 if (!com->esp) 2574#endif 2575 sio_setreg(com, com_fifo, 2576 FIFO_XMT_RST | com->fifo_image); 2577 com->obufs[0].l_queued = FALSE; 2578 com->obufs[1].l_queued = FALSE; 2579 if (com->state & CS_ODONE) 2580 com_events -= LOTS_OF_EVENTS; 2581 com->state &= ~(CS_ODONE | CS_BUSY); 2582 com->tp->t_state &= ~TS_BUSY; 2583 } 2584 if (rw & FREAD) { 2585 if (com->hasfifo) 2586#ifdef COM_ESP 2587 /* XXX avoid h/w bug. */ 2588 if (!com->esp) 2589#endif 2590 sio_setreg(com, com_fifo, 2591 FIFO_RCV_RST | com->fifo_image); 2592 com_events -= (com->iptr - com->ibuf); 2593 com->iptr = com->ibuf; 2594 } 2595 mtx_unlock_spin(&sio_lock); 2596 comstart(tp); 2597} 2598 2599static int 2600commctl(com, bits, how) 2601 struct com_s *com; 2602 int bits; 2603 int how; 2604{ 2605 int mcr; 2606 int msr; 2607 2608 if (how == DMGET) { 2609 bits = TIOCM_LE; /* XXX - always enabled while open */ 2610 mcr = com->mcr_image; 2611 if (mcr & MCR_DTR) 2612 bits |= TIOCM_DTR; 2613 if (mcr & MCR_RTS) 2614 bits |= TIOCM_RTS; 2615 msr = com->prev_modem_status; 2616 if (msr & MSR_CTS) 2617 bits |= TIOCM_CTS; 2618 if (msr & MSR_DCD) 2619 bits |= TIOCM_CD; 2620 if (msr & MSR_DSR) 2621 bits |= TIOCM_DSR; 2622 /* 2623 * XXX - MSR_RI is naturally volatile, and we make MSR_TERI 2624 * more volatile by reading the modem status a lot. Perhaps 2625 * we should latch both bits until the status is read here. 2626 */ 2627 if (msr & (MSR_RI | MSR_TERI)) 2628 bits |= TIOCM_RI; 2629 return (bits); 2630 } 2631 mcr = 0; 2632 if (bits & TIOCM_DTR) 2633 mcr |= MCR_DTR; 2634 if (bits & TIOCM_RTS) 2635 mcr |= MCR_RTS; 2636 if (com->gone) 2637 return(0); 2638 mtx_lock_spin(&sio_lock); 2639 switch (how) { 2640 case DMSET: 2641 outb(com->modem_ctl_port, 2642 com->mcr_image = mcr | (com->mcr_image & MCR_IENABLE)); 2643 break; 2644 case DMBIS: 2645 outb(com->modem_ctl_port, com->mcr_image |= mcr); 2646 break; 2647 case DMBIC: 2648 outb(com->modem_ctl_port, com->mcr_image &= ~mcr); 2649 break; 2650 } 2651 mtx_unlock_spin(&sio_lock); 2652 return (0); 2653} 2654 2655static void 2656siosettimeout() 2657{ 2658 struct com_s *com; 2659 bool_t someopen; 2660 int unit; 2661 2662 /* 2663 * Set our timeout period to 1 second if no polled devices are open. 2664 * Otherwise set it to max(1/200, 1/hz). 2665 * Enable timeouts iff some device is open. 2666 */ 2667 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 2668 sio_timeout = hz; 2669 someopen = FALSE; 2670 for (unit = 0; unit < sio_numunits; ++unit) { 2671 com = com_addr(unit); 2672 if (com != NULL && com->tp != NULL 2673 && com->tp->t_state & TS_ISOPEN && !com->gone) { 2674 someopen = TRUE; 2675 if (com->poll || com->poll_output) { 2676 sio_timeout = hz > 200 ? hz / 200 : 1; 2677 break; 2678 } 2679 } 2680 } 2681 if (someopen) { 2682 sio_timeouts_until_log = hz / sio_timeout; 2683 sio_timeout_handle = timeout(comwakeup, (void *)NULL, 2684 sio_timeout); 2685 } else { 2686 /* Flush error messages, if any. */ 2687 sio_timeouts_until_log = 1; 2688 comwakeup((void *)NULL); 2689 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 2690 } 2691} 2692 2693static void 2694comwakeup(chan) 2695 void *chan; 2696{ 2697 struct com_s *com; 2698 int unit; 2699 2700 sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout); 2701 2702 /* 2703 * Recover from lost output interrupts. 2704 * Poll any lines that don't use interrupts. 2705 */ 2706 for (unit = 0; unit < sio_numunits; ++unit) { 2707 com = com_addr(unit); 2708 if (com != NULL && !com->gone 2709 && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) { 2710 mtx_lock_spin(&sio_lock); 2711 siointr1(com); 2712 mtx_unlock_spin(&sio_lock); 2713 } 2714 } 2715 2716 /* 2717 * Check for and log errors, but not too often. 2718 */ 2719 if (--sio_timeouts_until_log > 0) 2720 return; 2721 sio_timeouts_until_log = hz / sio_timeout; 2722 for (unit = 0; unit < sio_numunits; ++unit) { 2723 int errnum; 2724 2725 com = com_addr(unit); 2726 if (com == NULL) 2727 continue; 2728 if (com->gone) 2729 continue; 2730 for (errnum = 0; errnum < CE_NTYPES; ++errnum) { 2731 u_int delta; 2732 u_long total; 2733 2734 mtx_lock_spin(&sio_lock); 2735 delta = com->delta_error_counts[errnum]; 2736 com->delta_error_counts[errnum] = 0; 2737 mtx_unlock_spin(&sio_lock); 2738 if (delta == 0) 2739 continue; 2740 total = com->error_counts[errnum] += delta; 2741 log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n", 2742 unit, delta, error_desc[errnum], 2743 delta == 1 ? "" : "s", total); 2744 } 2745 } 2746} 2747 2748static void 2749disc_optim(tp, t, com) 2750 struct tty *tp; 2751 struct termios *t; 2752 struct com_s *com; 2753{ 2754 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON)) 2755 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK)) 2756 && (!(t->c_iflag & PARMRK) 2757 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK)) 2758 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN)) 2759 && linesw[tp->t_line].l_rint == ttyinput) 2760 tp->t_state |= TS_CAN_BYPASS_L_RINT; 2761 else 2762 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 2763 com->hotchar = linesw[tp->t_line].l_hotchar; 2764} 2765 2766/* 2767 * Following are all routines needed for SIO to act as console 2768 */ 2769#include <sys/cons.h> 2770 2771struct siocnstate { 2772 u_char dlbl; 2773 u_char dlbh; 2774 u_char ier; 2775 u_char cfcr; 2776 u_char mcr; 2777}; 2778 2779#ifndef __alpha__ 2780static speed_t siocngetspeed(Port_t, u_long rclk); 2781#endif 2782static void siocnclose(struct siocnstate *sp, Port_t iobase); 2783static void siocnopen(struct siocnstate *sp, Port_t iobase, int speed); 2784static void siocntxwait(Port_t iobase); 2785 2786#ifdef __alpha__ 2787int siocnattach(int port, int speed); 2788int siogdbattach(int port, int speed); 2789int siogdbgetc(void); 2790void siogdbputc(int c); 2791#else 2792static cn_probe_t siocnprobe; 2793static cn_init_t siocninit; 2794static cn_term_t siocnterm; 2795#endif 2796static cn_checkc_t siocncheckc; 2797static cn_getc_t siocngetc; 2798static cn_putc_t siocnputc; 2799 2800#ifndef __alpha__ 2801CONS_DRIVER(sio, siocnprobe, siocninit, siocnterm, siocngetc, siocncheckc, 2802 siocnputc, NULL); 2803#endif 2804 2805/* To get the GDB related variables */ 2806#if DDB > 0 2807#include <ddb/ddb.h> 2808static struct consdev gdbconsdev; 2809 2810#endif 2811 2812static void 2813siocntxwait(iobase) 2814 Port_t iobase; 2815{ 2816 int timo; 2817 2818 /* 2819 * Wait for any pending transmission to finish. Required to avoid 2820 * the UART lockup bug when the speed is changed, and for normal 2821 * transmits. 2822 */ 2823 timo = 100000; 2824 while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY)) 2825 != (LSR_TSRE | LSR_TXRDY) && --timo != 0) 2826 ; 2827} 2828 2829#ifndef __alpha__ 2830 2831/* 2832 * Read the serial port specified and try to figure out what speed 2833 * it's currently running at. We're assuming the serial port has 2834 * been initialized and is basicly idle. This routine is only intended 2835 * to be run at system startup. 2836 * 2837 * If the value read from the serial port doesn't make sense, return 0. 2838 */ 2839 2840static speed_t 2841siocngetspeed(iobase, rclk) 2842 Port_t iobase; 2843 u_long rclk; 2844{ 2845 u_int divisor; 2846 u_char dlbh; 2847 u_char dlbl; 2848 u_char cfcr; 2849 2850 cfcr = inb(iobase + com_cfcr); 2851 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 2852 2853 dlbl = inb(iobase + com_dlbl); 2854 dlbh = inb(iobase + com_dlbh); 2855 2856 outb(iobase + com_cfcr, cfcr); 2857 2858 divisor = dlbh << 8 | dlbl; 2859 2860 /* XXX there should be more sanity checking. */ 2861 if (divisor == 0) 2862 return (CONSPEED); 2863 return (rclk / (16UL * divisor)); 2864} 2865 2866#endif 2867 2868static void 2869siocnopen(sp, iobase, speed) 2870 struct siocnstate *sp; 2871 Port_t iobase; 2872 int speed; 2873{ 2874 u_int divisor; 2875 u_char dlbh; 2876 u_char dlbl; 2877 2878 /* 2879 * Save all the device control registers except the fifo register 2880 * and set our default ones (cs8 -parenb speed=comdefaultrate). 2881 * We can't save the fifo register since it is read-only. 2882 */ 2883 sp->ier = inb(iobase + com_ier); 2884 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */ 2885 siocntxwait(iobase); 2886 sp->cfcr = inb(iobase + com_cfcr); 2887 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 2888 sp->dlbl = inb(iobase + com_dlbl); 2889 sp->dlbh = inb(iobase + com_dlbh); 2890 /* 2891 * Only set the divisor registers if they would change, since on 2892 * some 16550 incompatibles (Startech), setting them clears the 2893 * data input register. This also reduces the effects of the 2894 * UMC8669F bug. 2895 */ 2896 divisor = siodivisor(comdefaultrclk, speed); 2897 dlbl = divisor & 0xFF; 2898 if (sp->dlbl != dlbl) 2899 outb(iobase + com_dlbl, dlbl); 2900 dlbh = divisor >> 8; 2901 if (sp->dlbh != dlbh) 2902 outb(iobase + com_dlbh, dlbh); 2903 outb(iobase + com_cfcr, CFCR_8BITS); 2904 sp->mcr = inb(iobase + com_mcr); 2905 /* 2906 * We don't want interrupts, but must be careful not to "disable" 2907 * them by clearing the MCR_IENABLE bit, since that might cause 2908 * an interrupt by floating the IRQ line. 2909 */ 2910 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS); 2911} 2912 2913static void 2914siocnclose(sp, iobase) 2915 struct siocnstate *sp; 2916 Port_t iobase; 2917{ 2918 /* 2919 * Restore the device control registers. 2920 */ 2921 siocntxwait(iobase); 2922 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 2923 if (sp->dlbl != inb(iobase + com_dlbl)) 2924 outb(iobase + com_dlbl, sp->dlbl); 2925 if (sp->dlbh != inb(iobase + com_dlbh)) 2926 outb(iobase + com_dlbh, sp->dlbh); 2927 outb(iobase + com_cfcr, sp->cfcr); 2928 /* 2929 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them. 2930 */ 2931 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS); 2932 outb(iobase + com_ier, sp->ier); 2933} 2934 2935#ifndef __alpha__ 2936 2937static void 2938siocnprobe(cp) 2939 struct consdev *cp; 2940{ 2941 speed_t boot_speed; 2942 u_char cfcr; 2943 u_int divisor; 2944 int s, unit; 2945 struct siocnstate sp; 2946 2947 /* 2948 * Find our first enabled console, if any. If it is a high-level 2949 * console device, then initialize it and return successfully. 2950 * If it is a low-level console device, then initialize it and 2951 * return unsuccessfully. It must be initialized in both cases 2952 * for early use by console drivers and debuggers. Initializing 2953 * the hardware is not necessary in all cases, since the i/o 2954 * routines initialize it on the fly, but it is necessary if 2955 * input might arrive while the hardware is switched back to an 2956 * uninitialized state. We can't handle multiple console devices 2957 * yet because our low-level routines don't take a device arg. 2958 * We trust the user to set the console flags properly so that we 2959 * don't need to probe. 2960 */ 2961 cp->cn_pri = CN_DEAD; 2962 2963 for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */ 2964 int flags; 2965 int disabled; 2966 if (resource_int_value("sio", unit, "disabled", &disabled) == 0) { 2967 if (disabled) 2968 continue; 2969 } 2970 if (resource_int_value("sio", unit, "flags", &flags)) 2971 continue; 2972 if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) { 2973 int port; 2974 Port_t iobase; 2975 2976 if (resource_int_value("sio", unit, "port", &port)) 2977 continue; 2978 iobase = port; 2979 s = spltty(); 2980 if (boothowto & RB_SERIAL) { 2981 boot_speed = 2982 siocngetspeed(iobase, comdefaultrclk); 2983 if (boot_speed) 2984 comdefaultrate = boot_speed; 2985 } 2986 2987 /* 2988 * Initialize the divisor latch. We can't rely on 2989 * siocnopen() to do this the first time, since it 2990 * avoids writing to the latch if the latch appears 2991 * to have the correct value. Also, if we didn't 2992 * just read the speed from the hardware, then we 2993 * need to set the speed in hardware so that 2994 * switching it later is null. 2995 */ 2996 cfcr = inb(iobase + com_cfcr); 2997 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 2998 divisor = siodivisor(comdefaultrclk, comdefaultrate); 2999 outb(iobase + com_dlbl, divisor & 0xff); 3000 outb(iobase + com_dlbh, divisor >> 8); 3001 outb(iobase + com_cfcr, cfcr); 3002 3003 siocnopen(&sp, iobase, comdefaultrate); 3004 3005 splx(s); 3006 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) { 3007 cp->cn_dev = makedev(CDEV_MAJOR, unit); 3008 cp->cn_pri = COM_FORCECONSOLE(flags) 3009 || boothowto & RB_SERIAL 3010 ? CN_REMOTE : CN_NORMAL; 3011 siocniobase = iobase; 3012 siocnunit = unit; 3013 } 3014 if (COM_DEBUGGER(flags)) { 3015 printf("sio%d: gdb debugging port\n", unit); 3016 siogdbiobase = iobase; 3017 siogdbunit = unit; 3018#if DDB > 0 3019 gdbconsdev.cn_dev = makedev(CDEV_MAJOR, unit); 3020 gdb_arg = &gdbconsdev; 3021 gdb_getc = siocngetc; 3022 gdb_putc = siocnputc; 3023#endif 3024 } 3025 } 3026 } 3027#ifdef __i386__ 3028#if DDB > 0 3029 /* 3030 * XXX Ugly Compatability. 3031 * If no gdb port has been specified, set it to be the console 3032 * as some configuration files don't specify the gdb port. 3033 */ 3034 if (gdb_arg == NULL && (boothowto & RB_GDB)) { 3035 printf("Warning: no GDB port specified. Defaulting to sio%d.\n", 3036 siocnunit); 3037 printf("Set flag 0x80 on desired GDB port in your\n"); 3038 printf("configuration file (currently sio only).\n"); 3039 siogdbiobase = siocniobase; 3040 siogdbunit = siocnunit; 3041 gdbconsdev.cn_dev = makedev(CDEV_MAJOR, siocnunit); 3042 gdb_arg = &gdbconsdev; 3043 gdb_getc = siocngetc; 3044 gdb_putc = siocnputc; 3045 } 3046#endif 3047#endif 3048} 3049 3050static void 3051siocninit(cp) 3052 struct consdev *cp; 3053{ 3054 comconsole = DEV_TO_UNIT(cp->cn_dev); 3055} 3056 3057static void 3058siocnterm(cp) 3059 struct consdev *cp; 3060{ 3061 comconsole = -1; 3062} 3063 3064#endif 3065 3066#ifdef __alpha__ 3067 3068CONS_DRIVER(sio, NULL, NULL, NULL, siocngetc, siocncheckc, siocnputc, NULL); 3069 3070int 3071siocnattach(port, speed) 3072 int port; 3073 int speed; 3074{ 3075 int s; 3076 u_char cfcr; 3077 u_int divisor; 3078 struct siocnstate sp; 3079 int unit = 0; /* XXX random value! */ 3080 3081 siocniobase = port; 3082 siocnunit = unit; 3083 comdefaultrate = speed; 3084 sio_consdev.cn_pri = CN_NORMAL; 3085 sio_consdev.cn_dev = makedev(CDEV_MAJOR, unit); 3086 3087 s = spltty(); 3088 3089 /* 3090 * Initialize the divisor latch. We can't rely on 3091 * siocnopen() to do this the first time, since it 3092 * avoids writing to the latch if the latch appears 3093 * to have the correct value. Also, if we didn't 3094 * just read the speed from the hardware, then we 3095 * need to set the speed in hardware so that 3096 * switching it later is null. 3097 */ 3098 cfcr = inb(siocniobase + com_cfcr); 3099 outb(siocniobase + com_cfcr, CFCR_DLAB | cfcr); 3100 divisor = siodivisor(comdefaultrclk, comdefaultrate); 3101 outb(siocniobase + com_dlbl, divisor & 0xff); 3102 outb(siocniobase + com_dlbh, divisor >> 8); 3103 outb(siocniobase + com_cfcr, cfcr); 3104 3105 siocnopen(&sp, siocniobase, comdefaultrate); 3106 splx(s); 3107 3108 cnadd(&sio_consdev); 3109 return (0); 3110} 3111 3112int 3113siogdbattach(port, speed) 3114 int port; 3115 int speed; 3116{ 3117 int s; 3118 u_char cfcr; 3119 u_int divisor; 3120 struct siocnstate sp; 3121 int unit = 1; /* XXX random value! */ 3122 3123 siogdbiobase = port; 3124 gdbdefaultrate = speed; 3125 3126 printf("sio%d: gdb debugging port\n", unit); 3127 siogdbunit = unit; 3128#if DDB > 0 3129 gdbconsdev.cn_dev = makedev(CDEV_MAJOR, unit); 3130 gdb_arg = &gdbconsdev; 3131 gdb_getc = siocngetc; 3132 gdb_putc = siocnputc; 3133#endif 3134 3135 s = spltty(); 3136 3137 /* 3138 * Initialize the divisor latch. We can't rely on 3139 * siocnopen() to do this the first time, since it 3140 * avoids writing to the latch if the latch appears 3141 * to have the correct value. Also, if we didn't 3142 * just read the speed from the hardware, then we 3143 * need to set the speed in hardware so that 3144 * switching it later is null. 3145 */ 3146 cfcr = inb(siogdbiobase + com_cfcr); 3147 outb(siogdbiobase + com_cfcr, CFCR_DLAB | cfcr); 3148 divisor = siodivisor(comdefaultrclk, gdbdefaultrate); 3149 outb(siogdbiobase + com_dlbl, divisor & 0xff); 3150 outb(siogdbiobase + com_dlbh, divisor >> 8); 3151 outb(siogdbiobase + com_cfcr, cfcr); 3152 3153 siocnopen(&sp, siogdbiobase, gdbdefaultrate); 3154 splx(s); 3155 3156 return (0); 3157} 3158 3159#endif 3160 3161static int 3162siocncheckc(struct consdev *cd) 3163{ 3164 int c; 3165 dev_t dev; 3166 Port_t iobase; 3167 int s; 3168 struct siocnstate sp; 3169 speed_t speed; 3170 3171 dev = cd->cn_dev; 3172 if (minor(dev) == siocnunit) { 3173 iobase = siocniobase; 3174 speed = comdefaultrate; 3175 } else { 3176 iobase = siogdbiobase; 3177 speed = gdbdefaultrate; 3178 } 3179 s = spltty(); 3180 siocnopen(&sp, iobase, speed); 3181 if (inb(iobase + com_lsr) & LSR_RXRDY) 3182 c = inb(iobase + com_data); 3183 else 3184 c = -1; 3185 siocnclose(&sp, iobase); 3186 splx(s); 3187 return (c); 3188} 3189 3190 3191static int 3192siocngetc(struct consdev *cd) 3193{ 3194 int c; 3195 dev_t dev; 3196 Port_t iobase; 3197 int s; 3198 struct siocnstate sp; 3199 speed_t speed; 3200 3201 dev = cd->cn_dev; 3202 if (minor(dev) == siocnunit) { 3203 iobase = siocniobase; 3204 speed = comdefaultrate; 3205 } else { 3206 iobase = siogdbiobase; 3207 speed = gdbdefaultrate; 3208 } 3209 s = spltty(); 3210 siocnopen(&sp, iobase, speed); 3211 while (!(inb(iobase + com_lsr) & LSR_RXRDY)) 3212 ; 3213 c = inb(iobase + com_data); 3214 siocnclose(&sp, iobase); 3215 splx(s); 3216 return (c); 3217} 3218 3219static void 3220siocnputc(struct consdev *cd, int c) 3221{ 3222 int need_unlock; 3223 int s; 3224 dev_t dev; 3225 struct siocnstate sp; 3226 Port_t iobase; 3227 speed_t speed; 3228 3229 dev = cd->cn_dev; 3230 if (minor(dev) == siocnunit) { 3231 iobase = siocniobase; 3232 speed = comdefaultrate; 3233 } else { 3234 iobase = siogdbiobase; 3235 speed = gdbdefaultrate; 3236 } 3237 s = spltty(); 3238 need_unlock = 0; 3239 if (sio_inited == 2 && !mtx_owned(&sio_lock)) { 3240 mtx_lock_spin(&sio_lock); 3241 need_unlock = 1; 3242 } 3243 siocnopen(&sp, iobase, speed); 3244 siocntxwait(iobase); 3245 outb(iobase + com_data, c); 3246 siocnclose(&sp, iobase); 3247 if (need_unlock) 3248 mtx_unlock_spin(&sio_lock); 3249 splx(s); 3250} 3251 3252#ifdef __alpha__ 3253int 3254siogdbgetc() 3255{ 3256 int c; 3257 Port_t iobase; 3258 speed_t speed; 3259 int s; 3260 struct siocnstate sp; 3261 3262 if (siogdbunit == siocnunit) { 3263 iobase = siocniobase; 3264 speed = comdefaultrate; 3265 } else { 3266 iobase = siogdbiobase; 3267 speed = gdbdefaultrate; 3268 } 3269 3270 s = spltty(); 3271 siocnopen(&sp, iobase, speed); 3272 while (!(inb(iobase + com_lsr) & LSR_RXRDY)) 3273 ; 3274 c = inb(iobase + com_data); 3275 siocnclose(&sp, iobase); 3276 splx(s); 3277 return (c); 3278} 3279 3280void 3281siogdbputc(c) 3282 int c; 3283{ 3284 Port_t iobase; 3285 speed_t speed; 3286 int s; 3287 struct siocnstate sp; 3288 3289 if (siogdbunit == siocnunit) { 3290 iobase = siocniobase; 3291 speed = comdefaultrate; 3292 } else { 3293 iobase = siogdbiobase; 3294 speed = gdbdefaultrate; 3295 } 3296 3297 s = spltty(); 3298 siocnopen(&sp, iobase, speed); 3299 siocntxwait(siogdbiobase); 3300 outb(siogdbiobase + com_data, c); 3301 siocnclose(&sp, siogdbiobase); 3302 splx(s); 3303} 3304#endif 3305