1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 4. Neither the name of the University nor the names of its contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: @(#)com.c 7.5 (Berkeley) 5/16/91 30 * from: i386/isa sio.c,v 1.234 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD$"); 35 36#include "opt_compat.h" 37#include "opt_gdb.h" 38#include "opt_kdb.h" 39#include "opt_sio.h" 40 41/* 42 * Serial driver, based on 386BSD-0.1 com driver. 43 * Mostly rewritten to use pseudo-DMA. 44 * Works for National Semiconductor NS8250-NS16550AF UARTs. 45 * COM driver, based on HP dca driver. 46 * 47 * Changes for PC Card integration: 48 * - Added PC Card driver table and handlers 49 */ 50#include <sys/param.h> 51#include <sys/systm.h> 52#include <sys/bus.h> 53#include <sys/conf.h> 54#include <sys/fcntl.h> 55#include <sys/interrupt.h> 56#include <sys/kdb.h> 57#include <sys/kernel.h> 58#include <sys/limits.h> 59#include <sys/lock.h> 60#include <sys/malloc.h> 61#include <sys/module.h> 62#include <sys/mutex.h> 63#include <sys/proc.h> 64#include <sys/reboot.h> 65#include <sys/serial.h> 66#include <sys/sysctl.h> 67#include <sys/syslog.h> 68#include <sys/tty.h> 69#include <machine/bus.h> 70#include <sys/rman.h> 71#include <sys/timepps.h> 72#include <sys/uio.h> 73#include <sys/cons.h> 74 75#include <isa/isavar.h> 76 77#include <machine/resource.h> 78 79#include <dev/sio/sioreg.h> 80#include <dev/sio/siovar.h> 81 82#ifdef COM_ESP 83#include <dev/ic/esp.h> 84#endif 85#include <dev/ic/ns16550.h> 86 87#define LOTS_OF_EVENTS 64 /* helps separate urgent events from input */ 88 89#ifdef COM_MULTIPORT 90/* checks in flags for multiport and which is multiport "master chip" 91 * for a given card 92 */ 93#define COM_ISMULTIPORT(flags) ((flags) & 0x01) 94#define COM_MPMASTER(flags) (((flags) >> 8) & 0x0ff) 95#define COM_NOTAST4(flags) ((flags) & 0x04) 96#else 97#define COM_ISMULTIPORT(flags) (0) 98#endif /* COM_MULTIPORT */ 99 100#define COM_C_IIR_TXRDYBUG 0x80000 101#define COM_CONSOLE(flags) ((flags) & 0x10) 102#define COM_DEBUGGER(flags) ((flags) & 0x80) 103#define COM_FIFOSIZE(flags) (((flags) & 0xff000000) >> 24) 104#define COM_FORCECONSOLE(flags) ((flags) & 0x20) 105#define COM_IIR_TXRDYBUG(flags) ((flags) & COM_C_IIR_TXRDYBUG) 106#define COM_LLCONSOLE(flags) ((flags) & 0x40) 107#define COM_LOSESOUTINTS(flags) ((flags) & 0x08) 108#define COM_NOFIFO(flags) ((flags) & 0x02) 109#define COM_NOPROBE(flags) ((flags) & 0x40000) 110#define COM_NOSCR(flags) ((flags) & 0x100000) 111#define COM_PPSCTS(flags) ((flags) & 0x10000) 112#define COM_ST16650A(flags) ((flags) & 0x20000) 113#define COM_TI16754(flags) ((flags) & 0x200000) 114 115#define sio_getreg(com, off) \ 116 (bus_space_read_1((com)->bst, (com)->bsh, (off))) 117#define sio_setreg(com, off, value) \ 118 (bus_space_write_1((com)->bst, (com)->bsh, (off), (value))) 119 120/* 121 * com state bits. 122 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher 123 * than the other bits so that they can be tested as a group without masking 124 * off the low bits. 125 * 126 * The following com and tty flags correspond closely: 127 * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and 128 * comstop()) 129 * CS_TTGO = ~TS_TTSTOP (maintained by comparam() and comstart()) 130 * CS_CTS_OFLOW = CCTS_OFLOW (maintained by comparam()) 131 * CS_RTS_IFLOW = CRTS_IFLOW (maintained by comparam()) 132 * TS_FLUSH is not used. 133 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON. 134 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state). 135 */ 136#define CS_BUSY 0x80 /* output in progress */ 137#define CS_TTGO 0x40 /* output not stopped by XOFF */ 138#define CS_ODEVREADY 0x20 /* external device h/w ready (CTS) */ 139#define CS_CHECKMSR 1 /* check of MSR scheduled */ 140#define CS_CTS_OFLOW 2 /* use CTS output flow control */ 141#define CS_ODONE 4 /* output completed */ 142#define CS_RTS_IFLOW 8 /* use RTS input flow control */ 143#define CSE_BUSYCHECK 1 /* siobusycheck() scheduled */ 144 145static char const * const error_desc[] = { 146#define CE_OVERRUN 0 147 "silo overflow", 148#define CE_INTERRUPT_BUF_OVERFLOW 1 149 "interrupt-level buffer overflow", 150#define CE_TTY_BUF_OVERFLOW 2 151 "tty-level buffer overflow", 152}; 153 154#define CE_NTYPES 3 155#define CE_RECORD(com, errnum) (++(com)->delta_error_counts[errnum]) 156 157/* types. XXX - should be elsewhere */ 158typedef u_int Port_t; /* hardware port */ 159typedef u_char bool_t; /* boolean */ 160 161/* queue of linear buffers */ 162struct lbq { 163 u_char *l_head; /* next char to process */ 164 u_char *l_tail; /* one past the last char to process */ 165 struct lbq *l_next; /* next in queue */ 166 bool_t l_queued; /* nonzero if queued */ 167}; 168 169/* com device structure */ 170struct com_s { 171 u_char state; /* miscellaneous flag bits */ 172 u_char cfcr_image; /* copy of value written to CFCR */ 173#ifdef COM_ESP 174 bool_t esp; /* is this unit a hayes esp board? */ 175#endif 176 u_char extra_state; /* more flag bits, separate for order trick */ 177 u_char fifo_image; /* copy of value written to FIFO */ 178 bool_t hasfifo; /* nonzero for 16550 UARTs */ 179 bool_t loses_outints; /* nonzero if device loses output interrupts */ 180 u_char mcr_image; /* copy of value written to MCR */ 181#ifdef COM_MULTIPORT 182 bool_t multiport; /* is this unit part of a multiport device? */ 183#endif /* COM_MULTIPORT */ 184 bool_t no_irq; /* nonzero if irq is not attached */ 185 bool_t gone; /* hardware disappeared */ 186 bool_t poll; /* nonzero if polling is required */ 187 bool_t poll_output; /* nonzero if polling for output is required */ 188 bool_t st16650a; /* nonzero if Startech 16650A compatible */ 189 int unit; /* unit number */ 190 u_int flags; /* copy of device flags */ 191 u_int tx_fifo_size; 192 193 /* 194 * The high level of the driver never reads status registers directly 195 * because there would be too many side effects to handle conveniently. 196 * Instead, it reads copies of the registers stored here by the 197 * interrupt handler. 198 */ 199 u_char last_modem_status; /* last MSR read by intr handler */ 200 u_char prev_modem_status; /* last MSR handled by high level */ 201 202 u_char *ibuf; /* start of input buffer */ 203 u_char *ibufend; /* end of input buffer */ 204 u_char *ibufold; /* old input buffer, to be freed */ 205 u_char *ihighwater; /* threshold in input buffer */ 206 u_char *iptr; /* next free spot in input buffer */ 207 int ibufsize; /* size of ibuf (not include error bytes) */ 208 int ierroff; /* offset of error bytes in ibuf */ 209 210 struct lbq obufq; /* head of queue of output buffers */ 211 struct lbq obufs[2]; /* output buffers */ 212 213 bus_space_tag_t bst; 214 bus_space_handle_t bsh; 215 216 Port_t data_port; /* i/o ports */ 217#ifdef COM_ESP 218 Port_t esp_port; 219#endif 220 Port_t int_ctl_port; 221 Port_t int_id_port; 222 Port_t modem_ctl_port; 223 Port_t line_status_port; 224 Port_t modem_status_port; 225 226 struct tty *tp; /* cross reference */ 227 228 struct pps_state pps; 229 int pps_bit; 230#ifdef KDB 231 int alt_brk_state; 232#endif 233 234 u_long bytes_in; /* statistics */ 235 u_long bytes_out; 236 u_int delta_error_counts[CE_NTYPES]; 237 u_long error_counts[CE_NTYPES]; 238 239 u_long rclk; 240 241 struct resource *irqres; 242 struct resource *ioportres; 243 int ioportrid; 244 void *cookie; 245 246 /* 247 * Data area for output buffers. Someday we should build the output 248 * buffer queue without copying data. 249 */ 250 u_char obuf1[256]; 251 u_char obuf2[256]; 252}; 253 254#ifdef COM_ESP 255static int espattach(struct com_s *com, Port_t esp_port); 256#endif 257 258static void combreak(struct tty *tp, int sig); 259static timeout_t siobusycheck; 260static u_int siodivisor(u_long rclk, speed_t speed); 261static void comclose(struct tty *tp); 262static int comopen(struct tty *tp, struct cdev *dev); 263static void sioinput(struct com_s *com); 264static void siointr1(struct com_s *com); 265static int siointr(void *arg); 266static int commodem(struct tty *tp, int sigon, int sigoff); 267static int comparam(struct tty *tp, struct termios *t); 268static void siopoll(void *); 269static void siosettimeout(void); 270static int siosetwater(struct com_s *com, speed_t speed); 271static void comstart(struct tty *tp); 272static void comstop(struct tty *tp, int rw); 273static timeout_t comwakeup; 274 275char sio_driver_name[] = "sio"; 276static struct mtx sio_lock; 277static int sio_inited; 278 279/* table and macro for fast conversion from a unit number to its com struct */ 280devclass_t sio_devclass; 281#define com_addr(unit) ((struct com_s *) \ 282 devclass_get_softc(sio_devclass, unit)) /* XXX */ 283 284int comconsole = -1; 285static volatile speed_t comdefaultrate = CONSPEED; 286static u_long comdefaultrclk = DEFAULT_RCLK; 287SYSCTL_ULONG(_machdep, OID_AUTO, conrclk, CTLFLAG_RW, &comdefaultrclk, 0, ""); 288static speed_t gdbdefaultrate = GDBSPEED; 289SYSCTL_UINT(_machdep, OID_AUTO, gdbspeed, CTLFLAG_RW, 290 &gdbdefaultrate, GDBSPEED, ""); 291static u_int com_events; /* input chars + weighted output completions */ 292static Port_t siocniobase; 293static int siocnunit = -1; 294static void *sio_slow_ih; 295static void *sio_fast_ih; 296static int sio_timeout; 297static int sio_timeouts_until_log; 298static struct callout_handle sio_timeout_handle 299 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle); 300static int sio_numunits; 301 302#ifdef GDB 303static Port_t siogdbiobase = 0; 304#endif 305 306#ifdef COM_ESP 307/* XXX configure this properly. */ 308/* XXX quite broken for new-bus. */ 309static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, }; 310static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 }; 311#endif 312 313/* 314 * handle sysctl read/write requests for console speed 315 * 316 * In addition to setting comdefaultrate for I/O through /dev/console, 317 * also set the initial and lock values for the /dev/ttyXX device 318 * if there is one associated with the console. Finally, if the /dev/tty 319 * device has already been open, change the speed on the open running port 320 * itself. 321 */ 322 323static int 324sysctl_machdep_comdefaultrate(SYSCTL_HANDLER_ARGS) 325{ 326 int error, s; 327 speed_t newspeed; 328 struct com_s *com; 329 struct tty *tp; 330 331 newspeed = comdefaultrate; 332 333 error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req); 334 if (error || !req->newptr) 335 return (error); 336 337 comdefaultrate = newspeed; 338 339 if (comconsole < 0) /* serial console not selected? */ 340 return (0); 341 342 com = com_addr(comconsole); 343 if (com == NULL) 344 return (ENXIO); 345 346 tp = com->tp; 347 if (tp == NULL) 348 return (ENXIO); 349 350 /* 351 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX 352 * (note, the lock rates really are boolean -- if non-zero, disallow 353 * speed changes) 354 */ 355 tp->t_init_in.c_ispeed = tp->t_init_in.c_ospeed = 356 tp->t_lock_in.c_ispeed = tp->t_lock_in.c_ospeed = 357 tp->t_init_out.c_ispeed = tp->t_init_out.c_ospeed = 358 tp->t_lock_out.c_ispeed = tp->t_lock_out.c_ospeed = comdefaultrate; 359 360 if (tp->t_state & TS_ISOPEN) { 361 tp->t_termios.c_ispeed = 362 tp->t_termios.c_ospeed = comdefaultrate; 363 s = spltty(); 364 error = comparam(tp, &tp->t_termios); 365 splx(s); 366 } 367 return error; 368} 369 370SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW, 371 0, 0, sysctl_machdep_comdefaultrate, "I", ""); 372TUNABLE_INT("machdep.conspeed", __DEVOLATILE(int *, &comdefaultrate)); 373 374#define SET_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) | (bit)) 375#define CLR_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) & ~(bit)) 376 377/* 378 * Unload the driver and clear the table. 379 * XXX this is mostly wrong. 380 * XXX TODO: 381 * This is usually called when the card is ejected, but 382 * can be caused by a kldunload of a controller driver. 383 * The idea is to reset the driver's view of the device 384 * and ensure that any driver entry points such as 385 * read and write do not hang. 386 */ 387int 388siodetach(device_t dev) 389{ 390 struct com_s *com; 391 392 com = (struct com_s *) device_get_softc(dev); 393 if (com == NULL) { 394 device_printf(dev, "NULL com in siounload\n"); 395 return (0); 396 } 397 com->gone = TRUE; 398 if (com->tp) 399 ttyfree(com->tp); 400 if (com->irqres) { 401 bus_teardown_intr(dev, com->irqres, com->cookie); 402 bus_release_resource(dev, SYS_RES_IRQ, 0, com->irqres); 403 } 404 if (com->ioportres) 405 bus_release_resource(dev, SYS_RES_IOPORT, com->ioportrid, 406 com->ioportres); 407 if (com->ibuf != NULL) 408 free(com->ibuf, M_DEVBUF); 409 410 device_set_softc(dev, NULL); 411 free(com, M_DEVBUF); 412 return (0); 413} 414 415int 416sioprobe(dev, xrid, rclk, noprobe) 417 device_t dev; 418 int xrid; 419 u_long rclk; 420 int noprobe; 421{ 422#if 0 423 static bool_t already_init; 424 device_t xdev; 425#endif 426 struct com_s *com; 427 u_int divisor; 428 bool_t failures[10]; 429 int fn; 430 device_t idev; 431 Port_t iobase; 432 intrmask_t irqmap[4]; 433 intrmask_t irqs; 434 u_char mcr_image; 435 int result; 436 u_long xirq; 437 u_int flags = device_get_flags(dev); 438 int rid; 439 struct resource *port; 440 441 rid = xrid; 442 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 443 0, ~0, IO_COMSIZE, RF_ACTIVE); 444 if (!port) 445 return (ENXIO); 446 447 com = malloc(sizeof(*com), M_DEVBUF, M_NOWAIT | M_ZERO); 448 if (com == NULL) { 449 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 450 return (ENOMEM); 451 } 452 device_set_softc(dev, com); 453 com->bst = rman_get_bustag(port); 454 com->bsh = rman_get_bushandle(port); 455 if (rclk == 0) 456 rclk = DEFAULT_RCLK; 457 com->rclk = rclk; 458 459 while (sio_inited != 2) 460 if (atomic_cmpset_int(&sio_inited, 0, 1)) { 461 mtx_init(&sio_lock, sio_driver_name, NULL, 462 (comconsole != -1) ? 463 MTX_SPIN | MTX_QUIET : MTX_SPIN); 464 atomic_store_rel_int(&sio_inited, 2); 465 } 466 467#if 0 468 /* 469 * XXX this is broken - when we are first called, there are no 470 * previously configured IO ports. We could hard code 471 * 0x3f8, 0x2f8, 0x3e8, 0x2e8 etc but that's probably worse. 472 * This code has been doing nothing since the conversion since 473 * "count" is zero the first time around. 474 */ 475 if (!already_init) { 476 /* 477 * Turn off MCR_IENABLE for all likely serial ports. An unused 478 * port with its MCR_IENABLE gate open will inhibit interrupts 479 * from any used port that shares the interrupt vector. 480 * XXX the gate enable is elsewhere for some multiports. 481 */ 482 device_t *devs; 483 int count, i, xioport; 484 485 devclass_get_devices(sio_devclass, &devs, &count); 486 for (i = 0; i < count; i++) { 487 xdev = devs[i]; 488 if (device_is_enabled(xdev) && 489 bus_get_resource(xdev, SYS_RES_IOPORT, 0, &xioport, 490 NULL) == 0) 491 outb(xioport + com_mcr, 0); 492 } 493 free(devs, M_TEMP); 494 already_init = TRUE; 495 } 496#endif 497 498 if (COM_LLCONSOLE(flags)) { 499 printf("sio%d: reserved for low-level i/o\n", 500 device_get_unit(dev)); 501 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 502 device_set_softc(dev, NULL); 503 free(com, M_DEVBUF); 504 return (ENXIO); 505 } 506 507 /* 508 * If the device is on a multiport card and has an AST/4 509 * compatible interrupt control register, initialize this 510 * register and prepare to leave MCR_IENABLE clear in the mcr. 511 * Otherwise, prepare to set MCR_IENABLE in the mcr. 512 * Point idev to the device struct giving the correct id_irq. 513 * This is the struct for the master device if there is one. 514 */ 515 idev = dev; 516 mcr_image = MCR_IENABLE; 517#ifdef COM_MULTIPORT 518 if (COM_ISMULTIPORT(flags)) { 519 Port_t xiobase; 520 u_long io; 521 522 idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags)); 523 if (idev == NULL) { 524 printf("sio%d: master device %d not configured\n", 525 device_get_unit(dev), COM_MPMASTER(flags)); 526 idev = dev; 527 } 528 if (!COM_NOTAST4(flags)) { 529 if (bus_get_resource(idev, SYS_RES_IOPORT, 0, &io, 530 NULL) == 0) { 531 xiobase = io; 532 if (bus_get_resource(idev, SYS_RES_IRQ, 0, 533 NULL, NULL) == 0) 534 outb(xiobase + com_scr, 0x80); 535 else 536 outb(xiobase + com_scr, 0); 537 } 538 mcr_image = 0; 539 } 540 } 541#endif /* COM_MULTIPORT */ 542 if (bus_get_resource(idev, SYS_RES_IRQ, 0, NULL, NULL) != 0) 543 mcr_image = 0; 544 545 bzero(failures, sizeof failures); 546 iobase = rman_get_start(port); 547 548 /* 549 * We don't want to get actual interrupts, just masked ones. 550 * Interrupts from this line should already be masked in the ICU, 551 * but mask them in the processor as well in case there are some 552 * (misconfigured) shared interrupts. 553 */ 554 mtx_lock_spin(&sio_lock); 555/* EXTRA DELAY? */ 556 557 /* 558 * For the TI16754 chips, set prescaler to 1 (4 is often the 559 * default after-reset value) as otherwise it's impossible to 560 * get highest baudrates. 561 */ 562 if (COM_TI16754(flags)) { 563 u_char cfcr, efr; 564 565 cfcr = sio_getreg(com, com_cfcr); 566 sio_setreg(com, com_cfcr, CFCR_EFR_ENABLE); 567 efr = sio_getreg(com, com_efr); 568 /* Unlock extended features to turn off prescaler. */ 569 sio_setreg(com, com_efr, efr | EFR_EFE); 570 /* Disable EFR. */ 571 sio_setreg(com, com_cfcr, (cfcr != CFCR_EFR_ENABLE) ? cfcr : 0); 572 /* Turn off prescaler. */ 573 sio_setreg(com, com_mcr, 574 sio_getreg(com, com_mcr) & ~MCR_PRESCALE); 575 sio_setreg(com, com_cfcr, CFCR_EFR_ENABLE); 576 sio_setreg(com, com_efr, efr); 577 sio_setreg(com, com_cfcr, cfcr); 578 } 579 580 /* 581 * Initialize the speed and the word size and wait long enough to 582 * drain the maximum of 16 bytes of junk in device output queues. 583 * The speed is undefined after a master reset and must be set 584 * before relying on anything related to output. There may be 585 * junk after a (very fast) soft reboot and (apparently) after 586 * master reset. 587 * XXX what about the UART bug avoided by waiting in comparam()? 588 * We don't want to to wait long enough to drain at 2 bps. 589 */ 590 if (iobase == siocniobase) 591 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10)); 592 else { 593 sio_setreg(com, com_cfcr, CFCR_DLAB | CFCR_8BITS); 594 divisor = siodivisor(rclk, SIO_TEST_SPEED); 595 sio_setreg(com, com_dlbl, divisor & 0xff); 596 sio_setreg(com, com_dlbh, divisor >> 8); 597 sio_setreg(com, com_cfcr, CFCR_8BITS); 598 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10)); 599 } 600 601 /* 602 * Enable the interrupt gate and disable device interrupts. This 603 * should leave the device driving the interrupt line low and 604 * guarantee an edge trigger if an interrupt can be generated. 605 */ 606/* EXTRA DELAY? */ 607 sio_setreg(com, com_mcr, mcr_image); 608 sio_setreg(com, com_ier, 0); 609 DELAY(1000); /* XXX */ 610 irqmap[0] = isa_irq_pending(); 611 612 /* 613 * Attempt to set loopback mode so that we can send a null byte 614 * without annoying any external device. 615 */ 616/* EXTRA DELAY? */ 617 sio_setreg(com, com_mcr, mcr_image | MCR_LOOPBACK); 618 619 /* 620 * Attempt to generate an output interrupt. On 8250's, setting 621 * IER_ETXRDY generates an interrupt independent of the current 622 * setting and independent of whether the THR is empty. On 16450's, 623 * setting IER_ETXRDY generates an interrupt independent of the 624 * current setting. On 16550A's, setting IER_ETXRDY only 625 * generates an interrupt when IER_ETXRDY is not already set. 626 */ 627 sio_setreg(com, com_ier, IER_ETXRDY); 628 629 /* 630 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate 631 * an interrupt. They'd better generate one for actually doing 632 * output. Loopback may be broken on the same incompatibles but 633 * it's unlikely to do more than allow the null byte out. 634 */ 635 sio_setreg(com, com_data, 0); 636 if (iobase == siocniobase) 637 DELAY((1 + 2) * 1000000 / (comdefaultrate / 10)); 638 else 639 DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10)); 640 641 /* 642 * Turn off loopback mode so that the interrupt gate works again 643 * (MCR_IENABLE was hidden). This should leave the device driving 644 * an interrupt line high. It doesn't matter if the interrupt 645 * line oscillates while we are not looking at it, since interrupts 646 * are disabled. 647 */ 648/* EXTRA DELAY? */ 649 sio_setreg(com, com_mcr, mcr_image); 650 651 /* 652 * It seems my Xircom CBEM56G Cardbus modem wants to be reset 653 * to 8 bits *again*, or else probe test 0 will fail. 654 * gwk@sgi.com, 4/19/2001 655 */ 656 sio_setreg(com, com_cfcr, CFCR_8BITS); 657 658 /* 659 * Some PCMCIA cards (Palido 321s, DC-1S, ...) have the "TXRDY bug", 660 * so we probe for a buggy IIR_TXRDY implementation even in the 661 * noprobe case. We don't probe for it in the !noprobe case because 662 * noprobe is always set for PCMCIA cards and the problem is not 663 * known to affect any other cards. 664 */ 665 if (noprobe) { 666 /* Read IIR a few times. */ 667 for (fn = 0; fn < 2; fn ++) { 668 DELAY(10000); 669 failures[6] = sio_getreg(com, com_iir); 670 } 671 672 /* IIR_TXRDY should be clear. Is it? */ 673 result = 0; 674 if (failures[6] & IIR_TXRDY) { 675 /* 676 * No. We seem to have the bug. Does our fix for 677 * it work? 678 */ 679 sio_setreg(com, com_ier, 0); 680 if (sio_getreg(com, com_iir) & IIR_NOPEND) { 681 /* Yes. We discovered the TXRDY bug! */ 682 SET_FLAG(dev, COM_C_IIR_TXRDYBUG); 683 } else { 684 /* No. Just fail. XXX */ 685 result = ENXIO; 686 sio_setreg(com, com_mcr, 0); 687 } 688 } else { 689 /* Yes. No bug. */ 690 CLR_FLAG(dev, COM_C_IIR_TXRDYBUG); 691 } 692 sio_setreg(com, com_ier, 0); 693 sio_setreg(com, com_cfcr, CFCR_8BITS); 694 mtx_unlock_spin(&sio_lock); 695 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 696 if (iobase == siocniobase) 697 result = 0; 698 /* 699 * XXX: Since we don't return 0, we shouldn't be relying on 700 * the softc that we set to persist to the call to attach 701 * since other probe routines may be called, and the malloc 702 * here causes subr_bus to not allocate anything for the 703 * other probes. Instead, this softc is preserved and other 704 * probe routines can corrupt it. 705 */ 706 if (result != 0) { 707 device_set_softc(dev, NULL); 708 free(com, M_DEVBUF); 709 } 710 return (result == 0 ? BUS_PROBE_DEFAULT + 1 : result); 711 } 712 713 /* 714 * Check that 715 * o the CFCR, IER and MCR in UART hold the values written to them 716 * (the values happen to be all distinct - this is good for 717 * avoiding false positive tests from bus echoes). 718 * o an output interrupt is generated and its vector is correct. 719 * o the interrupt goes away when the IIR in the UART is read. 720 */ 721/* EXTRA DELAY? */ 722 failures[0] = sio_getreg(com, com_cfcr) - CFCR_8BITS; 723 failures[1] = sio_getreg(com, com_ier) - IER_ETXRDY; 724 failures[2] = sio_getreg(com, com_mcr) - mcr_image; 725 DELAY(10000); /* Some internal modems need this time */ 726 irqmap[1] = isa_irq_pending(); 727 failures[4] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_TXRDY; 728 DELAY(1000); /* XXX */ 729 irqmap[2] = isa_irq_pending(); 730 failures[6] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND; 731 732 /* 733 * Turn off all device interrupts and check that they go off properly. 734 * Leave MCR_IENABLE alone. For ports without a master port, it gates 735 * the OUT2 output of the UART to 736 * the ICU input. Closing the gate would give a floating ICU input 737 * (unless there is another device driving it) and spurious interrupts. 738 * (On the system that this was first tested on, the input floats high 739 * and gives a (masked) interrupt as soon as the gate is closed.) 740 */ 741 sio_setreg(com, com_ier, 0); 742 sio_setreg(com, com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */ 743 failures[7] = sio_getreg(com, com_ier); 744 DELAY(1000); /* XXX */ 745 irqmap[3] = isa_irq_pending(); 746 failures[9] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND; 747 748 mtx_unlock_spin(&sio_lock); 749 750 irqs = irqmap[1] & ~irqmap[0]; 751 if (bus_get_resource(idev, SYS_RES_IRQ, 0, &xirq, NULL) == 0 && 752 ((1 << xirq) & irqs) == 0) { 753 printf( 754 "sio%d: configured irq %ld not in bitmap of probed irqs %#x\n", 755 device_get_unit(dev), xirq, irqs); 756 printf( 757 "sio%d: port may not be enabled\n", 758 device_get_unit(dev)); 759 } 760 if (bootverbose) 761 printf("sio%d: irq maps: %#x %#x %#x %#x\n", 762 device_get_unit(dev), 763 irqmap[0], irqmap[1], irqmap[2], irqmap[3]); 764 765 result = 0; 766 for (fn = 0; fn < sizeof failures; ++fn) 767 if (failures[fn]) { 768 sio_setreg(com, com_mcr, 0); 769 result = ENXIO; 770 if (bootverbose) { 771 printf("sio%d: probe failed test(s):", 772 device_get_unit(dev)); 773 for (fn = 0; fn < sizeof failures; ++fn) 774 if (failures[fn]) 775 printf(" %d", fn); 776 printf("\n"); 777 } 778 break; 779 } 780 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 781 if (iobase == siocniobase) 782 result = 0; 783 /* 784 * XXX: Since we don't return 0, we shouldn't be relying on the softc 785 * that we set to persist to the call to attach since other probe 786 * routines may be called, and the malloc here causes subr_bus to not 787 * allocate anything for the other probes. Instead, this softc is 788 * preserved and other probe routines can corrupt it. 789 */ 790 if (result != 0) { 791 device_set_softc(dev, NULL); 792 free(com, M_DEVBUF); 793 } 794 return (result == 0 ? BUS_PROBE_DEFAULT + 1 : result); 795} 796 797#ifdef COM_ESP 798static int 799espattach(com, esp_port) 800 struct com_s *com; 801 Port_t esp_port; 802{ 803 u_char dips; 804 u_char val; 805 806 /* 807 * Check the ESP-specific I/O port to see if we're an ESP 808 * card. If not, return failure immediately. 809 */ 810 if ((inb(esp_port) & 0xf3) == 0) { 811 printf(" port 0x%x is not an ESP board?\n", esp_port); 812 return (0); 813 } 814 815 /* 816 * We've got something that claims to be a Hayes ESP card. 817 * Let's hope so. 818 */ 819 820 /* Get the dip-switch configuration */ 821 outb(esp_port + ESP_CMD1, ESP_GETDIPS); 822 dips = inb(esp_port + ESP_STATUS1); 823 824 /* 825 * Bits 0,1 of dips say which COM port we are. 826 */ 827 if (rman_get_start(com->ioportres) == likely_com_ports[dips & 0x03]) 828 printf(" : ESP"); 829 else { 830 printf(" esp_port has com %d\n", dips & 0x03); 831 return (0); 832 } 833 834 /* 835 * Check for ESP version 2.0 or later: bits 4,5,6 = 010. 836 */ 837 outb(esp_port + ESP_CMD1, ESP_GETTEST); 838 val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */ 839 val = inb(esp_port + ESP_STATUS2); 840 if ((val & 0x70) < 0x20) { 841 printf("-old (%o)", val & 0x70); 842 return (0); 843 } 844 845 /* 846 * Check for ability to emulate 16550: bit 7 == 1 847 */ 848 if ((dips & 0x80) == 0) { 849 printf(" slave"); 850 return (0); 851 } 852 853 /* 854 * Okay, we seem to be a Hayes ESP card. Whee. 855 */ 856 com->esp = TRUE; 857 com->esp_port = esp_port; 858 return (1); 859} 860#endif /* COM_ESP */ 861 862int 863sioattach(dev, xrid, rclk) 864 device_t dev; 865 int xrid; 866 u_long rclk; 867{ 868 struct com_s *com; 869#ifdef COM_ESP 870 Port_t *espp; 871#endif 872 Port_t iobase; 873 int unit; 874 u_int flags; 875 int rid; 876 struct resource *port; 877 int ret; 878 int error; 879 struct tty *tp; 880 881 rid = xrid; 882 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 883 0, ~0, IO_COMSIZE, RF_ACTIVE); 884 if (!port) 885 return (ENXIO); 886 887 iobase = rman_get_start(port); 888 unit = device_get_unit(dev); 889 com = device_get_softc(dev); 890 flags = device_get_flags(dev); 891 892 if (unit >= sio_numunits) 893 sio_numunits = unit + 1; 894 /* 895 * sioprobe() has initialized the device registers as follows: 896 * o cfcr = CFCR_8BITS. 897 * It is most important that CFCR_DLAB is off, so that the 898 * data port is not hidden when we enable interrupts. 899 * o ier = 0. 900 * Interrupts are only enabled when the line is open. 901 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible 902 * interrupt control register or the config specifies no irq. 903 * Keeping MCR_DTR and MCR_RTS off might stop the external 904 * device from sending before we are ready. 905 */ 906 bzero(com, sizeof *com); 907 com->unit = unit; 908 com->ioportres = port; 909 com->ioportrid = rid; 910 com->bst = rman_get_bustag(port); 911 com->bsh = rman_get_bushandle(port); 912 com->cfcr_image = CFCR_8BITS; 913 com->loses_outints = COM_LOSESOUTINTS(flags) != 0; 914 com->no_irq = bus_get_resource(dev, SYS_RES_IRQ, 0, NULL, NULL) != 0; 915 com->tx_fifo_size = 1; 916 com->obufs[0].l_head = com->obuf1; 917 com->obufs[1].l_head = com->obuf2; 918 919 com->data_port = iobase + com_data; 920 com->int_ctl_port = iobase + com_ier; 921 com->int_id_port = iobase + com_iir; 922 com->modem_ctl_port = iobase + com_mcr; 923 com->mcr_image = inb(com->modem_ctl_port); 924 com->line_status_port = iobase + com_lsr; 925 com->modem_status_port = iobase + com_msr; 926 927 tp = com->tp = ttyalloc(); 928 tp->t_oproc = comstart; 929 tp->t_param = comparam; 930 tp->t_stop = comstop; 931 tp->t_modem = commodem; 932 tp->t_break = combreak; 933 tp->t_close = comclose; 934 tp->t_open = comopen; 935 tp->t_sc = com; 936 937 if (rclk == 0) 938 rclk = DEFAULT_RCLK; 939 com->rclk = rclk; 940 941 if (unit == comconsole) 942 ttyconsolemode(tp, comdefaultrate); 943 error = siosetwater(com, tp->t_init_in.c_ispeed); 944 mtx_unlock_spin(&sio_lock); 945 if (error) { 946 /* 947 * Leave i/o resources allocated if this is a `cn'-level 948 * console, so that other devices can't snarf them. 949 */ 950 if (iobase != siocniobase) 951 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 952 return (ENOMEM); 953 } 954 955 /* attempt to determine UART type */ 956 printf("sio%d: type", unit); 957 958 if (!COM_ISMULTIPORT(flags) && 959 !COM_IIR_TXRDYBUG(flags) && !COM_NOSCR(flags)) { 960 u_char scr; 961 u_char scr1; 962 u_char scr2; 963 964 scr = sio_getreg(com, com_scr); 965 sio_setreg(com, com_scr, 0xa5); 966 scr1 = sio_getreg(com, com_scr); 967 sio_setreg(com, com_scr, 0x5a); 968 scr2 = sio_getreg(com, com_scr); 969 sio_setreg(com, com_scr, scr); 970 if (scr1 != 0xa5 || scr2 != 0x5a) { 971 printf(" 8250 or not responding"); 972 goto determined_type; 973 } 974 } 975 sio_setreg(com, com_fifo, FIFO_ENABLE | FIFO_RX_HIGH); 976 DELAY(100); 977 switch (inb(com->int_id_port) & IIR_FIFO_MASK) { 978 case FIFO_RX_LOW: 979 printf(" 16450"); 980 break; 981 case FIFO_RX_MEDL: 982 printf(" 16450?"); 983 break; 984 case FIFO_RX_MEDH: 985 printf(" 16550?"); 986 break; 987 case FIFO_RX_HIGH: 988 if (COM_NOFIFO(flags)) { 989 printf(" 16550A fifo disabled"); 990 break; 991 } 992 com->hasfifo = TRUE; 993 if (COM_ST16650A(flags)) { 994 printf(" ST16650A"); 995 com->st16650a = TRUE; 996 com->tx_fifo_size = 32; 997 break; 998 } 999 if (COM_TI16754(flags)) { 1000 printf(" TI16754"); 1001 com->tx_fifo_size = 64; 1002 break; 1003 } 1004 printf(" 16550A"); 1005#ifdef COM_ESP 1006 for (espp = likely_esp_ports; *espp != 0; espp++) 1007 if (espattach(com, *espp)) { 1008 com->tx_fifo_size = 1024; 1009 break; 1010 } 1011 if (com->esp) 1012 break; 1013#endif 1014 com->tx_fifo_size = COM_FIFOSIZE(flags); 1015 if (com->tx_fifo_size == 0) 1016 com->tx_fifo_size = 16; 1017 else 1018 printf(" lookalike with %u bytes FIFO", 1019 com->tx_fifo_size); 1020 break; 1021 } 1022#ifdef COM_ESP 1023 if (com->esp) { 1024 /* 1025 * Set 16550 compatibility mode. 1026 * We don't use the ESP_MODE_SCALE bit to increase the 1027 * fifo trigger levels because we can't handle large 1028 * bursts of input. 1029 * XXX flow control should be set in comparam(), not here. 1030 */ 1031 outb(com->esp_port + ESP_CMD1, ESP_SETMODE); 1032 outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO); 1033 1034 /* Set RTS/CTS flow control. */ 1035 outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE); 1036 outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS); 1037 outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS); 1038 1039 /* Set flow-control levels. */ 1040 outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW); 1041 outb(com->esp_port + ESP_CMD2, HIBYTE(768)); 1042 outb(com->esp_port + ESP_CMD2, LOBYTE(768)); 1043 outb(com->esp_port + ESP_CMD2, HIBYTE(512)); 1044 outb(com->esp_port + ESP_CMD2, LOBYTE(512)); 1045 } 1046#endif /* COM_ESP */ 1047 sio_setreg(com, com_fifo, 0); 1048determined_type: ; 1049 1050#ifdef COM_MULTIPORT 1051 if (COM_ISMULTIPORT(flags)) { 1052 device_t masterdev; 1053 1054 com->multiport = TRUE; 1055 printf(" (multiport"); 1056 if (unit == COM_MPMASTER(flags)) 1057 printf(" master"); 1058 printf(")"); 1059 masterdev = devclass_get_device(sio_devclass, 1060 COM_MPMASTER(flags)); 1061 com->no_irq = (masterdev == NULL || bus_get_resource(masterdev, 1062 SYS_RES_IRQ, 0, NULL, NULL) != 0); 1063 } 1064#endif /* COM_MULTIPORT */ 1065 if (unit == comconsole) 1066 printf(", console"); 1067 if (COM_IIR_TXRDYBUG(flags)) 1068 printf(" with a buggy IIR_TXRDY implementation"); 1069 printf("\n"); 1070 1071 if (sio_fast_ih == NULL) { 1072 swi_add(&tty_intr_event, "sio", siopoll, NULL, SWI_TTY, 0, 1073 &sio_fast_ih); 1074 swi_add(&clk_intr_event, "sio", siopoll, NULL, SWI_CLOCK, 0, 1075 &sio_slow_ih); 1076 } 1077 1078 com->flags = flags; 1079 com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 1080 tp->t_pps = &com->pps; 1081 1082 if (COM_PPSCTS(flags)) 1083 com->pps_bit = MSR_CTS; 1084 else 1085 com->pps_bit = MSR_DCD; 1086 pps_init(&com->pps); 1087 1088 rid = 0; 1089 com->irqres = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); 1090 if (com->irqres) { 1091 ret = bus_setup_intr(dev, com->irqres, 1092 INTR_TYPE_TTY, 1093 siointr, NULL, com, 1094 &com->cookie); 1095 if (ret) { 1096 ret = bus_setup_intr(dev, 1097 com->irqres, INTR_TYPE_TTY, 1098 NULL, (driver_intr_t *)siointr, com, &com->cookie); 1099 if (ret == 0) 1100 device_printf(dev, "unable to activate interrupt in fast mode - using normal mode\n"); 1101 } 1102 if (ret) 1103 device_printf(dev, "could not activate interrupt\n"); 1104#if defined(KDB) 1105 /* 1106 * Enable interrupts for early break-to-debugger support 1107 * on the console. 1108 */ 1109 if (ret == 0 && unit == comconsole) 1110 outb(siocniobase + com_ier, IER_ERXRDY | IER_ERLS | 1111 IER_EMSC); 1112#endif 1113 } 1114 1115 /* We're ready, open the doors... */ 1116 ttycreate(tp, TS_CALLOUT, "d%r", unit); 1117 1118 return (0); 1119} 1120 1121static int 1122comopen(struct tty *tp, struct cdev *dev) 1123{ 1124 struct com_s *com; 1125 int i; 1126 1127 com = tp->t_sc; 1128 com->poll = com->no_irq; 1129 com->poll_output = com->loses_outints; 1130 if (com->hasfifo) { 1131 /* 1132 * (Re)enable and drain fifos. 1133 * 1134 * Certain SMC chips cause problems if the fifos 1135 * are enabled while input is ready. Turn off the 1136 * fifo if necessary to clear the input. We test 1137 * the input ready bit after enabling the fifos 1138 * since we've already enabled them in comparam() 1139 * and to handle races between enabling and fresh 1140 * input. 1141 */ 1142 for (i = 0; i < 500; i++) { 1143 sio_setreg(com, com_fifo, 1144 FIFO_RCV_RST | FIFO_XMT_RST 1145 | com->fifo_image); 1146 /* 1147 * XXX the delays are for superstitious 1148 * historical reasons. It must be less than 1149 * the character time at the maximum 1150 * supported speed (87 usec at 115200 bps 1151 * 8N1). Otherwise we might loop endlessly 1152 * if data is streaming in. We used to use 1153 * delays of 100. That usually worked 1154 * because DELAY(100) used to usually delay 1155 * for about 85 usec instead of 100. 1156 */ 1157 DELAY(50); 1158 if (!(inb(com->line_status_port) & LSR_RXRDY)) 1159 break; 1160 sio_setreg(com, com_fifo, 0); 1161 DELAY(50); 1162 (void) inb(com->data_port); 1163 } 1164 if (i == 500) 1165 return (EIO); 1166 } 1167 1168 mtx_lock_spin(&sio_lock); 1169 (void) inb(com->line_status_port); 1170 (void) inb(com->data_port); 1171 com->prev_modem_status = com->last_modem_status 1172 = inb(com->modem_status_port); 1173 outb(com->int_ctl_port, 1174 IER_ERXRDY | IER_ERLS | IER_EMSC 1175 | (COM_IIR_TXRDYBUG(com->flags) ? 0 : IER_ETXRDY)); 1176 mtx_unlock_spin(&sio_lock); 1177 siosettimeout(); 1178 /* XXX: should be generic ? */ 1179 if (com->prev_modem_status & MSR_DCD || ISCALLOUT(dev)) 1180 ttyld_modem(tp, 1); 1181 return (0); 1182} 1183 1184static void 1185comclose(tp) 1186 struct tty *tp; 1187{ 1188 int s; 1189 struct com_s *com; 1190 1191 s = spltty(); 1192 com = tp->t_sc; 1193 com->poll = FALSE; 1194 com->poll_output = FALSE; 1195 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 1196 1197#if defined(KDB) 1198 /* 1199 * Leave interrupts enabled and don't clear DTR if this is the 1200 * console. This allows us to detect break-to-debugger events 1201 * while the console device is closed. 1202 */ 1203 if (com->unit != comconsole) 1204#endif 1205 { 1206 sio_setreg(com, com_ier, 0); 1207 if (tp->t_cflag & HUPCL 1208 /* 1209 * XXX we will miss any carrier drop between here and the 1210 * next open. Perhaps we should watch DCD even when the 1211 * port is closed; it is not sufficient to check it at 1212 * the next open because it might go up and down while 1213 * we're not watching. 1214 */ 1215 || (!tp->t_actout 1216 && !(com->prev_modem_status & MSR_DCD) 1217 && !(tp->t_init_in.c_cflag & CLOCAL)) 1218 || !(tp->t_state & TS_ISOPEN)) { 1219 (void)commodem(tp, 0, SER_DTR); 1220 ttydtrwaitstart(tp); 1221 } 1222 } 1223 if (com->hasfifo) { 1224 /* 1225 * Disable fifos so that they are off after controlled 1226 * reboots. Some BIOSes fail to detect 16550s when the 1227 * fifos are enabled. 1228 */ 1229 sio_setreg(com, com_fifo, 0); 1230 } 1231 tp->t_actout = FALSE; 1232 wakeup(&tp->t_actout); 1233 wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */ 1234 siosettimeout(); 1235 splx(s); 1236} 1237 1238static void 1239siobusycheck(chan) 1240 void *chan; 1241{ 1242 struct com_s *com; 1243 int s; 1244 1245 com = (struct com_s *)chan; 1246 1247 /* 1248 * Clear TS_BUSY if low-level output is complete. 1249 * spl locking is sufficient because siointr1() does not set CS_BUSY. 1250 * If siointr1() clears CS_BUSY after we look at it, then we'll get 1251 * called again. Reading the line status port outside of siointr1() 1252 * is safe because CS_BUSY is clear so there are no output interrupts 1253 * to lose. 1254 */ 1255 s = spltty(); 1256 if (com->state & CS_BUSY) 1257 com->extra_state &= ~CSE_BUSYCHECK; /* False alarm. */ 1258 else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY)) 1259 == (LSR_TSRE | LSR_TXRDY)) { 1260 com->tp->t_state &= ~TS_BUSY; 1261 ttwwakeup(com->tp); 1262 com->extra_state &= ~CSE_BUSYCHECK; 1263 } else 1264 timeout(siobusycheck, com, hz / 100); 1265 splx(s); 1266} 1267 1268static u_int 1269siodivisor(rclk, speed) 1270 u_long rclk; 1271 speed_t speed; 1272{ 1273 long actual_speed; 1274 u_int divisor; 1275 int error; 1276 1277 if (speed == 0) 1278 return (0); 1279#if UINT_MAX > (ULONG_MAX - 1) / 8 1280 if (speed > (ULONG_MAX - 1) / 8) 1281 return (0); 1282#endif 1283 divisor = (rclk / (8UL * speed) + 1) / 2; 1284 if (divisor == 0 || divisor >= 65536) 1285 return (0); 1286 actual_speed = rclk / (16UL * divisor); 1287 1288 /* 10 times error in percent: */ 1289 error = ((actual_speed - (long)speed) * 2000 / (long)speed + 1) / 2; 1290 1291 /* 3.0% maximum error tolerance: */ 1292 if (error < -30 || error > 30) 1293 return (0); 1294 1295 return (divisor); 1296} 1297 1298/* 1299 * Call this function with the sio_lock mutex held. It will return with the 1300 * lock still held. 1301 */ 1302static void 1303sioinput(com) 1304 struct com_s *com; 1305{ 1306 u_char *buf; 1307 int incc; 1308 u_char line_status; 1309 int recv_data; 1310 struct tty *tp; 1311 1312 buf = com->ibuf; 1313 tp = com->tp; 1314 if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) { 1315 com_events -= (com->iptr - com->ibuf); 1316 com->iptr = com->ibuf; 1317 return; 1318 } 1319 if (tp->t_state & TS_CAN_BYPASS_L_RINT) { 1320 /* 1321 * Avoid the grotesquely inefficient lineswitch routine 1322 * (ttyinput) in "raw" mode. It usually takes about 450 1323 * instructions (that's without canonical processing or echo!). 1324 * slinput is reasonably fast (usually 40 instructions plus 1325 * call overhead). 1326 */ 1327 do { 1328 /* 1329 * This may look odd, but it is using save-and-enable 1330 * semantics instead of the save-and-disable semantics 1331 * that are used everywhere else. 1332 */ 1333 mtx_unlock_spin(&sio_lock); 1334 incc = com->iptr - buf; 1335 if (tp->t_rawq.c_cc + incc > tp->t_ihiwat 1336 && (com->state & CS_RTS_IFLOW 1337 || tp->t_iflag & IXOFF) 1338 && !(tp->t_state & TS_TBLOCK)) 1339 ttyblock(tp); 1340 com->delta_error_counts[CE_TTY_BUF_OVERFLOW] 1341 += b_to_q((char *)buf, incc, &tp->t_rawq); 1342 buf += incc; 1343 tk_nin += incc; 1344 tk_rawcc += incc; 1345 tp->t_rawcc += incc; 1346 ttwakeup(tp); 1347 if (tp->t_state & TS_TTSTOP 1348 && (tp->t_iflag & IXANY 1349 || tp->t_cc[VSTART] == tp->t_cc[VSTOP])) { 1350 tp->t_state &= ~TS_TTSTOP; 1351 tp->t_lflag &= ~FLUSHO; 1352 comstart(tp); 1353 } 1354 mtx_lock_spin(&sio_lock); 1355 } while (buf < com->iptr); 1356 } else { 1357 do { 1358 /* 1359 * This may look odd, but it is using save-and-enable 1360 * semantics instead of the save-and-disable semantics 1361 * that are used everywhere else. 1362 */ 1363 mtx_unlock_spin(&sio_lock); 1364 line_status = buf[com->ierroff]; 1365 recv_data = *buf++; 1366 if (line_status 1367 & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) { 1368 if (line_status & LSR_BI) 1369 recv_data |= TTY_BI; 1370 if (line_status & LSR_FE) 1371 recv_data |= TTY_FE; 1372 if (line_status & LSR_OE) 1373 recv_data |= TTY_OE; 1374 if (line_status & LSR_PE) 1375 recv_data |= TTY_PE; 1376 } 1377 ttyld_rint(tp, recv_data); 1378 mtx_lock_spin(&sio_lock); 1379 } while (buf < com->iptr); 1380 } 1381 com_events -= (com->iptr - com->ibuf); 1382 com->iptr = com->ibuf; 1383 1384 /* 1385 * There is now room for another low-level buffer full of input, 1386 * so enable RTS if it is now disabled and there is room in the 1387 * high-level buffer. 1388 */ 1389 if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) && 1390 !(tp->t_state & TS_TBLOCK)) 1391 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 1392} 1393 1394static int 1395siointr(arg) 1396 void *arg; 1397{ 1398 struct com_s *com; 1399 1400#ifndef COM_MULTIPORT 1401 com = (struct com_s *)arg; 1402 1403 mtx_lock_spin(&sio_lock); 1404 siointr1(com); 1405 mtx_unlock_spin(&sio_lock); 1406#else /* COM_MULTIPORT */ 1407 bool_t possibly_more_intrs; 1408 int unit; 1409 1410 /* 1411 * Loop until there is no activity on any port. This is necessary 1412 * to get an interrupt edge more than to avoid another interrupt. 1413 * If the IRQ signal is just an OR of the IRQ signals from several 1414 * devices, then the edge from one may be lost because another is 1415 * on. 1416 */ 1417 mtx_lock_spin(&sio_lock); 1418 do { 1419 possibly_more_intrs = FALSE; 1420 for (unit = 0; unit < sio_numunits; ++unit) { 1421 com = com_addr(unit); 1422 /* 1423 * XXX COM_LOCK(); 1424 * would it work here, or be counter-productive? 1425 */ 1426 if (com != NULL 1427 && !com->gone 1428 && (inb(com->int_id_port) & IIR_IMASK) 1429 != IIR_NOPEND) { 1430 siointr1(com); 1431 possibly_more_intrs = TRUE; 1432 } 1433 /* XXX COM_UNLOCK(); */ 1434 } 1435 } while (possibly_more_intrs); 1436 mtx_unlock_spin(&sio_lock); 1437#endif /* COM_MULTIPORT */ 1438 return(FILTER_HANDLED); 1439} 1440 1441static struct timespec siots[8]; 1442static int siotso; 1443static int volatile siotsunit = -1; 1444 1445static int 1446sysctl_siots(SYSCTL_HANDLER_ARGS) 1447{ 1448 char buf[128]; 1449 long long delta; 1450 size_t len; 1451 int error, i, tso; 1452 1453 for (i = 1, tso = siotso; i < tso; i++) { 1454 delta = (long long)(siots[i].tv_sec - siots[i - 1].tv_sec) * 1455 1000000000 + 1456 (siots[i].tv_nsec - siots[i - 1].tv_nsec); 1457 len = sprintf(buf, "%lld\n", delta); 1458 if (delta >= 110000) 1459 len += sprintf(buf + len - 1, ": *** %ld.%09ld\n", 1460 (long)siots[i].tv_sec, siots[i].tv_nsec) - 1; 1461 if (i == tso - 1) 1462 buf[len - 1] = '\0'; 1463 error = SYSCTL_OUT(req, buf, len); 1464 if (error != 0) 1465 return (error); 1466 } 1467 return (0); 1468} 1469 1470SYSCTL_PROC(_machdep, OID_AUTO, siots, CTLTYPE_STRING | CTLFLAG_RD, 1471 0, 0, sysctl_siots, "A", "sio timestamps"); 1472 1473static void 1474siointr1(com) 1475 struct com_s *com; 1476{ 1477 u_char int_ctl; 1478 u_char int_ctl_new; 1479 u_char line_status; 1480 u_char modem_status; 1481 u_char *ioptr; 1482 u_char recv_data; 1483 1484#ifdef KDB 1485again: 1486#endif 1487 1488 if (COM_IIR_TXRDYBUG(com->flags)) { 1489 int_ctl = inb(com->int_ctl_port); 1490 int_ctl_new = int_ctl; 1491 } else { 1492 int_ctl = 0; 1493 int_ctl_new = 0; 1494 } 1495 1496 while (!com->gone) { 1497 if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) { 1498 modem_status = inb(com->modem_status_port); 1499 if ((modem_status ^ com->last_modem_status) & 1500 com->pps_bit) { 1501 pps_capture(&com->pps); 1502 pps_event(&com->pps, 1503 (modem_status & com->pps_bit) ? 1504 PPS_CAPTUREASSERT : PPS_CAPTURECLEAR); 1505 } 1506 } 1507 line_status = inb(com->line_status_port); 1508 1509 /* input event? (check first to help avoid overruns) */ 1510 while (line_status & LSR_RCV_MASK) { 1511 /* break/unnattached error bits or real input? */ 1512 if (!(line_status & LSR_RXRDY)) 1513 recv_data = 0; 1514 else 1515 recv_data = inb(com->data_port); 1516#ifdef KDB 1517 if (com->unit == comconsole && 1518 kdb_alt_break(recv_data, &com->alt_brk_state) != 0) 1519 goto again; 1520#endif /* KDB */ 1521 if (line_status & (LSR_BI | LSR_FE | LSR_PE)) { 1522 /* 1523 * Don't store BI if IGNBRK or FE/PE if IGNPAR. 1524 * Otherwise, push the work to a higher level 1525 * (to handle PARMRK) if we're bypassing. 1526 * Otherwise, convert BI/FE and PE+INPCK to 0. 1527 * 1528 * This makes bypassing work right in the 1529 * usual "raw" case (IGNBRK set, and IGNPAR 1530 * and INPCK clear). 1531 * 1532 * Note: BI together with FE/PE means just BI. 1533 */ 1534 if (line_status & LSR_BI) { 1535#if defined(KDB) 1536 if (com->unit == comconsole) { 1537 kdb_break(); 1538 goto cont; 1539 } 1540#endif 1541 if (com->tp == NULL 1542 || com->tp->t_iflag & IGNBRK) 1543 goto cont; 1544 } else { 1545 if (com->tp == NULL 1546 || com->tp->t_iflag & IGNPAR) 1547 goto cont; 1548 } 1549 if (com->tp->t_state & TS_CAN_BYPASS_L_RINT 1550 && (line_status & (LSR_BI | LSR_FE) 1551 || com->tp->t_iflag & INPCK)) 1552 recv_data = 0; 1553 } 1554 ++com->bytes_in; 1555 if (com->tp != NULL && 1556 com->tp->t_hotchar != 0 && recv_data == com->tp->t_hotchar) 1557 swi_sched(sio_fast_ih, 0); 1558 ioptr = com->iptr; 1559 if (ioptr >= com->ibufend) 1560 CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW); 1561 else { 1562 if (com->tp != NULL && com->tp->t_do_timestamp) 1563 microtime(&com->tp->t_timestamp); 1564 ++com_events; 1565 swi_sched(sio_slow_ih, SWI_DELAY); 1566#if 0 /* for testing input latency vs efficiency */ 1567if (com->iptr - com->ibuf == 8) 1568 swi_sched(sio_fast_ih, 0); 1569#endif 1570 ioptr[0] = recv_data; 1571 ioptr[com->ierroff] = line_status; 1572 com->iptr = ++ioptr; 1573 if (ioptr == com->ihighwater 1574 && com->state & CS_RTS_IFLOW) 1575 outb(com->modem_ctl_port, 1576 com->mcr_image &= ~MCR_RTS); 1577 if (line_status & LSR_OE) 1578 CE_RECORD(com, CE_OVERRUN); 1579 } 1580cont: 1581 if (line_status & LSR_TXRDY 1582 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) 1583 goto txrdy; 1584 1585 /* 1586 * "& 0x7F" is to avoid the gcc-1.40 generating a slow 1587 * jump from the top of the loop to here 1588 */ 1589 line_status = inb(com->line_status_port) & 0x7F; 1590 } 1591 1592 /* modem status change? (always check before doing output) */ 1593 modem_status = inb(com->modem_status_port); 1594 if (modem_status != com->last_modem_status) { 1595 /* 1596 * Schedule high level to handle DCD changes. Note 1597 * that we don't use the delta bits anywhere. Some 1598 * UARTs mess them up, and it's easy to remember the 1599 * previous bits and calculate the delta. 1600 */ 1601 com->last_modem_status = modem_status; 1602 if (!(com->state & CS_CHECKMSR)) { 1603 com_events += LOTS_OF_EVENTS; 1604 com->state |= CS_CHECKMSR; 1605 swi_sched(sio_fast_ih, 0); 1606 } 1607 1608 /* handle CTS change immediately for crisp flow ctl */ 1609 if (com->state & CS_CTS_OFLOW) { 1610 if (modem_status & MSR_CTS) 1611 com->state |= CS_ODEVREADY; 1612 else 1613 com->state &= ~CS_ODEVREADY; 1614 } 1615 } 1616 1617txrdy: 1618 /* output queued and everything ready? */ 1619 if (line_status & LSR_TXRDY 1620 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) { 1621 ioptr = com->obufq.l_head; 1622 if (com->tx_fifo_size > 1 && com->unit != siotsunit) { 1623 u_int ocount; 1624 1625 ocount = com->obufq.l_tail - ioptr; 1626 if (ocount > com->tx_fifo_size) 1627 ocount = com->tx_fifo_size; 1628 com->bytes_out += ocount; 1629 do 1630 outb(com->data_port, *ioptr++); 1631 while (--ocount != 0); 1632 } else { 1633 outb(com->data_port, *ioptr++); 1634 ++com->bytes_out; 1635 if (com->unit == siotsunit 1636 && siotso < sizeof siots / sizeof siots[0]) 1637 nanouptime(&siots[siotso++]); 1638 } 1639 com->obufq.l_head = ioptr; 1640 if (COM_IIR_TXRDYBUG(com->flags)) 1641 int_ctl_new = int_ctl | IER_ETXRDY; 1642 if (ioptr >= com->obufq.l_tail) { 1643 struct lbq *qp; 1644 1645 qp = com->obufq.l_next; 1646 qp->l_queued = FALSE; 1647 qp = qp->l_next; 1648 if (qp != NULL) { 1649 com->obufq.l_head = qp->l_head; 1650 com->obufq.l_tail = qp->l_tail; 1651 com->obufq.l_next = qp; 1652 } else { 1653 /* output just completed */ 1654 if (COM_IIR_TXRDYBUG(com->flags)) 1655 int_ctl_new = int_ctl 1656 & ~IER_ETXRDY; 1657 com->state &= ~CS_BUSY; 1658 } 1659 if (!(com->state & CS_ODONE)) { 1660 com_events += LOTS_OF_EVENTS; 1661 com->state |= CS_ODONE; 1662 /* handle at high level ASAP */ 1663 swi_sched(sio_fast_ih, 0); 1664 } 1665 } 1666 if (COM_IIR_TXRDYBUG(com->flags) 1667 && int_ctl != int_ctl_new) 1668 outb(com->int_ctl_port, int_ctl_new); 1669 } 1670 1671 /* finished? */ 1672#ifndef COM_MULTIPORT 1673 if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND) 1674#endif /* COM_MULTIPORT */ 1675 return; 1676 } 1677} 1678 1679/* software interrupt handler for SWI_TTY */ 1680static void 1681siopoll(void *dummy) 1682{ 1683 int unit; 1684 1685 if (com_events == 0) 1686 return; 1687repeat: 1688 for (unit = 0; unit < sio_numunits; ++unit) { 1689 struct com_s *com; 1690 int incc; 1691 struct tty *tp; 1692 1693 com = com_addr(unit); 1694 if (com == NULL) 1695 continue; 1696 tp = com->tp; 1697 if (tp == NULL || com->gone) { 1698 /* 1699 * Discard any events related to never-opened or 1700 * going-away devices. 1701 */ 1702 mtx_lock_spin(&sio_lock); 1703 incc = com->iptr - com->ibuf; 1704 com->iptr = com->ibuf; 1705 if (com->state & CS_CHECKMSR) { 1706 incc += LOTS_OF_EVENTS; 1707 com->state &= ~CS_CHECKMSR; 1708 } 1709 com_events -= incc; 1710 mtx_unlock_spin(&sio_lock); 1711 continue; 1712 } 1713 if (com->iptr != com->ibuf) { 1714 mtx_lock_spin(&sio_lock); 1715 sioinput(com); 1716 mtx_unlock_spin(&sio_lock); 1717 } 1718 if (com->state & CS_CHECKMSR) { 1719 u_char delta_modem_status; 1720 1721 mtx_lock_spin(&sio_lock); 1722 delta_modem_status = com->last_modem_status 1723 ^ com->prev_modem_status; 1724 com->prev_modem_status = com->last_modem_status; 1725 com_events -= LOTS_OF_EVENTS; 1726 com->state &= ~CS_CHECKMSR; 1727 mtx_unlock_spin(&sio_lock); 1728 if (delta_modem_status & MSR_DCD) 1729 ttyld_modem(tp, 1730 com->prev_modem_status & MSR_DCD); 1731 } 1732 if (com->state & CS_ODONE) { 1733 mtx_lock_spin(&sio_lock); 1734 com_events -= LOTS_OF_EVENTS; 1735 com->state &= ~CS_ODONE; 1736 mtx_unlock_spin(&sio_lock); 1737 if (!(com->state & CS_BUSY) 1738 && !(com->extra_state & CSE_BUSYCHECK)) { 1739 timeout(siobusycheck, com, hz / 100); 1740 com->extra_state |= CSE_BUSYCHECK; 1741 } 1742 ttyld_start(tp); 1743 } 1744 if (com_events == 0) 1745 break; 1746 } 1747 if (com_events >= LOTS_OF_EVENTS) 1748 goto repeat; 1749} 1750 1751static void 1752combreak(tp, sig) 1753 struct tty *tp; 1754 int sig; 1755{ 1756 struct com_s *com; 1757 1758 com = tp->t_sc; 1759 1760 if (sig) 1761 sio_setreg(com, com_cfcr, com->cfcr_image |= CFCR_SBREAK); 1762 else 1763 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 1764} 1765 1766static int 1767comparam(tp, t) 1768 struct tty *tp; 1769 struct termios *t; 1770{ 1771 u_int cfcr; 1772 int cflag; 1773 struct com_s *com; 1774 u_int divisor; 1775 u_char dlbh; 1776 u_char dlbl; 1777 u_char efr_flowbits; 1778 int s; 1779 1780 com = tp->t_sc; 1781 if (com == NULL) 1782 return (ENODEV); 1783 1784 /* check requested parameters */ 1785 if (t->c_ispeed != (t->c_ospeed != 0 ? t->c_ospeed : tp->t_ospeed)) 1786 return (EINVAL); 1787 divisor = siodivisor(com->rclk, t->c_ispeed); 1788 if (divisor == 0) 1789 return (EINVAL); 1790 1791 /* parameters are OK, convert them to the com struct and the device */ 1792 s = spltty(); 1793 if (t->c_ospeed == 0) 1794 (void)commodem(tp, 0, SER_DTR); /* hang up line */ 1795 else 1796 (void)commodem(tp, SER_DTR, 0); 1797 cflag = t->c_cflag; 1798 switch (cflag & CSIZE) { 1799 case CS5: 1800 cfcr = CFCR_5BITS; 1801 break; 1802 case CS6: 1803 cfcr = CFCR_6BITS; 1804 break; 1805 case CS7: 1806 cfcr = CFCR_7BITS; 1807 break; 1808 default: 1809 cfcr = CFCR_8BITS; 1810 break; 1811 } 1812 if (cflag & PARENB) { 1813 cfcr |= CFCR_PENAB; 1814 if (!(cflag & PARODD)) 1815 cfcr |= CFCR_PEVEN; 1816 } 1817 if (cflag & CSTOPB) 1818 cfcr |= CFCR_STOPB; 1819 1820 if (com->hasfifo) { 1821 /* 1822 * Use a fifo trigger level low enough so that the input 1823 * latency from the fifo is less than about 16 msec and 1824 * the total latency is less than about 30 msec. These 1825 * latencies are reasonable for humans. Serial comms 1826 * protocols shouldn't expect anything better since modem 1827 * latencies are larger. 1828 * 1829 * The fifo trigger level cannot be set at RX_HIGH for high 1830 * speed connections without further work on reducing 1831 * interrupt disablement times in other parts of the system, 1832 * without producing silo overflow errors. 1833 */ 1834 com->fifo_image = com->unit == siotsunit ? 0 1835 : t->c_ispeed <= 4800 1836 ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_MEDH; 1837#ifdef COM_ESP 1838 /* 1839 * The Hayes ESP card needs the fifo DMA mode bit set 1840 * in compatibility mode. If not, it will interrupt 1841 * for each character received. 1842 */ 1843 if (com->esp) 1844 com->fifo_image |= FIFO_DMA_MODE; 1845#endif 1846 sio_setreg(com, com_fifo, com->fifo_image); 1847 } 1848 1849 /* 1850 * This returns with interrupts disabled so that we can complete 1851 * the speed change atomically. Keeping interrupts disabled is 1852 * especially important while com_data is hidden. 1853 */ 1854 (void) siosetwater(com, t->c_ispeed); 1855 1856 sio_setreg(com, com_cfcr, cfcr | CFCR_DLAB); 1857 /* 1858 * Only set the divisor registers if they would change, since on 1859 * some 16550 incompatibles (UMC8669F), setting them while input 1860 * is arriving loses sync until data stops arriving. 1861 */ 1862 dlbl = divisor & 0xFF; 1863 if (sio_getreg(com, com_dlbl) != dlbl) 1864 sio_setreg(com, com_dlbl, dlbl); 1865 dlbh = divisor >> 8; 1866 if (sio_getreg(com, com_dlbh) != dlbh) 1867 sio_setreg(com, com_dlbh, dlbh); 1868 1869 efr_flowbits = 0; 1870 1871 if (cflag & CRTS_IFLOW) { 1872 com->state |= CS_RTS_IFLOW; 1873 efr_flowbits |= EFR_AUTORTS; 1874 /* 1875 * If CS_RTS_IFLOW just changed from off to on, the change 1876 * needs to be propagated to MCR_RTS. This isn't urgent, 1877 * so do it later by calling comstart() instead of repeating 1878 * a lot of code from comstart() here. 1879 */ 1880 } else if (com->state & CS_RTS_IFLOW) { 1881 com->state &= ~CS_RTS_IFLOW; 1882 /* 1883 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS 1884 * on here, since comstart() won't do it later. 1885 */ 1886 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 1887 } 1888 1889 /* 1890 * Set up state to handle output flow control. 1891 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level? 1892 * Now has 10+ msec latency, while CTS flow has 50- usec latency. 1893 */ 1894 com->state |= CS_ODEVREADY; 1895 com->state &= ~CS_CTS_OFLOW; 1896 if (cflag & CCTS_OFLOW) { 1897 com->state |= CS_CTS_OFLOW; 1898 efr_flowbits |= EFR_AUTOCTS; 1899 if (!(com->last_modem_status & MSR_CTS)) 1900 com->state &= ~CS_ODEVREADY; 1901 } 1902 1903 if (com->st16650a) { 1904 sio_setreg(com, com_lcr, LCR_EFR_ENABLE); 1905 sio_setreg(com, com_efr, 1906 (sio_getreg(com, com_efr) 1907 & ~(EFR_AUTOCTS | EFR_AUTORTS)) | efr_flowbits); 1908 } 1909 sio_setreg(com, com_cfcr, com->cfcr_image = cfcr); 1910 1911 /* XXX shouldn't call functions while intrs are disabled. */ 1912 ttyldoptim(tp); 1913 1914 mtx_unlock_spin(&sio_lock); 1915 splx(s); 1916 comstart(tp); 1917 if (com->ibufold != NULL) { 1918 free(com->ibufold, M_DEVBUF); 1919 com->ibufold = NULL; 1920 } 1921 return (0); 1922} 1923 1924/* 1925 * This function must be called with the sio_lock mutex released and will 1926 * return with it obtained. 1927 */ 1928static int 1929siosetwater(com, speed) 1930 struct com_s *com; 1931 speed_t speed; 1932{ 1933 int cp4ticks; 1934 u_char *ibuf; 1935 int ibufsize; 1936 struct tty *tp; 1937 1938 /* 1939 * Make the buffer size large enough to handle a softtty interrupt 1940 * latency of about 2 ticks without loss of throughput or data 1941 * (about 3 ticks if input flow control is not used or not honoured, 1942 * but a bit less for CS5-CS7 modes). 1943 */ 1944 cp4ticks = speed / 10 / hz * 4; 1945 for (ibufsize = 128; ibufsize < cp4ticks;) 1946 ibufsize <<= 1; 1947 if (ibufsize == com->ibufsize) { 1948 mtx_lock_spin(&sio_lock); 1949 return (0); 1950 } 1951 1952 /* 1953 * Allocate input buffer. The extra factor of 2 in the size is 1954 * to allow for an error byte for each input byte. 1955 */ 1956 ibuf = malloc(2 * ibufsize, M_DEVBUF, M_NOWAIT); 1957 if (ibuf == NULL) { 1958 mtx_lock_spin(&sio_lock); 1959 return (ENOMEM); 1960 } 1961 1962 /* Initialize non-critical variables. */ 1963 com->ibufold = com->ibuf; 1964 com->ibufsize = ibufsize; 1965 tp = com->tp; 1966 if (tp != NULL) { 1967 tp->t_ififosize = 2 * ibufsize; 1968 tp->t_ispeedwat = (speed_t)-1; 1969 tp->t_ospeedwat = (speed_t)-1; 1970 } 1971 1972 /* 1973 * Read current input buffer, if any. Continue with interrupts 1974 * disabled. 1975 */ 1976 mtx_lock_spin(&sio_lock); 1977 if (com->iptr != com->ibuf) 1978 sioinput(com); 1979 1980 /*- 1981 * Initialize critical variables, including input buffer watermarks. 1982 * The external device is asked to stop sending when the buffer 1983 * exactly reaches high water, or when the high level requests it. 1984 * The high level is notified immediately (rather than at a later 1985 * clock tick) when this watermark is reached. 1986 * The buffer size is chosen so the watermark should almost never 1987 * be reached. 1988 * The low watermark is invisibly 0 since the buffer is always 1989 * emptied all at once. 1990 */ 1991 com->iptr = com->ibuf = ibuf; 1992 com->ibufend = ibuf + ibufsize; 1993 com->ierroff = ibufsize; 1994 com->ihighwater = ibuf + 3 * ibufsize / 4; 1995 return (0); 1996} 1997 1998static void 1999comstart(tp) 2000 struct tty *tp; 2001{ 2002 struct com_s *com; 2003 int s; 2004 2005 com = tp->t_sc; 2006 if (com == NULL) 2007 return; 2008 s = spltty(); 2009 mtx_lock_spin(&sio_lock); 2010 if (tp->t_state & TS_TTSTOP) 2011 com->state &= ~CS_TTGO; 2012 else 2013 com->state |= CS_TTGO; 2014 if (tp->t_state & TS_TBLOCK) { 2015 if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW) 2016 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS); 2017 } else { 2018 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater 2019 && com->state & CS_RTS_IFLOW) 2020 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2021 } 2022 mtx_unlock_spin(&sio_lock); 2023 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) { 2024 ttwwakeup(tp); 2025 splx(s); 2026 return; 2027 } 2028 if (tp->t_outq.c_cc != 0) { 2029 struct lbq *qp; 2030 struct lbq *next; 2031 2032 if (!com->obufs[0].l_queued) { 2033 com->obufs[0].l_tail 2034 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1, 2035 sizeof com->obuf1); 2036 com->obufs[0].l_next = NULL; 2037 com->obufs[0].l_queued = TRUE; 2038 mtx_lock_spin(&sio_lock); 2039 if (com->state & CS_BUSY) { 2040 qp = com->obufq.l_next; 2041 while ((next = qp->l_next) != NULL) 2042 qp = next; 2043 qp->l_next = &com->obufs[0]; 2044 } else { 2045 com->obufq.l_head = com->obufs[0].l_head; 2046 com->obufq.l_tail = com->obufs[0].l_tail; 2047 com->obufq.l_next = &com->obufs[0]; 2048 com->state |= CS_BUSY; 2049 } 2050 mtx_unlock_spin(&sio_lock); 2051 } 2052 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) { 2053 com->obufs[1].l_tail 2054 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2, 2055 sizeof com->obuf2); 2056 com->obufs[1].l_next = NULL; 2057 com->obufs[1].l_queued = TRUE; 2058 mtx_lock_spin(&sio_lock); 2059 if (com->state & CS_BUSY) { 2060 qp = com->obufq.l_next; 2061 while ((next = qp->l_next) != NULL) 2062 qp = next; 2063 qp->l_next = &com->obufs[1]; 2064 } else { 2065 com->obufq.l_head = com->obufs[1].l_head; 2066 com->obufq.l_tail = com->obufs[1].l_tail; 2067 com->obufq.l_next = &com->obufs[1]; 2068 com->state |= CS_BUSY; 2069 } 2070 mtx_unlock_spin(&sio_lock); 2071 } 2072 tp->t_state |= TS_BUSY; 2073 } 2074 mtx_lock_spin(&sio_lock); 2075 if (com->state >= (CS_BUSY | CS_TTGO)) 2076 siointr1(com); /* fake interrupt to start output */ 2077 mtx_unlock_spin(&sio_lock); 2078 ttwwakeup(tp); 2079 splx(s); 2080} 2081 2082static void 2083comstop(tp, rw) 2084 struct tty *tp; 2085 int rw; 2086{ 2087 struct com_s *com; 2088 2089 com = tp->t_sc; 2090 if (com == NULL || com->gone) 2091 return; 2092 mtx_lock_spin(&sio_lock); 2093 if (rw & FWRITE) { 2094 if (com->hasfifo) 2095#ifdef COM_ESP 2096 /* XXX avoid h/w bug. */ 2097 if (!com->esp) 2098#endif 2099 sio_setreg(com, com_fifo, 2100 FIFO_XMT_RST | com->fifo_image); 2101 com->obufs[0].l_queued = FALSE; 2102 com->obufs[1].l_queued = FALSE; 2103 if (com->state & CS_ODONE) 2104 com_events -= LOTS_OF_EVENTS; 2105 com->state &= ~(CS_ODONE | CS_BUSY); 2106 com->tp->t_state &= ~TS_BUSY; 2107 } 2108 if (rw & FREAD) { 2109 if (com->hasfifo) 2110#ifdef COM_ESP 2111 /* XXX avoid h/w bug. */ 2112 if (!com->esp) 2113#endif 2114 sio_setreg(com, com_fifo, 2115 FIFO_RCV_RST | com->fifo_image); 2116 com_events -= (com->iptr - com->ibuf); 2117 com->iptr = com->ibuf; 2118 } 2119 mtx_unlock_spin(&sio_lock); 2120 comstart(tp); 2121} 2122 2123static int 2124commodem(struct tty *tp, int sigon, int sigoff) 2125{ 2126 struct com_s *com; 2127 int bitand, bitor, msr; 2128 2129 com = tp->t_sc; 2130 if (com->gone) 2131 return(0); 2132 if (sigon != 0 || sigoff != 0) { 2133 bitand = bitor = 0; 2134 if (sigoff & SER_DTR) 2135 bitand |= MCR_DTR; 2136 if (sigoff & SER_RTS) 2137 bitand |= MCR_RTS; 2138 if (sigon & SER_DTR) 2139 bitor |= MCR_DTR; 2140 if (sigon & SER_RTS) 2141 bitor |= MCR_RTS; 2142 bitand = ~bitand; 2143 mtx_lock_spin(&sio_lock); 2144 com->mcr_image &= bitand; 2145 com->mcr_image |= bitor; 2146 outb(com->modem_ctl_port, com->mcr_image); 2147 mtx_unlock_spin(&sio_lock); 2148 return (0); 2149 } else { 2150 bitor = 0; 2151 if (com->mcr_image & MCR_DTR) 2152 bitor |= SER_DTR; 2153 if (com->mcr_image & MCR_RTS) 2154 bitor |= SER_RTS; 2155 msr = com->prev_modem_status; 2156 if (msr & MSR_CTS) 2157 bitor |= SER_CTS; 2158 if (msr & MSR_DCD) 2159 bitor |= SER_DCD; 2160 if (msr & MSR_DSR) 2161 bitor |= SER_DSR; 2162 if (msr & MSR_DSR) 2163 bitor |= SER_DSR; 2164 if (msr & (MSR_RI | MSR_TERI)) 2165 bitor |= SER_RI; 2166 return (bitor); 2167 } 2168} 2169 2170static void 2171siosettimeout() 2172{ 2173 struct com_s *com; 2174 bool_t someopen; 2175 int unit; 2176 2177 /* 2178 * Set our timeout period to 1 second if no polled devices are open. 2179 * Otherwise set it to max(1/200, 1/hz). 2180 * Enable timeouts iff some device is open. 2181 */ 2182 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 2183 sio_timeout = hz; 2184 someopen = FALSE; 2185 for (unit = 0; unit < sio_numunits; ++unit) { 2186 com = com_addr(unit); 2187 if (com != NULL && com->tp != NULL 2188 && com->tp->t_state & TS_ISOPEN && !com->gone) { 2189 someopen = TRUE; 2190 if (com->poll || com->poll_output) { 2191 sio_timeout = hz > 200 ? hz / 200 : 1; 2192 break; 2193 } 2194 } 2195 } 2196 if (someopen) { 2197 sio_timeouts_until_log = hz / sio_timeout; 2198 sio_timeout_handle = timeout(comwakeup, (void *)NULL, 2199 sio_timeout); 2200 } else { 2201 /* Flush error messages, if any. */ 2202 sio_timeouts_until_log = 1; 2203 comwakeup((void *)NULL); 2204 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 2205 } 2206} 2207 2208static void 2209comwakeup(chan) 2210 void *chan; 2211{ 2212 struct com_s *com; 2213 int unit; 2214 2215 sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout); 2216 2217 /* 2218 * Recover from lost output interrupts. 2219 * Poll any lines that don't use interrupts. 2220 */ 2221 for (unit = 0; unit < sio_numunits; ++unit) { 2222 com = com_addr(unit); 2223 if (com != NULL && !com->gone 2224 && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) { 2225 mtx_lock_spin(&sio_lock); 2226 siointr1(com); 2227 mtx_unlock_spin(&sio_lock); 2228 } 2229 } 2230 2231 /* 2232 * Check for and log errors, but not too often. 2233 */ 2234 if (--sio_timeouts_until_log > 0) 2235 return; 2236 sio_timeouts_until_log = hz / sio_timeout; 2237 for (unit = 0; unit < sio_numunits; ++unit) { 2238 int errnum; 2239 2240 com = com_addr(unit); 2241 if (com == NULL) 2242 continue; 2243 if (com->gone) 2244 continue; 2245 for (errnum = 0; errnum < CE_NTYPES; ++errnum) { 2246 u_int delta; 2247 u_long total; 2248 2249 mtx_lock_spin(&sio_lock); 2250 delta = com->delta_error_counts[errnum]; 2251 com->delta_error_counts[errnum] = 0; 2252 mtx_unlock_spin(&sio_lock); 2253 if (delta == 0) 2254 continue; 2255 total = com->error_counts[errnum] += delta; 2256 log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n", 2257 unit, delta, error_desc[errnum], 2258 delta == 1 ? "" : "s", total); 2259 } 2260 } 2261} 2262 2263/* 2264 * Following are all routines needed for SIO to act as console 2265 */ 2266struct siocnstate { 2267 u_char dlbl; 2268 u_char dlbh; 2269 u_char ier; 2270 u_char cfcr; 2271 u_char mcr; 2272}; 2273 2274/* 2275 * This is a function in order to not replicate "ttyd%d" more 2276 * places than absolutely necessary. 2277 */ 2278static void 2279siocnset(struct consdev *cd, int unit) 2280{ 2281 2282 cd->cn_unit = unit; 2283 sprintf(cd->cn_name, "ttyd%d", unit); 2284} 2285 2286static speed_t siocngetspeed(Port_t, u_long rclk); 2287static void siocnclose(struct siocnstate *sp, Port_t iobase); 2288static void siocnopen(struct siocnstate *sp, Port_t iobase, int speed); 2289static void siocntxwait(Port_t iobase); 2290 2291static cn_probe_t sio_cnprobe; 2292static cn_init_t sio_cninit; 2293static cn_term_t sio_cnterm; 2294static cn_getc_t sio_cngetc; 2295static cn_putc_t sio_cnputc; 2296static cn_grab_t sio_cngrab; 2297static cn_ungrab_t sio_cnungrab; 2298 2299CONSOLE_DRIVER(sio); 2300 2301static void 2302siocntxwait(iobase) 2303 Port_t iobase; 2304{ 2305 int timo; 2306 2307 /* 2308 * Wait for any pending transmission to finish. Required to avoid 2309 * the UART lockup bug when the speed is changed, and for normal 2310 * transmits. 2311 */ 2312 timo = 100000; 2313 while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY)) 2314 != (LSR_TSRE | LSR_TXRDY) && --timo != 0) 2315 ; 2316} 2317 2318/* 2319 * Read the serial port specified and try to figure out what speed 2320 * it's currently running at. We're assuming the serial port has 2321 * been initialized and is basicly idle. This routine is only intended 2322 * to be run at system startup. 2323 * 2324 * If the value read from the serial port doesn't make sense, return 0. 2325 */ 2326 2327static speed_t 2328siocngetspeed(iobase, rclk) 2329 Port_t iobase; 2330 u_long rclk; 2331{ 2332 u_int divisor; 2333 u_char dlbh; 2334 u_char dlbl; 2335 u_char cfcr; 2336 2337 cfcr = inb(iobase + com_cfcr); 2338 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 2339 2340 dlbl = inb(iobase + com_dlbl); 2341 dlbh = inb(iobase + com_dlbh); 2342 2343 outb(iobase + com_cfcr, cfcr); 2344 2345 divisor = dlbh << 8 | dlbl; 2346 2347 /* XXX there should be more sanity checking. */ 2348 if (divisor == 0) 2349 return (CONSPEED); 2350 return (rclk / (16UL * divisor)); 2351} 2352 2353static void 2354siocnopen(sp, iobase, speed) 2355 struct siocnstate *sp; 2356 Port_t iobase; 2357 int speed; 2358{ 2359 u_int divisor; 2360 u_char dlbh; 2361 u_char dlbl; 2362 2363 /* 2364 * Save all the device control registers except the fifo register 2365 * and set our default ones (cs8 -parenb speed=comdefaultrate). 2366 * We can't save the fifo register since it is read-only. 2367 */ 2368 sp->ier = inb(iobase + com_ier); 2369 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */ 2370 siocntxwait(iobase); 2371 sp->cfcr = inb(iobase + com_cfcr); 2372 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 2373 sp->dlbl = inb(iobase + com_dlbl); 2374 sp->dlbh = inb(iobase + com_dlbh); 2375 /* 2376 * Only set the divisor registers if they would change, since on 2377 * some 16550 incompatibles (Startech), setting them clears the 2378 * data input register. This also reduces the effects of the 2379 * UMC8669F bug. 2380 */ 2381 divisor = siodivisor(comdefaultrclk, speed); 2382 dlbl = divisor & 0xFF; 2383 if (sp->dlbl != dlbl) 2384 outb(iobase + com_dlbl, dlbl); 2385 dlbh = divisor >> 8; 2386 if (sp->dlbh != dlbh) 2387 outb(iobase + com_dlbh, dlbh); 2388 outb(iobase + com_cfcr, CFCR_8BITS); 2389 sp->mcr = inb(iobase + com_mcr); 2390 /* 2391 * We don't want interrupts, but must be careful not to "disable" 2392 * them by clearing the MCR_IENABLE bit, since that might cause 2393 * an interrupt by floating the IRQ line. 2394 */ 2395 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS); 2396} 2397 2398static void 2399siocnclose(sp, iobase) 2400 struct siocnstate *sp; 2401 Port_t iobase; 2402{ 2403 /* 2404 * Restore the device control registers. 2405 */ 2406 siocntxwait(iobase); 2407 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 2408 if (sp->dlbl != inb(iobase + com_dlbl)) 2409 outb(iobase + com_dlbl, sp->dlbl); 2410 if (sp->dlbh != inb(iobase + com_dlbh)) 2411 outb(iobase + com_dlbh, sp->dlbh); 2412 outb(iobase + com_cfcr, sp->cfcr); 2413 /* 2414 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them. 2415 */ 2416 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS); 2417 outb(iobase + com_ier, sp->ier); 2418} 2419 2420static void 2421sio_cnprobe(cp) 2422 struct consdev *cp; 2423{ 2424 speed_t boot_speed; 2425 u_char cfcr; 2426 u_int divisor; 2427 int s, unit; 2428 struct siocnstate sp; 2429 2430 /* 2431 * Find our first enabled console, if any. If it is a high-level 2432 * console device, then initialize it and return successfully. 2433 * If it is a low-level console device, then initialize it and 2434 * return unsuccessfully. It must be initialized in both cases 2435 * for early use by console drivers and debuggers. Initializing 2436 * the hardware is not necessary in all cases, since the i/o 2437 * routines initialize it on the fly, but it is necessary if 2438 * input might arrive while the hardware is switched back to an 2439 * uninitialized state. We can't handle multiple console devices 2440 * yet because our low-level routines don't take a device arg. 2441 * We trust the user to set the console flags properly so that we 2442 * don't need to probe. 2443 */ 2444 cp->cn_pri = CN_DEAD; 2445 2446 for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */ 2447 int flags; 2448 2449 if (resource_disabled("sio", unit)) 2450 continue; 2451 if (resource_int_value("sio", unit, "flags", &flags)) 2452 continue; 2453 if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) { 2454 int port; 2455 Port_t iobase; 2456 2457 if (resource_int_value("sio", unit, "port", &port)) 2458 continue; 2459 iobase = port; 2460 s = spltty(); 2461 if ((boothowto & RB_SERIAL) && COM_CONSOLE(flags)) { 2462 boot_speed = 2463 siocngetspeed(iobase, comdefaultrclk); 2464 if (boot_speed) 2465 comdefaultrate = boot_speed; 2466 } 2467 2468 /* 2469 * Initialize the divisor latch. We can't rely on 2470 * siocnopen() to do this the first time, since it 2471 * avoids writing to the latch if the latch appears 2472 * to have the correct value. Also, if we didn't 2473 * just read the speed from the hardware, then we 2474 * need to set the speed in hardware so that 2475 * switching it later is null. 2476 */ 2477 cfcr = inb(iobase + com_cfcr); 2478 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 2479 divisor = siodivisor(comdefaultrclk, comdefaultrate); 2480 outb(iobase + com_dlbl, divisor & 0xff); 2481 outb(iobase + com_dlbh, divisor >> 8); 2482 outb(iobase + com_cfcr, cfcr); 2483 2484 siocnopen(&sp, iobase, comdefaultrate); 2485 2486 splx(s); 2487 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) { 2488 siocnset(cp, unit); 2489 cp->cn_pri = COM_FORCECONSOLE(flags) 2490 || boothowto & RB_SERIAL 2491 ? CN_REMOTE : CN_NORMAL; 2492 siocniobase = iobase; 2493 siocnunit = unit; 2494 } 2495#ifdef GDB 2496 if (COM_DEBUGGER(flags)) 2497 siogdbiobase = iobase; 2498#endif 2499 } 2500 } 2501} 2502 2503static void 2504sio_cninit(cp) 2505 struct consdev *cp; 2506{ 2507 comconsole = cp->cn_unit; 2508} 2509 2510static void 2511sio_cnterm(cp) 2512 struct consdev *cp; 2513{ 2514 comconsole = -1; 2515} 2516 2517static void 2518sio_cngrab(struct consdev *cp) 2519{ 2520} 2521 2522static void 2523sio_cnungrab(struct consdev *cp) 2524{ 2525} 2526 2527static int 2528sio_cngetc(struct consdev *cd) 2529{ 2530 int c; 2531 Port_t iobase; 2532 int s; 2533 struct siocnstate sp; 2534 speed_t speed; 2535 2536 if (cd != NULL && cd->cn_unit == siocnunit) { 2537 iobase = siocniobase; 2538 speed = comdefaultrate; 2539 } else { 2540#ifdef GDB 2541 iobase = siogdbiobase; 2542 speed = gdbdefaultrate; 2543#else 2544 return (-1); 2545#endif 2546 } 2547 s = spltty(); 2548 siocnopen(&sp, iobase, speed); 2549 if (inb(iobase + com_lsr) & LSR_RXRDY) 2550 c = inb(iobase + com_data); 2551 else 2552 c = -1; 2553 siocnclose(&sp, iobase); 2554 splx(s); 2555 return (c); 2556} 2557 2558static void 2559sio_cnputc(struct consdev *cd, int c) 2560{ 2561 int need_unlock; 2562 int s; 2563 struct siocnstate sp; 2564 Port_t iobase; 2565 speed_t speed; 2566 2567 if (cd != NULL && cd->cn_unit == siocnunit) { 2568 iobase = siocniobase; 2569 speed = comdefaultrate; 2570 } else { 2571#ifdef GDB 2572 iobase = siogdbiobase; 2573 speed = gdbdefaultrate; 2574#else 2575 return; 2576#endif 2577 } 2578 s = spltty(); 2579 need_unlock = 0; 2580 if (!kdb_active && sio_inited == 2 && !mtx_owned(&sio_lock)) { 2581 mtx_lock_spin(&sio_lock); 2582 need_unlock = 1; 2583 } 2584 siocnopen(&sp, iobase, speed); 2585 siocntxwait(iobase); 2586 outb(iobase + com_data, c); 2587 siocnclose(&sp, iobase); 2588 if (need_unlock) 2589 mtx_unlock_spin(&sio_lock); 2590 splx(s); 2591} 2592 2593/* 2594 * Remote gdb(1) support. 2595 */ 2596 2597#if defined(GDB) 2598 2599#include <gdb/gdb.h> 2600 2601static gdb_probe_f siogdbprobe; 2602static gdb_init_f siogdbinit; 2603static gdb_term_f siogdbterm; 2604static gdb_getc_f siogdbgetc; 2605static gdb_putc_f siogdbputc; 2606 2607GDB_DBGPORT(sio, siogdbprobe, siogdbinit, siogdbterm, siogdbgetc, siogdbputc); 2608 2609static int 2610siogdbprobe(void) 2611{ 2612 return ((siogdbiobase != 0) ? 0 : -1); 2613} 2614 2615static void 2616siogdbinit(void) 2617{ 2618} 2619 2620static void 2621siogdbterm(void) 2622{ 2623} 2624 2625static void 2626siogdbputc(int c) 2627{ 2628 sio_cnputc(NULL, c); 2629} 2630 2631static int 2632siogdbgetc(void) 2633{ 2634 return (sio_cngetc(NULL)); 2635} 2636 2637#endif 2638